[Joey-Magnus]

Two of OoT's compute programs fail to translate ("does not lower ... native global load uniform addressing mode"), so their dispatches do nothing on every PC. Both load from a uniform-register address with memory-ordering bit 78 set beside bit 77, and the lowering only allowed 77.

The encodings (startup pipeline build, Linux; also in a Radeon 890M v2.0.13 log from #bug-reporting):

a7a54ff1af0cfa19 +0x10   LDG  ff017981 00002c04 0c1ee900 000ea800   LDG.E R1, [UR4+0x2c], 32 bits
a09bdc185d560567 +0x80   LDG  ff087981 00002004 0c1eed00 000ea200   LDG.E R8, [UR4+0x20], 128 bits
a09bdc185d560567 +0x720  STG  ff000986 00003007 0c10e906 000fee00   STG.E [UR6+0x30], R7, 32 bits

These are the uniform-address forms the lowering already handles (0x081e8100 for LDG, 0x0810a100 for STG, bit 79 set, bit 76 clear). The only extra is bit 78. Bit 77, in the same ordering field, is already ignored ("needs nothing extra from a Maxwell LDG"), because Maxwell's LDG/STG have no ordering qualifier. The second program got past its load and then stopped at the store, so the store is included here.

Change (lower_to_maxwell.h): bit 78 is allowed beside 77 in the uniform-address LDG (0x981) and STG (0x986). They lower to Maxwell LDG.E / STG.E of the uniform register pair plus the offset, as before. Bit 76 and other unknown bits in the uniform form stay refused, as do odd uniform registers.

Tests

• New tests/test_lower_ldg_uniform_order.py (in run_all.py): the three encodings lower to LDG.E / STG.E with the right destination or data, offset, size, .E and an aligned address pair; bit 77 alone or neither lower as before; bit 76 is refused. It fails on main and passes here.
• run_all.py: 246 passed, 0 failed.
• In game (Linux, RTX 4070 Ti, 595.99.02), stacked on fix(shaders): lower TLD.MS (multisampled texel fetch) to Maxwell TLDS 2D.LZ.MS #1769: programs that do not lower go 7 → 5 (both gone), and the build's failed-program count 19 → 17.

Ordering note: lowering a strong load or store to a plain one could matter only across workgroups, for example a spin on a flag another workgroup writes. I haven't disassembled these two programs to rule that out. Reviewers who know these passes may want to check. The register form has accepted bit 77 the same way.

🤖 Generated with Claude Code

[Joey-Magnus]

Thanks, agreed. Bits 77-79 all set read as .STRONG.GPU next to the RED/ATOMG encodings. Done in the new commit: with bit 78, the LDG.E and the STG.E are each fenced by MEMBAR.GL (0xef98000000000000 | predicate | 1 << 8) before and after, mirroring SUST.STRONG.GPU at 0xb9b. The test checks two fences around each of the log's strong accesses, and none for bit 77 alone or neither. I also removed the ordering caveat from the description. Rebased onto main's new run_all.py (RUN_ALL_ARGS in the test); run_all.py: 263 passed, 0 failed.

[Joey-Magnus]

Correction to my last comment: I didn't rebase this one. I saw your merge of main into the branch, so I kept it, merged the current main on top (the new run_all.py, with RUN_ALL_ARGS in the test), and added the MEMBAR commit. Plain push, no force.