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Fix CI ccache SIGILL by building Linux for x86-64-v3 - #272
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- Pass -DSIMD_CXX_FLAGS=-march=x86-64-v3 in the Linux continuous and CUDA jobs so ccache's flag hash describes the generated code - Key those caches on x86-64-v3 instead of the CPU, so one cache serves every runner - Fail early if a runner lacks an x86-64-v3 feature - Keep coverage on -march=native so CI still compiles the default path Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
2 of 10 tasks
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
- Skip find_package(SIMD) when SIMD_CXX_FLAGS is already set - Fail with an error if the compiler rejects the flags, instead of silently falling back to a build without SIMD - Add ipc_toolkit_check_cxx_flags() to test a flag list as a whole Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #272 +/- ##
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- Coverage 96.92% 96.92% -0.01%
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Files 194 194
Lines 17348 17349 +1
Branches 944 943 -1
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Hits 16815 16815
- Misses 533 534 +1
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Description
Builds the Linux CI jobs for
x86-64-v3instead of-march=native, so one ccache serves every runner CPU. Also fixes CI comments that named MeshFEMCore as a source of-march=native.continuous.yml,cuda.yml,python.yml, andcoverage.yml(Linux) pass-DSIMD_CXX_FLAGS=-march=x86-64-v3(AVX2, FMA, BMI1/2, LZCNT, F16C). The flag string ccache hashes now fully describes the generated code.continuous,cuda,python, andcoveragecache keys have no CPU component on any OS, so one cache per OS and config serves every runner CPU (for example<os>-<config>-cache, with acuda-prefix for CUDA). The CPU fingerprint steps are gone, apart from a CPU log line in the Linux guard.pypi.ymlpassesCMAKE_ARGS=-DSIMD_CXX_FLAGS=-march=x86-64-v3throughCIBW_ENVIRONMENT_LINUX. Without it, wheels take-march=nativefrom the runner that built them. The 1.6.0 Linux wheels contain no AVX-512 but already need AVX2, FMA, BMI and LZCNT. macOS and Windows wheels are unchanged.docs.ymlgets its ccache back (reverting Fix docs SIGILL by dropping ccache from the docs build #270's removal) with the same x86-64-v3 baseline throughCMAKE_ARGSand the same guard. It uses a new key,docs-ccache, because entries are immutable and the olddocs-cacheholds-march=nativeobjects.-g: the Debug configures incontinuous.yml(Linux and macOS) andcuda.ymlpass-DCMAKE_C_FLAGS_DEBUG=-O0 -DCMAKE_CXX_FLAGS_DEBUG=-O0, so asserts stay on (NDEBUGundefined) but debug info is gone. In the first Fix CI ccache SIGILL by keying on the resolved ISA #269 run the Debug ccache was 0.41 GB against 0.02 GB for Release on Linux, and 0.53 GB against 0.14 GB on CUDA. The CUDA job emptiesCMAKE_CUDA_FLAGS_DEBUGinstead, because nvcc would apply-O0to device code. Windows is unchanged, since MSVC's Debug flags differ.SIMD_CXX_FLAGSis already set,CMakeLists.txtskipsfind_package(SIMD)and only checks that the compiler accepts the flags, through the newipc_toolkit_check_cxx_flags()inipc_toolkit_filter_flags.cmake. Rejected flags are aFATAL_ERRORinstead of a silent fallback to a non-SIMD build, so a typo can't pass as a working build. Auto-detection is unchanged when the flags are not set.coverage.ymlgets the same baseline, guard, and plaincoverage-cachekey. Its stray trailing backslashes are gone.meshfem_sparse.cmakeusesDOWNLOAD_ONLY.python.ymlno longer setsIPCTK_WITH_SIMD=0on Linux (added in Add env var to disable SIMD in setup.py #231 with no stated reason). It builds with SIMD and the same x86-64-v3 pin and guard, so the Linux Python tests now exercise the SIMD code through the bindings.Impact:
The first run after merge is cold on every OS, because every key changes. After that the cache is shared across CPUs. Only 16 of 40 recent Linux jobs restored a cache, because keys were split across six CPU models.
No Linux CI job compiles the
-march=nativedefault or the AVX-512xsimdpath (batch width 8 instead of 4) any more. Users on AVX-512 hardware run code CI no longer builds.No source or API changes.
Windows already passes explicit
/arch:AVX2, so its objects do not depend on the runner.macOS still builds with
-march=native. It shares one cache because 27 of 29 recent macOS jobs ran on the same Apple M1. A cache seeded by an M2 Pro runner could in principle reach M1 runners.Why
-march=nativeliterally. On an Ice Lake runner it expands to-march=icelake-server -mavx512f …, and the cached objects are only safe on a runner with the same ISA.-march=native -mavx2 -mno-avx512f …, which caps its objects at AVX2. I left them as they are. A switch there would make them strictly deterministic.-DSIMD_CXX_FLAGS=-march=x86-64-v3, all 94ipc_toolkittranslation units compile with it and none with-march=native.Type of change
How Has This Been Tested?
runblock passesbash -n./proc/cpuinfofiles: it passes on a v3-capable CPU and fails with a clear message whenbmi2,fma, oravx2is missing.-DSIMD_CXX_FLAGS=-march=x86-64-v3and checkedcompile_commands.json(see above). Configure only, no build.pypi.ymlonly runs onworkflow_dispatch, and I haven't checked that cibuildwheel passesCMAKE_ARGSinto the manylinux container.-march=x86-64-v3through-Xcompiler. CI on this PR is the test, since each workflow triggers on its own file. A re-run after the first shows the cross-CPU cache hits.Test Configuration:
Checklist