[avrabe]

Implements the maintainer decision on #477 (2026-10-21): retire the legacy hover scenario and make a scenario that flies the current stack the default.

Measured on the base commit, before the change

falcon-sitl-gz --backend=mock --duration=25:

scenario	final_dist	verdict
hover (old default)	74.63 m	FAIL
flightcore (new default)	0.04 m	PASS

The mock plant reads 0.00 m horizontally by construction, so only the vertical figure carries information there.

Change

• removes the hover arm and run_closed_loop_hover, the legacy relay-ekf → pos → att → rate cascade
• DEFAULT_SCENARIO = "flightcore"
• SCENARIOS lists every dispatched name. main refuses anything else with exit 2, before it opens evidence or connects to gz. Previously an unknown name fell back silently to hover, so a typo measured the diverging path under the name the operator had typed.
• new test: legacy_hover_is_retired_and_the_default_flies_the_flight_core
• SWREQ-FALCON-SIM-P04 gains a retirement note; the README and recording-script docs are updated

Checked

• cargo test -p falcon-sitl-gz: 32/32 pass, including the new test
• --scenario=hover exits 2; the default runs flightcore and passes; supervised-rotorout still passes
• rivet validate PASS (403 warnings, the same as main)
• no CI job runs hover: every gz and soak invocation names its scenario explicitly
• no hits on the Kani scope regex, so the Kani matrix does not run

Not armed for auto-merge: #588 goes first in the merge order.

Refs #477. The issue stays open until the change ships in a tagged release.

🤖 Generated with Claude Code

https://claude.ai/code/session_01HvusAXYbHLyv3uTzfBcMbG

[github-actions]

✅ Rivet verification gate — falcon

176/176 passed

count
Passed	176
Failed	0
Skipped (bench-only — needs hardware / sim)	21
Skipped (no steps)	12

Bench-only artifacts (not run by CI)

• FV-FALCON-ARCH-001 — spar AADL architectural model — falcon cascade (v0.13)
• FV-FALCON-ARCH-002 — spar codegen --format wit recheck — works at v0.10.0 (v0.15.0)
• FV-FALCON-COV-001 — witness MC/DC structural coverage — falcon pipeline wired (v0.13)
• FV-FALCON-COV-002 — cargo-llvm-cov statement coverage — workspace-wide (v0.14.0)
• FV-FALCON-COV-003 — witness MC/DC on real Rust source — Geofence subject (v0.14.1)
• FV-FALCON-GEO-003 — Geofence safety path — miri UB/overflow check (v0.12, AI substitute)
• FV-FALCON-LYAP-002 — Strict (cross-term) Lyapunov — exponential-decay inequality + CI-gated Lean proofs (v1.105)
• FV-FALCON-LYAP-004 — Lyapunov exponential convergence — the deferred 'trajectory ⇒ converges' step, discharged (v1.107)
• FV-FALCON-MATHF32-003 — MATHF32-P03 — machine-checked (Gappa→Flocq→coqc) rounding bound for the f32 sin polynomial (v1.127)
• FV-FALCON-MATHF32-004 — MATHF32-P04 — machine-checked (Coq-Interval) approximation bound for the f32 sin polynomial (v1.128)
• FV-FALCON-MATHF32-005 — MATHF32-P05 — machine-checked rounding + approximation bounds for the f32 cosine kernel (v1.129)
• FV-FALCON-MELD-001 — meld-fuse the verified cascade into a single module (v1.5.0)
• FV-FALCON-OCI-001 — OCI-P01 — signed per-component publish, WASI-free build, and through-wasm closed-loop proof (v1.129)
• FV-FALCON-SIM-001 — PX4-SITL end-to-end loop — recipe + preset + smoke (v0.14.0)
• FV-FALCON-SIM-005 — gz-transport NavSat + Home projection — position-dependent loops (v0.18.1)
• FV-FALCON-TARGET-001 — Verified flight core as a bare-metal ARM Cortex-M ELF + sim backend (v1.6.0)
• FV-FALCON-WASMCM-001 — Verified flight core runs in wasmtime as a CM component (v1.26.0)
• FV-FALCON-WASMCM-002 — All 8 falcon CM components build and bundle script emits versioned dist/ (v1.56)
• FV-FALCON-WCET-001 — Compositional WCET + flight-cascade schedulability, kernel-checked (v1.10.0)
• FV-FALCON-WIT-001 — Verified IEKF componentized + plugged into the composed cascade (v1.4.0)
• FV-RELAY-KANICI-003 — Orphaned-proof sweep completed — flight-support + HAL + infra Kani harnesses enforced in CI (v1.108)

Source of truth: artifacts/verification/FV-FALCON-*.yaml.