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The linker script has L1 address ORIGIN set to 0x10000004 even through in hardware it is set to 0x10000000. However the testbench assumes 64b alignment to initialize the L1. Thus, the data was shifted by 32b in the simulation. While the AXI bursts are set to 64b, the misalignment needs to be handled coming from the linker script.
Being unnecessarily unpacked, it was not compatible with other systems (like Cheshire)
It created problems in routing of requests through peripheral interconnect
… configurations based on WidePortShouldBeEnabled. Update AXI request/response handling and introduce a multiplexer for merging cluster bus and DMA narrow master requests. Enhance isolation and CDC instantiation for wide port scenarios.
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…ncy in DMA configuration Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…PE_PORT also in the package as reference Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
… for Questa Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…ke hex; roll back to astral version Neureka; 3 HWPEs added Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…lized Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…arameters - Update HCI interface parameter structure to correctly propagate the FIFO depth parameter to both the interconnect and the HWPE (Neureka) - Increase the FIFO depth parameter from 0 to 2 to fix the combinational loop due to iDMA being able to read+write from+to TCDM with its 2 backend - Bump versions of HCI and Neureka in bender for updated parameter structure
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Supersedes #103