This code in your top file gives error, I've quartus 18.1 lite. CPU isn't the main file. I mean why you made top file ? The RTL CPU generates is the RISC-V ? How to run "PIPELINE CODE" ? which one is top hierarchy file ? Top or CPU ?
Can you please explain following code to me ?
icon0 instanceB (
.CONTROL0(VIO_CONTROL) // INOUT BUS [35:0]
);
vio0 instanceC (
.CONTROL(VIO_CONTROL), // INOUT BUS [35:0]
.ASYNC_OUT({reset, manclk}), // OUT BUS [65:0]
.ASYNC_IN({PC,x31,we,dwdata,daddr,iaddr}) // IN BUS [163:0]
);
This code in your top file gives error, I've quartus 18.1 lite. CPU isn't the main file. I mean why you made top file ? The RTL CPU generates is the RISC-V ? How to run "PIPELINE CODE" ? which one is top hierarchy file ? Top or CPU ?
Can you please explain following code to me ?
icon0 instanceB (
.CONTROL0(VIO_CONTROL) // INOUT BUS [35:0]
);
vio0 instanceC (
.CONTROL(VIO_CONTROL), // INOUT BUS [35:0]
.ASYNC_OUT({reset, manclk}), // OUT BUS [65:0]
.ASYNC_IN({PC,x31,we,dwdata,daddr,iaddr}) // IN BUS [163:0]
);