Release 0.2.25 - #385
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Release 0.2.25#385
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begin() drove GPIO46 high as a power hold before the board was known. When the application had already called Display.init(), the StopWatch QSPI io2 on GPIO46 was overwritten and never re-routed, so every pixel had a fixed bit and black showed as a bright colour. Skip the early hold in that case and apply it after the pin map is known, only on boards whose power hold is GPIO46 (Dial, Capsule, AirQ, DinMeter). (cherry picked from commit 3d67022)
…the I2S clock where the raw divider is unverified A chip that none of the pin tables name fell through to the ESP32 rows, so a new target with enough GPIOs (ESP32-S31, H4) compiled and then probed the ESP32 I2C pins as board_unknown, while one with fewer (H21) failed to compile. The seven tables now name the ESP32 branch and end in the sentinel row for anything else. (The ESP32-C2, which has no board, moves from the ESP32 rows to the sentinel as well.) The I2S driver configuration asks for I2S_CLK_SRC_DEFAULT everywhere: on every chip whose raw divider path runs it is the PLL_160M source that path expects, so nothing changes on the existing targets, and a chip without it no longer needs naming. The raw clock divider that the speaker and mic tasks write afterwards depends on a per-chip source frequency (M5UNIFIED_I2S_PLL_D2_HZ) that cannot be derived from a capability macro, so it is defined only for the targets it has been verified on; any other chip takes the driver-managed path that the ESP32-P4 already uses (real rate passed at setup, no raw override, the over-sampled rate for PDM capture) instead of guessing 80 MHz. The unverified H4 entry is dropped from the table for the same reason. Together with the matching M5GFX change, ESP32-S31 and ESP32-H21 (ESP-IDF 6.1 preview) build; the existing targets keep their code paths. (cherry picked from commit 17c89a5)
On PowerHub, timerSleep() powered the board off before the STM32 front-end had armed the RTC alarm, so the board never woke up and only the power button brought it back. The STM32 acknowledges the alarm register writes (D0..D3) at once but applies them from its main loop, behind a single "update pending" flag, so a power-off request right after the alarm-enable write can overtake the update, and an update that lands while an older one is applied can be dropped. Space the alarm register writes by 50 ms and wait 500 ms before the timer power-off request. After the request the existing light sleep and restart path is kept. Backport of the waiting part of m5stack#369; the API changes that came with it on the development branch are not included.
setAlarmIRQ(time) passes a null date pointer, and the PowerHub implementation dereferenced it. Leave the day register at zero (every day) when no date is given. Backport of the corresponding part of m5stack#368.
disableIRQ() and the disabled branch of setAlarmIRQ() called bitOff() with a zero mask, which changes no bits, so the alarm stayed enabled. Write zero to the alarm enable register instead. Backport of the corresponding part of m5stack#368.
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Fixes
M5.Display.init()beforeM5.begin()showed wrong colors (black as a bright color):begin()drove GPIO46 as a power hold although it is a display data line on that board. The early hold is skipped in that case and applied once the board is known, only on boards whose power hold is GPIO46 (Dial, Capsule, AirQ, DinMeter). (Keep the display bus on GPIO46 when Display.init() ran before begin() #382)timerSleep()powered the board off before the PowerHub front-end had armed the RTC alarm, so the board did not wake up. The alarm register writes are spaced and the power-off waits for the alarm to settle. (Power/RTC: let the PowerHub STM32 arm the alarm before powering off #369)setAlarmIRQ(time)(no date) crashed, anddisableIRQ()left the alarm enabled. (RTC: report failures from every setter, add isValid(), make timerSleep fail-closed #368)