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| | Type | Item | Status | Note/Collaterals | | ||
| |---------------|----------------------------|--------|------------------| | ||
| | Documentation | SPEC_COMPLETED | Done | [Debug Module specification][block doc]. | ||
| | Documentation | CSR_DEFINED | TODO | The DMI registers are defined here: [DMI registers][dmi-registers]. The memory-mapped registers from the core are defined here: [Debug Memory Map][bus-registers]. TODO: two additional registers are required for CHERI, to indicate the program buffer is in integral pointer mode or capability pointer mode. These are currently allocated offsets 0x120 and 0x128. |
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Should I update the docs to include these registers?
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The CHERI registers can be added to the doc once we integrate the new block. For now it's fine to document the functionality of the current block without CHERI.
| | RTL | IP_INSTANTIABLE | Done | It is instantiated in top chip system. | ||
| | RTL | PHYSICAL_MACROS_DEFINED_80 | TODO | ... | ||
| | RTL | FUNC_IMPLEMENTED | Done | Debug functionality is already impelemented and smoke tested within Mocha. Small changes are expected to support capability debugging. | ||
| | RTL | ASSERT_KNOWN_ADDED | TODO | ... |
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Were these already done for OpenTitan somewhere?
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You may be able to use: https://github.com/lowRISC/opentitan/blob/master/hw/ip/rv_dm/rtl/rv_dm.sv#L744-L763
| | RTL | PHYSICAL_MACROS_DEFINED_80 | TODO | ... | ||
| | RTL | FUNC_IMPLEMENTED | Done | Debug functionality is already impelemented and smoke tested within Mocha. Small changes are expected to support capability debugging. | ||
| | RTL | ASSERT_KNOWN_ADDED | TODO | ... | ||
| | Code Quality | LINT_SETUP | TODO | ... |
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I believe these are already being checked by the system linting?
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Yes, and I don't see any debug or JTAG related lint waives in this file: https://github.com/lowRISC/mocha/blob/main/hw/top_chip/lint/top_chip_system.vlt
| ### D1 | ||
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| The Debug Module used for D1 sign-off is revision [358f9011][debug-hash], the same as used in OpenTitan. | ||
| The sign-off checklist items are described in the [D1 design sign-off checklist][D1 checklist]. |
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Oops, the "D1 checklist" link is broken
| | RTL | CLKRST_CONNECTED | Done | `dm_top.sv` correctly connects `clk_i` and `rst_ni` to `dm_csrs.sv`, `dm_sba.sv`, and `dm_mem.sv`. `dm_csrs.sv` instantiates a `prim_fifo_sync` that connects up the right clock, but changes reset domain to `dmi_rst_ni`, with a comment confirming this is intended. `dm_mem.sv` and `dm_sba.sv` have no further submodules. | ||
| | RTL | IP_TOP | Done | This module is defined in `dm_top.sv`. | ||
| | RTL | IP_INSTANTIABLE | Done | It is instantiated in top chip system. | ||
| | RTL | PHYSICAL_MACROS_DEFINED_80 | TODO | ... |
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The ROM size here, and the CHERI one shouldn't increase by that much right?
marnovandermaas
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marnovandermaas
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I left some initial comments here, please address the TODOs as best you can. The CHERI register documentation, ROM additions, etc. can be deferred to D2. Please also mark this as ready to review once the TODOs are done.
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