[proj] CVA6-CHERI D1 sign-off by PRugg-Cap · Pull Request #738 · lowRISC/mocha

PRugg-Cap · 2026-09-16T14:55:34Z

No description provided.

marnovandermaas

Thank you so much for putting this together. Once the comments are addressed I think we will be able to sign this one off!

marnovandermaas · 2026-09-16T14:58:55Z

Can we rename this file cva6-cheri-d1-clock-audit.md or similar? It would also be nice if this was rederable markdown.

Okay: I will do that if we're happy we want to keep it!

Just to check: Am I okay to Resolve these, or would you prefer to do it once you've checked the comment is addressed?

You can resolve whichever ones you think I don't need to have a second look at.

marnovandermaas · 2026-09-17T14:13:32Z

@@ -0,0 +1,101 @@
+# CVA6-CHERI
+
+CVA6-CHERI in Mocha is imported from the [Capabilities Limited repo][capltd-cva6-cheri].


Probably good to mention that there are some extra patches on top in the lowRISC fork.

marnovandermaas · 2026-09-17T14:15:17Z

+
+CVA6-CHERI in Mocha is imported from the [Capabilities Limited repo][capltd-cva6-cheri].
+
+## CVA6-CHERI design specification


This should probably go in a file called cva6.md in this folder: https://github.com/lowRISC/mocha/tree/main/doc/ref
We should also reference it in https://github.com/lowRISC/mocha/blob/main/doc/ref/arch.md

marnovandermaas · 2026-09-17T14:16:37Z

+
+[riscv-spec]: https://github.com/riscv/riscv-isa-manual
+[capltd-cva6-cheri]: https://github.com/Capabilities-Limited/cheri-cva6
+[cva6-cheri-docs]: https://github.com/Capabilities-Limited/cheri-cva6/tree/zcheri/docs


We should prefer to point to the vendored in versions of these: https://github.com/lowRISC/mocha/tree/main/hw/vendor/cva6_cheri/docs

marnovandermaas · 2026-09-17T14:18:13Z

+F (floating point)
+D (double-precision floating point)
+C (compressed instructions)
+A (atomics)
+Y (CHERI: both purecap and hybrid)
+Zkn (scalar cryptography)
+B (bit manipulation)
+Zicond (branchless conditional instructions)
+Sdext (debug support)
+Sdtrig (debug trigger support)
+Zicbom (cache management operations)


Probably good to make this a bullet list.

marnovandermaas · 2026-09-17T14:23:16Z

+
+| Type          | Item                       | Status | Note/Collaterals |
+|---------------|----------------------------|--------|------------------|
+| Documentation | SPEC_COMPLETED             | Done   | The above section gives information on the specification for CVA6-CHERI, including links to the parent RISC-V and RISC-V CHERI (Y) specifications.


Once we move the spec to the doc/ref document we should link to it here.

marnovandermaas · 2026-09-17T14:25:04Z

+|---------------|----------------------------|--------|------------------|
+| Documentation | SPEC_COMPLETED             | Done   | The above section gives information on the specification for CVA6-CHERI, including links to the parent RISC-V and RISC-V CHERI (Y) specifications.
+| Documentation | CSR_DEFINED                | Done   | As the CPU itself, CVA6-CHERI does not have a memory mapped interface for CSRs. The CSRs are defined by the RISC-V specifications listed above and accessed internally within the core.
+| RTL           | CLKRST_CONNECTED           | TODO   | This is still in progress. I've checked up to about 3 modules deep: see `clock_audit.txt`. We should discuss whether/how this should be checked in.


I think it's fine to have it in the doc/proj. As suggested above we should rename it and make sure it is markdown, but fine to keep this as a separate file to avoid clutter in this one.

marnovandermaas · 2026-09-17T14:25:40Z

+| RTL           | CLKRST_CONNECTED           | TODO   | This is still in progress. I've checked up to about 3 modules deep: see `clock_audit.txt`. We should discuss whether/how this should be checked in.
+| RTL           | IP_TOP                     | Done   | CVA6-CHERI's top-level `cva6` module is defined in [`cva6.sv`][cva6-top]
+| RTL           | IP_INSTANTIABLE            | Done   | CVA6-CHERI's top-level module is instantiated in [`top_chip_system.sv`][cva6-inst-loc].
+| RTL           | PHYSICAL_MACROS_DEFINED_80 | TODO   | ...


Main question here is whether the data cache is configured as you would expect the final version to be. If yes, then happy for this to be checked off.

@marnovandermaas On the PHYSICAL_MACROS_DEFINED_80, it looks like we have doubled the ICache size (16KB -> 32KB) since the version imported in Mocha. This was due to the observed sensitivity of Linux boot times to the ICache size. This means we'll miss the 80% accuracy requirement. I guess there are three options:

Bump the size up in Mocha. This should be a simple patch.

Waive the requirement and document the expected byte usage, as with the tag controller.

Plan to keep the 16K ICache in the version vendored into Mocha.

Let me know what you think is the best path forwards.

I think we can waive the requirement. Please link the following issue where we track this: #745

marnovandermaas · 2026-09-17T14:26:38Z

+| RTL           | IP_INSTANTIABLE            | Done   | CVA6-CHERI's top-level module is instantiated in [`top_chip_system.sv`][cva6-inst-loc].
+| RTL           | PHYSICAL_MACROS_DEFINED_80 | TODO   | ...
+| RTL           | FUNC_IMPLEMENTED           | Done   | CVA6-CHERI's mainline functionality is implemented. The baseline processor implements the RISC-V specification, and CHERI features are implemented, including manipulating capabilities, enforcing capability checks, and propagating tags and capability metadata throughout the pipeline. This is demonstrating by booting the pure capability CHERI Linux within Mocha, and pure capability CheriBSD in the `COREV_APU` SoC on FGPA.
+| RTL           | ASSERT_KNOWN_ADDED         | TODO   | ...


Just putting a comment here so that we can mark it as resolved when the assert knowns are added.

Co-authored-by: Marno van der Maas <34654485+marnovandermaas@users.noreply.github.com>

I haven't been able to test these. I also need to apply the patch to the vendored repo.

I wonder if this should be PR'd into the lowRISC fork instead...

marnovandermaas

Ok I've left another review, I think we're nearly there. If you can address all the open comments that I've raised and then mark them as resolved (unless you need my further input). Please also clean up the commit history a bit. It's fine to introduce the assertions in one commit and then the documentation in another but there's no need to see edits of the same file. If that is too much work it is also fine for you to squash it all into one commit.

marnovandermaas · 2026-09-22T15:17:36Z

 | RTL           | FUNC_IMPLEMENTED           | Done   | CVA6-CHERI's mainline functionality is implemented. The baseline processor implements the RISC-V specification, and CHERI features are implemented, including manipulating capabilities, enforcing capability checks, and propagating tags and capability metadata throughout the pipeline. This is demonstrating by booting the pure capability CHERI Linux within Mocha, and pure capability CheriBSD in the `COREV_APU` SoC on FGPA.
 | RTL           | ASSERT_KNOWN_ADDED         | TODO   | ...
-| Code Quality  | LINT_SETUP                 | DONE   | Verilator warning waivers are added to [`top_chip_system.vlt`][waivers].
+| Code Quality  | LINT_SETUP                 | Done   | Verilator warning waivers are added to [`top_chip_system.vlt`][waivers].


Nit: can we squash this commit with the previous one?

Yeah, I was definitely expecting all these commits to get squashed. Just thought the history would be helpful for you to check all your comments were addressed. I'll rework the history

marnovandermaas · 2026-09-22T15:18:11Z

Nit: can we squash the rename of the file with the commit that introduces clockaudit.txt?

marnovandermaas · 2026-09-22T15:21:28Z

Instead of adding this patch, I have fixed and commited these output asserts on our fork see this commit
You should be able to vendor in the latest CVA6 from there with the following command:

util/vendor.py --update --commit hw/vendor/cva6_cheri.vendor.hjson

Great, thank you!

marnovandermaas · 2026-09-22T15:22:16Z

+|---------------|----------------------------|--------|------------------|
+| Documentation | SPEC_COMPLETED             | Done   | [The CVA6-CHERI design spec][cva6-cheri-spec] describes the specification for CVA6-CHERI, including links to the parent RISC-V and RISC-V CHERI (Y) specifications.
+| Documentation | CSR_DEFINED                | Done   | As the CPU itself, CVA6-CHERI does not have a memory mapped interface for CSRs. The CSRs are defined by the RISC-V specifications listed above and accessed internally within the core.
+| RTL           | CLKRST_CONNECTED           | TODO   | This is still in progress. See the [clock audit][clock-audit].


This is now done right?

marnovandermaas · 2026-09-22T15:24:19Z

+| RTL           | CLKRST_CONNECTED           | TODO   | This is still in progress. I've checked up to about 3 modules deep: see `clock_audit.txt`. We should discuss whether/how this should be checked in.
+| RTL           | IP_TOP                     | Done   | CVA6-CHERI's top-level `cva6` module is defined in [`cva6.sv`][cva6-top]
+| RTL           | IP_INSTANTIABLE            | Done   | CVA6-CHERI's top-level module is instantiated in [`top_chip_system.sv`][cva6-inst-loc].
+| RTL           | PHYSICAL_MACROS_DEFINED_80 | TODO   | ...


I think we can waive the requirement. Please link the following issue where we track this: #745

PRugg-Cap added 2 commits September 16, 2026 15:50

Check in WIP file documenting hierarchical CVA6-CHERI clock connections

baddafe

Add documentation for CVA6-CHERI D1 sign-off

c4273a5

marnovandermaas reviewed Sep 17, 2026

View reviewed changes

PRugg-Cap and others added 17 commits September 17, 2026 16:59

Update doc/proj/cva6-cheri.md

afc389d

Co-authored-by: Marno van der Maas <34654485+marnovandermaas@users.noreply.github.com>

Rename clock autit file

4af8130

Explain and make the clock audit readable MD

abaa78e

document that CVA6-CHERI comes from lowRISC fork

f2cfe23

Split CVA6 design spec into ref directory

59c655e

Reference cva6 design spec from mocha spec

6716a78

Switch to referencing vendored CVA6 docs

f93d7c4

Make supported extensions a bullet list

1cb0316

Link to upstream cva6

453a0f4

Fix local links to be relative

ff168cb

Fix references to CVA6 CHERI design spec

27ee315

Update link to clock audit

d53e986

Fix link to CVA6 top

1703100

Bump the status of CVA6-CHERI

3965875

Add patch for CVA6 output assertions

28b8ebc

I haven't been able to test these. I also need to apply the patch to the vendored repo.

Run vendor script to bring in Known CVA6 asserts

0e14594

I wonder if this should be PR'd into the lowRISC fork instead...

Report Done for ASSERT_KNOWN_ADDED

a3a8cb3

marnovandermaas reviewed Sep 22, 2026

View reviewed changes

		@@ -0,0 +1,101 @@
		# CVA6-CHERI

		CVA6-CHERI in Mocha is imported from the [Capabilities Limited repo][capltd-cva6-cheri].


		CVA6-CHERI in Mocha is imported from the [Capabilities Limited repo][capltd-cva6-cheri].

		## CVA6-CHERI design specification

Conversation

PRugg-Cap commented Sep 16, 2026

Uh oh!

marnovandermaas left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

PRugg-Cap Sep 17, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

marnovandermaas left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

PRugg-Cap Sep 17, 2026 •

edited

Loading