[proj] Timer D1 sign-off - #726
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tchilikov-semify wants to merge 1 commit into
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marnovandermaas
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Sep 22, 2026
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One minor comment, but otherwise looks good to me. Let's wait for 3 approvers before merging.
| |---------------|----------------------------|--------|------------------| | ||
| | Documentation | SPEC_COMPLETED | Done | [Timer specification][block doc]. | ||
| | Documentation | CSR_DEFINED | Done | [Timer registers][registers]. | ||
| | RTL | CLKRST_CONNECTED | Done | Modules containing submodules checked: `rv_timer.sv` and `rv_timer_reg_top.sv`. Modules without clocks and resets are confirmed to be purely combinational: `prim_onehot_enc`, `prim_subreg_ext`, `tlul_cmd_intg_chk` and `tlul_rsp_intg_gen`. The shared `prim_*` and `tlul_*` submodules are covered by their own OpenTitan sign-offs and are not walked here. |
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Are there more prim and tlul modules besides the one you already list as purely combinational? If not we can remove the last sentence.
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Yes, I explicitly named them now.
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Add the D1 design sign-off checklist for the Timer and move it to D1 in the stage table.
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Add the D1 design sign-off checklist for the Timer and move it to D1 in the stage table.