Repository navigation
[arch][x86][lapic] don't stop the timer on a 0 interval - #546
Merged
Merged
Conversation
timer_cancel() passes a 0 interval when the timer it promotes to the head of the queue is already due. In one-shot count-down mode a 0 initial count stops the LAPIC timer, so that timer never fires and every later timer on the cpu stalls behind it. Clamp the count to 1 tick so a 0 interval fires as soon as possible; only lapic_cancel_timer() writes 0. Document that platform_set_oneshot_timer() must not treat 0 as a stop, and add a test that hits the race.
There was a problem hiding this comment.
Copilot was unable to review this pull request because the user who requested the review has insufficient remaining quota.
An organization owner can choose the repository organization as the billing source for reviews requested by members with a paid Copilot license. Learn about Copilot code review billing.
Member
|
LGTM. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
timer_cancel()passes a 0 interval toplatform_set_oneshot_timer()when the timer it promotes to the head of the queue is already due. In LAPIC one-shot count-down mode (no TSC-deadline, e.g. QEMU TCG), a 0 initial count stops the timer: the new head never fires, and every later timer on that CPU stalls behind it.lapic_cancel_timer()writes 0.platform/timer.hthat a 0 interval must not disarm the timer;platform_stop_timer()is the only way to do that.test_timer_cancel_past_due_newhead. It sets two 1ms timers halfway through a tick, waits until their deadline has passed but before the hardware fires, then cancels the head. It pins itself to CPU 0, which relies on the synchronous migration from [kernel][thread] migrate running thread immediately in thread_set_pinned_cpu #544.Tested with
scripts/run-qemu-boot-tests.py: without the fix, x86-64 hangs in the new test; with it, x86-64, x86, arm64, arm and arm-m3 pass.