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Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Clear VCVTPS2PH register destination upper lanes and merge SoftFloat exception flags into MXCSR after both F16C conversion directions. Ignore FTZ for PS2PH and DAZ for PH2PS, restoring the original controls after each conversion. Add x86_64/i386 regressions for upper lanes, exception state, rounding, and register preservation. NaN result handling is unchanged. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
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VCVTPH2PS xmm, m64 consumes eight bytes, but both LASX and LSX translation paths loaded sixteen bytes. A valid source at the end of a readable mapping could therefore fault when the following mapping was inaccessible. Use the raw 64-bit load for the XMM destination form and retain the 128-bit load for the YMM form. Preserve the existing borrowed-register handling and result-state updates. Add a registered page-boundary regression that checks XMM and YMM conversion results and XMM upper-zero behavior. The test faults with the previous binary and passes after the fix in JIT, cold AOT, and marker-verified hot AOT execution. Validation on LoongArch: x86_64/i386 builds passed; lat-pr-fast passed 51/51; F16C memory-boundary, MXCSR, and upper-zero integration tests passed 3/3. Runtime coverage is x86_64 on the current host; independent LSX and i386 execution remains unverified. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
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Summary
LATX already implements VCVTPH2PS, VCVTPS2PH, and 16/32/64-bit LZCNT. Advertise F16C and LZCNT in the default x86-64 CPU model so guests can use those translations. Keep F16C hidden when AVX is disabled because F16C depends on AVX state support.
Validation
master; clean 3A6000-25G O1 integrated build passed.aot2filelat-pr-fast: 25/25 passed on the integrated treeThis PR remains a draft pending review and CI.