[Copilot]

Adds CanHardware drivers for the MCP25625T (CAN 2.0) and MCP251863T (CAN FD) SPI controllers. Each driver is a single header and source file with no external driver library. The CanHardware interface is unchanged, and chip-specific features such as FD mode sit outside it.

Both drivers are untested. Only a syntax check against stub headers was done, because libopencm3 isn't available in this environment.

Mcp251863Can can(SPI1, DigIo::can_cs, CanHardware::Baud500);
can.EnableFd(true, 2000000);
can.SendFd(0x123, buf, 32, /*brs*/ true);
// from the INT pin ISR or a poll loop:
can.HandleInterrupt();

• Common to both
  • Constructor is (uint32_t spi, DigIo& cs, baudrate). spi is a libopencm3 SPI base address, which must already be configured for mode 0, MSB first, 8 bit. CS is active low.
  • Send buffer is copied from Stm32Can (sendBuffer, sendCnt, SENDBUFFER_LEN). Frames that don't fit in the chip's TX buffers are queued and drained by HandleTx(). The same DISABLE/ENABLE_CAN_USER_INTERRUPTS guards are used.
  • There is no ISR wiring. The application calls HandleInterrupt() (RX, then TX drain) from the INT pin handler or a poll loop.
  • Bit timing is computed from MCP25625_OSC_HZ (default 16 MHz) or MCP251863_SYSCLK_HZ (default 40 MHz).
• mcp25625_can.{h,cpp}
  • Uses the MCP2515-compatible command set: three TX buffers and two RX buffers with rollover.
  • Hardware filters are left open and userIds/userMasks are matched in software. ConfigureFilters() does nothing.
  • Extra function: SetListenOnly().
• mcp251863_can.{h,cpp}
  • Uses an 8-element TXQ and a 16-element RX FIFO. Both have 64-byte payloads and fit in the 2 KB of RAM.
  • ConfigureFilters() programs the 32 hardware filters (a standard or extended match, with an optional mask) from userIds/userMasks.
  • Defaults to CAN 2.0 mode. FD is controlled outside the interface by EnableFd(), SetDataBaudrate(), SendFd() (up to 64 bytes, optional BRS) and SetFdRxCallback(). Frames longer than 8 bytes go to the callback if set, otherwise they are truncated to 8 bytes.
  • SetListenOnly() is also available.

Review focus

• The MCP251863T register layout and bit positions were written from my knowledge of the MCP2518FD datasheet, not from a reference library. Please check these against the datasheet:
  • C1CON, NBTCFG, DBTCFG, TDC
  • FIFOCON, FIFOSTA and FIFOUA, including the +0x400 RAM offset
  • the FLTOBJ and MASK layout
• The MCP25625T oscillator is assumed to be 16 MHz and the MCP251863T system clock 40 MHz. Override them with the macros above if your hardware differs.