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Add Si5351::reset_freq() to forget one clock output - #114
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reset_freq() stores 0 Hz for one CLK, disables that output, and clears its first-set flag so the next set_freq() enables it again. An invalid clock index is ignored and other outputs are left unchanged. reset() uses it for the per-output initial state. Based on #104 by KT315AM. Co-authored-by: KT315AM <kt@315.am> Co-authored-by: Jason Milldrum <NT7S@users.noreply.github.com>
si5351_clock is an unfixed enum covering CLK0..CLK7. A value outside that range is undefined behavior, so the README, changelog, and function comment now say out-of-range values are not supported. The bounds check in reset_freq() is unchanged. Co-authored-by: Jason Milldrum <NT7S@users.noreply.github.com>
This was referenced Nov 8, 2026
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Summary
Adds public
Si5351::reset_freq(enum si5351_clock clk)on current master (v2.4.1,ee6cdb0). The idea and the original patch are from @KT315AM in #104. That branch conflicts with the v2.4.x source, so this is a new implementation against master rather than a rebase of #104.reset_freq(clk):clk_freq[clk]clk_first_set[clk]so the nextset_freq()enables the output automatically, the same as the first callsi5351_clockvalue (SI5351_CLK0..SI5351_CLK7); out-of-range values are not supported.si5351_clockis an unfixed enum, so a value outside 0..7 is undefined behavior and rejection cannot be promised portably. The function still bounds-checks the index.Other clocks are left unchanged: stored frequency, enable bit, first-set flag, PLL assignment, and every register except that clock's output-enable bit.
reset()usesreset_freq()for its per-output initial state; the register writes match the previous loop. Version and license are unchanged.Test plan
tests/regression/reset_freq/t_reset_freq.cpp(100 checks, ASan/UBSan clean): reset thenset_freqre-enables CLK0, CLK3, CLK5, CLK6, and CLK7; a manualoutput_enable(0)does not; other clocks stay untouched./tests/regression/run_v231_checks.sh --src <tree>overall PASS: acceptance 25/25, must-not-break 776/776, t106, goldens,reset_freq100/100