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Lock the R-divider table, document v2.4.1 limits, replace dead links - #113
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Issue #89's repeated divide-by-64 clause is the following divide-by-32 octave. Keep that table, cite the AN619 R0_DIV codes, and regression-test every band edge. Document that SI5351_CRYSTAL_LOAD_0PF is the reserved XTAL_CL value in AN619 Register 183 and that init() keeps 10 pF. Record the v2.4.1 multisynth, output, quadrature, and 200 MHz limits in the README. Point the dead etherkit.com links at this repository. Fixes #89, fixes #102 Co-authored-by: Jason Milldrum <NT7S@users.noreply.github.com>
select_r_div() is the CLK0-5 octave table. set_freq() on CLK6/7 picks the smallest R that reaches 600 MHz/254, so 36908 Hz is divide-by-128 in register 92, not divide-by-64. The regression test now drives set_freq and reads that register. The distinct-code masks record the divider that was actually returned. Qualify the CLK6/7 upper clamp as set_freq() behavior: set_freq_manual(150 MHz, 900 MHz, CLK6) is a legal ratio 6. State the CLK0-5 set_freq cap as 200 MHz in the v1-to-v2 note, and check those README numbers against the header constants. Co-authored-by: Jason Milldrum <NT7S@users.noreply.github.com>
…mits-links-1511 Co-authored-by: Jason Milldrum <NT7S@users.noreply.github.com> # Conflicts: # README.md # tests/regression/README.md # tests/regression/run_v231_checks.sh
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Summary
[2F, 4F)and divide-by-32 for[4F, 8F). That octave table is whatselect_r_div()does for CLK0–CLK5 (AN619 Register 44,R0_DIV).tests/regression/rdiv/t_rdiv.cpplocks every CLK0–CLK5 edge, including register 44 at 8 kHz (/64) and 16 kHz (/32). The distinct-code check records the divider the function returned, so a duplicated band fails it.set_freq()picks the smallest R that reaches 600 MHz / 254. 36908 Hz is divide-by-128 in register 92 (/64would leave the multisynth under 600 MHz). The test drivesset_freq()on CLK6 and CLK7 and locks those register 92 edges.SI5351_CRYSTAL_LOAD_0PFremains the reserved XTAL_CL value00b. AN619 Register 183 says "00: Reserved. Do not select this option."init()substitutes the 10 pF default and writes bits 5:0 as010010b. The macro is deprecated, not aliased to another load.set_freq()runs from 4 kHz to 200 MHz on CLK0–CLK5. The just-under-150 MHz CLK6/CLK7 ceiling isset_freq()only;set_freq_manual(150 MHz, 900 MHz PLL, CLK6)is ratio 6 and returns 0. The regression test greps those README numbers against the header constants andSI5351_FOUT_MAX.library.propertiesalready used that URL. The examples have no etherkit.com link.Version is still 2.4.1. The license is unchanged.
Fixes #89, fixes #102
Tests
tests/regression/run_v231_checks.sh --srcon this tree:rdiv_xtalpasses, acceptance A01–A25 pass, must-not-break 776/776. Breaking the/32band, or stopping the CLK6/7 divider at/64, makes the distinct-code checks fail.