Repository navigation
PCB layout phase 1: stackup, outline, edge/panel placement (unrouted) - #3
Merged
Merged
Conversation
…p (blue mask), RF50 netclass 0.35 mm, 100x65 outline + 4x M3, edge/panel part placement, OLED keepout, rough placement (unrouted); simple 3D models; mechanical outline + STEP
…mm tact switches, plated GND M3 holes, In1 cut under SMA centre pads, In1/In2 GND planes, Etherkit branding + Rev A on F.Cu; regen renders/outline/STEP
…upling at U2/X1 pins, power/USB tidied (LDO rows Cin-U-Cout-FB), CLK0-2 labels, horizontal front branding, back-silk book line, silkscreen overlaps cleared; regen renders/outline/STEP
…adder -> out-select -> SMA), bypass jumper at input end behind GND via fence; J5 UPDI title + pin labels
…ed bypass lane; netlist sync
…select jumpers, Cauer LPF, bypass lane to SMAs; GND vias at all SMD GND pads; RF stitching; F/B GND pours
…ower+digital (WIP, 26 unconnected); Alps EC11E18244A5 model for SW1; regen board STEP
…g; add tools/pcbgen build scripts; U3 EP vias; OLED-area F.Cu track keepout
…I2C, UPDI); DRC 0 unconnected
…ing, 0402 CLK series Rs, RF50 incl. CLK*_BYP; regen docs
…1-S3, SW2-SW4 SOFT1-3; regen docs
…>U2 on In2/B.Cu; C26 at VDDO pin 7, C4 at VDD pin 1
…; DRC 0 unconnected, 0 clearance
…ks at 0.20-0.21 mm, all RF lanes 0.31 mm except 0.25 mm U2 pin breakouts)
…ut, 20 vias closing >2.2 mm gaps on filter fence lines
…est of +3V3_CLK trunk clear of UPDI legend; DRC: only SMA edge-launch hits
…nts, models, router/stitch helpers, fr.ses); document hand-fix caveat
added 7 commits
October 24, 2026 15:57
… wall); DRC unchanged
…/SDA) on B.Cu, 1.5 mm SMD, excluded from BOM/CPL; no RF nets. JLC fab outputs (tools/export_fab.sh -> PCB/production). ERC 0, DRC only the 15 accepted SMA edge hits
…C105580->C23186 (0603WAF5101T5E). Board fields synced, ERC 0, DRC 15 accepted SMA hits, fab outputs + schematic PDF regenerated
…usb second set renamed #PWR920-923 (property + instance reference). Netlist export clean, ERC 0, DRC 15 accepted SMA hits, BOM/CPL unchanged; docs regenerated
…03WAF1001T5E 1%), grouped with R29. Extended parts 33->32. ERC 0, DRC 15 accepted SMA hits, 0 unconnected/parity; fab + docs regenerated
…d docs conflicted, regenerated from merged schematic (ERC 0)
NT7S
marked this pull request as ready for review
October 25, 2026 16:49
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Depends on #2 (rev-a-schematic). This branch is built on top of it; merge #2 first. Draft, do not merge.
Phase 1 only, with no traces routed:
Known DRC items: SMA pads sit at the board edge on purpose (end-launch), J1's stock footprint has a hole clearance of 0.185 mm, silkscreen is not tidied yet, and nothing is routed.