Schematic review round 2: US resistors, decoupling placement, VERIFY checklist, gitignore

.github/workflows/kicad-docs.yml

@@ -0,0 +1,76 @@
+# Regenerates docs/ and runs ERC on schematic changes; see tools/export_docs.sh.
+name: KiCad docs and ERC
+
+on:
+  push:
+    paths:
+      - 'PCB/**/*.kicad_sch'
+      - 'PCB/*.kicad_pro'
+      - 'tools/export_docs.sh'
+      - '.github/workflows/kicad-docs.yml'
+  pull_request:
+    paths:
+      - 'PCB/**/*.kicad_sch'
+      - 'PCB/*.kicad_pro'
+      - 'tools/export_docs.sh'
+      - '.github/workflows/kicad-docs.yml'
+
+permissions:
+  contents: write
+
+concurrency:
+  group: kicad-docs-${{ github.ref }}
+  cancel-in-progress: false
+
+jobs:
+  erc-and-docs:
+    # Loop guard: never react to our own bot commits.
+    if: github.actor != 'github-actions[bot]'
+    runs-on: ubuntu-latest
+    container:
+      image: kicad/kicad:10.0-full  # -full ships the stock symbol/footprint libs
+      options: --user root
+    steps:
+      - name: Install git
+        run: apt-get update -qq && apt-get install -y -qq git >/dev/null
+
+      - uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event_name == 'push' && github.ref || '' }}
+
+      - name: Trust workspace
+        run: git config --global --add safe.directory "$GITHUB_WORKSPACE"
+
+      - name: Install default KiCad library tables for this user
+        run: |
+          d="$HOME/.config/kicad/10.0"; mkdir -p "$d"
+          for t in sym-lib-table fp-lib-table; do
+            [ -f "$d/$t" ] || cp "/usr/share/kicad/template/$t" "$d/$t"
+          done
+          ls -l "$d"
+
+      - name: ERC (fail on errors only; warnings allowed)
+        run: |
+          kicad-cli sch erc --severity-error --exit-code-violations \
+            -o /tmp/erc-errors.rpt PCB/Si5351AVFO.kicad_sch
+          cat /tmp/erc-errors.rpt || true
+
+      - name: Export PDF, netlist, SVGs, ERC report
+        run: tools/export_docs.sh
+
+      - name: Commit regenerated docs (push only, skip date-only changes)
+        if: github.event_name == 'push'
+        run: |
+          git add -A docs
+          # Netlist, ERC report and SVGs are text renderings of the same
+          # schematic as the PDF. If they differ only in timestamp lines,
+          # the PDF change is just its embedded date: drop everything.
+          if git diff --cached --quiet -I 'date' -I '\(source ' -I 'ERC report \(' -- docs/Si5351AVFO.net docs/erc.rpt docs/svg \
+             && ! git diff --cached --name-only --diff-filter=AD -- docs | grep -q .; then
+            echo "Only embedded dates changed; nothing to commit."
+            exit 0
+          fi
+          git config user.name "github-actions[bot]"
+          git config user.email "41898282+github-actions[bot]@users.noreply.github.com"
+          git commit -m "docs: regenerate schematic PDF, netlist, SVGs, ERC report [skip ci]"
+          git push origin "HEAD:${GITHUB_REF_NAME}"

.gitignore

@@ -0,0 +1,15 @@
+# KiCad lock files
+*.lck
+~*.lck
+# KiCad autosave and backups
+_autosave-*
+*-backups/
+\#auto_saved_files\#
+*.bak
+*.bck
+*-bak
+*.kicad_sch-bak
+*.kicad_pcb-bak
+*~
+# Caches
+fp-info-cache

PCB/Si5351AVFO.kicad_pro

@@ -264,7 +264,7 @@
     "classes": [
       {
         "bus_width": 12,
-        "clearance": 0.2,
+        "clearance": 0.15,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
@@ -280,14 +280,142 @@
         "via_diameter": 0.6,
         "via_drill": 0.3,
         "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "RF50",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 0,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.31,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
       }
     ],
     "meta": {
       "version": 5
     },
     "net_colors": {},
     "netclass_assignments": {},
-    "netclass_patterns": []
+    "netclass_patterns": [
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK0"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK1"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK2"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C100-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C102-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C103-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C120-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C122-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C123-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C140-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C142-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(C143-Pad1)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(J2-In)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(J3-In)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(J4-In)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP102-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP102-B)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP103-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP122-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP122-B)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP123-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP142-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP142-B)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "Net-(JP143-A)"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK0_BYP"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK1_BYP"
+      },
+      {
+        "netclass": "RF50",
+        "pattern": "/Synth and RF outputs/CLK2_BYP"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {
@@ -458,4 +586,4 @@
     },
     "tuning_profiles_impedance_geometric": []
   }
-}
+}

PCB/Si5351AVFO.kicad_sch

@@ -9,7 +9,7 @@
 		(date "2026-10-22")
 		(rev "A")
 		(company "Etherkit / NT7S")
-		(comment 1 "Draft schematic, not reviewed. See VERIFY notes.")
+		(comment 1 "Draft schematic, not reviewed. Open items: docs/VERIFY.md")
 	)
 	(lib_symbols)
 	(text "Si5351A VFO Rev A - Field Manual Ch. 6. Plan: PLAN.md (2026-10-22). Hierarchy: power/USB, MCU/UI, synth/RF.\nInter-sheet nets via global labels (MCU_TX, MCU_RX, DTR, I2C_SCL, I2C_SDA) and power rails."