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Update Proof section with measured collaborative scan benchmark #26

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Merged
timkpaine merged 2 commits into from
Oct 6, 2026
Merged

Update Proof section with measured collaborative scan benchmark #26

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93fd69c
State the measured CPU-plus-card result in the Proof section
timkpaine Oct 6, 2026
6dcb3ba
Check the Proof section's measured result in the page test
timkpaine Oct 6, 2026
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15 changes: 9 additions & 6 deletions src/lib/home/Proof.svelte
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,13 @@
<p class="text-lg leading-relaxed text-neutral-400">
dau began on dpv1 with a 5 GB NYSE TAQ dataset and a concrete task: calculate OHLCV bars.
Staged resident, repeated queries ran in 0.92 seconds against 1.5 seconds on the CPU—39%
lower per-query latency, every result matched to the software golden. dpv2 now carries that
work further: a fused temporal-finance workflow—as-of join, derived features, time bars and
rolling moments in a single pass, with no intermediate ever written back to memory—runs in
11.5 ms against 31.4 ms for the same workload on an 18-core laptop, bit-exact. The
accelerator costs a fraction of the machine it outruns.
lower per-query latency, every result matched to the software golden. dpv2 is commodity
hardware doing real work: a consumer-grade FPGA card that costs about $700, in a
consumer-grade desktop with a quad-core Intel Core i7. With a six-million-row table resident
on the card, Polars and the card working the same scan together finished in 4.2 ms against
10.4 ms for the CPU alone, using all of its threads. That is 2.5x faster, and every result
matched the software golden at every one of the 164 split points we measured. The scheduler
chose the split from measured costs; nobody tuned it by hand.
</p>
</div>
<div class="grid gap-4">
Expand Down Expand Up @@ -43,7 +45,8 @@
<p class="text-lg text-white mb-2">204K LUTs · 10 GB DDR3 · PCIe x8</p>
<p class="text-sm text-neutral-400">
Two memory systems (2 GB onboard for bandwidth, 8 GB SODIMM for resident capacity) and
eight parallel lanes. Where the fused temporal workflow now beats the CPU baseline.
eight parallel lanes. CPU and card together: 2.5x the CPU alone on a resident scan,
bit-exact.
</p>
</div>
<div class="rounded-lg border border-dashed border-neutral-700 p-6 opacity-50">
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3 changes: 2 additions & 1 deletion tests/test.ts
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Expand Up @@ -25,7 +25,8 @@ test('home page presents both ends of the dau platform', async ({ page }) => {
await expect(page.getByText('In design')).toBeVisible();
await expect(page.getByText('39% lower per-query latency', { exact: false })).toBeVisible();
// the current platform's measured result, not just the origin story
await expect(page.getByText('11.5 ms', { exact: false })).toBeVisible();
await expect(page.getByText('4.2 ms against', { exact: false })).toBeVisible();
await expect(page.getByText('2.5x faster', { exact: false })).toBeVisible();
await expect(page.getByRole('link', { name: 'Become a design partner' })).toBeVisible();
});

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