dau simulator
dau-sim simulates digital hardware designs on csp's reactive stream processing engine. Hardware signals become CSP time-series edges, combinational logic becomes CSP nodes, and clock domains become CSP clock processes. The result is a cycle-accurate simulator with deterministic event scheduling and multi-clock support.
Supported inputs:
- Amaranth HDL, Python-native hardware description
- SystemVerilog / Verilog, parsed with pyslang
- Hand-constructed IR, for programmatic design generation
Output formats: VCD (IEEE 1364-2001) waveform files. FST and live streaming are planned.
pip install dau-simFor development:
git clone https://github.com/dau-dev/dau-sim.git
cd dau-sim
pip install -e ".[develop]"from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out
from amaranth.hdl import Module
from dau_sim.frontends import from_amaranth
from dau_sim.compiler import compile_module
class Counter(wiring.Component):
en: In(1)
count: Out(8)
def elaborate(self, platform):
m = Module()
with m.If(self.en):
m.d.sync += self.count.eq(self.count + 1)
return m
cm = compile_module(from_amaranth(Counter()))
traces = cm.run(cycles=20, inputs={"en": 1})
cm.write_vcd("counter.vcd", traces)dau-sim is a general simulator. It knows nothing about DAU contracts or
tiles. The rest of the stack uses it through composition: the simulate task
in dau-build drives it from the same declarative build spec as synthesis,
so one description both simulates and builds:
# in a dau-build checkout, which carries the identity example
dau-build task=tasks/sim/simulate model.module=dau_identity_top model.spec_path=examples/identity/dau-build.yamlDesign-specific verification, such as the golden-equal cocotb benches for
the DAU operator tiles, lives with the tiles in dau-core.
| Topic | Description |
|---|---|
| Amaranth | Simulating Amaranth HDL designs |
| Verilog / SystemVerilog | Simulating SV/V designs and hand-built IR |
| cocotb | Running cocotb testbenches against dau-sim |
| CLI | Command-line interface reference |
| Architecture | Pipeline and internal design |
| API Reference | Full API tables |
| Benchmarks | Performance numbers and execution modes |
This project is licensed under the Apache 2.0 License. See LICENSE for details.