feat(dmac): add shared hardware CRC channel support

[crabel99]

Why

Expose the SAMD DMAC CRC engine without making each DMA consumer program its registers or arbitrate ownership. DmacCrc observes a channel whose owner retains the descriptors and transfer callbacks.

Scope

Adds cores/arduino/DmacCrc.h and .cpp only. begin() selects CRC-16 or CRC-32 with an explicit seed before a DMA channel starts. finish() returns the hardware checksum after successful completion, or releases ownership after abort without publishing a partial checksum. Competing requests return Busy. Register access preserves interrupt state and the D21 channel selector.

The module supports the D21, D51 and SAME53/54 register layouts. It uses one byte of persistent state and no heap allocation or payload buffer. It does not automatically append or verify a SERCOM wire trailer.

Verification

The exact CRC source files were tested in the integrated Framework checkout:

• Framework_test native CTest suite: 35/35 passed, including D21, D51 and E54 register/ownership tests.
• ARM firmware builds: RedBoard Turbo D21, Metro M0, Metro M4 and SAME54 passed.
• RedBoard Turbo hardware: 10/10 real DMA cases passed, including known CRC16/CRC32 vectors, 255-byte and 256-byte transfers, linked descriptors, contention, abort and reuse. Its bootloader was verified unchanged.
• Local CI example matrix via tools/build_all.py: all 12 workflow configurations passed in the integrated checkout, including both TinyUSB configurations.
• SAME54 hardware validation remains pending.

Known-vector results were CRC32 CBF43926, CRC16 seed FFFF 29B1, and CRC16 seed zero 31C3 for 123456789. A 255-byte patterned transfer produced 6626D95D both contiguously and through linked 127-byte/128-byte descriptors.

Base: upstream master at e914db61e1ab88c7f0fbf4827f8329389a4cc8d5. The PR contains none of the integration bundle's other changes.