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Merged
eyck merged 8 commits into from
Sep 28, 2026
Merged

Bugfix/floating and reset #60

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4bae3b8
new generation of asmjit changed order of includes
EAlexJ Aug 18, 2026
145547c
reset now correctly zeroes out all registers
EAlexJ Aug 18, 2026
025ceaa
adds newly generated files, addressing the concerns of #59
EAlexJ Sep 24, 2026
872abbb
new generation of asmjit changed order of includes
EAlexJ Aug 18, 2026
0952293
reset now correctly zeroes out all registers
EAlexJ Aug 18, 2026
47e33b2
adds newly generated files, addressing the concerns of #59
EAlexJ Sep 24, 2026
34756e2
Merge remote-tracking branch 'origin/bugfix/reset' into bugfix/floati…
EAlexJ Sep 24, 2026
398d8e6
Merge remote-tracking branch 'origin/bugfix/floating_point_instructio…
EAlexJ Sep 24, 2026
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2 changes: 1 addition & 1 deletion gen_input/ISA
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Submodule ISA updated 3 files
+2 −2 RVC.core_desc
+4 −3 RVD.core_desc
+7 −7 Zc.core_desc
6 changes: 1 addition & 5 deletions gen_input/templates/CORENAME.cpp.gtl
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Expand Up @@ -57,14 +57,10 @@ ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;

void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv32gc.cpp
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Expand Up @@ -50,14 +50,10 @@ rv32gc::rv32gc() = default;
rv32gc::~rv32gc() = default;

void rv32gc::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv32gc>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv32gc>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv32gc::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv32gcv.cpp
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Expand Up @@ -50,14 +50,10 @@ rv32gcv::rv32gcv() = default;
rv32gcv::~rv32gcv() = default;

void rv32gcv::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv32gcv>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv32gcv>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv32gcv::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv32i.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv32i::rv32i() = default;
rv32i::~rv32i() = default;

void rv32i::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv32i>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv32i>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv32i::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv32imac.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv32imac::rv32imac() = default;
rv32imac::~rv32imac() = default;

void rv32imac::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv32imac>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv32imac::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv64gc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv64gc::rv64gc() = default;
rv64gc::~rv64gc() = default;

void rv64gc::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv64gc>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv64gc>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv64gc::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv64gcv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv64gcv::rv64gcv() = default;
rv64gcv::~rv64gcv() = default;

void rv64gcv::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv64gcv>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv64gcv>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv64gcv::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv64i.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv64i::rv64i() = default;
rv64i::~rv64i() = default;

void rv64i::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv64i>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv64i>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv64i::get_regs_base_ptr() {
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6 changes: 1 addition & 5 deletions src/iss/arch/rv64imac.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,14 +50,10 @@ rv64imac::rv64imac() = default;
rv64imac::~rv64imac() = default;

void rv64imac::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<rv64imac>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<rv64imac>::NUM_REGS; ++i)
*(base_ptr+i)=0;
std::memset(&reg, 0, sizeof(reg));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
reg.trap_state=0;
reg.icount=0;
}

uint8_t *rv64imac::get_regs_base_ptr() {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv32gc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv32gc.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -10106,8 +10106,8 @@ std::unique_ptr<vm_if> create<arch::rv32gc>(arch::rv32gc *core, unsigned short p
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv32gcv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv32gcv.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -85513,8 +85513,8 @@ std::unique_ptr<vm_if> create<arch::rv32gcv>(arch::rv32gcv *core, unsigned short
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv32i.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv32i.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -2949,8 +2949,8 @@ std::unique_ptr<vm_if> create<arch::rv32i>(arch::rv32i *core, unsigned short por
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv32imac.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv32imac.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -5549,8 +5549,8 @@ std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned sho
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv64gc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv64gc.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -12687,8 +12687,8 @@ std::unique_ptr<vm_if> create<arch::rv64gc>(arch::rv64gc *core, unsigned short p
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv64gcv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv64gcv.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -88094,8 +88094,8 @@ std::unique_ptr<vm_if> create<arch::rv64gcv>(arch::rv64gcv *core, unsigned short
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv64i.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv64i.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -3604,8 +3604,8 @@ std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short por
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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4 changes: 2 additions & 2 deletions src/vm/asmjit/vm_rv64imac.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/

// clang-format off
#include <iss/arch/rv64imac.h>
#include <iss/debugger/gdb_session.h>
Expand Down Expand Up @@ -7597,8 +7597,8 @@ std::unique_ptr<vm_if> create<arch::rv64imac>(arch::rv64imac *core, unsigned sho
} // namespace iss

#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/factory.h>
namespace iss {
namespace {
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