A digital control system for a commercial washing machine implemented on a Nexys A7-100T FPGA.
This project was developed collaboratively as part of the Digital Systems Design coursework at the Technical University of Cluj-Napoca.
The architecture is strictly divided into a Data Path (Execution Unit) and a Control Path (Moore FSM), consisting of 24 custom resources (timers, debouncers, frequency dividers, and decoders) written entirely in VHDL.
For a complete breakdown of the state machine, hardware routing, timing constraints, and design justifications, please read the Hardware Architecture Spec included in this repository.
- 13-State Moore FSM: Completely glitch-free control unit managing hardware phases (Pre-wash, Main Wash, Rinse, Centrifuge).
- Dual-Mode Operation: 5 factory-programmed automatic modes via ROM LUTs, plus fully granular manual configuration.
- Real-Time Timers: Frame-rate independent countdown timers utilizing 100MHz to 1Hz/2Hz frequency dividers.
- Safety Protocols: Immediate door-lock engagement with a delayed 1-minute release post-centrifuge.
- Board: Digilent Nexys A7-100T (Artix-7 FPGA)
- Language: VHDL
- Toolchain: AMD Xilinx Vivado
/src- Contains all 27 VHDL modules.WASH_TOP.xdc- Constraints file for Nexys A7 hardware mapping.Hardware_Architecture_Spec.pdf- The 38-page comprehensive engineering spec.ORGANIGRAMA.svg- System architecture block diagram.
- Developed as a two-person joint academic project, with responsibilities shared across system architecture, datapath components, FSM design, and documentation.