I'm Ashish Kumar Kashyap, an Electronics & Communication Engineering student at MNNIT Allahabad with a strong interest in digital hardware, RTL design, FPGA architectures, and VLSI.
I enjoy understanding how digital systems work at the hardware level and turning those concepts into working RTL designs.
- 🔹 RTL Design
- 🔹 Verilog HDL
- 🔹 FPGA Architecture
- 🔹 Digital System Design
- 🔹 Memory Architectures
- 🔹 Computer Architecture
- 🔹 VLSI Design
An industrial-style asynchronous dual-port RAM subsystem designed using modular Verilog RTL.
- True Dual-Port RAM architecture
- Independent memory ports
- Independent clock domains
- Synchronizer circuits
- Collision detection
- VALID/READY handshake
- FPGA BRAM-friendly RTL
- Parameterized data width and memory depth
- Modular RTL hierarchy
- Simulation testbench
Memory Fundamentals
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Single-Port RAM
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Dual-Port RAM
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True Dual-Port RAM
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Collision Detection
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Synchronizer Circuits
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FPGA BRAM Inference
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Industrial RTL Architecture