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feat(pmu): Supp. C.a EXT64 layout & event filters - #695
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chetan-rathore merged 1 commit intoNov 11, 2026
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chetan-rathore merged 1 commit into
chetan-rathore merged 1 commit into
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- Decode PMDEVARCH per PMU node to select the C.a CoreSight PMU register layout. Preserve EXT32 support while enabling EXT64 offsets and 64-bit register access for ARCHPART 0xAF4/0xAF5/0xAF6. - Cache the EXT64 model during PMU table creation so register helpers do not reread PMDEVARCH on every access. Keep event IDs 32-bit, retain 64-bit monitor count validation for EXT64 counter values, and bound PMU event-list lookup to avoid out-of-range scans. - Add a PAL event-filter hook so platforms can provide implementation-defined PMEVFILTRn mask/value programming. VAL saves and restores the previous filter state around monitor configuration, allowing platform requirements such as byte-count TC=INCR_BY_VAL without hardcoding filter fields in common VAL. - Add coverage for unsupported PMU event configuration. Signed-off-by: Chetan Singh <chetan.singh2@arm.com> Change-Id: Ib001a85ed6894a8c82b05fad2f1f6b1476ce2378
chetan-rathore
merged commit Nov 11, 2026
001aa3e
into
ARM-software:release/sbsa/v8.0.4
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Change-Id: Ib001a85ed6894a8c82b05fad2f1f6b1476ce2378