From 1d8610779fade76c4269cfa8440cc927ed1fa4fb Mon Sep 17 00:00:00 2001
From: jgeorge1316 <137907302+jgeorge1316@users.noreply.github.com>
Date: Thu, 10 Sep 2026 10:05:36 -0400
Subject: [PATCH 1/2] Update vorago_va416x0.config

Header size increased for proper vector table alignment.
---
 config/examples/vorago_va416x0.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/config/examples/vorago_va416x0.config b/config/examples/vorago_va416x0.config
index ba223fb2ab..9e851d4217 100644
--- a/config/examples/vorago_va416x0.config
+++ b/config/examples/vorago_va416x0.config
@@ -5,7 +5,7 @@ TARGET?=va416x0
 # ECDSA P384 and SHA384
 SIGN?=ECC384
 HASH?=SHA384
-IMAGE_HEADER_SIZE=512
+IMAGE_HEADER_SIZE=1024
 
 # ML-DSA Level 5 (87)
 #SIGN=ML_DSA

From f01c9e40b9b10bebc156cdc9ee2c10aad435e456 Mon Sep 17 00:00:00 2001
From: jgeorge1316 <137907302+jgeorge1316@users.noreply.github.com>
Date: Thu, 10 Sep 2026 10:22:47 -0400
Subject: [PATCH 2/2] Update Vorago VA416x0 in Targets.md

Update documentation to reflect changes for vector table alignment.
---
 docs/Targets.md | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/docs/Targets.md b/docs/Targets.md
index 526374ed80..033e98bef0 100644
--- a/docs/Targets.md
+++ b/docs/Targets.md
@@ -8691,11 +8691,13 @@ Default flash layout:
 
 | Partition   | Size  | Address | Description |
 |-------------|-------|---------|-------------|
-| Bootloader  | 38KB  | 0x0     | Bootloader partition |
-| Application | 108KB | 0x9800  | Boot partition |
-| Update      | 108KB | 0x24800 | Update partition |
+| Bootloader  | 46KB  | 0x0     | Bootloader partition |
+| Application | 104KB | 0xB800  | Boot partition |
+| Update      | 104KB | 0x25800 | Update partition |
 | Swap        | 2KB   | 0x3F800 | Swap area |
 
+**Note**: To address vector table alignment requirements, the default image header size (IMAGE_HEADER_SIZE) has been increased to 1024 bytes. Alternatively, the SWAP partition size (WOLFBOOT_SECTOR_SIZE) can be reduced and partition addresses can be adjusted to ensure that the application address is aligned to a 256-word (1024 byte) boundary.
+
 SRAM: 64KB on-chip SRAM and 256KB on-chip instruction/program memory
 
 Boot ROM loads at 20MHz from SPI bus to internal data SRAM.