diff --git a/.github/workflows/regression.yml b/.github/workflows/regression.yml
new file mode 100644
index 0000000..08e18fb
--- /dev/null
+++ b/.github/workflows/regression.yml
@@ -0,0 +1,39 @@
+# Report-only regression tests (not a required check; never gates merges).
+# Harness: tests/regression, from Test Lab's Si5351 regression suite.
+name: Regression tests (report-only)
+
+on:
+  pull_request:
+  push:
+    branches-ignore: [master]
+  workflow_dispatch:
+
+permissions:
+  contents: read
+
+jobs:
+  regression:
+    runs-on: ubuntu-latest
+    timeout-minutes: 20
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: '3.x'
+      - name: Run regression harness (native g++ against src/si5351.cpp)
+        working-directory: tests/regression
+        run: ./run_v231_checks.sh --src "$GITHUB_WORKSPACE" --out "$RUNNER_TEMP/regression"
+      - name: Summary
+        if: always()
+        run: |
+          if [ -f "$RUNNER_TEMP/regression/summary.md" ]; then
+            cat "$RUNNER_TEMP/regression/summary.md" | tee -a "$GITHUB_STEP_SUMMARY"
+          fi
+      - uses: actions/upload-artifact@v4
+        if: always()
+        with:
+          name: regression-results
+          path: |
+            ${{ runner.temp }}/regression/summary.*
+            ${{ runner.temp }}/regression/results.tsv
+            ${{ runner.temp }}/regression/logs/
diff --git a/tests/README.md b/tests/README.md
new file mode 100644
index 0000000..754ca3a
--- /dev/null
+++ b/tests/README.md
@@ -0,0 +1,11 @@
+# Tests
+
+`regression/` is the Si5351 regression harness written by Test Lab (an agent working for Jason Milldrum, NT7S),
+ported unchanged from its working copy. It compiles `src/si5351.cpp` natively with g++ against host
+Arduino/Wire stubs and checks register output against golden cases, AN619/datasheet oracles, and the
+v2.3.1 acceptance scenarios. See `regression/README.md`.
+
+Run locally: `cd tests/regression && ./run_v231_checks.sh --src ../..`
+
+In CI (`.github/workflows/regression.yml`) it is **report-only**: not a required check, never gates merges.
+In default mode, the 25 v2.3.1 acceptance tests are expected to XFAIL on master (they are bugs v2.3.1 fixes).
diff --git a/tests/regression/README.md b/tests/regression/README.md
new file mode 100644
index 0000000..9d2eaa3
--- /dev/null
+++ b/tests/regression/README.md
@@ -0,0 +1,53 @@
+# Si5351Arduino v2.3.1 pre-review checks (`run_v231_checks.sh`)
+
+One self-contained, repeatable entry point for the v2.3.1 acceptance suite and the regression locks.
+Everything it needs is vendored here: no `/workspace` paths and no network access except the optional
+read-only git fetch and arduino-cli core installs. It never commits, pushes, or writes to the library repo.
+Library sources are always pinned with `git archive` (or copied, for a plain tree) into `<out>/lib`.
+
+## Requirements
+bash, git, tar, g++ (or `CXX=clang++`) with C++17, python3 (3.8+, standard library only).
+Optional: `arduino-cli` (≥1.0) for `--cores`; it is looked up as `$ARDUINO_CLI`, then `~/bin/arduino-cli`, then `PATH`.
+User-level install: `curl -fsSL https://raw.githubusercontent.com/arduino/arduino-cli/master/install.sh | BINDIR=~/bin sh`
+
+## Usage
+```
+./run_v231_checks.sh                                  # etherkit/Si5351Arduino master HEAD (read-only shallow fetch)
+./run_v231_checks.sh --ref abf9b2a                    # any branch/tag/SHA from upstream (GitHub serves SHAs)
+./run_v231_checks.sh --repo https://github.com/<fork>/Si5351Arduino.git --ref twowire-bus-select
+./run_v231_checks.sh --src ~/src/Si5351Arduino --ref v2.3.1-fixes   # a local clone; ref archived, clone untouched
+./run_v231_checks.sh --src ~/src/Si5351Arduino        # local clone at HEAD (committed state; uncommitted edits are flagged, not tested)
+./run_v231_checks.sh --src /path/to/tree              # plain source tree (src/si5351.{cpp,h} or si5351.{cpp,h})
+./run_v231_checks.sh --require-fixed ...              # v2.3.1 gate: all 25 acceptance tests must PASS
+./run_v231_checks.sh --cores                          # + arduino-cli compiles on all 9 boards (installs missing cores into ~/.arduino15)
+./run_v231_checks.sh --cores uno,esp32 --out /tmp/r1  # subset of boards, explicit output dir
+```
+Exit code: 0 = every check PASS/XFAIL/SKIP/INFO; 1 = at least one unexpected FAIL; 2 = usage/setup error.
+
+## What runs
+| Check | What | Gating |
+|---|---|---|
+| `build_acceptance`, `run_acceptance` | `v231/acceptance.cpp` + `scenarios_v231.inc` (per-scenario fork, so SIGFPE is recorded) compiled with the host compiler against the pinned source and the Wire stub | yes |
+| `acceptance_A01..A25` | `v231/test_v231.py` AN619/datasheet oracle. **Default mode: a failing test is XFAIL** (master is expected to fail all 25). `--require-fixed`: a failing test is FAIL | per mode |
+| `must_not_break` | 776 register/state/return/reg177 locks from `v231/must_not_break.json` | yes |
+| `t106_twowire` | issue #106 TwoWire bus-selection test (`issue106/t106.cpp`, multi-bus stub). SKIP when the source has no `TwoWire*` constructor | yes |
+| `goldens27_vs_lib` | C++ equivalence harness (`equiv/harness.cpp`) on the pinned source vs the 27 original golden cases | yes (INFO under `--require-fixed`) |
+| `equiv_vs_master_1ddd43e` | Full harness transcript diff against vendored master 1ddd43e (`reference/`). 0 means behaviourally identical | INFO |
+| `goldens_newer_vs_lib` | Newer `lib_*` golden register maps | INFO |
+| `py_test_golden`, `py_test_spec` | Python golden/spec suites: self-consistency of the AN619 oracle and goldens used above (library-independent) | yes |
+| `cxx98_syntax` | `-std=c++98 -pedantic -fsyntax-only` warning count | INFO |
+| `compile_<board>_<sketch>` (`--cores`) | arduino-cli `--warnings all` compile of `si5351_example`, `si5351_vcxo` and (TwoWire sources only) `sketches/Ctor106` on `boards.txt`. A vcxo `get_correction` error in default mode is XFAIL (known v2.3.0 example bug, fixed in 2.4.0) | yes |
+
+## Notes
+- Version-manager shims (mise, asdf, pyenv) on `PATH` can make cores that call `python3` during the build (esp8266, rp2040) fail with a "shim fallback recursion" error. When a real `python3` is still reachable without them, the script runs arduino-cli with those shim directories removed from `PATH`.
+- Cores are installed per user into `~/.arduino15`. Nothing is installed system-wide and sudo is never used.
+
+## Output (`--out`, default `./runs/run_<date>_<time>_<pid>`)
+`summary.md`, `summary.json` (overall, pinned SHA, source, mode, UTC timestamps, host and toolchain, per-check status/detail/log),
+`results.tsv`, `meta.env`, `PINNED_SHA`, `PINNED_SHA256SUMS`, `logs/` (build logs, JSONL transcripts, test logs, compile logs), `lib/` (pinned tree), `build/`.
+
+## Layout
+`v231/` acceptance runner, scenarios, oracle, locks, and reports · `stubs/` Arduino/Wire host stubs · `issue106/` t106 and its multi-bus stubs ·
+`equiv/` harness, goldens snapshot, compare.py · `reference/master_1ddd43e/` reference source · `python/` golden/spec suites and refs ·
+`sketches/` Ctor106 · `boards.txt` board set and Boards Manager URLs · `tools/summarize.py`.
+`v231/Makefile` is the original manual build, kept for reference only; the script does not use it.
diff --git a/tests/regression/boards.txt b/tests/regression/boards.txt
new file mode 100644
index 0000000..d98365d
--- /dev/null
+++ b/tests/regression/boards.txt
@@ -0,0 +1,14 @@
+# key|fqbn|core   (url| lines = additional Boards Manager URLs)
+url|https://espressif.github.io/arduino-esp32/package_esp32_index.json
+url|https://arduino.esp8266.com/stable/package_esp8266com_index.json
+url|https://github.com/stm32duino/BoardManagerFiles/raw/main/package_stmicroelectronics_index.json
+url|https://github.com/earlephilhower/arduino-pico/releases/download/global/package_rp2040_index.json
+uno|arduino:avr:uno|arduino:avr
+mega|arduino:avr:mega|arduino:avr
+nano_every|arduino:megaavr:nona4809|arduino:megaavr
+esp32|esp32:esp32:esp32|esp32:esp32
+esp8266|esp8266:esp8266:nodemcuv2|esp8266:esp8266
+bluepill|STMicroelectronics:stm32:GenF1:pnum=BLUEPILL_F103C8|STMicroelectronics:stm32
+nano33ble|arduino:mbed_nano:nano33ble|arduino:mbed_nano
+zero|arduino:samd:arduino_zero_native|arduino:samd
+pico|rp2040:rp2040:rpipico|rp2040:rp2040
diff --git a/tests/regression/equiv/compare.py b/tests/regression/equiv/compare.py
new file mode 100644
index 0000000..e6780b9
--- /dev/null
+++ b/tests/regression/equiv/compare.py
@@ -0,0 +1,180 @@
+#!/usr/bin/env python3
+"""Compare original vs refactored harness output and check goldens vs ORIGINAL C++."""
+import json, sys
+from pathlib import Path
+
+ROOT = Path(__file__).resolve().parent
+GOLDEN = ROOT / "logs/golden_cases.snapshot.json"   # pinned copy of /workspace/si5351-regression/golden_cases.json
+ORIG27 = json.loads((ROOT / "orig27_ids.json").read_text())
+ORIG_P = sys.argv[1] if len(sys.argv) > 1 else ROOT / "logs/orig.jsonl"
+REFAC_P = sys.argv[2] if len(sys.argv) > 2 else ROOT / "logs/refac.jsonl"
+REPORT_P = sys.argv[3] if len(sys.argv) > 3 else ROOT / "logs/compare_report.txt"
+orig = [json.loads(l) for l in open(ORIG_P)]
+refac = [json.loads(l) for l in open(REFAC_P)]
+report = []
+def say(s=""):
+    print(s); report.append(s)
+
+# ---------------- Task A.2: behavioural equivalence ----------------
+assert len(orig) == len(refac), (len(orig), len(refac))
+diffs = 0
+tx_events = 0
+for o, r in zip(orig, refac):
+    assert o["id"] == r["id"] and o["pattern"] == r["pattern"]
+    tx_events += len(o["tx"])
+    problems = []
+    if o["rets"] != r["rets"]:
+        problems.append(f"return codes differ: orig={o['rets']} refac={r['rets']}")
+    if o["tx"] != r["tx"]:
+        n = next((i for i, (a, b) in enumerate(zip(o["tx"], r["tx"])) if a != b), min(len(o["tx"]), len(r["tx"])))
+        last_call = next((o["tx"][j] for j in range(min(n, len(o["tx"]) - 1), -1, -1) if o["tx"][j].startswith("CALL")), "?")
+        problems.append(f"I2C transcript differs at event #{n} (during {last_call}): "
+                        f"orig={o['tx'][n] if n < len(o['tx']) else '<end>'} | refac={r['tx'][n] if n < len(r['tx']) else '<end>'}"
+                        f" (len orig={len(o['tx'])} refac={len(r['tx'])})")
+    rd = [(i, a, b) for i, (a, b) in enumerate(zip(o["regs"], r["regs"])) if a != b]
+    if rd:
+        problems.append("register file differs: " + ", ".join(f"reg{i}: orig=0x{a:02X} refac=0x{b:02X}" for i, a, b in rd[:12]))
+    if o["state"] != r["state"]:
+        problems.append(f"object state differs: orig={o['state']} refac={r['state']}")
+    if problems:
+        diffs += 1
+        say(f"DIFF {o['id']} (pattern {o['pattern']}):")
+        for p in problems: say("   " + p)
+
+ids = sorted({x["id"] for x in orig})
+n_g = len([i for i in ids if i.startswith("G:")]); n_x = len([i for i in ids if i.startswith("X:")]); n_f = len([i for i in ids if i.startswith("F:")]); n_n = len([i for i in ids if i.startswith("N:")]); n_h = len([i for i in ids if i.startswith("H:")])
+say(f"Equivalence: {len(ids)} scenarios ({n_g} from the 27 original goldens, {n_n} from newer lib_* goldens, {n_x} targeted P0/P1, {n_h} FreqChecks.ino hardware sequences, {n_f} seeded fuzz) x 2 register-file patterns "
+    f"= {len(orig)} runs, {tx_events} I2C/marker events compared; differing runs: {diffs}")
+
+# ---------------- Task A.3: goldens vs ORIGINAL C++ ----------------
+def decode(b):
+    p3 = (b[0] << 8) | b[1] | ((b[5] >> 4) << 16)
+    p1 = ((b[2] & 3) << 16) | (b[3] << 8) | b[4]
+    p2 = ((b[5] & 0xF) << 16) | (b[6] << 8) | b[7]
+    return p1, p2, p3
+def frac(a, b, c):
+    q = (128 * b) // c
+    return (128 * a + q - 512) & 0xFFFFFFFF, (128 * b - c * q) & 0xFFFFFFFF, c
+
+runs = {(x["id"], x["pattern"]): x for x in orig}
+gold = json.loads(GOLDEN.read_text())
+gfail, gchecks = [], 0
+def chk(cid, what, got, exp):
+    global gchecks
+    gchecks += 1
+    if got != exp: gfail.append(f"{cid}: {what}: C++ wrote {got}, golden says {exp}")
+
+def check_pll(cid, run, base, g, prefix="pll_"):
+    regs = run["regs"]
+    blk = regs[base:base + 8]
+    p = decode(blk)
+    chk(cid, f"PLL@{base} p1/p2/p3", p, (g[prefix + "p1"], g[prefix + "p2"], g[prefix + "p3"]))
+    if prefix + "a" in g:
+        chk(cid, f"PLL a/b/c -> p consistency", p, frac(g[prefix + "a"], g[prefix + "b"], g[prefix + "c"]))
+    if "pll_packed_bytes" in g:
+        chk(cid, f"PLL@{base} packed bytes", blk, g["pll_packed_bytes"])
+
+def check_ms05(cid, run, clk, g):
+    regs = run["regs"]; base = 42 + 8 * clk
+    blk = regs[base:base + 8]
+    p = decode(blk)
+    chk(cid, f"MS{clk} p1/p2/p3", p, (g["ms_p1"], g["ms_p2"], g["ms_p3"]))
+    exp_abc = (0, 0, 1) if g.get("div_by_4") else frac(g["ms_a"], g["ms_b"], g["ms_c"])
+    chk(cid, f"MS{clk} a/b/c -> p consistency", p, exp_abc)
+    if "ms_packed_bytes" in g:
+        chk(cid, f"MS{clk} packed bytes (excl. byte2)", blk[:2] + blk[3:], g["ms_packed_bytes"][:2] + g["ms_packed_bytes"][3:])
+    chk(cid, f"MS{clk} byte+2 (ms_div byte, reg {base+2})", blk[2], g["ms_div_byte"])
+    chk(cid, f"MS{clk} r_div field", (blk[2] >> 4) & 7, g["r_div"])
+    chk(cid, f"MS{clk} DIVBY4 field", (blk[2] >> 2) & 3, 3 if g["div_by_4"] else 0)
+    chk(cid, f"CLK{clk}_CTRL integer-mode bit", (regs[16 + clk] >> 6) & 1, g["int_mode"])
+
+def calls_after_last(run, name):
+    tx = run["tx"]; i = max(j for j, e in enumerate(tx) if e.startswith("CALL " + name))
+    return tx[i:]
+
+for g in [c for c in gold["cases"] if c["id"] in ORIG27]:
+    cid = g["id"]
+    if g["api"] == "parity_check":
+        a = runs[("G:" + cid + "#auto", 0)]; m = runs[("G:" + cid + "#manual", 0)]
+        if "auto_ms" in g:
+            for tag, run, ms in (("auto", a, g["auto_ms"]), ("manual", m, g["manual_ms"])):
+                p = decode(run["regs"][42:50])
+                chk(cid, f"{tag} MS0 p1/p2/p3", p, (ms["p1"], ms["p2"], ms["p3"]))
+                chk(cid, f"{tag} MS0 r_div", (run["regs"][44] >> 4) & 7, ms["r_div"])
+            chk(cid, "manual PLLA p1/p2/p3", decode(m["regs"][26:34]), (g["manual_pll"]["p1"], g["manual_pll"]["p2"], g["manual_pll"]["p3"]))
+        else:
+            for tag, run in (("auto", a), ("manual", m)):
+                check_ms05(cid + "#" + tag, run, 0, g[tag]); check_pll(cid + "#" + tag, run, 26, g[tag])
+        chk(cid, "auto vs manual MS0 bytes identical (ms_match)", a["regs"][42:50] == m["regs"][42:50], g["ms_match"])
+        if "pll_match" in g:
+            chk(cid, "auto vs manual PLLA bytes identical (pll_match)", a["regs"][26:34] == m["regs"][26:34], g["pll_match"])
+        continue
+    run = runs[("G:" + cid, 0)]
+    rets = run["rets"]
+    if g["api"] == "set_pll":   # reset baseline
+        check_pll(cid, run, 26, g); check_pll(cid, run, 34, g)
+        chk(cid, "pll_assignment after reset", run["state"]["pll_assignment"], [0]*6 + [1, 1])
+        continue
+    if g["api"] == "set_vcxo":
+        check_pll(cid, run, 34, g)
+        chk(cid, "VCXO regs 162-164", run["regs"][162:165], g["vcxo_bytes"])
+        continue
+    if g.get("clk_path") == "CLK6/7":
+        clk = 7 if "clk7" in cid else 6
+        if g.get("rejected"):
+            chk(cid, "set_freq return (reject)", rets[-1], "set_freq=1")
+            chk(cid, "clk_freq[7] untouched", run["state"]["clk_freq"][7], 0)
+            chk(cid, "no I2C writes after rejected call", [e for e in calls_after_last(run, "set_freq") if e.startswith("W ")], [])
+            continue
+        chk(cid, "set_freq return", rets[-1], "set_freq=0")
+        chk(cid, f"MS{clk} single byte reg {90 + clk - 6}", run["regs"][90 + clk - 6], g["clk67_ms_register_byte"])
+        r92 = run["regs"][92]
+        chk(cid, f"reg92 r_div field CLK{clk}", (r92 & 7) if clk == 6 else ((r92 >> 4) & 7), g["r_div"])
+        check_pll(cid, run, 34, g)
+        if "pll_freq_lib" in g: chk(cid, "pllb_freq state", run["state"]["pllb_freq"], g["pll_freq_lib"])
+        continue
+    # CLK0-5 set_freq / set_freq_manual
+    clk = 1 if cid in ("P0-clk1-PLLB-14MHz", "P0-manual-DIVBY4-175MHz-pll700") else 0
+    pll_base = 34 if (g.get("pll_assignment") == "PLLB" or clk == 1 or "vcxo" in cid) else 26
+    chk(cid, f"{g['api']} return", rets[-1], f"{g['api']}=0")
+    check_ms05(cid, run, clk, g)
+    check_pll(cid, run, pll_base, g)
+    if "pll_rewritten_by_set_correction" in g:
+        check_pll(cid + "[set_correction]", run, 26, g["pll_rewritten_by_set_correction"])
+    if g.get("pll_assignment") == "PLLB":
+        chk(cid, f"CLK{clk}_CTRL PLL_SELECT bit", (run["regs"][16 + clk] >> 5) & 1, 1)
+    if "pll_reset" in g:
+        did_reset = any(e.startswith("W a=60 r=177 ") for e in calls_after_last(run, g["api"]))
+        chk(cid, "pll_reset (reg 177 write) in this call", did_reset, g["pll_reset"])
+    if g.get("branch") == "recalc_pll_gt_100mhz":
+        chk(cid, "plla_freq state", run["state"]["plla_freq"], g["pll_freq_lib"])
+
+assert len([c for c in gold["cases"] if c["id"] in ORIG27]) == 27
+say(f"Goldens vs ORIGINAL C++: 27 original golden cases, {gchecks} field checks, {len(gfail)} mismatches")
+for f in gfail: say("   GOLDEN MISMATCH " + f)
+
+# ---------------- bonus: newer golden cases with lib_* register maps ----------------
+nfail, nchecks, ncases = [], 0, 0
+for g in gold["cases"]:
+    key = ("N:" + g["id"], 0)
+    if key not in runs: continue
+    ncases += 1
+    run = runs[key]; regs = run["regs"]
+    def nchk(what, got, exp):
+        global nchecks
+        nchecks += 1
+        if got != exp: nfail.append(f"{g['id']}: {what}: C++ wrote {got}, golden says {exp}")
+    for k, v in g.items():
+        if k in ("lib_plla_regs", "lib_pllb_regs", "lib_pll_regs", "lib_ms_regs", "lib_ms67_regs", "lib_clk_ctrl", "lib_vcxo_regs"):
+            for reg, val in v.items(): nchk(f"{k} reg{reg}", regs[int(reg)], val)
+        elif k == "lib_reg92": nchk("reg92", regs[92], v)
+        elif k == "lib_reg3_after": nchk("reg3 (output enable)", regs[3], v)
+        elif k == "lib_reg177_writes":
+            tx = run["tx"]; i = max(j for j, e in enumerate(tx) if e.startswith("CALL reset()"))
+            got = [int(e.split("[")[1].rstrip("]"), 16) for e in tx[i:] if e.startswith("W a=60 r=177 ")]
+            nchk("reg177 writes during reset()", got, v)
+say(f"Bonus - newer lib_* golden cases vs ORIGINAL C++: {ncases} cases, {nchecks} register checks, {len(nfail)} mismatches")
+for f in nfail: say("   NEW-GOLDEN MISMATCH " + f)
+
+Path(REPORT_P).write_text("\n".join(report) + "\n")
+sys.exit(1 if (diffs or gfail) else 0)  # bonus new-golden mismatches reported, not gating
diff --git a/tests/regression/equiv/golden_extra.inc b/tests/regression/equiv/golden_extra.inc
new file mode 100644
index 0000000..d931b9d
--- /dev/null
+++ b/tests/regression/equiv/golden_extra.inc
@@ -0,0 +1,24 @@
+// generated by gen_extra.py from /workspace/si5351-equiv/logs/golden_cases.snapshot.json
+  add("N:S-reset-pll-blocks-and-reg177", [] { init0(); mark("reset()"); S->reset(); });
+  add("N:S-ms5-block-10MHz-clk5", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(1000000000ULL, (enum si5351_clock)5)"); S->set_freq(1000000000ULL, (enum si5351_clock)5); });
+  add("N:S-rdiv-placement-clk2-5kHz", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(500000ULL, (enum si5351_clock)2)"); S->set_freq(500000ULL, (enum si5351_clock)2); });
+  add("N:S-divby4-block-clk3-200MHz", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(20000000000ULL, (enum si5351_clock)3)"); S->set_freq(20000000000ULL, (enum si5351_clock)3); });
+  add("N:S-boundary-112p5MHz-ratio8", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(11250000000ULL, (enum si5351_clock)0)"); S->set_freq(11250000000ULL, (enum si5351_clock)0); });
+  add("N:S-clk6-R6div-100kHz", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(10000000ULL, (enum si5351_clock)6)"); S->set_freq(10000000ULL, (enum si5351_clock)6); });
+  add("N:S-clk7-R7div-50kHz", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(5000000ULL, (enum si5351_clock)7)"); S->set_freq(5000000ULL, (enum si5351_clock)7); });
+  add("N:S-clk6-150MHz-upper-clamp", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(15000000000ULL, (enum si5351_clock)6)"); S->set_freq(15000000000ULL, (enum si5351_clock)6); });
+  add("N:S-vcxo-800MHz-100ppm", [] { init0(); mark("reset()"); S->reset(); mark("set_vcxo(80000000000ULL, 100)"); S->set_vcxo(80000000000ULL, 100); });
+  add("N:S-vcxo-ppm-clamp-low-10to30", [] { init0(); mark("reset()"); S->reset(); mark("set_vcxo(87600000000ULL, 10)"); S->set_vcxo(87600000000ULL, 10); });
+  add("N:S-vcxo-ppm-clamp-high-250to240", [] { init0(); mark("reset()"); S->reset(); mark("set_vcxo(87600000000ULL, 250)"); S->set_vcxo(87600000000ULL, 250); });
+  add("N:D-clk0-210MHz-above-spec-max", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(21000000000ULL, (enum si5351_clock)0)"); S->set_freq(21000000000ULL, (enum si5351_clock)0); });
+  add("N:D-clk0-250MHz-clamped-to-225", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(25000000000ULL, (enum si5351_clock)0)"); S->set_freq(25000000000ULL, (enum si5351_clock)0); });
+  add("N:D-clk0-2p5kHz-clamped-to-4kHz", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(250000ULL, (enum si5351_clock)0)"); S->set_freq(250000ULL, (enum si5351_clock)0); });
+  add("N:D-clk6-10kHz-ms6-p1-zero", [] { init0(); mark("reset()"); S->reset(); mark("set_freq(1000000ULL, (enum si5351_clock)6)"); S->set_freq(1000000ULL, (enum si5351_clock)6); });
+  add("N:D-manual-100MHz-pll700-ratio7", [] { init0(); mark("reset()"); S->reset(); mark("set_freq_manual(10000000000ULL, 70000000000ULL, (enum si5351_clock)0)"); S->set_freq_manual(10000000000ULL, 70000000000ULL, (enum si5351_clock)0); });
+  add("N:D-manual-90MHz-pll600-ratio6p67", [] { init0(); mark("reset()"); S->reset(); mark("set_freq_manual(9000000000ULL, 60000000000ULL, (enum si5351_clock)0)"); S->set_freq_manual(9000000000ULL, 60000000000ULL, (enum si5351_clock)0); });
+  add("N:D-manual-140MHz-pll700-stale-a5", [] { init0(); mark("reset()"); S->reset(); mark("set_freq_manual(14000000000ULL, 70000000000ULL, (enum si5351_clock)0)"); S->set_freq_manual(14000000000ULL, 70000000000ULL, (enum si5351_clock)0); });
+  add("N:D-manual-175MHz-pll800-divby4-precondition", [] { init0(); mark("reset()"); S->reset(); mark("set_freq_manual(17500000000ULL, 80000000000ULL, (enum si5351_clock)0)"); S->set_freq_manual(17500000000ULL, 80000000000ULL, (enum si5351_clock)0); });
+  add("N:D-vcxo-then-set_correction-clobbers-pllb", [] { init0(); mark("reset()"); S->reset(); mark("set_vcxo(87600000000ULL, 40)"); S->set_vcxo(87600000000ULL, 40); mark("set_correction(0, SI5351_PLL_INPUT_XO)"); S->set_correction(0, SI5351_PLL_INPUT_XO); });
+  add("N:D-vcxo-875MHz-then-manual-rewrites-c1", [] { init0(); mark("reset()"); S->reset(); mark("set_vcxo(87500000000ULL, 40)"); S->set_vcxo(87500000000ULL, 40); mark("set_ms_source(SI5351_CLK0, SI5351_PLLB)"); S->set_ms_source(SI5351_CLK0, SI5351_PLLB); mark("set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0)"); S->set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0); });
+  add("N:D-manual-clk7-87p4MHz-p1-truncated", [] { init0(); mark("reset()"); S->reset(); mark("set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7)"); S->set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7); });
+  add("N:D-set_int-clk6-sets-FBA_INT-on-fractional-plla", [] { init0(); mark("reset()"); S->reset(); mark("set_correction(100000, SI5351_PLL_INPUT_XO)"); S->set_correction(100000, SI5351_PLL_INPUT_XO); mark("set_int(SI5351_CLK6, 1)"); S->set_int(SI5351_CLK6, 1); });
diff --git a/tests/regression/equiv/harness.cpp b/tests/regression/equiv/harness.cpp
new file mode 100644
index 0000000..b7c38d0
--- /dev/null
+++ b/tests/regression/equiv/harness.cpp
@@ -0,0 +1,546 @@
+// Native host harness: drives the Si5351 library through identical call
+// sequences and emits, per scenario, the full I2C transcript, return codes,
+// final 256-byte register file and public object state as one JSON line.
+// Compiled twice: once against the pristine original, once against the refactor.
+#include "si5351.h"
+#include "sim.h"
+#include <new>
+#include <stdio.h>
+#include <stdarg.h>
+#include <string>
+#include <vector>
+#include <functional>
+#include <signal.h>
+#include <setjmp.h>
+static sigjmp_buf g_fpe_jb;
+static void on_fpe(int) { siglongjmp(g_fpe_jb, 1); }
+
+typedef unsigned long long ull;
+static const ull M = SI5351_FREQ_MULT;  // Hz -> library units
+
+alignas(Si5351) static unsigned char objbuf[sizeof(Si5351)];
+static Si5351 *S;
+static std::vector<std::string> RETS;
+
+static void mark(const char *fmt, ...) {
+  char b[160]; va_list ap; va_start(ap, fmt); vsnprintf(b, sizeof b, fmt, ap); va_end(ap);
+  g_sim.mark(b);
+}
+static void ret(const char *name, long long v) {
+  char b[96]; snprintf(b, sizeof b, "%s=%lld", name, v);
+  RETS.push_back(b); g_sim.events.push_back(std::string("RET ") + b);
+}
+
+// ---- API wrappers (mark call, run, record return) ----
+static bool init_(uint8_t load, uint32_t xo, int32_t corr) {
+  mark("init(%u,%u,%d)", load, xo, corr); bool r = S->init(load, xo, corr); ret("init", r); return r; }
+static void reset_() { mark("reset()"); S->reset(); }
+static uint8_t sf(ull f, int clk) {
+  mark("set_freq(%llu,CLK%d)", f, clk); uint8_t r = S->set_freq(f, (enum si5351_clock)clk); ret("set_freq", r); return r; }
+static uint8_t sfm(ull f, ull p, int clk) {
+  mark("set_freq_manual(%llu,%llu,CLK%d)", f, p, clk);
+  uint8_t r = S->set_freq_manual(f, p, (enum si5351_clock)clk); ret("set_freq_manual", r); return r; }
+static void spll(ull p, int pll) { mark("set_pll(%llu,PLL%c)", p, pll ? 'B' : 'A'); S->set_pll(p, (enum si5351_pll)pll); }
+static void sms(int clk, uint32_t p1, uint32_t p2, uint32_t p3, int im, int rd, int d4) {
+  mark("set_ms(CLK%d,{%u,%u,%u},%d,%d,%d)", clk, p1, p2, p3, im, rd, d4);
+  struct Si5351RegSet r; r.p1 = p1; r.p2 = p2; r.p3 = p3;
+  S->set_ms((enum si5351_clock)clk, r, im, rd, d4); }
+static void svcxo(ull p, int ppm) { mark("set_vcxo(%llu,%d)", p, ppm); S->set_vcxo(p, ppm); }
+static void corr_(int32_t c, int ref) { mark("set_correction(%d,%d)", c, ref); S->set_correction(c, (enum si5351_pll_input)ref); }
+static void mssrc(int clk, int pll) { mark("set_ms_source(CLK%d,PLL%c)", clk, pll ? 'B' : 'A'); S->set_ms_source((enum si5351_clock)clk, (enum si5351_pll)pll); }
+static void oe(int clk, int en) { mark("output_enable(CLK%d,%d)", clk, en); S->output_enable((enum si5351_clock)clk, en); }
+static void pllin(int pll, int in) { mark("set_pll_input(%d,%d)", pll, in); S->set_pll_input((enum si5351_pll)pll, (enum si5351_pll_input)in); }
+static void reff(uint32_t f, int ref) { mark("set_ref_freq(%u,%d)", f, ref); S->set_ref_freq(f, (enum si5351_pll_input)ref); }
+static void pllrst(int pll) { mark("pll_reset(%d)", pll); S->pll_reset((enum si5351_pll)pll); }
+static void sph(int clk, int ph) { mark("set_phase(CLK%d,%d)", clk, ph); S->set_phase((enum si5351_clock)clk, ph); }
+static void sint(int clk, int en) { mark("set_int(CLK%d,%d)", clk, en); S->set_int((enum si5351_clock)clk, en); }
+static void drv(int clk, int d) { mark("drive_strength(CLK%d,%d)", clk, d); S->drive_strength((enum si5351_clock)clk, (enum si5351_drive)d); }
+// Si5351_FreqChecks.ino: one check = [reset(); allOff();] drive_strength(8mA); set_freq(f*100); output_enable(clk,1)
+static const struct { ull hz; int clk; } FC[12] = {
+  {10000000ULL,0},{14070000ULL,0},{28000000ULL,0},{100000000ULL,0},{112500000ULL,0},{150000000ULL,0},
+  {200000000ULL,0},{210000000ULL,0},{512000ULL,0},{4000ULL,0},{23000000ULL,6},{87400000ULL,7}};
+static void fc_check(int i) {
+  mark("FreqCheck #%d", i + 1);
+  if (FC[i].clk != 7) { reset_(); for (int c = 0; c < 8; c++) oe(c, 0); }
+  drv(FC[i].clk, SI5351_DRIVE_8MA);
+  sf(FC[i].hz * 100ULL, FC[i].clk);
+  oe(FC[i].clk, 1);
+}
+static void misc_smoke() {
+  mark("misc_smoke");
+  S->drive_strength(SI5351_CLK2, SI5351_DRIVE_8MA);
+  S->set_phase(SI5351_CLK1, 0xFF);
+  S->set_int(SI5351_CLK3, 1);
+  S->set_clock_pwr(SI5351_CLK4, 0);
+  S->set_clock_invert(SI5351_CLK5, 1);
+  S->set_clock_source(SI5351_CLK1, SI5351_CLK_SRC_MS0);
+  S->set_clock_disable(SI5351_CLK6, SI5351_CLK_DISABLE_HI_Z);
+  S->set_clock_fanout(SI5351_FANOUT_XO, 1);
+  S->update_status();
+  ret("get_correction0", S->get_correction(SI5351_PLL_INPUT_XO));
+}
+static const uint8_t LOAD = SI5351_CRYSTAL_LOAD_8PF;
+// ---- Si5351_Issue65_Verify.ino replica ----
+static void hv_fresh() { reset_(); for (int c = 0; c < 8; c++) oe(c, 0); for (int c = 0; c < 6; c++) drv(c, SI5351_DRIVE_8MA); }
+static void hv_dump(int clk) { mark("dump(CLK%d)", clk); S->update_status(); S->si5351_read(16 + clk); S->si5351_read(44 + 8 * clk);
+  S->si5351_read(44 + 8 * clk); S->si5351_read(3); }
+static void hv_step(int s) {
+  mark("STEP %d", s);
+  switch (s) {
+  case 1: hv_fresh(); sf(21000000000ULL, 0); oe(0, 1); hv_fresh(); sf(51200000ULL, 0); oe(0, 1); hv_dump(0); break;
+  case 2: hv_fresh(); oe(0, 1); sf(8000000000ULL, 0); sf(15600000000ULL, 0); sf(8000000000ULL, 0); hv_dump(0); break;
+  case 3: hv_fresh(); oe(0, 1); sf(15500000000ULL, 0); sf(9600000000ULL, 0); hv_dump(0); break;
+  case 4: hv_fresh(); oe(0, 1); sf(20000000000ULL, 0); sf(1000000000ULL, 0); hv_dump(0); break;
+  case 5: hv_fresh(); mssrc(1, 1); oe(1, 1); sf(16000000000ULL, 1); sf(1400000000ULL, 1); hv_dump(1); break;
+  case 6: hv_fresh(); oe(2, 1); sfm(17500000000ULL, 70000000000ULL, 2); sfm(1400000000ULL, 80000000000ULL, 2); hv_dump(2); break;
+  case 7: hv_fresh(); oe(0, 1); for (ull i = 0; i <= 1000; i++) sf((7000000ULL + 10ULL * i) * 100ULL, 0); hv_dump(0); break;
+  case 8: hv_fresh(); oe(0, 1); oe(2, 1); sf(15500000000ULL, 0); sf(9900000000ULL, 2); hv_dump(2); break;
+  }
+}
+
+static void init0() { init_(LOAD, 0, 0); }
+
+// ---- Si5351_Issue65_Verify.ino v2 replica (steps with controls); keep in sync with the sketch ----
+static const char *HV2_NAMES[] = {"1","2","3","4","5c1","5c2","5","5x","6c","6","6x","7","8","9"};
+static const int HV2_N = 14;
+static void hv2_dump(int clk) { mark("dump(CLK%d)", clk); S->update_status(); S->si5351_read(3); S->si5351_read(16 + clk); }
+static void hv2_step(int s) {
+  mark("STEP %s", HV2_NAMES[s]);
+  int clk = 0;
+  switch (s) {
+  case 0: hv_fresh(); sf(21000000000ULL, 0); oe(0, 1); hv_fresh(); sf(51200000ULL, 0); oe(0, 1); break;
+  case 1: hv_fresh(); oe(0, 1); sf(8000000000ULL, 0); sf(15600000000ULL, 0); sf(8000000000ULL, 0); break;
+  case 2: hv_fresh(); oe(0, 1); sf(15500000000ULL, 0); sf(9600000000ULL, 0); break;
+  case 3: hv_fresh(); oe(0, 1); sf(20000000000ULL, 0); sf(1000000000ULL, 0); break;
+  case 4: clk = 1; hv_fresh(); oe(1, 1); sf(1400000000ULL, 1); break;                                   // control: CLK1, PLLA, no DIVBY4
+  case 5: clk = 1; hv_fresh(); mssrc(1, 1); oe(1, 1); sf(1400000000ULL, 1); break;                      // control: CLK1, PLLB, no DIVBY4
+  case 6: clk = 1; hv_fresh(); mssrc(1, 1); oe(1, 1); sf(16000000000ULL, 1); sf(1400000000ULL, 1); break;
+  case 7: clk = 0; hv_fresh(); mssrc(0, 1); oe(0, 1); sf(16000000000ULL, 0); sf(1400000000ULL, 0); break; // step 5 on CLK0
+  case 8: clk = 2; hv_fresh(); oe(2, 1); sfm(1400000000ULL, 80000000000ULL, 2); break;                 // control: CLK2 manual
+  case 9: clk = 2; hv_fresh(); oe(2, 1); sfm(17500000000ULL, 70000000000ULL, 2); sfm(1400000000ULL, 80000000000ULL, 2); break;
+  case 10: clk = 0; hv_fresh(); oe(0, 1); sfm(17500000000ULL, 70000000000ULL, 0); sfm(1400000000ULL, 80000000000ULL, 0); break; // step 6 on CLK0
+  case 11: hv_fresh(); oe(0, 1); for (ull i = 0; i <= 1000; i++) sf((7000000ULL + 10ULL * i) * 100ULL, 0); break;
+  case 12: clk = 2; hv_fresh(); oe(0, 1); oe(2, 1); sf(15500000000ULL, 0); sf(9900000000ULL, 2); break;
+  case 13: hv_fresh(); oe(0, 1); sf(12000000000ULL, 0); break;                                          // 120 MHz: MS ratio 6, MS_INT=0
+  }
+  hv2_dump(clk);
+}
+
+// ---- Si5351_Issue65_Verify.ino v3 replica: steps + list of clocks to probe/check; keep in sync with gen_verify_sketch.py ----
+struct HV3 { const char *name; int clks[3]; };
+static const HV3 HV3S[] = {
+  {"1",{0,-1,-1}}, {"2",{0,-1,-1}}, {"3",{0,-1,-1}}, {"4",{0,-1,-1}}, {"5c1",{1,-1,-1}}, {"5c2",{1,-1,-1}}, {"5",{1,-1,-1}},
+  {"5x",{0,-1,-1}}, {"6c",{2,-1,-1}}, {"6",{2,-1,-1}}, {"6x",{0,-1,-1}}, {"7",{0,-1,-1}}, {"8",{2,0,-1}}, {"9",{0,-1,-1}},
+  {"10",{2,1,0}}, {"11",{2,0,-1}}, {"12",{2,0,-1}}, {"13",{2,0,-1}}, {"14",{0,-1,-1}}, {"15",{2,1,0}}};
+static const int HV3_N = sizeof(HV3S) / sizeof(HV3S[0]);
+static void hv3_step(int s) {
+  mark("STEP %s", HV3S[s].name);
+  switch (s) {
+  case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11: case 13:
+    { int map2[] = {0,1,2,3,4,5,6,7,8,9,10,11,-1,13}; int s2 = map2[s];
+      // reuse v2 sequences without their dump
+      switch (s2) {
+      case 0: hv_fresh(); sf(21000000000ULL, 0); oe(0, 1); hv_fresh(); sf(51200000ULL, 0); oe(0, 1); break;
+      case 1: hv_fresh(); oe(0, 1); sf(8000000000ULL, 0); sf(15600000000ULL, 0); sf(8000000000ULL, 0); break;
+      case 2: hv_fresh(); oe(0, 1); sf(15500000000ULL, 0); sf(9600000000ULL, 0); break;
+      case 3: hv_fresh(); oe(0, 1); sf(20000000000ULL, 0); sf(1000000000ULL, 0); break;
+      case 4: hv_fresh(); oe(1, 1); sf(1400000000ULL, 1); break;
+      case 5: hv_fresh(); mssrc(1, 1); oe(1, 1); sf(1400000000ULL, 1); break;
+      case 6: hv_fresh(); mssrc(1, 1); oe(1, 1); sf(16000000000ULL, 1); sf(1400000000ULL, 1); break;
+      case 7: hv_fresh(); mssrc(0, 1); oe(0, 1); sf(16000000000ULL, 0); sf(1400000000ULL, 0); break;
+      case 8: hv_fresh(); oe(2, 1); sfm(1400000000ULL, 80000000000ULL, 2); break;
+      case 9: hv_fresh(); oe(2, 1); sfm(17500000000ULL, 70000000000ULL, 2); sfm(1400000000ULL, 80000000000ULL, 2); break;
+      case 10: hv_fresh(); oe(0, 1); sfm(17500000000ULL, 70000000000ULL, 0); sfm(1400000000ULL, 80000000000ULL, 0); break;
+      case 11: hv_fresh(); oe(0, 1); for (ull i = 0; i <= 1000; i++) sf((7000000ULL + 10ULL * i) * 100ULL, 0); break;
+      case 13: hv_fresh(); oe(0, 1); sf(12000000000ULL, 0); break;
+      } } break;
+  case 12: hv_fresh(); oe(0, 1); oe(2, 1); sf(15500000000ULL, 0); sf(9900000000ULL, 2); break;            // #65 3rd: CLK2 moves to PLLB
+  case 14: hv_fresh(); mssrc(1, 1); oe(0, 1); oe(1, 1); oe(2, 1); sf(1400000000ULL, 1);                  // PLLB shared with CLK1 14 MHz: reused
+           sf(15500000000ULL, 0); sf(9900000000ULL, 2); break;
+  case 15: hv_fresh(); spll(60000000000ULL, 1); oe(0, 1); oe(2, 1); sf(15500000000ULL, 0); sf(9900000000ULL, 2); break; // PLLB free but 600: re-planned
+  case 16: hv_fresh(); oe(2, 1); sf(16000000000ULL, 2); hv_fresh(); oe(0, 1); oe(2, 1);                  // move + DIVBY4 exit
+           sf(15500000000ULL, 0); sf(9900000000ULL, 2); break;
+  case 17: hv_fresh(); oe(0, 1); oe(2, 1); sf(15500000000ULL, 0); sf(9900000000ULL, 2); sf(1000000000ULL, 0); // back and forth
+           sf(9800000000ULL, 2); sf(16000000000ULL, 0); sf(9700000000ULL, 2); break;
+  case 18: hv_fresh(); oe(0, 1); sf(20000000000ULL, 0); sf(11000000000ULL, 0); break;                    // single reset (dedupe)
+  case 19: hv_fresh(); mssrc(1, 1); oe(0, 1); oe(1, 1); oe(2, 1); sf(16000000000ULL, 1);                 // both PLLs held: fallback
+           sf(15500000000ULL, 0); sf(9900000000ULL, 2); break;
+  }
+  for (int j = 0; j < 3 && HV3S[s].clks[j] >= 0; j++) { mark("dump(CLK%d)", HV3S[s].clks[j]); S->update_status(); S->si5351_read(3); S->si5351_read(16 + HV3S[s].clks[j]); }
+}
+
+// ---- deterministic PRNG for fuzz ----
+static ull rng_state;
+static ull rnd() { ull z = (rng_state += 0x9E3779B97F4A7C15ULL);
+  z = (z ^ (z >> 30)) * 0xBF58476D1CE4E5B9ULL; z = (z ^ (z >> 27)) * 0x94D049BB133111EBULL; return z ^ (z >> 31); }
+static ull rr(ull lo, ull hi) { return lo + rnd() % (hi - lo + 1); }
+
+static std::vector<ull> edge_freqs() {
+  std::vector<ull> v;
+  ull t[] = {400000ULL, 1845400ULL};  // CLKOUT_MIN*100, CLKOUT67_MIN*100
+  for (ull base : t) for (int k = 0; k <= 7; k++) { ull e = base << k; v.push_back(e - 1); v.push_back(e); v.push_back(e + 1); }
+  ull more[] = {1, 399999, 50000000ULL, 51200000ULL, 10000000000ULL - 1, 10000000000ULL, 10000000001ULL,
+                15000000000ULL - 1, 15000000000ULL, 15000000001ULL, 22500000000ULL, 22500000001ULL,
+                1400000000ULL, 1407400000ULL, 2300000000ULL, 8740000000ULL, 11200000000ULL};
+  for (ull m : more) v.push_back(m);
+  return v;
+}
+static ull rand_freq(bool clk67) {
+  static std::vector<ull> E = edge_freqs();
+  ull f;
+  if (rnd() % 3 == 0) f = E[rnd() % E.size()];
+  else { // log-uniform 1 kHz .. 250 MHz
+    double lo = 3.0, hi = 8.4, x = lo + (hi - lo) * (double)(rnd() % 1000000) / 1e6;
+    f = (ull)(__builtin_pow(10.0, x) * 100.0);
+  }
+  if (f == 0) f = 1;
+  (void)clk67;
+  return f;
+}
+static void fuzz_seq(ull seed, int n_ops) {
+  rng_state = seed;
+  init_(LOAD, (rnd() % 4 == 0) ? 27000000 : 0, (rnd() % 3 == 0) ? (int32_t)rr(0, 400000) - 200000 : 0);
+  for (int i = 0; i < n_ops; i++) {
+    int op = rnd() % 100;
+    if (op < 45) sf(rand_freq(false), rnd() % 8);
+    else if (op < 58) sfm(rand_freq(false), rr(55000, 95000) * 1000000ULL, rnd() % 8);
+    else if (op < 66) mssrc(rnd() % 8, rnd() % 2);
+    else if (op < 72) corr_((int32_t)rr(0, 400000) - 200000, rnd() % 2);
+    else if (op < 77) svcxo(rr(60000, 90000) * 1000000ULL, (int)rr(0, 300));
+    else if (op < 82) spll(rr(55000, 95000) * 1000000ULL, rnd() % 2);
+    else if (op < 89) sms(rnd() % 8, rnd() & 0x3FFFF, rnd() & 0xFFFFF, (rnd() & 0xFFFFF) | 1, rnd() % 2, rnd() % 8, rnd() % 2);
+    else if (op < 93) oe(rnd() % 8, rnd() % 2);
+    else if (op < 95) reset_();
+    else if (op < 97) pllrst(rnd() % 2);
+    else { reff(rnd() % 2 ? 25000000 : (uint32_t)rr(10000000, 100000000), 1); pllin(rnd() % 2, rnd() % 2); }
+  }
+}
+
+// ---- scenarios ----
+struct Scn { std::string id; std::function<void()> fn; bool present; };
+static std::vector<Scn> SC;
+static void add(const std::string &id, std::function<void()> fn, bool present = true) { SC.push_back({id, fn, present}); }
+
+static void build() {
+  // ===== Golden cases (golden_cases.json, 27 ids) =====
+  struct { const char *id; ull f; int32_t corr; } g05[] = {
+    {"P0-clk0-common-1-14MHz", 14000000, 0}, {"P0-clk0-common-2-10MHz", 10000000, 0},
+    {"P0-clk0-common-3-7MHz", 7000000, 0}, {"P0-clk0-common-4-28MHz", 28000000, 0},
+    {"P0-clk0-integer-MS-16MHz", 16000000, 0}, {"P0-clk0-fractional-MS-14p07MHz", 14070000, 0},
+    {"P0-clk0-gt100MHz-recalc-pll-112MHz", 112000000, 0}, {"P0-clk0-DIVBY4-boundary-150MHz", 150000000, 0},
+    {"P0-clk0-DIVBY4-200MHz", 200000000, 0}, {"P0-corr-100000-14MHz-existing-pll", 14000000, 100000},
+    {"P0-corr--50000-14MHz-existing-pll", 14000000, -50000}, {"P0-corr-100000-gt100MHz-112MHz", 112000000, 100000},
+    {"P0-rdiv-128-5kHz", 5000, 0}, {"P0-rdiv-64-10kHz", 10000, 0}, {"P0-rdiv-8-100kHz", 100000, 0},
+    {"P0-rdiv-2-400kHz", 400000, 0}, {"P0-rdiv-1-512kHz-boundary", 512000, 0},
+  };
+  for (auto &g : g05) { ull f = g.f * M; int32_t c = g.corr; add(std::string("G:") + g.id, [f, c] { init_(LOAD, 0, c); sf(f, 0); }); }
+  add("G:P0-manual-DIVBY4-175MHz-pll700", [] { init0(); mssrc(1, 1); sfm(175000000 * M, 700000000 * M, 1); });
+  add("G:P0-clk1-PLLB-14MHz", [] { init0(); mssrc(1, 1); sf(14000000 * M, 1); });
+  add("G:P0-clk6-23MHz", [] { init0(); sf(23000000 * M, 6); });
+  add("G:P0-clk7-874MHz-even-div-of-clk6-pll", [] { init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); });
+  add("G:P0-clk7-reject-noninteger-12p345678MHz", [] { init0(); sf(23000000 * M, 6); sf(12345678 * M, 7); });
+  add("G:P0-vcxo-876MHz-40ppm", [] { init0(); svcxo(876000000 * M, 40); });
+  add("G:P0-vcxo-manual-146MHz-on-876pll", [] { init0(); svcxo(876000000 * M, 40); mssrc(0, 1); sfm(146000000 * M, 876000000 * M, 0); });
+  add("G:P1-parity-set_freq-vs-manual-14MHz-pll800#auto", [] { init0(); sf(14000000 * M, 0); });
+  add("G:P1-parity-set_freq-vs-manual-14MHz-pll800#manual", [] { init0(); sfm(14000000 * M, 800000000 * M, 0); });
+  add("G:P1-parity-gt100-set_freq-vs-manual-175MHz#auto", [] { init0(); sf(175000000 * M, 0); });
+  add("G:P1-parity-gt100-set_freq-vs-manual-175MHz#manual", [] { init0(); sfm(175000000 * M, 700000000 * M, 0); });
+  add("G:P1-reset-pll-fixed-800MHz", [] { init0(); });
+
+  // ===== Example sketches verbatim =====
+  add("X:example-si5351_example", [] { init0(); sf(1400000000ULL, 0); mssrc(1, 1); sfm(17500000000ULL, 70000000000ULL, 1); S->update_status(); });
+  add("X:example-clk67", [] { init0(); sf(1400000000ULL, 0); sf(2300000000ULL, 6); sf(1234567800ULL, 7); sf(8740000000ULL, 7); });
+  add("X:example-vcxo", [] { init0(); svcxo(87600000000ULL, 40); mssrc(0, 1); sfm(14600000000ULL, 87600000000ULL, 0); });
+
+  // ===== P1 multi-clock >100 MHz conflicts / share =====
+  add("X:conflict-clk1-gt100-same-pll", [] { init0(); sf(112000000 * M, 0); sf(120000000 * M, 1); });
+  add("X:conflict-clk1-gt100-other-pll-ok", [] { init0(); sf(112000000 * M, 0); mssrc(1, 1); sf(120000000 * M, 1); });
+  add("X:conflict-same-clk-twice-gt100", [] { init0(); sf(112000000 * M, 0); sf(130000000 * M, 0); });
+  add("X:share-peer-recalc", [] { init0(); sf(10000000 * M, 1); sf(7100000 * M, 2); sf(5000 * M, 3); sf(112000000 * M, 0); sf(14000000 * M, 4); });
+  add("X:share-peer-recalc-divby4", [] { init0(); sf(10000000 * M, 1); sf(160000000 * M, 0); sf(3000000 * M, 5); });
+  add("X:share-boundary-100MHz", [] { init0(); sf(100000000 * M, 0); sf(100000000 * M + 1, 1); sf(100000000 * M - 1, 2); });
+  add("X:share-pllb-gt100", [] { init0(); mssrc(2, 1); mssrc(3, 1); sf(20000000 * M, 3); sf(140000000 * M, 2); sf(110000000 * M, 0); });
+  add("X:all-six-clocks", [] { init0(); for (int c = 0; c < 6; c++) sf((ull)(1000000 + 3333333 * c) * M, c); });
+
+  // ===== DIVBY4 / bounds =====
+  add("X:divby4-edges", [] { init0(); sf(150000000 * M - 1, 0); sf(150000000 * M, 1); sf(150000000 * M + 1, 2); });
+  add("X:bounds-clk05", [] { init0(); sf(0, 0); sf(1, 1); sf(399999, 2); sf(400000, 3); sf(22500000000ULL, 4); sf(30000000000ULL, 5); });
+  add("X:bounds-manual", [] { init0(); sfm(1, 80000000000ULL, 0); sfm(30000000000ULL, 90000000000ULL, 1); sfm(16000000000ULL, 64000000000ULL, 2); });
+
+  // ===== R-div band edges (exact thresholds and +-1), CLK0-5 and CLK6/7 =====
+  for (int k = 0; k <= 7; k++) {
+    char id[64]; snprintf(id, sizeof id, "X:rdiv05-edge-k%d", k);
+    ull e = 400000ULL << k;
+    add(id, [e] { init0(); sf(e - 1, 0); sf(e, 1); sf(e + 1, 2); sfm(e - 1, 80000000000ULL, 3); sfm(e, 80000000000ULL, 4); sfm(e + 1, 87600000000ULL, 5); });
+    snprintf(id, sizeof id, "X:rdiv67-edge-k%d", k);
+    ull e7 = 1845400ULL << k;
+    add(id, [e7] { init0(); sf(e7 - 1, 6); });
+    snprintf(id, sizeof id, "X:rdiv67-edge-k%d-eq", k);
+    add(id, [e7] { init0(); sf(e7, 7); });
+    snprintf(id, sizeof id, "X:rdiv67-edge-k%d-p1", k);
+    add(id, [e7] { init0(); sf(e7 + 1, 6); });
+  }
+
+  // ===== CLK6 / CLK7 peer logic =====
+  add("X:clk7-first-then-clk6-accept", [] { init0(); sf(23000000 * M, 7); sf(87400000 * M, 6); });
+  add("X:clk7-first-then-clk6-reject-odd", [] { init0(); sf(23000000 * M, 7); sf(46000000 * M, 6); });
+  add("X:clk7-first-then-clk6-reject-nonint", [] { init0(); sf(23000000 * M, 7); sf(12345678 * M, 6); });
+  add("X:clk6-then-clk7-reject-odd", [] { init0(); sf(23000000 * M, 6); sf(46000000 * M, 7); });
+  add("X:clk6-then-clk7-even-lowfreq-ms67fail", [] { init0(); sf(23000000 * M, 6); sf(23000 * M, 7); });
+  add("X:clk6-reset-peer-by-reset", [] { init0(); sf(23000000 * M, 6); reset_(); sf(12345678 * M, 7); });
+  add("X:clk67-bounds", [] { init0(); sf(1, 6); sf(1845399, 7); });
+  add("X:clk67-upper-clamp", [] { init0(); sf(20000000000ULL, 6); });
+  add("X:clk67-upper-clamp7", [] { init0(); sf(15000000000ULL, 7); });
+  add("X:clk67-resets-6", [] { init0(); sf(10000000 * M, 6); sf(20000000 * M, 6); });
+  add("X:clk6-pll-asym-clk6-on-plla", [] { init0(); mssrc(6, 0); sf(23000000 * M, 6); });
+  add("X:clk7-pll-asym-clk7-on-plla", [] { init0(); mssrc(7, 0); sf(23000000 * M, 7); });
+  add("X:clk67-plus-clk0", [] { init0(); sf(14000000 * M, 0); sf(30000000 * M, 6); sf(60000000 * M, 7); sf(7000000 * M, 1); });
+
+  // ===== set_freq_manual =====
+  add("X:manual-various", [] { init0(); sfm(14000000 * M, 87600000000ULL, 0); sfm(5000 * M, 80000000000ULL, 1); sfm(200000000 * M, 80000000000ULL, 2);
+                               mssrc(3, 1); sfm(10000000 * M, 60000000000ULL, 3); sfm(1000000 * M, 90000000000ULL, 5); });
+  add("X:manual-on-clk6-clk7", [] { init0(); sfm(20000000 * M, 80000000000ULL, 6); sfm(40000000 * M, 80000000000ULL, 7); });
+  add("X:manual-pll-out-of-vco", [] { init0(); sfm(10000000 * M, 50000000000ULL, 0); sfm(10000000 * M, 100000000000ULL, 1); });
+
+  // ===== correction =====
+  add("X:corr-then-freq", [] { init0(); sf(14000000 * M, 0); corr_(100000, 0); sf(112000000 * M, 0); sf(10000000 * M, 1); corr_(-50000, 0); sf(7000000 * M, 2); });
+  add("X:corr-clkin", [] { init0(); reff(50000000, 1); pllin(1, 1); corr_(-30000, 1); sf(23000000 * M, 6); sf(14000000 * M, 0); mssrc(1, 1); sf(10000000 * M, 1); });
+  add("X:corr-init-large", [] { init_(LOAD, 0, 1500000); sf(14000000 * M, 0); sf(150000000 * M, 1); });
+  add("X:clkin-dividers", [] { init0(); reff(25000000, 1); pllin(0, 1); sf(112000000 * M, 0); reff(80000000, 1); pllin(0, 1); sf(112000000 * M, 0); pllin(0, 0); });
+
+  // ===== VCXO =====
+  add("X:vcxo-ppm-bounds", [] { init0(); svcxo(87600000000ULL, 10); svcxo(87600000000ULL, 30); svcxo(87600000000ULL, 240); svcxo(87600000000ULL, 255); });
+  add("X:vcxo-pll-range", [] { init0(); svcxo(60000000000ULL, 100); svcxo(90000000000ULL, 100); svcxo(70012345600ULL, 77); svcxo(50000000000ULL, 50); });
+  add("X:vcxo-with-corr", [] { init_(LOAD, 0, 12345); svcxo(87600000000ULL, 40); mssrc(0, 1); sfm(14600000000ULL, 87600000000ULL, 0); });
+
+  // ===== reset/init =====
+  add("X:init-27MHz", [] { init_(LOAD, 27000000, 0); sf(14000000 * M, 0); sf(23000000 * M, 6); });
+  add("X:init-xo-50MHz", [] { init_(SI5351_CRYSTAL_LOAD_10PF, 50000000, 0); sf(14000000 * M, 0); });
+  add("X:init-xo-150MHz-ignored", [] { init_(SI5351_CRYSTAL_LOAD_6PF, 150000000, 0); sf(14000000 * M, 0); });
+  add("X:reset-after-use", [] { init0(); sf(14000000 * M, 0); sf(112000000 * M, 1); sf(23000000 * M, 6); mssrc(2, 1); reset_(); sf(14000000 * M, 2); });
+  add("X:init-no-device", [] { init0(); sf(14000000 * M, 0); }, false);
+
+  // ===== direct set_ms / set_pll public calls =====
+  add("X:set_ms-direct-all-clks", [] { init0();
+    for (int c = 0; c < 8; c++) sms(c, 0x3ABCD + c, 0xFEDCB - c, 0xF4240 + c, c & 1, (c * 3) & 7, (c >> 1) & 1); });
+  add("X:set_ms-direct-maxbits", [] { init0();
+    for (int c = 0; c < 8; c++) sms(c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 1, 7, 1); });
+  add("X:set_pll-direct", [] { init0(); spll(0, 0); spll(87654321012ULL, 1); spll(200000000000ULL, 0); spll(64000000000ULL, 1); });
+  add("X:misc-smoke", [] { init0(); misc_smoke(); oe(3, 1); oe(3, 0); pllrst(0); pllrst(1); });
+
+#ifdef OOR_SCENARIOS
+  // Out-of-contract: clk value outside enum si5351_clock (not part of pass/fail set)
+  add("OOR:set_ms-clk8", [] { init0(); sms(8, 0x12345, 0x6789A, 0xF4240, 0, 3, 0); });
+  add("OOR:set_freq-clk8", [] { init0(); sf(14000000 * M, 8); });
+  add("OOR:set_freq_manual-clk8", [] { init0(); sfm(14000000 * M, 80000000000ULL, 8); });
+  return;
+#endif
+  // ===== extra golden cases with library register maps (generated) =====
+#if __has_include("golden_extra.inc")
+#include "golden_extra.inc"
+#endif
+
+  // ===== Si5351_FreqChecks.ino hardware-check sequences (2026-10-07) =====
+  add("H:check9-isolated", [] { init0(); fc_check(8); });            // init -> check 9 only
+  add("H:check10-isolated", [] { init0(); fc_check(9); });
+  add("H:check8-then-9", [] { init0(); fc_check(7); fc_check(8); });
+  add("H:check11-isolated", [] { init0(); fc_check(10); });
+  for (int k = 1; k <= 12; k++) {                                    // real sketch: checks 1..k cumulative
+    char id[40]; snprintf(id, sizeof id, "H:freqchecks-1-to-%02d", k);
+    add(id, [k] { init0(); for (int i = 0; i < k; i++) fc_check(i); });
+  }
+
+  // ===== Issue #65 scenarios (DIVBY4 exit), 2026-10-07 =====
+  add("I65:S1-clk0-80-156-80", [] { init0(); sf(80000000 * M, 0); sf(156000000 * M, 0); sf(80000000 * M, 0); });
+  add("I65:S2-clk0-80-156-143-80-control", [] { init0(); sf(80000000 * M, 0); sf(156000000 * M, 0); sf(143000000 * M, 0); sf(80000000 * M, 0); });
+  add("I65:S3-clk0-80-156-80-manual-pll_reset", [] { init0(); sf(80000000 * M, 0); sf(156000000 * M, 0); sf(80000000 * M, 0); pllrst(0); });
+  add("I65:S4-clk0-155-96", [] { init0(); sf(155000000 * M, 0); sf(96000000 * M, 0); });
+  add("I65:S6-clk0-155-then-clk2-99", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("I65:clk0-200-10", [] { init0(); sf(200000000 * M, 0); sf(10000000 * M, 0); });
+  add("I65:clk0-200-512k-rdiv", [] { init0(); sf(200000000 * M, 0); sf(512000 * M, 0); sf(5000 * M, 0); });
+  add("I65:clk0-200-120-gt100-path", [] { init0(); sf(200000000 * M, 0); sf(120000000 * M, 0); });
+  add("I65:clk0-200-180-stays-divby4", [] { init0(); sf(200000000 * M, 0); sf(180000000 * M, 0); sf(160000000 * M, 0); });
+  for (int c = 0; c < 6; c++) {                         // every MS0..5 on both PLLs
+    for (int pll = 0; pll < 2; pll++) {
+      char id[48]; snprintf(id, sizeof id, "I65:clk%d-pll%c-160-14", c, pll ? 'B' : 'A');
+      add(id, [c, pll] { init0(); mssrc(c, pll); sf(160000000 * M, c); sf(14000000 * M, c); });
+    }
+  }
+  add("I65:manual-175-pll700-to-14-pll800-pllb", [] { init0(); mssrc(1, 1); sfm(175000000 * M, 700000000 * M, 1); sfm(14000000 * M, 800000000 * M, 1); });
+  add("I65:manual-200-to-set_freq-10", [] { init0(); sfm(200000000 * M, 800000000 * M, 2); sf(10000000 * M, 2); });
+  add("I65:set_freq-200-to-manual-10", [] { init0(); sf(200000000 * M, 3); sfm(10000000 * M, 800000000 * M, 3); });
+  add("I65:set_ms-direct-divby4-exit", [] { init0(); sms(2, 0, 0, 1, 1, 0, 1); sms(2, 0x0B40, 0, 1, 0, 0, 0); sms(2, 0x0B40, 0, 1, 0, 0, 0); });
+  add("I65:reset-after-divby4-then-512k", [] { init0(); sf(210000000 * M, 0); reset_(); sf(512000 * M, 0); oe(0, 1); });
+  add("I65:reset-after-divby4-then-14M-other-clk", [] { init0(); sf(210000000 * M, 0); reset_(); sf(14000000 * M, 1); sf(14000000 * M, 0); });
+  add("I65:peer-divby4-recalc", [] { init0(); sf(10000000 * M, 1); sf(160000000 * M, 0); sf(3000000 * M, 5); sf(7000000 * M, 0); });
+
+  // ===== Steady-state tuning (no DIVBY4 transition): fix must add ZERO resets =====
+  add("T:vfo-clk0-7MHz-1kHz-x300", [] { init0(); for (int i = 0; i <= 300; i++) sf((7000000ULL + 1000ULL * i) * M, 0); });
+  add("T:vfo-clk0-14MHz-frac-1.37Hz-x300", [] { init0(); for (int i = 0; i <= 300; i++) sf(14074000ULL * M + 137ULL * i, 0); });
+  add("T:vfo-clk0-sweep-3k-100M-log-x400", [] { init0(); for (int i = 0; i <= 400; i++) sf((ull)(__builtin_pow(10.0, 3.5 + 4.5 * i / 400.0) * 100.0), 0); });
+  add("T:vfo-clk0-sweep-100M-down-3k-x400", [] { init0(); for (int i = 400; i >= 0; i--) sf((ull)(__builtin_pow(10.0, 3.5 + 4.5 * i / 400.0) * 100.0), 0); });
+  add("T:rdiv-band-hop-clk0-clk3", [] { init0();
+    ull f[] = {5000, 10000, 20000, 50000, 100000, 200000, 400000, 512000, 1000000, 512000, 400000, 100000, 10000, 4000, 5000, 1000000, 4000};
+    for (int r = 0; r < 3; r++) for (ull x : f) { sf(x * M, 0); sf(x * M + 1, 3); } });
+  add("T:multi-clk012-interleaved-x150", [] { init0(); for (int i = 0; i < 150; i++) { sf((3500000ULL + 997ULL * i) * M, 0); sf((7000000ULL + 1501ULL * i) * M, 1); sf((50000000ULL + 12345ULL * i) * M, 2); } });
+  add("T:clk1-pllb-x200", [] { init0(); mssrc(1, 1); for (int i = 0; i < 200; i++) sf((10000000ULL + 2500ULL * i) * M + i, 1); });
+  add("T:clk67-steps", [] { init0(); for (int i = 0; i < 60; i++) { sf((20000000ULL + 100000ULL * i) * M, 6); sf((20000000ULL + 100000ULL * i) * M, 7); } });
+  add("T:manual-clk0-pll800-x200", [] { init0(); for (int i = 0; i < 200; i++) sfm((14000000ULL + 50ULL * i) * M, 800000000ULL * M, 0); });
+  add("T:manual-clk2-pll-varies-x100", [] { init0(); for (int i = 0; i < 100; i++) sfm(10000000ULL * M, (600000000ULL + 2000000ULL * i) * M, 2); });
+  add("T:corr-during-tuning", [] { init0(); for (int i = 0; i < 100; i++) { if (i % 10 == 0) corr_((i - 50) * 1000, 0); sf((7040000ULL + 10ULL * i) * M, 0); } });
+  add("T:gt100-non-divby4-tuning-x100", [] { init0(); for (int i = 0; i < 100; i++) sf((101000000ULL + 480000ULL * i) * M, 0); });
+  add("T:divby4-steady-tuning-x50", [] { init0(); for (int i = 0; i < 50; i++) sf((151000000ULL + 1000000ULL * i) * M, 0); });
+  add("T:repeat-same-freq-x100", [] { init0(); for (int i = 0; i < 100; i++) sf(14070000ULL * M, 0); });
+  add("T:freqchecks-1-to-4-then-tune", [] { init0(); for (int i = 0; i < 4; i++) fc_check(i); for (int i = 0; i < 100; i++) sf((28000000ULL + 100ULL * i) * M, 0); });
+
+  // ===== Si5351_Issue65_Verify.ino, call-for-call (steps run cumulatively on one chip) =====
+  for (int k = 1; k <= 8; k++) {
+    char id[40]; snprintf(id, sizeof id, "HV:verify-steps-1-to-%d", k);
+    add(id, [k] { init0(); for (int s = 1; s <= k; s++) hv_step(s); });
+  }
+
+  add("HV2:verify-v2-all-steps", [] { init0(); for (int s = 0; s < HV2_N; s++) hv2_step(s); });
+  for (int s = 0; s < HV2_N; s++) { char id[40]; snprintf(id, sizeof id, "HV2:only-step-%s", HV2_NAMES[s]); add(id, [s] { init0(); hv2_step(s); }); }
+
+  // ===== low-clock move to the other PLL (#65 third scenario), 2026-10-08 =====
+  add("MV:155clk0-99clk2", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:155clk0-99clk2-then-tune-x200", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2);
+    for (int i = 0; i < 200; i++) sf((99000000ULL - 20000ULL * i) * M + i, 2); });
+  add("MV:both-held-keeps-old", [] { init0(); mssrc(1, 1); sf(130000000 * M, 1); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:dest-shared-reuse", [] { init0(); mssrc(1, 1); sf(14000000 * M, 1); sf(155000000 * M, 0); sf(99000000 * M, 2); sf(14100000 * M, 1); });
+  add("MV:dest-shared-low-keeps-old", [] { init0(); mssrc(1, 1); sfm(10000000 * M, 60000000000ULL, 1); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:dest-free-low-replan", [] { init0(); spll(60000000000ULL, 1); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:clk6-on-pllb-then-move", [] { init0(); sf(23000000 * M, 6); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:clk6-even-on-pllb-then-move", [] { init0(); sf(100000000 * M, 6); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:move-then-clk6-first-set", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); sf(23000000 * M, 6); });
+  add("MV:move-then-clk7-first-set", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); sf(20000000 * M, 7); });
+  add("MV:back-and-forth", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); sf(10000000 * M, 0); sf(98000000 * M, 2);
+    sf(160000000 * M, 0); sf(97000000 * M, 2); sf(120000000 * M, 2); sf(99000000 * M, 2); sf(99000000 * M, 0); sf(160000000 * M, 2); sf(99000000 * M, 0); });
+  add("MV:pllb-held-move-to-plla", [] { init0(); mssrc(1, 1); mssrc(3, 1); sf(155000000 * M, 1); sf(99000000 * M, 3); });
+  add("MV:move-with-divby4-exit", [] { init0(); sf(160000000 * M, 2); reset_(); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  add("MV:manual-not-moved", [] { init0(); sf(155000000 * M, 0); sfm(99000000 * M, 62000000000ULL, 2); });
+  add("MV:two-low-clocks-move", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); sf(95000000 * M, 3); sf(14000000 * M, 4); });
+  add("MV:rdiv-low-freq-no-move", [] { init0(); sf(155000000 * M, 0); sf(5000 * M, 2); sf(512000 * M, 3); });
+  add("MV:corr-then-move", [] { init_(LOAD, 0, 120000); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+  // ===== double-reset cases (one reset after all writes) =====
+  add("DR:200-120-gt100-exit", [] { init0(); sf(200000000 * M, 0); sf(120000000 * M, 0); });
+  add("DR:155-96-replan-exit", [] { init0(); sf(155000000 * M, 0); sf(96000000 * M, 0); });
+  add("DR:peer-recalc-exit", [] { init0(); sf(10000000 * M, 1); sf(160000000 * M, 0); sf(120000000 * M, 0); sf(90000000 * M, 0); });
+  add("DR:two-divby4-peers-reset", [] { init0(); sf(160000000 * M, 0); reset_(); sf(160000000 * M, 1); sf(120000000 * M, 1); });
+
+  add("HV3:verify-v3-all-steps", [] { init0(); for (int s = 0; s < HV3_N; s++) hv3_step(s); });
+  for (int s = 12; s < HV3_N; s++) { char id[40]; snprintf(id, sizeof id, "HV3:only-step-%s", HV3S[s].name); add(id, [s] { init0(); hv3_step(s); }); }
+
+  // ===== v2.3.1 fix sequences (2026-10-10) =====
+  // item 1: MS6/7 divider range (DEV-03, DEV-15) + CLK6/7 small bugs
+  add("V:dev03-clk6-10kHz", [] { init0(); sf(10000 * M, 6); });
+  add("V:dev03-clk7-10kHz", [] { init0(); sf(10000 * M, 7); });
+  add("V:dev03-clk6-old-min-18454Hz", [] { init0(); sf(18454 * M, 6); });
+  add("V:dev03-clk6-new-min-18455Hz", [] { init0(); sf(18455 * M, 6); });
+  add("V:dev03-clk6-band-window-r64", [] { init0(); sf(3690900ULL, 6); });          // 36909.00 Hz -> MS 2.362176 MHz at R=64
+  add("V:dev03-clk6-band-window-r1", [] { init0(); sf(236215000ULL, 6); });         // 2.36215 MHz at R=1
+  add("V:clk6-sweep-low", [] { for (ull f = 1000; f <= 3000000; f = f * 21 / 20 + 7) { init0(); sf(f * M, 6); } });
+  add("V:clk7-sweep-all", [] { for (ull f = 15000; f <= 160000000; f = f * 13 / 10 + 3) { init0(); sf(f * M, 7); } });
+  add("V:clk6-150MHz-clamp", [] { init0(); sf(160000000 * M, 6); });
+  add("V:dev15-manual-clk7-87p4", [] { init0(); sfm(87400000 * M, 874000000ULL * M, 7); });
+  add("V:dev15-manual-clk6-1MHz-needs-R4", [] { init0(); sfm(1000000 * M, 800000000ULL * M, 6); });
+  add("V:dev15-manual-clk6-10kHz-no-valid", [] { init0(); sfm(10000 * M, 800000000ULL * M, 6); });
+  add("V:dev15-manual-clk6-13MHz-non-integer", [] { init0(); sfm(13000000 * M, 800000000ULL * M, 6); });
+  add("V:dev15-manual-clk6-80MHz-odd-11", [] { init0(); sfm(80000000 * M, 880000000ULL * M, 6); });
+  add("V:dev15-manual-clk7-3MHz-odd-after-R", [] { init0(); sfm(3000000 * M, 774000000ULL * M, 7); });
+  add("V:peer-ok-then-uninit-case", [] { init0(); sf(23000000 * M, 6); sf(100000 * M, 7); sf(87400000 * M, 7); });
+  add("V:peer-needs-R16", [] { init0(); sf(23000000 * M, 6); sf(273125 * M, 7); });
+  add("V:freq0-clk7-peer-set", [] { init0(); sf(23000000 * M, 6); sf(0, 7); });
+  add("V:freq0-clk6-no-peer", [] { init0(); sf(0, 6); });
+  add("V:freq0-manual-clk6", [] { init0(); sfm(0, 800000000ULL * M, 6); });
+  // item 2: DEV-14 CLK6/7 output enable
+  add("V:dev14-clk6-clk7-enable", [] { init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); });
+  add("V:dev14-clk6-reject-stays-off", [] { init0(); sf(23000000 * M, 6); sf(12345678 * M, 7); });
+  add("V:dev14-clk6-after-user-disable", [] { init0(); sf(23000000 * M, 6); oe(6, 0); sf(24000000 * M, 6); });
+  // item 4: 200 MHz clamp
+  add("V:fout-200-210-225-250-clk0", [] { init0(); sf(200000000 * M, 0); sf(210000000 * M, 0); sf(225000000 * M, 0); sf(250000000 * M, 0); });
+  add("V:fout-manual-210-clk0", [] { init0(); sfm(210000000 * M, 840000000ULL * M, 0); });
+  add("V:fout-210-clk1-plus-14-clk0", [] { init0(); sf(14000000 * M, 0); sf(210000000 * M, 1); });
+  // item 4: manual MS ratio 5 (stale a); 6.67/7 unchanged on purpose
+  add("V:manual-ratio5-140-at-700", [] { init0(); sfm(140000000 * M, 700000000ULL * M, 0); });
+  add("V:manual-ratio6p67-unchanged", [] { init0(); sfm(90000000 * M, 600000000ULL * M, 0); });
+  add("V:manual-ratio7-unchanged", [] { init0(); sfm(100000000 * M, 700000000ULL * M, 0); });
+  // item 4: set_phase / set_int on CLK6/7
+  add("V:phase-clk0-5-and-6-7", [] { init0(); for (int c = 0; c < 8; c++) sph(c, 10 + c); });
+  add("V:set_int-clk6-clk7", [] { init0(); sf(14000000 * M, 0); sint(6, 1); sint(7, 1); sint(6, 0); sint(0, 1); });
+  // item 4: CLKIN_DIV field
+  add("V:clkin-div-2-then-4", [] { init0(); reff(50000000, 1); pllin(0, 1); reff(80000000, 1); pllin(1, 1); });
+  add("V:clkin-div-4-then-1-then-xo", [] { init0(); reff(80000000, 1); pllin(0, 1); reff(25000000, 1); pllin(1, 1); pllin(1, 0); });
+  // item 4: crystal load
+  add("V:xtal-load-0pf", [] { init_(SI5351_CRYSTAL_LOAD_0PF, 0, 0); });
+  add("V:xtal-load-6-8-10pf", [] { init_(SI5351_CRYSTAL_LOAD_6PF, 0, 0); init_(SI5351_CRYSTAL_LOAD_8PF, 0, 0); init_(SI5351_CRYSTAL_LOAD_10PF, 0, 0); });
+  // item 4: VCXO denominator
+  add("V:vcxo-then-correction", [] { init0(); svcxo(87500000000ULL, 100); corr_(2000, 0); });
+  add("V:vcxo-example-manual-on-pllb", [] { init0(); svcxo(87600000000ULL, 30); mssrc(0, 1); sfm(14600000000ULL, 87600000000ULL, 0); corr_(-500, 0); });
+  add("V:vcxo-875-manual-on-pllb-b0", [] { init0(); svcxo(87500000000ULL, 30); mssrc(0, 1); sfm(14583333333ULL, 87500000000ULL, 0); });
+  add("V:vcxo-then-pll-input", [] { init0(); svcxo(87500000000ULL, 100); pllin(1, 0); });
+  add("V:vcxo-then-reset-normal-pllb", [] { init0(); svcxo(87500000000ULL, 100); reset_(); spll(87500000000ULL, 1); corr_(100, 0); });
+  // item 4: DEV-13 5 MHz reference (documented, not changed)
+  add("V:dev13-5MHz-ref", [] { init_(LOAD, 5000000, 0); sf(10000000 * M, 0); });
+
+  // ===== v2.3.1 follow-up: recalc clocks when their PLL changes =====
+  add("RC:clk1-10M-pllb-then-clk6-plans-pllb", [] { init0(); mssrc(1, 1); sf(10000000 * M, 1); sf(23000000 * M, 6); });
+  add("RC:clk6-25M-then-clk0-150M-on-pllb", [] { init0(); sf(25000000 * M, 6); mssrc(0, 1); sf(150000000 * M, 0); });
+  add("RC:clk6-23M-then-clk0-150M-on-pllb-left", [] { init0(); sf(23000000 * M, 6); mssrc(0, 1); sf(150000000 * M, 0); });
+  add("RC:clk1-10M-then-clk0-150M-plla", [] { init0(); sf(10000000 * M, 1); sf(150000000 * M, 0); });
+  add("RC:direct-set_pll-clk0-10M", [] { init0(); sf(10000000 * M, 0); spll(70000000000ULL, 0); });
+  add("RC:direct-set_pll-same-freq-no-writes", [] { init0(); sf(10000000 * M, 0); spll(80000000000ULL, 0); });
+  add("RC:vcxo-with-clk1-on-pllb", [] { init0(); mssrc(1, 1); sf(10000000 * M, 1); svcxo(87600000000ULL, 30); corr_(500, 0); });
+  add("RC:manual-clk2-then-set_pll", [] { init0(); sfm(14000000 * M, 80000000000ULL, 2); spll(72000000000ULL, 0); });
+  add("RC:manual-divby4-left-on-set_pll", [] { init0(); sfm(175000000 * M, 70000000000ULL, 0); sf(10000000 * M, 1); spll(80000000000ULL, 0); });
+  add("RC:clk7-87p4-then-set_pll-pllb", [] { init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); spll(69000000000ULL, 1); });
+
+  // ===== seeded random fuzz =====
+  for (int i = 0; i < 400; i++) {
+    char id[32]; snprintf(id, sizeof id, "F:fuzz-%03d", i);
+    ull seed = 0x5155351ULL * (i + 1);
+    add(id, [seed] { fuzz_seq(seed, 16); });
+  }
+}
+
+// ---- JSON output ----
+static void jstr(FILE *o, const std::string &s) {
+  fputc('"', o);
+  for (char ch : s) { if (ch == '"' || ch == '\\') fputc('\\', o); fputc(ch, o); }
+  fputc('"', o);
+}
+
+int main(int argc, char **argv) {
+  const char *outpath = argc > 1 ? argv[1] : "out.jsonl";
+  FILE *o = fopen(outpath, "w");
+  build();
+  for (int pattern = 0; pattern < 2; pattern++) {
+    for (auto &sc : SC) {
+      g_sim.reset(pattern, sc.present);
+      RETS.clear();
+      memset(objbuf, 0, sizeof objbuf);   // mimic Arduino global object (.bss zero-init)
+      S = new (objbuf) Si5351();
+      signal(SIGFPE, on_fpe);
+      if (sigsetjmp(g_fpe_jb, 1)) { g_sim.mark("CRASH SIGFPE (division by zero)"); RETS.push_back("CRASH=SIGFPE"); }
+      else sc.fn();
+      fprintf(o, "{\"id\":"); jstr(o, sc.id);
+      fprintf(o, ",\"pattern\":%d,\"rets\":[", pattern);
+      for (size_t i = 0; i < RETS.size(); i++) { if (i) fputc(',', o); jstr(o, RETS[i]); }
+      fprintf(o, "],\"regs\":[");
+      for (int i = 0; i < 256; i++) fprintf(o, i ? ",%u" : "%u", g_sim.regs[i]);
+      fprintf(o, "],\"state\":{\"plla_freq\":%llu,\"pllb_freq\":%llu,\"clk_freq\":[", (ull)S->plla_freq, (ull)S->pllb_freq);
+      for (int i = 0; i < 8; i++) fprintf(o, i ? ",%llu" : "%llu", (ull)S->clk_freq[i]);
+      fprintf(o, "],\"pll_assignment\":[");
+      for (int i = 0; i < 8; i++) fprintf(o, i ? ",%d" : "%d", (int)S->pll_assignment[i]);
+      fprintf(o, "],\"xtal_freq\":[%u,%u],\"ref_osc\":[%d,%d],\"corr\":[%d,%d]}", S->xtal_freq[0], S->xtal_freq[1],
+              (int)S->plla_ref_osc, (int)S->pllb_ref_osc, S->get_correction(SI5351_PLL_INPUT_XO), S->get_correction(SI5351_PLL_INPUT_CLKIN));
+      fprintf(o, ",\"n_writes\":%lu,\"n_reads\":%lu,\"tx\":[", g_sim.n_writes, g_sim.n_reads);
+      for (size_t i = 0; i < g_sim.events.size(); i++) { if (i) fputc(',', o); jstr(o, g_sim.events[i]); }
+      fprintf(o, "]}\n");
+      S->~Si5351();
+    }
+  }
+  fclose(o);
+  fprintf(stderr, "%zu scenarios x 2 register-file patterns written to %s\n", SC.size(), outpath);
+  return 0;
+}
diff --git a/tests/regression/equiv/logs/golden_cases.snapshot.json b/tests/regression/equiv/logs/golden_cases.snapshot.json
new file mode 100644
index 0000000..78639d6
--- /dev/null
+++ b/tests/regression/equiv/logs/golden_cases.snapshot.json
@@ -0,0 +1,10411 @@
+{
+  "source_repo": "https://github.com/etherkit/Si5351Arduino",
+  "source_commit": "0559cbf82865e2957d46af72e70cc88207421434",
+  "source_ref": "master",
+  "library_version": "2.2.0",
+  "spec_sources": {
+    "AN619": "AN619 Rev 0.8 (2021-09-23) Manually Generating an Si5351 Register Map for 10-MSOP and 20-QFN Devices",
+    "DS": "Si5351A/B/C-B datasheet Rev 1.3 (2021-08-27)"
+  },
+  "assumptions": {
+    "xtal_hz_default": 25000000,
+    "freq_mult": 100,
+    "pll_fixed_lib": 80000000000,
+    "rfrac_denom": 1000000,
+    "correction_default_ppb": 0,
+    "freq_units": "API takes Hz * 100 (SI5351_FREQ_MULT)",
+    "init_xo_freq_0_means": "SI5351_XTAL_FREQ (25 MHz)",
+    "unknown_prior_register_bits": "assumed 0 (reg 44-style byte bit7, reg 92, reg 3 before reset)",
+    "spec_bc_choice": "spec does not prescribe b/c selection; spec registers are encoded from the library's a/b/c",
+    "accuracy_tolerance_ppb": 1000
+  },
+  "golden_corrections": [
+    {
+      "cases": [
+        "P0-clk0-DIVBY4-200MHz",
+        "P0-clk0-DIVBY4-boundary-150MHz",
+        "P0-manual-DIVBY4-175MHz-pll700",
+        "P1-parity-gt100-set_freq-vs-manual-175MHz (embedded auto/manual)"
+      ],
+      "field": "ms_a",
+      "old": 6,
+      "new": 4,
+      "reason": "multisynth_calc(freq, pll_freq) sees a = pll/freq = 4 < SI5351_MULTISYNTH_A_MIN, clamps freq = pll/6 but does NOT recompute a. The first-draft mirror recomputed a (=6). Registers were never affected because DIVBY4 overrides P1/P2/P3 to 0/0/1; only the reported intermediate changes. Mirror now matches library exactly (also fixes the same pattern in pll_calc)."
+    }
+  ],
+  "deviation_catalog": {
+    "DEV-01-FOUT-MAX-225": {
+      "title": "Library accepts CLK0-5 output up to 225 MHz; spec max is 200 MHz",
+      "library": "SI5351_MULTISYNTH_MAX_FREQ = 225000000; set_freq clamps to 225 MHz, programs DIVBY4 with fVCO=4*Fout (e.g. 210 MHz -> VCO 840 MHz, 250 MHz request -> 225 MHz/VCO 900 MHz)",
+      "spec": "DS Table 7 FCLK max 200 MHz; AN619 \u00a72 MS output 500 kHz-200 MHz; AN619 \u00a74.1.3 DIVBY4 range 150 < Fout <= 200 MHz",
+      "rules": "OUT_FREQ_RANGE, MS_OUT_RANGE (+OUT_FREQ_ACCURACY when clamped)",
+      "severity": "medium"
+    },
+    "DEV-02-FOUT-MIN-4K": {
+      "title": "Library min CLK0-5 output is 4 kHz; datasheet min is 2.5 kHz",
+      "library": "SI5351_CLKOUT_MIN_FREQ = 4000; 2.5 kHz request silently becomes 4 kHz (R=128, MS 512 kHz)",
+      "spec": "DS Table 7 FCLK min 0.0025 MHz; AN619 \u00a72 'down to 2.5 kHz' (note AN619 \u00a74.2.2 says 8 kHz: docs disagree)",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "low (conservative)"
+    },
+    "DEV-03-CLK67-LOWFREQ-P1-TRUNC": {
+      "title": "CLK6/7 low-frequency request writes MS6_P1 = 0 (uint8 truncation of 256)",
+      "library": "set_freq(<18.454 kHz, CLK6/7) clamps to 4 kHz (CLKOUT_MIN, not CLKOUT67_MIN), select_r_div_ms67 picks R=1, multisynth67_calc clamps to 500 kHz, a=254 -> PLL 127 MHz < VCO_MIN -> a+=2 = 256 -> reg->p1=(uint8_t)256 = 0; set_pll(128 MHz) is clamped to 600 MHz inside pll_calc but pllb_freq stores 128 MHz",
+      "spec": "AN619 Reg 90/91: MS6/7 ratio even integer 6..254; AN619 \u00a72 VCO 600-900 MHz",
+      "rules": "MS67_RATIO_VALID, VCO_REQUEST_RANGE, OUT_FREQ_ACCURACY",
+      "severity": "high"
+    },
+    "DEV-04-MS-RATIO-6-TO-8": {
+      "title": "Library permits output MS ratios in [6,8) other than 6 (odd 7, fractional 6.x, 7.x)",
+      "library": "multisynth_calc(freq, pll_freq) only clamps a<6 / a>1800; set_freq_manual(100 MHz, 700 MHz) -> ratio 7; (90 MHz, 600 MHz) -> 6.666666",
+      "spec": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2: valid ratios 4, 6, 8, or 8+1/1048575 .. 2048",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium (set_freq_manual / mixed-PLL scenarios)"
+    },
+    "DEV-05-MS-STALE-A": {
+      "title": "multisynth_calc keeps stale a after the a<6 clamp -> programs ratio 5",
+      "library": "a = pll/freq = 5; freq = pll/6 but a is not recomputed; b = 0 -> P1 = 128 (ratio 5). set_freq_manual(140 MHz, 700 MHz)",
+      "spec": "AN619 \u00a72.1.1: ratio 5 invalid",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium"
+    },
+    "DEV-06-DIVBY4-PRECONDITION": {
+      "title": "set_freq_manual forces DIVBY4 for Fout >= 150 MHz regardless of pll_freq",
+      "library": "set_freq_manual(175 MHz, 800 MHz) writes DIVBY4 (P=0,0,1) -> actual output 200 MHz",
+      "spec": "AN619 \u00a74.1.3 'Set the appropriate feedback Multisynth to generate fVCO = Fout*4'",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "medium (documented 'track settings yourself' API)"
+    },
+    "DEV-07-VCXO-CENTER-112M5": {
+      "title": "VCXO-linked output above 112.5 MHz (library example si5351_vcxo.ino uses 146 MHz)",
+      "library": "No check; example tunes CLK0 = 146 MHz on VCXO PLLB 876 MHz",
+      "spec": "DS \u00a74.2 'Multisynth ... synthesizes the VCXO output's center frequency up to 112.5 MHz'",
+      "rules": "VCXO_CENTER_MAX",
+      "severity": "low (example/precondition)"
+    },
+    "DEV-08-VCXO-C-NOT-PRESERVED": {
+      "title": "VCXO requirement c = 10^6 on MSNB is lost after later set_pll() calls",
+      "library": "set_vcxo() does not update pllb_freq; set_correction()/set_pll_input() re-run set_pll(pllb_freq=800 MHz) -> MSNB a=32,b=0,c=1. set_freq_manual(..., 875 MHz) after set_vcxo(875 MHz) re-runs non-VCXO pll_calc -> b=0 -> c=1",
+      "spec": "AN619 \u00a73.2 & \u00a77: 'Feedback B Multisynth divider ratio must be set such that ... c ... is fixed to 10^6'",
+      "rules": "VCXO_C_FIXED, VCXO_PLL_PRESERVED",
+      "severity": "medium"
+    },
+    "DEV-09-PHOFF-CLK67": {
+      "title": "set_phase(CLK6/7) writes reserved registers 171/172",
+      "library": "si5351_write(SI5351_CLK0_PHASE_OFFSET + clk, phase) with no clk bound",
+      "spec": "AN619 \u00a76 & Reg 165-170: phase offset only for CLK0-5; 171-176 Reserved",
+      "rules": "PHOFF_ADDR",
+      "severity": "low"
+    },
+    "DEV-10-XTAL-CL-0PF": {
+      "title": "SI5351_CRYSTAL_LOAD_0PF writes reserved XTAL_CL = 00b",
+      "library": "init(SI5351_CRYSTAL_LOAD_0PF, ...) -> reg183 = 0x12",
+      "spec": "AN619 Reg 183: XTAL_CL 00 'Reserved. Do not select this option.'",
+      "rules": "XTAL_CL_RESERVED",
+      "severity": "low"
+    },
+    "DEV-11-SET_INT-CLK67-IS-FB_INT": {
+      "title": "set_int(CLK6/7) toggles FBA_INT/FBB_INT (reg 22/23 bit 6), not an MS6/7 integer bit",
+      "library": "set_int() writes bit 6 of SI5351_CLK0_CTRL+clk for any clk; on fractional PLLA this forces MSNA integer mode",
+      "spec": "AN619 Reg 22/23 bit 6 = FBA_INT/FBB_INT; \u00a73.2.1 only for even-integer feedback; \u00a74.1.2.1 MS6/7 have no INT bit",
+      "rules": "FB_INT_ONLY_EVEN_INT",
+      "severity": "medium"
+    },
+    "DEV-12-CLKIN-DIV-RMW": {
+      "title": "set_pll_input ORs CLKIN_DIV into reg 15 without clearing the old field",
+      "library": "reg_val |= clkin_div (the &= ~SI5351_CLKIN_DIV_MASK line is commented out): prior /2 (01b) + new /4 (10b) -> 11b = /8",
+      "spec": "AN619 Reg 15 CLKIN_DIV[1:0] is a 2-bit field (00 /1, 01 /2, 10 /4, 11 /8)",
+      "rules": "CLKIN_DIV_FIELD",
+      "severity": "medium (Si5351C/CLKIN users)"
+    },
+    "DEV-13-PLL-STALE-A": {
+      "title": "pll_calc keeps stale a after a>90 clamp (non-25/27 MHz reference)",
+      "library": "5 MHz reference: a = 160 > 90, freq clamped to 450 MHz but a not recomputed; P1 = 19968 (ratio 160)",
+      "spec": "AN619 \u00a73.2 feedback ratio 15..90; AN619 \u00a73.1.2 PLL input 10-40 MHz; DS Table 6/8 XTAL 25-27 MHz",
+      "rules": "FB_RATIO_RANGE, REF_RANGE",
+      "severity": "low (out-of-spec reference)"
+    },
+    "DEV-14-CLK67-NOT-ENABLED": {
+      "title": "set_freq() on CLK6/CLK7 never enables the output (reg 3 OEB bit stays 1)",
+      "library": "CLK0-5 branch calls output_enable(clk,1) on first set; CLK6/7 branch has no output_enable(); reset() disabled all outputs",
+      "spec": "AN619 Reg 3 CLKx_OEB: 1 = output disabled",
+      "rules": "OUTPUT_ENABLED_AFTER_SET",
+      "severity": "medium (functional; recommend hardware confirmation)"
+    },
+    "DEV-15-MANUAL-CLK67": {
+      "title": "set_freq_manual() on CLK6/7 writes a truncated fractional-MS P1 to reg 90/91",
+      "library": "set_freq_manual(87.4 MHz, 874 MHz, CLK7): multisynth_calc gives a=10,b=0,c=1 -> P1=128*10-512=768; set_ms writes (uint8_t)768 = 0x00 to reg 91",
+      "spec": "AN619 \u00a74.1.2 / Reg 91: 'For MS6 and MS7, set MSx_P1 directly (e.g., MSx_P1 = divide value)' -> 10 (0x0A)",
+      "rules": "MS67_RATIO_VALID, OUT_FREQ_ACCURACY",
+      "severity": "high (silent wrong output)"
+    }
+  },
+  "known_deviation_cases": {
+    "P0-clk6-23MHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-clk7-874MHz-even-div-of-clk6-pll": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-vcxo-manual-146MHz-on-876pll": {
+      "devs": [
+        "DEV-07-VCXO-CENTER-112M5"
+      ],
+      "rules": [
+        "VCXO_CENTER_MAX"
+      ]
+    },
+    "S-clk6-R6div-100kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk7-R7div-50kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk6-150MHz-upper-clamp": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "D-clk0-210MHz-above-spec-max": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-250MHz-clamped-to-225": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_ACCURACY",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-2p5kHz-clamped-to-4kHz": {
+      "devs": [
+        "DEV-02-FOUT-MIN-4K"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-clk6-10kHz-ms6-p1-zero": {
+      "devs": [
+        "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUTPUT_ENABLED_AFTER_SET",
+        "OUT_FREQ_ACCURACY",
+        "VCO_REQUEST_RANGE"
+      ]
+    },
+    "D-manual-100MHz-pll700-ratio7": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-90MHz-pll600-ratio6p67": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-140MHz-pll700-stale-a5": {
+      "devs": [
+        "DEV-05-MS-STALE-A"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-175MHz-pll800-divby4-precondition": {
+      "devs": [
+        "DEV-06-DIVBY4-PRECONDITION"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-vcxo-then-set_correction-clobbers-pllb": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED",
+        "VCXO_PLL_PRESERVED"
+      ]
+    },
+    "D-vcxo-875MHz-then-manual-rewrites-c1": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED"
+      ]
+    },
+    "D-manual-clk7-87p4MHz-p1-truncated": {
+      "devs": [
+        "DEV-15-MANUAL-CLK67"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-set_phase-clk6-writes-reserved-171": {
+      "devs": [
+        "DEV-09-PHOFF-CLK67"
+      ],
+      "rules": [
+        "PHOFF_ADDR"
+      ]
+    },
+    "D-init-crystal-load-0pF-reserved": {
+      "devs": [
+        "DEV-10-XTAL-CL-0PF"
+      ],
+      "rules": [
+        "XTAL_CL_RESERVED"
+      ]
+    },
+    "D-set_int-clk6-sets-FBA_INT-on-fractional-plla": {
+      "devs": [
+        "DEV-11-SET_INT-CLK67-IS-FB_INT"
+      ],
+      "rules": [
+        "FB_INT_ONLY_EVEN_INT"
+      ]
+    },
+    "D-set_pll_input-clkin_div-or-without-clear": {
+      "devs": [
+        "DEV-12-CLKIN-DIV-RMW"
+      ],
+      "rules": [
+        "CLKIN_DIV_FIELD"
+      ]
+    },
+    "D-ref5MHz-pll_calc-stale-a160": {
+      "devs": [
+        "DEV-13-PLL-STALE-A"
+      ],
+      "rules": [
+        "FB_RATIO_RANGE",
+        "REF_RANGE"
+      ]
+    }
+  },
+  "original_case_count": 27,
+  "new_case_count": 29,
+  "case_count": 56,
+  "cases": [
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-1-14MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-2-10MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 38,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 38,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 700000000,
+      "input_freq_hz": 7000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 700000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 114,
+      "ms_b": 285714,
+      "ms_c": 1000000,
+      "ms_p1": 14116,
+      "ms_p2": 571392,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        55,
+        36,
+        248,
+        184,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-3-7MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 55,
+        "46": 36,
+        "47": 248,
+        "48": 184,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 55,
+          "46": 36,
+          "47": 248,
+          "48": 184,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 7000000.0175,
+        "ms_ratio": "57142857/500000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[14116, 571392, 1000000] spec=[14116, 571392, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=14116 P2=571392 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=114.285714000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=7000000.018 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=7000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=7000000.017500 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 2800000000,
+      "input_freq_hz": 28000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2800000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 28,
+      "ms_b": 571428,
+      "ms_c": 1000000,
+      "ms_p1": 3145,
+      "ms_p2": 142784,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        12,
+        73,
+        242,
+        45,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-4-28MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 12,
+        "46": 73,
+        "47": 242,
+        "48": 45,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 12,
+          "46": 73,
+          "47": 242,
+          "48": 45,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 28000000.56000001,
+        "ms_ratio": "7142857/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[3145, 142784, 1000000] spec=[3145, 142784, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3145 P2=142784 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=28.571428000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=28000000.560 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=28000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=28000000.560000 Hz err=20.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1600000000,
+      "input_freq_hz": 16000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1600000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 50,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 5888,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        23,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-integer-MS-16MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "integer_MS",
+        "b_eq_0"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 23,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 23,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 16000000.0,
+        "ms_ratio": "50",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[5888, 0, 1] spec=[5888, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=5888 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=50.000000000 (=50)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 50 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=16000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1407000000,
+      "input_freq_hz": 14070000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1407000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 56,
+      "ms_b": 858564,
+      "ms_c": 1000000,
+      "ms_p1": 6765,
+      "ms_p2": 896192,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        109,
+        253,
+        172,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-fractional-MS-14p07MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_MS"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 109,
+        "47": 253,
+        "48": 172,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 109,
+          "47": 253,
+          "48": 172,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14070000.0794955,
+        "ms_ratio": "14214641/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6765, 896192, 1000000] spec=[6765, 896192, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6765 P2=896192 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=56.858564000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14070000.079 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14070000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14070000.079496 Hz err=5.650 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 840000,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 520000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        247,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-clk0-gt100MHz-recalc-pll-112MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "recalc_pll",
+        "gt_SHARE_MAX"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 247,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112000000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 896000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 520000, 1000000] spec=[4075, 520000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=520000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.840000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=896000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "P0-manual-DIVBY4-175MHz-pll700",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "int_mode",
+        "set_freq_manual",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "pll_assignment": "PLLB",
+      "lib_ms_regs": {
+        "50": 0,
+        "51": 1,
+        "52": 12,
+        "53": 0,
+        "54": 0,
+        "55": 0,
+        "56": 0,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 108
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 12,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 0,
+          "51": 1,
+          "52": 12,
+          "53": 0,
+          "54": 0,
+          "55": 0,
+          "56": 0,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 108
+        },
+        "realized_hz": 175000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0} spec={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 108} spec={'17': 108}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=175000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=175000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=175000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-boundary-150MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll",
+        "a_eq_4"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 150000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=150000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-200MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk1-PLLB-14MHz",
+      "priority": "P0",
+      "covers": [
+        "PLLB_assignment",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "lib_ms_regs": {
+        "50": 66,
+        "51": 64,
+        "52": 0,
+        "53": 26,
+        "54": 146,
+        "55": 244,
+        "56": 92,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 44
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 66,
+          "51": 64,
+          "52": 0,
+          "53": 26,
+          "54": 146,
+          "55": 244,
+          "56": 92,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 44
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0} spec={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 44} spec={'17': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 31,
+      "pll_b": 996800,
+      "pll_c": 1000000,
+      "pll_p1": 3583,
+      "pll_p2": 590400,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr-100000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 31,
+        "pll_b": 996800,
+        "pll_c": 1000000,
+        "pll_p1": 3583,
+        "pll_p2": 590400,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          13,
+          255,
+          249,
+          2,
+          64
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 13,
+        "30": 255,
+        "31": 249,
+        "32": 2,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 13999999.895,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999992.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3583, 590400, 1000000] spec=[3583, 590400, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3583 P2=590400 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=31.996800000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999992.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=13999999.895 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=13999999.895000 Hz err=-7.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": -50000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 1600,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 204800,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr--50000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 32,
+        "pll_b": 1600,
+        "pll_c": 1000000,
+        "pll_p1": 3584,
+        "pll_p2": 204800,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          14,
+          0,
+          243,
+          32,
+          0
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 243,
+        "32": 32,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.0,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999998.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 204800, 1000000] spec=[3584, 204800, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=204800 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.001600000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999998.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 836416,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 61248,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        240,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-corr-100000-gt100MHz-112MHz",
+      "priority": "P0",
+      "covers": [
+        "correction_factor",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 240,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 111999998.88,
+        "ms_ratio": "8",
+        "fvco_hz": 895999991.04,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 61248, 1000000] spec=[4075, 61248, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=61248 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.836416000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=895999991.040 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=111999998.880 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=111999998.880000 Hz err=-10.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "P0-rdiv-128-5kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "select_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 114,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 114,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 98,
+      "pll_reset": false,
+      "id": "P0-rdiv-64-10kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 98,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 98,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 3,
+      "r_div_name": "DIV_8",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 49,
+      "pll_reset": false,
+      "id": "P0-rdiv-8-100kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 49,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 49,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 40000000,
+      "input_freq_hz": 400000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 1,
+      "r_div_name": "DIV_2",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 17,
+      "pll_reset": false,
+      "id": "P0-rdiv-2-400kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 17,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 17,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 400000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 51200000,
+      "input_freq_hz": 512000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 3,
+      "pll_reset": false,
+      "id": "P0-rdiv-1-512kHz-boundary",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "no_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 3,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 3,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 512000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=512000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 2300000000,
+      "input_freq_hz": 23000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2300000000,
+      "ms_a": 38,
+      "ms_p1": 38,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "clk67_ms_register_byte": 38,
+      "id": "P0-clk6-23MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "multisynth67_calc",
+        "PLLB"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 38
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 38
+        },
+        "spec_ms67_regs": {
+          "90": 38
+        },
+        "spec_reg92": 0,
+        "realized_hz": 23000000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=38"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 38} spec={'90': 38}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=23000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=23000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "peer_already_set",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "ms_a": 10,
+      "ms_p1": 10,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "clk67_ms_register_byte": 10,
+      "id": "P0-clk7-874MHz-even-div-of-clk6-pll",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "peer_even_integer"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 10
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": 87400000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=10"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 10} spec={'91': 10}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1234567800,
+      "input_freq_hz": 12345678.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": true,
+      "reason": "peer_requires_even_integer_divide_of_pllb",
+      "id": "P0-clk7-reject-noninteger-12p345678MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "reject_path"
+      ],
+      "clk": 7,
+      "spec": {
+        "spec_expectation": "reject: requested freq is not an even-integer division of PLLB",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "MS67_REJECT_CONSISTENT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note (even integers 6..254 only)",
+            "detail": "library rejected (peer_requires_even_integer_divide_of_pllb)"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 40,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 184577,
+      "vcxo_bytes": [
+        1,
+        209,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 1,
+        "VXCO_PARAMETERS_MID(163)": 209,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "P0-vcxo-876MHz-40ppm",
+      "priority": "P0",
+      "covers": [
+        "set_vcxo",
+        "PLLB",
+        "vcxo_param"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 1,
+        "163": 209,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 184577.648,
+        "spec_vcxo_floor": 184577,
+        "spec_vcxo_round": 184578,
+        "spec_vcxo_regs": {
+          "162": 1,
+          "163": 209,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=40 requested=40"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=184577 spec=184577"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 1, '163': 209, '164': 2} spec={'162': 1, '163': 209, '164': 2}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=184577.6480: library floors to 184577; round-half-up would give 184578"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14600000000,
+      "input_freq_hz": 146000000.0,
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 256,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "P0-vcxo-manual-146MHz-on-876pll",
+      "priority": "P0",
+      "covers": [
+        "set_freq_manual",
+        "VCXO_companion",
+        "near_DIVBY4"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 146000000.0,
+        "ms_ratio": "6",
+        "fvco_hz": 876000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_CENTER_MAX"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-07-VCXO-CENTER-112M5"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[256, 0, 1] spec=[256, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=256 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.000000000 (=6)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 6 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=146000000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=146000000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1000000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-set_freq-vs-manual-14MHz-pll800",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity"
+      ],
+      "api": "parity_check",
+      "description": "For freq<=100 MHz, set_freq uses existing PLL and does not call set_pll; set_freq_manual always calls set_pll(pll_freq). MS a/b/c and p1/p2/p3 must match when the same pll_freq is supplied. Differences: set_freq_manual always output_enable(1); set_freq enables only on first set. set_freq skips pll_reset in <=100 MHz branch; set_freq_manual does not reset either.",
+      "auto_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "manual_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "ms_match": true,
+      "manual_also_writes_pll": true,
+      "manual_pll": {
+        "a": 32,
+        "b": 0,
+        "c": 1,
+        "p1": 3584,
+        "p2": 0,
+        "p3": 1
+      },
+      "clk": 0,
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_MS_MATCH",
+            "ok": true,
+            "severity": "error",
+            "cite": "library parity (no spec rule)",
+            "detail": ""
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-gt100-set_freq-vs-manual-175MHz",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity",
+        "DIVBY4"
+      ],
+      "api": "parity_check",
+      "description": "set_freq(175 MHz) chooses pll_freq via multisynth_calc(freq,0) \u2192 a=4, pll=700 MHz. set_freq_manual(175 MHz, 700 MHz) must yield identical MS p1/p2/p3, div_by_4=1, int_mode=1 and identical PLL a/b/c when correction matches.",
+      "auto": {
+        "api": "set_freq",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_assignment": "PLLA",
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "branch": "recalc_pll_gt_100mhz",
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12,
+        "pll_reset": true
+      },
+      "manual": {
+        "api": "set_freq_manual",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12
+      },
+      "ms_match": true,
+      "pll_match": true,
+      "clk": 0,
+      "spec": {
+        "auto_status": "agree",
+        "manual_status": "agree",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_SPEC_REGS_EQUAL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2/\u00a74.1.3",
+            "detail": "spec MS registers for auto vs manual"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-reset-pll-fixed-800MHz",
+      "priority": "P1",
+      "covers": [
+        "reset",
+        "SI5351_PLL_FIXED",
+        "set_pll"
+      ],
+      "api": "set_pll",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "note": "reset() calls set_pll(SI5351_PLL_FIXED) for both PLLA and PLLB",
+      "clk": 0,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=25000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-reset-pll-blocks-and-reg177",
+      "priority": "S",
+      "api": "reset_plls",
+      "covers": [
+        "MSNA regs 26-33",
+        "MSNB regs 34-41",
+        "PLL reset reg 177",
+        "CLK ctrl regs 16-23"
+      ],
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_plla_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "lib_pllb_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "lib_reg177_writes": [
+        32,
+        128
+      ],
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_PLL_BLOCK_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "REG_PLL_BLOCK_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_177",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 177 (PLLB_RST bit7, PLLA_RST bit5)",
+            "detail": "library=[32, 128] spec=[32, 128]"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-23 (PDN=0, INT=0, SRC per PLL, CLK_SRC=11 own MS, 2 mA)",
+            "detail": "library={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44} spec={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "S-ms5-block-10MHz-clk5",
+      "priority": "S",
+      "covers": [
+        "MS5 regs 82-89 address offset",
+        "reg 21"
+      ],
+      "clk": 5,
+      "lib_ms_regs": {
+        "82": 0,
+        "83": 1,
+        "84": 0,
+        "85": 38,
+        "86": 0,
+        "87": 0,
+        "88": 0,
+        "89": 0
+      },
+      "lib_clk_ctrl": {
+        "21": 12
+      },
+      "lib_reg3_after": 223,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "82": 0,
+          "83": 1,
+          "84": 0,
+          "85": 38,
+          "86": 0,
+          "87": 0,
+          "88": 0,
+          "89": 0
+        },
+        "spec_clk_ctrl": {
+          "21": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0} spec={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'21': 12} spec={'21': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xDF"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "S-rdiv-placement-clk2-5kHz",
+      "priority": "S",
+      "covers": [
+        "R2_DIV bits 6:4 of reg 60",
+        "MS2 regs 58-65"
+      ],
+      "clk": 2,
+      "lib_ms_regs": {
+        "58": 0,
+        "59": 1,
+        "60": 114,
+        "61": 111,
+        "62": 0,
+        "63": 0,
+        "64": 0,
+        "65": 0
+      },
+      "lib_clk_ctrl": {
+        "18": 12
+      },
+      "lib_reg3_after": 251,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "58": 0,
+          "59": 1,
+          "60": 114,
+          "61": 111,
+          "62": 0,
+          "63": 0,
+          "64": 0,
+          "65": 0
+        },
+        "spec_clk_ctrl": {
+          "18": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0} spec={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'18': 12} spec={'18': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFB"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "S-divby4-block-clk3-200MHz",
+      "priority": "S",
+      "covers": [
+        "MS3_DIVBY4 bits 3:2 of reg 68",
+        "MS3_INT reg 19 bit6",
+        "MSNA block"
+      ],
+      "clk": 3,
+      "lib_ms_regs": {
+        "66": 0,
+        "67": 1,
+        "68": 12,
+        "69": 0,
+        "70": 0,
+        "71": 0,
+        "72": 0,
+        "73": 0
+      },
+      "lib_clk_ctrl": {
+        "19": 76
+      },
+      "lib_reg3_after": 247,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "66": 0,
+          "67": 1,
+          "68": 12,
+          "69": 0,
+          "70": 0,
+          "71": 0,
+          "72": 0,
+          "73": 0
+        },
+        "spec_clk_ctrl": {
+          "19": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0} spec={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'19': 76} spec={'19': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xF7"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11250000000,
+      "input_freq_hz": 112500000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "S-boundary-112p5MHz-ratio8",
+      "priority": "S",
+      "covers": [
+        "AN619 2.1.1 900/8 boundary",
+        "integer ratio 8"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112500000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112500000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 5,
+      "r_div_name": "DIV_32",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk6-R6div-100kHz",
+      "priority": "S",
+      "covers": [
+        "R6_DIV bits 2:0 of reg 92",
+        "reg 90"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 254
+      },
+      "lib_reg92": 5,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 254
+        },
+        "spec_ms67_regs": {
+          "90": 254
+        },
+        "spec_reg92": 5,
+        "realized_hz": 100000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 254} spec={'90': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=5 spec=5"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 5000000,
+      "input_freq_hz": 50000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk7-R7div-50kHz",
+      "priority": "S",
+      "covers": [
+        "R7_DIV bits 6:4 of reg 92",
+        "reg 91"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 254
+      },
+      "lib_reg92": 96,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 254
+        },
+        "spec_ms67_regs": {
+          "91": 254
+        },
+        "spec_reg92": 96,
+        "realized_hz": 50000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 254} spec={'91': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=96 spec=96"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=50000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=50000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 14999999999,
+      "ms_a": 6,
+      "ms_p1": 6,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 89999999994,
+      "pll_freq_hz": 899999999.94,
+      "pll_a": 35,
+      "pll_b": 999999,
+      "pll_c": 1000000,
+      "pll_p1": 4095,
+      "pll_p2": 999872,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        255,
+        255,
+        65,
+        192
+      ],
+      "clk67_ms_register_byte": 6,
+      "id": "S-clk6-150MHz-upper-clamp",
+      "priority": "S",
+      "covers": [
+        "CLK6 upper bound",
+        "MS6 ratio 6"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 6
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 255,
+        "39": 255,
+        "40": 65,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms67_regs": {
+          "90": 6
+        },
+        "spec_reg92": 0,
+        "realized_hz": 149999995.83333334,
+        "fvco_hz": 899999975.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4095, 999872, 1000000] spec=[4095, 999872, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4095 P2=999872 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.999999000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=899999975.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=6"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=899999999.94 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 6} spec={'90': 6}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=149999995.833333 Hz err=-27.778 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "ppm": 100,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        0,
+        240,
+        0,
+        0
+      ],
+      "vcxo_param_raw_from_pll_calc": 4096000000,
+      "vcxo_param": 421888,
+      "vcxo_bytes": [
+        0,
+        112,
+        6
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 0,
+        "VXCO_PARAMETERS_MID(163)": 112,
+        "VXCO_PARAMETERS_HIGH(164)": 6
+      },
+      "id": "S-vcxo-800MHz-100ppm",
+      "priority": "S",
+      "covers": [
+        "VCXO regs 162-164",
+        "c=10^6"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 240,
+        "40": 0,
+        "41": 0
+      },
+      "lib_vcxo_regs": {
+        "162": 0,
+        "163": 112,
+        "164": 6
+      },
+      "spec": {
+        "spec_vcxo_exact": 421888.0,
+        "spec_vcxo_floor": 421888,
+        "spec_vcxo_round": 421888,
+        "spec_vcxo_regs": {
+          "162": 0,
+          "163": 112,
+          "164": 6
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1000000] spec=[3584, 0, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=100 requested=100"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=421888 spec=421888"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 0, '163': 112, '164': 6} spec={'162': 0, '163': 112, '164': 6}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 30,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 138433,
+      "vcxo_bytes": [
+        193,
+        28,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 193,
+        "VXCO_PARAMETERS_MID(163)": 28,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "S-vcxo-ppm-clamp-low-10to30",
+      "priority": "S",
+      "covers": [
+        "VCXO APR min 30"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 10,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 193,
+        "163": 28,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 138433.236,
+        "spec_vcxo_floor": 138433,
+        "spec_vcxo_round": 138433,
+        "spec_vcxo_regs": {
+          "162": 193,
+          "163": 28,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=30 requested=10"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=138433 spec=138433"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 193, '163': 28, '164': 2} spec={'162': 193, '163': 28, '164': 2}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 240,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 1107465,
+      "vcxo_bytes": [
+        9,
+        230,
+        16
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 9,
+        "VXCO_PARAMETERS_MID(163)": 230,
+        "VXCO_PARAMETERS_HIGH(164)": 16
+      },
+      "id": "S-vcxo-ppm-clamp-high-250to240",
+      "priority": "S",
+      "covers": [
+        "VCXO APR max 240"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 250,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 9,
+        "163": 230,
+        "164": 16
+      },
+      "spec": {
+        "spec_vcxo_exact": 1107465.888,
+        "spec_vcxo_floor": 1107465,
+        "spec_vcxo_round": 1107466,
+        "spec_vcxo_regs": {
+          "162": 9,
+          "163": 230,
+          "164": 16
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=240 requested=250"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=1107465 spec=1107465"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 9, '163': 230, '164': 16} spec={'162': 9, '163': 230, '164': 16}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=1107465.8880: library floors to 1107465; round-half-up would give 1107466"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-phase-clk0-mask",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "reg 165",
+        "PHOFF[6:0]"
+      ],
+      "clk": 0,
+      "requested_phase": 255,
+      "lib_write": {
+        "reg": 165,
+        "value": 127
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 165"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x7F"
+          },
+          {
+            "rule": "REG_PHOFF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170",
+            "detail": "library=[165, 127] spec=[165, 127]"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-xtal-load-6-8-10pF",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "reg 183"
+      ],
+      "lib_writes": {
+        "6pF": 82,
+        "8pF": 146,
+        "10pF": 210
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_183_6pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=82 spec=82"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "6pF: reg183=0x52"
+          },
+          {
+            "rule": "REG_183_8pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=146 spec=146"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "8pF: reg183=0x92"
+          },
+          {
+            "rule": "REG_183_10pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=210 spec=210"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "10pF: reg183=0xD2"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 21000000000,
+      "input_freq_hz": 210000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 84000000000,
+      "pll_freq_hz": 840000000.0,
+      "pll_a": 33,
+      "pll_b": 600000,
+      "pll_c": 1000000,
+      "pll_p1": 3788,
+      "pll_p2": 800000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        204,
+        252,
+        53,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-210MHz-above-spec-max",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 204,
+        "31": 252,
+        "32": 53,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 210000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 840000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3788, 800000, 1000000] spec=[3788, 800000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3788 P2=800000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=33.600000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=840000000.000 Hz"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=210000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=210000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=210000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=210000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 25000000000,
+      "input_freq_hz": 250000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-250MHz-clamped-to-225",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz",
+        "clamp"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 225000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_ACCURACY",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=225000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=225000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=250000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=225000000.000000 Hz err=-100000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 250000,
+      "input_freq_hz": 2500.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 115,
+      "pll_reset": false,
+      "id": "D-clk0-2p5kHz-clamped-to-4kHz",
+      "priority": "S",
+      "covers": [
+        "Fout min 2.5 kHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 115,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 115,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 4000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-02-FOUT-MIN-4K"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=2500.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=4000.000000 Hz err=600000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 400000,
+      "ms_a": 256,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 12800000000,
+      "pll_freq_hz": 128000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "clk67_ms_register_byte": 0,
+      "pllb_freq_member_lib": 12800000000,
+      "id": "D-clk6-10kHz-ms6-p1-zero",
+      "priority": "S",
+      "covers": [
+        "MS6 even 6..254",
+        "uint8 truncation"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 10,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUTPUT_ENABLED_AFTER_SET",
+          "OUT_FREQ_ACCURACY",
+          "VCO_REQUEST_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=128000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS6_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000000,
+      "input_freq_hz": 100000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 7,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 384,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-100MHz-pll700-ratio7",
+      "priority": "S",
+      "covers": [
+        "MS ratio 7 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000000.0,
+        "ms_ratio": "7",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[384, 0, 1] spec=[384, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=384 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=7.000000000 (=7)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 9000000000,
+      "input_freq_hz": 90000000.0,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 666666,
+      "ms_c": 1000000,
+      "ms_p1": 341,
+      "ms_p2": 333248,
+      "ms_p3": 1000000,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        1,
+        85,
+        245,
+        21,
+        192
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-90MHz-pll600-ratio6p67",
+      "priority": "S",
+      "covers": [
+        "MS fractional ratio < 8 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 1,
+        "46": 85,
+        "47": 245,
+        "48": 21,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 1,
+          "46": 85,
+          "47": 245,
+          "48": 21,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 90000009.0000009,
+        "ms_ratio": "3333333/500000",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[341, 333248, 1000000] spec=[341, 333248, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=341 P2=333248 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.666666000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=90000009.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=90000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=90000009.000001 Hz err=100.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14000000000,
+      "input_freq_hz": 140000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 5,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 128,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-140MHz-pll700-stale-a5",
+      "priority": "S",
+      "covers": [
+        "multisynth_calc stale a after a<6 clamp"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 0,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 0,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 140000000.0,
+        "ms_ratio": "5",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-05-MS-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[128, 0, 1] spec=[128, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=128 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=5.000000000 (=5)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=140000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "D-manual-175MHz-pll800-divby4-precondition",
+      "priority": "S",
+      "covers": [
+        "DIVBY4 requires fVCO = 4*Fout"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-06-DIVBY4-PRECONDITION"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=142857142.857 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-vcxo-then-set_correction-clobbers-pllb",
+      "priority": "S",
+      "api": "vcxo_sequence",
+      "covers": [
+        "set_vcxo does not update pllb_freq",
+        "VCXO c=10^6"
+      ],
+      "sequence": [
+        "reset()",
+        "set_vcxo(87600000000ULL, 40)",
+        "set_correction(0, SI5351_PLL_INPUT_XO)"
+      ],
+      "vcxo_context": true,
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 40000,
+        "c": 1000000,
+        "p1": 3973,
+        "p2": 120000,
+        "p3": 1000000
+      },
+      "pllb_freq_member_lib": 80000000000,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED",
+          "VCXO_PLL_PRESERVED"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3 after sequence=1"
+          },
+          {
+            "rule": "VCXO_PLL_PRESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (PLLB is the VCXO)",
+            "detail": "MSNB ratio after set_vcxo=35.04 after sequence=32.0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 8750000000,
+      "input_freq_hz": 87500000.0,
+      "pll_freq_lib": 87500000000,
+      "pll_freq_hz": 875000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        15,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "sequence": [
+        "reset()",
+        "set_vcxo(87500000000ULL, 40)",
+        "set_ms_source(SI5351_CLK0, SI5351_PLLB)",
+        "set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0)"
+      ],
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 0,
+        "c": 1000000,
+        "p1": 3968,
+        "p2": 0,
+        "p3": 1000000
+      },
+      "id": "D-vcxo-875MHz-then-manual-rewrites-c1",
+      "priority": "S",
+      "covers": [
+        "VCXO c=10^6 lost via set_pll"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 3,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 15,
+        "38": 128,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 3,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 87500000.0,
+        "ms_ratio": "10",
+        "fvco_hz": 875000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3968, 0, 1] spec=[3968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=875000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[768, 0, 1] spec=[768, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=768 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=10.000000000 (=10)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 10 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87500000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=87500000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-clk7-87p4MHz-p1-truncated",
+      "priority": "S",
+      "clk": 7,
+      "pll_assignment": "PLLB",
+      "covers": [
+        "set_freq_manual on CLK6/7",
+        "reg 91"
+      ],
+      "sequence": [
+        "reset()",
+        "set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7)"
+      ],
+      "lib_ms67_regs": {
+        "91": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 127,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-15-MANUAL-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0x7F"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS7_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_phase-clk6-writes-reserved-171",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "phase regs only CLK0-5"
+      ],
+      "clk": 6,
+      "requested_phase": 10,
+      "lib_write": {
+        "reg": 171,
+        "value": 10
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "PHOFF_ADDR"
+        ],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-09-PHOFF-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 171"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x0A"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-init-crystal-load-0pF-reserved",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "XTAL_CL=00 reserved"
+      ],
+      "lib_writes": {
+        "0pF": 18
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "XTAL_CL_RESERVED"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-10-XTAL-CL-0PF"
+        ],
+        "checks": [
+          {
+            "rule": "REG_183_0pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=18 spec=18"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "0pF: reg183=0x12"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_int-clk6-sets-FBA_INT-on-fractional-plla",
+      "priority": "S",
+      "api": "set_int",
+      "covers": [
+        "reg 22 bit6 = FBA_INT"
+      ],
+      "clk": 6,
+      "sequence": [
+        "reset()",
+        "set_correction(100000, SI5351_PLL_INPUT_XO)",
+        "set_int(SI5351_CLK6, 1)"
+      ],
+      "lib_write": {
+        "reg": 22,
+        "value": 108
+      },
+      "plla": {
+        "a": 31,
+        "b": 996800,
+        "c": 1000000,
+        "p1": 3583,
+        "p2": 590400,
+        "p3": 1000000
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "FB_INT_ONLY_EVEN_INT"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-11-SET_INT-CLK67-IS-FB_INT"
+        ],
+        "checks": [
+          {
+            "rule": "FB_INT_ONLY_EVEN_INT",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2.1 / Reg 22 bit6 FBA_INT (only for even-integer a+b/c)",
+            "detail": "reg22=0x6C -> FBA_INT=1; MSNA ratio=31.996800000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_pll_input-clkin_div-or-without-clear",
+      "priority": "S",
+      "api": "set_pll_input",
+      "covers": [
+        "reg 15 CLKIN_DIV[1:0]"
+      ],
+      "sequence": [
+        "(reg15 = 0x44 from earlier CLKIN @ 40 MHz)",
+        "set_ref_freq(80000000, CLKIN)",
+        "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"
+      ],
+      "prior_reg15": 68,
+      "intended_clkin_div": 4,
+      "lib_write": {
+        "reg": 15,
+        "value": 196
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "CLKIN_DIV_FIELD"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-12-CLKIN-DIV-RMW"
+        ],
+        "checks": [
+          {
+            "rule": "CLKIN_DIV_FIELD",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 15 CLKIN_DIV[1:0]",
+            "detail": "reg15=0xC4 -> CLKIN_DIV=11b (/8); intended /4"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-ref5MHz-pll_calc-stale-a160",
+      "priority": "S",
+      "api": "set_pll",
+      "covers": [
+        "feedback ratio 15..90",
+        "PLL input 10..40 MHz"
+      ],
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 5000000, 0)  -> reset() -> set_pll(800 MHz)"
+      ],
+      "pll_freq_lib": 80000000000,
+      "xtal_hz": 5000000,
+      "correction_ppb": 0,
+      "pll_a": 160,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 19968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_calc_return_lib": 80000000000,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 78,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "FB_RATIO_RANGE",
+          "REF_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-13-PLL-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[19968, 0, 1] spec=[19968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=19968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=160.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 160 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=5000000 Hz"
+          }
+        ]
+      }
+    }
+  ]
+}
\ No newline at end of file
diff --git a/tests/regression/equiv/orig27_ids.json b/tests/regression/equiv/orig27_ids.json
new file mode 100644
index 0000000..d3cd2cd
--- /dev/null
+++ b/tests/regression/equiv/orig27_ids.json
@@ -0,0 +1 @@
+["P0-clk0-common-1-14MHz", "P0-clk0-common-2-10MHz", "P0-clk0-common-3-7MHz", "P0-clk0-common-4-28MHz", "P0-clk0-integer-MS-16MHz", "P0-clk0-fractional-MS-14p07MHz", "P0-clk0-gt100MHz-recalc-pll-112MHz", "P0-manual-DIVBY4-175MHz-pll700", "P0-clk0-DIVBY4-boundary-150MHz", "P0-clk0-DIVBY4-200MHz", "P0-clk1-PLLB-14MHz", "P0-corr-100000-14MHz-existing-pll", "P0-corr--50000-14MHz-existing-pll", "P0-corr-100000-gt100MHz-112MHz", "P0-rdiv-128-5kHz", "P0-rdiv-64-10kHz", "P0-rdiv-8-100kHz", "P0-rdiv-2-400kHz", "P0-rdiv-1-512kHz-boundary", "P0-clk6-23MHz", "P0-clk7-874MHz-even-div-of-clk6-pll", "P0-clk7-reject-noninteger-12p345678MHz", "P0-vcxo-876MHz-40ppm", "P0-vcxo-manual-146MHz-on-876pll", "P1-parity-set_freq-vs-manual-14MHz-pll800", "P1-parity-gt100-set_freq-vs-manual-175MHz", "P1-reset-pll-fixed-800MHz"]
\ No newline at end of file
diff --git a/tests/regression/golden_cases.json b/tests/regression/golden_cases.json
new file mode 100644
index 0000000..aaae83b
--- /dev/null
+++ b/tests/regression/golden_cases.json
@@ -0,0 +1,11747 @@
+{
+  "source_repo": "https://github.com/etherkit/Si5351Arduino",
+  "source_commit": "0559cbf82865e2957d46af72e70cc88207421434",
+  "source_ref": "master",
+  "library_version": "2.2.0",
+  "spec_sources": {
+    "AN619": "AN619 Rev 0.8 (2021-09-23) Manually Generating an Si5351 Register Map for 10-MSOP and 20-QFN Devices",
+    "DS": "Si5351A/B/C-B datasheet Rev 1.3 (2021-08-27)"
+  },
+  "assumptions": {
+    "xtal_hz_default": 25000000,
+    "freq_mult": 100,
+    "pll_fixed_lib": 80000000000,
+    "rfrac_denom": 1000000,
+    "correction_default_ppb": 0,
+    "freq_units": "API takes Hz * 100 (SI5351_FREQ_MULT)",
+    "init_xo_freq_0_means": "SI5351_XTAL_FREQ (25 MHz)",
+    "unknown_prior_register_bits": "assumed 0 (reg 44-style byte bit7, reg 92, reg 3 before reset)",
+    "spec_bc_choice": "spec does not prescribe b/c selection; spec registers are encoded from the library's a/b/c",
+    "accuracy_tolerance_ppb": 1000
+  },
+  "golden_corrections": [
+    {
+      "cases": [
+        "P0-clk0-DIVBY4-200MHz",
+        "P0-clk0-DIVBY4-boundary-150MHz",
+        "P0-manual-DIVBY4-175MHz-pll700",
+        "P1-parity-gt100-set_freq-vs-manual-175MHz (embedded auto/manual)"
+      ],
+      "field": "ms_a",
+      "old": 6,
+      "new": 4,
+      "reason": "multisynth_calc(freq, pll_freq) sees a = pll/freq = 4 < SI5351_MULTISYNTH_A_MIN, clamps freq = pll/6 but does NOT recompute a. The first-draft mirror recomputed a (=6). Registers were never affected because DIVBY4 overrides P1/P2/P3 to 0/0/1; only the reported intermediate changes. Mirror now matches library exactly (also fixes the same pattern in pll_calc)."
+    }
+  ],
+  "deviation_catalog": {
+    "DEV-01-FOUT-MAX-225": {
+      "title": "Library accepts CLK0-5 output up to 225 MHz; spec max is 200 MHz",
+      "library": "SI5351_MULTISYNTH_MAX_FREQ = 225000000; set_freq clamps to 225 MHz, programs DIVBY4 with fVCO=4*Fout (e.g. 210 MHz -> VCO 840 MHz, 250 MHz request -> 225 MHz/VCO 900 MHz)",
+      "spec": "DS Table 7 FCLK max 200 MHz; AN619 \u00a72 MS output 500 kHz-200 MHz; AN619 \u00a74.1.3 DIVBY4 range 150 < Fout <= 200 MHz",
+      "rules": "OUT_FREQ_RANGE, MS_OUT_RANGE (+OUT_FREQ_ACCURACY when clamped)",
+      "severity": "medium"
+    },
+    "DEV-02-FOUT-MIN-4K": {
+      "title": "Library min CLK0-5 output is 4 kHz; datasheet min is 2.5 kHz",
+      "library": "SI5351_CLKOUT_MIN_FREQ = 4000; 2.5 kHz request silently becomes 4 kHz (R=128, MS 512 kHz)",
+      "spec": "DS Table 7 FCLK min 0.0025 MHz; AN619 \u00a72 'down to 2.5 kHz' (note AN619 \u00a74.2.2 says 8 kHz: docs disagree)",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "low (conservative)"
+    },
+    "DEV-03-CLK67-LOWFREQ-P1-TRUNC": {
+      "title": "CLK6/7 low-frequency request writes MS6_P1 = 0 (uint8 truncation of 256)",
+      "library": "set_freq(<18.454 kHz, CLK6/7) clamps to 4 kHz (CLKOUT_MIN, not CLKOUT67_MIN), select_r_div_ms67 picks R=1, multisynth67_calc clamps to 500 kHz, a=254 -> PLL 127 MHz < VCO_MIN -> a+=2 = 256 -> reg->p1=(uint8_t)256 = 0; set_pll(128 MHz) is clamped to 600 MHz inside pll_calc but pllb_freq stores 128 MHz",
+      "spec": "AN619 Reg 90/91: MS6/7 ratio even integer 6..254; AN619 \u00a72 VCO 600-900 MHz",
+      "rules": "MS67_RATIO_VALID, VCO_REQUEST_RANGE, OUT_FREQ_ACCURACY",
+      "severity": "high"
+    },
+    "DEV-04-MS-RATIO-6-TO-8": {
+      "title": "Library permits output MS ratios in [6,8) other than 6 (odd 7, fractional 6.x, 7.x)",
+      "library": "multisynth_calc(freq, pll_freq) only clamps a<6 / a>1800; set_freq_manual(100 MHz, 700 MHz) -> ratio 7; (90 MHz, 600 MHz) -> 6.666666",
+      "spec": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2: valid ratios 4, 6, 8, or 8+1/1048575 .. 2048",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium (set_freq_manual / mixed-PLL scenarios)"
+    },
+    "DEV-05-MS-STALE-A": {
+      "title": "multisynth_calc keeps stale a after the a<6 clamp -> programs ratio 5",
+      "library": "a = pll/freq = 5; freq = pll/6 but a is not recomputed; b = 0 -> P1 = 128 (ratio 5). set_freq_manual(140 MHz, 700 MHz)",
+      "spec": "AN619 \u00a72.1.1: ratio 5 invalid",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium"
+    },
+    "DEV-06-DIVBY4-PRECONDITION": {
+      "title": "set_freq_manual forces DIVBY4 for Fout >= 150 MHz regardless of pll_freq",
+      "library": "set_freq_manual(175 MHz, 800 MHz) writes DIVBY4 (P=0,0,1) -> actual output 200 MHz",
+      "spec": "AN619 \u00a74.1.3 'Set the appropriate feedback Multisynth to generate fVCO = Fout*4'",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "medium (documented 'track settings yourself' API)"
+    },
+    "DEV-07-VCXO-CENTER-112M5": {
+      "title": "VCXO-linked output above 112.5 MHz (library example si5351_vcxo.ino uses 146 MHz)",
+      "library": "No check; example tunes CLK0 = 146 MHz on VCXO PLLB 876 MHz",
+      "spec": "DS \u00a74.2 'Multisynth ... synthesizes the VCXO output's center frequency up to 112.5 MHz'",
+      "rules": "VCXO_CENTER_MAX",
+      "severity": "low (example/precondition)"
+    },
+    "DEV-08-VCXO-C-NOT-PRESERVED": {
+      "title": "VCXO requirement c = 10^6 on MSNB is lost after later set_pll() calls",
+      "library": "set_vcxo() does not update pllb_freq; set_correction()/set_pll_input() re-run set_pll(pllb_freq=800 MHz) -> MSNB a=32,b=0,c=1. set_freq_manual(..., 875 MHz) after set_vcxo(875 MHz) re-runs non-VCXO pll_calc -> b=0 -> c=1",
+      "spec": "AN619 \u00a73.2 & \u00a77: 'Feedback B Multisynth divider ratio must be set such that ... c ... is fixed to 10^6'",
+      "rules": "VCXO_C_FIXED, VCXO_PLL_PRESERVED",
+      "severity": "medium"
+    },
+    "DEV-09-PHOFF-CLK67": {
+      "title": "set_phase(CLK6/7) writes reserved registers 171/172",
+      "library": "si5351_write(SI5351_CLK0_PHASE_OFFSET + clk, phase) with no clk bound",
+      "spec": "AN619 \u00a76 & Reg 165-170: phase offset only for CLK0-5; 171-176 Reserved",
+      "rules": "PHOFF_ADDR",
+      "severity": "low"
+    },
+    "DEV-10-XTAL-CL-0PF": {
+      "title": "SI5351_CRYSTAL_LOAD_0PF writes reserved XTAL_CL = 00b",
+      "library": "init(SI5351_CRYSTAL_LOAD_0PF, ...) -> reg183 = 0x12",
+      "spec": "AN619 Reg 183: XTAL_CL 00 'Reserved. Do not select this option.'",
+      "rules": "XTAL_CL_RESERVED",
+      "severity": "low"
+    },
+    "DEV-11-SET_INT-CLK67-IS-FB_INT": {
+      "title": "set_int(CLK6/7) toggles FBA_INT/FBB_INT (reg 22/23 bit 6), not an MS6/7 integer bit",
+      "library": "set_int() writes bit 6 of SI5351_CLK0_CTRL+clk for any clk; on fractional PLLA this forces MSNA integer mode",
+      "spec": "AN619 Reg 22/23 bit 6 = FBA_INT/FBB_INT; \u00a73.2.1 only for even-integer feedback; \u00a74.1.2.1 MS6/7 have no INT bit",
+      "rules": "FB_INT_ONLY_EVEN_INT",
+      "severity": "medium"
+    },
+    "DEV-12-CLKIN-DIV-RMW": {
+      "title": "set_pll_input ORs CLKIN_DIV into reg 15 without clearing the old field",
+      "library": "reg_val |= clkin_div (the &= ~SI5351_CLKIN_DIV_MASK line is commented out): prior /2 (01b) + new /4 (10b) -> 11b = /8",
+      "spec": "AN619 Reg 15 CLKIN_DIV[1:0] is a 2-bit field (00 /1, 01 /2, 10 /4, 11 /8)",
+      "rules": "CLKIN_DIV_FIELD",
+      "severity": "medium (Si5351C/CLKIN users)"
+    },
+    "DEV-13-PLL-STALE-A": {
+      "title": "pll_calc keeps stale a after a>90 clamp (non-25/27 MHz reference)",
+      "library": "5 MHz reference: a = 160 > 90, freq clamped to 450 MHz but a not recomputed; P1 = 19968 (ratio 160)",
+      "spec": "AN619 \u00a73.2 feedback ratio 15..90; AN619 \u00a73.1.2 PLL input 10-40 MHz; DS Table 6/8 XTAL 25-27 MHz",
+      "rules": "FB_RATIO_RANGE, REF_RANGE",
+      "severity": "low (out-of-spec reference)"
+    },
+    "DEV-14-CLK67-NOT-ENABLED": {
+      "title": "set_freq() on CLK6/CLK7 never enables the output (reg 3 OEB bit stays 1)",
+      "library": "CLK0-5 branch calls output_enable(clk,1) on first set; CLK6/7 branch has no output_enable(); reset() disabled all outputs",
+      "spec": "AN619 Reg 3 CLKx_OEB: 1 = output disabled",
+      "rules": "OUTPUT_ENABLED_AFTER_SET",
+      "severity": "medium (functional; recommend hardware confirmation)"
+    },
+    "DEV-15-MANUAL-CLK67": {
+      "title": "set_freq_manual() on CLK6/7 writes a truncated fractional-MS P1 to reg 90/91",
+      "library": "set_freq_manual(87.4 MHz, 874 MHz, CLK7): multisynth_calc gives a=10,b=0,c=1 -> P1=128*10-512=768; set_ms writes (uint8_t)768 = 0x00 to reg 91",
+      "spec": "AN619 \u00a74.1.2 / Reg 91: 'For MS6 and MS7, set MSx_P1 directly (e.g., MSx_P1 = divide value)' -> 10 (0x0A)",
+      "rules": "MS67_RATIO_VALID, OUT_FREQ_ACCURACY",
+      "severity": "high (silent wrong output)"
+    }
+  },
+  "known_deviation_cases": {
+    "P0-clk6-23MHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-clk7-874MHz-even-div-of-clk6-pll": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-vcxo-manual-146MHz-on-876pll": {
+      "devs": [
+        "DEV-07-VCXO-CENTER-112M5"
+      ],
+      "rules": [
+        "VCXO_CENTER_MAX"
+      ]
+    },
+    "S-clk6-R6div-100kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk7-R7div-50kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk6-150MHz-upper-clamp": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "D-clk0-210MHz-above-spec-max": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-250MHz-clamped-to-225": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_ACCURACY",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-2p5kHz-clamped-to-4kHz": {
+      "devs": [
+        "DEV-02-FOUT-MIN-4K"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-clk6-10kHz-ms6-p1-zero": {
+      "devs": [
+        "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUTPUT_ENABLED_AFTER_SET",
+        "OUT_FREQ_ACCURACY",
+        "VCO_REQUEST_RANGE"
+      ]
+    },
+    "D-manual-100MHz-pll700-ratio7": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-90MHz-pll600-ratio6p67": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-140MHz-pll700-stale-a5": {
+      "devs": [
+        "DEV-05-MS-STALE-A"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-175MHz-pll800-divby4-precondition": {
+      "devs": [
+        "DEV-06-DIVBY4-PRECONDITION"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-vcxo-then-set_correction-clobbers-pllb": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED",
+        "VCXO_PLL_PRESERVED"
+      ]
+    },
+    "D-vcxo-875MHz-then-manual-rewrites-c1": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED"
+      ]
+    },
+    "D-manual-clk7-87p4MHz-p1-truncated": {
+      "devs": [
+        "DEV-15-MANUAL-CLK67"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-set_phase-clk6-writes-reserved-171": {
+      "devs": [
+        "DEV-09-PHOFF-CLK67"
+      ],
+      "rules": [
+        "PHOFF_ADDR"
+      ]
+    },
+    "D-init-crystal-load-0pF-reserved": {
+      "devs": [
+        "DEV-10-XTAL-CL-0PF"
+      ],
+      "rules": [
+        "XTAL_CL_RESERVED"
+      ]
+    },
+    "D-set_int-clk6-sets-FBA_INT-on-fractional-plla": {
+      "devs": [
+        "DEV-11-SET_INT-CLK67-IS-FB_INT"
+      ],
+      "rules": [
+        "FB_INT_ONLY_EVEN_INT"
+      ]
+    },
+    "D-set_pll_input-clkin_div-or-without-clear": {
+      "devs": [
+        "DEV-12-CLKIN-DIV-RMW"
+      ],
+      "rules": [
+        "CLKIN_DIV_FIELD"
+      ]
+    },
+    "D-ref5MHz-pll_calc-stale-a160": {
+      "devs": [
+        "DEV-13-PLL-STALE-A"
+      ],
+      "rules": [
+        "FB_RATIO_RANGE",
+        "REF_RANGE"
+      ]
+    }
+  },
+  "original_case_count": 27,
+  "new_case_count": 40,
+  "case_count": 67,
+  "cases": [
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-1-14MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-2-10MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 38,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 38,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 700000000,
+      "input_freq_hz": 7000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 700000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 114,
+      "ms_b": 285714,
+      "ms_c": 1000000,
+      "ms_p1": 14116,
+      "ms_p2": 571392,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        55,
+        36,
+        248,
+        184,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-3-7MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 55,
+        "46": 36,
+        "47": 248,
+        "48": 184,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 55,
+          "46": 36,
+          "47": 248,
+          "48": 184,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 7000000.0175,
+        "ms_ratio": "57142857/500000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[14116, 571392, 1000000] spec=[14116, 571392, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=14116 P2=571392 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=114.285714000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=7000000.018 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=7000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=7000000.017500 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 2800000000,
+      "input_freq_hz": 28000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2800000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 28,
+      "ms_b": 571428,
+      "ms_c": 1000000,
+      "ms_p1": 3145,
+      "ms_p2": 142784,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        12,
+        73,
+        242,
+        45,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-4-28MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 12,
+        "46": 73,
+        "47": 242,
+        "48": 45,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 12,
+          "46": 73,
+          "47": 242,
+          "48": 45,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 28000000.56000001,
+        "ms_ratio": "7142857/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[3145, 142784, 1000000] spec=[3145, 142784, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3145 P2=142784 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=28.571428000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=28000000.560 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=28000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=28000000.560000 Hz err=20.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1600000000,
+      "input_freq_hz": 16000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1600000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 50,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 5888,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        23,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-integer-MS-16MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "integer_MS",
+        "b_eq_0"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 23,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 23,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 16000000.0,
+        "ms_ratio": "50",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[5888, 0, 1] spec=[5888, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=5888 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=50.000000000 (=50)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 50 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=16000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1407000000,
+      "input_freq_hz": 14070000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1407000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 56,
+      "ms_b": 858564,
+      "ms_c": 1000000,
+      "ms_p1": 6765,
+      "ms_p2": 896192,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        109,
+        253,
+        172,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-fractional-MS-14p07MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_MS"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 109,
+        "47": 253,
+        "48": 172,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 109,
+          "47": 253,
+          "48": 172,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14070000.0794955,
+        "ms_ratio": "14214641/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6765, 896192, 1000000] spec=[6765, 896192, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6765 P2=896192 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=56.858564000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14070000.079 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14070000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14070000.079496 Hz err=5.650 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 840000,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 520000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        247,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-clk0-gt100MHz-recalc-pll-112MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "recalc_pll",
+        "gt_SHARE_MAX"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 247,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112000000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 896000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 520000, 1000000] spec=[4075, 520000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=520000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.840000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=896000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "P0-manual-DIVBY4-175MHz-pll700",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "int_mode",
+        "set_freq_manual",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "pll_assignment": "PLLB",
+      "lib_ms_regs": {
+        "50": 0,
+        "51": 1,
+        "52": 12,
+        "53": 0,
+        "54": 0,
+        "55": 0,
+        "56": 0,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 108
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 12,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 0,
+          "51": 1,
+          "52": 12,
+          "53": 0,
+          "54": 0,
+          "55": 0,
+          "56": 0,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 108
+        },
+        "realized_hz": 175000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0} spec={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 108} spec={'17': 108}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=175000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=175000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=175000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-boundary-150MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll",
+        "a_eq_4"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 150000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=150000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-200MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk1-PLLB-14MHz",
+      "priority": "P0",
+      "covers": [
+        "PLLB_assignment",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "lib_ms_regs": {
+        "50": 66,
+        "51": 64,
+        "52": 0,
+        "53": 26,
+        "54": 146,
+        "55": 244,
+        "56": 92,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 44
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 66,
+          "51": 64,
+          "52": 0,
+          "53": 26,
+          "54": 146,
+          "55": 244,
+          "56": 92,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 44
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0} spec={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 44} spec={'17': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 31,
+      "pll_b": 996800,
+      "pll_c": 1000000,
+      "pll_p1": 3583,
+      "pll_p2": 590400,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr-100000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 31,
+        "pll_b": 996800,
+        "pll_c": 1000000,
+        "pll_p1": 3583,
+        "pll_p2": 590400,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          13,
+          255,
+          249,
+          2,
+          64
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 13,
+        "30": 255,
+        "31": 249,
+        "32": 2,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 13999999.895,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999992.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3583, 590400, 1000000] spec=[3583, 590400, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3583 P2=590400 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=31.996800000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999992.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=13999999.895 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=13999999.895000 Hz err=-7.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": -50000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 1600,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 204800,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr--50000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 32,
+        "pll_b": 1600,
+        "pll_c": 1000000,
+        "pll_p1": 3584,
+        "pll_p2": 204800,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          14,
+          0,
+          243,
+          32,
+          0
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 243,
+        "32": 32,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.0,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999998.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 204800, 1000000] spec=[3584, 204800, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=204800 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.001600000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999998.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 836416,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 61248,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        240,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-corr-100000-gt100MHz-112MHz",
+      "priority": "P0",
+      "covers": [
+        "correction_factor",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 240,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 111999998.88,
+        "ms_ratio": "8",
+        "fvco_hz": 895999991.04,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 61248, 1000000] spec=[4075, 61248, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=61248 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.836416000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=895999991.040 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=111999998.880 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=111999998.880000 Hz err=-10.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "P0-rdiv-128-5kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "select_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 114,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 114,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 98,
+      "pll_reset": false,
+      "id": "P0-rdiv-64-10kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 98,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 98,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 3,
+      "r_div_name": "DIV_8",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 49,
+      "pll_reset": false,
+      "id": "P0-rdiv-8-100kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 49,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 49,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 40000000,
+      "input_freq_hz": 400000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 1,
+      "r_div_name": "DIV_2",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 17,
+      "pll_reset": false,
+      "id": "P0-rdiv-2-400kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 17,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 17,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 400000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 51200000,
+      "input_freq_hz": 512000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 3,
+      "pll_reset": false,
+      "id": "P0-rdiv-1-512kHz-boundary",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "no_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 3,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 3,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 512000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=512000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 2300000000,
+      "input_freq_hz": 23000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2300000000,
+      "ms_a": 38,
+      "ms_p1": 38,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "clk67_ms_register_byte": 38,
+      "id": "P0-clk6-23MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "multisynth67_calc",
+        "PLLB"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 38
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 38
+        },
+        "spec_ms67_regs": {
+          "90": 38
+        },
+        "spec_reg92": 0,
+        "realized_hz": 23000000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=38"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 38} spec={'90': 38}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=23000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=23000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "peer_already_set",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "ms_a": 10,
+      "ms_p1": 10,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "clk67_ms_register_byte": 10,
+      "id": "P0-clk7-874MHz-even-div-of-clk6-pll",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "peer_even_integer"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 10
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": 87400000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=10"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 10} spec={'91': 10}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1234567800,
+      "input_freq_hz": 12345678.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": true,
+      "reason": "peer_requires_even_integer_divide_of_pllb",
+      "id": "P0-clk7-reject-noninteger-12p345678MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "reject_path"
+      ],
+      "clk": 7,
+      "spec": {
+        "spec_expectation": "reject: requested freq is not an even-integer division of PLLB",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "MS67_REJECT_CONSISTENT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note (even integers 6..254 only)",
+            "detail": "library rejected (peer_requires_even_integer_divide_of_pllb)"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 40,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 184577,
+      "vcxo_bytes": [
+        1,
+        209,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 1,
+        "VXCO_PARAMETERS_MID(163)": 209,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "P0-vcxo-876MHz-40ppm",
+      "priority": "P0",
+      "covers": [
+        "set_vcxo",
+        "PLLB",
+        "vcxo_param"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 1,
+        "163": 209,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 184577.648,
+        "spec_vcxo_floor": 184577,
+        "spec_vcxo_round": 184578,
+        "spec_vcxo_regs": {
+          "162": 1,
+          "163": 209,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=40 requested=40"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=184577 spec=184577"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 1, '163': 209, '164': 2} spec={'162': 1, '163': 209, '164': 2}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=184577.6480: library floors to 184577; round-half-up would give 184578"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14600000000,
+      "input_freq_hz": 146000000.0,
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 256,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "P0-vcxo-manual-146MHz-on-876pll",
+      "priority": "P0",
+      "covers": [
+        "set_freq_manual",
+        "VCXO_companion",
+        "near_DIVBY4"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 146000000.0,
+        "ms_ratio": "6",
+        "fvco_hz": 876000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_CENTER_MAX"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-07-VCXO-CENTER-112M5"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[256, 0, 1] spec=[256, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=256 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.000000000 (=6)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 6 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=146000000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=146000000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1000000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-set_freq-vs-manual-14MHz-pll800",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity"
+      ],
+      "api": "parity_check",
+      "description": "For freq<=100 MHz, set_freq uses existing PLL and does not call set_pll; set_freq_manual always calls set_pll(pll_freq). MS a/b/c and p1/p2/p3 must match when the same pll_freq is supplied. Differences: set_freq_manual always output_enable(1); set_freq enables only on first set. set_freq skips pll_reset in <=100 MHz branch; set_freq_manual does not reset either.",
+      "auto_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "manual_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "ms_match": true,
+      "manual_also_writes_pll": true,
+      "manual_pll": {
+        "a": 32,
+        "b": 0,
+        "c": 1,
+        "p1": 3584,
+        "p2": 0,
+        "p3": 1
+      },
+      "clk": 0,
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_MS_MATCH",
+            "ok": true,
+            "severity": "error",
+            "cite": "library parity (no spec rule)",
+            "detail": ""
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-gt100-set_freq-vs-manual-175MHz",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity",
+        "DIVBY4"
+      ],
+      "api": "parity_check",
+      "description": "set_freq(175 MHz) chooses pll_freq via multisynth_calc(freq,0) \u2192 a=4, pll=700 MHz. set_freq_manual(175 MHz, 700 MHz) must yield identical MS p1/p2/p3, div_by_4=1, int_mode=1 and identical PLL a/b/c when correction matches.",
+      "auto": {
+        "api": "set_freq",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_assignment": "PLLA",
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "branch": "recalc_pll_gt_100mhz",
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12,
+        "pll_reset": true
+      },
+      "manual": {
+        "api": "set_freq_manual",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12
+      },
+      "ms_match": true,
+      "pll_match": true,
+      "clk": 0,
+      "spec": {
+        "auto_status": "agree",
+        "manual_status": "agree",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_SPEC_REGS_EQUAL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2/\u00a74.1.3",
+            "detail": "spec MS registers for auto vs manual"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-reset-pll-fixed-800MHz",
+      "priority": "P1",
+      "covers": [
+        "reset",
+        "SI5351_PLL_FIXED",
+        "set_pll"
+      ],
+      "api": "set_pll",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "note": "reset() calls set_pll(SI5351_PLL_FIXED) for both PLLA and PLLB",
+      "clk": 0,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=25000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-reset-pll-blocks-and-reg177",
+      "priority": "S",
+      "api": "reset_plls",
+      "covers": [
+        "MSNA regs 26-33",
+        "MSNB regs 34-41",
+        "PLL reset reg 177",
+        "CLK ctrl regs 16-23"
+      ],
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_plla_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "lib_pllb_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "lib_reg177_writes": [
+        32,
+        128
+      ],
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_PLL_BLOCK_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "REG_PLL_BLOCK_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_177",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 177 (PLLB_RST bit7, PLLA_RST bit5)",
+            "detail": "library=[32, 128] spec=[32, 128]"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-23 (PDN=0, INT=0, SRC per PLL, CLK_SRC=11 own MS, 2 mA)",
+            "detail": "library={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44} spec={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "S-ms5-block-10MHz-clk5",
+      "priority": "S",
+      "covers": [
+        "MS5 regs 82-89 address offset",
+        "reg 21"
+      ],
+      "clk": 5,
+      "lib_ms_regs": {
+        "82": 0,
+        "83": 1,
+        "84": 0,
+        "85": 38,
+        "86": 0,
+        "87": 0,
+        "88": 0,
+        "89": 0
+      },
+      "lib_clk_ctrl": {
+        "21": 12
+      },
+      "lib_reg3_after": 223,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "82": 0,
+          "83": 1,
+          "84": 0,
+          "85": 38,
+          "86": 0,
+          "87": 0,
+          "88": 0,
+          "89": 0
+        },
+        "spec_clk_ctrl": {
+          "21": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0} spec={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'21': 12} spec={'21': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xDF"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "S-rdiv-placement-clk2-5kHz",
+      "priority": "S",
+      "covers": [
+        "R2_DIV bits 6:4 of reg 60",
+        "MS2 regs 58-65"
+      ],
+      "clk": 2,
+      "lib_ms_regs": {
+        "58": 0,
+        "59": 1,
+        "60": 114,
+        "61": 111,
+        "62": 0,
+        "63": 0,
+        "64": 0,
+        "65": 0
+      },
+      "lib_clk_ctrl": {
+        "18": 12
+      },
+      "lib_reg3_after": 251,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "58": 0,
+          "59": 1,
+          "60": 114,
+          "61": 111,
+          "62": 0,
+          "63": 0,
+          "64": 0,
+          "65": 0
+        },
+        "spec_clk_ctrl": {
+          "18": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0} spec={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'18': 12} spec={'18': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFB"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "S-divby4-block-clk3-200MHz",
+      "priority": "S",
+      "covers": [
+        "MS3_DIVBY4 bits 3:2 of reg 68",
+        "MS3_INT reg 19 bit6",
+        "MSNA block"
+      ],
+      "clk": 3,
+      "lib_ms_regs": {
+        "66": 0,
+        "67": 1,
+        "68": 12,
+        "69": 0,
+        "70": 0,
+        "71": 0,
+        "72": 0,
+        "73": 0
+      },
+      "lib_clk_ctrl": {
+        "19": 76
+      },
+      "lib_reg3_after": 247,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "66": 0,
+          "67": 1,
+          "68": 12,
+          "69": 0,
+          "70": 0,
+          "71": 0,
+          "72": 0,
+          "73": 0
+        },
+        "spec_clk_ctrl": {
+          "19": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0} spec={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'19': 76} spec={'19': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xF7"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11250000000,
+      "input_freq_hz": 112500000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "S-boundary-112p5MHz-ratio8",
+      "priority": "S",
+      "covers": [
+        "AN619 2.1.1 900/8 boundary",
+        "integer ratio 8"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112500000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112500000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 5,
+      "r_div_name": "DIV_32",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk6-R6div-100kHz",
+      "priority": "S",
+      "covers": [
+        "R6_DIV bits 2:0 of reg 92",
+        "reg 90"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 254
+      },
+      "lib_reg92": 5,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 254
+        },
+        "spec_ms67_regs": {
+          "90": 254
+        },
+        "spec_reg92": 5,
+        "realized_hz": 100000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 254} spec={'90': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=5 spec=5"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 5000000,
+      "input_freq_hz": 50000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk7-R7div-50kHz",
+      "priority": "S",
+      "covers": [
+        "R7_DIV bits 6:4 of reg 92",
+        "reg 91"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 254
+      },
+      "lib_reg92": 96,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 254
+        },
+        "spec_ms67_regs": {
+          "91": 254
+        },
+        "spec_reg92": 96,
+        "realized_hz": 50000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 254} spec={'91': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=96 spec=96"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=50000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=50000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 14999999999,
+      "ms_a": 6,
+      "ms_p1": 6,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 89999999994,
+      "pll_freq_hz": 899999999.94,
+      "pll_a": 35,
+      "pll_b": 999999,
+      "pll_c": 1000000,
+      "pll_p1": 4095,
+      "pll_p2": 999872,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        255,
+        255,
+        65,
+        192
+      ],
+      "clk67_ms_register_byte": 6,
+      "id": "S-clk6-150MHz-upper-clamp",
+      "priority": "S",
+      "covers": [
+        "CLK6 upper bound",
+        "MS6 ratio 6"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 6
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 255,
+        "39": 255,
+        "40": 65,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms67_regs": {
+          "90": 6
+        },
+        "spec_reg92": 0,
+        "realized_hz": 149999995.83333334,
+        "fvco_hz": 899999975.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4095, 999872, 1000000] spec=[4095, 999872, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4095 P2=999872 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.999999000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=899999975.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=6"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=899999999.94 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 6} spec={'90': 6}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=149999995.833333 Hz err=-27.778 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "ppm": 100,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        0,
+        240,
+        0,
+        0
+      ],
+      "vcxo_param_raw_from_pll_calc": 4096000000,
+      "vcxo_param": 421888,
+      "vcxo_bytes": [
+        0,
+        112,
+        6
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 0,
+        "VXCO_PARAMETERS_MID(163)": 112,
+        "VXCO_PARAMETERS_HIGH(164)": 6
+      },
+      "id": "S-vcxo-800MHz-100ppm",
+      "priority": "S",
+      "covers": [
+        "VCXO regs 162-164",
+        "c=10^6"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 240,
+        "40": 0,
+        "41": 0
+      },
+      "lib_vcxo_regs": {
+        "162": 0,
+        "163": 112,
+        "164": 6
+      },
+      "spec": {
+        "spec_vcxo_exact": 421888.0,
+        "spec_vcxo_floor": 421888,
+        "spec_vcxo_round": 421888,
+        "spec_vcxo_regs": {
+          "162": 0,
+          "163": 112,
+          "164": 6
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1000000] spec=[3584, 0, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=100 requested=100"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=421888 spec=421888"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 0, '163': 112, '164': 6} spec={'162': 0, '163': 112, '164': 6}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 30,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 138433,
+      "vcxo_bytes": [
+        193,
+        28,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 193,
+        "VXCO_PARAMETERS_MID(163)": 28,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "S-vcxo-ppm-clamp-low-10to30",
+      "priority": "S",
+      "covers": [
+        "VCXO APR min 30"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 10,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 193,
+        "163": 28,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 138433.236,
+        "spec_vcxo_floor": 138433,
+        "spec_vcxo_round": 138433,
+        "spec_vcxo_regs": {
+          "162": 193,
+          "163": 28,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=30 requested=10"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=138433 spec=138433"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 193, '163': 28, '164': 2} spec={'162': 193, '163': 28, '164': 2}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 240,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 1107465,
+      "vcxo_bytes": [
+        9,
+        230,
+        16
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 9,
+        "VXCO_PARAMETERS_MID(163)": 230,
+        "VXCO_PARAMETERS_HIGH(164)": 16
+      },
+      "id": "S-vcxo-ppm-clamp-high-250to240",
+      "priority": "S",
+      "covers": [
+        "VCXO APR max 240"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 250,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 9,
+        "163": 230,
+        "164": 16
+      },
+      "spec": {
+        "spec_vcxo_exact": 1107465.888,
+        "spec_vcxo_floor": 1107465,
+        "spec_vcxo_round": 1107466,
+        "spec_vcxo_regs": {
+          "162": 9,
+          "163": 230,
+          "164": 16
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=240 requested=250"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=1107465 spec=1107465"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 9, '163': 230, '164': 16} spec={'162': 9, '163': 230, '164': 16}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=1107465.8880: library floors to 1107465; round-half-up would give 1107466"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-phase-clk0-mask",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "reg 165",
+        "PHOFF[6:0]"
+      ],
+      "clk": 0,
+      "requested_phase": 255,
+      "lib_write": {
+        "reg": 165,
+        "value": 127
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 165"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x7F"
+          },
+          {
+            "rule": "REG_PHOFF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170",
+            "detail": "library=[165, 127] spec=[165, 127]"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-xtal-load-6-8-10pF",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "reg 183"
+      ],
+      "lib_writes": {
+        "6pF": 82,
+        "8pF": 146,
+        "10pF": 210
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_183_6pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=82 spec=82"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "6pF: reg183=0x52"
+          },
+          {
+            "rule": "REG_183_8pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=146 spec=146"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "8pF: reg183=0x92"
+          },
+          {
+            "rule": "REG_183_10pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=210 spec=210"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "10pF: reg183=0xD2"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 21000000000,
+      "input_freq_hz": 210000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 84000000000,
+      "pll_freq_hz": 840000000.0,
+      "pll_a": 33,
+      "pll_b": 600000,
+      "pll_c": 1000000,
+      "pll_p1": 3788,
+      "pll_p2": 800000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        204,
+        252,
+        53,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-210MHz-above-spec-max",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 204,
+        "31": 252,
+        "32": 53,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 210000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 840000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3788, 800000, 1000000] spec=[3788, 800000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3788 P2=800000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=33.600000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=840000000.000 Hz"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=210000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=210000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=210000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=210000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 25000000000,
+      "input_freq_hz": 250000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-250MHz-clamped-to-225",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz",
+        "clamp"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 225000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_ACCURACY",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=225000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=225000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=250000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=225000000.000000 Hz err=-100000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 250000,
+      "input_freq_hz": 2500.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 115,
+      "pll_reset": false,
+      "id": "D-clk0-2p5kHz-clamped-to-4kHz",
+      "priority": "S",
+      "covers": [
+        "Fout min 2.5 kHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 115,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 115,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 4000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-02-FOUT-MIN-4K"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=2500.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=4000.000000 Hz err=600000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 400000,
+      "ms_a": 256,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 12800000000,
+      "pll_freq_hz": 128000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "clk67_ms_register_byte": 0,
+      "pllb_freq_member_lib": 12800000000,
+      "id": "D-clk6-10kHz-ms6-p1-zero",
+      "priority": "S",
+      "covers": [
+        "MS6 even 6..254",
+        "uint8 truncation"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 10,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUTPUT_ENABLED_AFTER_SET",
+          "OUT_FREQ_ACCURACY",
+          "VCO_REQUEST_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=128000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS6_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000000,
+      "input_freq_hz": 100000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 7,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 384,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-100MHz-pll700-ratio7",
+      "priority": "S",
+      "covers": [
+        "MS ratio 7 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000000.0,
+        "ms_ratio": "7",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[384, 0, 1] spec=[384, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=384 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=7.000000000 (=7)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 9000000000,
+      "input_freq_hz": 90000000.0,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 666666,
+      "ms_c": 1000000,
+      "ms_p1": 341,
+      "ms_p2": 333248,
+      "ms_p3": 1000000,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        1,
+        85,
+        245,
+        21,
+        192
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-90MHz-pll600-ratio6p67",
+      "priority": "S",
+      "covers": [
+        "MS fractional ratio < 8 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 1,
+        "46": 85,
+        "47": 245,
+        "48": 21,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 1,
+          "46": 85,
+          "47": 245,
+          "48": 21,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 90000009.0000009,
+        "ms_ratio": "3333333/500000",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[341, 333248, 1000000] spec=[341, 333248, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=341 P2=333248 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.666666000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=90000009.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=90000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=90000009.000001 Hz err=100.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14000000000,
+      "input_freq_hz": 140000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 5,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 128,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-140MHz-pll700-stale-a5",
+      "priority": "S",
+      "covers": [
+        "multisynth_calc stale a after a<6 clamp"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 0,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 0,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 140000000.0,
+        "ms_ratio": "5",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-05-MS-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[128, 0, 1] spec=[128, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=128 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=5.000000000 (=5)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=140000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "D-manual-175MHz-pll800-divby4-precondition",
+      "priority": "S",
+      "covers": [
+        "DIVBY4 requires fVCO = 4*Fout"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-06-DIVBY4-PRECONDITION"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=142857142.857 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-vcxo-then-set_correction-clobbers-pllb",
+      "priority": "S",
+      "api": "vcxo_sequence",
+      "covers": [
+        "set_vcxo does not update pllb_freq",
+        "VCXO c=10^6"
+      ],
+      "sequence": [
+        "reset()",
+        "set_vcxo(87600000000ULL, 40)",
+        "set_correction(0, SI5351_PLL_INPUT_XO)"
+      ],
+      "vcxo_context": true,
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 40000,
+        "c": 1000000,
+        "p1": 3973,
+        "p2": 120000,
+        "p3": 1000000
+      },
+      "pllb_freq_member_lib": 80000000000,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED",
+          "VCXO_PLL_PRESERVED"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3 after sequence=1"
+          },
+          {
+            "rule": "VCXO_PLL_PRESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (PLLB is the VCXO)",
+            "detail": "MSNB ratio after set_vcxo=35.04 after sequence=32.0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 8750000000,
+      "input_freq_hz": 87500000.0,
+      "pll_freq_lib": 87500000000,
+      "pll_freq_hz": 875000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        15,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "sequence": [
+        "reset()",
+        "set_vcxo(87500000000ULL, 40)",
+        "set_ms_source(SI5351_CLK0, SI5351_PLLB)",
+        "set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0)"
+      ],
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 0,
+        "c": 1000000,
+        "p1": 3968,
+        "p2": 0,
+        "p3": 1000000
+      },
+      "id": "D-vcxo-875MHz-then-manual-rewrites-c1",
+      "priority": "S",
+      "covers": [
+        "VCXO c=10^6 lost via set_pll"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 3,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 15,
+        "38": 128,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 3,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 87500000.0,
+        "ms_ratio": "10",
+        "fvco_hz": 875000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3968, 0, 1] spec=[3968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=875000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[768, 0, 1] spec=[768, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=768 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=10.000000000 (=10)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 10 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87500000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=87500000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-clk7-87p4MHz-p1-truncated",
+      "priority": "S",
+      "clk": 7,
+      "pll_assignment": "PLLB",
+      "covers": [
+        "set_freq_manual on CLK6/7",
+        "reg 91"
+      ],
+      "sequence": [
+        "reset()",
+        "set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7)"
+      ],
+      "lib_ms67_regs": {
+        "91": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 127,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-15-MANUAL-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0x7F"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS7_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_phase-clk6-writes-reserved-171",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "phase regs only CLK0-5"
+      ],
+      "clk": 6,
+      "requested_phase": 10,
+      "lib_write": {
+        "reg": 171,
+        "value": 10
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "PHOFF_ADDR"
+        ],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-09-PHOFF-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 171"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x0A"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-init-crystal-load-0pF-reserved",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "XTAL_CL=00 reserved"
+      ],
+      "lib_writes": {
+        "0pF": 18
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "XTAL_CL_RESERVED"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-10-XTAL-CL-0PF"
+        ],
+        "checks": [
+          {
+            "rule": "REG_183_0pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=18 spec=18"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "0pF: reg183=0x12"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_int-clk6-sets-FBA_INT-on-fractional-plla",
+      "priority": "S",
+      "api": "set_int",
+      "covers": [
+        "reg 22 bit6 = FBA_INT"
+      ],
+      "clk": 6,
+      "sequence": [
+        "reset()",
+        "set_correction(100000, SI5351_PLL_INPUT_XO)",
+        "set_int(SI5351_CLK6, 1)"
+      ],
+      "lib_write": {
+        "reg": 22,
+        "value": 108
+      },
+      "plla": {
+        "a": 31,
+        "b": 996800,
+        "c": 1000000,
+        "p1": 3583,
+        "p2": 590400,
+        "p3": 1000000
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "FB_INT_ONLY_EVEN_INT"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-11-SET_INT-CLK67-IS-FB_INT"
+        ],
+        "checks": [
+          {
+            "rule": "FB_INT_ONLY_EVEN_INT",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2.1 / Reg 22 bit6 FBA_INT (only for even-integer a+b/c)",
+            "detail": "reg22=0x6C -> FBA_INT=1; MSNA ratio=31.996800000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_pll_input-clkin_div-or-without-clear",
+      "priority": "S",
+      "api": "set_pll_input",
+      "covers": [
+        "reg 15 CLKIN_DIV[1:0]"
+      ],
+      "sequence": [
+        "(reg15 = 0x44 from earlier CLKIN @ 40 MHz)",
+        "set_ref_freq(80000000, CLKIN)",
+        "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"
+      ],
+      "prior_reg15": 68,
+      "intended_clkin_div": 4,
+      "lib_write": {
+        "reg": 15,
+        "value": 196
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "CLKIN_DIV_FIELD"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-12-CLKIN-DIV-RMW"
+        ],
+        "checks": [
+          {
+            "rule": "CLKIN_DIV_FIELD",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 15 CLKIN_DIV[1:0]",
+            "detail": "reg15=0xC4 -> CLKIN_DIV=11b (/8); intended /4"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-ref5MHz-pll_calc-stale-a160",
+      "priority": "S",
+      "api": "set_pll",
+      "covers": [
+        "feedback ratio 15..90",
+        "PLL input 10..40 MHz"
+      ],
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 5000000, 0)  -> reset() -> set_pll(800 MHz)"
+      ],
+      "pll_freq_lib": 80000000000,
+      "xtal_hz": 5000000,
+      "correction_ppb": 0,
+      "pll_a": 160,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 19968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_calc_return_lib": 80000000000,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 78,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "FB_RATIO_RANGE",
+          "REF_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-13-PLL-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[19968, 0, 1] spec=[19968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=19968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=160.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 160 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=5000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000000,
+      "input_freq_hz": 100000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 10000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "F-clk0-100MHz-share-max-boundary",
+      "priority": "S",
+      "covers": [
+        "<=100 MHz branch boundary",
+        "ratio 8 on 800 MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 400000,
+      "input_freq_hz": 4000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 115,
+      "pll_reset": false,
+      "id": "F-clk0-4kHz-library-min",
+      "priority": "S",
+      "covers": [
+        "CLKOUT_MIN",
+        "R=128"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 115,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 115,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 4000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=4000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=4000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "id": "M-clk7-pllb-assignment",
+      "priority": "M",
+      "api": "reset_pll_assignment",
+      "covers": [
+        "CLK7 \u2192 PLLB after reset",
+        "reg 23 MS7_SRC bit5",
+        "mutation: CLK7\u2192PLLA"
+      ],
+      "clk": 7,
+      "pll_assignment": "PLLB",
+      "pll_assignment_table": {
+        "0": "PLLA",
+        "1": "PLLA",
+        "2": "PLLA",
+        "3": "PLLA",
+        "4": "PLLA",
+        "5": "PLLA",
+        "6": "PLLB",
+        "7": "PLLB"
+      },
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_write": {
+        "reg": 23,
+        "value": 44
+      },
+      "mutation_fail_if": {
+        "clk7_ctrl_equals": 12,
+        "pll_assignment_7": "PLLA"
+      },
+      "spec_note": "AN619 \u00a74.1.1 / Reg 23 MS7_SRC: 0=PLLA, 1=PLLB/VCXO \u2014 either legal when no spread-spectrum/VCXO constraint. Library reset() chooses PLLB for CLK7; that choice is the regression lock. Spec agrees the bit encoding; does not mandate PLLB.",
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLK5_RESET_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk5 \u2192 PLLA (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[5]=PLLA"
+          },
+          {
+            "rule": "CLK7_RESET_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk7 \u2192 PLLB (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[7]=PLLB"
+          },
+          {
+            "rule": "REG_CLK_CTRL_0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 17 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_2",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 18 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 19 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 20 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_CLK_CTRL_7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_FOCUS_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "PLL_ASSIGN_SPEC_PERMITS_EITHER",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.1",
+            "detail": "AN619 \u00a74.1.1 / Reg 23 MS7_SRC: 0=PLLA, 1=PLLB/VCXO \u2014 either legal when no spread-spectrum/VCXO constraint. Library reset() chooses PLLB for CLK7; that choice is the regression lock. Spec agrees the bit encoding; does not mandate PLLB."
+          },
+          {
+            "rule": "MUTATION_CLK7_NOT_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "mutation detector (Coding PM)",
+            "detail": "locked reg23=0x2C assignment=PLLB"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_ms_rmw",
+      "clk_path": null,
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "M-set-ms-byte2-rmw",
+      "priority": "M",
+      "covers": [
+        "set_ms byte+2 RMW",
+        "ms_div byte+2 RMW",
+        "bit7 preserve",
+        "P1[17:16] preserve"
+      ],
+      "clk": 0,
+      "prior_byte2": 255,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 242,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "rmw_transcript": {
+        "reg": 44,
+        "prior": 255,
+        "steps": [
+          {
+            "op": "si5351_read",
+            "reg": 44,
+            "returns": 255,
+            "note": "set_ms RMW start"
+          },
+          {
+            "op": "si5351_write_bulk_byte2",
+            "reg": 44,
+            "value": 254,
+            "mask_cleared": 3,
+            "bits_preserved": "7:2",
+            "note": "set_ms: reg_val &= ~0x03; |= P1[17:16]"
+          },
+          {
+            "op": "si5351_read",
+            "reg": 44,
+            "returns": 254,
+            "note": "ms_div RMW start"
+          },
+          {
+            "op": "si5351_write",
+            "reg": 44,
+            "value": 242,
+            "mask_cleared": 124,
+            "bits_preserved": "7 and 1:0",
+            "note": "ms_div: reg_val &= ~0x7C; |= R_DIV<<4 | DIVBY4"
+          }
+        ],
+        "final": 242,
+        "mutation_detectors": {
+          "naive_ms_div_overwrite": 112,
+          "naive_set_ms_then_correct_ms_div": 114,
+          "note": "naive_ms_div_overwrite loses P1[17:16] and bit7; naive_set_ms_then_correct_ms_div loses bit7 (and any prior R_DIV/DIVBY4 mid-bulk)"
+        }
+      },
+      "wire_stub_must_assert": "Future Wire stub: (1) set_ms bulk byte at reg 44 must equal (prior & ~0x03) | P1[17:16] \u2014 bits 7:2 survive; (2) ms_div write at reg 44 must equal that value with bits 6:2 replaced by R_DIV/DIVBY4 \u2014 bits 7 and 1:0 survive. Final byte MUST be 0xF2 for this case, NOT 0x70 or 0x72.",
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 114,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_B0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=1 spec=1"
+          },
+          {
+            "rule": "REG_MS_B3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=111 spec=111"
+          },
+          {
+            "rule": "REG_MS_B4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_BYTE2_LOW7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 44 bits 6:0 (R_DIV|DIVBY4|P1[17:16])",
+            "detail": "library=0xF2 spec_low7=0x72"
+          },
+          {
+            "rule": "RMW_BIT7_PRESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library set_ms/ms_div RMW preserves unused bit7 (AN619 Reg 44 bit7 Unused)",
+            "detail": "prior=0xFF final=0xF2"
+          },
+          {
+            "rule": "MUTATION_NOT_NAIVE_MS_DIV",
+            "ok": true,
+            "severity": "error",
+            "cite": "Coding PM mutation: naive ms_div overwrite",
+            "detail": "final=0xF2 naive=0x70"
+          },
+          {
+            "rule": "MUTATION_NOT_NAIVE_SET_MS",
+            "ok": true,
+            "severity": "error",
+            "cite": "Coding PM mutation: naive set_ms (no RMW) then correct ms_div",
+            "detail": "final=0xF2 naive=0x72"
+          },
+          {
+            "rule": "RMW_TRANSCRIPT_FINAL",
+            "ok": true,
+            "severity": "error",
+            "cite": "set_ms+ms_div RMW transcript",
+            "detail": "library=242 spec=242"
+          },
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          }
+        ]
+      }
+    },
+    {
+      "id": "M-clk5-reset-plla",
+      "priority": "M",
+      "api": "reset_pll_assignment",
+      "covers": [
+        "CLK5 \u2192 PLLA after reset",
+        "reg 21 MS5_SRC bit5",
+        "mutation: CLK5\u2192PLLB"
+      ],
+      "clk": 5,
+      "pll_assignment": "PLLA",
+      "pll_assignment_table": {
+        "0": "PLLA",
+        "1": "PLLA",
+        "2": "PLLA",
+        "3": "PLLA",
+        "4": "PLLA",
+        "5": "PLLA",
+        "6": "PLLB",
+        "7": "PLLB"
+      },
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_write": {
+        "reg": 21,
+        "value": 12
+      },
+      "mutation_fail_if": {
+        "clk5_ctrl_equals": 44,
+        "pll_assignment_5": "PLLB"
+      },
+      "spec_note": "AN619 \u00a74.1.1 / Reg 21 MS5_SRC: 0=PLLA, 1=PLLB. Library reset() chooses PLLA for CLK0\u20135; that choice is the regression lock.",
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLK5_RESET_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk5 \u2192 PLLA (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[5]=PLLA"
+          },
+          {
+            "rule": "CLK7_RESET_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk7 \u2192 PLLB (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[7]=PLLB"
+          },
+          {
+            "rule": "REG_CLK_CTRL_0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 17 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_2",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 18 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 19 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 20 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_CLK_CTRL_7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_FOCUS_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "PLL_ASSIGN_SPEC_PERMITS_EITHER",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.1",
+            "detail": "AN619 \u00a74.1.1 / Reg 21 MS5_SRC: 0=PLLA, 1=PLLB. Library reset() chooses PLLA for CLK0\u20135; that choice is the regression lock."
+          },
+          {
+            "rule": "MUTATION_CLK5_NOT_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "mutation detector (Coding PM)",
+            "detail": "locked reg21=0x0C assignment=PLLA"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_phase-clk1-0x2A",
+      "priority": "A",
+      "api": "set_phase",
+      "covers": [
+        "set_phase",
+        "reg 166"
+      ],
+      "clk": 1,
+      "requested_phase": 42,
+      "lib_write": {
+        "reg": 166,
+        "value": 42
+      },
+      "sequence": [
+        "reset()",
+        "set_phase(SI5351_CLK1, 0x2A)"
+      ],
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 166"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x2A"
+          },
+          {
+            "rule": "REG_PHOFF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170",
+            "detail": "library=[166, 42] spec=[166, 42]"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-init-crystal-load-8pF",
+      "priority": "A",
+      "api": "init_xtal_load",
+      "covers": [
+        "init xtal load",
+        "reg 183"
+      ],
+      "lib_writes": {
+        "8pF": 146
+      },
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 0, 0)"
+      ],
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_183_8pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=146 spec=146"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "8pF: reg183=0x92"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_int-clk0-ms-int",
+      "priority": "A",
+      "api": "set_int",
+      "covers": [
+        "set_int CLK0",
+        "reg 16 bit6 = MS0_INT"
+      ],
+      "clk": 0,
+      "sequence": [
+        "reset()",
+        "set_int(SI5351_CLK0, 1)"
+      ],
+      "lib_write": {
+        "reg": 16,
+        "value": 76
+      },
+      "ms_int_target": true,
+      "plla": null,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 bit6 = MSx_INT",
+            "detail": "library=76 spec=76"
+          },
+          {
+            "rule": "MS_INT_BIT_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2.1 / Reg 16-21 bit6",
+            "detail": "reg16=0x4C"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_pll_input-clkin-div4-clean",
+      "priority": "A",
+      "api": "set_pll_input",
+      "covers": [
+        "set_pll_input",
+        "set_ref_freq",
+        "reg 15"
+      ],
+      "sequence": [
+        "reset()",
+        "set_ref_freq(80000000, SI5351_PLL_INPUT_CLKIN)",
+        "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"
+      ],
+      "prior_reg15": 0,
+      "intended_clkin_div": 4,
+      "lib_write": {
+        "reg": 15,
+        "value": 132
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLKIN_DIV_FIELD",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 15 CLKIN_DIV[1:0]",
+            "detail": "reg15=0x84 -> CLKIN_DIV=10b (/4); intended /4"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-ref27MHz-set_pll-fixed",
+      "priority": "A",
+      "api": "set_pll",
+      "covers": [
+        "set_ref_freq 27 MHz",
+        "set_pll",
+        "in-spec XTAL"
+      ],
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 27000000, 0)",
+        "reset() \u2192 set_pll(SI5351_PLL_FIXED)"
+      ],
+      "pll_freq_lib": 80000000000,
+      "xtal_hz": 27000000,
+      "correction_ppb": 0,
+      "pll_assignment": "PLLA",
+      "pll_a": 29,
+      "pll_b": 629629,
+      "pll_c": 1000000,
+      "pll_p1": 3280,
+      "pll_p2": 592512,
+      "pll_p3": 1000000,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 12,
+        "30": 208,
+        "31": 249,
+        "32": 10,
+        "33": 128
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3280, 592512, 1000000] spec=[3280, 592512, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 12, '30': 208, '31': 249, '32': 10, '33': 128} spec={'26': 66, '27': 64, '28': 0, '29': 12, '30': 208, '31': 249, '32': 10, '33': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3280 P2=592512 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=29.629629000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999983.000 Hz"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=27000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_correction-then-set_int-clk0",
+      "priority": "A",
+      "api": "set_int",
+      "covers": [
+        "set_correction",
+        "set_int CLK0"
+      ],
+      "clk": 0,
+      "sequence": [
+        "reset()",
+        "set_correction(100000, SI5351_PLL_INPUT_XO)",
+        "set_int(SI5351_CLK0, 1)"
+      ],
+      "lib_write": {
+        "reg": 16,
+        "value": 76
+      },
+      "ms_int_target": true,
+      "plla": {
+        "a": 31,
+        "b": 996800,
+        "c": 1000000,
+        "p1": 3583,
+        "p2": 590400,
+        "p3": 1000000
+      },
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 13,
+        "30": 255,
+        "31": 249,
+        "32": 2,
+        "33": 64
+      },
+      "pll_a": 31,
+      "pll_b": 996800,
+      "pll_c": 1000000,
+      "pll_p1": 3583,
+      "pll_p2": 590400,
+      "pll_p3": 1000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 bit6 = MSx_INT",
+            "detail": "library=76 spec=76"
+          },
+          {
+            "rule": "MS_INT_BIT_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2.1 / Reg 16-21 bit6",
+            "detail": "reg16=0x4C"
+          }
+        ]
+      }
+    }
+  ]
+}
\ No newline at end of file
diff --git a/tests/regression/issue106/stubs/Arduino.h b/tests/regression/issue106/stubs/Arduino.h
new file mode 100644
index 0000000..438cc43
--- /dev/null
+++ b/tests/regression/issue106/stubs/Arduino.h
@@ -0,0 +1,9 @@
+// Minimal host stub of Arduino.h for native Si5351 harness
+#ifndef ARDUINO_STUB_H
+#define ARDUINO_STUB_H
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+typedef bool boolean;
+typedef uint8_t byte;
+#endif
diff --git a/tests/regression/issue106/stubs/Wire.h b/tests/regression/issue106/stubs/Wire.h
new file mode 100644
index 0000000..3830ba5
--- /dev/null
+++ b/tests/regression/issue106/stubs/Wire.h
@@ -0,0 +1,30 @@
+// Multi-bus TwoWire stub: each instance has its own register file + transcript.
+#ifndef WIRE_STUB_H
+#define WIRE_STUB_H
+#include <stdint.h>
+#include <stddef.h>
+#include <string>
+#include <vector>
+class TwoWire {
+public:
+  TwoWire(const char *n) : name(n) { for (int i=0;i<256;i++) regs[i]=(uint8_t)i; regs[0]=0; }
+  void begin() { log.push_back("BEGIN"); }
+  void beginTransmission(uint8_t a) { tx_addr=a; tx.clear(); }
+  size_t write(uint8_t b) { tx.push_back(b); return 1; }
+  uint8_t endTransmission(uint8_t) { return endTransmission(); }
+  uint8_t endTransmission(void) {
+    bool ack = present && tx_addr==0x60;
+    char l[64]; snprintf(l,sizeof l,"TX a=%02X n=%u ack=%d",tx_addr,(unsigned)tx.size(),ack); log.push_back(l);
+    if (ack && !tx.empty()) { ptr=tx[0]; for (size_t i=1;i<tx.size();i++) regs[(uint8_t)(ptr+i-1)]=tx[i]; }
+    return ack?0:2; }
+  uint8_t requestFrom(uint8_t a, uint8_t q) {
+    rx.clear(); rp=0; char l[48]; snprintf(l,sizeof l,"RX a=%02X n=%u",a,q); log.push_back(l);
+    if (present && a==0x60) for (int i=0;i<q;i++) rx.push_back(regs[(uint8_t)(ptr+i)]);
+    return (uint8_t)rx.size(); }
+  int available() { return (int)(rx.size()-rp); }
+  int read() { return rp<rx.size()? rx[rp++] : -1; }
+  const char *name; bool present=false; std::vector<std::string> log;
+  uint8_t regs[256], ptr=0, tx_addr=0; std::vector<uint8_t> tx, rx; size_t rp=0;
+};
+extern TwoWire Wire; extern TwoWire Wire1;
+#endif
diff --git a/tests/regression/issue106/t106.cpp b/tests/regression/issue106/t106.cpp
new file mode 100644
index 0000000..3e451a5
--- /dev/null
+++ b/tests/regression/issue106/t106.cpp
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <string.h>
+#include "si5351.h"
+TwoWire Wire("Wire"); TwoWire Wire1("Wire1");
+static int fails=0;
+#define CHECK(c,msg) do{ bool _c=(c); printf("%s  %s\n", _c?"PASS":"FAIL", msg); if(!_c) fails++; }while(0)
+static void clear(){ Wire.log.clear(); Wire1.log.clear(); Wire.present=Wire1.present=false; }
+int main(){
+  // T1 constructor matrix (compiles => overload resolution OK); check selected bus/addr
+  { Si5351 a;            CHECK(a._wire==&Wire  && a.i2c_bus_addr==0x60, "T1 Si5351 a; -> Wire,0x60"); }
+  { Si5351 b(0x61);      CHECK(b._wire==&Wire  && b.i2c_bus_addr==0x61, "T1 Si5351 b(0x61); -> Wire,0x61"); }
+  { Si5351 c(&Wire1);    CHECK(c._wire==&Wire1 && c.i2c_bus_addr==0x60, "T1 Si5351 c(&Wire1); -> Wire1,0x60"); }
+  { Si5351 d(&Wire1,0x61); CHECK(d._wire==&Wire1 && d.i2c_bus_addr==0x61, "T1 Si5351 d(&Wire1,0x61)"); }
+  { uint8_t addr=0x62; Si5351 e(addr); CHECK(e._wire==&Wire && e.i2c_bus_addr==0x62, "T1 Si5351 e(uint8_t var)"); }
+  { Si5351 *p=new Si5351(&Wire1); CHECK(p->_wire==&Wire1, "T1 new Si5351(&Wire1) (issue #106 line)"); delete p; }
+  // T2 routing: chip on Wire1 only
+  clear(); Wire1.present=true;
+  { Si5351 s(&Wire1); bool r=s.init(SI5351_CRYSTAL_LOAD_8PF,0,0); s.set_freq(1000000000ULL,SI5351_CLK0);
+    CHECK(r, "T2 init() true with chip on Wire1");
+    CHECK(Wire.log.empty(), "T2 zero traffic on Wire (bus0)");
+    CHECK(!Wire1.log.empty() && Wire1.log[0]=="BEGIN", "T2 begin() called on Wire1");
+    printf("      Wire1 events=%zu Wire events=%zu\n",Wire1.log.size(),Wire.log.size());
+    // T5 status reads on selected bus
+    size_t before=Wire1.log.size(); s.update_status();
+    bool rxw1=false; for(size_t i=before;i<Wire1.log.size();i++) if(Wire1.log[i].rfind("RX",0)==0) rxw1=true;
+    CHECK(rxw1 && Wire.log.empty(), "T5 update_status() reads only on Wire1");
+    uint8_t v=s.si5351_read(16); CHECK(v==Wire1.regs[16] && Wire.log.empty(), "T5 si5351_read() returns Wire1 data"); }
+  // T4 no-ACK: chip absent on chosen bus (and the #106 failure: default bus while chip on Wire1)
+  clear(); Wire1.present=true;
+  { Si5351 s; CHECK(!s.init(SI5351_CRYSTAL_LOAD_8PF,0,0) && Wire1.log.empty(), "T4 default-bus object, chip on Wire1 -> init false, Wire1 untouched (old #106 behavior)"); }
+  clear();
+  { Si5351 s(&Wire1); CHECK(!s.init(SI5351_CRYSTAL_LOAD_8PF,0,0) && Wire.log.empty(), "T4 no ACK on Wire1 -> init false, no bus0 fallback"); }
+  // Review #7 additions
+  { Si5351 z(0);    CHECK(z._wire==&Wire && z.i2c_bus_addr==0x00, "T1 Si5351(0) -> address path (Wire,0x00)"); }
+  { Si5351 n(NULL); CHECK(n._wire==&Wire && n.i2c_bus_addr==0x00, "T1 Si5351(NULL) -> address path (Wire,0x00)"); }
+  { Si5351 q(0x61u), r(0x61L), t(0x61UL), u(0x61LL), w(0x61ULL); uint16_t a16=0x61; Si5351 x(a16); char ch=0x61; Si5351 y(ch);
+    CHECK(q.i2c_bus_addr==0x61&&r.i2c_bus_addr==0x61&&t.i2c_bus_addr==0x61&&u.i2c_bus_addr==0x61&&w.i2c_bus_addr==0x61&&x.i2c_bus_addr==0x61&&y.i2c_bus_addr==0x61
+          && q._wire==&Wire && x._wire==&Wire, "T1 all integer types -> address path"); }
+  { TwoWire *np=0; Si5351 g(np); CHECK(g._wire==&Wire, "T1 null TwoWire* variable -> Wire (guard)"); }
+#if __cplusplus >= 201103L
+  { Si5351 g(nullptr); CHECK(g._wire==&Wire && g.i2c_bus_addr==0x60, "T1 Si5351(nullptr) -> Wire,0x60 (guard)"); }
+#endif
+  // T6 two objects on two buses stay isolated
+  clear(); Wire.present=Wire1.present=true;
+  { Si5351 s0, s1(&Wire1);
+    bool r0=s0.init(SI5351_CRYSTAL_LOAD_8PF,0,0); size_t w0=Wire.log.size(), w1=Wire1.log.size();
+    CHECK(r0 && w1==0, "T6 s0.init() touches Wire only");
+    bool r1=s1.init(SI5351_CRYSTAL_LOAD_8PF,0,0); CHECK(r1 && Wire.log.size()==w0, "T6 s1.init() touches Wire1 only");
+    s0.set_freq(1000000000ULL,SI5351_CLK0); w0=Wire.log.size(); w1=Wire1.log.size();
+    s1.set_freq(2500000000ULL,SI5351_CLK1); CHECK(Wire.log.size()==w0, "T6 s1.set_freq no traffic on Wire");
+    size_t w1b=Wire1.log.size(); s0.set_freq(700000000ULL,SI5351_CLK2); CHECK(Wire1.log.size()==w1b, "T6 s0.set_freq no traffic on Wire1");
+    CHECK(memcmp(Wire.regs+42,Wire1.regs+42,24)!=0, "T6 Multisynth regs 42..65 differ between buses (independent state)"); }
+  printf("%s (%d failures)\n", fails?"FAILED":"ALL PASS", fails); return fails!=0;
+}
diff --git a/tests/regression/python/generate_goldens.py b/tests/regression/python/generate_goldens.py
new file mode 100644
index 0000000..c505e69
--- /dev/null
+++ b/tests/regression/python/generate_goldens.py
@@ -0,0 +1,177 @@
+#!/usr/bin/env python3
+"""Regenerate golden_cases.json (library lock + independent spec columns) and golden_cases.md."""
+from __future__ import annotations
+import copy, json
+from pathlib import Path
+
+import si5351_math as L
+from spec_crosscheck import evaluate, DEVIATION_CATALOG, KNOWN_DEVIATIONS
+
+ROOT = Path(__file__).resolve().parent
+
+GOLDEN_CORRECTIONS = [{
+    "cases": ["P0-clk0-DIVBY4-200MHz", "P0-clk0-DIVBY4-boundary-150MHz", "P0-manual-DIVBY4-175MHz-pll700",
+              "P1-parity-gt100-set_freq-vs-manual-175MHz (embedded auto/manual)"],
+    "field": "ms_a",
+    "old": 6, "new": 4,
+    "reason": ("multisynth_calc(freq, pll_freq) sees a = pll/freq = 4 < SI5351_MULTISYNTH_A_MIN, clamps freq = pll/6 "
+               "but does NOT recompute a. The first-draft mirror recomputed a (=6). Registers were never affected "
+               "because DIVBY4 overrides P1/P2/P3 to 0/0/1; only the reported intermediate changes. Mirror now "
+               "matches library exactly (also fixes the same pattern in pll_calc)."),
+}]
+
+
+def library_cases():
+    return L.build_golden_suite() + L.build_spec_coverage_cases()
+
+
+def build():
+    cases = library_cases()
+    out_cases = []
+    for c in cases:
+        c = copy.deepcopy(c)
+        c["spec"] = evaluate(c)
+        out_cases.append(c)
+    n_orig = len(L.build_golden_suite())
+    data = {
+        "source_repo": "https://github.com/etherkit/Si5351Arduino",
+        "source_commit": "0559cbf82865e2957d46af72e70cc88207421434",
+        "source_ref": "master",
+        "library_version": "2.2.0",
+        "spec_sources": {
+            "AN619": "AN619 Rev 0.8 (2021-09-23) Manually Generating an Si5351 Register Map for 10-MSOP and 20-QFN Devices",
+            "DS": "Si5351A/B/C-B datasheet Rev 1.3 (2021-08-27)",
+        },
+        "assumptions": {
+            "xtal_hz_default": L.SI5351_XTAL_FREQ, "freq_mult": L.SI5351_FREQ_MULT,
+            "pll_fixed_lib": L.SI5351_PLL_FIXED, "rfrac_denom": L.RFRAC_DENOM,
+            "correction_default_ppb": 0, "freq_units": "API takes Hz * 100 (SI5351_FREQ_MULT)",
+            "init_xo_freq_0_means": "SI5351_XTAL_FREQ (25 MHz)",
+            "unknown_prior_register_bits": "assumed 0 (reg 44-style byte bit7, reg 92, reg 3 before reset)",
+            "spec_bc_choice": "spec does not prescribe b/c selection; spec registers are encoded from the library's a/b/c",
+            "accuracy_tolerance_ppb": 1000,
+        },
+        "golden_corrections": GOLDEN_CORRECTIONS,
+        "deviation_catalog": DEVIATION_CATALOG,
+        "known_deviation_cases": {k: {"devs": v["devs"], "rules": sorted(v["rules"])} for k, v in KNOWN_DEVIATIONS.items()},
+        "original_case_count": n_orig,
+        "new_case_count": len(out_cases) - n_orig,
+        "case_count": len(out_cases),
+        "cases": out_cases,
+    }
+    return data
+
+
+def fmt_regs(d):
+    if not d:
+        return "—"
+    return " ".join(f"{k}:0x{v:02X}" for k, v in d.items())
+
+
+def write_md(data):
+    L_ = []
+    a = L_.append
+    a("# Golden cases — Si5351Arduino master vs AN619/datasheet")
+    a("")
+    a(f"**Library:** `{data['source_repo']}` @ `{data['source_commit']}` (v{data['library_version']})  ")
+    a(f"**Spec:** {data['spec_sources']['AN619']}; {data['spec_sources']['DS']}")
+    a("")
+    a(f"**Cases:** {data['case_count']} total = {data['original_case_count']} original + {data['new_case_count']} new (S-/D-).")
+    a("")
+    a("Two columns throughout: **Library** = what current master computes/writes (the regression lock — never edited to match the spec). "
+      "**Spec** = independent AN619/datasheet oracle (`spec_oracle.py`). A *deviation* means the library is locked to current "
+      "behaviour but the spec flags it; `test_spec.py` treats those as expected failures (xfail).")
+    a("")
+    a("## Assumptions")
+    for k, v in data["assumptions"].items():
+        a(f"- **{k}:** `{v}`")
+    a("")
+    a("## Golden corrections vs first draft")
+    for g in data["golden_corrections"]:
+        a(f"- `{g['field']}` {g['old']} → {g['new']} in {', '.join(g['cases'])}. {g['reason']}")
+    a("")
+    a("## Summary")
+    a("")
+    a("| Case | Status | Register agreement | Failed spec rules | Known deviation | Advisories |")
+    a("|---|---|---|---|---|---|")
+    for c in data["cases"]:
+        s = c["spec"]
+        a(f"| `{c['id']}` | {s['status']} | {s['register_agreement']} | {', '.join(s['failed_rules']) or '—'} | "
+          f"{', '.join(s['known_deviations']) or '—'} | {', '.join(s['advisories']) or '—'} |")
+    a("")
+    a("## Deviation catalogue")
+    a("")
+    for k, d in data["deviation_catalog"].items():
+        a(f"### {k}: {d['title']}")
+        a(f"- **Library (locked):** {d['library']}")
+        a(f"- **Spec:** {d['spec']}")
+        a(f"- **Rules:** {d['rules']} — **Severity:** {d['severity']}")
+        a("")
+    a("## Per-case detail")
+    a("")
+    for c in data["cases"]:
+        s = c["spec"]
+        a(f"### `{c['id']}`  — {s['status'].upper()}")
+        a("")
+        if c.get("covers"):
+            a(f"Covers: {', '.join(c['covers'])}")
+        if c.get("sequence"):
+            a(f"Sequence: `{' ; '.join(c['sequence'])}`")
+        if c.get("description"):
+            a(c["description"])
+        a("")
+        a("| Item | Library (regression lock) | Spec (AN619/DS) |")
+        a("|---|---|---|")
+        if "input_freq_hz" in c:
+            a(f"| Requested | {c['input_freq_hz']} Hz ({c.get('api')}, CLK{c.get('clk',0)}, {c.get('pll_assignment','')}) | "
+              f"realized from regs: {s.get('realized_hz')} Hz |")
+        if "pll_a" in c:
+            a(f"| PLL a,b,c / P1,P2,P3 | {c['pll_a']},{c['pll_b']},{c['pll_c']} / {c['pll_p1']},{c['pll_p2']},{c['pll_p3']} | "
+              f"fVCO={s.get('fvco_hz')} |")
+        for libk, speck, label in (("lib_pll_regs", None, "PLL regs"), ("lib_plla_regs", None, "MSNA regs"),
+                                   ("lib_pllb_regs", None, "MSNB regs")):
+            if libk in c:
+                a(f"| {label} | {fmt_regs(c[libk])} | {'agree' if s['register_agreement'] else 'see checks'} |")
+        if "ms_p1" in c and c.get("clk_path") == "CLK0-5":
+            a(f"| MS a,b,c / P1,P2,P3 | {c['ms_a']},{c['ms_b']},{c['ms_c']} / {c['ms_p1']},{c['ms_p2']},{c['ms_p3']} | "
+              f"ratio={s.get('ms_ratio')} |")
+            a(f"| R_DIV / DIVBY4 / MS_INT | {c['r_div_name']} / {c['div_by_4']} / {c['int_mode']} | |")
+        if "lib_ms_regs" in c:
+            a(f"| MS block | {fmt_regs(c['lib_ms_regs'])} | {fmt_regs(s.get('spec_ms_regs'))} |")
+        if "lib_ms67_regs" in c:
+            a(f"| MS6/7 P1 reg | {fmt_regs(c['lib_ms67_regs'])} (R {c.get('r_div_name')}) | "
+              f"{fmt_regs(s.get('spec_ms67_regs')) if s.get('spec_ms67_regs') else 'invalid'}"
+              f"{' ; intended ' + fmt_regs(s['spec_intended_ms67_regs']) if s.get('spec_intended_ms67_regs') else ''} |")
+        if "lib_reg92" in c:
+            a(f"| Reg 92 | 0x{c['lib_reg92']:02X} | 0x{s['spec_reg92']:02X} |")
+        if "lib_clk_ctrl" in c:
+            a(f"| CLK ctrl | {fmt_regs(c['lib_clk_ctrl'])} | {fmt_regs(s.get('spec_clk_ctrl')) if s.get('spec_clk_ctrl') else 'see checks'} |")
+        if "lib_reg3_after" in c:
+            a(f"| Reg 3 (OEB) after | 0x{c['lib_reg3_after']:02X} | bit{c.get('clk',0)} must be 0 to output |")
+        if "lib_vcxo_regs" in c:
+            a(f"| VCXO param / regs 162-164 | {c['vcxo_param']} / {fmt_regs(c['lib_vcxo_regs'])} | exact {s['spec_vcxo_exact']:.4f}, floor {s['spec_vcxo_floor']}, round {s['spec_vcxo_round']} / {fmt_regs(s['spec_vcxo_regs'])} |")
+        if "lib_write" in c:
+            a(f"| Register write | reg {c['lib_write']['reg']} = 0x{c['lib_write']['value']:02X} | see checks |")
+        if "lib_writes" in c:
+            a(f"| Register writes | {', '.join(f'{k}: 0x{v:02X}' for k, v in c['lib_writes'].items())} | see checks |")
+        if "lib_reg177_writes" in c:
+            a(f"| Reg 177 writes | {', '.join(f'0x{v:02X}' for v in c['lib_reg177_writes'])} | 0x20 (PLLA_RST), 0x80 (PLLB_RST) |")
+        a("")
+        bad = [k for k in s["checks"] if not k["ok"]]
+        if bad:
+            a("Failed / advisory checks:")
+            for k in bad:
+                a(f"- **{k['rule']}** ({k['severity']}) — {k['detail']} — _{k['cite']}_")
+            a("")
+    (ROOT / "golden_cases.md").write_text("\n".join(L_) + "\n")
+
+
+def main():
+    data = build()
+    (ROOT / "golden_cases.json").write_text(json.dumps(data, indent=2, default=str))
+    write_md(data)
+    print(f"Wrote {data['case_count']} cases ({data['original_case_count']} original + {data['new_case_count']} new)")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/tests/regression/python/golden_cases.json b/tests/regression/python/golden_cases.json
new file mode 100644
index 0000000..aaae83b
--- /dev/null
+++ b/tests/regression/python/golden_cases.json
@@ -0,0 +1,11747 @@
+{
+  "source_repo": "https://github.com/etherkit/Si5351Arduino",
+  "source_commit": "0559cbf82865e2957d46af72e70cc88207421434",
+  "source_ref": "master",
+  "library_version": "2.2.0",
+  "spec_sources": {
+    "AN619": "AN619 Rev 0.8 (2021-09-23) Manually Generating an Si5351 Register Map for 10-MSOP and 20-QFN Devices",
+    "DS": "Si5351A/B/C-B datasheet Rev 1.3 (2021-08-27)"
+  },
+  "assumptions": {
+    "xtal_hz_default": 25000000,
+    "freq_mult": 100,
+    "pll_fixed_lib": 80000000000,
+    "rfrac_denom": 1000000,
+    "correction_default_ppb": 0,
+    "freq_units": "API takes Hz * 100 (SI5351_FREQ_MULT)",
+    "init_xo_freq_0_means": "SI5351_XTAL_FREQ (25 MHz)",
+    "unknown_prior_register_bits": "assumed 0 (reg 44-style byte bit7, reg 92, reg 3 before reset)",
+    "spec_bc_choice": "spec does not prescribe b/c selection; spec registers are encoded from the library's a/b/c",
+    "accuracy_tolerance_ppb": 1000
+  },
+  "golden_corrections": [
+    {
+      "cases": [
+        "P0-clk0-DIVBY4-200MHz",
+        "P0-clk0-DIVBY4-boundary-150MHz",
+        "P0-manual-DIVBY4-175MHz-pll700",
+        "P1-parity-gt100-set_freq-vs-manual-175MHz (embedded auto/manual)"
+      ],
+      "field": "ms_a",
+      "old": 6,
+      "new": 4,
+      "reason": "multisynth_calc(freq, pll_freq) sees a = pll/freq = 4 < SI5351_MULTISYNTH_A_MIN, clamps freq = pll/6 but does NOT recompute a. The first-draft mirror recomputed a (=6). Registers were never affected because DIVBY4 overrides P1/P2/P3 to 0/0/1; only the reported intermediate changes. Mirror now matches library exactly (also fixes the same pattern in pll_calc)."
+    }
+  ],
+  "deviation_catalog": {
+    "DEV-01-FOUT-MAX-225": {
+      "title": "Library accepts CLK0-5 output up to 225 MHz; spec max is 200 MHz",
+      "library": "SI5351_MULTISYNTH_MAX_FREQ = 225000000; set_freq clamps to 225 MHz, programs DIVBY4 with fVCO=4*Fout (e.g. 210 MHz -> VCO 840 MHz, 250 MHz request -> 225 MHz/VCO 900 MHz)",
+      "spec": "DS Table 7 FCLK max 200 MHz; AN619 \u00a72 MS output 500 kHz-200 MHz; AN619 \u00a74.1.3 DIVBY4 range 150 < Fout <= 200 MHz",
+      "rules": "OUT_FREQ_RANGE, MS_OUT_RANGE (+OUT_FREQ_ACCURACY when clamped)",
+      "severity": "medium"
+    },
+    "DEV-02-FOUT-MIN-4K": {
+      "title": "Library min CLK0-5 output is 4 kHz; datasheet min is 2.5 kHz",
+      "library": "SI5351_CLKOUT_MIN_FREQ = 4000; 2.5 kHz request silently becomes 4 kHz (R=128, MS 512 kHz)",
+      "spec": "DS Table 7 FCLK min 0.0025 MHz; AN619 \u00a72 'down to 2.5 kHz' (note AN619 \u00a74.2.2 says 8 kHz: docs disagree)",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "low (conservative)"
+    },
+    "DEV-03-CLK67-LOWFREQ-P1-TRUNC": {
+      "title": "CLK6/7 low-frequency request writes MS6_P1 = 0 (uint8 truncation of 256)",
+      "library": "set_freq(<18.454 kHz, CLK6/7) clamps to 4 kHz (CLKOUT_MIN, not CLKOUT67_MIN), select_r_div_ms67 picks R=1, multisynth67_calc clamps to 500 kHz, a=254 -> PLL 127 MHz < VCO_MIN -> a+=2 = 256 -> reg->p1=(uint8_t)256 = 0; set_pll(128 MHz) is clamped to 600 MHz inside pll_calc but pllb_freq stores 128 MHz",
+      "spec": "AN619 Reg 90/91: MS6/7 ratio even integer 6..254; AN619 \u00a72 VCO 600-900 MHz",
+      "rules": "MS67_RATIO_VALID, VCO_REQUEST_RANGE, OUT_FREQ_ACCURACY",
+      "severity": "high"
+    },
+    "DEV-04-MS-RATIO-6-TO-8": {
+      "title": "Library permits output MS ratios in [6,8) other than 6 (odd 7, fractional 6.x, 7.x)",
+      "library": "multisynth_calc(freq, pll_freq) only clamps a<6 / a>1800; set_freq_manual(100 MHz, 700 MHz) -> ratio 7; (90 MHz, 600 MHz) -> 6.666666",
+      "spec": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2: valid ratios 4, 6, 8, or 8+1/1048575 .. 2048",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium (set_freq_manual / mixed-PLL scenarios)"
+    },
+    "DEV-05-MS-STALE-A": {
+      "title": "multisynth_calc keeps stale a after the a<6 clamp -> programs ratio 5",
+      "library": "a = pll/freq = 5; freq = pll/6 but a is not recomputed; b = 0 -> P1 = 128 (ratio 5). set_freq_manual(140 MHz, 700 MHz)",
+      "spec": "AN619 \u00a72.1.1: ratio 5 invalid",
+      "rules": "MS_RATIO_VALID",
+      "severity": "medium"
+    },
+    "DEV-06-DIVBY4-PRECONDITION": {
+      "title": "set_freq_manual forces DIVBY4 for Fout >= 150 MHz regardless of pll_freq",
+      "library": "set_freq_manual(175 MHz, 800 MHz) writes DIVBY4 (P=0,0,1) -> actual output 200 MHz",
+      "spec": "AN619 \u00a74.1.3 'Set the appropriate feedback Multisynth to generate fVCO = Fout*4'",
+      "rules": "OUT_FREQ_ACCURACY",
+      "severity": "medium (documented 'track settings yourself' API)"
+    },
+    "DEV-07-VCXO-CENTER-112M5": {
+      "title": "VCXO-linked output above 112.5 MHz (library example si5351_vcxo.ino uses 146 MHz)",
+      "library": "No check; example tunes CLK0 = 146 MHz on VCXO PLLB 876 MHz",
+      "spec": "DS \u00a74.2 'Multisynth ... synthesizes the VCXO output's center frequency up to 112.5 MHz'",
+      "rules": "VCXO_CENTER_MAX",
+      "severity": "low (example/precondition)"
+    },
+    "DEV-08-VCXO-C-NOT-PRESERVED": {
+      "title": "VCXO requirement c = 10^6 on MSNB is lost after later set_pll() calls",
+      "library": "set_vcxo() does not update pllb_freq; set_correction()/set_pll_input() re-run set_pll(pllb_freq=800 MHz) -> MSNB a=32,b=0,c=1. set_freq_manual(..., 875 MHz) after set_vcxo(875 MHz) re-runs non-VCXO pll_calc -> b=0 -> c=1",
+      "spec": "AN619 \u00a73.2 & \u00a77: 'Feedback B Multisynth divider ratio must be set such that ... c ... is fixed to 10^6'",
+      "rules": "VCXO_C_FIXED, VCXO_PLL_PRESERVED",
+      "severity": "medium"
+    },
+    "DEV-09-PHOFF-CLK67": {
+      "title": "set_phase(CLK6/7) writes reserved registers 171/172",
+      "library": "si5351_write(SI5351_CLK0_PHASE_OFFSET + clk, phase) with no clk bound",
+      "spec": "AN619 \u00a76 & Reg 165-170: phase offset only for CLK0-5; 171-176 Reserved",
+      "rules": "PHOFF_ADDR",
+      "severity": "low"
+    },
+    "DEV-10-XTAL-CL-0PF": {
+      "title": "SI5351_CRYSTAL_LOAD_0PF writes reserved XTAL_CL = 00b",
+      "library": "init(SI5351_CRYSTAL_LOAD_0PF, ...) -> reg183 = 0x12",
+      "spec": "AN619 Reg 183: XTAL_CL 00 'Reserved. Do not select this option.'",
+      "rules": "XTAL_CL_RESERVED",
+      "severity": "low"
+    },
+    "DEV-11-SET_INT-CLK67-IS-FB_INT": {
+      "title": "set_int(CLK6/7) toggles FBA_INT/FBB_INT (reg 22/23 bit 6), not an MS6/7 integer bit",
+      "library": "set_int() writes bit 6 of SI5351_CLK0_CTRL+clk for any clk; on fractional PLLA this forces MSNA integer mode",
+      "spec": "AN619 Reg 22/23 bit 6 = FBA_INT/FBB_INT; \u00a73.2.1 only for even-integer feedback; \u00a74.1.2.1 MS6/7 have no INT bit",
+      "rules": "FB_INT_ONLY_EVEN_INT",
+      "severity": "medium"
+    },
+    "DEV-12-CLKIN-DIV-RMW": {
+      "title": "set_pll_input ORs CLKIN_DIV into reg 15 without clearing the old field",
+      "library": "reg_val |= clkin_div (the &= ~SI5351_CLKIN_DIV_MASK line is commented out): prior /2 (01b) + new /4 (10b) -> 11b = /8",
+      "spec": "AN619 Reg 15 CLKIN_DIV[1:0] is a 2-bit field (00 /1, 01 /2, 10 /4, 11 /8)",
+      "rules": "CLKIN_DIV_FIELD",
+      "severity": "medium (Si5351C/CLKIN users)"
+    },
+    "DEV-13-PLL-STALE-A": {
+      "title": "pll_calc keeps stale a after a>90 clamp (non-25/27 MHz reference)",
+      "library": "5 MHz reference: a = 160 > 90, freq clamped to 450 MHz but a not recomputed; P1 = 19968 (ratio 160)",
+      "spec": "AN619 \u00a73.2 feedback ratio 15..90; AN619 \u00a73.1.2 PLL input 10-40 MHz; DS Table 6/8 XTAL 25-27 MHz",
+      "rules": "FB_RATIO_RANGE, REF_RANGE",
+      "severity": "low (out-of-spec reference)"
+    },
+    "DEV-14-CLK67-NOT-ENABLED": {
+      "title": "set_freq() on CLK6/CLK7 never enables the output (reg 3 OEB bit stays 1)",
+      "library": "CLK0-5 branch calls output_enable(clk,1) on first set; CLK6/7 branch has no output_enable(); reset() disabled all outputs",
+      "spec": "AN619 Reg 3 CLKx_OEB: 1 = output disabled",
+      "rules": "OUTPUT_ENABLED_AFTER_SET",
+      "severity": "medium (functional; recommend hardware confirmation)"
+    },
+    "DEV-15-MANUAL-CLK67": {
+      "title": "set_freq_manual() on CLK6/7 writes a truncated fractional-MS P1 to reg 90/91",
+      "library": "set_freq_manual(87.4 MHz, 874 MHz, CLK7): multisynth_calc gives a=10,b=0,c=1 -> P1=128*10-512=768; set_ms writes (uint8_t)768 = 0x00 to reg 91",
+      "spec": "AN619 \u00a74.1.2 / Reg 91: 'For MS6 and MS7, set MSx_P1 directly (e.g., MSx_P1 = divide value)' -> 10 (0x0A)",
+      "rules": "MS67_RATIO_VALID, OUT_FREQ_ACCURACY",
+      "severity": "high (silent wrong output)"
+    }
+  },
+  "known_deviation_cases": {
+    "P0-clk6-23MHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-clk7-874MHz-even-div-of-clk6-pll": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "P0-vcxo-manual-146MHz-on-876pll": {
+      "devs": [
+        "DEV-07-VCXO-CENTER-112M5"
+      ],
+      "rules": [
+        "VCXO_CENTER_MAX"
+      ]
+    },
+    "S-clk6-R6div-100kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk7-R7div-50kHz": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "S-clk6-150MHz-upper-clamp": {
+      "devs": [
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "OUTPUT_ENABLED_AFTER_SET"
+      ]
+    },
+    "D-clk0-210MHz-above-spec-max": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-250MHz-clamped-to-225": {
+      "devs": [
+        "DEV-01-FOUT-MAX-225"
+      ],
+      "rules": [
+        "MS_OUT_RANGE",
+        "OUT_FREQ_ACCURACY",
+        "OUT_FREQ_RANGE"
+      ]
+    },
+    "D-clk0-2p5kHz-clamped-to-4kHz": {
+      "devs": [
+        "DEV-02-FOUT-MIN-4K"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-clk6-10kHz-ms6-p1-zero": {
+      "devs": [
+        "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+        "DEV-14-CLK67-NOT-ENABLED"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUTPUT_ENABLED_AFTER_SET",
+        "OUT_FREQ_ACCURACY",
+        "VCO_REQUEST_RANGE"
+      ]
+    },
+    "D-manual-100MHz-pll700-ratio7": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-90MHz-pll600-ratio6p67": {
+      "devs": [
+        "DEV-04-MS-RATIO-6-TO-8"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-140MHz-pll700-stale-a5": {
+      "devs": [
+        "DEV-05-MS-STALE-A"
+      ],
+      "rules": [
+        "MS_RATIO_VALID"
+      ]
+    },
+    "D-manual-175MHz-pll800-divby4-precondition": {
+      "devs": [
+        "DEV-06-DIVBY4-PRECONDITION"
+      ],
+      "rules": [
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-vcxo-then-set_correction-clobbers-pllb": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED",
+        "VCXO_PLL_PRESERVED"
+      ]
+    },
+    "D-vcxo-875MHz-then-manual-rewrites-c1": {
+      "devs": [
+        "DEV-08-VCXO-C-NOT-PRESERVED"
+      ],
+      "rules": [
+        "VCXO_C_FIXED"
+      ]
+    },
+    "D-manual-clk7-87p4MHz-p1-truncated": {
+      "devs": [
+        "DEV-15-MANUAL-CLK67"
+      ],
+      "rules": [
+        "MS67_RATIO_VALID",
+        "OUT_FREQ_ACCURACY"
+      ]
+    },
+    "D-set_phase-clk6-writes-reserved-171": {
+      "devs": [
+        "DEV-09-PHOFF-CLK67"
+      ],
+      "rules": [
+        "PHOFF_ADDR"
+      ]
+    },
+    "D-init-crystal-load-0pF-reserved": {
+      "devs": [
+        "DEV-10-XTAL-CL-0PF"
+      ],
+      "rules": [
+        "XTAL_CL_RESERVED"
+      ]
+    },
+    "D-set_int-clk6-sets-FBA_INT-on-fractional-plla": {
+      "devs": [
+        "DEV-11-SET_INT-CLK67-IS-FB_INT"
+      ],
+      "rules": [
+        "FB_INT_ONLY_EVEN_INT"
+      ]
+    },
+    "D-set_pll_input-clkin_div-or-without-clear": {
+      "devs": [
+        "DEV-12-CLKIN-DIV-RMW"
+      ],
+      "rules": [
+        "CLKIN_DIV_FIELD"
+      ]
+    },
+    "D-ref5MHz-pll_calc-stale-a160": {
+      "devs": [
+        "DEV-13-PLL-STALE-A"
+      ],
+      "rules": [
+        "FB_RATIO_RANGE",
+        "REF_RANGE"
+      ]
+    }
+  },
+  "original_case_count": 27,
+  "new_case_count": 40,
+  "case_count": 67,
+  "cases": [
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-1-14MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-2-10MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 38,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 38,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 38, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 700000000,
+      "input_freq_hz": 7000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 700000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 114,
+      "ms_b": 285714,
+      "ms_c": 1000000,
+      "ms_p1": 14116,
+      "ms_p2": 571392,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        55,
+        36,
+        248,
+        184,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-3-7MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 55,
+        "46": 36,
+        "47": 248,
+        "48": 184,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 55,
+          "46": 36,
+          "47": 248,
+          "48": 184,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 7000000.0175,
+        "ms_ratio": "57142857/500000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[14116, 571392, 1000000] spec=[14116, 571392, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 55, '46': 36, '47': 248, '48': 184, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=14116 P2=571392 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=114.285714000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=7000000.018 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=7000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=7000000.017500 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 2800000000,
+      "input_freq_hz": 28000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2800000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 28,
+      "ms_b": 571428,
+      "ms_c": 1000000,
+      "ms_p1": 3145,
+      "ms_p2": 142784,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        12,
+        73,
+        242,
+        45,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-common-4-28MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_or_integer_MS",
+        "existing_PLLA_800MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 12,
+        "46": 73,
+        "47": 242,
+        "48": 45,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 12,
+          "46": 73,
+          "47": 242,
+          "48": 45,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 28000000.56000001,
+        "ms_ratio": "7142857/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[3145, 142784, 1000000] spec=[3145, 142784, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 12, '46': 73, '47': 242, '48': 45, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3145 P2=142784 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=28.571428000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=28000000.560 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=28000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=28000000.560000 Hz err=20.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1600000000,
+      "input_freq_hz": 16000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1600000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 50,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 5888,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        23,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-integer-MS-16MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "integer_MS",
+        "b_eq_0"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 23,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 23,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 16000000.0,
+        "ms_ratio": "50",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[5888, 0, 1] spec=[5888, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 23, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=5888 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=50.000000000 (=50)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 50 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=16000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=16000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1407000000,
+      "input_freq_hz": 14070000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1407000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 56,
+      "ms_b": 858564,
+      "ms_c": 1000000,
+      "ms_p1": 6765,
+      "ms_p2": 896192,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        109,
+        253,
+        172,
+        192
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk0-fractional-MS-14p07MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "fractional_MS"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 109,
+        "47": 253,
+        "48": 172,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 109,
+          "47": 253,
+          "48": 172,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14070000.0794955,
+        "ms_ratio": "14214641/250000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6765, 896192, 1000000] spec=[6765, 896192, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 109, '47': 253, '48': 172, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6765 P2=896192 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=56.858564000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14070000.079 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14070000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14070000.079496 Hz err=5.650 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 840000,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 520000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        247,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-clk0-gt100MHz-recalc-pll-112MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK0-5",
+        "recalc_pll",
+        "gt_SHARE_MAX"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 247,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112000000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 896000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 520000, 1000000] spec=[4075, 520000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 247, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=520000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.840000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=896000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "P0-manual-DIVBY4-175MHz-pll700",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "int_mode",
+        "set_freq_manual",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "pll_assignment": "PLLB",
+      "lib_ms_regs": {
+        "50": 0,
+        "51": 1,
+        "52": 12,
+        "53": 0,
+        "54": 0,
+        "55": 0,
+        "56": 0,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 108
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 12,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 0,
+          "51": 1,
+          "52": 12,
+          "53": 0,
+          "54": 0,
+          "55": 0,
+          "56": 0,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 108
+        },
+        "realized_hz": 175000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 12, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0} spec={'50': 0, '51': 1, '52': 12, '53': 0, '54': 0, '55': 0, '56': 0, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 108} spec={'17': 108}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=175000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=175000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=175000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-boundary-150MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll",
+        "a_eq_4"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 150000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=150000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "P0-clk0-DIVBY4-200MHz",
+      "priority": "P0",
+      "covers": [
+        "DIVBY4",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-clk1-PLLB-14MHz",
+      "priority": "P0",
+      "covers": [
+        "PLLB_assignment",
+        "CLK0-5"
+      ],
+      "clk": 1,
+      "lib_ms_regs": {
+        "50": 66,
+        "51": 64,
+        "52": 0,
+        "53": 26,
+        "54": 146,
+        "55": 244,
+        "56": 92,
+        "57": 0
+      },
+      "lib_clk_ctrl": {
+        "17": 44
+      },
+      "lib_reg3_after": 253,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "50": 66,
+          "51": 64,
+          "52": 0,
+          "53": 26,
+          "54": 146,
+          "55": 244,
+          "56": 92,
+          "57": 0
+        },
+        "spec_clk_ctrl": {
+          "17": 44
+        },
+        "realized_hz": 14000000.035,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0} spec={'50': 66, '51': 64, '52': 0, '53': 26, '54': 146, '55': 244, '56': 92, '57': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'17': 44} spec={'17': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFD"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.035 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.035000 Hz err=2.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 31,
+      "pll_b": 996800,
+      "pll_c": 1000000,
+      "pll_p1": 3583,
+      "pll_p2": 590400,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr-100000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 31,
+        "pll_b": 996800,
+        "pll_c": 1000000,
+        "pll_p1": 3583,
+        "pll_p2": 590400,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          13,
+          255,
+          249,
+          2,
+          64
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 13,
+        "30": 255,
+        "31": 249,
+        "32": 2,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 13999999.895,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999992.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3583, 590400, 1000000] spec=[3583, 590400, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 13, '30': 255, '31': 249, '32': 2, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3583 P2=590400 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=31.996800000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999992.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=13999999.895 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=13999999.895000 Hz err=-7.500 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1400000000,
+      "input_freq_hz": 14000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": -50000,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1400000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 57,
+      "ms_b": 142857,
+      "ms_c": 1000000,
+      "ms_p1": 6802,
+      "ms_p2": 285696,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 1600,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 204800,
+      "pll_p3": 1000000,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        26,
+        146,
+        244,
+        92,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "P0-corr--50000-14MHz-existing-pll",
+      "priority": "P0",
+      "covers": [
+        "correction_factor"
+      ],
+      "pll_rewritten_by_set_correction": {
+        "pll_a": 32,
+        "pll_b": 1600,
+        "pll_c": 1000000,
+        "pll_p1": 3584,
+        "pll_p2": 204800,
+        "pll_p3": 1000000,
+        "pll_packed_bytes": [
+          66,
+          64,
+          0,
+          14,
+          0,
+          243,
+          32,
+          0
+        ],
+        "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq"
+      },
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 26,
+        "46": 146,
+        "47": 244,
+        "48": 92,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 243,
+        "32": 32,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 26,
+          "46": 146,
+          "47": 244,
+          "48": 92,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 14000000.0,
+        "ms_ratio": "57142857/1000000",
+        "fvco_hz": 799999998.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 204800, 1000000] spec=[3584, 204800, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 0, '31': 243, '32': 32, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=204800 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.001600000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999998.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[6802, 285696, 1000000] spec=[6802, 285696, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0} spec={'42': 66, '43': 64, '44': 0, '45': 26, '46': 146, '47': 244, '48': 92, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=6802 P2=285696 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=57.142857000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=14000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=14000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11200000000,
+      "input_freq_hz": 112000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 89600000000,
+      "pll_freq_hz": 896000000.0,
+      "pll_a": 35,
+      "pll_b": 836416,
+      "pll_c": 1000000,
+      "pll_p1": 4075,
+      "pll_p2": 61248,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        235,
+        240,
+        239,
+        64
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "P0-corr-100000-gt100MHz-112MHz",
+      "priority": "P0",
+      "covers": [
+        "correction_factor",
+        "recalc_pll"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 15,
+        "30": 235,
+        "31": 240,
+        "32": 239,
+        "33": 64
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 111999998.88,
+        "ms_ratio": "8",
+        "fvco_hz": 895999991.04,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4075, 61248, 1000000] spec=[4075, 61248, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64} spec={'26': 66, '27': 64, '28': 0, '29': 15, '30': 235, '31': 240, '32': 239, '33': 64}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4075 P2=61248 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.836416000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=895999991.040 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=111999998.880 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=111999998.880000 Hz err=-10.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "P0-rdiv-128-5kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "select_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 114,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 114,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 114, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 98,
+      "pll_reset": false,
+      "id": "P0-rdiv-64-10kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 98,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 98,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 10000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 98, '45': 111, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 3,
+      "r_div_name": "DIV_8",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 49,
+      "pll_reset": false,
+      "id": "P0-rdiv-8-100kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 49,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 49,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 49, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 40000000,
+      "input_freq_hz": 400000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 1,
+      "r_div_name": "DIV_2",
+      "freq_after_r_div_lib": 80000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1000,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 127488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        1,
+        242,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 17,
+      "pll_reset": false,
+      "id": "P0-rdiv-2-400kHz",
+      "priority": "P0",
+      "covers": [
+        "R_divider"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 17,
+        "45": 242,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 17,
+          "45": 242,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 400000.0,
+        "ms_ratio": "1000",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[127488, 0, 1] spec=[127488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 17, '45': 242, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=127488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1000.000000000 (=1000)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1000 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=800000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 51200000,
+      "input_freq_hz": 512000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 3,
+      "pll_reset": false,
+      "id": "P0-rdiv-1-512kHz-boundary",
+      "priority": "P0",
+      "covers": [
+        "R_divider",
+        "no_r_div"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 3,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 3,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 512000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 3, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=512000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 2300000000,
+      "input_freq_hz": 23000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 2300000000,
+      "ms_a": 38,
+      "ms_p1": 38,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "clk67_ms_register_byte": 38,
+      "id": "P0-clk6-23MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "multisynth67_calc",
+        "PLLB"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 38
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 38
+        },
+        "spec_ms67_regs": {
+          "90": 38
+        },
+        "spec_reg92": 0,
+        "realized_hz": 23000000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=38"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 38} spec={'90': 38}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=23000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=23000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "peer_already_set",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "ms_a": 10,
+      "ms_p1": 10,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 87400000000,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "clk67_ms_register_byte": 10,
+      "id": "P0-clk7-874MHz-even-div-of-clk6-pll",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "peer_even_integer"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 10
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": 87400000.0,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=10"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 10} spec={'91': 10}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87400000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1234567800,
+      "input_freq_hz": 12345678.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": true,
+      "reason": "peer_requires_even_integer_divide_of_pllb",
+      "id": "P0-clk7-reject-noninteger-12p345678MHz",
+      "priority": "P0",
+      "covers": [
+        "CLK6/7",
+        "reject_path"
+      ],
+      "clk": 7,
+      "spec": {
+        "spec_expectation": "reject: requested freq is not an even-integer division of PLLB",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "MS67_REJECT_CONSISTENT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note (even integers 6..254 only)",
+            "detail": "library rejected (peer_requires_even_integer_divide_of_pllb)"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 40,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 184577,
+      "vcxo_bytes": [
+        1,
+        209,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 1,
+        "VXCO_PARAMETERS_MID(163)": 209,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "P0-vcxo-876MHz-40ppm",
+      "priority": "P0",
+      "covers": [
+        "set_vcxo",
+        "PLLB",
+        "vcxo_param"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 1,
+        "163": 209,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 184577.648,
+        "spec_vcxo_floor": 184577,
+        "spec_vcxo_round": 184578,
+        "spec_vcxo_regs": {
+          "162": 1,
+          "163": 209,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=40 requested=40"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=184577 spec=184577"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 1, '163': 209, '164': 2} spec={'162': 1, '163': 209, '164': 2}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=184577.6480: library floors to 184577; round-half-up would give 184578"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14600000000,
+      "input_freq_hz": 146000000.0,
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 256,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "P0-vcxo-manual-146MHz-on-876pll",
+      "priority": "P0",
+      "covers": [
+        "set_freq_manual",
+        "VCXO_companion",
+        "near_DIVBY4"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 146000000.0,
+        "ms_ratio": "6",
+        "fvco_hz": 876000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_CENTER_MAX"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-07-VCXO-CENTER-112M5"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[256, 0, 1] spec=[256, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=256 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.000000000 (=6)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 6 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=146000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=146000000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=146000000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1000000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-set_freq-vs-manual-14MHz-pll800",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity"
+      ],
+      "api": "parity_check",
+      "description": "For freq<=100 MHz, set_freq uses existing PLL and does not call set_pll; set_freq_manual always calls set_pll(pll_freq). MS a/b/c and p1/p2/p3 must match when the same pll_freq is supplied. Differences: set_freq_manual always output_enable(1); set_freq enables only on first set. set_freq skips pll_reset in <=100 MHz branch; set_freq_manual does not reset either.",
+      "auto_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "manual_ms": {
+        "a": 57,
+        "b": 142857,
+        "c": 1000000,
+        "p1": 6802,
+        "p2": 285696,
+        "p3": 1000000,
+        "r_div": 0,
+        "div_by_4": 0
+      },
+      "ms_match": true,
+      "manual_also_writes_pll": true,
+      "manual_pll": {
+        "a": 32,
+        "b": 0,
+        "c": 1,
+        "p1": 3584,
+        "p2": 0,
+        "p3": 1
+      },
+      "clk": 0,
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_MS_MATCH",
+            "ok": true,
+            "severity": "error",
+            "cite": "library parity (no spec rule)",
+            "detail": ""
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-parity-gt100-set_freq-vs-manual-175MHz",
+      "priority": "P1",
+      "covers": [
+        "set_freq_vs_set_freq_manual_parity",
+        "DIVBY4"
+      ],
+      "api": "parity_check",
+      "description": "set_freq(175 MHz) chooses pll_freq via multisynth_calc(freq,0) \u2192 a=4, pll=700 MHz. set_freq_manual(175 MHz, 700 MHz) must yield identical MS p1/p2/p3, div_by_4=1, int_mode=1 and identical PLL a/b/c when correction matches.",
+      "auto": {
+        "api": "set_freq",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_assignment": "PLLA",
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "branch": "recalc_pll_gt_100mhz",
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12,
+        "pll_reset": true
+      },
+      "manual": {
+        "api": "set_freq_manual",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": 17500000000,
+        "input_freq_hz": 175000000.0,
+        "pll_freq_lib": 70000000000,
+        "pll_freq_hz": 700000000.0,
+        "xtal_hz": 25000000,
+        "correction_ppb": 0,
+        "r_div": 0,
+        "r_div_name": "DIV_1",
+        "div_by_4": 1,
+        "int_mode": 1,
+        "ms_a": 4,
+        "ms_b": 0,
+        "ms_c": 1,
+        "ms_p1": 0,
+        "ms_p2": 0,
+        "ms_p3": 1,
+        "pll_a": 28,
+        "pll_b": 0,
+        "pll_c": 1,
+        "pll_p1": 3072,
+        "pll_p2": 0,
+        "pll_p3": 1,
+        "pll_packed_bytes": [
+          0,
+          1,
+          0,
+          12,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_packed_bytes": [
+          0,
+          1,
+          0,
+          0,
+          0,
+          0,
+          0,
+          0
+        ],
+        "ms_div_byte": 12
+      },
+      "ms_match": true,
+      "pll_match": true,
+      "clk": 0,
+      "spec": {
+        "auto_status": "agree",
+        "manual_status": "agree",
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PARITY_SPEC_REGS_EQUAL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2/\u00a74.1.3",
+            "detail": "spec MS registers for auto vs manual"
+          }
+        ]
+      }
+    },
+    {
+      "id": "P1-reset-pll-fixed-800MHz",
+      "priority": "P1",
+      "covers": [
+        "reset",
+        "SI5351_PLL_FIXED",
+        "set_pll"
+      ],
+      "api": "set_pll",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "note": "reset() calls set_pll(SI5351_PLL_FIXED) for both PLLA and PLLB",
+      "clk": 0,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=25000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-reset-pll-blocks-and-reg177",
+      "priority": "S",
+      "api": "reset_plls",
+      "covers": [
+        "MSNA regs 26-33",
+        "MSNB regs 34-41",
+        "PLL reset reg 177",
+        "CLK ctrl regs 16-23"
+      ],
+      "pll_freq_hz": 800000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_plla_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "lib_pllb_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "lib_reg177_writes": [
+        32,
+        128
+      ],
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_PLL_BLOCK_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "REG_PLL_BLOCK_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 26-33 / 34-41",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_177",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 177 (PLLB_RST bit7, PLLA_RST bit5)",
+            "detail": "library=[32, 128] spec=[32, 128]"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-23 (PDN=0, INT=0, SRC per PLL, CLK_SRC=11 own MS, 2 mA)",
+            "detail": "library={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44} spec={'16': 12, '17': 12, '18': 12, '19': 12, '20': 12, '21': 12, '22': 44, '23': 44}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 1000000000,
+      "input_freq_hz": 10000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 1000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 80,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 9728,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        38,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "S-ms5-block-10MHz-clk5",
+      "priority": "S",
+      "covers": [
+        "MS5 regs 82-89 address offset",
+        "reg 21"
+      ],
+      "clk": 5,
+      "lib_ms_regs": {
+        "82": 0,
+        "83": 1,
+        "84": 0,
+        "85": 38,
+        "86": 0,
+        "87": 0,
+        "88": 0,
+        "89": 0
+      },
+      "lib_clk_ctrl": {
+        "21": 12
+      },
+      "lib_reg3_after": 223,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "82": 0,
+          "83": 1,
+          "84": 0,
+          "85": 38,
+          "86": 0,
+          "87": 0,
+          "88": 0,
+          "89": 0
+        },
+        "spec_clk_ctrl": {
+          "21": 12
+        },
+        "realized_hz": 10000000.0,
+        "ms_ratio": "80",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[9728, 0, 1] spec=[9728, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0} spec={'82': 0, '83': 1, '84': 0, '85': 38, '86': 0, '87': 0, '88': 0, '89': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'21': 12} spec={'21': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xDF"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=9728 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=80.000000000 (=80)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 80 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=10000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "S-rdiv-placement-clk2-5kHz",
+      "priority": "S",
+      "covers": [
+        "R2_DIV bits 6:4 of reg 60",
+        "MS2 regs 58-65"
+      ],
+      "clk": 2,
+      "lib_ms_regs": {
+        "58": 0,
+        "59": 1,
+        "60": 114,
+        "61": 111,
+        "62": 0,
+        "63": 0,
+        "64": 0,
+        "65": 0
+      },
+      "lib_clk_ctrl": {
+        "18": 12
+      },
+      "lib_reg3_after": 251,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "58": 0,
+          "59": 1,
+          "60": 114,
+          "61": 111,
+          "62": 0,
+          "63": 0,
+          "64": 0,
+          "65": 0
+        },
+        "spec_clk_ctrl": {
+          "18": 12
+        },
+        "realized_hz": 5000.0,
+        "ms_ratio": "1250",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[159488, 0, 1] spec=[159488, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0} spec={'58': 0, '59': 1, '60': 114, '61': 111, '62': 0, '63': 0, '64': 0, '65': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'18': 12} spec={'18': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFB"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=159488 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1250.000000000 (=1250)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 1250 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=640000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=5000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=5000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 20000000000,
+      "input_freq_hz": 200000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "S-divby4-block-clk3-200MHz",
+      "priority": "S",
+      "covers": [
+        "MS3_DIVBY4 bits 3:2 of reg 68",
+        "MS3_INT reg 19 bit6",
+        "MSNA block"
+      ],
+      "clk": 3,
+      "lib_ms_regs": {
+        "66": 0,
+        "67": 1,
+        "68": 12,
+        "69": 0,
+        "70": 0,
+        "71": 0,
+        "72": 0,
+        "73": 0
+      },
+      "lib_clk_ctrl": {
+        "19": 76
+      },
+      "lib_reg3_after": 247,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "66": 0,
+          "67": 1,
+          "68": 12,
+          "69": 0,
+          "70": 0,
+          "71": 0,
+          "72": 0,
+          "73": 0
+        },
+        "spec_clk_ctrl": {
+          "19": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0} spec={'66': 0, '67': 1, '68': 12, '69': 0, '70': 0, '71': 0, '72': 0, '73': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'19': 76} spec={'19': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xF7"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=200000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 11250000000,
+      "input_freq_hz": 112500000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": true,
+      "id": "S-boundary-112p5MHz-ratio8",
+      "priority": "S",
+      "covers": [
+        "AN619 2.1.1 900/8 boundary",
+        "integer ratio 8"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 112500000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=112500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=112500000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 10000000,
+      "input_freq_hz": 100000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 5,
+      "r_div_name": "DIV_32",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk6-R6div-100kHz",
+      "priority": "S",
+      "covers": [
+        "R6_DIV bits 2:0 of reg 92",
+        "reg 90"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 254
+      },
+      "lib_reg92": 5,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "90": 254
+        },
+        "spec_ms67_regs": {
+          "90": 254
+        },
+        "spec_reg92": 5,
+        "realized_hz": 100000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 254} spec={'90': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=5 spec=5"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 5000000,
+      "input_freq_hz": 50000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 6,
+      "r_div_name": "DIV_64",
+      "freq_after_r_div_lib": 320000000,
+      "ms_a": 254,
+      "ms_p1": 254,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 81280000000,
+      "pll_freq_hz": 812800000.0,
+      "pll_a": 32,
+      "pll_b": 512000,
+      "pll_c": 1000000,
+      "pll_p1": 3649,
+      "pll_p2": 536000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        65,
+        248,
+        45,
+        192
+      ],
+      "clk67_ms_register_byte": 254,
+      "id": "S-clk7-R7div-50kHz",
+      "priority": "S",
+      "covers": [
+        "R7_DIV bits 6:4 of reg 92",
+        "reg 91"
+      ],
+      "clk": 7,
+      "lib_ms67_regs": {
+        "91": 254
+      },
+      "lib_reg92": 96,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 65,
+        "39": 248,
+        "40": 45,
+        "41": 192
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 254
+        },
+        "spec_ms67_regs": {
+          "91": 254
+        },
+        "spec_reg92": 96,
+        "realized_hz": 50000.0,
+        "fvco_hz": 812800000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3649, 536000, 1000000] spec=[3649, 536000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 65, '39': 248, '40': 45, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3649 P2=536000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.512000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=812800000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=254"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=812800000.0 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'91': 254} spec={'91': 254}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=96 spec=96"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=50000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=50000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 15000000000,
+      "input_freq_hz": 150000000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 14999999999,
+      "ms_a": 6,
+      "ms_p1": 6,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 89999999994,
+      "pll_freq_hz": 899999999.94,
+      "pll_a": 35,
+      "pll_b": 999999,
+      "pll_c": 1000000,
+      "pll_p1": 4095,
+      "pll_p2": 999872,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        255,
+        255,
+        65,
+        192
+      ],
+      "clk67_ms_register_byte": 6,
+      "id": "S-clk6-150MHz-upper-clamp",
+      "priority": "S",
+      "covers": [
+        "CLK6 upper bound",
+        "MS6 ratio 6"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 6
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 255,
+        "39": 255,
+        "40": 65,
+        "41": 192
+      },
+      "spec": {
+        "spec_ms67_regs": {
+          "90": 6
+        },
+        "spec_reg92": 0,
+        "realized_hz": 149999995.83333334,
+        "fvco_hz": 899999975.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUTPUT_ENABLED_AFTER_SET"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4095, 999872, 1000000] spec=[4095, 999872, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 255, '39': 255, '40': 65, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4095 P2=999872 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.999999000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=899999975.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=6"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=899999999.94 Hz"
+          },
+          {
+            "rule": "REG_MS67",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "library={'90': 6} spec={'90': 6}"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=150000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=149999995.833333 Hz err=-27.778 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "ppm": 100,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1000000,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        0,
+        240,
+        0,
+        0
+      ],
+      "vcxo_param_raw_from_pll_calc": 4096000000,
+      "vcxo_param": 421888,
+      "vcxo_bytes": [
+        0,
+        112,
+        6
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 0,
+        "VXCO_PARAMETERS_MID(163)": 112,
+        "VXCO_PARAMETERS_HIGH(164)": 6
+      },
+      "id": "S-vcxo-800MHz-100ppm",
+      "priority": "S",
+      "covers": [
+        "VCXO regs 162-164",
+        "c=10^6"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 240,
+        "40": 0,
+        "41": 0
+      },
+      "lib_vcxo_regs": {
+        "162": 0,
+        "163": 112,
+        "164": 6
+      },
+      "spec": {
+        "spec_vcxo_exact": 421888.0,
+        "spec_vcxo_floor": 421888,
+        "spec_vcxo_round": 421888,
+        "spec_vcxo_regs": {
+          "162": 0,
+          "163": 112,
+          "164": 6
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1000000] spec=[3584, 0, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0} spec={'34': 66, '35': 64, '36': 0, '37': 14, '38': 0, '39': 240, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=100 requested=100"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=421888 spec=421888"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 0, '163': 112, '164': 6} spec={'162': 0, '163': 112, '164': 6}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 30,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 138433,
+      "vcxo_bytes": [
+        193,
+        28,
+        2
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 193,
+        "VXCO_PARAMETERS_MID(163)": 28,
+        "VXCO_PARAMETERS_HIGH(164)": 2
+      },
+      "id": "S-vcxo-ppm-clamp-low-10to30",
+      "priority": "S",
+      "covers": [
+        "VCXO APR min 30"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 10,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 193,
+        "163": 28,
+        "164": 2
+      },
+      "spec": {
+        "spec_vcxo_exact": 138433.236,
+        "spec_vcxo_floor": 138433,
+        "spec_vcxo_round": 138433,
+        "spec_vcxo_regs": {
+          "162": 193,
+          "163": 28,
+          "164": 2
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=30 requested=10"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=138433 spec=138433"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 193, '163': 28, '164': 2} spec={'162': 193, '163': 28, '164': 2}"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_vcxo",
+      "pll_freq_lib": 87600000000,
+      "pll_freq_hz": 876000000.0,
+      "ppm": 240,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "pll_a": 35,
+      "pll_b": 40000,
+      "pll_c": 1000000,
+      "pll_p1": 3973,
+      "pll_p2": 120000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        133,
+        241,
+        212,
+        192
+      ],
+      "vcxo_param_raw_from_pll_calc": 4480040000,
+      "vcxo_param": 1107465,
+      "vcxo_bytes": [
+        9,
+        230,
+        16
+      ],
+      "regs": {
+        "VXCO_PARAMETERS_LOW(162)": 9,
+        "VXCO_PARAMETERS_MID(163)": 230,
+        "VXCO_PARAMETERS_HIGH(164)": 16
+      },
+      "id": "S-vcxo-ppm-clamp-high-250to240",
+      "priority": "S",
+      "covers": [
+        "VCXO APR max 240"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "requested_ppm": 250,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 133,
+        "39": 241,
+        "40": 212,
+        "41": 192
+      },
+      "lib_vcxo_regs": {
+        "162": 9,
+        "163": 230,
+        "164": 16
+      },
+      "spec": {
+        "spec_vcxo_exact": 1107465.888,
+        "spec_vcxo_floor": 1107465,
+        "spec_vcxo_round": 1107466,
+        "spec_vcxo_regs": {
+          "162": 9,
+          "163": 230,
+          "164": 16
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "VCXO_PARAM_ROUNDING"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3973, 120000, 1000000] spec=[3973, 120000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 133, '39': 241, '40': 212, '41': 192}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3973 P2=120000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.040000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=876000000.000 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "c=1000000 P3=1000000"
+          },
+          {
+            "rule": "VCXO_APR_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 5 (\u00b130..\u00b1240 ppm)",
+            "detail": "applied ppm=240 requested=250"
+          },
+          {
+            "rule": "VCXO_PARAM_FLOOR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (floor of exact value)",
+            "detail": "library=1107465 spec=1107465"
+          },
+          {
+            "rule": "REG_VCXO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')",
+            "detail": "library={'162': 9, '163': 230, '164': 16} spec={'162': 9, '163': 230, '164': 16}"
+          },
+          {
+            "rule": "VCXO_PARAM_ROUNDING",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a77 (no rounding rule stated)",
+            "detail": "exact=1107465.8880: library floors to 1107465; round-half-up would give 1107466"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-phase-clk0-mask",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "reg 165",
+        "PHOFF[6:0]"
+      ],
+      "clk": 0,
+      "requested_phase": 255,
+      "lib_write": {
+        "reg": 165,
+        "value": 127
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 165"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x7F"
+          },
+          {
+            "rule": "REG_PHOFF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170",
+            "detail": "library=[165, 127] spec=[165, 127]"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "S-xtal-load-6-8-10pF",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "reg 183"
+      ],
+      "lib_writes": {
+        "6pF": 82,
+        "8pF": 146,
+        "10pF": 210
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_183_6pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=82 spec=82"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "6pF: reg183=0x52"
+          },
+          {
+            "rule": "REG_183_8pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=146 spec=146"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "8pF: reg183=0x92"
+          },
+          {
+            "rule": "REG_183_10pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=210 spec=210"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "10pF: reg183=0xD2"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 21000000000,
+      "input_freq_hz": 210000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 84000000000,
+      "pll_freq_hz": 840000000.0,
+      "pll_a": 33,
+      "pll_b": 600000,
+      "pll_c": 1000000,
+      "pll_p1": 3788,
+      "pll_p2": 800000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        14,
+        204,
+        252,
+        53,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-210MHz-above-spec-max",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 14,
+        "30": 204,
+        "31": 252,
+        "32": 53,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 210000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 840000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3788, 800000, 1000000] spec=[3788, 800000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0} spec={'26': 66, '27': 64, '28': 0, '29': 14, '30': 204, '31': 252, '32': 53, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3788 P2=800000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=33.600000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=840000000.000 Hz"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=210000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=210000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=210000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=210000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 25000000000,
+      "input_freq_hz": 250000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "recalc_pll_gt_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 90000000000,
+      "pll_freq_hz": 900000000.0,
+      "pll_a": 36,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 4096,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        16,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "pll_reset": true,
+      "id": "D-clk0-250MHz-clamped-to-225",
+      "priority": "S",
+      "covers": [
+        "Fout max 200 MHz",
+        "clamp"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 16,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 225000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 900000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_OUT_RANGE",
+          "OUT_FREQ_ACCURACY",
+          "OUT_FREQ_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-01-FOUT-MAX-225"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[4096, 0, 1] spec=[4096, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 16, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=4096 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=36.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=900000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 36 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=225000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=225000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=250000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=225000000.000000 Hz err=-100000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 250000,
+      "input_freq_hz": 2500.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 115,
+      "pll_reset": false,
+      "id": "D-clk0-2p5kHz-clamped-to-4kHz",
+      "priority": "S",
+      "covers": [
+        "Fout min 2.5 kHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 115,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 115,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 4000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-02-FOUT-MIN-4K"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=2500.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=4000.000000 Hz err=600000000.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 1000000,
+      "input_freq_hz": 10000.0,
+      "pll_assignment": "PLLB",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "rejected": false,
+      "branch": "set_pllb_from_clk67",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 400000,
+      "ms_a": 256,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 0,
+      "pll_freq_lib": 12800000000,
+      "pll_freq_hz": 128000000.0,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "clk67_ms_register_byte": 0,
+      "pllb_freq_member_lib": 12800000000,
+      "id": "D-clk6-10kHz-ms6-p1-zero",
+      "priority": "S",
+      "covers": [
+        "MS6 even 6..254",
+        "uint8 truncation"
+      ],
+      "clk": 6,
+      "lib_ms67_regs": {
+        "90": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "22": 44
+      },
+      "lib_reg3_after": 255,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 10,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUTPUT_ENABLED_AFTER_SET",
+          "OUT_FREQ_ACCURACY",
+          "VCO_REQUEST_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-03-CLK67-LOWFREQ-P1-TRUNC",
+          "DEV-14-CLK67-NOT-ENABLED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 10, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=128000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'22': 44} spec={'22': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFF"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=10000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS6_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000000,
+      "input_freq_hz": 100000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 7,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 384,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        1,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-100MHz-pll700-ratio7",
+      "priority": "S",
+      "covers": [
+        "MS ratio 7 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 1,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 1,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000000.0,
+        "ms_ratio": "7",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[384, 0, 1] spec=[384, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 1, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=384 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=7.000000000 (=7)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 9000000000,
+      "input_freq_hz": 90000000.0,
+      "pll_freq_lib": 60000000000,
+      "pll_freq_hz": 600000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 6,
+      "ms_b": 666666,
+      "ms_c": 1000000,
+      "ms_p1": 341,
+      "ms_p2": 333248,
+      "ms_p3": 1000000,
+      "pll_a": 24,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 2560,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        10,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        66,
+        64,
+        0,
+        1,
+        85,
+        245,
+        21,
+        192
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-90MHz-pll600-ratio6p67",
+      "priority": "S",
+      "covers": [
+        "MS fractional ratio < 8 invalid"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 0,
+        "45": 1,
+        "46": 85,
+        "47": 245,
+        "48": 21,
+        "49": 192
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 10,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 0,
+          "45": 1,
+          "46": 85,
+          "47": 245,
+          "48": 21,
+          "49": 192
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 90000009.0000009,
+        "ms_ratio": "3333333/500000",
+        "fvco_hz": 600000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-04-MS-RATIO-6-TO-8"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[2560, 0, 1] spec=[2560, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 10, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=2560 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=24.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=600000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 24 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[341, 333248, 1000000] spec=[341, 333248, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192} spec={'42': 66, '43': 64, '44': 0, '45': 1, '46': 85, '47': 245, '48': 21, '49': 192}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=341 P2=333248 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=6.666666000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=90000009.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=90000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=90000009.000001 Hz err=100.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 14000000000,
+      "input_freq_hz": 140000000.0,
+      "pll_freq_lib": 70000000000,
+      "pll_freq_hz": 700000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 5,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 128,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 28,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3072,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        12,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-140MHz-pll700-stale-a5",
+      "priority": "S",
+      "covers": [
+        "multisynth_calc stale a after a<6 clamp"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 0,
+        "46": 128,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 12,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 0,
+          "46": 128,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 140000000.0,
+        "ms_ratio": "5",
+        "fvco_hz": 700000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS_RATIO_VALID"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-05-MS-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3072, 0, 1] spec=[3072, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 12, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3072 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=28.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=700000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 28 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[128, 0, 1] spec=[128, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 0, '46': 128, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=128 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=5.000000000 (=5)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=140000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=140000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 17500000000,
+      "input_freq_hz": 175000000.0,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 1,
+      "int_mode": 1,
+      "ms_a": 4,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 0,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        14,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 12,
+      "id": "D-manual-175MHz-pll800-divby4-precondition",
+      "priority": "S",
+      "covers": [
+        "DIVBY4 requires fVCO = 4*Fout"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLA",
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 12,
+        "45": 0,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 76
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 12,
+          "45": 0,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 76
+        },
+        "realized_hz": 200000000.0,
+        "ms_ratio": "4",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-06-DIVBY4-PRECONDITION"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 12, '45': 0, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 76} spec={'16': 76}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "DIVBY4_PARAMS",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (P1=0,P2=0,P3=1)",
+            "detail": "P=(0,0,1)"
+          },
+          {
+            "rule": "DIVBY4_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (MSx_INT=1)",
+            "detail": "MS_INT=1"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=200000000.000 Hz"
+          },
+          {
+            "rule": "DIVBY4_REQUIRED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+            "detail": "f_MS=200000000.000 Hz divby4=1"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=175000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=200000000.000000 Hz err=142857142.857 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-vcxo-then-set_correction-clobbers-pllb",
+      "priority": "S",
+      "api": "vcxo_sequence",
+      "covers": [
+        "set_vcxo does not update pllb_freq",
+        "VCXO c=10^6"
+      ],
+      "sequence": [
+        "reset()",
+        "set_vcxo(87600000000ULL, 40)",
+        "set_correction(0, SI5351_PLL_INPUT_XO)"
+      ],
+      "vcxo_context": true,
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 40000,
+        "c": 1000000,
+        "p1": 3973,
+        "p2": 120000,
+        "p3": 1000000
+      },
+      "pllb_freq_member_lib": 80000000000,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 14,
+        "38": 0,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED",
+          "VCXO_PLL_PRESERVED"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 14, '38': 0, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3 after sequence=1"
+          },
+          {
+            "rule": "VCXO_PLL_PRESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a77 (PLLB is the VCXO)",
+            "detail": "MSNB ratio after set_vcxo=35.04 after sequence=32.0"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 8750000000,
+      "input_freq_hz": 87500000.0,
+      "pll_freq_lib": 87500000000,
+      "pll_freq_hz": 875000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 35,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_packed_bytes": [
+        0,
+        1,
+        0,
+        15,
+        128,
+        0,
+        0,
+        0
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "sequence": [
+        "reset()",
+        "set_vcxo(87500000000ULL, 40)",
+        "set_ms_source(SI5351_CLK0, SI5351_PLLB)",
+        "set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0)"
+      ],
+      "pllb_after_set_vcxo": {
+        "a": 35,
+        "b": 0,
+        "c": 1000000,
+        "p1": 3968,
+        "p2": 0,
+        "p3": 1000000
+      },
+      "id": "D-vcxo-875MHz-then-manual-rewrites-c1",
+      "priority": "S",
+      "covers": [
+        "VCXO c=10^6 lost via set_pll"
+      ],
+      "clk": 0,
+      "pll_assignment": "PLLB",
+      "vcxo_context": true,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 3,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 44
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "34": 0,
+        "35": 1,
+        "36": 0,
+        "37": 15,
+        "38": 128,
+        "39": 0,
+        "40": 0,
+        "41": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 3,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 44
+        },
+        "realized_hz": 87500000.0,
+        "ms_ratio": "10",
+        "fvco_hz": 875000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "VCXO_C_FIXED"
+        ],
+        "advisories": [
+          "MS_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-08-VCXO-C-NOT-PRESERVED"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3968, 0, 1] spec=[3968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0} spec={'34': 0, '35': 1, '36': 0, '37': 15, '38': 128, '39': 0, '40': 0, '41': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=35.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=875000000.000 Hz"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[768, 0, 1] spec=[768, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 3, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 44} spec={'16': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=768 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=10.000000000 (=10)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 10 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87500000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=87500000.000000 Hz err=0.000 ppb"
+          },
+          {
+            "rule": "VCXO_CENTER_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS \u00a74.2 (VCXO center <= 112.5 MHz)",
+            "detail": "Fout=87500000.0 Hz"
+          },
+          {
+            "rule": "VCXO_C_FIXED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a77 (MSNB c = 10^6)",
+            "detail": "MSNB P3=c=1"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq_manual",
+      "clk_path": "CLK6/7",
+      "input_freq_lib": 8740000000,
+      "input_freq_hz": 87400000.0,
+      "pll_freq_lib": 87400000000,
+      "pll_freq_hz": 874000000.0,
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 10,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 768,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_a": 34,
+      "pll_b": 960000,
+      "pll_c": 1000000,
+      "pll_p1": 3962,
+      "pll_p2": 880000,
+      "pll_p3": 1000000,
+      "pll_packed_bytes": [
+        66,
+        64,
+        0,
+        15,
+        122,
+        253,
+        109,
+        128
+      ],
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        3,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "id": "D-manual-clk7-87p4MHz-p1-truncated",
+      "priority": "S",
+      "clk": 7,
+      "pll_assignment": "PLLB",
+      "covers": [
+        "set_freq_manual on CLK6/7",
+        "reg 91"
+      ],
+      "sequence": [
+        "reset()",
+        "set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7)"
+      ],
+      "lib_ms67_regs": {
+        "91": 0
+      },
+      "lib_reg92": 0,
+      "lib_clk_ctrl": {
+        "23": 44
+      },
+      "lib_reg3_after": 127,
+      "lib_pll_regs": {
+        "34": 66,
+        "35": 64,
+        "36": 0,
+        "37": 15,
+        "38": 122,
+        "39": 253,
+        "40": 109,
+        "41": 128
+      },
+      "spec": {
+        "spec_intended_ms67_regs": {
+          "91": 10
+        },
+        "spec_reg92": 0,
+        "realized_hz": null,
+        "fvco_hz": 874000000.0,
+        "register_agreement": true,
+        "failed_rules": [
+          "MS67_RATIO_VALID",
+          "OUT_FREQ_ACCURACY"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-15-MANUAL-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3962, 880000, 1000000] spec=[3962, 880000, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128} spec={'34': 66, '35': 64, '36': 0, '37': 15, '38': 122, '39': 253, '40': 109, '41': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3962 P2=880000 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=34.960000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=874000000.000 Hz"
+          },
+          {
+            "rule": "MS67_RATIO_VALID",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a72.2 Note, \u00a74.1.2, Reg 90/91 (even integer 6..254)",
+            "detail": "MSx_P1=0"
+          },
+          {
+            "rule": "VCO_REQUEST_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz); library stores requested value in pllb_freq",
+            "detail": "requested PLLB=874000000.0 Hz"
+          },
+          {
+            "rule": "REG_92",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22/23",
+            "detail": "library={'23': 44} spec={'23': 44}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0x7F"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=87400000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 90/91",
+            "detail": "undefined output: MS7_P1=0"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_phase-clk6-writes-reserved-171",
+      "priority": "S",
+      "api": "set_phase",
+      "covers": [
+        "phase regs only CLK0-5"
+      ],
+      "clk": 6,
+      "requested_phase": 10,
+      "lib_write": {
+        "reg": 171,
+        "value": 10
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "PHOFF_ADDR"
+        ],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-09-PHOFF-CLK67"
+        ],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 171"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x0A"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-init-crystal-load-0pF-reserved",
+      "priority": "S",
+      "api": "init_xtal_load",
+      "covers": [
+        "XTAL_CL=00 reserved"
+      ],
+      "lib_writes": {
+        "0pF": 18
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "XTAL_CL_RESERVED"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-10-XTAL-CL-0PF"
+        ],
+        "checks": [
+          {
+            "rule": "REG_183_0pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=18 spec=18"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "0pF: reg183=0x12"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_int-clk6-sets-FBA_INT-on-fractional-plla",
+      "priority": "S",
+      "api": "set_int",
+      "covers": [
+        "reg 22 bit6 = FBA_INT"
+      ],
+      "clk": 6,
+      "sequence": [
+        "reset()",
+        "set_correction(100000, SI5351_PLL_INPUT_XO)",
+        "set_int(SI5351_CLK6, 1)"
+      ],
+      "lib_write": {
+        "reg": 22,
+        "value": 108
+      },
+      "plla": {
+        "a": 31,
+        "b": 996800,
+        "c": 1000000,
+        "p1": 3583,
+        "p2": 590400,
+        "p3": 1000000
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "FB_INT_ONLY_EVEN_INT"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-11-SET_INT-CLK67-IS-FB_INT"
+        ],
+        "checks": [
+          {
+            "rule": "FB_INT_ONLY_EVEN_INT",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2.1 / Reg 22 bit6 FBA_INT (only for even-integer a+b/c)",
+            "detail": "reg22=0x6C -> FBA_INT=1; MSNA ratio=31.996800000"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-set_pll_input-clkin_div-or-without-clear",
+      "priority": "S",
+      "api": "set_pll_input",
+      "covers": [
+        "reg 15 CLKIN_DIV[1:0]"
+      ],
+      "sequence": [
+        "(reg15 = 0x44 from earlier CLKIN @ 40 MHz)",
+        "set_ref_freq(80000000, CLKIN)",
+        "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"
+      ],
+      "prior_reg15": 68,
+      "intended_clkin_div": 4,
+      "lib_write": {
+        "reg": 15,
+        "value": 196
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [
+          "CLKIN_DIV_FIELD"
+        ],
+        "advisories": [],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-12-CLKIN-DIV-RMW"
+        ],
+        "checks": [
+          {
+            "rule": "CLKIN_DIV_FIELD",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 Reg 15 CLKIN_DIV[1:0]",
+            "detail": "reg15=0xC4 -> CLKIN_DIV=11b (/8); intended /4"
+          }
+        ]
+      }
+    },
+    {
+      "id": "D-ref5MHz-pll_calc-stale-a160",
+      "priority": "S",
+      "api": "set_pll",
+      "covers": [
+        "feedback ratio 15..90",
+        "PLL input 10..40 MHz"
+      ],
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 5000000, 0)  -> reset() -> set_pll(800 MHz)"
+      ],
+      "pll_freq_lib": 80000000000,
+      "xtal_hz": 5000000,
+      "correction_ppb": 0,
+      "pll_a": 160,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 19968,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "pll_calc_return_lib": 80000000000,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 78,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [
+          "FB_RATIO_RANGE",
+          "REF_RANGE"
+        ],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "deviation",
+        "known_deviations": [
+          "DEV-13-PLL-STALE-A"
+        ],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[19968, 0, 1] spec=[19968, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 78, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=19968 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=160.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 160 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": false,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=5000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 10000000000,
+      "input_freq_hz": 100000000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 0,
+      "r_div_name": "DIV_1",
+      "freq_after_r_div_lib": 10000000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 8,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 512,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 0,
+      "pll_reset": false,
+      "id": "F-clk0-100MHz-share-max-boundary",
+      "priority": "S",
+      "covers": [
+        "<=100 MHz branch boundary",
+        "ratio 8 on 800 MHz"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 0,
+        "45": 2,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 0,
+          "45": 2,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 100000000.0,
+        "ms_ratio": "8",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY",
+          "MS_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[512, 0, 1] spec=[512, 0, 1]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0} spec={'42': 0, '43': 1, '44': 0, '45': 2, '46': 0, '47': 0, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=512 P2=0 P3=1"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=8.000000000 (=8)"
+          },
+          {
+            "rule": "MS_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a72.1.1 item 2, \u00a74.1.2.1",
+            "detail": "MS ratio 8 is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=100000000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=100000000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_freq",
+      "clk_path": "CLK0-5",
+      "input_freq_lib": 400000,
+      "input_freq_hz": 4000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 51200000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1562,
+      "ms_b": 500000,
+      "ms_c": 1000000,
+      "ms_p1": 199488,
+      "ms_p2": 0,
+      "ms_p3": 1000000,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        66,
+        64,
+        3,
+        11,
+        64,
+        240,
+        0,
+        0
+      ],
+      "ms_div_byte": 115,
+      "pll_reset": false,
+      "id": "F-clk0-4kHz-library-min",
+      "priority": "S",
+      "covers": [
+        "CLKOUT_MIN",
+        "R=128"
+      ],
+      "clk": 0,
+      "lib_ms_regs": {
+        "42": 66,
+        "43": 64,
+        "44": 115,
+        "45": 11,
+        "46": 64,
+        "47": 240,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 66,
+          "43": 64,
+          "44": 115,
+          "45": 11,
+          "46": 64,
+          "47": 240,
+          "48": 0,
+          "49": 0
+        },
+        "spec_clk_ctrl": {
+          "16": 12
+        },
+        "realized_hz": 4000.0,
+        "ms_ratio": "3125/2",
+        "fvco_hz": 800000000.0,
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          },
+          {
+            "rule": "MS_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2 MSx_P1/P2/P3 equations",
+            "detail": "library=[199488, 0, 1000000] spec=[199488, 0, 1000000]"
+          },
+          {
+            "rule": "REG_MS_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)",
+            "detail": "library={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0} spec={'42': 66, '43': 64, '44': 115, '45': 11, '46': 64, '47': 240, '48': 0, '49': 0}"
+          },
+          {
+            "rule": "REG_CLK_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16-21",
+            "detail": "library={'16': 12} spec={'16': 12}"
+          },
+          {
+            "rule": "OUTPUT_ENABLED_AFTER_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 3 CLKx_OEB (0 = enabled)",
+            "detail": "reg3=0xFE"
+          },
+          {
+            "rule": "MS_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=199488 P2=0 P3=1000000"
+          },
+          {
+            "rule": "MS_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "MS_RATIO_VALID",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72.1.1 item 1 / \u00a74.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+            "detail": "MS ratio=1562.500000000"
+          },
+          {
+            "rule": "MS_OUT_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (MS output 500 kHz - 200 MHz)",
+            "detail": "f_MS=512000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 7 FCLK 2.5 kHz - 200 MHz",
+            "detail": "requested=4000.000 Hz"
+          },
+          {
+            "rule": "OUT_FREQ_ACCURACY",
+            "ok": true,
+            "severity": "error",
+            "cite": "programmed registers must realize requested freq (tol 1000 ppb)",
+            "detail": "realized=4000.000000 Hz err=0.000 ppb"
+          }
+        ]
+      }
+    },
+    {
+      "id": "M-clk7-pllb-assignment",
+      "priority": "M",
+      "api": "reset_pll_assignment",
+      "covers": [
+        "CLK7 \u2192 PLLB after reset",
+        "reg 23 MS7_SRC bit5",
+        "mutation: CLK7\u2192PLLA"
+      ],
+      "clk": 7,
+      "pll_assignment": "PLLB",
+      "pll_assignment_table": {
+        "0": "PLLA",
+        "1": "PLLA",
+        "2": "PLLA",
+        "3": "PLLA",
+        "4": "PLLA",
+        "5": "PLLA",
+        "6": "PLLB",
+        "7": "PLLB"
+      },
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_write": {
+        "reg": 23,
+        "value": 44
+      },
+      "mutation_fail_if": {
+        "clk7_ctrl_equals": 12,
+        "pll_assignment_7": "PLLA"
+      },
+      "spec_note": "AN619 \u00a74.1.1 / Reg 23 MS7_SRC: 0=PLLA, 1=PLLB/VCXO \u2014 either legal when no spread-spectrum/VCXO constraint. Library reset() chooses PLLB for CLK7; that choice is the regression lock. Spec agrees the bit encoding; does not mandate PLLB.",
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLK5_RESET_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk5 \u2192 PLLA (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[5]=PLLA"
+          },
+          {
+            "rule": "CLK7_RESET_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk7 \u2192 PLLB (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[7]=PLLB"
+          },
+          {
+            "rule": "REG_CLK_CTRL_0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 17 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_2",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 18 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 19 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 20 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_CLK_CTRL_7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_FOCUS_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "PLL_ASSIGN_SPEC_PERMITS_EITHER",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.1",
+            "detail": "AN619 \u00a74.1.1 / Reg 23 MS7_SRC: 0=PLLA, 1=PLLB/VCXO \u2014 either legal when no spread-spectrum/VCXO constraint. Library reset() chooses PLLB for CLK7; that choice is the regression lock. Spec agrees the bit encoding; does not mandate PLLB."
+          },
+          {
+            "rule": "MUTATION_CLK7_NOT_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "mutation detector (Coding PM)",
+            "detail": "locked reg23=0x2C assignment=PLLB"
+          }
+        ]
+      }
+    },
+    {
+      "api": "set_ms_rmw",
+      "clk_path": null,
+      "input_freq_lib": 500000,
+      "input_freq_hz": 5000.0,
+      "pll_assignment": "PLLA",
+      "xtal_hz": 25000000,
+      "correction_ppb": 0,
+      "branch": "use_existing_pll_le_100mhz",
+      "r_div": 7,
+      "r_div_name": "DIV_128",
+      "freq_after_r_div_lib": 64000000,
+      "div_by_4": 0,
+      "int_mode": 0,
+      "ms_a": 1250,
+      "ms_b": 0,
+      "ms_c": 1,
+      "ms_p1": 159488,
+      "ms_p2": 0,
+      "ms_p3": 1,
+      "pll_freq_lib": 80000000000,
+      "pll_freq_hz": 800000000.0,
+      "pll_a": 32,
+      "pll_b": 0,
+      "pll_c": 1,
+      "pll_p1": 3584,
+      "pll_p2": 0,
+      "pll_p3": 1,
+      "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+      "ms_packed_bytes": [
+        0,
+        1,
+        2,
+        111,
+        0,
+        0,
+        0,
+        0
+      ],
+      "ms_div_byte": 114,
+      "pll_reset": false,
+      "id": "M-set-ms-byte2-rmw",
+      "priority": "M",
+      "covers": [
+        "set_ms byte+2 RMW",
+        "ms_div byte+2 RMW",
+        "bit7 preserve",
+        "P1[17:16] preserve"
+      ],
+      "clk": 0,
+      "prior_byte2": 255,
+      "lib_ms_regs": {
+        "42": 0,
+        "43": 1,
+        "44": 242,
+        "45": 111,
+        "46": 0,
+        "47": 0,
+        "48": 0,
+        "49": 0
+      },
+      "lib_clk_ctrl": {
+        "16": 12
+      },
+      "lib_reg3_after": 254,
+      "rmw_transcript": {
+        "reg": 44,
+        "prior": 255,
+        "steps": [
+          {
+            "op": "si5351_read",
+            "reg": 44,
+            "returns": 255,
+            "note": "set_ms RMW start"
+          },
+          {
+            "op": "si5351_write_bulk_byte2",
+            "reg": 44,
+            "value": 254,
+            "mask_cleared": 3,
+            "bits_preserved": "7:2",
+            "note": "set_ms: reg_val &= ~0x03; |= P1[17:16]"
+          },
+          {
+            "op": "si5351_read",
+            "reg": 44,
+            "returns": 254,
+            "note": "ms_div RMW start"
+          },
+          {
+            "op": "si5351_write",
+            "reg": 44,
+            "value": 242,
+            "mask_cleared": 124,
+            "bits_preserved": "7 and 1:0",
+            "note": "ms_div: reg_val &= ~0x7C; |= R_DIV<<4 | DIVBY4"
+          }
+        ],
+        "final": 242,
+        "mutation_detectors": {
+          "naive_ms_div_overwrite": 112,
+          "naive_set_ms_then_correct_ms_div": 114,
+          "note": "naive_ms_div_overwrite loses P1[17:16] and bit7; naive_set_ms_then_correct_ms_div loses bit7 (and any prior R_DIV/DIVBY4 mid-bulk)"
+        }
+      },
+      "wire_stub_must_assert": "Future Wire stub: (1) set_ms bulk byte at reg 44 must equal (prior & ~0x03) | P1[17:16] \u2014 bits 7:2 survive; (2) ms_div write at reg 44 must equal that value with bits 6:2 replaced by R_DIV/DIVBY4 \u2014 bits 7 and 1:0 survive. Final byte MUST be 0xF2 for this case, NOT 0x70 or 0x72.",
+      "lib_pll_regs": {
+        "26": 0,
+        "27": 1,
+        "28": 0,
+        "29": 14,
+        "30": 0,
+        "31": 0,
+        "32": 0,
+        "33": 0
+      },
+      "spec": {
+        "spec_ms_regs": {
+          "42": 0,
+          "43": 1,
+          "44": 114,
+          "45": 111,
+          "46": 0,
+          "47": 0,
+          "48": 0,
+          "49": 0
+        },
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "FB_INT_ADVISORY"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_B0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=1 spec=1"
+          },
+          {
+            "rule": "REG_MS_B3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=111 spec=111"
+          },
+          {
+            "rule": "REG_MS_B4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_B7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 MS0 parameter block",
+            "detail": "library=0 spec=0"
+          },
+          {
+            "rule": "REG_MS_BYTE2_LOW7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 44 bits 6:0 (R_DIV|DIVBY4|P1[17:16])",
+            "detail": "library=0xF2 spec_low7=0x72"
+          },
+          {
+            "rule": "RMW_BIT7_PRESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library set_ms/ms_div RMW preserves unused bit7 (AN619 Reg 44 bit7 Unused)",
+            "detail": "prior=0xFF final=0xF2"
+          },
+          {
+            "rule": "MUTATION_NOT_NAIVE_MS_DIV",
+            "ok": true,
+            "severity": "error",
+            "cite": "Coding PM mutation: naive ms_div overwrite",
+            "detail": "final=0xF2 naive=0x70"
+          },
+          {
+            "rule": "MUTATION_NOT_NAIVE_SET_MS",
+            "ok": true,
+            "severity": "error",
+            "cite": "Coding PM mutation: naive set_ms (no RMW) then correct ms_div",
+            "detail": "final=0xF2 naive=0x72"
+          },
+          {
+            "rule": "RMW_TRANSCRIPT_FINAL",
+            "ok": true,
+            "severity": "error",
+            "cite": "set_ms+ms_div RMW transcript",
+            "detail": "library=242 spec=242"
+          },
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3584, 0, 1] spec=[3584, 0, 1]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0} spec={'26': 0, '27': 1, '28': 0, '29': 14, '30': 0, '31': 0, '32': 0, '33': 0}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3584 P2=0 P3=1"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=32.000000000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=800000000.000 Hz"
+          },
+          {
+            "rule": "FB_INT_ADVISORY",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a73.2.1 / Reg 22-23 bit6 FBx_INT",
+            "detail": "feedback ratio 32 is an even integer; FBx_INT=1 'in most cases ... improve jitter' (optional; library never sets FBx_INT)"
+          }
+        ]
+      }
+    },
+    {
+      "id": "M-clk5-reset-plla",
+      "priority": "M",
+      "api": "reset_pll_assignment",
+      "covers": [
+        "CLK5 \u2192 PLLA after reset",
+        "reg 21 MS5_SRC bit5",
+        "mutation: CLK5\u2192PLLB"
+      ],
+      "clk": 5,
+      "pll_assignment": "PLLA",
+      "pll_assignment_table": {
+        "0": "PLLA",
+        "1": "PLLA",
+        "2": "PLLA",
+        "3": "PLLA",
+        "4": "PLLA",
+        "5": "PLLA",
+        "6": "PLLB",
+        "7": "PLLB"
+      },
+      "lib_clk_ctrl": {
+        "16": 12,
+        "17": 12,
+        "18": 12,
+        "19": 12,
+        "20": 12,
+        "21": 12,
+        "22": 44,
+        "23": 44
+      },
+      "lib_write": {
+        "reg": 21,
+        "value": 12
+      },
+      "mutation_fail_if": {
+        "clk5_ctrl_equals": 44,
+        "pll_assignment_5": "PLLB"
+      },
+      "spec_note": "AN619 \u00a74.1.1 / Reg 21 MS5_SRC: 0=PLLA, 1=PLLB. Library reset() chooses PLLA for CLK0\u20135; that choice is the regression lock.",
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLK5_RESET_PLLA",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk5 \u2192 PLLA (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[5]=PLLA"
+          },
+          {
+            "rule": "CLK7_RESET_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "Library reset() clk7 \u2192 PLLB (AN619 \u00a74.1.1 allows either)",
+            "detail": "pll_assignment[7]=PLLB"
+          },
+          {
+            "rule": "REG_CLK_CTRL_0",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_1",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 17 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_2",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 18 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_3",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 19 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_4",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 20 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_5",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21 MSx_SRC",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "REG_CLK_CTRL_6",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 22 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_CLK_CTRL_7",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 23 MSx_SRC",
+            "detail": "library=44 spec=44"
+          },
+          {
+            "rule": "REG_FOCUS_CTRL",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 21",
+            "detail": "library=12 spec=12"
+          },
+          {
+            "rule": "PLL_ASSIGN_SPEC_PERMITS_EITHER",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.1",
+            "detail": "AN619 \u00a74.1.1 / Reg 21 MS5_SRC: 0=PLLA, 1=PLLB. Library reset() chooses PLLA for CLK0\u20135; that choice is the regression lock."
+          },
+          {
+            "rule": "MUTATION_CLK5_NOT_PLLB",
+            "ok": true,
+            "severity": "error",
+            "cite": "mutation detector (Coding PM)",
+            "detail": "locked reg21=0x0C assignment=PLLA"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_phase-clk1-0x2A",
+      "priority": "A",
+      "api": "set_phase",
+      "covers": [
+        "set_phase",
+        "reg 166"
+      ],
+      "clk": 1,
+      "requested_phase": 42,
+      "lib_write": {
+        "reg": 166,
+        "value": 42
+      },
+      "sequence": [
+        "reset()",
+        "set_phase(SI5351_CLK1, 0x2A)"
+      ],
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [
+          "PHOFF_PRECONDITION"
+        ],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "PHOFF_ADDR",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a76, Reg 165-170 (CLK0-5 only; 171-176 Reserved)",
+            "detail": "library writes reg 166"
+          },
+          {
+            "rule": "PHOFF_BIT7_ZERO",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170 bit 7 'Only write 0'",
+            "detail": "value=0x2A"
+          },
+          {
+            "rule": "REG_PHOFF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 165-170",
+            "detail": "library=[166, 42] spec=[166, 42]"
+          },
+          {
+            "rule": "PHOFF_PRECONDITION",
+            "ok": false,
+            "severity": "advisory",
+            "cite": "AN619 \u00a76 / \u00a74.1.2.1",
+            "detail": "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-init-crystal-load-8pF",
+      "priority": "A",
+      "api": "init_xtal_load",
+      "covers": [
+        "init xtal load",
+        "reg 183"
+      ],
+      "lib_writes": {
+        "8pF": 146
+      },
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 0, 0)"
+      ],
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_183_8pF",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (bits 5:0 = 010010b)",
+            "detail": "library=146 spec=146"
+          },
+          {
+            "rule": "XTAL_CL_RESERVED",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 183 (XTAL_CL=00 reserved)",
+            "detail": "8pF: reg183=0x92"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_int-clk0-ms-int",
+      "priority": "A",
+      "api": "set_int",
+      "covers": [
+        "set_int CLK0",
+        "reg 16 bit6 = MS0_INT"
+      ],
+      "clk": 0,
+      "sequence": [
+        "reset()",
+        "set_int(SI5351_CLK0, 1)"
+      ],
+      "lib_write": {
+        "reg": 16,
+        "value": 76
+      },
+      "ms_int_target": true,
+      "plla": null,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 bit6 = MSx_INT",
+            "detail": "library=76 spec=76"
+          },
+          {
+            "rule": "MS_INT_BIT_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2.1 / Reg 16-21 bit6",
+            "detail": "reg16=0x4C"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_pll_input-clkin-div4-clean",
+      "priority": "A",
+      "api": "set_pll_input",
+      "covers": [
+        "set_pll_input",
+        "set_ref_freq",
+        "reg 15"
+      ],
+      "sequence": [
+        "reset()",
+        "set_ref_freq(80000000, SI5351_PLL_INPUT_CLKIN)",
+        "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"
+      ],
+      "prior_reg15": 0,
+      "intended_clkin_div": 4,
+      "lib_write": {
+        "reg": 15,
+        "value": 132
+      },
+      "spec": {
+        "register_agreement": null,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "CLKIN_DIV_FIELD",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 15 CLKIN_DIV[1:0]",
+            "detail": "reg15=0x84 -> CLKIN_DIV=10b (/4); intended /4"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-ref27MHz-set_pll-fixed",
+      "priority": "A",
+      "api": "set_pll",
+      "covers": [
+        "set_ref_freq 27 MHz",
+        "set_pll",
+        "in-spec XTAL"
+      ],
+      "sequence": [
+        "init(SI5351_CRYSTAL_LOAD_8PF, 27000000, 0)",
+        "reset() \u2192 set_pll(SI5351_PLL_FIXED)"
+      ],
+      "pll_freq_lib": 80000000000,
+      "xtal_hz": 27000000,
+      "correction_ppb": 0,
+      "pll_assignment": "PLLA",
+      "pll_a": 29,
+      "pll_b": 629629,
+      "pll_c": 1000000,
+      "pll_p1": 3280,
+      "pll_p2": 592512,
+      "pll_p3": 1000000,
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 12,
+        "30": 208,
+        "31": 249,
+        "32": 10,
+        "33": 128
+      },
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "FB_ENCODING",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 P1/P2/P3 equations",
+            "detail": "library=[3280, 592512, 1000000] spec=[3280, 592512, 1000000]"
+          },
+          {
+            "rule": "REG_PLL_BLOCK",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a78.1 / Reg 26-33 (MSNA), 34-41 (MSNB)",
+            "detail": "library={'26': 66, '27': 64, '28': 0, '29': 12, '30': 208, '31': 249, '32': 10, '33': 128} spec={'26': 66, '27': 64, '28': 0, '29': 12, '30': 208, '31': 249, '32': 10, '33': 128}"
+          },
+          {
+            "rule": "FB_P_WIDTH",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 P1[17:0], P2[19:0], P3[19:0]",
+            "detail": "P1=3280 P2=592512 P3=1000000"
+          },
+          {
+            "rule": "FB_C_MAX",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2/\u00a74.1.2 (c <= 1,048,575)",
+            "detail": "c=P3=1000000"
+          },
+          {
+            "rule": "FB_RATIO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a73.2 (15 .. 90)",
+            "detail": "a+b/c=29.629629000"
+          },
+          {
+            "rule": "VCO_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a72 (600-900 MHz)",
+            "detail": "fVCO=799999983.000 Hz"
+          },
+          {
+            "rule": "REF_RANGE",
+            "ok": true,
+            "severity": "error",
+            "cite": "DS Table 6/8 XTAL 25-27 MHz; AN619 \u00a73.1.2 PLL input 10-40 MHz",
+            "detail": "ref=27000000 Hz"
+          }
+        ]
+      }
+    },
+    {
+      "id": "A-set_correction-then-set_int-clk0",
+      "priority": "A",
+      "api": "set_int",
+      "covers": [
+        "set_correction",
+        "set_int CLK0"
+      ],
+      "clk": 0,
+      "sequence": [
+        "reset()",
+        "set_correction(100000, SI5351_PLL_INPUT_XO)",
+        "set_int(SI5351_CLK0, 1)"
+      ],
+      "lib_write": {
+        "reg": 16,
+        "value": 76
+      },
+      "ms_int_target": true,
+      "plla": {
+        "a": 31,
+        "b": 996800,
+        "c": 1000000,
+        "p1": 3583,
+        "p2": 590400,
+        "p3": 1000000
+      },
+      "lib_pll_regs": {
+        "26": 66,
+        "27": 64,
+        "28": 0,
+        "29": 13,
+        "30": 255,
+        "31": 249,
+        "32": 2,
+        "33": 64
+      },
+      "pll_a": 31,
+      "pll_b": 996800,
+      "pll_c": 1000000,
+      "pll_p1": 3583,
+      "pll_p2": 590400,
+      "pll_p3": 1000000,
+      "xtal_hz": 25000000,
+      "correction_ppb": 100000,
+      "spec": {
+        "register_agreement": true,
+        "failed_rules": [],
+        "advisories": [],
+        "status": "agree",
+        "known_deviations": [],
+        "checks": [
+          {
+            "rule": "REG_MS_INT",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 Reg 16 bit6 = MSx_INT",
+            "detail": "library=76 spec=76"
+          },
+          {
+            "rule": "MS_INT_BIT_SET",
+            "ok": true,
+            "severity": "error",
+            "cite": "AN619 \u00a74.1.2.1 / Reg 16-21 bit6",
+            "detail": "reg16=0x4C"
+          }
+        ]
+      }
+    }
+  ]
+}
\ No newline at end of file
diff --git a/tests/regression/python/ref/AN619.txt b/tests/regression/python/ref/AN619.txt
new file mode 100644
index 0000000..22d8d0e
--- /dev/null
+++ b/tests/regression/python/ref/AN619.txt
@@ -0,0 +1,3293 @@
+                                                                                                               AN619
+Manually Generating an Si5351 Register Map for 10-MSOP and
+20-QFN Devices
+
+
+1. Introduction
+The Si5351 is a highly flexible and configurable clock generator and VCXO. A block diagram of the Si5351
+programmable clock IC is shown in Figure 1. To support this flexibility, Skyworks Solutions has created
+ClockBuilder Pro to create register maps automatically and easily for a given configuration. Since programming
+with ClockBuilder Pro may not always be well suited for every system’s requirements, this document presents the
+procedures and equations for determining a complete register set from a frequency plan for any 10-MSOP or 20-
+QFN Si5351 device. Section 2 highlights the overall frequency plan algorithm, and sections 3 and beyond detail all
+the necessary register calculations.
+
+
+
+
+                                    Figure 1. Generalized Si5351 Block Diagram
+Figure 1 is a generalized block diagram of the Si5351. The Si5351 is available in three variants:
+  Si5351A—XTAL only device.
+  Si5351B—XTAL + VCXO.
+  Si5351C—XTAL + CLKIN.
+If spread spectrum is turned on, it is supported by PLLA.
+VCXO functionality (Si5351B devices only) is supported by PLLB.
+The Si5351 can also come in three package types: 10-MSOP, 20-QFN, and 16-QFN. This document only covers
+the programming of 10-MSOP and 20-QFN devices. For more information on programming a 16-QFN device, see
+AN1234.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+2. Conceptualizing a Frequency Plan
+The device consists of two PLLs—PLLA and PLLB. Each PLL generates an intermediate VCO frequency in the
+range of 600 to 900 MHz using a Feedback Multisynth. These VCO frequencies can then be divided down by
+individual output Multisynth dividers to generate any frequency between 500 kHz and 200 MHz. Additionally, the R
+dividers can be used to generate any output frequency down to 2.5 kHz. The relationship between the VCO and
+output frequencies is given below.
+                                                                                       fvco
+                                                 fout x = ---------------------------------------------------------------------
+                                                          Output_Multisynth x  R x
+
+
+                                                fvco = fin  Feedback_Multisynth
+
+Use the steps in the sections below to draw out a conceptual frequency plan map.
+
+2.1. PLL Selection
+If spread spectrum is not enabled, either of the two PLLs may be used as the source for any outputs of the
+Si5351A. If both XTAL and CLKIN input options are used simultaneously (Si5351C only), then one PLL must be
+reserved for use with CLKIN and one for use with the XTAL.
+Note: PLLA must be used for any spread spectrum-enabled outputs. PLLB must be used for any VCXO outputs.
+2.1.1. Selecting the Proper VCO Frequencies and Divide Ratios
+The general criteria below may be used to set the VCO frequencies. This is a general model, and individual
+applications may require some modification.
+     1. Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 2048. This
+        means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one of the
+        VCO frequencies.
+     2. For the frequencies where jitter is a concern make the output Multisynth divide ratio an integer. If possible,
+        make both output and feedback Multisynth ratios integers.
+     3. Once criteria 1 and 2 are satisfied, try to select as many integer output Multisynth ratios as possible.
+
+2.2. Output Clock Pin Assignment (Optional)
+Some customers may wish to have full control of output clock pin assignment. The guidelines below may be used
+to assign clocks to pins on the device.
+     1. Equal output frequencies should share a VDDO bank (e.g., CLK0&1, CLK2&3, etc.) whenever possible in
+        order to ensure minimal jitter due to PCB crosstalk.
+     2. Isolate unique output frequencies on individual VDDO bank if possible. For example, if the four outputs are
+        25 MHz, 25 MHz, 27 MHz, and 74.25 MHz, then place them on CLK0, CLK1, CLK2, and CLK4,
+        respectively.
+     3. Otherwise, use all necessary CLK channels based on the required frequency plan.
+Note: The only valid divide ratios for CLK6 and CLK7 Multisynth dividers are even integers between 6 and 254 inclusive. This
+      may limit the two VCO frequencies if all 8 output clocks are used.
+
+
+
+
+2         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+3. Configuring Input and PLL Register Parameters (Synthesis Stage 1)
+This section describes register parameters related to the input reference and the two PLLs.
+
+3.1. PLL Input Source
+The input source for each PLL must be selected. For the Si5351A and Si5351B devices, the only possible source
+is the XTAL, but for the Si5351C device, each PLL can be synchronized to either an XTAL or a CMOS clock on the
+CLKIN pin.
+3.1.1. XTAL Source
+If the source for the PLL is a crystal, PLLx_SRC must be set to 0 in register 15. XTAL_CL[1:0] must also be set to
+match the crystal load capacitance (see register 183).
+3.1.2. CMOS Clock Source
+If a PLL needs to be synchronized to a CMOS clock, PLLx_SRC must be 1. The input frequency range of the PLL
+is 10 to 40 MHz. If CLKIN is > 40 MHz, the CLKIN input divider must be used to bring the PLL input within the 10–
+40 MHz range. See CLKIN_DIV[1:0], register 15, bits [7:6].
+
+3.2. Feedback Multisynth Divider Equations
+Once the input source for each PLL and (if necessary) CLKIN_DIV are determined, the two VCO frequencies
+selected in Section 2 above can be generated using the following equations. Each feedback divider essentially
+multiplies the source frequency such that
+
+
+                                                         f VCO = f XTAL   a + b
+                                                                                 -- 
+                                                                                 c
+                            and/or
+
+                                                                   f CLKIN                            b
+                                                   f VCO = ---------------------------------   a + -- 
+                                                           CLKIN_DIV                                  c
+The fractional ratio
+                                                                          a+b
+                                                                            --
+                                                                            c
+has a valid range of 15 + 0/1,048,575 and 90 and is represented in the Si5351 register space using the equations
+below.
+                                                                                   b
+                                       MSNx_P1  17:0  = 128  a + Floor  128  --  – 512
+                                                                                   c
+
+
+                                                                                       b
+                                        MSNx_P2  19:0  = 128  b – c  Floor  128  -- 
+                                                                                      c
+
+
+
+                                                          MSNx_P3  19:0  = c
+
+
+In the equations above, x is used to represent MSNA and MSNB, the PLLA and PLLB Multisynth dividers
+respectively. The equations above must be repeated for Multisynths MSNA and MSNB. As mentioned earlier in
+Section “2.1. PLL Selection”, spread spectrum is only supported by PLLA, and the VCXO functionality is only
+supported by PLLB. When using the VCXO function, set the MSNB divide ratio a + b/c such that c = 106. This must
+be taken into consideration when configuring a frequency plan.
+3.2.1. Integer Divide Values (FBx_INT)
+If a + b/c is an even integer, integer mode may be enabled for PLLA or PLLB by setting parameter FBA_INT or
+FBB_INT respectively. In most cases setting this bit will improve jitter when using even integer divide values.
+Whenever spread spectrum is enabled, FBA_INT must be set to 0.
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             3
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+4. Configuring the Output Register Parameters
+This section covers the Multisynth and output driver settings necessary for each output. As shown in Figure 2, one
+of the two VCO frequencies is divided down by each Multisynth divider. This is followed by an output driver state.
+See “4.2. Output Driver Settings”.
+
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                   ÷R0            CLK0
+                                                      VCOA
+                                                                       Multisynth0         M0
+                                                      VCOB               ÷M0
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                   ÷R1            CLK1
+                                                                                           M0
+                                                      VCOA
+                                                                       Multisynth1         M1
+                                                      VCOB               ÷M1
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                                  CLK2
+                                                                                           M0      ÷R2
+                                                      VCOA
+                                                                       Multisynth2         M2
+                                                      VCOB               ÷M2
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                   ÷R3            CLK3
+                   XO                                                                      M0
+                                    PLLA      VCOA
+                   CLKIN             NA                                Multisynth3         M3
+                                                      VCOB               ÷M3
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                                  CLK4
+                                                                                                   ÷R4
+                                                      VCOA
+                   XO                                                  Multisynth4         M4
+                                    PLLB      VCOB                       ÷M4
+                   CLKIN             NB
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                                  CLK5
+                                                                                           M4      ÷R5
+                                                      VCOA
+                                                                       Multisynth5         M5
+                                                      VCOB               ÷M5
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                   ÷R6            CLK6
+                                                                                           M4
+                                                      VCOA
+                                                                       Multisynth6         M6
+                                                      VCOB               ÷M6*
+
+                                                                                          XO
+                                                                                          CLKIN
+                                                                                                                  CLK7
+                                                                                           M4      ÷R7
+                                                      VCOA
+                                                                       Multisynth7         M7
+                                                      VCOB               ÷M7*
+
+                  * Multisynth 6 and 7 divide ratios can only be even integers between6 and 254.
+
+
+                           Figure 2. Detailed Dividers and Output Drivers Block Diagram
+
+
+4         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+4.1. Output Multisynth Settings (Synthesis Stage 2)
+This section describes the settings related to the individual Multisynths. The Si5351 consists of six fractional
+Multisynth divides (MS0-MS5) and two even-integer dividers (MS6 and MS7).
+4.1.1. Output Multisynth Source (MSx_SRC)
+Each of these dividers can be set to use PLLA or PLLB as its reference by setting MSx_SRC to 0 or 1 respectively.
+See bit 5 description of registers 16-23.
+4.1.2. Output Multisynth Divider Equations (Fout <= 150 MHz)
+Once the PLL source for the output Multisynth is selected, the divide ratio can be set using the equations below.
+Divider represented as fractional number,
+                                                                 a+b
+                                                                   --
+                                                                   c
+between 8 + 1/1,048,575 and 2048.
+                                                                                   b
+                                        MSx_P1  17:0  = 128  a + Floor  128  --  – 512
+                                                                                   c
+
+                                                                                       b
+                                         MSx_P2  19:0  = 128  b – c  Floor  128  -- 
+                                                                                      c
+
+
+                                                        MSx_P3  19:0  = c
+In the equations above, x=0, 1, ...5. As previously noted, MS6 and MS7 are integer-only dividers. The valid range
+of values for these dividers is all even integers between 6 and 254 inclusive. For MS6 and MS7, set MSx_P1
+directly (e.g., MSx_P1=divide value).
+4.1.2.1. Integer Divide Values(MSx_INT)
+If any of the MS0-MS5 is an even integer, Multisynth integer mode may be enabled by setting MSx_INT=1 (see
+registers 16-21, bit 6). In most cases setting this bit will improve jitter when using even integer divide values.
+Multisynths 6 and 7 inherently operate in integer mode, and so there is no register to turn integer mode on or off.
+However, it's important to note that Multisynth integer mode cannot be used when adding phase offsets in NVM. In
+other words, MSx_INT needs to be set to 0 if phase offsets need to be enabled.
+4.1.3. Output Multisynth Divider Equations (150 MHz <Fout<=200 MHz)
+Output frequencies greater than 150 MHz are available on Multisynths 0-5. For this frequency range a divide value
+of 4 must be used by setting
+  MSx_P1=0,
+  MSx_P2=0,
+  MSx_P3=1,
+  MSx_INT=1, and
+  MSx_DIVBY4[1:0]=11b.
+Set the appropriate feedback Multisynth to generate fVCO=Fout*4.
+
+4.2. Output Driver Settings
+Once the Multisynth registers are assembled, the output driver settings can be modified according to the
+information in this section.
+4.2.1. Clock Source (CLKx_SRC)
+Generally, Multisynth x should be output on CLKx, however XO, CLKIN, or a divided version of either (see section
+4.2.2 on R dividers) may also be output on each of the CLKx pins. Additionally, MS0 (or a divided version of MS0)
+may be output on CLK0-CLK3, and MS4 (or a divided version of MS4) may be output on CLK4-CLK7. See
+CLKx_SRC description for details.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             5
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+4.2.2. R Dividers
+The R dividers can be used to generate frequencies below about 500 kHz. Each individual output R divider can be
+set to 1, 2, 4, 8,....128 by writing the proper setting for Rx_DIV. Set this parameter to generate frequencies down to
+8kHz.
+4.2.3. (CLKx_INV)
+In some cases, the user may need to invert the polarity (i.e., 180° phase offset) of one or more outputs with respect
+to the other outputs. This is achieved by setting CLKx_INV=1.
+4.2.4. (CLKx_DIS_STATE)
+When a clock is disabled via the OEB pin or OEB control register (reg 3), the output driver may be set to present a
+logic low, logic high, or high-impedance at the device pin. See CLKx_DIS_STATE description for details.
+4.2.5. Unused Clock Outputs
+Any unused clock outputs may be powered down to reduce IDDO current consumption. Set CLKx_PDN=1 to
+power down unused clock output drivers.
+In the case of the 3-output 10-MSOP Si5351, only CLK0, 1, and 2 are used. The remaining clock outputs should be
+powered down to conserve power. This will be done automatically for any project created in ClockBuilder Pro.
+However, this will need to be done manually when programming a blank Si5351A-B-GT completely by hand,
+without the use of ClockBuilder Pro.
+
+
+
+
+6         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                                     AN619
+5. Configuring Spread Spectrum Register Parameters
+Spread spectrum can be enabled on any Multisynth output that uses PLLA as its reference. Valid ranges for spread
+spectrum include –0.1% to –2.5% down spread and up to ± 1.5% center spread. This spread modulation rate is
+fixed at approximately 31.5 kHz.
+The following parameters must be known to properly set up spread spectrum:
+  fPFD(A) input frequency to PLLA in Hz (determined in Sec 2 above and referred to in “3.1.2. CMOS Clock
+     Source”). This is also listed in the ClockBuilder Pro generated register map file as “#PFD(MHz)=...”
+  a + b/c PLLA Multisynth ratio (determined in Sec 2 above).
+  sscAMPSpread amplitude (e.g., for down or center spread amplitude of 1%, sscAmp = 0.01).
+Use the equations below to set up the desired spread spectrum profile.
+Note: Make sure MSNA is set up in fractional mode when using the spread spectrum feature. See parameter FBA_INT in reg-
+      ister 22.
+
+5.1. Down Spread
+For down spread, four spread spectrum parameters need to be written: SSUDP[11:0], SSDN_P1[11:0],
+SSDN_P2[14:0], and SSDN_P3[14:0].
+Up/Down Parameter:
+                                                                                      f PFD
+                                                   SSUDP  11:0  = Floor  ---------------------------- 
+                                                                             4  31 500
+Intermediate Equation (no register writes):
+
+
+                                                                                      sscAmp
+                                        SSDN = 64   a + b
+                                                          --   -----------------------------------------------------------------
+                                                         c  1 + sscAmp   SSUDP
+
+Down-Spread Parameters:
+                                                     SSDN_P1  11:0  = Floor  SSDN 
+
+
+                                       SSDN_P2  14:0  = 32 767   SSDN – SSDN_P1 
+
+
+                                                SSDN_P3  14:0  = 32 767 = 0x7FFF
+Up-Spread Parameters:
+                                                                      SSUP_P1 = 0
+
+
+                                                                      SSUP_P2 = 0
+
+
+                                                                      SSUP_P3 = 1
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             7
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+5.2. Center Spread
+For center spread, seven spread spectrum parameters need to be written: SSUDP[11:0], SSDN_P1[11:0],
+SSDN_P2[14:0], SSDN_P3[14:0], SSUP_P1[11:0], SSUP_P2[14:0], and SSUP_P3[14:0].
+Up/Down Parameter:
+                                                                                       f PFD
+                                                     SSUDP  11:0  = Floor  ---------------------------- 
+                                                                             4  31 500
+
+Intermediate Equations (no register writes):
+                                                                                        sscAmp
+                                         SSUP = 128   a + b
+                                                            --   -----------------------------------------------------------------
+                                                           c  1 – sscAmp   SSUDP
+
+
+                                                                                          sscAmp
+                                         SSDN = 128   a + b
+                                                             --   -----------------------------------------------------------------
+                                                             c        1 + sscAmp   SSUDP
+Up-Spread Parameters:
+                                                       SSUP_P1  11:0  = Floor  SSUP 
+
+
+                                        SSUP_P2  14:0  = 32 767   SSUP – SSUP_P1 
+
+
+                                                  SSUP_P3  14:0  = 32 767 = 0x7FFF
+Down-Spread Parameters:
+                                                       SSDN_P1  11:0  = Floor  SSDN 
+
+
+                                        SSDN_P2  14:0  = 32 767   SSDN – SSDN_P1 
+
+
+                                                   SSDN_P3  14:0  = 32767 = 0x7FFF
+
+5.3. Spread Spectrum Enable Pin (SSEN)
+The Spread Spectrum Enable control pin is available on the Si5351A and B devices. Spread spectrum enable
+functionality is a logical OR of the SSEN pin and SSC_EN register bit, so for the SSEN pin to work properly, the
+SSC_EN register bit must be set to 0.
+
+
+
+
+8         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+6. Configuring Initial Phase Offset Register Parameters
+Outputs 0-5 of the Si5351 can be programmed with an independent initial phase offset. The phase offset only
+works when MS0-5 are set as fractional dividers (divider values greater than 8). The phase offset parameter is an
+unsigned integer where each LSB represents a phase difference of a quarter of the VCO period, TVCO/4. Use the
+equation below to determine the register value. Also, remember that any divider using the phase offset feature
+needs the MSx_INT bit set to 0.
+
+
+                                CLKx_PHOFF  4:0  = Round  DesiredOffset  sec   4  F VCO 
+
+
+7. Configuring VCXO Parameters (Si5351 B only)
+The Si5351B combines free-running clock generation and a VCXO in a single package. The VCXO architecture of
+the Si5350B eliminates the need for an external pullable crystal. The “pulling” is done at PLLB. Only a standard,
+low cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required and is used as the reference source for both
+PLLA and PLLB.
+PLLB must be used as the source for any VCXO output clock. Feedback B Multisynth divider ratio must be set
+such that the denominator, c, in the fractional divider a + b/c is fixed to 106. Set VCXO_Param register value
+according to the equation below. Note that 1.03 is a margining factor to ensure the full desired pull range is
+achieved. For a desired pull-range of +/– 30 ppm, the value APR in the equation below is 30, for +/– 60 ppm APR
+is 60, and so on.
+
+                                                                           b  APR
+                                       VCXO_Param[21:0] = 1.03  128a + --------
+                                                                               6
+                                                                        10
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             9
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+8. Si5351 Registers
+This section describes the registers and their usage in detail. These values are easily configured using
+ClockBuilder Pro.
+
+8.1. Register Map Summary
+The following is a summary of the register map used to read status, control, and configure the Si5351.
+
+Register         7                 6                5               4                 3                     2                    1                    0
+   0         SYS_INIT          LOL_B           LOL_A          LOS_CLKIN         LOS_XTAL              Reserved                         REVID[1:0]
+   1         SYS_INIT_        LOL_B_           LOL_A_         LOS_CLKIN_       LOS_XTAL_                                   Reserved
+               STKY            STKY             STKY             STKY            STKY
+   2         SYS_INIT_        LOL_B_          LOL_A _         LOS_CLKIN-       LOS_XTAL_                                   Reserved
+               MASK            MASK            MASK             MASK             MASK
+   3         CLK7_OEB        CLK6_OEB        CLK5_OEB         CLK4_OEB          CLK3_OEB             CLK2_OEB             CLK1_OEB             CLK0_OEB
+  4–8                                                                      Reserved
+   9        OEB_MASK7       OEB_MASK6       OEB_MASK5         OEB_MASK4        OEB_MASK3            OEB_MASK2            OEB_MASK1            OEB_MASK0
+ 10–14                                                                     Reserved
+  15              CLKIN_DIV[1:0]                        Reserved                PLLB_SRC             PLLA_SRC                           Reserved
+  16         CLK0_PDN         MS0_INT         MS0_SRC          CLK0_INV                   CLK0_SRC[1:0]                              CLK0_IDRV[1:0]
+  17         CLK1_PDN         MS1_INT         MS1_SRC          CLK1_INV                   CLK1_SRC[1:0]                              CLK1_IDRV[1:0]
+  18         CLK2_PDN         MS2_INT         MS2_SRC          CLK2_INV                   CLK2_SRC[1:0]                              CLK2_IDRV[1:0]
+  19         CLK3_PDN         MS3_INT         MS3_SRC          CLK3_INV                   CLK3_SRC[1:0]                              CLK3_IDRV[1:0]
+  20         CLK4_PDN         MS4_INT         MS4_SRC          CLK4_INV                   CLK4_SRC[1:0]                              CLK4_IDRV[1:0]
+  21         CLK5_PDN         MS5_INT         MS5_SRC          CLK5_INV                   CLK5_SRC[1:0]                              CLK5_IDRV[1:0]
+  22         CLK6_PDN         FBA_INT         MS6_SRC          CLK6_INV                   CLK6_SRC[1:0]                              CLK6_IDRV[1:0]
+  23         CLK7_PDN         FBB_INT         MS6_SRC          CLK7_INV                   CLK7_SRC[1:0]                              CLK7_IDRV[1:0]
+  24           CLK3_DIS_STATE[1:0]             CLK2_DIS_STATE[1:0]                    CLK1_DIS_STATE[1:0]                       CLK0_DIS_STATE[1:0]
+  25           CLK7_DIS_STATE[1:0]             CLK6_DIS_STATE[1:0]                    CLK5_DIS_STATE[1:0]                       CLK4_DIS_STATE[1:0]
+  26                                                                    MSNA_P3[15:8]
+  27                                                                    MSNA_P3[7:0]
+  28                                                     Reserved                                                                    MSNA_P1[17:16]
+
+  29                                                                    MSNA_P1[15:8]
+  30                                                                    MSNA_P1[7:0]
+  31                               MSNA_P3[19:16]                                                           MSNA_P2[19:16]
+
+  32                                                                    MSNA_P2[15:8]
+  33                                                                    MSNA_P2[7:0]
+  34                                                                    MSNB_P3[15:8]
+  35                                                                    MSNB_P3[7:0]
+
+  36                                                     Reserved                                                                    MSNB_P1[17:16]
+
+  37                                                                    MSNB_P1[15:8]
+  38                                                                    MSNB_P1[7:0]
+  39                               MSNB_P3[19:16]                                                           MSNB_P2[19:16]
+  40                                                                    MSNB_P2[15:8]
+  41                                                                    MSNB_P2[7:0]
+  42                                                                    MS0_P3[15:8]
+  43                                                                     MS0_P3[7:0]
+  44                                         R0_DIV[2:0]                                  MS0_DIVBY4[1:0]                            MS0_P1[17:16]
+  45                                                                    MS0_P1[15:8]
+  46                                                                     MS0_P1[7:0]
+  47                               MS0_P3[19:16]                                                                MS0_P2[19:16]
+  48                                                                    MS0_P2[15:8]
+  49                                                                     MS0_P2[7:0]
+
+
+
+
+10        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                                    AN619
+Register         7               6               5             4                  3                     2                   1                   0
+  50                                                                MS1_P3[15:8]
+  51                                                                MS1_P3[7:0]
+  52                                        R1_DIV[2:0]                               MS1_DIVBY4[1:0]                           MS1_P1[17:16]
+  53                                                                MS1_P1[15:8]
+  54                                                                MS1_P1[7:0]
+  55                             MS1_P3[19:16]                                                              MS1_P2[19:16]
+  56                                                                MS1_P2[15:8]
+  57                                                                MS1_P2[7:0]
+  58                                                                MS2_P3[15:8]
+  59                                                                MS2_P3[7:0]
+  60                                        R2_DIV[2:0]                               MS2_DIVBY4[1:0]                           MS2_P1[17:16]
+  61                                                                MS2_P1[15:8]
+  62                                                                MS2_P1[7:0]
+  63                             MS2_P3[19:16]                                                              MS2_P2[19:16]
+  64                                                                MS2_P2[15:8]
+  65                                                                MS2_P2[7:0]
+  66                                                                MS3_P3[15:8]
+  67                                                                MS3_P3[7:0]
+  68                                        R3_DIV[2:0]                               MS3_DIVBY4[1:0]                           MS3_P1[17:16]
+  69                                                                MS3_P1[15:8]
+  70                                                                MS3_P1[7:0]
+  71                             MS3_P3[19:16]                                                              MS3_P2[19:16]
+  72                                                                MS3_P2[15:8]
+  73                                                                MS3_P2[7:0]
+  74                                                                MS4_P3[15:8]
+  75                                                                MS4_P3[7:0]
+  76                                        R4_DIV[2:0]                               MS4_DIVBY4[1:0]                           MS4_P1[17:16]
+  77                                                                MS4_P1[15:8]
+  78                                                                MS4_P1[7:0]
+  79                             MS4_P3[19:16]                                                              MS4_P2[19:16]
+  80                                                                MS4_P2[15:8]
+  81                                                                MS4_P2[7:0]
+  82                                                                MS5_P3[15:8]
+  83                                                                MS5_P3[7:0]
+  84                                        R5_DIV[2:0]                               MS5_DIVBY4[1:0]                           MS5_P1[17:16]
+  85                                                                MS5_P1[15:8]
+  86                                                                MS5_P1[7:0]
+  87                             MS5_P3[19:16]                                                              MS5_P2[19:16]
+  88                                                                MS5_P2[15:8]
+  89                                                                MS5_P2[7:0]
+  90                                                                MS6_P1[7:0]
+  91                                                                MS7_P1[7:0]
+  92          Reserved                      R7_DIV[2:0]                     Reserved                                  R6_DIV[2:0]
+  149         SSC_EN                                                        SSDN_P2[14:8]
+
+  150                                                               SSDN_P2[7:0]
+
+  151       SSC_MODE                                                        SSDN_P3[14:8]
+  152                                                               SSDN_P3[7:0]
+
+  153                                                               SSDN_P1[7:0]
+  154                             SSUDP[11:8]                                                               SSDN_P1[11:8]
+
+  155                                                                SSUDP[7:0]
+  156                                                                       SSUP_P2[14:8]
+
+
+
+
+          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            11
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+Register         7                 6              5            4                  3                  2                   1        0
+  157                                                                SSUP_P2[7:0]
+  158                                                                        SSUP_P3[14:8]
+  159                                                                SSUP_P3[7:0]
+  160                                                                SSUP_P1[7:0]
+  161                              SS_NCLK[3:0]                                                          SSUP_P1[11:8]
+
+  162                                                              VCXO_Param[7:0]
+  163                                                              VCXO_Param[15:8]
+  164                Reserved                                                         VCXO_Param[21:16]
+  165         Reserved                                                     CLK0_PHOFF[6:0]
+  166         Reserved                                                     CLK1_PHOFF[6:0]
+
+  167         Reserved                                                     CLK2_PHOFF[6:0]
+  168         Reserved                                                     CLK3_PHOFF[6:0]
+
+  169         Reserved                                                     CLK4_PHOFF[6:0]
+
+  170         Reserved                                                     CLK5_PHOFF[6:0]
+
+
+171–176                                                                Reserved
+  177        PLLB_RST           Reserved    PLLA_RST                                              Reserved
+178–182                                                                Reserved
+  183                XTAL_CL                                                              Reserved
+184–186                                                                Reserved
+  187        CLKIN_FA-           XO_FA-      Reserved       MS_FA-                                         Reserved
+             NOUT_EN            NOUT_EN                    NOUT_EN
+188-255                                                                Reserved
+
+
+
+
+12        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+9. Register Descriptions
+
+Register 0. Device Status
+
+
+  Bit           D7             D6              D5               D4               D3              D2              D1             D0
+
+ Name      SYS_INIT          LOL_B           LOL_A        LOS_CLKIN LOS_XTAL                 Reserved              REVID[1:0]
+
+ Type           R               R               R                R                R              R                       R
+
+Reset value = 0000 0000
+
+ Bit         Name                                                            Function
+  7        SYS_INIT          System Initialization Status.
+                             During power up the device copies the content of the NVM into RAM and performs a sys-
+                             tem initialization. The device is not operational until initialization is complete. It is not rec-
+                             ommended to read or write registers in RAM through the I2C interface until initialization is
+                             complete. An interrupt will be triggered (INTR pin = 0, Si5351C only) during the system
+                             initialization period.
+                             0: System initialization is complete. Device is ready.
+                             1: Device is in system initialization mode.
+  6          LOL_B           PLLB Loss Of Lock Status.
+                             Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from
+                             CLKIN or XTAL. A loss of lock will occur if the frequency of the reference clock forces the
+                             PLL to operate outside of its lock range or if the reference clock fails to meet the minimum
+                             requirements of a valid input signal as specified in the Si5351 data sheet. An interrupt will
+                             be triggered (INTR pin = 0, Si5351C) during a LOL condition.
+                             0: PLL B is locked.
+                             1: PLL B is unlocked. When the device is in this state it will trigger an interrupt causing the
+                             INTR pin to go low (Si5351C only).
+  5          LOL_A           PLL A Loss Of Lock Status.
+                             PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL. A
+                             loss of lock will occur if the frequency of the reference clock forces the PLL to operate out-
+                             side of its lock range as specified in the data sheet, or if the reference clock fails to meet
+                             the minimum requirements of a valid input signal as specified in the Si5351 data sheet. An
+                             interrupt will be triggered (INTR pin = 0, Si5351C only) during a LOL condition.
+                             0: PLL A is operating normally.
+                             1: PLL A is unlocked. When the device is in this state it will trigger an interrupt causing the
+                             INTR pin to go low (Si5351C only).
+  4       LOS_CLKIN          CLKIN Loss Of Signal (Si5351C Only).
+                             A loss of signal status indicates if the reference clock fails to meet the minimum require-
+                             ments of a valid input signal as specified in the Si5351 data sheet. An interrupt will be trig-
+                             gered (INTR pin = 0, Si5351C only) during a LOS condition.
+                             0: Valid clock signal at the CLKIN pin.
+                             1: Loss of signal detected at the CLKIN pin.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            13
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+  3        LOS_XTAL           Crystal Loss of Signal
+                              A loss of signal status indicates that the crystal failed to meet the minimum requirements
+                              of a valid input signal as specified in the Si5351 datasheet. This bit going high will trigger
+                              an interrupt (INTR pin = 0) on a Si5351C device.
+                              0: Valid crystal signal at the XA and XB Pins
+                              1: Loss of crystal signal detected
+  2         Reserved          Leave as default.
+ 1:0       REVID[1:0]         Revision number of the device.
+
+
+
+
+14        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                        AN619
+
+Register 1. Interrupt Status Sticky
+
+
+   Bit              D7                    D6                 D5                 D4                  D3             D2      D1      D0
+
+ Name       SYS_INIT_STKY LOL_B_STKY LOL_A_STKY                            LOS_-                LOS_
+                                                                         CLKIN_STKY           XTAL_STKY
+
+  Type             R/W                   R/W                R/W                R/W                 R/W            R/W     R/W     R/W
+
+Reset value = 0000 0000
+
+ Bit            Name                                                           Function
+
+  7       SYS_INIT_STKY          System Calibration Status Sticky Bit.
+                                 The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig-
+                                 gered high. It remains high until cleared. Writing a 0 to this register bit will cause it to
+                                 clear.
+                                 0: No SYS_INIT interrupt has occurred since it was last cleared.
+                                 1: A SYS_INIT interrupt has occurred since it was last cleared.
+
+  6        LOL_B_STKY            PLLB Loss Of Lock Status Sticky Bit.
+                                 The LOL_B_STKY bit is triggered when the LOL_B bit (register 0, bit 6) is triggered
+                                 high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
+                                 0: No PLL B interrupt has occurred since it was last cleared.
+                                 1: A PLL B interrupt has occurred since it was last cleared.
+
+  5        LOL_A_STKY            PLLA Loss Of Lock Status Sticky Bit.
+                                 The LOL_A_STKY bit is triggered when the LOL_A bit (register 0, bit 5) is triggered
+                                 high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
+                                 0: No PLLA interrupt has occurred since it was last cleared.
+                                 1: A PLLA interrupt has occurred since it was last cleared.
+
+  4      LOS_CLKIN_STKY CLKIN Loss Of Signal Sticky Bit (Si5351C Only).
+                                 The LOS_CLKIN_STKY bit is triggered when the LOS_CLKIN bit (register 0, bit 4) is
+                                 triggered high. It remains high until cleared. Writing a 0 to this register bit will cause it
+                                 to clear.
+                                 0: No LOS_CLKIN interrupt has occurred since it was last cleared.
+                                 1: A LOS_CLKIN interrupt has occurred since it was last cleared.
+
+  3      LOS_XTAL_STKY Crystal Loss of Signal Sticky Bit
+                                 The LOS_XTAL_STKY bit is triggered when the LOS_XTAL bit (register 0, bit 3) is
+                                 triggered high. It remains high until cleared. Writing a 0 to this register bit will cause it
+                                 to clear.
+                                 0: No LOS_XTAL interrupt has occurred since it was last cleared.
+                                 1: A LOS_XTAL interrupt has occurred since it was last cleared.
+
+ 2:0          Reserved           Leave as default.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            15
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 2. Interrupt Status Mask
+
+
+   Bit               D7                    D6                  D5                 D4                  D3            D2      D1      D0
+
+  Name      SYS_INIT_MASK LOL_B_MASK LOL_A_MASK                               LOS_-                LOS_
+                                                                           CLKIN_MASK           XTAL_MASK
+
+  Type              R/W                   R/W                 R/W                R/W                 R/W           R/W     R/W     R/W
+
+Reset value = 0000 0000
+
+  Bit           Name                                                           Function
+
+   7     SYS_INIT_MASK System Initialization Status Mask.
+                                 Use this mask bit to prevent the INTR pin (Si5351C only) from going low when SYS-
+                                 _INIT is asserted.
+                                 0: Do not mask the SYS_INIT interrupt.
+                                 1: Mask the SYS_INIT interrupt.
+
+   6       LOL_B_MASK            PLLB Loss Of Lock Status Mask.
+                                 Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_B
+                                 is asserted.
+                                 0: Do not mask the LOL_B interrupt.
+                                 1: Mask the LOL_B interrupt.
+
+   5       LOL_A_MASK            PLL A Loss Of Lock Status Mask.
+                                 Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_A
+                                 is asserted.
+                                 0: Do not mask the LOL_A interrupt.
+                                 1: Mask the LOL_A interrupt.
+
+   4          LOS_-              CLKIN Loss Of Signal Mask (Si5351C Only).
+           CLKIN_MASK            Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOS_-
+                                 CLKIN is asserted.
+                                 0: Do not mask the LOS_CLKIN interrupt.
+                                 1: Mask the LOS_CLKIN interrupt.
+
+   3           LOS_              Crystal Loss of Signal Mask
+            XTAL_MASK            Use this mask bit to prevent the INTR pin (Si5351C only) from going low when
+                                 LOS_XTAL is asserted.
+                                 0: Do not mask the LOS_XTAL interrupt
+                                 1: Mask the LOS_XTAL interrupt
+
+  2:0         Reserved           Leave as default.
+
+
+
+
+16        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 3. Output Enable Control
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name      CLK7_OEB CLK6_OEB CLK5_OEB CLK4_OEB CLK3_OEB CLK2_OEB CLK1_OEB CLK0_OEB
+
+  Type          R/W            R/W             R/W             R/W             R/W            R/W             R/W             R/W
+
+Reset value = 0000 0000
+
+ Bit       Name                                                           Function
+
+ 7:0     CLKx_OEB Output Disable for CLKx.
+                        Where x = 0, 1, 2, 3, 4, 5, 6, 7
+                        0: Enable CLKx output.
+                        1: Disable CLKx output.
+
+
+
+Register 9. OEB Pin Enable Control Mask
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name       OEB_MAS OEB_MAS OEB_MAS OEB_MAS OEB_MAS OEB_MAS OEB_MAS OEB_MAS
+               K7      K6      K5      K4      K3      K2      K1      K0
+
+  Type          R/W            R/W             R/W             R/W             R/W            R/W             R/W             R/W
+
+Reset value = 0000 0000
+
+ Bit       Name                                                           Function
+
+ 7:0     OEB_CLKx OEB pin enable control of CLKx.
+                        Where x = 0, 1, 2, 3, 4, 5, 6, 7
+                        0: OEB pin controls enable/disable state of CLKx output.
+                        1: OEB pin does not control enable/disable state of CLKx output.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            17
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 15. PLL Input Source
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name           CLKIN_DIV[1:0]                                            PLLB_SRC PLLA_SRC
+
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+
+Reset value = 0000 0000
+
+ Bit            Name                                                            Function
+
+ 7:6      CLKIN_DIV[1:0]         ClKIN Input Divider.
+                                 Valid PLL input range is 10-40 MHz. If CLKIN is > 40 MHz, CLKIN input divider,
+                                 CLKIN_DIV, must be used to bring the PLL input within the 10-40 MHz range.
+                                 00b: Divide by 1.
+                                 01b: Divide by 2.
+                                 10b: Divide by 4.
+                                 11b: Divide by 8.
+
+ 5:4          Reserved           Leave as default.
+
+  3          PLLB_SRC            Input Source Select for PLLB.
+                                 0: Select the XTAL input as the reference clock for PLLB.
+                                 1: Select the CLKIN input as the reference clock for PLLB (Si5351C only).
+
+  2          PLLA_SRC            Input Source Select for PLLA.
+                                 0: Select the XTAL input as the reference clock for PLLA.
+                                 1: Select the CLKIN input as the reference clock for PLLA (Si5351C only).
+
+ 1:0          Reserved           Leave as default.
+
+
+
+
+18        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 16. CLK0 Control
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name      CLK0_PDN         MS0_INT        MS0_SRC         CLK0_INV            CLK0_SRC[1:0]                   CLK0_IDRV[1:0]
+
+  Type          R/W            R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+ Bit           Name                                                          Function
+
+  7        CLK0_PDN           Clock 0 Power Down.
+                              This bit allows powering down the CLK0 output driver to conserve power when the out-
+                              put is unused.
+                              0: CLK0 is powered up.
+                              1: CLK0 is powered down.
+
+  6          MS0_INT          MultiSynth 0 Integer Mode.
+                              This bit can be used to force MS0 into Integer mode to improve jitter performance. Note
+                              that the fractional mode is necessary when a delay offset is specified for CLK0.
+                              0: MS0 operates in fractional division mode.
+                              1: MS0 operates in integer mode.
+
+  5         MS0_SRC           MultiSynth Source Select for CLK0.
+                              0: Select PLLA as the source for MultiSynth0.
+                              1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth0.
+
+  4         CLK0_INV          Output Clock 0 Invert.
+                              0: Output Clock 0 is not inverted.
+                              1: Output Clock 0 is inverted.
+
+ 3:2     CLK0_SRC[1:0] Output Clock 0 Input Source.
+                              These bits determine the input source for CLK0.
+                              00: Select the XTAL as the clock source for CLK0. This option by-passes both synthesis
+                              stages (PLL/VCXO & MultiSynth) and connects CLK0 directly to the oscillator which
+                              generates an output frequency determined by the XTAL frequency.
+                              01: Select CLKIN as the clock source for CLK0. This by-passes both synthesis stages
+                              (PLL/VCXO & MultiSynth) and connects CLK0 directly to the CLKIN input. This essen-
+                              tially creates a buffered output of the CLKIN input.
+                              10: Reserved. Do not select this option.
+                              11: Select MultiSynth 0 as the source for CLK0. Select this option when using the
+                              Si5351 to generate free-running or synchronous clocks.
+
+ 1:0     CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength Control.
+                              00: 2 mA
+                              01: 4 mA
+                              10: 6 mA
+                              11: 8 mA
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            19
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 17. CLK1 Control
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name      CLK1_PDN         MS1_INT        MS1_SRC         CLK1_INV            CLK1_SRC[1:0]                   CLK1_IDRV[1:0]
+
+   Type         R/W             R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit          Name                                                           Function
+
+   7        CLK1_PDN           Clock 1 Power Down.
+                               This bit allows powering down the CLK1 output driver to conserve power when the out-
+                               put is unused.
+                               0: CLK1 is powered up.
+                               1: CLK1 is powered down.
+
+   6         MS1_INT           MultiSynth 1 Integer Mode.
+                               When the MS1 divider is an even integer, this bit can be used to force MS1 into integer
+                               mode to improve jitter performance. Not valid for odd integers. Note that the fractional
+                               mode is necessary when a delay offset is specified for CLK1.
+                               0: MS1 operates in fractional division mode.
+                               1: MS1 operates in integer mode.
+
+   5         MS1_SRC           MultiSynth Source Select for CLK1.
+                               0: Select PLLA as the source for MultiSynth1.
+                               1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth1.
+
+   4         CLK1_INV          Output Clock 1 Invert.
+                               0: Output Clock 1 is not inverted.
+                               1: Output Clock 1 is inverted.
+
+  3:2     CLK1_SRC[1:0] Output Clock 1 Input Source.
+                               These bits determine the input source for CLK1.
+                               00: Select the XTAL as the clock source for CLK1. This option by-passes both synthesis
+                               stages (PLL/VCXO & MultiSynth) and connects CLK1 directly to the oscillator which
+                               generates an output frequency determined by the XTAL frequency.
+                               01: Select CLKIN as the clock source for CLK1. This by-passes both synthesis stages
+                               (PLL/VCXO & MultiSynth) and connects CLK1 directly to the CLKIN input. This essen-
+                               tially creates a buffered output of the CLKIN input.
+                               10: Select Multisynth 0 as the source for CLK1.
+                               11: Select MultiSynth 1 as the source for CLK1. Select this option when using the
+                               Si5351 to generate free-running or synchronous clocks.
+
+  1:0     CLK1_IDRV[1:0] CLK1 Output Rise and Fall time / Drive Strength Control.
+                               00: 2 mA
+                               01: 4 mA
+                               10: 6 mA
+                               11: 8 mA
+
+
+
+
+20        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 18. CLK2 Control
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name      CLK2_PDN         MS2_INT        MS2_SRC         CLK2_INV            CLK2_SRC[1:0]                   CLK2_IDRV[1:0]
+
+  Type          R/W            R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+ Bit          Name                                                           Function
+
+  7        CLK2_PDN           Clock 2 Power Down.
+                              This bit allows powering down the CLK2 output driver to conserve power when the out-
+                              put is unused.
+                              0: CLK2 is powered up.
+                              1: CLK2 is powered down.
+
+  6         MS2_INT           MultiSynth 2 Integer Mode.
+                              When the MS2 divider is an even integer, this bit can be used to force MS2 into integer
+                              mode to improve jitter performance. Not valid for odd integers. Note that the fractional
+                              mode is necessary when a delay offset is specified for CLK2.
+                              0: MS2 operates in fractional division mode.
+                              1: MS2 operates in integer mode.
+
+  5        MS2_SRC            MultiSynth Source Select for CLK2.
+                              0: Select PLLA as the source for MultiSynth2.
+                              1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth2.
+
+  4        CLK2_INV           Output Clock 2 Invert.
+                              0: Output Clock 2 is not inverted.
+                              1: Output Clock 2 is inverted.
+
+ 3:2     CLK2_SRC[1:0] Output Clock 2 Input Source.
+                              These bits determine the input source for CLK2.
+                              00: Select the XTAL as the clock source for CLK2. This option by-passes both synthesis
+                              stages (PLL/VCXO & MultiSynth) and connects CLK2 directly to the oscillator which gen-
+                              erates an output frequency determined by the XTAL frequency.
+                              01: Select CLKIN as the clock source for CLK2. This by-passes both synthesis stages
+                              (PLL/VCXO & MultiSynth) and connects CLK2 directly to the CLKIN input. This essen-
+                              tially creates a buffered output of the CLKIN input.
+                              10: Select Multisynth 0 as the source for CLK2.
+                              11: Select MultiSynth 2 as the source for CLK2. Select this option when using the Si5351
+                              to generate free-running or synchronous clocks.
+
+ 1:0     CLK2_IDRV[1:0] CLK2 Output Rise and Fall time / Drive Strength Control.
+                              00: 2 mA
+                              01: 4 mA
+                              10: 6 mA
+                              11: 8 mA
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            21
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 19. CLK3 Control
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name      CLK3_PDN         MS3_INT        MS3_SRC         CLK3_INV            CLK3_SRC[1:0]                   CLK3_IDRV[1:0]
+
+   Type         R/W             R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit           Name                                                           Function
+
+   7         CLK3_PDN           Clock 3 Power Down.
+                                This bit allows powering down the CLK3 output driver to conserve power when the out-
+                                put is unused.
+                                0: CLK3 is powered up.
+                                1: CLK3 is powered down.
+                                Write this bit to a 1 when programming a Si5351A-B-GT 10-MSOP Device.
+
+   6          MS3_INT           MultiSynth 3 Integer Mode.
+                                When the MS3 divider is an even integer, this bit can be used to force MS3 into integer
+                                mode to improve jitter performance. Not valid for odd integers. Note that the fractional
+                                mode is necessary when a delay offset is specified for CLK3.
+                                0: MS3 operates in fractional division mode.
+                                1: MS3 operates in integer mode.
+
+   5         MS3_SRC            MultiSynth Source Select for CLK3.
+                                0: Select PLLA as the source for MultiSynth3.
+                                1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth3.
+
+   4         CLK3_INV           Output Clock 3 Invert.
+                                0: Output Clock 3 is not inverted.
+                                1: Output Clock 3 is inverted.
+
+  3:2     CLK3_SRC[1:0] Output Clock 3 Input Source.
+                                These bits determine the input source for CLK3.
+                                00: Select the XTAL as the clock source for CLK3. This option by-passes both synthe-
+                                sis changes (PCL/VCXO and Multisynth) and connects CLK3 directly to the oscillator
+                                which generates an output frequency determined by the XTAL frequency.
+                                01: Select CLKIN as the clock source for CLK3. This by-passes both synthesis stages
+                                (PLL/VCXO and Multisynth) and connects CLK3 directly to the CLKIN input. This
+                                essentially creates a buffered output of the CLKIN input.
+                                10: Select Multisynth 0 as the source for CLK3.
+                                11: Select Multisynth 3 as the source for CLK3. Select this option when using the
+                                Si5351 to generate free-running or synchronous clocks.
+
+  1:0     CLK3_IDRV[1:0] CLK3 Output Rise and Fall time / Drive Strength Control.
+                                00: 2 mA
+                                01: 4 mA
+                                10: 6 mA
+                                11: 8 mA
+
+
+
+22        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 20. CLK4 Control
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name      CLK4_PDN         MS4_INT        MS4_SRC         CLK4_INV            CLK4_SRC[1:0]                   CLK4_IDRV[1:0]
+
+  Type          R/W            R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit          Name                                                           Function
+
+  7         CLK4_PDN           Clock 4 Power Down.
+                               This bit allows powering down the CLK4 output driver to conserve power when the out-
+                               put is unused.
+                               0: CLK4 is powered up.
+                               1: CLK4 is powered down.
+                               Write this bit to a 1 when programming a Si5351A-B-GT 10-MSOP Device.
+
+  6          MS4_INT           MultiSynth 4 Integer Mode.
+                               When the MS4 divider is an even integer, this bit can be used to force MS4 into integer
+                               mode to improve jitter performance. Not valid for odd integers. Note that the fractional
+                               mode is necessary when a delay offset is specified for CLK4.
+                               0: MS4 operates in fractional division mode.
+                               1: MS4 operates in integer mode.
+
+  5          MS4_SRC           MultiSynth Source Select for CLK4.
+                               0: Select PLLA as the source for MultiSynth4.
+                               1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth4.
+
+  4          CLK4_INV          Output Clock 4 Invert.
+                               0: Output Clock 4 is not inverted.
+                               1: Output Clock 4 is inverted.
+
+ 3:2     CLK4_SRC[1:0] Output Clock 4 Input Source.
+                               These bits determine the input source for CLK4.
+                               00: Select the XTAL as the clock source for CLK4. This option by-passes both synthe-
+                               sis stages (PLL/VCXO & MultiSynth) and connects CLK4 directly to the oscillator
+                               which generates an output frequency determined by the XTAL frequency.
+                               01: Select CLKIN as the clock source for CLK4. This by-passes both synthesis stages
+                               (PLL/VCXO & MultiSynth) and connects CLK4 directly to the CLKIN input. This essen-
+                               tially creates a buffered output of the CLKIN input.
+                               10: Reserved. Do not select this option.
+                               11: Select MultiSynth 4 as the source for CLK4. Select this option when using the
+                               Si5351 to generate free-running or synchronous clocks.
+
+ 1:0     CLK4_IDRV[1:0] CLK4 Output Rise and Fall time / Drive Strength Control.
+                               00: 2 mA
+                               01: 4 mA
+                               10: 6 mA
+                               11: 8 mA
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            23
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 21. CLK5 Control
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name      CLK5_PDN         MS5_INT        MS5_SRC         CLK5_INV            CLK5_SRC[1:0]                   CLK5_IDRV[1:0]
+
+   Type         R/W             R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit           Name                                                           Function
+
+   7         CLK5_PDN           Clock 5 Power Down.
+                                This bit allows powering down the CLK5 output driver to conserve power when the out-
+                                put is unused.
+                                0: CLK5 is powered up.
+                                1: CLK5 is powered down.
+                                Write this bit to a 1 when programming a Si5351A-B-GT 10-MSOP Device.
+
+   6          MS5_INT           MultiSynth 5 Integer Mode.
+                                When the MS5 divider is an even integer, this bit can be used to force MS5 into integer
+                                mode to improve jitter performance. Not valid for odd integers. Note that the fractional
+                                mode is necessary when a delay offset is specified for CLK5.
+                                0: MS5 operates in fractional division mode.
+                                1: MS5 operates in integer mode.
+
+   5          MS5_SRC           MultiSynth Source Select for CLK5.
+                                0: Select PLLA as the source for MultiSynth5.
+                                1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth5.
+
+   4          CLK5_INV          Output Clock 5 Invert.
+                                0: Output Clock 5 is not inverted.
+                                1: Output Clock 5 is inverted.
+
+  3:2     CLK5_SRC[1:0] Output Clock 5 Input Source.
+                                These bits determine the input source for CLK5.
+                                00: Select the XTAL as the clock source for CLK5. This option by-passes both synthe-
+                                sis stages (PLL/VCXO & MultiSynth) and connects CLK5 directly to the oscillator
+                                which generates an output frequency determined by the XTAL frequency.
+                                01: Select CLKIN as the clock source for CLK5. This by-passes both synthesis stages
+                                (PLL/VCXO & MultiSynth) and connects CLK5 directly to the CLKIN input. This essen-
+                                tially creates a buffered output of the CLKIN input.
+                                10: Select Multisynth 4 as the source for CLK5.
+                                11: Select MultiSynth 5 as the source for CLK5. Select this option when using the
+                                Si5351 to generate free-running or synchronous clocks.
+
+  1:0     CLK5_IDRV[1:0] CLK5 Output Rise and Fall time / Drive Strength Control.
+                                00: 2 mA
+                                01: 4 mA
+                                10: 6 mA
+                                11: 8 mA
+
+
+
+24        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 22. CLK6 Control
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name      CLK6_PDN         FBA_INT        MS6_SRC         CLK6_INV            CLK6_SRC[1:0]                   CLK6_IDRV[1:0]
+
+  Type          R/W            R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit          Name                                                           Function
+
+  7         CLK6_PDN           Clock 7 Power Down.
+                               This bit allows powering down the CLK6 output driver to conserve power when the out-
+                               put is unused.
+                               0: CLK6 is powered up.
+                               1: CLK6 is powered down.
+                               Write this bit to a 1 when programming a Si5351A-B-GT 10-MSOP Device.
+
+  6          FBA_INT           FBA MultiSynth Integer Mode.
+                               This bit can be used to force Feedback A Multisynth into Integer mode to improve jitter
+                               performance. Note that the fractional mode is necessary when spread spectrum is
+                               specified for any output clocks.
+                               0: MSNA operates in fractional division mode.
+                               1: MSNA operates in integer mode.
+
+  5          MS6_SRC           MultiSynth Source Select for CLK6.
+                               0: Select PLLA as the source for MultiSynth6.
+                               1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth6.
+
+  4          CLK6_INV          Output Clock 6 Invert.
+                               0: Output Clock 6 is not inverted.
+                               1: Output Clock 6 is inverted.
+
+ 3:2     CLK6_SRC[1:0] Output Clock 6 Input Source.
+                               These bits determine the input source for CLK6.
+                               00: Select the XTAL as the clock source for CLK6. This option by-passes both synthe-
+                               sis stages (PLL/VCXO & MultiSynth) and connects CLK6 directly to the oscillator
+                               which generates an output frequency determined by the XTAL frequency.
+                               01: Select CLKIN as the clock source for CLK6. This by-passes both synthesis stages
+                               (PLL/VCXO & MultiSynth) and connects CLK6 directly to the CLKIN input. This essen-
+                               tially creates a buffered output of the CLKIN input.
+                               10: Select Multisynth 4 as the source for CLK6.
+                               11: Select MultiSynth 6 as the source for CLK6. Select this option when using the
+                               Si5351 to generate free-running or synchronous clocks.
+
+ 1:0     CLK6_IDRV[1:0] CLK6 Output Rise and Fall time / Drive Strength Control.
+                               00: 2 mA
+                               01: 4 mA
+                               10: 6 mA
+                               11: 8 mA
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            25
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 23. CLK7 Control
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name      CLK7_PDN         FBB_INT        MS7_SRC         CLK7_INV            CLK7_SRC[1:0]                   CLK7_IDRV[1:0]
+
+   Type         R/W             R/W             R/W             R/W                     R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit           Name                                                           Function
+
+   7         CLK7_PDN           Clock 7 Power Down.
+                                This bit allows powering down the CLK7 output driver to conserve power when the out-
+                                put is unused.
+                                0: CLK7 is powered up.
+                                1: CLK7 is powered down.
+                                Write this bit to a 1 when programming a Si5351A-B-GT 10-MSOP Device.
+
+   6          FBB_INT           FBB MultiSynth Integer Mode.
+                                This bit can be used to force Feedback B into Integer mode to improve jitter perfor-
+                                mance.
+                                0: MSNB operates in fractional division mode.
+                                1: MSNB operates in integer mode.
+
+   5          MS7_SRC           MultiSynth Source Select for CLK7.
+                                0: Select PLLA as the source for MultiSynth7.
+                                1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) for MultiSynth7.
+
+   4          CLK7_INV          Output Clock 7 Invert.
+                                0: Output Clock 7 is not inverted.
+                                1: Output Clock 7 is inverted.
+
+  3:2     CLK7_SRC[1:0] Output Clock 7 Input Source.
+                                These bits determine the input source for CLK7.
+                                00: Select the XTAL as the clock source for CLK7. This option by-passes both synthe-
+                                sis stages (PLL/VCXO & MultiSynth) and connects CLK7 directly to the oscillator
+                                which generates an output frequency determined by the XTAL frequency.
+                                01: Select CLKIN as the clock source for CLK7. This by-passes both synthesis stages
+                                (PLL/VCXO & MultiSynth) and connects CLK7 directly to the CLKIN input. This essen-
+                                tially creates a buffered output of the CLKIN input.
+                                10: Select Multisynth 4 as the source for CLK7.
+                                11: Select MultiSynth 7 as the source for CLK7. Select this option when using the
+                                Si5351 to generate free-running or synchronous clocks.
+
+  1:0     CLK7_IDRV[1:0] CLK7 Output Rise and Fall time / Drive Strength Control.
+                                00: 2 mA
+                                01: 4 mA
+                                10: 6 mA
+                                11: 8 mA
+
+
+
+
+26        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 24. CLK3–0 Disable State
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name          CLK3_DIS_STATE                 CLK2_DIS_STATE                  CLK1_DIS_STATE                 CLK0_DIS_STATE
+
+  Type                 R/W                             R/W                             R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit             Name                                                          Function
+
+  7:0     CLKx_DIS_STATE             Clock x Disable State.
+                                     Where x = 0, 1, 2, 3. These 2 bits determine the state of the CLKx output when dis-
+                                     abled. Individual output clocks can be disabled using register Output Enable Con-
+                                     trol located at address 3. Outputs are also disabled using the OEB pin.
+                                     00: CLKx is set to a LOW state when disabled.
+                                     01: CLKx is set to a HIGH state when disabled.
+                                     10: CLKx is set to a HIGH IMPEDANCE state when disabled.
+                                     11: CLKx is NEVER DISABLED.
+
+
+Register 25. CLK7–4 Disable State
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+ Name          CLK7_DIS_STATE                 CLK6_DIS_STATE                  CLK5_DIS_STATE                 CLK4_DIS_STATE
+
+  Type                 R/W                             R/W                             R/W                            R/W
+
+Reset value = 0000 0000
+
+  Bit            Name                                                           Function
+
+ 7:0      CLKx_DIS_STATE             Clock x Disable State.
+                                     Where x = 4, 5, 6, 7. These 2 bits determine the state of the CLKx output when dis-
+                                     abled. Individual output clocks can be disabled using register Output Enable Con-
+                                     trol located at address 3. Outputs are also disabled using the OEB pin.
+                                     00: CLKx is set to a LOW state when disabled.
+                                     01: CLKx is set to a HIGH state when disabled.
+                                     10: CLKx is set to a HIGH IMPEDANCE state when disabled.
+                                     11: CLKx is NEVER DISABLED.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            27
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 26. Multisynth NA Parameters
+
+
+     Bit            D7             D6              D5             D4              D3              D2             D1             D0
+   Name                                                           MSNA_P3[15:8]
+
+   Type                                                                  R/W
+Reset value = xxxx xxxx
+
+   Bit          Name                                                             Function
+   7:0       MSNA_P3[15:8]          Multisynth NA Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the PLLA Feedback Multisynth Divider.
+
+
+
+Register 27. Multisynth NA Parameters
+
+
+     Bit            D7             D6              D5             D4              D3              D2             D1             D0
+
+   Name                                                            MSNA_P3[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit           Name                                                            Function
+   7:0        MSNA_P3[7:0]          Multisynth NA Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the PLLA Feedback Multisynth Divider.
+
+
+
+Register 28. Multisynth NA Parameters
+
+
+     Bit            D7             D6              D5             D4              D3              D2             D1             D0
+
+   Name                                 Unused                                         Reserved                 MSNA_P1[17:16]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:4            Unused            Unused.
+   3:2           Reserved           Reserved.
+                                    Leave as default, 0.
+   1:0      MSNA_P1[17:16]          Multisynth NA Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the PLLA
+                                    Feedback Multisynth divider.
+
+
+
+
+28        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 29. Multisynth NA Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                           MSNA_P1[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit          Name                                                             Function
+  7:0       MSNA_P1[15:8]          Multisynth NA Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the PLLA
+                                   Feedback Multisynth divider.
+
+
+
+Register 30. Multisynth NA Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MSNA_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit           Name                                                            Function
+  7:0        MSNA_P1[7:0]          Multisynth NA Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the PLLA
+                                   Feedback Multisynth divider.
+
+
+
+Register 31. Multisynth NA Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                           MSNA_P3[19:16]                                                MSNA_P2[19:16]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit         Name                                                              Function
+  7:4      MSNA_P3[19:16]          Multisynth NA Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the PLLA Feedback Multisynth divider.
+  3:0      MSNA_P2[19:16]          Multisynth NA Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the PLLA Feedback Multisynth divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            29
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 32. Multisynth NA Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                           MSNA_P2[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit          Name                                                             Function
+   7:0       MSNA_P2[15:8]          Multisynth NA Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the PLLA Feedback Multisynth divider.
+
+
+
+Register 33. Multisynth NA Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MSNA_P2[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit           Name                                                            Function
+   7:0        MSNA_P2[7:0]          Multisynth NA Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the PLLA Feedback Multisynth divider.
+
+
+
+Register 34. Multisynth NB Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                           MSNB_P3[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit          Name                                                             Function
+   7:0       MSNB_P3[15:8]          Multisynth NA Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the PLLA Feedback Multisynth divider.
+
+
+
+
+30        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 35. Multisynth NB Parameters
+
+
+    Bit            D7             D6              D5             D4              D3              D2             D1             D0
+
+  Name                                                            MSNB_P3[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit           Name                                                            Function
+  7:0        MSNB_P3[7:0]          Multisynth NB Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the PLLB Feedback Multisynth divider.
+
+
+
+Register 36. Multisynth NB Parameters
+
+
+    Bit            D7             D6              D5             D4              D3              D2             D1             D0
+
+  Name                                 Unused                                         Reserved                 MSNB_P1[17:16]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:4                                                               Unused
+  3:2           Reserved           Reserved.
+                                   Leave as default, 0.
+  1:0      MSNB_P1[17:16]          Multisynth NB Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part for the frac-
+                                   tional part of the PLLB Feedback Multisynth divider.
+
+
+
+Register 37. Multisynth NB Parameters
+
+
+    Bit            D7             D6              D5             D4              D3              D2             D1             D0
+
+  Name                                                           MSNB_P1[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit          Name                                                   Function
+  7:0       MSNB_P1[15:8]          Multisynth NB Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the PLLB
+                                   Feedback Multisynth divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            31
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 38. Multisynth NB Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MSNB_P1[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit           Name                                                  Function
+   7:0        MSNB_P1[7:0]          Multisynth NB Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the PLLB
+                                    Feedback Multisynth divider.
+
+
+
+Register 39. Multisynth NB Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                           MSNB_P3[19:16]                                                MSNB_P2[19:16]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit         Name                                                              Function
+   7:4      MSNB_P3[19:16]          Multisynth NB Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the PLLB Feedback Multisynth divider.
+   3:0      MSNB_P2[19:16]          Multisynth NB Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the PLLB Feedback Multisynth divider.
+
+
+
+Register 40. Multisynth NB Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                           MSNB_P2[15:8]
+
+    Type                                                                 R/W
+
+Reset value = xxxx xxxx
+
+   Bit          Name                                                             Function
+   7:0       MSNB_P2[15:8]          Multisynth NB Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the PLLB Feedback Multisynth divider.
+
+
+
+
+32        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 41. Multisynth NB Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MSNB_P2[7:0]
+
+   Type                                                                 R/W
+
+  Bit           Name                                                   Function
+  7:0        MSNB_P2[7:0]          Multisynth NB Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the PLLB Feedback Multisynth divider.
+
+
+
+Register 42. Multisynth0 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+  Name                                                            MS0_P3[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit           Name                                                            Function
+  7:0        MS0_P3[15:8]          Multisynth0 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the MultiSynth0 Divider.
+
+
+
+Register 43. Multisynth0 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS0_P3[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit              Name                                                          Function
+  7:0          MS0_P3[7:0]           Multisynth0 Parameter 3.
+                                     This 20-bit number is an encoded representation of the denominator for the frac-
+                                     tional part of the MultiSynth0 Divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            33
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 44. Multisynth0 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+   Name                                      R0_DIV[2:0]                        MS0_DIVBY4[1:0]                  MS0_P1[17:16]
+   Type            R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+    7             Unused
+   6:4         R0_DIV[2:0]          R0 Output Divider.
+                                    000b: Divide by 1
+                                    001b: Divide by 2
+                                    010b: Divide by 4
+                                    011b: Divide by 8
+                                    100b: Divide by 16
+                                    101b: Divide by 32
+                                    110b: Divide by 64
+                                    111b: Divide by 128
+   3:2     MS0_DIVBY4[1:0] MS0 Divide by 4 Enable.
+                           11: Divide by 4 enabled.
+                           00: Divide by a value other than 4.
+   1:0       MS0_P1[17:16]          Multisynth0 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    Synth0 divider.
+
+
+
+Register 45. Multisynth0 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2             D1              D0
+   Name                                                            MS0_P1[15:8]
+  Type                                                                   R/W
+Reset value = xxxx xxxx
+
+
+   Bit             Name                                                          Function
+   7:0        MS0_P1[15:8]          Multisynth0 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    Synth1 divider.
+
+
+
+
+34        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 46. Multisynth0 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS0_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS0_P1[7:0]          Multisynth0 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   Synth1 divider.
+
+
+
+Register 47. Multisynth0 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                            MS0_P3[19:16]                                                 MS0_P2[19:16]
+
+   Type                                  R/W                                                           R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:4       MS0_P3[19:16]          Multisynth0 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the MultiSynth0 Divider
+  3:0       MS0_P2[19:16]          Multisynth0 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the MultiSynth1 Divider.
+
+
+
+Register 48. Multisynth0 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS0_P2[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS0_P2[15:8]          Multisynth0 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the MultiSynth1 Divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            35
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 49. Multisynth0 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS0_P2[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS0_P2[7:0]          Multisynth0 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the MultiSynth1 Divider.
+
+
+
+Register 50. Multisynth1 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS1_P3[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS1_P3[15:8]          Multisynth1 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the MultiSynth1 Divider.
+
+
+
+Register 51. Multisynth1 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS1_P3[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS1_P3[7:0]          Multisynth1 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the MultiSynth1 Divider.
+
+
+
+
+36        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 52. Multisynth1 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+  Name                                      R1_DIV[2:0]                        MS1_DIVBY4[1:0]                  MS1_P1[17:16]
+
+   Type           R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+   7             Unused
+  6:4         R1_DIV[2:0]          R1 Output Divider.
+                                   000b: Divide by 1
+                                   001b: Divide by 2
+                                   010b: Divide by 4
+                                   011b: Divide by 8
+                                   100b: Divide by 16
+                                   101b: Divide by 32
+                                   110b: Divide by 64
+                                   111b: Divide by 128
+  3:2     MS1_DIVBY4[1:0] MS1 Divide by 4 Enable.
+                          11: Divide by 4 enabled.
+                          00: Divide by a value other than 4.
+  1:0       MS1_P1[17:16]          Multisynth1 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   Synth1 divider.
+
+
+
+Register 53. Multisynth1 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS1_P1[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS1_P1[15:8]          Multisynth1 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   Synth1 divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            37
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 54. Multisynth1 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS1_P1[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS1_P1[7:0]          Multisynth1 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    Synth1 divider.
+
+
+
+Register 55. Multisynth1 Parameters
+
+
+     Bit             D7             D6             D5              D4             D3             D2              D1             D0
+
+   Name                             MS1_P3[19:16]                                                MS1_P2[19:16]
+
+    Type                                   R/W                                                          R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:4       MS1_P3[19:16]          Multisynth1 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth1 Divider
+   3:0       MS1_P2[19:16]          Multisynth1 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the MultiSynth1 Divider.
+
+
+
+Register 56. Multisynth1 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS1_P2[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS1_P2[15:8]          Multisynth1 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the MultiSynth1 divider.
+
+
+
+
+38        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 57. Multisynth1 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS1_P2[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS1_P2[7:0]          Multisynth1 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the MultiSynth1 divider.
+
+
+
+Register 58. Multisynth2 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS2_P3[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS2_P3[15:8]          Multisynth2 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the MultiSynth2 divider.
+
+
+
+Register 59. Multisynth2 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS2_P3[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS2_P3[7:0]          Multisynth2 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the MultiSynth2 divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            39
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 60. Multisynth2 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2             D1              D0
+
+   Name                                      R2_DIV[2:0]                        MS2_DIVBY4[1:0]                 MS2_P1[17:16]
+
+    Type           R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+    7             Unused
+   6:4         R2_DIV[2:0]          R2 Output Divider.
+                                    000b: Divide by 1
+                                    001b: Divide by 2
+                                    010b: Divide by 4
+                                    011b: Divide by 8
+                                    100b: Divide by 16
+                                    101b: Divide by 32
+                                    110b: Divide by 64
+                                    111b: Divide by 128
+   3:2     MS2_DIVBY4[1:0] MS2 Divide by 4 Enable.
+                           11: Divide by 4 enabled.
+                           00: Divide by a value other than 4.
+   1:0       MS2_P1[17:16]          Multisynth2 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth2 divider.
+
+
+
+Register 61. Multisynth2 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS2_P1[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS2_P1[15:8]          Multisynth2 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth2 divider.
+
+
+
+
+40        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 62. Multisynth2 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS2_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS2_P1[7:0]          Multisynth2 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth2 divider.
+
+
+
+Register 63. Multisynth2 Parameters
+
+
+    Bit             D7             D6             D5              D4             D3             D2              D1             D0
+
+   Name                            MS2_P3[19:16]                                                MS2_P2[19:16]
+
+   Type                                   R/W                                                          R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:4       MS2_P3[19:16]          Multisynth2 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the Multisynth2 divider
+  3:0       MS2_P2[19:16]          Multisynth2 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the MultiSynth2 divider.
+
+
+
+Register 64. Multisynth2 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS2_P2[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS2_P2[15:8]          Multisynth2 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the Multisynth2 divider.
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            41
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 65. Multisynth2 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS2_P2[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS2_P2[7:0]          Multisynth2 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the Multisynth2 divider.
+
+
+
+Register 66. Multisynth3 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS3_P3[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS3_P3[15:8]          Multisynth3 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth3 divider.
+
+
+
+Register 67. Multisynth3 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS3_P3[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS3_P3[7:0]          Multisynth3 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth3 divider.
+
+
+
+
+42        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 68. Multisynth3 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2             D1              D0
+
+  Name                                      R3_DIV[2:0]                        MS3_DIVBY4[1:0]                 MS3_P1[17:16]
+
+   Type           R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+   7             Unused
+  6:4         R3_DIV[2:0]          R3 Output Divider.
+                                   000b: Divide by 1
+                                   001b: Divide by 2
+                                   010b: Divide by 4
+                                   011b: Divide by 8
+                                   100b: Divide by 16
+                                   101b: Divide by 32
+                                   110b: Divide by 64
+                                   111b: Divide by 128
+  3:2     MS3_DIVBY4[1:0] MS3 Divide by 4 Enable.
+                          11: Divide by 4 enabled.
+                          00: Divide by a value other than 4.
+  1:0       MS3_P1[17:16]          Multisynth3 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth3 divider.
+
+
+
+Register 69. Multisynth3 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS3_P1[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS3_P1[15:8]          Multisynth3 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth3 divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            43
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 70. Multisynth3 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS3_P1[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS3_P1[7:0]          Multisynth3 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth3 divider.
+
+
+
+Register 71. Multisynth3 Parameters
+
+
+     Bit             D7             D6             D5              D4             D3             D2              D1             D0
+
+   Name                             MS3_P3[19:16]                                                MS3_P2[19:16]
+
+    Type                                   R/W                                                          R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:4       MS3_P3[19:16]          Multisynth3 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth3 divider
+   3:0       MS3_P2[19:16]          Multisynth3 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the MultiSynth3 divider.
+
+
+
+Register 72. Multisynth3 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS3_P2[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS3_P2[15:8]          Multisynth3 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the Multisynth3 divider.
+
+
+
+44        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 73. Multisynth3 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS3_P2[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS3_P2[7:0]          Multisynth3 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the Multisynth3 divider.
+
+
+
+Register 74. Multisynth4 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS4_P3[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS4_P3[15:8]          Multisynth4 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the Multisynth4 divider.
+
+
+
+Register 75. Multisynth4 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS4_P3[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS4_P3[7:0]          Multisynth4 Parameter 3.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the Multisynth4 divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            45
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 76. Multisynth4 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2             D1              D0
+
+   Name                                      R4_DIV[2:0]                        MS4_DIVBY4[1:0]                 MS4_P1[17:16]
+
+    Type           R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+    7             Unused
+   6:4         R4_DIV[2:0]          R4 Output Divider.
+                                    000b: Divide by 1
+                                    001b: Divide by 2
+                                    010b: Divide by 4
+                                    011b: Divide by 8
+                                    100b: Divide by 16
+                                    101b: Divide by 32
+                                    110b: Divide by 64
+                                    111b: Divide by 128
+   3:2     MS4_DIVBY4[1:0] MS4 Divide by 4 Enable.
+                           11: Divide by 4 enabled.
+                           00: Divide by a value other than 4.
+   1:0       MS4_P1[17:16]          Multisynth4 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth4 divider.
+
+
+
+Register 77. Multisynth4 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS4_P1[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS4_P1[15:8]          Multisynth4 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth4 divider.
+
+
+
+
+46        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 78. Multisynth4 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS4_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS4_P1[7:0]          Multisynth4 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth4 divider.
+
+
+
+Register 79. Multisynth4 Parameters
+
+
+    Bit             D7             D6             D5              D4             D3             D2              D1             D0
+
+   Name                            MS4_P3[19:16]                                                MS4_P2[19:16]
+
+   Type                                   R/W                                                          R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:4       MS4_P3[19:16]          Multisynth4 Parameter 3.
+                                   This 20-bit number is an encoded representation of the denominator for the frac-
+                                   tional part of the Multisynth4 divider
+  3:0       MS4_P2[19:16]          Multisynth4 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the MultiSynth4 divider.
+
+
+
+Register 80. Multisynth4 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS4_P2[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS4_P2[15:8]          Multisynth4 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the Multisynth4 Divider.
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            47
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 81. Multisynth4 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS4_P2[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS4_P2[7:0]          Multisynth4 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the Multisynth4 divider.
+
+
+
+Register 82. Multisynth5 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS5_P3[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS5_P3[15:8]          Multisynth5 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth5 divider.
+
+
+
+Register 83. Multisynth5 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS5_P3[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS5_P3[7:0]          Multisynth5 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth5 divider.
+
+
+
+
+48        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 84. Multisynth5 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2             D1              D0
+
+  Name                                      R5_DIV[2:0]                        MS5_DIVBY4[1:0]                 MS5_P1[17:16]
+
+   Type           R/W                            R/W                            R/W            R/W                    R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+   7             Unused
+  6:4         R5_DIV[2:0]          R5 Output Divider.
+                                   000b: Divide by 1
+                                   001b: Divide by 2
+                                   010b: Divide by 4
+                                   011b: Divide by 8
+                                   100b: Divide by 16
+                                   101b: Divide by 32
+                                   110b: Divide by 64
+                                   111b: Divide by 128
+  3:2     MS5_DIVBY4[1:0] MS5 Divide by 4 Enable.
+                          11: Divide by 4 enabled.
+                          00: Divide by a value other than 4.
+  1:0       MS5_P1[17:16]          Multisynth5 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth5 divider.
+
+
+
+Register 85. Multisynth5 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                            MS5_P1[15:8]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0        MS5_P1[15:8]          Multisynth5 Parameter 1.
+                                   This 18-bit number is an encoded representation of the integer part of the Multi-
+                                   synth5 divider.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            49
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 86. Multisynth5 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                             MS5_P1[7:0]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0         MS5_P1[7:0]          Multisynth5 Parameter 1.
+                                    This 18-bit number is an encoded representation of the integer part of the Multi-
+                                    synth5 divider.
+
+
+
+Register 87. Multisynth5 Parameters
+
+
+     Bit             D7             D6             D5              D4             D3             D2              D1             D0
+
+   Name                             MS5_P3[19:16]                                                MS5_P2[19:16]
+
+    Type                                   R/W                                                          R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:4       MS5_P3[19:16]          Multisynth5 Parameter 3.
+                                    This 20-bit number is an encoded representation of the denominator for the frac-
+                                    tional part of the Multisynth5 divider
+   3:0       MS5_P2[19:16]          Multisynth5 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the MultiSynth5 divider.
+
+
+
+Register 88. Multisynth5 Parameters
+
+
+     Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+   Name                                                            MS5_P2[15:8]
+
+    Type                                                                 R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+   7:0        MS5_P2[15:8]          Multisynth5 Parameter 2.
+                                    This 20-bit number is an encoded representation of the numerator for the fractional
+                                    part of the Multisynth5 Divider.
+
+
+
+50        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 89. Multisynth5 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS5_P2[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS5_P2[7:0]          Multisynth5 Parameter 2.
+                                   This 20-bit number is an encoded representation of the numerator for the fractional
+                                   part of the Multisynth5 Divider.
+
+
+
+Register 90. Multisynth6 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS6_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS6_P1[7:0]          Multisynth6 Parameter 1.
+                                   This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be
+                                   even integers greater than or equal to 6. All other divide values are invalid.
+
+
+
+Register 91. Multisynth7 Parameters
+
+
+    Bit            D7             D6              D5             D4              D3             D2              D1             D0
+
+  Name                                                             MS7_P1[7:0]
+
+   Type                                                                 R/W
+Reset value = xxxx xxxx
+
+  Bit             Name                                                          Function
+  7:0         MS7_P1[7:0]          Multisynth7 Parameter 1.
+                                   This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be
+                                   even integers greater than or equal to 6. All other divide values are invalid.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            51
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 92. Clock 6 and 7 Output Divider
+
+
+     Bit            D7             D6              D5             D4              D3             D2             D1              D0
+
+   Name         Reserved                     R7_DIV[2:0]                     Reserved                      R6_DIV[2:0]
+
+    Type           R/W                            R/W                            R/W                            R/W
+Reset value = xxxx xxxx
+
+   Bit             Name                                                          Function
+    7            Reserved           Leave as default.
+   6:4         R7_DIV[2:0]          R7 Output Divider.
+                                    000b: Divide by 1
+                                    001b: Divide by 2
+                                    010b: Divide by 4
+                                    011b: Divide by 8
+                                    100b: Divide by 16
+                                    101b: Divide by 32
+                                    110b: Divide by 64
+                                    111b: Divide by 128
+    3            Reserved           Leave as default.
+   1:0         R6_DIV[2:0]          R6 Output Divider.
+                                    000b: Divide by 1
+                                    001b: Divide by 2
+                                    010b: Divide by 4
+                                    011b: Divide by 8
+                                    100b: Divide by 16
+                                    101b: Divide by 32
+                                    110b: Divide by 64
+                                    111b: Divide by 128
+
+
+
+
+52        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 149. Spread Spectrum Parameters
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+ Name        SSC_EN                                                     SSDN_P2[14:8]
+  Type                                                                 R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+  7           SSC_EN             Spread Spectrum Enable
+                                 1: Enable
+                                 0: Disable
+                                 Note: Spread Spectrum Enable control pin is available on the Si5351A and B devices. Spread
+                                       spectrum enable functionality is a logical OR of the SSEN pin and SSC_EN register bit,
+                                       so for the SSEN pin to work properly, this register bit must be set to 0.
+ 6:0      SSDN_P2[14:8]          PLL A Spread Spectrum Down Parameter 2.
+
+
+Register 150. Spread Spectrum Parameters
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+ Name                                                            SSDN_P2[7:0]
+  Type                                                                 R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+ 7:0       SSDN_P2[7:0]          PLL A Spread Spectrum Down Parameter 2.
+
+
+Register 151. Spread Spectrum Parameters
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name     SSC_MODE                                                       SSDN_P3[14:8]
+ Type                                                                  R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+  7         SSC_MODE             Spread Spectrum Mode.
+                                 0: Down Spread
+                                 1: Center Spread
+ 6:0      SSDN_P3[14:8]          PLL A Spread Spectrum Down Parameter 3.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            53
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 152. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                             SSDN_P3[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0        SSDN_P3[7:0]          PLL A Spread Spectrum Down Parameter 3.
+
+
+Register 153. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                             SSDN_P1[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0        SSDN_P1[7:0]          PLL A Spread Spectrum Down Parameter 1.
+
+
+Register 154. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                              SSUDP[11:8]                                                   SSDN_P1[11:8]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:4        SSUDP[11:8]           PLL A Spread Spectrum Up/Down Parameter.
+ 3:0       SSDN_P1[11:8]          PLL A Spread Spectrum Down Parameter 1.
+
+
+Register 155. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                              SSUDP[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0         SSUDP[7:0]           PLL A Spread Spectrum Up/Down Parameter.
+
+
+54        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 156. Spread Spectrum Parameters
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name        Unused                                                      SSUP_P2[14:8]
+ Type                                                                  R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+  7            Unused            Unused.
+ 6:0      SSUP_P2[14:8]          PLL A Spread Spectrum Up Parameter 2.
+
+
+Register 157. Spread Spectrum Parameters
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                            SSUP_P2[7:0]
+ Type                                                                  R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+ 7:0       SSUP_P2[7:0]          PLL A Spread Spectrum Up Parameter 2.
+
+
+Register 158. Spread Spectrum Parameters
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name        Unused                                                      SSUP_P3[14:8]
+ Type                                                                  R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+  7            Unused            Unused.
+ 6:0      SSUP_P3[14:8]          PLL A Spread Spectrum Up Parameter 3.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            55
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 159. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                             SSUP_P3[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0        SSUP_P3[7:0]          PLL A Spread Spectrum Up Parameter 3.
+
+
+Register 160. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                             SSUP_P1[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0        SSUP_P1[7:0]          PLL A Spread Spectrum Up Parameter 1.
+
+
+Register 161. Spread Spectrum Parameters
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                             SS_NCLK[3:0]                                                   SSUP_P1[11:8]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:4        SS_NCLK[3:0]          Must write 0000b to these bits.
+ 3:0       SSUP_P1[11:8]          PLL A Spread Spectrum Up Parameter 1.
+
+
+Register 162. VCXO Parameter
+
+
+   Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                          VCXO_Param[7:0]
+  Type                                                                  R/W
+Reset value = xxxx xxxx
+
+  Bit            Name                                                           Function
+ 7:0     VCXO_Param[7:0] VCXO Parameter.
+
+
+56        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 163. VCXO Parameter
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                                                        VCXO_Param[15:8]
+ Type                                                                  R/W
+Reset value = xxxx xxxx
+
+ Bit            Name                                                           Function
+ 7:0     VCXO_Param[15:8] VCXO Parameter.
+
+
+Register 164. VCXO Parameter
+
+
+  Bit            D7              D6              D5              D4              D3             D2              D1              D0
+ Name                 Reserved                                               VCXO_Param[21:16]
+  Type                                                                 R/W
+Reset value = xxxx xxxx
+
+ Bit             Name                                                           Function
+ 7:6           Reserved               Reserved. Only write 00b to these bits.
+ 5:0     VCXO_Param[21:16] VCXO Parameter.
+
+
+Register 165. CLK0 Initial Phase Offset
+
+
+   Bit           D7              D6             D5              D4              D3              D2             D1              D0
+ Name                                                                 CLK0_PHOFF[6:0]
+  Type          R/W            R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+ Bit            Name                                                           Function
+  7           Reserved           Only write 0 to this bit.
+ 6:0     CLK0_PHOFF[6:0] Clock 0 Initial Phase Offset.
+                                 CLK0_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                 Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            57
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 166. CLK1 Initial Phase Offset
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+  Name                                                                 CLK1_PHOFF[6:0]
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+  Bit            Name                                                           Function
+   7           Reserved           Only write 0 to this bit.
+ 6:0      CLK1_PHOFF[6:0] Clock 1 Initial Phase Offset.
+                                  CLK1_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                  Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+Register 167. CLK2 Initial Phase Offset
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+  Name                                                                 CLK2_PHOFF[6:0]
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+  Bit            Name                                                           Function
+   7           Reserved           Only write 0 to this bit.
+ 6:0      CLK2_PHOFF[6:0] Clock 2 Initial Phase Offset.
+                                  CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                  Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+Register 168. CLK3 Initial Phase Offset
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+  Name                                                                 CLK3_PHOFF[6:0]
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+  Bit            Name                                                           Function
+   7           Reserved           Only write 0 to this bit.
+  6:0     CLK3_PHOFF[6:0] Clock 3 Initial Phase Offset.
+                                  CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                  Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+
+
+58        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 169. CLK4 Initial Phase Offset
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+ Name                                                                 CLK4_PHOFF[6:0]
+  Type          R/W            R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+ Bit            Name                                                           Function
+  7           Reserved           Only write 0 to this bit.
+ 6:0     CLK4_PHOFF[6:0] Clock 4 Initial Phase Offset.
+                                 CLK4_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                 Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+Register 170. CLK5 Initial Phase Offset
+
+
+   Bit           D7             D6              D5              D4              D3              D2             D1              D0
+ Name                                                                 CLK5_PHOFF[6:0]
+  Type          R/W            R/W             R/W             R/W             R/W            R/W             R/W             R/W
+Reset value = 0000 0000
+
+ Bit            Name                                                           Function
+  7           Reserved           Only write 0 to this bit.
+ 6:0     CLK5_PHOFF[6:0] Clock 5 Initial Phase Offset.
+                                 CLK5_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
+                                 Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            59
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+
+Register 177. PLL Reset
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name      PLLB_RST                        PLLA_RST
+
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+
+Reset value = 0000 0000
+
+  Bit        Name                                                           Function
+
+   7      PLLB_RST PLLB_Reset.
+                          Writing a 1 to this bit will reset PLLB. This is a self clearing bit.
+
+   6       Reserved       Leave as default.
+
+   5      PLLA_RST PLLA_Reset.
+                          Writing a 1 to this bit will reset PLLA. This is a self clearing bit.
+
+  4:0      Reserved       Leave as default.
+
+
+Register 183. Crystal Internal Load Capacitance
+
+
+    Bit           D7             D6              D5              D4              D3              D2             D1              D0
+
+  Name             XTAL_CL[1:0]
+
+   Type         R/W             R/W             R/W             R/W             R/W            R/W             R/W             R/W
+
+Reset value = 11xx xxxx
+
+  Bit         Name                                                           Function
+
+  7:6     XTAL_CL[1:0] Crystal Load Capacitance Selection.
+                             These 2 bits determine the internal load capacitance value for the crystal. See the Crystal
+                             Inputs section in the Si5351 data sheet.
+                             00: Reserved. Do not select this option.
+                             01: Internal CL = 6 pF.
+                             10: Internal CL = 8 pF.
+                             11: Internal CL = 10 pF (default).
+
+  5:0       Reserved         Bits 5:0 should be written to 010010b.
+
+
+
+
+60        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+                                                                                                                       AN619
+
+Register 187. Fanout Enable
+
+
+   Bit           D7              D6             D5              D4              D3              D2              D1             D0
+
+ Name      CLKIN_FA- XO_FA-                 Reserved        MS_FA-                                   Reserved
+           NOUT_EN NOUT_EN                                 NOUT_EN
+
+  Type          R/W             R/W            R/W             R/W             R/W             R/W             R/W            R/W
+
+Reset value = xxxx xxxx
+
+  Bit        Name                                                           Function
+
+   7      CLKIN_FA-         Enable fanout of CLKIN to clock output multiplexers. Set this bit to 1b.
+          NOUT_EN
+
+   6        XO_FA-          Enable fanout of XO to clock output multiplexers. Set this bit to 1b.
+           NOUT_EN
+
+   5       Reserved         Reserved.
+
+   4        MS_FA-          Enable fanout of Multisynth0 and Multisynth4 to all output multiplexers. Set this bit to 1b.
+           NOUT_EN
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com            61
+Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+AN619
+DOCUMENT CHANGE LIST                                                     Updated Register 36 description
+                                                                      Revision 0.7 to Revision 0.8
+Revision 0.1 to Revision 0.2
+                                                                         Updated to include ClockBuilder Pro
+   Corrected Typos
+                                                                         Clarified 10-MSOP and 20-QFN package coverage
+    Feedback fractional divide value can be up to 90 (not
+      900).                                                              Added reference to AN1234 for 16-QFN
+    Corrected miscellaneous typographical errors.
+                                                                          Programming Instructions
+ Added note to “3.2. Feedback Multisynth Divider                        Updated Section "8.1. Register Map Summary" on
+  Equations” to set MSNB a + b/c divide ratio such that                   page 10.
+  c = 106 when using VCXO equations in this                              Cleaned up register descriptions
+  document.
+ Added Figure 2.
+
+Revision 0.2 to Revision 0.3
+ Updated first bullet in “Section 5. Configuring Spread
+  Spectrum Register Parameters.”
+ Updated “Section 8.1 Register Map Summary.”
+ Updated Register 183.
+
+Revision 0.3 to Revision 0.4
+ Corrected typographic error in maximum spread
+  spectrum percentage for center spread on page 8.
+ Added rounding operator for up spread depth
+  calculation on page 9.
+ Corrected register description errata on pages 11,13,
+  31, and 32.
+Revision 0.4 to Revision 0.5
+ Updated “8.1. Register Map Summary”.
+ Updated “6. Configuring Initial Phase Offset Register
+  Parameters”.
+ Corrected Register 16 description.
+
+Revision 0.5 to Revision 0.6
+   Updated “8.1. Register Map Summary”.
+   Corrected Register 161 description.
+Revision 0.6 to Revision 0.7
+   Corrected Typo in Section “3.1.2. CMOS Clock
+    Source”
+   Corrected Typo in Section “3.2. Feedback Multisynth
+    Divider Equations” Now c = 10^6
+   Removed Section 3.3. Miscellaneous PLL
+    Parameters.
+   Fixed minor typos in Section “5. Configuring Spread
+    Spectrum Register Parameters”
+   Corrected Register 36 fields in Section "“8.1.
+    Register Map Summary”.
+   Updated Register 0 description to include the
+    Revision ID.
+   Fixed Register 32 Register Name
+
+
+62        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+ Rev. 0.8 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 23, 2021
+     ClockBuilder Pro
+     Customize Skyworks clock generators,
+     jitter attenuators and network
+     synchronizers with a single tool. With
+     CBPro you can control evaluation
+     boards, access documentation, request
+     a custom part number, export for
+     in-system programming and more!
+
+
+     www.skyworksinc.com/CBPro
+
+
+
+
+                    Portfolio                           SW/HW                               Quality                     Support & Resources
+         www.skyworksinc.com/ia/timing        www.skyworksinc.com/CBPro           www.skyworksinc.com/quality         www.skyworksinc.com/support
+
+
+Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.
+Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the
+information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer.
+Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation,
+products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or
+information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
+
+No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability
+for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or
+materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.
+
+THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR
+OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY
+INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR
+COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR
+ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT
+LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT
+OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks
+products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such
+applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.
+
+Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of
+design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating
+safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any
+equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.
+
+Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or
+registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for
+identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at
+www.skyworksinc.com, are incorporated by reference.
+
+
+                          Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com
+                            USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |
+
\ No newline at end of file
diff --git a/tests/regression/python/ref/datasheet.txt b/tests/regression/python/ref/datasheet.txt
new file mode 100644
index 0000000..88c8208
--- /dev/null
+++ b/tests/regression/python/ref/datasheet.txt
@@ -0,0 +1,2530 @@
+                                                                                Si5351A/B/C-B
+I 2 C - P R O G R A M M A B L E A NY -F R E Q U E N C Y C M O S C L O C K
+G E N E R ATO R + V C X O
+
+Features
+    https://www.skyworksinc.com/Products/Timi Glitchless frequency changes
+     ng/CMOS-Clock-Generators                                                                                  10-MSOP
+                                               Separate voltage supply pins
+    Generates up to eight non-integer-                provide level translation:
+     related frequencies from 2.5 kHz to
+                                                      Core VDD: 2.5 or 3.3 V
+     200 MHz
+                                                      Output VDDO: 1.8, 2.5, or 3.3 V
+    I2C user definable configuration                 Excellent PSRR eliminates external
+    Exact frequency synthesis at each                 power supply filtering
+     output (0 ppm error)                             Very low power consumption
+    Highly linear VCXO                                                                                         16-QFN
+                                                      Adjustable output delay
+    Optional clock input (CLKIN)                     Available in three packages types:
+    Low output period jitter: < 70 ps pp,            10-MSOP: 3 outputs
+     typ
+                                                      16-QFN (3x3 mm): 4 outputs
+    Configurable spread spectrum
+                                                      20-QFN (4x4 mm): 8 outputs
+     selectable at each output
+                                                      PCIE Gen 1 compatible
+    Operates from a low-cost, fixed
+     frequency crystal: 25 or 27 MHz                  Supports HCSL compatible swing                          20-QFN
+
+    Supports static phase offset
+    Programmable rise/fall time control
+
+Applications
+ Audio/video equipment, gaming                     Residential gateways
+ Printers, scanners, projectors                    Networking/communication
+ Handheld Instrumentation                          Servers, storage                                    Ordering Information:
+ Laser range finder                                XO replacement                                          See page 34
+
+Description
+
+The Si5351 is an I2C configurable clock generator that is ideally suited for
+replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and
+fanout buffers in cost-sensitive applications.
+Based on a PLL/VCXO + high resolution MultiSynth fractional divider
+architecture, the Si5351 can generate any frequency up to 200 MHz on each of
+its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a
+wide variety of applications.
+The Si5351A generates up to 8 free-running clocks using an internal oscillator
+for replacing crystals and crystal oscillators. The Si5351B adds an internal
+VCXO and provides the flexibility to replace both free-running clocks and
+synchronous clocks. It eliminates the need for higher cost, custom pullable
+crystals while providing reliable operation over a wide tuning range. The
+Si5351C offers the same flexibility but synchronizes to an external reference
+clock (CLKIN).
+
+
+
+
+           Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+    Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+Functional Block Diagrams
+
+
+
+
+                                        Si5351A (20-QFN)
+                                                                        MultiSynth                     VDDOA
+                                 XA                    PLL                            R0
+                                            OSC                              0                          CLK0
+                                                        A
+                                 XB                                     MultiSynth                      CLK1
+                                                                                      R1
+                                                                             1
+                                                        PLL             MultiSynth                     VDDOB
+                                                         B                            R2
+                                                                             2                          CLK2
+                                                                        MultiSynth                      CLK3
+                                                                                      R3
+                                                                             3
+                                  A0                                                                   VDDOC
+                                                                        MultiSynth
+                                                                                      R4
+                                SDA           I2C                            4                          CLK4
+                                                                        MultiSynth                      CLK5
+                                SCL                                                   R5
+                                                                             5
+                                                                        MultiSynth                     VDDOD
+                                OEB                                                   R6
+                                            Control                          6                          CLK6
+                               SSEN          Logic                      MultiSynth                      CLK7
+                                                                                      R7
+                                                                             7
+
+
+
+
+                                       Si5351B (20-QFN)
+                                                                         MultiSynth                     VDDOA
+                                 XA                                                   R0
+                                                                              0                          CLK0
+                                            OSC        PLL
+                                                                         MultiSynth                      CLK1
+                                 XB                                                   R1
+                                                                              1
+                                                                         MultiSynth                     VDDOB
+                                                       VCXO                           R2
+                                                                              2                          CLK2
+                                 VC
+                                                                         MultiSynth                      CLK3
+                                                                                      R3
+                                                                              3
+                                                                        MultiSynth                      VDDOC
+                               SDA                                                    R4
+                                                                             4                           CLK4
+                                              I2C
+                                SCL                                     MultiSynth                       CLK5
+                                                                                      R5
+                                                                             5
+                                                                                                        VDDOD
+                                                                        MultiSynth
+                                OEB         Control                                   R6
+                                                                             6                           CLK6
+                              SSEN           Logic
+                                                                        MultiSynth                       CLK7
+                                                                                      R7
+                                                                             7
+
+
+
+
+2          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+    Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                              Si5351A/B/C-B
+
+                               Si5351C (20-QFN)
+                                                                                                  VDDOA
+                                                                   MultiSynth
+                        XA                                                       R0
+                                                                        0                         CLK0
+                                   OSC           PLL
+                                                  A                MultiSynth                     CLK1
+                        XB                                                       R1
+                                                                        1
+                                                                   MultiSynth                     VDDOB
+                                                 PLL                             R2
+                                                                        2                         CLK2
+                     CLKIN                        B
+                                                                   MultiSynth                     CLK3
+                                                                                 R3
+                                                                        3
+                                                                                                  VDDOC
+                                                                   MultiSynth
+                       SDA                                                       R4
+                                                                        4                         CLK4
+                       SCL           I2C                           MultiSynth                     CLK5
+                                                                                 R5
+                                                                        5
+                      INTR                                                                        VDDOD
+                                                                   MultiSynth
+                                                                                 R6
+                                                                        6                         CLK6
+                       OEB         Control
+                                    Logic                          MultiSynth                     CLK7
+                                                                                 R7
+                                                                        7
+
+
+
+                                Si5351A (16-QFN)
+                          XA                                                                    VDDOA
+                                                PLL              MultiSynth
+                                                                                R0              CLK0
+                                    OSC          A                    0
+                          XB                                                                    VDDOB
+                                                                 MultiSynth
+                                                                                R1              CLK1
+                                                                      1
+                                                PLL
+                         A0                      B              MultiSynth                      VDDOC
+                                                                                R2              CLK2
+                        SDA          I 2C                            2
+                        SCL                                                                     VDDOD
+                                                                MultiSynth
+                                                                                R3              CLK3
+                                                                     3
+                        OEB         Control
+                                     Logic
+
+
+
+
+                               Si5351B (16-QFN)
+                        XA                                                                        VDDOA
+                                               PLL               MultiSynth
+                                                                                R0                CLK0
+                                   OSC          A                     0
+                        XB                                                                        VDDOB
+                                                                 MultiSynth
+                                                                                R1                CLK1
+                                                                      1
+                                               vcxo
+                        VC                                                                        VDDOC
+                                                                 MultiSynth
+                                                                                R2                CLK2
+                      SDA            2
+                                                                      2
+                                    IC                                                            VDDOD
+                      SCL                                        MultiSynth
+                                                                                R3                CLK3
+                                                                      3
+                      OEB          Control
+                                    Logic
+
+
+
+
+                               Si5351C (16-QFN)
+
+                         XA                                                                       VDDOA
+                                                  PLL              MultiSynth
+                                                                                     R0           CLK0
+                                    OSC            A                    0
+                         XB                                                                       VDDOB
+                                                                   MultiSynth
+                                                                                     R1           CLK1
+                                                                        1
+                      CLKIN                        PLL
+                                                    B              MultiSynth                     VDDOC
+                                                                                     R2           CLK2
+                        SDA              2                              2
+                                     IC                                                           VDDOD
+                        SCL                                        MultiSynth
+                                                                                     R3           CLK3
+                                    Control                             3
+                        OEB
+                                     Logic
+
+
+
+
+       Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             3
+Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+   Si5351A/B/C-B
+   1. Ordering Guide
+
+                                                Table 1. Si5350/51 Ordering Guide1,2
+
+       Part Number             I2C or Pin       Frequency Reference                    Programmed?                  Outputs        Datasheet
+
+       Si5351A-B-GT                 I2C                XTAL only                             Blank                      3       Si5351A/B/C-B
+
+   Si5351A-B-GM1                    I2C                XTAL only                             Blank                      4       Si5351A/B/C-B
+
+   Si5351B-B-GM1                    I2C          XTAL and/or Voltage                         Blank                      4       Si5351A/B/C-B
+
+   Si5351C-B-GM1                    I2C           XTAL and/or CLKIN                          Blank                      4       Si5351A/B/C-B
+
+    Si5351A-B-GM                    I2C                XTAL only                             Blank                      8       Si5351A/B/C-B
+
+    Si5351B-B-GM                    I2C          XTAL and/or Voltage                         Blank                      8       Si5351A/B/C-B
+
+    Si5351C-B-GM                    I2C           XTAL and/or CLKIN                          Blank                      8       Si5351A/B/C-B
+
+ Si5351A-Bxxxxx-GT                  I2C                XTAL only                 Factory Preprogrammed                  3       Si5351A/B/C-B
+
+Si5351A-Bxxxxx-GM1                  I2C                XTAL only                 Factory Preprogrammed                  4       Si5351A/B/C-B
+
+Si5351B-Bxxxxx-GM1                  I2C          XTAL and/or Voltage             Factory Preprogrammed                  4       Si5351A/B/C-B
+
+Si5351C-Bxxxxx-GM1                  I2C           XTAL and/or CLKIN              Factory Preprogrammed                  4       Si5351A/B/C-B
+
+ Si5351A-Bxxxxx-GM                  I2C                XTAL only                 Factory Preprogrammed                  8       Si5351A/B/C-B
+
+ Si5351B-Bxxxxx-GM                  I2C          XTAL and/or Voltage             Factory Preprogrammed                  8       Si5351A/B/C-B
+
+ Si5351C-Bxxxxx-GM                  I2C           XTAL and/or CLKIN              Factory Preprogrammed                  8       Si5351A/B/C-B
+
+ Si5350A-Bxxxxx-GT                  Pin                XTAL only                 Factory Preprogrammed                  3          Si5350A-B
+
+Si5350A-Bxxxxx-GM1                  Pin                XTAL only                 Factory Preprogrammed                  4          Si5350A-B
+
+ Si5350A-Bxxxxx-GM                  Pin                XTAL only                 Factory Preprogrammed                  8          Si5350A-B
+
+ Si5350B-Bxxxxx-GT                  Pin          XTAL and/or Voltage             Factory Preprogrammed                  3          Si5350B-B
+
+Si5350B-Bxxxxx-GM1                  Pin          XTAL and/or Voltage             Factory Preprogrammed                  4          Si5350B-B
+
+ Si5350B-Bxxxxx-GM                  Pin          XTAL and/or Voltage             Factory Preprogrammed                  8          Si5350B-B
+
+ Si5350C-Bxxxxx-GT                  Pin           XTAL and/or CLKIN              Factory Preprogrammed                  3          Si5350C-B
+
+Si5350C-Bxxxxx-GM1                  Pin           XTAL and/or CLKIN              Factory Preprogrammed                  4          Si5350C-B
+
+ Si5350C-Bxxxxx-GM                  Pin           XTAL and/or CLKIN              Factory Preprogrammed                  8          Si5350C-B
+
+Notes:
+   1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
+   2. Create custom, factory preprogrammed parts using ClockBuilder Pro.
+
+
+
+
+   4           Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+        Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                               Si5351A/B/C-B
+2. Technical Support Resources
+
+                                        Table 2. Technical Support Resources
+
+                   Resource                                                                URL
+
+ Si5350/51 Frequently Asked Questions                https://www.skyworksinc.com/en/Products/Timing
+
+                                                     https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-
+    ClockBuilder Pro (CBPro) Software
+                                                     Pro-Software
+
+                                                     https://www.skyworksinc.com/en/Products/Timing/Evaluation-
+          Si535x Development Kits
+                                                     Kits/si535x-b20qfn-evb-evaluation-kit
+
+
+
+
+        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             5
+ Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+TA B L E O F C O N T E N T S
+
+Section                                                                                                                           Page
+1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
+2. Technical Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
+3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
+4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
+      4.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
+      4.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
+      4.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
+      4.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
+      4.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
+      4.6. Status Pins (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
+5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
+6. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
+      6.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
+      6.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
+      6.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
+      6.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .22
+      6.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 23
+      6.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
+      6.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
+7. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
+      7.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
+      7.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
+      7.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
+      7.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
+      7.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
+      7.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
+8. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
+9. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
+10. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
+      10.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
+      10.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
+      10.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
+      10.4. Si5351A 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
+      10.5. Si5351B 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
+      10.6. Si5351C 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
+      10.7. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
+11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
+12. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
+      12.1. 20-pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
+      12.2. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
+      12.3. 16-Pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
+      12.4. Land Pattern: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
+
+
+6          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+    Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                Si5351A/B/C-B
+     12.5. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
+     12.6. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
+13. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
+     13.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
+     13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
+     13.3. 16-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
+     13.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
+     13.5. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
+     13.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
+Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
+Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             7
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+3. Electrical Specifications
+
+Table 3. Recommended Operating Conditions
+
+          Parameter                 Symbol          Test Condition            Min              Typ               Max            Unit
+
+Ambient Temperature                     TA                                    –40               25               85              °C
+
+                                                                               3.0             3.3               3.60             V
+Core Supply Voltage                    VDD
+                                                                              2.25             2.5               2.75             V
+
+                                                                              1.71             1.8               1.89             V
+
+Output Buffer Voltage                 VDDOx                                   2.25             2.5               2.75             V
+
+                                                                               3.0             3.3               3.60             V
+
+Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
+      Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
+      VDD and VDDOx can be operated at independent voltages.
+      Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same
+      time as VDD.
+
+
+Table 4. DC Characteristics
+(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
+
+              Parameter                      Symbol             Test Condition                 Min        Typ           Max      Unit
+                                                               Enabled 3 outputs                —          22           35        mA
+Core Supply Current                           IDD              Enabled 4 outputs                —          24           38        mA
+                                                               Enabled 8 outputs                —          27           45        mA
+Output Buffer Supply Current
+                                             IDDOx                  CL = 5 pF                   —          2.2          5.6       mA
+(Per Output)*
+                                                               CLKIN, SDA, SCL
+                                             ICLKIN                                             —          —            10        µA
+Input Current                                                    Vin < 3.6 V
+                                              IVC                       VC                      —          —            30        µA
+                                                           3.3 V VDDO, default high
+Output Impedance                               ZO                                               —          50           —          
+                                                                    drive
+*Note: Output clocks less than or equal to 100 MHz.
+
+
+
+
+8          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+    Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                Si5351A/B/C-B
+
+Table 5. AC Characteristics
+(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
+
+            Parameter                     Symbol                  Test Condition                   Min      Typ        Max      Unit
+                                                           From VDD = VDDmin to valid
+Power-up Time                              TRDY              output clock, CL = 5 pF,               —         2         10       ms
+                                                                 fCLKn > 1 MHz
+                                                           From VDD = VDDmin to valid
+Power-up Time, PLL Bypass
+                                           TBYP              output clock, CL = 5 pF,               —        0.5        1        ms
+Mode
+                                                                 fCLKn > 1 MHz
+                                                          From OEB pulled low to valid
+Output Enable Time                          TOE              clock output, CL = 5 pF,               —        —          10       µs
+                                                                  fCLKn > 1 MHz
+Output Frequency Transition
+                                           TFREQ                   fCLKn > 1 MHz                    —        —          10       µs
+Time
+Output Phase Offset                        PSTEP                                                    —       333         —     ps/step
+                                                       Down spread. Selectable in 0.1%
+                                                                                                   –0.1      —         –2.5       %
+Spread Spectrum Frequency                                          steps.
+                                          SSDEV
+Deviation                                                 Center spread. Selectable in
+                                                                                                   ±0.1      —         ±1.5       %
+                                                                  0.1% steps.
+Spread Spectrum Modulation                SSMOD                                                     30      31.5        33      kHz
+Rate
+VCXO Specifications (Si5351B Only)
+VCXO Control Voltage Range                     Vc                                                    0     VDD/2       VDD          V
+VCXO Gain (configurable)                       Kv      Vc = 10–90% of VDD, VDD = 3.3 V              18       —         150     ppm/V
+VCXO Control Voltage Linearity              KVL                Vc = 10–90% of VDD                   –5       —         +5         %
+VCXO Pull Range
+                                               PR                  VDD = 3.3 V*                     ±30       0        ±240     ppm
+(configurable)
+VCXO Modulation Bandwidth                                                                           —        10         —       kHz
+*Note: Contact Skyworks Solutions for 2.5 V VCXO operation.
+
+Table 6. Input Clock Characteristics
+(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
+
+          Parameter                   Symbol         Test Condition             Min            Typ             Max            Unit
+
+Crystal Frequency                       fXTAL                                    25             —                 27          MHz
+
+CLKIN Input Low Voltage                  VIL                                   –0.1             —          0.3 x VDD            V
+
+CLKIN Input High Voltage                 VIH                                0.7 x VDD           —              3.60             V
+
+CLKIN Frequency Range                  fCLKIN                                    10             —              100            MHz
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             9
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+Table 7. Output Clock Characteristics
+(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
+
+             Parameter                  Symbol               Test Condition                   Min         Typ        Max          Unit
+
+ Frequency Range1                         FCLK                                              0.0025         —          200         MHz
+
+ Load Capacitance                          CL                                                  —           —          15           pF
+
+                                                      FCLK < 160 MHz, Measured
+                                                                                               45          50         55            %
+                                                               at VDD/2
+ Duty Cycle                                DC
+                                                      FCLK > 160 MHz, Measured
+                                                                                               40          50         60            %
+                                                               at VDD/2
+
+                                            tr           20%–80%, CL = 5 pF,                   —            1         1.5           ns
+ Rise/Fall Time
+                                            tf         Default high drive strength             —            1         1.5           ns
+
+ Output High Voltage                      VOH                                              VDD – 0.6       —           —            V
+                                                                 CL = 5 pF
+ Output Low Voltage                       VOL                                                  —           —          0.6           V
+
+                                                       16, 20-QFN, 4 outputs run-
+                                                                                               —           40         95       ps, pk-pk
+                                                            ning, 1 per VDDO
+ Period Jitter2,3                         JPER
+                                                          10-MSOP or 20-QFN,
+                                                                                               —           70         155      ps, pk-pk
+                                                           all outputs running
+
+                                                       16, 20-QFN, 4 outputs run-
+                                                                                               —           50         90         ps, pk
+                                                            ning, 1 per VDDO
+ Cycle-to-Cycle Jitter2,3                 JCC
+                                                          10-MSOP or 20-QFN,
+                                                                                               —           70         150        ps, pk
+                                                           all outputs running
+
+                                                       16, 20-QFN, 4 outputs run-
+                                                                                               —           50         95       ps, pk-pk
+                                                            ning, 1 per VDDO
+ Period Jitter VCXO2,3                JPER_VCXO
+                                                          10-MSOP or 20-QFN,
+                                                                                               —           70         155      ps, pk-pk
+                                                           all outputs running
+
+                                                       16, 20-QFN, 4 outputs run-
+                                                                                               —           50         90         ps, pk
+                                                            ning, 1 per VDDO
+ Cycle-to-Cycle Jitter
+                                       JCC_VCXO
+ VCXO2,3                                                  10-MSOP or 20-QFN,
+                                                                                               —           70         150        ps, pk
+                                                           all outputs running
+
+ Notes:
+    1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
+    2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50  output impedance).
+    3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
+        frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
+        outputs of 74.25, 24.576, and 48 MHz. Eight-output 20-QFN package measured with clock outputs of 33.333, 74.25,
+        27, 24.576, 22.5792, 28.322, 125, and 48 MHz. Four-output 16-QFN package measured with clock outputs of 33.333,
+        27, 28.322, and 48 MHz.
+
+
+
+
+10          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+
+Table 8. Crystal Requirements1,2
+
+              Parameter                          Symbol                  Min               Typ              Max               Unit
+
+ Crystal Frequency                                 fXTAL                  25               —                 27               MHz
+
+ Load Capacitance                                    CL                   6                 —                12                pF
+
+ Equivalent Series Resistance                      rESR                   —                 —               150                W
+
+ Crystal Max Drive Level                             dL                  100                —                —                µW
+
+ Notes:
+    1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
+        optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
+        combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
+        capacitors on XA and XB).
+    2. Refer to “AN551: Crystal Selection Guide” for more details.
+
+
+Table 9. I2C Specifications (SCL,SDA)1
+
+                                                                  Standard Mode                            Fast Mode
+   Parameter        Symbol         Test Condition                                                                                    Unit
+                                                                     100 kbps                               400 kbps
+                                                                 Min               Max               Min               Max
+LOW Level
+                      VILI2C                                     –0.5          0.3 x VDDI2C          –0.5         0.3 x VDDI2C2       V
+Input Voltage
+HIGH Level
+                      VIHI2C                                0.7 x VDDI2C           3.6          0.7 x VDDI2C2           3.6           V
+Input Voltage
+Hysteresis of
+Schmitt Trigger       VHYS                                        —                 —                0.1                —             V
+Inputs
+LOW Level
+Output Voltage
+(open drain or       VOLI2C2     VDDI2C2 = 2.5/3.3 V               0               0.4                0                 0.4           V
+open collector)
+at 3 mA Sink
+Current
+Input Current          III2C                                     –10                10               –10                10           µA
+Capacitance for
+                      CII2C      VIN = –0.1 to VDDI2C             —                 4                 —                  4           pF
+Each I/O Pin
+I2C Bus
+                       TTO         Timeout Enabled                25                35                25                35           ms
+Timeout
+Notes:
+   1. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03.
+   2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             11
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+Table 10. Thermal Characteristics (2-Layer Board)
+
+            Parameter                    Symbol           Test Condition             Package               Value                Unit
+
+                                                                                     10-MSOP                150                °C/W
+Thermal Resistance
+                                            JA                Still Air1             16-QFN                103                °C/W
+Junction to Ambient
+                                                                                      20-QFN                74.9               °C/W
+
+                                                                                     10-MSOP                 82                °C/W
+Thermal Resistance
+                                           ΨJB                 Still Air1             16-QFN                 37                °C/W
+Junction to Board
+                                                                                      20-QFN                9.94               °C/W
+
+                                                                                     10-MSOP                0.84               °C/W
+Thermal Resistance
+                                            ΨJT                Still Air1             16-QFN                4.26               °C/W
+Junction to Top Center
+                                                                                      20-QFN                 1.3               °C/W
+
+Notes:
+   1. Based on environment and board designed per JESD51-2A and JESD51-3.
+
+
+
+Table 11. Thermal Characteristics (4-Layer Board)
+
+            Parameter                    Symbol           Test Condition             Package               Value                Unit
+
+                                                                                     10-MSOP                126                °C/W
+Thermal Resistance                          JA                Still Air1             16-QFN                 65                °C/W
+Junction to Ambient
+                                                                                      20-QFN                 41                °C/W
+
+                                                                                     10-MSOP                 84                °C/W
+
+                                            JB          Junction to Board2           16-QFN                 48                °C/W
+
+                                                                                      20-QFN                 16                °C/W
+Thermal Resistance
+Junction to Board                                                                    10-MSOP                 83                °C/W
+
+                                           ΨJB                 Still Air1             16-QFN                 31                °C/W
+
+                                                                                      20-QFN                 8.1               °C/W
+
+                                                                                     10-MSOP                0.74               °C/W
+Thermal Resistance
+                                            ΨJT                Still Air1             16-QFN                 3.8               °C/W
+Junction to Top Center
+                                                                                      20-QFN                0.98               °C/W
+Notes:
+   1. Based on environment and board designed per JESD51-2A, JESD51-5, and JESD51-7.
+   2. Based on conditions set in JESD51-8.
+
+
+
+
+12          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+
+Table 12. Thermal Characteristics (Junction-to-Case)
+
+         Parameter                    Symbol            Test Condition            Package               Value                Unit
+
+                                                                                  10-MSOP                 36                °C/W
+Thermal Resistance
+                                         JC                 Still Air             16-QFN                 82                °C/W
+Junction to Case1
+                                                                                   20-QFN                 51                °C/W
+
+Notes:
+   1. Based on board designed per JESD51-1 (Top center of packages used).
+
+
+
+
+Table 13. Absolute Maximum Ratings1
+
+              Parameter                        Symbol              Test Condition                    Value                   Unit
+
+DC Supply Voltage                              VDD_max                                            –0.5 to 3.8                  V
+
+                                               VIN_CLKIN          CLKIN, SCL, SDA                 –0.5 to 3.8                  V
+
+Input Voltage                                   VIN_VC                     VC                –0.5 to (VDD+0.3)                 V
+
+                                               VIN_XA/B              Pins XA, XB                 –0.5 to 1.3 V                 V
+
+Junction Temperature                               TJ                                             –55 to 150                  °C
+
+Soldering Temperature
+                                                TPEAK                                                 260                     °C
+(Pb-free profile)2
+Soldering Temperature Time at
+                                                   TP                                                20–40                   Sec
+TPEAK (Pb-free profile)2
+Notes:
+   1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
+       restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
+       rating conditions for extended periods may affect device reliability.
+   2. The device is compliant with JEDEC J-STD-020.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             13
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+4. Functional Description
+The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal
+oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
+Figure 1. The device consists of an input stage, two synthesis stages, and an output stage.
+The input stage accepts an external crystal (XTAL), a control voltage input (VC), or a clock input (CLKIN)
+depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
+high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
+dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
+generating output frequencies as low as 2.5 kHz. Crosspoint switches at each of the synthesis stages allows total
+flexibility in routing any of the inputs to any of the outputs.
+Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
+synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
+synthesize clocks for multiple clock domains in a design.
+
+                              Input          Synthesis              Synthesis                     Output
+                              Stage           Stage 1                Stage 2                      Stage
+
+                                                                        Multi                                    VDDOA
+                                                                        Synth                R0
+                                                                          0                                      CLK0
+                                                                        Multi                                    CLK1
+                                                                        Synth                R1
+               CLKIN           Div                                        1
+                                                  PLL A
+                                                                        Multi                                    VDDOB
+                                                  (SSC)
+                                                                        Synth                R2
+                         XA                                               2                                      CLK2
+                                                   PLL B                Multi                                    CLK3
+                                                  (VCXO)                Synth                R3
+             XTAL             OSC                                         3
+                                                                        Multi                                    VDDOC
+                         XB                                             Synth                R4
+                                                                          4                                      CLK4
+                                                                        Multi                                    CLK5
+                                                                        Synth                R5
+                                                                          5
+                    VC        VCXO                                      Multi                                    VDDOD
+                                                                        Synth                R6
+                                                                          6                                      CLK6
+                                                                        Multi                                    CLK7
+                                                                        Synth                R7
+                                                                          7
+
+
+
+
+                                                 Figure 1. Si5351 Block Diagram
+
+
+
+
+14          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                    Si5351A/B/C-B
+4.1. Input Stage
+4.1.1. Crystal Inputs (XA, XB)
+The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
+the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
+asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
+27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
+Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to
+the Si5351. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8, or 10 pF. Crystals with
+alternate load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by
+using  4 pF capacitors on XA and XB) as shown in Figure 2. Refer to application note AN551 for crystal
+recommendations.
+
+
+                                                         XA
+
+
+
+
+                                                         XB
+
+                                       Optional additional                      Optional internal
+                                         external load                         load capacitance
+                                          capacitance                            0, 6, 8,10 pF
+                                            (< 2 pF)
+
+                             Figure 2. External XTAL with Optional Load Capacitors
+4.1.2. External Clock Input (CLKIN)
+The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
+CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
+30 MHz.
+4.1.3. Voltage Control Input (VC)
+The VCXO architecture of the Si5351B eliminates the need for an external pullable crystal. Only a standard, low-
+cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
+The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
+VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
+reliable startup and operation. Refer to Table 5 on page 9 for VCXO specification details.
+A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
+voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
+reference. An example is illustrated in Figure 3 on page 16.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             15
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+4.2. Synthesis Stages
+The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
+the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
+resolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies
+above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
+(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
+125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
+(CLKS4-7).
+A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
+This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
+clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
+stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
+any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
+spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
+All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO
+output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input. An
+interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This
+creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 3.
+Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth (see
+Figure 3 below).
+
+                                                                     Fixed Frequency
+                                                  XA          XB
+                                                                   Crystal (non-pullable)
+
+
+                                                                           Multi                     The clock frequency
+                                                       OSC                 Synth       R0   CLK0    generated from CLK0 is
+                                                                             0
+                                                                                                   controlled by the VC input
+
+                                     Control VC                            Multi
+                                                       VCXO                Synth       R1   CLK1
+                                     Voltage                                 1
+
+                                                                                                     Additional MultiSynths
+                                                                           Multi                     can be “linked” to the
+                                                                           Synth       R2   CLK2
+                                                                             2                        VCXO to generate
+                                                                                                       additional clock
+                                                                                                          frequencies
+
+
+
+
+                                   Figure 3. Using the Si5351 as a Multi-Output VCXO
+
+
+
+
+16          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+4.3. Output Stage
+An additional level of division (R) is available at the output stage for generating clocks as low as 2.5 kHz. All output
+drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
+signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
+4.4. Spread Spectrum
+Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
+useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
+frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
+available on clocks synchronized to PLLB or to the VCXO.
+Spread spectrum can be set to “Always Enabled” when creating a custom part in ClockBuilder Pro. The Si5351A/B
+variants also have a SSEN control pin. See "4.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B Only"
+on page 17 for more details.
+The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
+between system performance and EMI compliance.
+
+
+                                                   Reduced                                   Reduced
+                   Center
+                                                   Amplitude                                 Amplitude
+                 Frequency
+                                                    and EMI                                   and EMI
+                 Amplitude
+
+
+
+
+                             fc                                     fc                                        fc
+                         No Spread
+                                                               Center Spread                              Down Spread
+                         Spectrum
+                                     Figure 4. Available Spread Spectrum Profiles
+4.5. Control Pins (OEB, SSEN)
+The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
+4.5.1. Output Enable (OEB)
+The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
+held low, and disabled when pulled high. When disabled, the output state is configurable as output high, output low,
+or high-impedance.
+The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
+edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
+going into a disabled state.
+
+4.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B Only
+This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
+spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
+evaluating the effect of using spread spectrum clocks during EMI compliance testing.
+4.6. Status Pins (INTR)
+The Si5351C, in the 20-QFN package, includes an interrupt pin (INTR). This is an open drain status pin, requiring a
+4.7 k pullup resistor to Vdd. The pin will be pulled low when the Si5351C encounters an interrupt, such as crystal
+reference loss, external input clock loss, or loss-of-lock on either PLLA or PLLB.
+ClockBuilder Pro will automatically configure the interrupt mask when a frequency plan is created, so irrelevant
+interrupts are ignored. For example, if a frequency plan does not use PLLB, the LOL_B interrupt will not cause the
+INTR pin to go low. The interrupt status registers can be viewed at any time through I2C to get more details on the
+type of interrupt thrown. For more information on the status registers and the mask registers, see “AN619:
+Manually Generating an Si5351 Register Map” for 10MSOP and 20-QFN devices” or “AN1234: Manually
+Generating a Si5351 Register Map for 16-QFN Devices”.
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             17
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+5. I2C Interface
+Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
+I2C interface. The following is a list of the common features that are controllable through the I2C interface. For a
+complete listing of available I2C registers and programming steps, see AN619 or AN1234.
+Read Status Indicators
+      Crystal Reference Loss of signal, LOS_XTAL, reg0[3]
+
+      CLKIN Loss of signal, LOS_CLKIN, reg0[4]
+
+      PLLA and/or PLLB Loss of lock, LOL_A or LOL_B, reg0[6:5]
+
+ Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
+ Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
+ Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
+ Set output clock options
+      Enable/disable for each clock output
+
+      Invert/non-invert for each clock output
+                                   n
+      Output divider values (2 , n=1.. 7)
+
+      Output state when disabled (stop hi, stop low, Hi-Z)
+
+      Output phase offset
+
+
+The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
+Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
+The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 5.
+Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
+I2C specification.
+
+                                                                   VDD
+
+
+                                                           >1k           >1k
+                                                                                                   Si5351
+                                                                         SCL
+                                   I2C Bus
+                                                                         SDA
+
+                                                          4.7 k
+                                                                         INTR
+
+
+                                        I2C Address Select:               A0
+                                        Pull-up to VDD (A0 = 1)
+                                       Pull-down to GND (A0 = 0)
+
+
+
+
+                                                        Figure 5. I2C and Control Signals
+The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
+shown in Figure 6. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
+require more than one Si5351 on a single I2C bus. Only the Si5351A 20-QFN and Si5351A 16-QFN have the A0
+LSB pin option. If a part does not have the A0 pin, the default address is 0x60 with the A0 bit set to 0.
+
+                                                                               6   5   4   3   2   1    0
+
+                                       Slave Address                           1   1   0   0   0   0 0/1
+
+                                                                                                            A0
+
+                                                      Figure 6. Si5351 I2C Slave Address
+
+
+
+
+18          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                            Si5351A/B/C-B
+Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-
+bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 7. A write
+burst operation is also shown where every additional data word is written using to an auto-incremented address.
+
+                                     Write Operation – Single Byte
+                                      S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0]     A P
+
+
+
+                                     Write Operation - Burst (Auto Address Increment)
+                                      S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P
+
+
+                                                                                              Reg Addr +1
+
+
+
+                                          From slave to master         1 – Read
+                                                                       0 – Write
+                                          From master to slave         A – Acknowledge (SDA LOW)
+                                                                       N – Not Acknowledge (SDA HIGH)
+                                                                       S – START condition
+                                                                       P – STOP condition
+
+                                                  Figure 7. I2C Write Operation
+A read operation is performed in two stages. A data write is used to set the register address, then a data read is
+performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
+Figure 8.
+
+                                   Read Operation – Single Byte
+                                    S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
+
+                                    S Slv Addr [6:0] 1 A Data [7:0] N P
+
+
+
+
+                                   Read Operation - Burst (Auto Address Increment)
+
+                                    S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
+
+                                    S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P
+
+                                                                           Reg Addr +1
+
+
+
+
+                                        From slave to master         1 – Read
+                                                                     0 – Write
+                                        From master to slave         A – Acknowledge (SDA LOW)
+                                                                     N – Not Acknowledge (SDA HIGH)
+                                                                     S – START condition
+                                                                     P – STOP condition
+
+                                                  Figure 8. I2C Read Operation
+AC and DC electrical specifications for the SCL and SDA pins are shown in Table 9. The timing specifications and
+timing diagram for the I2C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility
+with SMBus interfaces.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             19
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+6. Configuring the Si5351
+The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s
+default configuration is stored in non-volatile memory (NVM) as shown in Figure 9. The NVM is a one time
+programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for
+applications that need a clock present at power-up (e.g., for providing a clock to a processor).
+
+                                                                  Power-Up
+
+
+                                                               NVM
+                                                              (OTP)
+                                                                           RAM
+                                                              Default
+                                                              Config
+
+
+
+                                                                            I2C
+                                           Figure 9. Si5351 Memory Configuration
+During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
+device configuration that will be used during normal operation. Any changes to the device configuration after
+power-up are made by reading and writing to registers in the RAM space through the I2C interface.
+6.1. Writing a Custom Configuration to RAM
+To simplify device configuration, Skyworks Solutions has released the ClockBuilder Pro. The software serves two
+purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
+EVB when connected to a host PC.
+The optimal configuration can be saved from the software in text files that can be used in any system, which
+configures     the    device    over     I2C.    ClockBuilder      Pro     can    be     downloaded     from
+https://www.skyworksinc.com/en/application-pages/clockbuilder-pro-software
+Once the configuration file has been saved, the device can be programmed via I2C by following the steps shown in
+Figure 10.
+
+
+
+
+20          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                               Si5351A/B/C-B
+
+
+
+                                                                        Disable Outputs
+                                                                Set CLKx_DIS high; Reg. 3 = 0xFF
+
+
+
+
+                                                                   Power-down all output drivers
+                                                                Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
+                                                                               0x80
+
+
+
+                                                                         Set interrupt masks
+                                                                      (see register 2 description)
+
+
+
+
+                                      Register               Write new configuration to device using
+                                       Map                      the contents of the register map
+                                                            generated by ClockBuilder Pro. This step
+                                                               also powers up the output drivers.
+                  To download ClockBuilder Pro ,
+                  go to:                                         (Registers 15-92 and 149-170)
+                  https://www.skyworksinc.com/en
+                  /application-pages/clockbuilder-
+                  pro-software
+
+
+                                                                  Apply PLLA and PLLB soft reset
+                                                                         Reg. 177 = 0xAC
+
+
+
+
+                                                                        Enable desired outputs
+                                                                           (see Register 3)
+
+
+
+
+                                      Figure 10. I2C Programming Procedure
+
+
+
+
+       Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             21
+Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+6.2. Si5351 Application Examples
+The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
+how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
+6.3. Replacing Crystals and Crystal Oscillators
+Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
+for replacing crystals and crystal oscillators. A 4-output with separate VDDO for each output and a 3-output version
+are also available in small 16-QFN and 10-MSOP packages, respectively, for applications that require fewer
+clocks. An example is shown in Figure 11.
+
+
+                               XA                                             Multi        CLK0       125 MHz                    Ethernet
+                                                                              Synth                                                PHY
+                                                                                0
+                   27 MHz                 OSC              PLL
+                                                                              Multi        CLK1
+                               XB                                                                      48 MHz                    USB
+                                                                              Synth                                            Controller
+                                                                                1
+                                                                              Multi        CLK2        28.322 MHz                 HDMI
+                                                                              Synth
+                                                                                2                                                  Port
+
+                                                                              Multi        CLK3       74.25 MHz
+                                                                              Synth
+                                                                                3
+                                                                              Multi        CLK4    74.25/1.001 MHz
+                                                                              Synth
+                                                                                4                                                    Video/Audio
+                                                                              Multi        CLK5        24.576 MHz                     Processor
+                                                                              Synth
+                                                                                5
+                                                                              Multi        CLK6       22.5792 MHz
+                                                                              Synth
+                                                                                6
+                                                                              Multi         CLK7       33.3333 MHz
+                                                                              Synth                                                CPU
+                                      Si5351A                                   7
+
+
+                                      Note: Si5351A replaces crystals, XOs, and PLLs.
+
+
+
+        Figure 11. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
+6.4. Replacing Crystals, Crystal Oscillators, and VCXOs
+The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
+applications. An example is shown in Figure 12.
+
+                                                                                                                Free-running
+                                                                                                                   Clocks
+                                         XA                                                          CLK0                                    Ethernet
+                                                                                        Multi                        125 MHz                   PHY
+                                                                                        Synth
+                                                                                          0
+                            27 MHz                     OSC              PLL
+                                                                                        Multi        CLK1
+                                         XB                                                                          48 MHz                    USB
+                                                                                        Synth
+                                                                                          1                                                  Controller
+
+                                                                                        Multi        CLK2            28.322 MHz
+                                                                                        Synth
+                                                                                          2                                                    HDMI
+                                                                                                                                               Port
+
+
+                                                                                        Multi        CLK3            74.25 MHz
+                                         VC                                             Synth
+                                                                                          3
+                                                                      VCXO
+                                                                                        Multi        CLK4       74.25/1.001 MHz             Video/Audio
+                                                                                        Synth
+                                                                                          4                                                  Processor
+
+                                                                                        Multi        CLK5            24.576 MHz
+                                                                                        Synth
+                                                                                          5
+                                                   Si5351B                                                        VCXO Clock
+                                                                                                                    Outputs
+
+                            Note: FBW = 10 kHz
+
+        Figure 12. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
+
+
+
+
+22          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                       Si5351A/B/C-B
+6.5. Replacing Crystals, Crystal Oscillators, and PLLs
+The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
+Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
+clocks. An example is shown in Figure 13.
+
+                                                                                     Free-running
+                                                                                        Clocks
+
+                                   XA                                         CLK0                      Ethernet
+                                                                     Multi             125 MHz            PHY
+                                                                     Synth
+                                                                       0
+                        25 MHz              OSC        PLL
+                                                                     Multi    CLK1
+                                   XB                                                  48 MHz             USB
+                                                                     Synth
+                                                                       1                                Controller
+
+                                                                     Multi    CLK2     28.322 MHz
+                                                                     Synth
+                                                                       2                                  HDMI
+                                                                                                          Port
+
+
+                                                                     Multi    CLK3     74.25 MHz
+                                 CLKIN                               Synth
+                                                                       3
+                       54 MHz                          PLL
+                                                                     Multi    CLK4   74.25/1.001 MHz   Video/Audio
+                                                                     Synth
+                                                                       4                                Processor
+
+                                                                     Multi    CLK5     24.576 MHz
+                                                                     Synth
+                                                                       5
+                                           Si5351C
+                                                                                     Synchronous
+                                                                                       Clocks
+
+
+           Figure 13. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
+6.6. Applying a Reference Clock at XTAL Input
+The Si5351 can be driven with a clock signal through the XA input pin. This is especially useful when in need of
+generating clock outputs in two synchronization domains. With the Si5351C, one reference clock can be provided
+at the CLKIN pin and at XA.
+
+
+
+                                                  VIN = 1 VPP
+                                                                                                               Multi
+                                                  25/27 MHz
+                                                                    XA                   PLLA                  Synth
+                                                                                                                 0
+                                                                0.1 µF       OSC                               Multi
+                                                                                                               Synth
+                                                                                                                 1
+                                                                    XB                   PLLB
+
+
+
+                                                                                                                 Multi
+                  Note: Float the XB input while driving                                                         Synth
+                                                                                                                   N
+                               the XA input with a clock
+
+
+
+
+                                         Figure 14. Si5351 Driven by a Clock Signal
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             23
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+6.7. HCSL Compatible Outputs
+The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
+set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
+The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
+must also be inverted to generate a differential pair. See register setting CLKx_INV. This functionality is only
+supported for Si5351 in 10-MSOP or 20-QFN packages.
+
+
+                                                                                 ZO = 50         R1
+                                                    Multi
+                                   PLLA             Synth
+                                                      0               0                        511 
+
+                      OSC                                                                         240      R2      HCSL
+                                                                                                                    CLKIN
+                                   PLLB                                          ZO = 50         R1
+                                                    Multi
+                                                    Synth
+                                                      1               0                        511 
+                                                                                                  240      R2
+
+                                                    Multi
+                                                    Synth       Note: The complementary -180 degree
+                                                      N
+                                                                out of phase output clock is generated
+                                                                using the INV function
+
+                                      Figure 15. Si5351 Output is HCSL Compatible
+
+
+
+
+24          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+7. Design Considerations
+The Si5351 is a self-contained clock generator that requires very few external components. The following general
+guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
+additional layout recommendations.
+7.1. Power Supply Decoupling/Filtering
+The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
+regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 to
+1.0 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and
+VDDOx pins as possible without using vias.
+7.2. Power Supply Sequencing
+The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
+flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
+powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
+7.3. External Crystal
+The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
+traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
+details.
+7.4. External Crystal Load Capacitors
+The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
+insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
+capacitors are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection
+Guide” for more details.
+7.5. Unused Pins
+Unused voltage control pin should be tied to GND.
+Unused CLKIN pin should be tied to GND.
+Unused XA/XB pins should be left floating. Refer to "6.6. Applying a Reference Clock at XTAL Input" on page 23
+when using XA as a clock input pin.
+Unused output pins (CLK0–CLK7) should be left floating.
+Unused VDDOx pins should be tied to VDD.
+7.6. Trace Characteristics
+The Si5351A/B/C features various output current drive strengths. It is recommended to configure the trace
+characteristics as shown in Figure 16 when the default high drive strength is used.
+
+
+
+                                                                         ZO = 50 ohms
+
+                                                 R = 0 ohms
+                                      CLK
+                                                (Optional resistor for
+                                                EMI management)
+
+
+
+
+        Figure 16. Recommended Trace Characteristics with Default Drive Strength Setting
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             25
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+8. Register Map Summary
+For many applications, the Si5351's register values are easily configured using ClockBuilder Pro software.
+However, for customers interested in using the Si5351 in operating modes beyond the capabilities available with
+ClockBuilder Pro, see AN619 or AN1234.
+9. Register Descriptions
+Refer to either AN619 for 10MSOP and 20QFN devices or AN1234 for 16-QFN devices. These application notes
+provide detailed descriptions of the Si5351 registers and their use.
+
+
+
+
+26          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                                              Si5351A/B/C-B
+10. Si5351 Pin Descriptions
+10.1. Si5351A 20-pin QFN
+
+
+
+
+                                                                              18 VDDOC
+                                                                    19 CLK4
+
+
+
+                                                                                         17 CLK5
+
+                                                                                                   16 CLK6
+                                                           20 VDD
+                                                XA     1                                                      15 CLK7
+
+                                                 XB    2                                                      14 VDDOD
+                                                                              GND
+                                                 A0    3                      PAD                             13 CLK0
+
+                                                SCL    4                                                      12 CLK1
+
+                                               SDA 5                                                          11 VDDOA
+
+
+
+
+                                                                                                   VDDOB 10
+                                                                    7
+
+
+
+                                                                                         9
+                                                                              8
+                                                           6
+                                                           SSEN
+
+
+
+                                                                              CLK3
+                                                                    OEB
+
+
+
+                                                                                         CLK2
+                                         Figure 17. Si5351A 20-QFN Top View
+
+                                          Table 14. Si5351A Pin Descriptions
+ Pin Name       Pin Number          Pin Type1                                                                            Function
+    XA                 1                  I           Input pin for external crystal.
+    XB                 2                  I           Input pin for external crystal.
+   CLK0                13                O            Output clock 0.
+   CLK1                12                O            Output clock 1.
+   CLK2                9                 O            Output clock 2.
+   CLK3                8                 O            Output clock 3.
+   CLK4                19                O            Output clock 4.
+   CLK5                17                O            Output clock 5.
+   CLK6                16                O            Output clock 6.
+   CLK7                15                O            Output clock 7.
+    A0                 3                  I           I2C address bit.
+   SCL                 4                  I           I2C bus serial clock input. Pull-up to VDD core with 1 k
+   SDA                 5                I/O           I2C bus serial data input. Pull-up to VDD core with 1 k
+  SSEN                 6                  I           Spread spectrum enable. High = enabled, Low = disabled.
+   OEB                 7                  I           Output driver enable. Low = enabled, High = disabled.
+   VDD                 20                P            Core voltage supply pin. See 7.2.
+  VDDOA                11                P            Output voltage supply pin for CLK0 and CLK1. See 7.2.
+  VDDOB                10                P            Output voltage supply pin for CLK2 and CLK3. See 7.2.
+  VDDOC                18                P            Output voltage supply pin for CLK4 and CLK5. See 7.2.
+  VDDOD                14                P            Output voltage supply pin for CLK6 and CLK7. See 7.2.
+   GND           Center Pad              P            Ground. Use multiple vias to ensure a solid path to GND.
+  1. I = Input, O = Output, P = Power.
+  2. Input pins are not internally pulled up.
+
+
+
+
+        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             27
+ Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+10.2. Si5351B 20-Pin QFN
+
+
+
+
+                                                                                  18 VDDOC
+                                                                        19 CLK4
+
+
+
+
+                                                                                             17 CLK5
+
+                                                                                                       16 CLK6
+                                                               20 VDD
+                                                                                                                       CLK7
+                                                   XA   1                                                         15
+                                                                                                                       VDDOD
+                                                   XB   2                                                         14
+                                                                                  GND                                  CLK0
+                                                  VC    3                         PAD                             13
+                                                                                                                       CLK1
+                                                  SCL   4                                                         12
+                                                                                                                       VDDOA
+                                                  SDA   5                                                         11
+
+
+
+
+                                                                                                       VDDOB 10
+                                                                        7
+
+
+
+
+                                                                                             9
+                                                                                  8
+                                                               6
+
+
+
+
+                                                                                  CLK3
+                                                                        OEB
+
+
+
+
+                                                                                             CLK2
+                                                               SSEN
+
+                                             Figure 18. Si5351B 20-QFN Top View
+
+                                              Table 15. Si5351B Pin Descriptions
+ Pin Name           Pin Number          Pin Type1                                                                         Function
+        XA                 1                  I             Input pin for external crystal
+        XB                 2                  I             Input pin for external crystal
+       CLK0                13                O              Output clock 0
+       CLK1                12                O              Output clock 1
+       CLK2                9                 O              Output clock 2
+       CLK3                8                 O              Output clock 3
+       CLK4                19                O              Output clock 4
+       CLK5                17                O              Output clock 5
+       CLK6                16                O              Output clock 6
+       CLK7                15                O              Output clock 7
+        VC                 3                  I             VCXO control voltage input
+       SCL                 4                  I             I2C bus serial clock input. Pull-up to VDD core with 1 k
+       SDA                 5                I/O             I2C bus serial data input. Pull-up to VDD core with 1 k
+      SSEN                 6                  I             Spread spectrum enable. High = enabled, Low = disabled.
+       OEB                 7                  I             Output driver enable. Low = enabled, High = disabled.
+       VDD                 20                P              Core voltage supply pin
+     VDDOA                 11                P              Output voltage supply pin for CLK0 and CLK1. See 7.2
+     VDDOB                 10                P              Output voltage supply pin for CLK2 and CLK3. See 7.2
+     VDDOC                 18                P              Output voltage supply pin for CLK4 and CLK5. See 7.2
+     VDDOD                 14                P              Output voltage supply pin for CLK6 and CLK7. See 7.2
+       GND           Center Pad              P              Ground
+      1. I = Input, O = Output, P = Power
+      2. Input pins are not internally pulled up.
+
+
+
+
+28          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                                             Si5351A/B/C-B
+10.3. Si5351C 20-Pin QFN
+
+
+
+
+                                                                            18 VDDOC
+                                                                  19 CLK4
+
+
+
+
+                                                                                       17 CLK5
+
+                                                                                                 16 CLK6
+                                                         20 VDD
+                                               XA    1                                                      15   CLK7
+
+                                               XB    2                                                      14   VDDOD
+                                                                            GND
+                                              INTR   3                      PAD                             13   CLK0
+
+                                              SCL    4                                                      12   CLK1
+
+                                              SDA    5                                                      11   VDDOA
+
+
+
+
+                                                                                                 VDDOB 10
+                                                                  7
+
+
+
+
+                                                                                       9
+                                                                            8
+                                                         6
+                                                         CLKIN
+
+
+
+
+                                                                            CLK3
+                                                                  OEB
+
+
+
+
+                                                                                       CLK2
+                                         Figure 19. Si5351C 20-QFN Top View
+
+                                          Table 16. Si5351C Pin Descriptions
+                Pin Number
+ Pin Name                           Pin Type1                                                                           Function
+                   20-QFN
+     XA                1                  I          Input pin for external crystal.
+     XB                2                  I          Input pin for external crystal.
+   CLK0                13                O           Output clock 0.
+   CLK1                12                O           Output clock 1.
+   CLK2                9                 O           Output clock 2.
+   CLK3                8                 O           Output clock 3.
+   CLK4                19                O           Output clock 4.
+   CLK5                17                O           Output clock 5.
+   CLK6                16                O           Output clock 6.
+   CLK7                15                O           Output clock 7.
+    INTR               3                 O           Interrupt pin. Open drain active low output, requires a pull-up resistor
+                                                     greater than 4.7 k
+    SCL                4                  I          I2C bus serial clock input. Pull-up to VDD core with 1 k
+    SDA                5                I/O          I2C bus serial data input. Pull-up to VDD core with 1 k
+   CLKIN               6                  I          PLL clock input.
+    OEB                7                  I          Output driver enable. Low = enabled, High = disabled.
+    VDD                20                P           Core voltage supply pin
+  VDDOA                11                P           Output voltage supply pin for CLK0 and CLK1. See 7.2
+  VDDOB                10                P           Output voltage supply pin for CLK2 and CLK3. See 7.2
+  VDDOC                18                P           Output voltage supply pin for CLK4 and CLK5. See 7.2
+  VDDOD                14                P           Output voltage supply pin for CLK6 and CLK7. See 7.2
+    GND          Center Pad              P           Ground.
+Notes:
+   1. I = Input, O = Output, P = Power.
+   2. Input pins are not internally pulled up.
+
+
+
+        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             29
+ Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+10.4. Si5351A 16-Pin QFN
+
+
+
+
+                                                                              14 VDDOC
+
+                                                                                         13 CLK2
+                                                                     15 GND
+                                                            16 VDD
+                                                  XA    1                                          12 CLK3
+
+                                                   XB   2                                          11 VDDOD
+                                                                          GND
+                                                                          PAD
+                                                  A0    3                                          10 CLK0
+
+                                                  SCL   4                                          9 VDDOA
+
+
+
+
+                                                            5
+
+                                                                     6
+
+                                                                                7
+
+                                                                                         8
+                                                                     OEB
+
+
+
+
+                                                                                         VDDOB
+                                                            SDA
+
+
+
+
+                                                                              CLK1
+                                             Figure 20. Si5351A 16-QFN Top View
+
+                                              Table 17. Si5351A Pin Descriptions
+
+ Pin Name            Pin Number          Pin Type1                                                           Function
+
+       XA                  1                  I         Input pin for external crystal.
+       XB                  2                  I         Input pin for external crystal.
+      CLK0                 10                O          Output Clock 0.
+      CLK1                 7                 O          Output Clock 1.
+      CLK2                 13                O          Output Clock 2.
+      CLK3                 12                O          Output Clock 3.
+       A0                   3                 I         I2C address bit.
+      SCL                   4                 I         I2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
+      SDA                  5                 I/O        I2C bus serial data input. Pull-up to VDD core with 1 kΩ.
+      OEB                   6                 I         Output driver enable. Low = Enabled; High = Disabled.
+      VDD                  16                 P         Core voltage supply pin. See “7.2. Power Supply Sequencing”
+     VDDOA                 9                  P         Output voltage supply pin for CLK0. See “7.2. Power Supply Sequencing” .
+     VDDOB                 8                  P         Output voltage supply pin for CLK1. See “7.2. Power Supply Sequencing” .
+     VDDOC                 14                 P         Output voltage supply pin for CLK2. See “7.2. Power Supply Sequencing” .
+     VDDOD                 11                 P         Output voltage supply pin for CLK3. See “7.2. Power Supply Sequencing” .
+      GND                  15               GND         Ground.
+ GND PAD              Center Pad            GND         Ground pad. Use multiple vias to ensure a solid path to Ground.
+
+Notes:
+   1. I = Input, O = Output, P= Power, GND = Ground Input pins are not internally pulled up.
+
+
+
+
+30          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                             Si5351A/B/C-B
+10.5. Si5351B 16-Pin QFN
+
+
+
+
+                                                                             14 VDDOC
+
+                                                                                        13 CLK2
+                                                                    15 GND
+                                                           16 VDD
+                                               XA   1                                             12 CLK3
+
+                                               XB   2                                             11 VDDOD
+                                                                         GND
+                                                                         PAD
+                                               VC   3                                             10 CLK0
+
+                                            SCL     4                                             9 VDDOA
+
+
+                                                           5
+
+                                                                    6
+
+                                                                               7
+
+                                                                                        8
+                                                                    OEB
+
+
+
+
+                                                                                        VDDOB
+                                                                             CLK1
+                                                           SDA
+
+
+
+                                         Figure 21. Si5351B 16-QFN Top View*
+
+                                           Table 18. Si5351B Pin Descriptions
+
+ Pin Name         Pin Number          Pin Type1                                                         Function
+
+    XA                  1                  I            Input pin for external crystal.
+    XB                  2                  I            Input pin for external crystal.
+   CLK0                 10                O             Output Clock 0.
+   CLK1                  7                O             Output Clock 1.
+   CLK2                 13                O             Output Clock 2.
+   CLK3                 12                O             Output Clock 3.
+    VC                   3                 I            VCXO control voltage input
+    SCL                  4                 I            I2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
+    SDA                  5                I/O           I2C bus serial data input. Pull-up to VDD core with 1 kΩ.
+    OEB                  6                 I            Output driver enable. Low = Enabled; High = Disabled.
+    VDD                 16                 P            Core voltage supply pin. See “7.2. Power Supply Sequencing”
+  VDDOA                  9                 P            Output voltage supply pin for CLK0. See “7.2. Power Supply Sequencing” .
+  VDDOB                  8                 P            Output voltage supply pin for CLK1. See “7.2. Power Supply Sequencing” .
+  VDDOC                 14                 P            Output voltage supply pin for CLK2. See “7.2. Power Supply Sequencing” .
+  VDDOD                 11                 P            Output voltage supply pin for CLK3. See “7.2. Power Supply Sequencing” .
+   GND                  15               GND            Ground.
+ GND PAD           Center Pad            GND            Ground pad. Use multiple vias to ensure a solid path to Ground
+
+Notes:
+   1. I = Input, O = Output, P= Power, GND = Ground Input pins are not internally pulled up.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             31
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+10.6. Si5351C 16-Pin QFN
+
+
+
+
+                                                                            14 VDDOC
+
+                                                                                       13 CLK2
+                                                                   15 GND
+                                                          16 VDD
+                                             XA    1                                             12 CLK3
+
+                                             XB    2                                             11 VDDOD
+                                                                        GND
+                                                                        PAD
+                                            OEB     3                                            10 CLK0
+
+                                            SCL     4                                            9 VDDOA
+
+                                                          5
+
+                                                                   6
+
+                                                                              7
+
+                                                                                       8
+                                                                   CLKIN
+
+
+
+
+                                                                                       VDDOB
+                                                                            CLK1
+                                                          SDA
+
+
+
+
+                                             Figure 22. Si5351C 16-QFN Top View
+
+                                              Table 19. Si5351C Pin Descriptions
+
+ Pin Name            Pin Number          Pin Type1                                                   Function
+
+       XA                  1                  I         Input pin for external crystal.
+       XB                  2                  I         Input pin for external crystal.
+      CLK0                 10                O          Output Clock 0.
+      CLK1                 7                 O          Output Clock 1.
+      CLK2                 13                O          Output Clock 2.
+      CLK3                 12                O          Output Clock 3.
+     CLKIN                 6                  I         PLL clock input
+      SCL                   4                 I         I2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
+      SDA                  5                 I/O        I2C bus serial data input. Pull-up to VDD core with 1 kΩ.
+      OEB                   3                 I         Output driver enable. Low = Enabled; High = Disabled.
+      VDD                  16                 P         Core voltage supply pin. See “7.2. Power Supply Sequencing”
+     VDDOA                 9                  P         Output voltage supply pin for CLK0. See “7.2. Power Supply Sequencing”
+     VDDOB                 8                  P         Output voltage supply pin for CLK1. See “7.2. Power Supply Sequencing”
+     VDDOC                 14                 P         Output voltage supply pin for CLK2. See “7.2. Power Supply Sequencing”
+     VDDOD                 11                 P         Output voltage supply pin for CLK3. See “7.2. Power Supply Sequencing”
+      GND                  15               GND         Ground.
+ GND PAD              Center Pad            GND         Ground pad. Use multiple vias to ensure a solid path to Ground.
+
+Notes:
+   1. I = Input, O = Output, P= Power, GND = Ground Input pins are not internally pulled up.
+
+
+
+32          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                Si5351A/B/C-B
+10.7. Si5351A 10-Pin MSOP
+
+
+                                          VDD            1               10            CLK0
+
+                                           XA            2                9            CLK1
+
+                                           XB            3                8            GND
+
+                                          SCL            4                7            VDDO
+
+                                          SDA            5                6           CLK2
+
+
+
+                                         Figure 23. Si5351A 10-MSOP Top View
+
+                                   Table 20. Si5351A 10-MSOP Pin Descriptions
+
+                  Pin
+Pin Name        Number         Pin Type*                                             Function
+               10-MSOP
+
+    XA              2               I        Input pin for external crystal.
+
+    XB              3               I        Input pin for external crystal.
+
+  CLK0             10               O        Output clock 0.
+
+  CLK1              9               O        Output clock 1.
+
+  CLK2              6               O        Output clock 2.
+
+   SCL              4               I        Serial clock input for the I2C bus. This pin must be pulled-up using a pull-
+                                             up resistor of at least 1 k.
+   SDA              5              I/O       Serial data input for the I2C bus. This pin must be pulled-up using a pull-up
+                                             resistor of at least 1 k.
+   VDD              1               P        Core voltage supply pin.
+
+  VDDO              7               P        Output voltage supply pin for CLK0, CLK1, and CLK2. See "7.2. Power
+                                             Supply Sequencing" on page 25.
+   GND              8               P        Ground.
+
+*Note: I = Input, O = Output, P = Power
+
+
+
+
+        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             33
+ Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+11. Ordering Information
+Factory pre-programmed Si5351 devices (e.g., with bootup frequencies) can be requested using the ClockBuilder
+Pro available at:https://www.skyworksinc.com/en/application-pages/clockbuilder-pro-software.
+A unique part number is assigned to each custom configuration as indicated in Figure 24. Blank, un-programmed
+Si5351 devices (with no boot-up frequency) do not contain a custom code.
+The Si5351x-B20QFN-EVB evaluation kit, along with ClockBuilder Pro, enables easy testing of any Si5351A/B/C
+frequency plan. ClockBuilder Pro makes it simple to emulate all three Si5351 packages, including the 10-MSOP,
+20-QFN, and 16-QFN, on the same evaluation board.
+
+
+              Si5351                        X           B           XXXXX                     XXX
+
+                                                                                                                Blank = Coil Tape
+                                                                                                                R = Tape and Reel
+
+                                                                                                                GT = 10-MSOP*
+                                                                                                                GM = 20-QFN
+                                                                                                                GM1 = 16-QFN
+
+                                                                                  Blank = For blank devices (no boot-up frequency)
+                                                                                  XXXXX = Unique Custom Code. A five-character
+                                                                                  code will be assigned for each unique custom
+                                                                                  configuration.
+
+
+                                                                                  B = Product Revision B
+        *Note: The 10-MSOP is only
+        available in the Si5351A variant.
+                                                                                  A = Crystal In
+                                                                                  B = Crystal In + VCXO
+                                                                                  C = Crystal In + CLKIN
+
+
+
+
+                         Evaluation Boards
+
+                  Si535x-B20QFN-EVB                       For evaluation of:
+                                                          Si5351A-B-GM (20-QFN)
+                                                          Si5351B-B-GM (20-QFN)
+                                                          Si5351C-B-GM (20-QFN)
+                                                Figure 24. Device Part Numbers
+
+
+
+
+34          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                       Si5351A/B/C-B
+12. Packaging
+12.1. 20-pin QFN Package Outline
+Figure 25 shows the package details for the Si5351 in a 20-QFN package. Table 21 lists the values for the
+dimensions shown in the illustration.
+
+
+
+
+                                                                        Seating Plane
+                                                                   C
+                                                                                                       D2
+                   B                  D                             A
+                                                                                                            D2/2
+                                                                   A1
+
+                                                                                          L
+
+
+
+
+               E                                                                                                              E2
+
+                                                                                                                       E2/2
+
+
+
+
+               A                                                                                                   b
+                                                                                                   e
+
+
+
+                                          Figure 25. 20-Pin QFN Package Drawing
+
+                                              Table 21. Package Dimensions
+                       Dimension                    Min                                  Nom                  Max
+                           A                        0.80                                 0.85                 0.90
+                            A1                      0.00                                   —                  0.05
+                             b                      0.20                                   0.25               0.30
+                            D                                                           4.00 BSC
+                            D2                      2.65                                   2.70               2.75
+                             e                                                          0.50 BSC
+                            E                                                           4.00 BSC
+                            E2                      2.65                                   2.70               2.75
+                             L                      0.35                                   0.40               0.45
+                           aaa                       —                                     —                  0.10
+                           bbb                       —                                     —                  0.10
+                           ccc                       —                                     —                  0.08
+                           ddd                       —                                     —                  0.10
+                   Notes:
+                      1. All dimensions shown are in millimeters (mm) unless otherwise noted.
+                      2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
+                      3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
+                      4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
+                          Small Body Components.
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             35
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+12.2. Land Pattern: 20-Pin QFN
+Figure 26 shows the recommended land pattern details for the Si5351 in a 20-Pin QFN package. Table 22 lists the
+values for the dimensions shown in the illustration.
+
+
+
+
+                                              Figure 26. 20-Pin QFN Land Pattern
+
+                                          Table 22. PCB Land Pattern Dimensions
+                                          Symbol                                        Millimeters
+                                             C1                                              4.0
+                                             C2                                              4.0
+                                              E                                          0.50 BSC
+                                             X1                                              0.30
+                                             X2                                              2.70
+                                             Y1                                              0.80
+                                             Y2                                              2.70
+                       Notes:
+                       General
+                          1. All dimensions shown are in millimeters (mm) unless otherwise noted.
+                          2. This land pattern design is based on IPC-7351 guidelines.
+                       Solder Mask Design
+                          3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
+                              the solder mask and the metal pad is to be 60 µm minimum, all the way around
+                              the pad.
+                       Stencil Design
+                          4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
+                              should be used to assure good solder paste release.
+                          5. The stencil thickness should be 0.125 mm (5 mils).
+                          6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
+                          7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the
+                              center ground pad.
+                       Card Assembly
+                          8. A No-Clean, Type-3 solder paste is recommended.
+                          9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
+                              specification for Small Body components.
+
+
+
+
+36          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+12.3. 16-Pin QFN Package Outline
+Figure 27 shows the package details for the Si5351 in a 16-QFN package. Table 23 lists the values for the
+dimensions shown in the illustration.
+
+
+
+
+                                       Figure 27. 16-Pin QFN Package Drawing
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             37
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+                                                 Table 23. Package Dimensions
+
+                             Dimension                    Min                    Nom                    Max
+                                    A                     0.80                   0.85                   0.90
+
+                                   A1                     0.00                   0.02                   0.05
+
+                                   A3                                         0.20 REF.
+
+                                    b                     0.18                   0.25                   0.30
+
+                                   D                                           3.0 BSC
+
+                                   D2                     1.70                   1.80                   1.90
+
+                                    e                                         0.50 BSC
+
+                                    E                                          3.0 BSC
+
+                                   E2                     1.70                   1.80                   1.90
+
+                                    L                     0.25                   0.35                   0.45
+
+                                    K                     0.20                     —                      —
+
+                                   R                      0.09                     —                    0.14
+
+                                  aaa                                            0.15
+
+                                  bbb                                            0.10
+
+                                  ccc                                            0.10
+
+                                  ddd                                            0.05
+
+                                  eee                                            0.08
+
+                                   fff                                           0.10
+
+                        Notes:
+                           1. All dimensions shown are in millimeters (mm) unless otherwise noted.
+                           2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
+                           3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
+                               specification for Small Body Components.
+
+
+
+
+38          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+12.4. Land Pattern: 16-Pin QFN
+Figure 28 shows the recommended land pattern details for the Si5351 in a 16-Pin QFN package. Table 24 lists the
+values for the dimensions shown in the illustration.
+
+
+
+
+                                           Figure 28. 16-Pin QFN Land Pattern
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             39
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+                                          Table 24. PCB Land Pattern Dimensions
+                                      Symbol                                                Millimeters
+                                         C1                                                     3.00
+                                         C2                                                     3.00
+                                          E                                                     0.50
+                                         X1                                                     0.30
+                                         Y1                                                     0.75
+                                         X2                                                     1.80
+                                         Y2                                                     1.80
+                Notes:
+                General
+                   1. All dimensions shown are in millimeters (mm).
+                   2. This land pattern design is based on IPC-7351 guidelines.
+                   3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
+                      Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
+                Solder Mask Design
+                   4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
+                      solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
+                Stencil Design
+                   5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
+                      be used to assure good solder paste release.
+                   6. The stencil thickness should be 0.125 mm (5 mils).
+                   7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
+                   8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the
+                      center ground pad.
+                Card Assembly
+                   9. A No-Clean, Type-3 solder paste is recommended.
+                   10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
+                      specification for Small Body components.
+                   11. The above notes and stencil design are shared as recommendations only. A
+                      customer or user may find it necessary to use different parameters and fine-tune
+                      their SMT process as required for their application and tooling.
+
+
+
+
+40          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+12.5. 10-Pin MSOP Package Outline
+Figure 29 illustrates the package details for the Si5351 in a 10-pin MSOP package. Table 25 lists the values for the
+dimensions shown in the illustration.
+
+
+
+
+                                      Figure 29. 10-pin MSOP Package Drawing
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             41
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+
+                                          Table 25. 10-MSOP Package Dimensions
+                   Dimension                         Min                          Nom                            Max
+                       A                              —                             —                            1.10
+                      A1                             0.00                           —                            0.15
+                      A2                             0.75                          0.85                          0.95
+                       b                             0.17                           —                            0.33
+                       c                             0.08                           —                            0.23
+                       D                                                        3.00 BSC
+                       E                                                        4.90 BSC
+                      E1                                                        3.00 BSC
+                       e                                                        0.50 BSC
+                       L                             0.40                          0.60                          0.80
+                      L2                                                        0.25 BSC
+                       q                               0                            —                             8
+                      aaa                              —                            —                            0.20
+                      bbb                              —                            —                            0.25
+                      ccc                              —                            —                            0.10
+                      ddd                              —                            —                            0.08
+            Notes:
+               1. All dimensions shown are in millimeters (mm) unless otherwise noted.
+               2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
+               3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
+               4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
+                   Components.
+
+
+
+
+42          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                 Si5351A/B/C-B
+12.6. Land Pattern: 10-Pin MSOP
+Figure 30 shows the recommended land pattern details for the Si5351 in a 10-Pin MSOP package. Table 26 lists
+the values for the dimensions shown in the illustration.
+
+
+
+
+                                          Figure 30. 10-Pin MSOP Land Pattern
+
+                                       Table 26. PCB Land Pattern Dimensions
+                                  Symbol                                    Millimeters
+                                                                  Min                          Max
+                                     C1                                      4.40 REF
+                                      E                                      0.50 BSC
+                                     G1                          3.00                           —
+                                     X1                            —                           0.30
+                                     Y1                                      1.40 REF
+                                     Z1                            —                           5.80
+                         Notes:
+                         General
+                            1. All dimensions shown are in millimeters (mm) unless otherwise noted.
+                            2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
+                            3. This Land Pattern Design is based on the IPC-7351 guidelines.
+                            4. All dimensions shown are at Maximum Material Condition (MMC). Least
+                                Material Condition (LMC) is calculated based on a Fabrication
+                                Allowance of 0.05mm.
+                         Solder Mask Design
+                            5. All metal pads are to be non-solder mask defined (NSMD). Clearance
+                                between the solder mask and the metal pad is to be 60 µm minimum, all
+                                the way around the pad.
+                         Stencil Design
+                            6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
+                                walls should be used to assure good solder paste release.
+                            7. The stencil thickness should be 0.125 mm (5 mils).
+                            8. The ratio of stencil aperture to land pad size should be 1:1.
+                         Card Assembly
+                            9. A No-Clean, Type-3 solder paste is recommended.
+                            10. The recommended card reflow profile is per the JEDEC/IPC J-STD-
+                                020C specification for Small Body components.
+
+
+
+
+         Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             43
+  Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+13. Top Marking
+13.1. 20-Pin QFN Top Marking
+
+
+
+
+                                              Figure 31. 20-Pin QFN Top Marking
+13.2. Top Marking Explanation
+
+Mark Method:                     Laser
+Pin 1 Mark:                      Filled Circle = 0.50 mm Diameter
+                                 (Bottom-Left Corner)
+Font Size:                       0.60 mm (24 mils)
+Line 1 Mark Format               Device Part Number                           Si5351
+Line 2 Mark Format:              TTTTTT = Mfg Code*                           Manufacturing Code from the Assembly Purchase
+                                                                              Order Form.
+Line 3 Mark Format:              YY = Year                                    Assigned by the Assembly House. Corresponds to
+                                 WW = Work Week                               the year and work week of the assembly date.
+*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
+      for package assembly quality tracking purposes only.
+
+
+
+
+44          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                Si5351A/B/C-B
+13.3. 16-Pin QFN Top Marking
+
+
+
+
+                                          Figure 32. 16-Pin QFN Top Marking
+13.4. Top Marking Explanation
+
+Mark Method:                 Laser
+Pin 1 Mark:                  Circle (Bottom-Left Corner)
+Font Size:                   0.60 mm (24 mils)
+Line 1 Mark Format           Device Part Number                           5351
+Line 2 Mark Format:          TTTT = Mfg Code*                             Manufacturing Code from the Assembly Purchase
+                                                                          Order Form.
+Line 3 Mark Format:          YWW = Date Code                              Assigned by the Assembly House.
+                                                                          Y = Last digit of the current year.
+                                                                          WW = Work week of the assembly date.
+*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
+      package assembly quality tracking purposes only.
+
+
+
+
+        Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             45
+ Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+Si5351A/B/C-B
+13.5. 10-Pin MSOP Top Marking
+
+
+
+
+                                             Figure 33. 10-Pin MSOP Top Marking
+13.6. Top Marking Explanation
+
+Mark Method:                     Laser
+Pin 1 Mark:                      Mold Dimple (Bottom-Left Corner)
+Font Size:                       0.60 mm (24 mils)
+Line 1 Mark Format               Device Part Number                           5351
+Line 2 Mark Format:              TTTT = Mfg Code*                             Line 2 from the “Markings” section of the Assembly
+                                                                              Purchase Order form.
+Line 3 Mark Format:              YWW = Date Code                              Assigned by the Assembly House.
+                                                                              Y = Last Digit of Current Year (Ex: 2013 = 3)
+                                                                              WW = Work Week of Assembly Date.
+*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
+      package assembly quality tracking purposes only.
+
+
+
+
+46          Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
+     Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+                                                                                                   Si5351A/B/C-B
+REVISION HISTORY
+Revision 1.3
+March, 2020
+    Updated " Functional Block Diagrams" on page 2 with Si5351A 20-QFN and 16-QFN block diagrams.
+    Updated "1. Ordering Guide" on page 4.
+    Updated Table 4, “DC Characteristics,” on page 8 to include 16-QFN data.
+    Updated thermal characteristics tables to include Table 10 (2-Layer Board), Table 11 (4-Layer Board), and
+     Table 12 (Junction-to-Case).
+    Updated "4.4. Spread Spectrum" on page 17.
+    Added "4.6. Status Pins (INTR)" on page 17.
+    Updated "5. I2C Interface" on page 18 with LSB pin option clarification.
+    Updated "6. Configuring the Si5351" on page 20 with ClockBuilder Pro.
+    Updated "6.3. Replacing Crystals and Crystal Oscillators" on page 22.
+    Updated "6.7. HCSL Compatible Outputs" on page 24.
+    Updated "8. Register Map Summary" on page 26.
+    Updated "9. Register Descriptions" on page 26.
+    Updated "10. Si5351 Pin Descriptions" on page 27 with 16-QFN pin descriptions and Ground Pad description.
+    Updated "10.3. Si5351C 20-Pin QFN" on page 29.
+    Updated Figure 24, “Device Part Numbers,” on page 34.
+    Updated "11. Ordering Information" on page 34.
+    Updated "12. Packaging" on page 35 with 16-QFN package information.
+    Updated "13. Top Marking" on page 44 with 16-QFN top mark.
+Revision 1.1
+August, 2018
+    Updated "11. Ordering Information" on page 34.
+     Changed “Blank = Bulk” to “Blank = Coil Tape” in Figure 24.
+
+
+Revision 1.0
+April, 2015
+    Extended frequency range from 8 kHz-160 MHz to 2.5 kHz-200 MHz.
+    Updated block diagrams for clarity.
+    Added complete Si5350/1 family table, Table 1.
+    Added top mark information.
+    Added land pattern drawings.
+    Added PowerUp Time, PLL Bypass mode, Table 4.
+    Clarified Down Spread step sizes in Table 4.
+    Updated max jitter specs (typ unchanged) in Table 6.
+    Clarified power supply sequencing requirement, Section 6.2.
+Revision 0.75
+October, 2012
+    Initial release.
+
+
+
+
+           Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com             47
+    Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021
+     ClockBuilder Pro
+     Customize Skyworks clock generators,
+     jitter attenuators and network
+     synchronizers with a single tool. With
+     CBPro you can control evaluation
+     boards, access documentation, request
+     a custom part number, export for
+     in-system programming and more!
+
+
+     www.skyworksinc.com/CBPro
+
+
+
+
+                    Portfolio                           SW/HW                               Quality                     Support & Resources
+         www.skyworksinc.com/ia/timing        www.skyworksinc.com/CBPro           www.skyworksinc.com/quality         www.skyworksinc.com/support
+
+
+Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.
+Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the
+information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer.
+Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation,
+products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or
+information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
+
+No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability
+for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or
+materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.
+
+THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR
+OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY
+INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR
+COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR
+ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT
+LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT
+OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
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+products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such
+applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.
+
+Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of
+design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating
+safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any
+equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.
+
+Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or
+registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for
+identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at
+www.skyworksinc.com, are incorporated by reference.
+
+
+                          Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com
+                            USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |
+
\ No newline at end of file
diff --git a/tests/regression/python/si5351_math.py b/tests/regression/python/si5351_math.py
new file mode 100644
index 0000000..52933d7
--- /dev/null
+++ b/tests/regression/python/si5351_math.py
@@ -0,0 +1,1273 @@
+#!/usr/bin/env python3
+"""
+Host-side mirror of etherkit/Si5351Arduino pure-math helpers from master
+(commit 0559cbf82865e2957d46af72e70cc88207421434, library 2.2.0).
+
+Faithfully ports:
+  pll_calc, multisynth_calc, multisynth67_calc, select_r_div, select_r_div_ms67
+plus register packing used by set_pll / set_ms (CLK0-5 path).
+
+Frequencies in this library are Hz * SI5351_FREQ_MULT (100).
+"""
+from __future__ import annotations
+from dataclasses import dataclass, asdict
+from typing import Optional, Tuple, List, Dict, Any
+import json
+
+# --- constants from si5351.h ---
+SI5351_XTAL_FREQ = 25_000_000
+SI5351_PLL_FIXED = 80_000_000_000  # 800 MHz * 100
+SI5351_FREQ_MULT = 100
+
+SI5351_PLL_VCO_MIN = 600_000_000
+SI5351_PLL_VCO_MAX = 900_000_000
+SI5351_MULTISYNTH_MIN_FREQ = 500_000
+SI5351_MULTISYNTH_DIVBY4_FREQ = 150_000_000
+SI5351_MULTISYNTH_MAX_FREQ = 225_000_000
+SI5351_MULTISYNTH_SHARE_MAX = 100_000_000
+SI5351_CLKOUT_MIN_FREQ = 4_000
+SI5351_MULTISYNTH67_A_MAX = 254
+SI5351_CLKOUT67_MS_MIN = SI5351_PLL_VCO_MIN // SI5351_MULTISYNTH67_A_MAX
+SI5351_CLKOUT67_MIN_FREQ = SI5351_CLKOUT67_MS_MIN // 128
+
+SI5351_PLL_A_MIN = 15
+SI5351_PLL_A_MAX = 90
+SI5351_MULTISYNTH_A_MIN = 6
+SI5351_MULTISYNTH_A_MAX = 1800
+
+RFRAC_DENOM = 1_000_000
+
+SI5351_OUTPUT_CLK_DIV_1 = 0
+SI5351_OUTPUT_CLK_DIV_2 = 1
+SI5351_OUTPUT_CLK_DIV_4 = 2
+SI5351_OUTPUT_CLK_DIV_8 = 3
+SI5351_OUTPUT_CLK_DIV_16 = 4
+SI5351_OUTPUT_CLK_DIV_32 = 5
+SI5351_OUTPUT_CLK_DIV_64 = 6
+SI5351_OUTPUT_CLK_DIV_128 = 7
+
+SI5351_VCXO_PULL_MIN = 30
+SI5351_VCXO_PULL_MAX = 240
+SI5351_VCXO_MARGIN = 103
+
+R_DIV_NAMES = {
+    0: "DIV_1", 1: "DIV_2", 2: "DIV_4", 3: "DIV_8",
+    4: "DIV_16", 5: "DIV_32", 6: "DIV_64", 7: "DIV_128",
+}
+
+
+@dataclass
+class RegSet:
+    p1: int
+    p2: int
+    p3: int
+
+
+def do_div(n: int, base: int) -> Tuple[int, int]:
+    """Return (n // base, n % base) mirroring do_div macro semantics on *n."""
+    return n // base, n % base
+
+
+def _c_div_trunc(n: int, d: int) -> int:
+    """C99 toward-zero integer division (Python // is floor for negatives)."""
+    if d < 0:
+        n, d = -n, -d
+    if n >= 0:
+        return n // d
+    return -((-n) // d)
+
+
+def apply_correction(ref_freq: int, correction: int) -> int:
+    """Exact C: ref_freq + (int32_t)((((((int64_t)correction) << 31) / 1000000000LL) * ref_freq) >> 31)
+
+    C99 '/' truncates toward zero; '>>' on a negative int64 is arithmetic on
+    gcc (verified against compiled C for +100000 / -50000 ppb).
+    """
+    term = _c_div_trunc(int(correction) << 31, 1_000_000_000) * ref_freq
+    delta = term >> 31  # Python >> is arithmetic for negatives (matches gcc)
+    delta &= 0xFFFFFFFF  # (int32_t) cast
+    if delta >= 0x80000000:
+        delta -= 0x100000000
+    return ref_freq + delta
+
+
+def pll_calc(
+    pll_freq: int,
+    ref_xtal_hz: int = SI5351_XTAL_FREQ,
+    correction: int = 0,
+    vcxo: bool = False,
+) -> Tuple[RegSet, int, Dict[str, int]]:
+    """Mirror Si5351::pll_calc. Returns (reg, return_value, intermediates a/b/c)."""
+    ref_freq = ref_xtal_hz * SI5351_FREQ_MULT
+    ref_freq = apply_correction(ref_freq, correction)
+
+    freq = pll_freq
+    if freq < SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT:
+        freq = SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT
+    if freq > SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT:
+        freq = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT
+
+    a = freq // ref_freq
+    # NOTE: library clamps freq but does NOT recompute `a` (stale a is used
+    # for P1). Mirrored exactly; see spec deviation DEV-PLL-STALE-A.
+    if a < SI5351_PLL_A_MIN:
+        freq = ref_freq * SI5351_PLL_A_MIN
+    if a > SI5351_PLL_A_MAX:
+        freq = ref_freq * SI5351_PLL_A_MAX
+
+    if vcxo:
+        b = ((freq % ref_freq) * 1_000_000) // ref_freq
+        c = 1_000_000
+    else:
+        b = ((freq % ref_freq) * RFRAC_DENOM) // ref_freq
+        c = RFRAC_DENOM if b else 1
+
+    p1 = 128 * a + ((128 * b) // c) - 512
+    p2 = 128 * b - c * ((128 * b) // c)
+    p3 = c
+
+    # Recalculate frequency as fIN * (a + b/c)
+    lltmp = ref_freq * b
+    lltmp, _ = do_div(lltmp, c)
+    freq_out = lltmp + ref_freq * a
+
+    reg = RegSet(p1=p1, p2=p2, p3=p3)
+    if vcxo:
+        ret = 128 * a * 1_000_000 + b
+    else:
+        ret = freq_out
+    return reg, ret, {"a": a, "b": b, "c": c, "ref_freq_corrected": ref_freq}
+
+
+def multisynth_calc(freq: int, pll_freq: int) -> Tuple[RegSet, int, Dict[str, Any]]:
+    """Mirror Si5351::multisynth_calc."""
+    divby4 = 0
+    ret_val = 0
+
+    if freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT
+    if freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT
+
+    if freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT:
+        divby4 = 1
+
+    a = b = c = 0
+    if pll_freq == 0:
+        if divby4 == 0:
+            lltmp = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT
+            lltmp, _ = do_div(lltmp, freq)
+            if lltmp == 5:
+                lltmp = 4
+            elif lltmp == 7:
+                lltmp = 6
+            a = int(lltmp)
+        else:
+            a = 4
+        b = 0
+        c = 1
+        pll_freq = a * freq
+    else:
+        ret_val = 1
+        a = pll_freq // freq
+        # NOTE: library clamps freq but does NOT recompute `a` (stale a).
+        # Mirrored exactly; see spec deviation DEV-MS-STALE-A.
+        if a < SI5351_MULTISYNTH_A_MIN:
+            freq = pll_freq // SI5351_MULTISYNTH_A_MIN
+        if a > SI5351_MULTISYNTH_A_MAX:
+            freq = pll_freq // SI5351_MULTISYNTH_A_MAX
+        b = ((pll_freq % freq) * RFRAC_DENOM) // freq
+        c = RFRAC_DENOM if b else 1
+
+    if divby4 == 1:
+        p3, p2, p1 = 1, 0, 0
+    else:
+        p1 = 128 * a + ((128 * b) // c) - 512
+        p2 = 128 * b - c * ((128 * b) // c)
+        p3 = c
+
+    reg = RegSet(p1=p1, p2=p2, p3=p3)
+    out = pll_freq if ret_val == 0 else freq
+    return reg, out, {"a": a, "b": b, "c": c, "divby4": divby4, "pll_freq_used_or_computed": pll_freq if ret_val == 0 else None}
+
+
+def multisynth67_calc(freq: int, pll_freq: int) -> Tuple[RegSet, int, Dict[str, Any]]:
+    """Mirror Si5351::multisynth67_calc."""
+    if freq > SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT
+    if freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT
+
+    if pll_freq == 0:
+        lltmp = (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT) - 100_000_000
+        lltmp, _ = do_div(lltmp, freq)
+        a = int(lltmp)
+        if a % 2 != 0:
+            a += 1
+        if a < SI5351_MULTISYNTH_A_MIN:
+            a = SI5351_MULTISYNTH_A_MIN
+        if a > SI5351_MULTISYNTH67_A_MAX:
+            a = SI5351_MULTISYNTH67_A_MAX
+        pll_freq = a * freq
+        if pll_freq > (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT):
+            a -= 2
+            pll_freq = a * freq
+        elif pll_freq < (SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT):
+            a += 2
+            pll_freq = a * freq
+        reg = RegSet(p1=a & 0xFF, p2=0, p3=0)
+        return reg, pll_freq, {"a": a}
+    else:
+        if pll_freq % freq:
+            return RegSet(0, 0, 0), 0, {"a": None, "error": "not_integer_divide"}
+        a = pll_freq // freq
+        if a < SI5351_MULTISYNTH_A_MIN or a > SI5351_MULTISYNTH67_A_MAX:
+            return RegSet(0, 0, 0), 0, {"a": a, "error": "a_out_of_range"}
+        reg = RegSet(p1=a & 0xFF, p2=0, p3=0)
+        return reg, 1, {"a": a}
+
+
+def select_r_div(freq: int) -> Tuple[int, int]:
+    """Mirror select_r_div; returns (r_div_code, adjusted_freq)."""
+    r_div = SI5351_OUTPUT_CLK_DIV_1
+    f = freq
+    lo = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT
+    if lo <= f < lo * 2:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_128, f * 128
+    elif lo * 2 <= f < lo * 4:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_64, f * 64
+    elif lo * 4 <= f < lo * 8:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_32, f * 32
+    elif lo * 8 <= f < lo * 16:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_16, f * 16
+    elif lo * 16 <= f < lo * 32:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_8, f * 8
+    elif lo * 32 <= f < lo * 64:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_4, f * 4
+    elif lo * 64 <= f < lo * 128:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_2, f * 2
+    return r_div, f
+
+
+def select_r_div_ms67(freq: int) -> Tuple[int, int]:
+    r_div = SI5351_OUTPUT_CLK_DIV_1
+    f = freq
+    lo = SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT
+    if lo <= f < lo * 2:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_128, f * 128
+    elif lo * 2 <= f < lo * 4:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_64, f * 64
+    elif lo * 4 <= f < lo * 8:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_32, f * 32
+    elif lo * 8 <= f < lo * 16:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_16, f * 16
+    elif lo * 16 <= f < lo * 32:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_8, f * 8
+    elif lo * 32 <= f < lo * 64:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_4, f * 4
+    elif lo * 64 <= f < lo * 128:
+        r_div, f = SI5351_OUTPUT_CLK_DIV_2, f * 2
+    return r_div, f
+
+
+def pack_pll_params(reg: RegSet) -> List[int]:
+    """8 bytes written by set_pll to PLLA_PARAMETERS (26) or PLLB (34)."""
+    params = []
+    params.append((reg.p3 >> 8) & 0xFF)
+    params.append(reg.p3 & 0xFF)
+    params.append((reg.p1 >> 16) & 0x03)
+    params.append((reg.p1 >> 8) & 0xFF)
+    params.append(reg.p1 & 0xFF)
+    params.append(((reg.p3 >> 12) & 0xF0) + ((reg.p2 >> 16) & 0x0F))
+    params.append((reg.p2 >> 8) & 0xFF)
+    params.append(reg.p2 & 0xFF)
+    return params
+
+
+def pack_ms_params(reg: RegSet, prior_reg44_low2: int = 0) -> List[int]:
+    """
+    8 bytes for CLK0-5 MS parameters.
+    Note: set_ms ORs p1[17:16] into existing register+2 low 2 bits after
+    clearing them; prior_reg44_low2 models those preserved upper bits
+    (r_div/divby4 live in same byte but are written later by ms_div).
+    For golden math we report packing with prior=0 (fresh after reset path
+    where ms_div overwrites the byte afterward anyway for r_div/divby4).
+    """
+    params = []
+    params.append((reg.p3 >> 8) & 0xFF)
+    params.append(reg.p3 & 0xFF)
+    # reg_val &= ~0x03; temp = reg_val | (p1>>16 & 0x03)
+    params.append((prior_reg44_low2 & ~0x03) | ((reg.p1 >> 16) & 0x03))
+    params.append((reg.p1 >> 8) & 0xFF)
+    params.append(reg.p1 & 0xFF)
+    params.append(((reg.p3 >> 12) & 0xF0) + ((reg.p2 >> 16) & 0x0F))
+    params.append((reg.p2 >> 8) & 0xFF)
+    params.append(reg.p2 & 0xFF)
+    return params
+
+
+def ms_div_byte_clk05(prior: int, r_div: int, div_by_4: int) -> int:
+    """Final value of MS parameter byte+2 after ms_div for CLK0-5."""
+    reg_val = prior & 0xFF
+    reg_val &= ~(0x7C)
+    if div_by_4:
+        reg_val |= (3 << 2)  # SI5351_OUTPUT_CLK_DIVBY4
+    else:
+        reg_val &= ~((3 << 2))
+    reg_val |= (r_div << 4)
+    return reg_val & 0xFF
+
+
+def simulate_set_freq_clk05(
+    freq_lib: int,
+    pll_assignment: str = "PLLA",
+    existing_pll_freq: int = SI5351_PLL_FIXED,
+    correction: int = 0,
+    xtal_hz: int = SI5351_XTAL_FREQ,
+) -> Dict[str, Any]:
+    """
+    Simulate set_freq for CLK0-5 (single clock, no peer >100 MHz conflict).
+    Mirrors the two branches: > SHARE_MAX recalculates PLL; else uses existing PLL.
+    """
+    freq = freq_lib
+    # bounds
+    if 0 < freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT
+    if freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT
+
+    result: Dict[str, Any] = {
+        "api": "set_freq",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": freq_lib,
+        "input_freq_hz": freq_lib / SI5351_FREQ_MULT,
+        "pll_assignment": pll_assignment,
+        "xtal_hz": xtal_hz,
+        "correction_ppb": correction,
+    }
+
+    if freq > SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT:
+        # recalculate PLL from multisynth_calc(freq, 0)
+        ms_reg, pll_freq, ms_abc = multisynth_calc(freq, 0)
+        pll_reg, pll_ret, pll_abc = pll_calc(pll_freq, xtal_hz, correction, vcxo=False)
+        # then for this clock: select_r_div on clk_freq, multisynth_calc with pll
+        temp_freq = freq
+        r_div, temp_freq = select_r_div(temp_freq)
+        ms_reg2, _, ms_abc2 = multisynth_calc(temp_freq, pll_freq)
+        div_by_4 = 1 if temp_freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT else 0
+        int_mode = 1 if div_by_4 else 0
+        # Note: when >100MHz and not DIVBY4, the first ms_reg from pll_freq==0 is
+        # overwritten by the recalculation loop which uses r_div-adjusted freq.
+        # For freqs >100MHz, r_div is always 1 (freq >> 512kHz), so ms_reg == ms_reg2
+        # when divby4 or integer a from max VCO.
+        result.update({
+            "branch": "recalc_pll_gt_100mhz",
+            "r_div": r_div,
+            "r_div_name": R_DIV_NAMES[r_div],
+            "div_by_4": div_by_4,
+            "int_mode": int_mode,
+            "ms_a": ms_abc2["a"],
+            "ms_b": ms_abc2["b"],
+            "ms_c": ms_abc2["c"],
+            "ms_p1": ms_reg2.p1,
+            "ms_p2": ms_reg2.p2,
+            "ms_p3": ms_reg2.p3,
+            "pll_freq_lib": pll_freq,
+            "pll_freq_hz": pll_freq / SI5351_FREQ_MULT,
+            "pll_a": pll_abc["a"],
+            "pll_b": pll_abc["b"],
+            "pll_c": pll_abc["c"],
+            "pll_p1": pll_reg.p1,
+            "pll_p2": pll_reg.p2,
+            "pll_p3": pll_reg.p3,
+            "pll_packed_bytes": pack_pll_params(pll_reg),
+            "ms_packed_bytes": pack_ms_params(ms_reg2),
+            "ms_div_byte": ms_div_byte_clk05(
+                pack_ms_params(ms_reg2)[2], r_div, div_by_4
+            ),
+            "pll_reset": True,
+        })
+    else:
+        r_div, freq_adj = select_r_div(freq)
+        ms_reg, _, ms_abc = multisynth_calc(freq_adj, existing_pll_freq)
+        pll_reg, _, pll_abc = pll_calc(existing_pll_freq, xtal_hz, correction, vcxo=False)
+        result.update({
+            "branch": "use_existing_pll_le_100mhz",
+            "r_div": r_div,
+            "r_div_name": R_DIV_NAMES[r_div],
+            "freq_after_r_div_lib": freq_adj,
+            "div_by_4": 0,
+            "int_mode": 0,
+            "ms_a": ms_abc["a"],
+            "ms_b": ms_abc["b"],
+            "ms_c": ms_abc["c"],
+            "ms_p1": ms_reg.p1,
+            "ms_p2": ms_reg.p2,
+            "ms_p3": ms_reg.p3,
+            "pll_freq_lib": existing_pll_freq,
+            "pll_freq_hz": existing_pll_freq / SI5351_FREQ_MULT,
+            "pll_a": pll_abc["a"],
+            "pll_b": pll_abc["b"],
+            "pll_c": pll_abc["c"],
+            "pll_p1": pll_reg.p1,
+            "pll_p2": pll_reg.p2,
+            "pll_p3": pll_reg.p3,
+            "note": "set_freq does NOT rewrite PLL in this branch; pll_* shown for reset-time SI5351_PLL_FIXED baseline",
+            "ms_packed_bytes": pack_ms_params(ms_reg),
+            "ms_div_byte": ms_div_byte_clk05(pack_ms_params(ms_reg)[2], r_div, 0),
+            "pll_reset": False,
+        })
+    return result
+
+
+def simulate_set_freq_manual(
+    freq_lib: int,
+    pll_freq: int,
+    correction: int = 0,
+    xtal_hz: int = SI5351_XTAL_FREQ,
+) -> Dict[str, Any]:
+    freq = freq_lib
+    if 0 < freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT
+    if freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT
+
+    r_div, freq_adj = select_r_div(freq)
+    ms_reg, _, ms_abc = multisynth_calc(freq_adj, pll_freq)
+    div_by_4 = 1 if freq_adj >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT else 0
+    int_mode = 1 if div_by_4 else 0
+    pll_reg, _, pll_abc = pll_calc(pll_freq, xtal_hz, correction, vcxo=False)
+
+    return {
+        "api": "set_freq_manual",
+        "clk_path": "CLK0-5",
+        "input_freq_lib": freq_lib,
+        "input_freq_hz": freq_lib / SI5351_FREQ_MULT,
+        "pll_freq_lib": pll_freq,
+        "pll_freq_hz": pll_freq / SI5351_FREQ_MULT,
+        "xtal_hz": xtal_hz,
+        "correction_ppb": correction,
+        "r_div": r_div,
+        "r_div_name": R_DIV_NAMES[r_div],
+        "div_by_4": div_by_4,
+        "int_mode": int_mode,
+        "ms_a": ms_abc["a"],
+        "ms_b": ms_abc["b"],
+        "ms_c": ms_abc["c"],
+        "ms_p1": ms_reg.p1,
+        "ms_p2": ms_reg.p2,
+        "ms_p3": ms_reg.p3,
+        "pll_a": pll_abc["a"],
+        "pll_b": pll_abc["b"],
+        "pll_c": pll_abc["c"],
+        "pll_p1": pll_reg.p1,
+        "pll_p2": pll_reg.p2,
+        "pll_p3": pll_reg.p3,
+        "pll_packed_bytes": pack_pll_params(pll_reg),
+        "ms_packed_bytes": pack_ms_params(ms_reg),
+        "ms_div_byte": ms_div_byte_clk05(pack_ms_params(ms_reg)[2], r_div, div_by_4),
+    }
+
+
+def simulate_set_freq_clk67(
+    freq_lib: int,
+    existing_peer_freq: Optional[int] = None,
+    existing_pllb: Optional[int] = None,
+    correction: int = 0,
+    xtal_hz: int = SI5351_XTAL_FREQ,
+) -> Dict[str, Any]:
+    """Simulate set_freq for CLK6/7 when no peer, or with peer constraint."""
+    freq = freq_lib
+    # lower bound quirk: uses CLKOUT67_MIN but clamps to CLKOUT_MIN (4 kHz) — library bug/quirk
+    if 0 < freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT
+    if freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT:
+        freq = SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT - 1
+
+    result: Dict[str, Any] = {
+        "api": "set_freq",
+        "clk_path": "CLK6/7",
+        "input_freq_lib": freq_lib,
+        "input_freq_hz": freq_lib / SI5351_FREQ_MULT,
+        "pll_assignment": "PLLB",
+        "xtal_hz": xtal_hz,
+        "correction_ppb": correction,
+    }
+
+    if existing_peer_freq and existing_pllb:
+        if existing_pllb % freq != 0 or (existing_pllb // freq) % 2 != 0:
+            result["rejected"] = True
+            result["reason"] = "peer_requires_even_integer_divide_of_pllb"
+            return result
+        r_div, freq_adj = select_r_div_ms67(freq)
+        ms_reg, ret, abc = multisynth67_calc(freq_adj, existing_pllb)
+        if ret == 0:
+            result["rejected"] = True
+            result["reason"] = abc.get("error", "multisynth67_calc_failed")
+            return result
+        pll_reg, _, pll_abc = pll_calc(existing_pllb, xtal_hz, correction)
+        result.update({
+            "rejected": False,
+            "branch": "peer_already_set",
+            "r_div": r_div,
+            "r_div_name": R_DIV_NAMES[r_div],
+            "ms_a": abc["a"],
+            "ms_p1": ms_reg.p1,  # for MS6/7, p1 is the integer a written to single register
+            "ms_p2": 0,
+            "ms_p3": 0,
+            "pll_freq_lib": existing_pllb,
+            "pll_a": pll_abc["a"],
+            "pll_b": pll_abc["b"],
+            "pll_c": pll_abc["c"],
+            "pll_p1": pll_reg.p1,
+            "pll_p2": pll_reg.p2,
+            "pll_p3": pll_reg.p3,
+            "clk67_ms_register_byte": ms_reg.p1 & 0xFF,
+        })
+        return result
+
+    # no peer: set PLLB from multisynth67_calc(freq, 0)
+    r_div, freq_adj = select_r_div_ms67(freq)
+    ms_reg, pll_freq, abc = multisynth67_calc(freq_adj, 0)
+    pll_reg, _, pll_abc = pll_calc(pll_freq, xtal_hz, correction)
+    result.update({
+        "rejected": False,
+        "branch": "set_pllb_from_clk67",
+        "r_div": r_div,
+        "r_div_name": R_DIV_NAMES[r_div],
+        "freq_after_r_div_lib": freq_adj,
+        "ms_a": abc["a"],
+        "ms_p1": ms_reg.p1,
+        "ms_p2": 0,
+        "ms_p3": 0,
+        "pll_freq_lib": pll_freq,
+        "pll_freq_hz": pll_freq / SI5351_FREQ_MULT,
+        "pll_a": pll_abc["a"],
+        "pll_b": pll_abc["b"],
+        "pll_c": pll_abc["c"],
+        "pll_p1": pll_reg.p1,
+        "pll_p2": pll_reg.p2,
+        "pll_p3": pll_reg.p3,
+        "pll_packed_bytes": pack_pll_params(pll_reg),
+        "clk67_ms_register_byte": ms_reg.p1 & 0xFF,
+    })
+    return result
+
+
+def simulate_set_vcxo(
+    pll_freq: int,
+    ppm: int,
+    correction: int = 0,
+    xtal_hz: int = SI5351_XTAL_FREQ,
+) -> Dict[str, Any]:
+    if ppm < SI5351_VCXO_PULL_MIN:
+        ppm = SI5351_VCXO_PULL_MIN
+    if ppm > SI5351_VCXO_PULL_MAX:
+        ppm = SI5351_VCXO_PULL_MAX
+    pll_reg, vcxo_param_raw, pll_abc = pll_calc(pll_freq, xtal_hz, correction, vcxo=True)
+    # vcxo_param = ((vcxo_param * ppm * SI5351_VCXO_MARGIN) / 100ULL) / 1000000ULL;
+    vcxo_param = ((vcxo_param_raw * ppm * SI5351_VCXO_MARGIN) // 100) // 1_000_000
+    return {
+        "api": "set_vcxo",
+        "pll_freq_lib": pll_freq,
+        "pll_freq_hz": pll_freq / SI5351_FREQ_MULT,
+        "ppm": ppm,
+        "xtal_hz": xtal_hz,
+        "correction_ppb": correction,
+        "pll_a": pll_abc["a"],
+        "pll_b": pll_abc["b"],
+        "pll_c": pll_abc["c"],
+        "pll_p1": pll_reg.p1,
+        "pll_p2": pll_reg.p2,
+        "pll_p3": pll_reg.p3,
+        "pll_packed_bytes": pack_pll_params(pll_reg),
+        "vcxo_param_raw_from_pll_calc": vcxo_param_raw,
+        "vcxo_param": vcxo_param,
+        "vcxo_bytes": [
+            vcxo_param & 0xFF,
+            (vcxo_param >> 8) & 0xFF,
+            (vcxo_param >> 16) & 0x3F,
+        ],
+        "regs": {
+            "VXCO_PARAMETERS_LOW(162)": vcxo_param & 0xFF,
+            "VXCO_PARAMETERS_MID(163)": (vcxo_param >> 8) & 0xFF,
+            "VXCO_PARAMETERS_HIGH(164)": (vcxo_param >> 16) & 0x3F,
+        },
+    }
+
+
+def hz(f_hz: float) -> int:
+    """Convert Hz to library units (Hz * 100)."""
+    return int(round(f_hz * SI5351_FREQ_MULT))
+
+
+def build_golden_suite() -> List[Dict[str, Any]]:
+    cases: List[Dict[str, Any]] = []
+
+    # --- P0: common CLK0-5 with default PLL_FIXED after reset ---
+    for i, f_hz in enumerate([14_000_000, 10_000_000, 7_000_000, 28_000_000]):
+        c = simulate_set_freq_clk05(hz(f_hz), "PLLA", SI5351_PLL_FIXED, 0)
+        c["id"] = f"P0-clk0-common-{i+1}-{int(f_hz/1e6)}MHz"
+        c["priority"] = "P0"
+        c["covers"] = ["CLK0-5", "fractional_or_integer_MS", "existing_PLLA_800MHz"]
+        cases.append(c)
+
+    # integer MS example: 800e6 / 16e6 = 50 exactly
+    c = simulate_set_freq_clk05(hz(16_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk0-integer-MS-16MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["CLK0-5", "integer_MS", "b_eq_0"]
+    cases.append(c)
+
+    # fractional MS (14 MHz already fractional); add explicit odd freq
+    c = simulate_set_freq_clk05(hz(14_070_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk0-fractional-MS-14p07MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["CLK0-5", "fractional_MS"]
+    cases.append(c)
+
+    # --- P0: >100 MHz path (recalc PLL) ---
+    c = simulate_set_freq_clk05(hz(112_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk0-gt100MHz-recalc-pll-112MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["CLK0-5", "recalc_pll", "gt_SHARE_MAX"]
+    cases.append(c)
+
+    # --- P0: DIVBY4 path (>=150 MHz) via set_freq_manual (set_freq also uses this in recalc loop) ---
+    c = simulate_set_freq_manual(hz(175_000_000), hz(700_000_000), 0)  # example sketch
+    c["id"] = "P0-manual-DIVBY4-175MHz-pll700"
+    c["priority"] = "P0"
+    c["covers"] = ["DIVBY4", "int_mode", "set_freq_manual", "CLK0-5"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(150_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk0-DIVBY4-boundary-150MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["DIVBY4", "recalc_pll", "a_eq_4"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(200_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk0-DIVBY4-200MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["DIVBY4", "recalc_pll"]
+    cases.append(c)
+
+    # --- P0: PLLB assignment (CLK1 with set_ms_source PLLB, then set_freq <=100MHz uses pllb) ---
+    c = simulate_set_freq_clk05(hz(14_000_000), "PLLB", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-clk1-PLLB-14MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["PLLB_assignment", "CLK0-5"]
+    cases.append(c)
+
+    # --- P0: correction nonzero ---
+    for corr in [100_000, -50_000]:  # ppb
+        c = simulate_set_freq_clk05(hz(14_000_000), "PLLA", SI5351_PLL_FIXED, corr)
+        # Also show effect on PLL register when PLL is rewritten (correction path via set_pll)
+        c["id"] = f"P0-corr-{corr}-14MHz-existing-pll"
+        c["priority"] = "P0"
+        c["covers"] = ["correction_factor"]
+        # For <=100MHz set_freq doesn't rewrite PLL; show set_pll effect explicitly:
+        pll_reg, _, pll_abc = pll_calc(SI5351_PLL_FIXED, SI5351_XTAL_FREQ, corr)
+        c["pll_rewritten_by_set_correction"] = {
+            "pll_a": pll_abc["a"], "pll_b": pll_abc["b"], "pll_c": pll_abc["c"],
+            "pll_p1": pll_reg.p1, "pll_p2": pll_reg.p2, "pll_p3": pll_reg.p3,
+            "pll_packed_bytes": pack_pll_params(pll_reg),
+            "note": "set_correction() calls set_pll(plla_freq) and set_pll(pllb_freq); MS unchanged until next set_freq",
+        }
+        cases.append(c)
+
+    # Correction with >100 MHz so both PLL and MS see corrected ref
+    c = simulate_set_freq_clk05(hz(112_000_000), "PLLA", SI5351_PLL_FIXED, 100_000)
+    c["id"] = "P0-corr-100000-gt100MHz-112MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["correction_factor", "recalc_pll"]
+    cases.append(c)
+
+    # --- P0: R-divider edges ---
+    # CLKOUT_MIN = 4 kHz → R=128 for [4kHz, 8kHz)
+    c = simulate_set_freq_clk05(hz(5_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-rdiv-128-5kHz"
+    c["priority"] = "P0"
+    c["covers"] = ["R_divider", "select_r_div"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(10_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-rdiv-64-10kHz"
+    c["priority"] = "P0"
+    c["covers"] = ["R_divider"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(100_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-rdiv-8-100kHz"
+    c["priority"] = "P0"
+    c["covers"] = ["R_divider"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(400_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-rdiv-2-400kHz"
+    c["priority"] = "P0"
+    c["covers"] = ["R_divider"]
+    cases.append(c)
+
+    c = simulate_set_freq_clk05(hz(512_000), "PLLA", SI5351_PLL_FIXED, 0)
+    c["id"] = "P0-rdiv-1-512kHz-boundary"
+    c["priority"] = "P0"
+    c["covers"] = ["R_divider", "no_r_div"]
+    cases.append(c)
+
+    # --- P0: CLK6/7 ---
+    c = simulate_set_freq_clk67(hz(23_000_000))  # example: library sets PLL ~874 MHz
+    c["id"] = "P0-clk6-23MHz"
+    c["priority"] = "P0"
+    c["covers"] = ["CLK6/7", "multisynth67_calc", "PLLB"]
+    cases.append(c)
+
+    # CLK7 with peer CLK6: 87.4 MHz works if pllb is 874 MHz (874/87.4=10 even)
+    pllb = c["pll_freq_lib"]
+    c7 = simulate_set_freq_clk67(hz(87_400_000), existing_peer_freq=hz(23_000_000), existing_pllb=pllb)
+    c7["id"] = "P0-clk7-874MHz-even-div-of-clk6-pll"
+    c7["priority"] = "P0"
+    c7["covers"] = ["CLK6/7", "peer_even_integer"]
+    cases.append(c7)
+
+    # Reject non-integer / odd divide (12345678 Hz from example)
+    c_bad = simulate_set_freq_clk67(hz(12_345_678), existing_peer_freq=hz(23_000_000), existing_pllb=pllb)
+    c_bad["id"] = "P0-clk7-reject-noninteger-12p345678MHz"
+    c_bad["priority"] = "P0"
+    c_bad["covers"] = ["CLK6/7", "reject_path"]
+    cases.append(c_bad)
+
+    # --- P0: VCXO ---
+    c = simulate_set_vcxo(hz(876_000_000), 40)  # example sketch
+    c["id"] = "P0-vcxo-876MHz-40ppm"
+    c["priority"] = "P0"
+    c["covers"] = ["set_vcxo", "PLLB", "vcxo_param"]
+    cases.append(c)
+
+    # VCXO + manual MS for 146 MHz (example)
+    c = simulate_set_freq_manual(hz(146_000_000), hz(876_000_000), 0)
+    c["id"] = "P0-vcxo-manual-146MHz-on-876pll"
+    c["priority"] = "P0"
+    c["covers"] = ["set_freq_manual", "VCXO_companion", "near_DIVBY4"]
+    cases.append(c)
+
+    # --- P1: set_freq vs set_freq_manual parity ---
+    # For freq <=100 MHz with same PLL, MS params should match if r_div/path same.
+    auto = simulate_set_freq_clk05(hz(14_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    manual = simulate_set_freq_manual(hz(14_000_000), SI5351_PLL_FIXED, 0)
+    parity = {
+        "id": "P1-parity-set_freq-vs-manual-14MHz-pll800",
+        "priority": "P1",
+        "covers": ["set_freq_vs_set_freq_manual_parity"],
+        "api": "parity_check",
+        "description": (
+            "For freq<=100 MHz, set_freq uses existing PLL and does not call set_pll; "
+            "set_freq_manual always calls set_pll(pll_freq). MS a/b/c and p1/p2/p3 must match "
+            "when the same pll_freq is supplied. Differences: set_freq_manual always "
+            "output_enable(1); set_freq enables only on first set. set_freq skips pll_reset "
+            "in <=100 MHz branch; set_freq_manual does not reset either."
+        ),
+        "auto_ms": {"a": auto["ms_a"], "b": auto["ms_b"], "c": auto["ms_c"],
+                    "p1": auto["ms_p1"], "p2": auto["ms_p2"], "p3": auto["ms_p3"],
+                    "r_div": auto["r_div"], "div_by_4": auto["div_by_4"]},
+        "manual_ms": {"a": manual["ms_a"], "b": manual["ms_b"], "c": manual["ms_c"],
+                      "p1": manual["ms_p1"], "p2": manual["ms_p2"], "p3": manual["ms_p3"],
+                      "r_div": manual["r_div"], "div_by_4": manual["div_by_4"]},
+        "ms_match": (
+            auto["ms_a"] == manual["ms_a"] and auto["ms_b"] == manual["ms_b"]
+            and auto["ms_c"] == manual["ms_c"]
+            and auto["ms_p1"] == manual["ms_p1"] and auto["ms_p2"] == manual["ms_p2"]
+            and auto["ms_p3"] == manual["ms_p3"]
+            and auto["r_div"] == manual["r_div"] and auto["div_by_4"] == manual["div_by_4"]
+        ),
+        "manual_also_writes_pll": True,
+        "manual_pll": {"a": manual["pll_a"], "b": manual["pll_b"], "c": manual["pll_c"],
+                       "p1": manual["pll_p1"], "p2": manual["pll_p2"], "p3": manual["pll_p3"]},
+    }
+    cases.append(parity)
+
+    # High-freq parity: set_freq(175e6) recalc vs manual(175e6, computed_pll)
+    auto_hi = simulate_set_freq_clk05(hz(175_000_000), "PLLA", SI5351_PLL_FIXED, 0)
+    # set_freq for >100 uses multisynth_calc(freq,0) → pll = a*freq with a=4 for DIVBY4
+    manual_hi = simulate_set_freq_manual(hz(175_000_000), auto_hi["pll_freq_lib"], 0)
+    parity2 = {
+        "id": "P1-parity-gt100-set_freq-vs-manual-175MHz",
+        "priority": "P1",
+        "covers": ["set_freq_vs_set_freq_manual_parity", "DIVBY4"],
+        "api": "parity_check",
+        "description": (
+            "set_freq(175 MHz) chooses pll_freq via multisynth_calc(freq,0) → a=4, pll=700 MHz. "
+            "set_freq_manual(175 MHz, 700 MHz) must yield identical MS p1/p2/p3, div_by_4=1, int_mode=1 "
+            "and identical PLL a/b/c when correction matches."
+        ),
+        "auto": auto_hi,
+        "manual": manual_hi,
+        "ms_match": (
+            auto_hi["ms_p1"] == manual_hi["ms_p1"]
+            and auto_hi["ms_p2"] == manual_hi["ms_p2"]
+            and auto_hi["ms_p3"] == manual_hi["ms_p3"]
+            and auto_hi["div_by_4"] == manual_hi["div_by_4"]
+        ),
+        "pll_match": (
+            auto_hi["pll_p1"] == manual_hi["pll_p1"]
+            and auto_hi["pll_p2"] == manual_hi["pll_p2"]
+            and auto_hi["pll_p3"] == manual_hi["pll_p3"]
+        ),
+    }
+    cases.append(parity2)
+
+    # --- P1: reset-time PLL_FIXED baseline ---
+    pll_reg, _, pll_abc = pll_calc(SI5351_PLL_FIXED, SI5351_XTAL_FREQ, 0)
+    cases.append({
+        "id": "P1-reset-pll-fixed-800MHz",
+        "priority": "P1",
+        "covers": ["reset", "SI5351_PLL_FIXED", "set_pll"],
+        "api": "set_pll",
+        "pll_freq_lib": SI5351_PLL_FIXED,
+        "pll_freq_hz": 800_000_000,
+        "xtal_hz": SI5351_XTAL_FREQ,
+        "correction_ppb": 0,
+        "pll_a": pll_abc["a"],
+        "pll_b": pll_abc["b"],
+        "pll_c": pll_abc["c"],
+        "pll_p1": pll_reg.p1,
+        "pll_p2": pll_reg.p2,
+        "pll_p3": pll_reg.p3,
+        "pll_packed_bytes": pack_pll_params(pll_reg),
+        "note": "reset() calls set_pll(SI5351_PLL_FIXED) for both PLLA and PLLB",
+    })
+
+    # Scenario metadata (which CLK / PLL the example or case targets)
+    meta = {
+        "P0-clk1-PLLB-14MHz": (1, "PLLB"),
+        "P0-manual-DIVBY4-175MHz-pll700": (1, "PLLB"),   # si5351_example.ino uses CLK1 on PLLB
+        "P0-clk6-23MHz": (6, "PLLB"),
+        "P0-clk7-874MHz-even-div-of-clk6-pll": (7, "PLLB"),
+        "P0-clk7-reject-noninteger-12p345678MHz": (7, "PLLB"),
+        "P0-vcxo-876MHz-40ppm": (0, "PLLB"),
+        "P0-vcxo-manual-146MHz-on-876pll": (0, "PLLB"),  # si5351_vcxo.ino uses CLK0 on PLLB
+    }
+    for c in cases:
+        clk, pll = meta.get(c["id"], (0, c.get("pll_assignment", "PLLA")))
+        c["clk"] = clk
+        if c.get("api") in ("set_freq", "set_freq_manual", "set_vcxo"):
+            c["pll_assignment"] = pll
+        if c["id"] == "P0-vcxo-manual-146MHz-on-876pll":
+            c["vcxo_context"] = True
+        annotate_library_regs(c)
+    return cases
+
+
+
+# ---------------------------------------------------------------------------
+# Library register-level mirrors (addressed bytes as the library writes them)
+# ---------------------------------------------------------------------------
+REG_CLK0_CTRL = 16
+REG_PLLA = 26
+REG_PLLB = 34
+REG_CLK0_PARAMS = 42
+REG_CLK67_DIV = 92
+
+
+def lib_pll_regs(pll: str, reg: RegSet) -> Dict[str, int]:
+    base = REG_PLLA if pll == "PLLA" else REG_PLLB
+    return {str(base + i): v for i, v in enumerate(pack_pll_params(reg))}
+
+
+def lib_ms_regs(clk: int, reg: RegSet, r_div: int, div_by_4: int, prior44: int = 0) -> Dict[str, int]:
+    """set_ms bulk write followed by ms_div RMW of byte +2.
+
+    prior44 is the pre-existing value of MS parameter byte+2 (reg 44+8*clk).
+    Library sequence (si5351.cpp set_ms + ms_div):
+      1. set_ms:  read byte+2; clear bits 1:0; OR P1[17:16]; include in 8-byte bulk write
+         -> preserves bits 7:2 of prior (R_DIV/DIVBY4/unused) during the bulk write
+      2. ms_div:  read byte+2; clear bits 6:2 (0x7C); OR R_DIV<<4 and DIVBY4; write
+         -> preserves bits 1:0 (P1[17:16]) and bit 7 (unused)
+    A naive full-byte overwrite at either step fails the packed-bytes golden.
+    """
+    base = REG_CLK0_PARAMS + 8 * clk
+    b = pack_ms_params(reg, prior44)
+    after_set_ms_byte2 = b[2]
+    b[2] = ms_div_byte_clk05(b[2], r_div, div_by_4)
+    return {str(base + i): v for i, v in enumerate(b)}
+
+
+def lib_ms_byte2_rmw_transcript(clk: int, reg: RegSet, r_div: int, div_by_4: int, prior44: int) -> Dict[str, Any]:
+    """Wire-stub transcript of the two RMWs on MS parameter byte+2. Future I2C mock must assert these."""
+    addr = REG_CLK0_PARAMS + 8 * clk + 2
+    after_set_ms = (prior44 & ~0x03) | ((reg.p1 >> 16) & 0x03)
+    after_ms_div = ms_div_byte_clk05(after_set_ms, r_div, div_by_4)
+    return {
+        "reg": addr,
+        "prior": prior44,
+        "steps": [
+            {"op": "si5351_read", "reg": addr, "returns": prior44,
+             "note": "set_ms RMW start"},
+            {"op": "si5351_write_bulk_byte2", "reg": addr, "value": after_set_ms,
+             "mask_cleared": 0x03, "bits_preserved": "7:2",
+             "note": "set_ms: reg_val &= ~0x03; |= P1[17:16]"},
+            {"op": "si5351_read", "reg": addr, "returns": after_set_ms,
+             "note": "ms_div RMW start"},
+            {"op": "si5351_write", "reg": addr, "value": after_ms_div,
+             "mask_cleared": 0x7C, "bits_preserved": "7 and 1:0",
+             "note": "ms_div: reg_val &= ~0x7C; |= R_DIV<<4 | DIVBY4"},
+        ],
+        "final": after_ms_div,
+        "mutation_detectors": {
+            "naive_ms_div_overwrite": (r_div << 4) | ((0x0C) if div_by_4 else 0),
+            "naive_set_ms_then_correct_ms_div": ms_div_byte_clk05((reg.p1 >> 16) & 0x03, r_div, div_by_4),
+            "note": ("naive_ms_div_overwrite loses P1[17:16] and bit7; "
+                     "naive_set_ms_then_correct_ms_div loses bit7 (and any prior R_DIV/DIVBY4 mid-bulk)"),
+        },
+    }
+
+
+def lib_ctrl_after_reset(clk: int, pll: str) -> int:
+    """reset(): write 0x80 then 0x0C to regs 16-23, then set_ms_source per default map;
+    a later set_ms_source(clk, PLLB) sets bit5."""
+    v = 0x0C
+    if pll == "PLLB":
+        v |= 0x20
+    return v
+
+
+def lib_set_int(prior: int, enable: int) -> int:
+    return (prior | 0x40) if enable == 1 else (prior & ~0x40 & 0xFF)
+
+
+def lib_ms_div_clk67(prior: int, clk: int, r_div: int) -> int:
+    if clk == 6:
+        return ((prior & ~0x07) | r_div) & 0xFF
+    return ((prior & ~0x70) | (r_div << 4)) & 0xFF
+
+
+def lib_output_enable(prior: int, clk: int, enable: int) -> int:
+    return (prior & ~(1 << clk)) & 0xFF if enable == 1 else (prior | (1 << clk)) & 0xFF
+
+
+REG3_AFTER_RESET = 0xFF  # reset(): output_enable(i, 0) for i=0..7 (prior assumed 0x00)
+
+
+def annotate_library_regs(c: Dict[str, Any]) -> Dict[str, Any]:
+    """Attach AN619-addressed register bytes as the LIBRARY would write them."""
+    api = c.get("api")
+    clk = c.get("clk", 0)
+    pll = c.get("pll_assignment", "PLLA")
+    if c.get("clk_path") == "CLK0-5" and "ms_p1" in c:
+        c["lib_ms_regs"] = lib_ms_regs(clk, RegSet(c["ms_p1"], c["ms_p2"], c["ms_p3"]), c["r_div"], c["div_by_4"])
+        c["lib_clk_ctrl"] = {str(REG_CLK0_CTRL + clk): lib_set_int(lib_ctrl_after_reset(clk, pll), c["int_mode"])}
+        c["lib_reg3_after"] = lib_output_enable(REG3_AFTER_RESET, clk, 1)
+    if c.get("clk_path") == "CLK6/7" and not c.get("rejected"):
+        c["lib_ms67_regs"] = {str(90 + clk - 6): c["ms_p1"] & 0xFF}
+        c["lib_reg92"] = lib_ms_div_clk67(0, clk, c["r_div"])
+        # set_ms() for CLK6/7 does not call set_int(); ctrl stays at reset value (PLLB)
+        c["lib_clk_ctrl"] = {str(REG_CLK0_CTRL + clk): lib_ctrl_after_reset(clk, "PLLB")}
+        # set_freq() CLK6/7 branch never calls output_enable(): OEB bit stays 1
+        c["lib_reg3_after"] = REG3_AFTER_RESET
+    if "pll_p1" in c and api != "set_vcxo":
+        c["lib_pll_regs"] = lib_pll_regs("PLLB" if c.get("clk_path") == "CLK6/7" else pll,
+                                         RegSet(c["pll_p1"], c["pll_p2"], c["pll_p3"]))
+    if api == "set_vcxo":
+        c["lib_pll_regs"] = lib_pll_regs("PLLB", RegSet(c["pll_p1"], c["pll_p2"], c["pll_p3"]))
+        c["lib_vcxo_regs"] = {"162": c["vcxo_bytes"][0], "163": c["vcxo_bytes"][1], "164": c["vcxo_bytes"][2]}
+    return c
+
+
+def build_spec_coverage_cases() -> List[Dict[str, Any]]:
+    """New cases added for AN619/datasheet coverage (library-side values only;
+    spec-side values are computed independently by spec_crosscheck.py)."""
+    cases: List[Dict[str, Any]] = []
+
+    def add(c, cid, covers, clk=0, pll="PLLA", **extra):
+        c["id"], c["priority"], c["covers"], c["clk"] = cid, "S", covers, clk
+        c.setdefault("pll_assignment", pll)
+        c.update(extra)
+        cases.append(annotate_library_regs(c))
+
+    # S: full PLL blocks after reset() + PLL reset writes
+    reg, _, abc = pll_calc(SI5351_PLL_FIXED)
+    cases.append({
+        "id": "S-reset-pll-blocks-and-reg177", "priority": "S", "api": "reset_plls",
+        "covers": ["MSNA regs 26-33", "MSNB regs 34-41", "PLL reset reg 177", "CLK ctrl regs 16-23"],
+        "pll_freq_hz": 800_000_000, "xtal_hz": SI5351_XTAL_FREQ, "correction_ppb": 0,
+        "pll_a": abc["a"], "pll_b": abc["b"], "pll_c": abc["c"],
+        "pll_p1": reg.p1, "pll_p2": reg.p2, "pll_p3": reg.p3,
+        "lib_plla_regs": lib_pll_regs("PLLA", reg), "lib_pllb_regs": lib_pll_regs("PLLB", reg),
+        "lib_reg177_writes": [0x20, 0x80],  # pll_reset(PLLA) then pll_reset(PLLB)
+        "lib_clk_ctrl": {str(16 + i): lib_ctrl_after_reset(i, "PLLB" if i >= 6 else "PLLA") for i in range(8)},
+        "lib_reg3_after": REG3_AFTER_RESET,
+    })
+
+    add(simulate_set_freq_clk05(hz(10_000_000)), "S-ms5-block-10MHz-clk5",
+        ["MS5 regs 82-89 address offset", "reg 21"], clk=5)
+    add(simulate_set_freq_clk05(hz(5_000)), "S-rdiv-placement-clk2-5kHz",
+        ["R2_DIV bits 6:4 of reg 60", "MS2 regs 58-65"], clk=2)
+    add(simulate_set_freq_clk05(hz(200_000_000)), "S-divby4-block-clk3-200MHz",
+        ["MS3_DIVBY4 bits 3:2 of reg 68", "MS3_INT reg 19 bit6", "MSNA block"], clk=3)
+    add(simulate_set_freq_clk05(hz(112_500_000)), "S-boundary-112p5MHz-ratio8",
+        ["AN619 2.1.1 900/8 boundary", "integer ratio 8"], clk=0)
+
+    c = simulate_set_freq_clk67(hz(100_000))
+    add(c, "S-clk6-R6div-100kHz", ["R6_DIV bits 2:0 of reg 92", "reg 90"], clk=6, pll="PLLB")
+    c = simulate_set_freq_clk67(hz(50_000))
+    add(c, "S-clk7-R7div-50kHz", ["R7_DIV bits 6:4 of reg 92", "reg 91"], clk=7, pll="PLLB")
+    c = simulate_set_freq_clk67(hz(150_000_000))
+    add(c, "S-clk6-150MHz-upper-clamp", ["CLK6 upper bound", "MS6 ratio 6"], clk=6, pll="PLLB")
+
+    add(simulate_set_vcxo(hz(800_000_000), 100), "S-vcxo-800MHz-100ppm", ["VCXO regs 162-164", "c=10^6"],
+        clk=0, pll="PLLB")
+    add(simulate_set_vcxo(hz(876_000_000), 10), "S-vcxo-ppm-clamp-low-10to30", ["VCXO APR min 30"],
+        clk=0, pll="PLLB", requested_ppm=10)
+    add(simulate_set_vcxo(hz(876_000_000), 250), "S-vcxo-ppm-clamp-high-250to240", ["VCXO APR max 240"],
+        clk=0, pll="PLLB", requested_ppm=250)
+
+    cases.append({"id": "S-phase-clk0-mask", "priority": "S", "api": "set_phase", "covers": ["reg 165", "PHOFF[6:0]"],
+                  "clk": 0, "requested_phase": 0xFF, "lib_write": {"reg": 165 + 0, "value": 0xFF & 0x7F}})
+    cases.append({"id": "S-xtal-load-6-8-10pF", "priority": "S", "api": "init_xtal_load", "covers": ["reg 183"],
+                  "lib_writes": {"6pF": (1 << 6 & 0xC0) | 0x12, "8pF": (2 << 6 & 0xC0) | 0x12,
+                                 "10pF": (3 << 6 & 0xC0) | 0x12}})
+
+    # ---- D: scenarios that expose library-vs-spec deviations (library behaviour locked) ----
+    add(simulate_set_freq_clk05(hz(210_000_000)), "D-clk0-210MHz-above-spec-max", ["Fout max 200 MHz"])
+    add(simulate_set_freq_clk05(hz(250_000_000)), "D-clk0-250MHz-clamped-to-225", ["Fout max 200 MHz", "clamp"])
+    add(simulate_set_freq_clk05(hz(2_500)), "D-clk0-2p5kHz-clamped-to-4kHz", ["Fout min 2.5 kHz"], clk=0)
+    c = simulate_set_freq_clk67(hz(10_000))
+    c["pllb_freq_member_lib"] = c["pll_freq_lib"]
+    add(c, "D-clk6-10kHz-ms6-p1-zero", ["MS6 even 6..254", "uint8 truncation"], clk=6, pll="PLLB")
+    m = simulate_set_freq_manual(hz(100_000_000), hz(700_000_000))
+    add(m, "D-manual-100MHz-pll700-ratio7", ["MS ratio 7 invalid"], clk=0)
+    m = simulate_set_freq_manual(hz(90_000_000), hz(600_000_000))
+    add(m, "D-manual-90MHz-pll600-ratio6p67", ["MS fractional ratio < 8 invalid"], clk=0)
+    m = simulate_set_freq_manual(hz(140_000_000), hz(700_000_000))
+    add(m, "D-manual-140MHz-pll700-stale-a5", ["multisynth_calc stale a after a<6 clamp"], clk=0)
+    m = simulate_set_freq_manual(hz(175_000_000), hz(800_000_000))
+    add(m, "D-manual-175MHz-pll800-divby4-precondition", ["DIVBY4 requires fVCO = 4*Fout"], clk=0)
+
+    # set_vcxo(876 MHz) leaves pllb_freq member at 800 MHz; set_correction() then rewrites PLLB
+    reg_v, raw, abc_v = pll_calc(hz(876_000_000), vcxo=True)
+    reg_b, _, abc_b = pll_calc(SI5351_PLL_FIXED)
+    cases.append({
+        "id": "D-vcxo-then-set_correction-clobbers-pllb", "priority": "S", "api": "vcxo_sequence",
+        "covers": ["set_vcxo does not update pllb_freq", "VCXO c=10^6"],
+        "sequence": ["reset()", "set_vcxo(87600000000ULL, 40)", "set_correction(0, SI5351_PLL_INPUT_XO)"],
+        "vcxo_context": True,
+        "pllb_after_set_vcxo": {"a": abc_v["a"], "b": abc_v["b"], "c": abc_v["c"],
+                                "p1": reg_v.p1, "p2": reg_v.p2, "p3": reg_v.p3},
+        "pllb_freq_member_lib": SI5351_PLL_FIXED,
+        "pll_a": abc_b["a"], "pll_b": abc_b["b"], "pll_c": abc_b["c"],
+        "pll_p1": reg_b.p1, "pll_p2": reg_b.p2, "pll_p3": reg_b.p3,
+        "lib_pll_regs": lib_pll_regs("PLLB", reg_b), "xtal_hz": SI5351_XTAL_FREQ, "correction_ppb": 0,
+    })
+    # set_vcxo(875 MHz) then set_freq_manual(..., 875 MHz) -> set_pll() non-VCXO path gives c=1 (b==0)
+    reg_v2, _, abc_v2 = pll_calc(hz(875_000_000), vcxo=True)
+    m = simulate_set_freq_manual(hz(87_500_000), hz(875_000_000))
+    m["sequence"] = ["reset()", "set_vcxo(87500000000ULL, 40)", "set_ms_source(SI5351_CLK0, SI5351_PLLB)",
+                     "set_freq_manual(8750000000ULL, 87500000000ULL, SI5351_CLK0)"]
+    m["pllb_after_set_vcxo"] = {"a": abc_v2["a"], "b": abc_v2["b"], "c": abc_v2["c"],
+                                "p1": reg_v2.p1, "p2": reg_v2.p2, "p3": reg_v2.p3}
+    add(m, "D-vcxo-875MHz-then-manual-rewrites-c1", ["VCXO c=10^6 lost via set_pll"], clk=0, pll="PLLB",
+        vcxo_context=True)
+
+    # set_freq_manual() has no CLK6/7 guard: multisynth_calc (fractional MS0-5 math) + select_r_div,
+    # then set_ms() writes (uint8_t)ms_reg.p1 to reg 90/91.
+    m = simulate_set_freq_manual(hz(87_400_000), hz(874_000_000))
+    m.update({"id": "D-manual-clk7-87p4MHz-p1-truncated", "priority": "S", "clk": 7, "clk_path": "CLK6/7",
+              "api": "set_freq_manual", "pll_assignment": "PLLB",
+              "covers": ["set_freq_manual on CLK6/7", "reg 91"],
+              "sequence": ["reset()", "set_freq_manual(8740000000ULL, 87400000000ULL, SI5351_CLK7)"],
+              "lib_ms67_regs": {"91": m["ms_p1"] & 0xFF},
+              "lib_reg92": lib_ms_div_clk67(0, 7, m["r_div"]),
+              "lib_clk_ctrl": {"23": lib_ctrl_after_reset(7, "PLLB")},
+              "lib_reg3_after": lib_output_enable(REG3_AFTER_RESET, 7, 1),
+              "lib_pll_regs": lib_pll_regs("PLLB", RegSet(m["pll_p1"], m["pll_p2"], m["pll_p3"]))})
+    cases.append(m)
+    cases.append({"id": "D-set_phase-clk6-writes-reserved-171", "priority": "S", "api": "set_phase",
+                  "covers": ["phase regs only CLK0-5"], "clk": 6, "requested_phase": 10,
+                  "lib_write": {"reg": 165 + 6, "value": 10 & 0x7F}})
+    cases.append({"id": "D-init-crystal-load-0pF-reserved", "priority": "S", "api": "init_xtal_load",
+                  "covers": ["XTAL_CL=00 reserved"], "lib_writes": {"0pF": (0 & 0xC0) | 0x12}})
+    # set_int(CLK6,1) after set_correction(100000) made MSNA fractional
+    reg_c, _, abc_c = pll_calc(SI5351_PLL_FIXED, correction=100_000)
+    cases.append({"id": "D-set_int-clk6-sets-FBA_INT-on-fractional-plla", "priority": "S", "api": "set_int",
+                  "covers": ["reg 22 bit6 = FBA_INT"], "clk": 6,
+                  "sequence": ["reset()", "set_correction(100000, SI5351_PLL_INPUT_XO)", "set_int(SI5351_CLK6, 1)"],
+                  "lib_write": {"reg": 22, "value": lib_set_int(lib_ctrl_after_reset(6, "PLLB"), 1)},
+                  "plla": {"a": abc_c["a"], "b": abc_c["b"], "c": abc_c["c"],
+                           "p1": reg_c.p1, "p2": reg_c.p2, "p3": reg_c.p3}})
+    # set_pll_input: reg_val |= clkin_div without clearing CLKIN_DIV[1:0]
+    prior15 = 0x40 | 0x04  # earlier CLKIN_DIV=/2 and PLLA_SRC=CLKIN
+    cases.append({"id": "D-set_pll_input-clkin_div-or-without-clear", "priority": "S", "api": "set_pll_input",
+                  "covers": ["reg 15 CLKIN_DIV[1:0]"],
+                  "sequence": ["(reg15 = 0x44 from earlier CLKIN @ 40 MHz)", "set_ref_freq(80000000, CLKIN)",
+                               "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"],
+                  "prior_reg15": prior15, "intended_clkin_div": 4,
+                  "lib_write": {"reg": 15, "value": prior15 | 0x04 | (2 << 6)}})
+    # Non-standard 5 MHz reference: pll_calc clamps freq but keeps stale a=160
+    reg5, ret5, abc5 = pll_calc(SI5351_PLL_FIXED, ref_xtal_hz=5_000_000)
+    cases.append({"id": "D-ref5MHz-pll_calc-stale-a160", "priority": "S", "api": "set_pll",
+                  "covers": ["feedback ratio 15..90", "PLL input 10..40 MHz"],
+                  "sequence": ["init(SI5351_CRYSTAL_LOAD_8PF, 5000000, 0)  -> reset() -> set_pll(800 MHz)"],
+                  "pll_freq_lib": SI5351_PLL_FIXED, "xtal_hz": 5_000_000, "correction_ppb": 0,
+                  "pll_a": abc5["a"], "pll_b": abc5["b"], "pll_c": abc5["c"],
+                  "pll_p1": reg5.p1, "pll_p2": reg5.p2, "pll_p3": reg5.p3,
+                  "pll_calc_return_lib": ret5, "lib_pll_regs": lib_pll_regs("PLLA", reg5)})
+    # F: Jason's short frequency check list (FREQ_CHECKS.md) - cases not already present
+    add(simulate_set_freq_clk05(hz(100_000_000)), "F-clk0-100MHz-share-max-boundary",
+        ["<=100 MHz branch boundary", "ratio 8 on 800 MHz"], clk=0)
+    add(simulate_set_freq_clk05(hz(4_000)), "F-clk0-4kHz-library-min",
+        ["CLKOUT_MIN", "R=128"], clk=0)
+
+    # =========================================================================
+    # M: mutation gaps found by Coding PM's original-vs-refactor harness
+    # =========================================================================
+
+    # M1: CLK7 default PLL assignment is PLLB (mutation: swap to PLLA)
+    # AN619 §4.1.1: MSx_SRC may be PLLA or PLLB; library reset() hard-codes CLK6/7 → PLLB.
+    cases.append({
+        "id": "M-clk7-pllb-assignment", "priority": "M", "api": "reset_pll_assignment",
+        "covers": ["CLK7 → PLLB after reset", "reg 23 MS7_SRC bit5", "mutation: CLK7→PLLA"],
+        "clk": 7,
+        "pll_assignment": "PLLB",
+        "pll_assignment_table": {str(i): ("PLLB" if i >= 6 else "PLLA") for i in range(8)},
+        "lib_clk_ctrl": {str(16 + i): lib_ctrl_after_reset(i, "PLLB" if i >= 6 else "PLLA") for i in range(8)},
+        "lib_write": {"reg": 23, "value": lib_ctrl_after_reset(7, "PLLB")},  # 0x2C: MS7_SRC=1
+        "mutation_fail_if": {
+            "clk7_ctrl_equals": lib_ctrl_after_reset(7, "PLLA"),  # 0x0C would mean PLLA
+            "pll_assignment_7": "PLLA",
+        },
+        "spec_note": ("AN619 §4.1.1 / Reg 23 MS7_SRC: 0=PLLA, 1=PLLB/VCXO — either legal when no "
+                      "spread-spectrum/VCXO constraint. Library reset() chooses PLLB for CLK7; that "
+                      "choice is the regression lock. Spec agrees the bit encoding; does not mandate PLLB."),
+    })
+
+    # M2: set_ms + ms_div byte+2 RMW bit preservation (prior bit7 set, R_DIV=128, P1[17:16]=2)
+    c5 = simulate_set_freq_clk05(hz(5_000))
+    prior44 = 0xFF  # leftover bits incl. unused bit7; would be wiped by a naive overwrite
+    regs = lib_ms_regs(0, RegSet(c5["ms_p1"], c5["ms_p2"], c5["ms_p3"]), c5["r_div"], 0, prior44=prior44)
+    transcript = lib_ms_byte2_rmw_transcript(0, RegSet(c5["ms_p1"], c5["ms_p2"], c5["ms_p3"]), c5["r_div"], 0, prior44)
+    assert regs["44"] == 0xF2, hex(regs["44"])  # bit7|R=111|DIVBY4=00|P1hi=10
+    assert transcript["final"] == 0xF2
+    assert transcript["mutation_detectors"]["naive_ms_div_overwrite"] == 0x70  # loses P1hi+bit7
+    assert transcript["mutation_detectors"]["naive_set_ms_then_correct_ms_div"] == 0x72  # loses bit7
+    c5.update({
+        "id": "M-set-ms-byte2-rmw", "priority": "M", "api": "set_ms_rmw",
+        "covers": ["set_ms byte+2 RMW", "ms_div byte+2 RMW", "bit7 preserve", "P1[17:16] preserve"],
+        "clk": 0, "pll_assignment": "PLLA",
+        "clk_path": None,  # force set_ms_rmw evaluator (not CLK0-5 path)
+        "prior_byte2": prior44,
+        "lib_ms_regs": regs,
+        "lib_clk_ctrl": {"16": lib_set_int(lib_ctrl_after_reset(0, "PLLA"), 0)},
+        "lib_reg3_after": lib_output_enable(REG3_AFTER_RESET, 0, 1),
+        "rmw_transcript": transcript,
+        "wire_stub_must_assert": (
+            "Future Wire stub: (1) set_ms bulk byte at reg 44 must equal (prior & ~0x03) | P1[17:16] "
+            "— bits 7:2 survive; (2) ms_div write at reg 44 must equal that value with bits 6:2 replaced "
+            "by R_DIV/DIVBY4 — bits 7 and 1:0 survive. Final byte MUST be 0xF2 for this case, NOT 0x70 or 0x72."
+        ),
+    })
+    # also keep pll fields from simulate
+    c5["lib_pll_regs"] = lib_pll_regs("PLLA", RegSet(c5["pll_p1"], c5["pll_p2"], c5["pll_p3"]))
+    cases.append(c5)
+
+    # M3: CLK5 → PLLA after reset (mutation: CLK5→PLLB)
+    cases.append({
+        "id": "M-clk5-reset-plla", "priority": "M", "api": "reset_pll_assignment",
+        "covers": ["CLK5 → PLLA after reset", "reg 21 MS5_SRC bit5", "mutation: CLK5→PLLB"],
+        "clk": 5,
+        "pll_assignment": "PLLA",
+        "pll_assignment_table": {str(i): ("PLLB" if i >= 6 else "PLLA") for i in range(8)},
+        "lib_clk_ctrl": {str(16 + i): lib_ctrl_after_reset(i, "PLLB" if i >= 6 else "PLLA") for i in range(8)},
+        "lib_write": {"reg": 21, "value": lib_ctrl_after_reset(5, "PLLA")},  # 0x0C: MS5_SRC=0
+        "mutation_fail_if": {
+            "clk5_ctrl_equals": lib_ctrl_after_reset(5, "PLLB"),  # 0x2C would mean PLLB
+            "pll_assignment_5": "PLLB",
+        },
+        "spec_note": ("AN619 §4.1.1 / Reg 21 MS5_SRC: 0=PLLA, 1=PLLB. Library reset() chooses PLLA for "
+                      "CLK0–5; that choice is the regression lock."),
+    })
+
+    # =========================================================================
+    # A: automate the six APIs Coding PM's C++ harness did not cover
+    # (happy-path companions to existing D-/S- deviation cases)
+    # =========================================================================
+
+    # A1 set_phase happy path — CLK1, non-trivial 7-bit value
+    cases.append({
+        "id": "A-set_phase-clk1-0x2A", "priority": "A", "api": "set_phase",
+        "covers": ["set_phase", "reg 166"], "clk": 1,
+        "requested_phase": 0x2A,
+        "lib_write": {"reg": 165 + 1, "value": 0x2A & 0x7F},
+        "sequence": ["reset()", "set_phase(SI5351_CLK1, 0x2A)"],
+    })
+
+    # A2 crystal load — already have S-xtal-load + D-0pF; add explicit init(8pF) single-write lock
+    cases.append({
+        "id": "A-init-crystal-load-8pF", "priority": "A", "api": "init_xtal_load",
+        "covers": ["init xtal load", "reg 183"],
+        "lib_writes": {"8pF": ((2 & 0x3) << 6) | 0x12},  # 0x92
+        "sequence": ["init(SI5351_CRYSTAL_LOAD_8PF, 0, 0)"],
+    })
+
+    # A3 set_int happy path — CLK0 MS0_INT (not FBA_INT)
+    cases.append({
+        "id": "A-set_int-clk0-ms-int", "priority": "A", "api": "set_int",
+        "covers": ["set_int CLK0", "reg 16 bit6 = MS0_INT"], "clk": 0,
+        "sequence": ["reset()", "set_int(SI5351_CLK0, 1)"],
+        "lib_write": {"reg": 16, "value": lib_set_int(lib_ctrl_after_reset(0, "PLLA"), 1)},  # 0x4C
+        "ms_int_target": True,  # evaluator: this is MSx_INT not FBx_INT
+        "plla": None,  # not used for MS_INT path
+    })
+
+    # A4 set_pll_input happy path — prior reg15 clear, select CLKIN /4
+    cases.append({
+        "id": "A-set_pll_input-clkin-div4-clean", "priority": "A", "api": "set_pll_input",
+        "covers": ["set_pll_input", "set_ref_freq", "reg 15"],
+        "sequence": ["reset()", "set_ref_freq(80000000, SI5351_PLL_INPUT_CLKIN)",  # -> clkin_div=/4
+                     "set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN)"],
+        "prior_reg15": 0x00,
+        "intended_clkin_div": 4,
+        "lib_write": {"reg": 15, "value": 0x00 | 0x04 | (2 << 6)},  # PLLA_SRC | CLKIN_DIV_4 = 0x84
+    })
+
+    # A5 5 MHz-ref — already D-ref5MHz; add companion 27 MHz in-spec ref (adjacent set_ref_freq/set_pll)
+    reg27, _, abc27 = pll_calc(SI5351_PLL_FIXED, ref_xtal_hz=27_000_000)
+    cases.append({
+        "id": "A-ref27MHz-set_pll-fixed", "priority": "A", "api": "set_pll",
+        "covers": ["set_ref_freq 27 MHz", "set_pll", "in-spec XTAL"],
+        "sequence": ["init(SI5351_CRYSTAL_LOAD_8PF, 27000000, 0)", "reset() → set_pll(SI5351_PLL_FIXED)"],
+        "pll_freq_lib": SI5351_PLL_FIXED, "xtal_hz": 27_000_000, "correction_ppb": 0,
+        "pll_assignment": "PLLA",
+        "pll_a": abc27["a"], "pll_b": abc27["b"], "pll_c": abc27["c"],
+        "pll_p1": reg27.p1, "pll_p2": reg27.p2, "pll_p3": reg27.p3,
+        "lib_pll_regs": lib_pll_regs("PLLA", reg27),
+    })
+
+    # A6 adjacent: set_correction nonzero then set_int CLK0 (pairs crystal-cal with MS_INT API)
+    reg_corr, _, abc_corr = pll_calc(SI5351_PLL_FIXED, correction=100_000)
+    cases.append({
+        "id": "A-set_correction-then-set_int-clk0", "priority": "A", "api": "set_int",
+        "covers": ["set_correction", "set_int CLK0"], "clk": 0,
+        "sequence": ["reset()", "set_correction(100000, SI5351_PLL_INPUT_XO)", "set_int(SI5351_CLK0, 1)"],
+        "lib_write": {"reg": 16, "value": lib_set_int(lib_ctrl_after_reset(0, "PLLA"), 1)},
+        "ms_int_target": True,
+        "plla": {"a": abc_corr["a"], "b": abc_corr["b"], "c": abc_corr["c"],
+                 "p1": reg_corr.p1, "p2": reg_corr.p2, "p3": reg_corr.p3},
+        "lib_pll_regs": lib_pll_regs("PLLA", reg_corr),
+        "pll_a": abc_corr["a"], "pll_b": abc_corr["b"], "pll_c": abc_corr["c"],
+        "pll_p1": reg_corr.p1, "pll_p2": reg_corr.p2, "pll_p3": reg_corr.p3,
+        "xtal_hz": SI5351_XTAL_FREQ, "correction_ppb": 100_000,
+    })
+
+
+    return cases
+
+
+def main():
+    # JSON/markdown generation lives in generate_goldens.py so this mirror
+    # module never imports the spec oracle.
+    import generate_goldens
+    generate_goldens.main()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/tests/regression/python/spec_crosscheck.py b/tests/regression/python/spec_crosscheck.py
new file mode 100644
index 0000000..4642aa1
--- /dev/null
+++ b/tests/regression/python/spec_crosscheck.py
@@ -0,0 +1,487 @@
+#!/usr/bin/env python3
+"""
+Cross-check library-mirror cases (si5351_math.py) against the independent
+AN619/datasheet oracle (spec_oracle.py).
+
+For each case we produce a `spec` block:
+  * spec-expected register bytes at AN619 addresses (from the library's chosen
+    a/b/c, because the spec does not prescribe how b/c is chosen)
+  * realized output frequency decoded from the library's registers (exact)
+  * constraint checks with citations
+  * status: "agree" | "deviation"  (+ which rules failed)
+Known deviations are declared in KNOWN_DEVIATIONS / DEVIATION_CATALOG and are
+treated as expected failures (xfail) by test_spec.py.
+"""
+from __future__ import annotations
+from fractions import Fraction as F
+from typing import Any, Dict, List, Optional
+
+import spec_oracle as S
+
+# ---------------------------------------------------------------------------
+# Deviation catalogue (library behaviour locked by golden_cases; spec flags it)
+# ---------------------------------------------------------------------------
+DEVIATION_CATALOG: Dict[str, Dict[str, str]] = {
+    "DEV-01-FOUT-MAX-225": {
+        "title": "Library accepts CLK0-5 output up to 225 MHz; spec max is 200 MHz",
+        "library": "SI5351_MULTISYNTH_MAX_FREQ = 225000000; set_freq clamps to 225 MHz, programs DIVBY4 with fVCO=4*Fout (e.g. 210 MHz -> VCO 840 MHz, 250 MHz request -> 225 MHz/VCO 900 MHz)",
+        "spec": "DS Table 7 FCLK max 200 MHz; AN619 §2 MS output 500 kHz-200 MHz; AN619 §4.1.3 DIVBY4 range 150 < Fout <= 200 MHz",
+        "rules": "OUT_FREQ_RANGE, MS_OUT_RANGE (+OUT_FREQ_ACCURACY when clamped)",
+        "severity": "medium",
+    },
+    "DEV-02-FOUT-MIN-4K": {
+        "title": "Library min CLK0-5 output is 4 kHz; datasheet min is 2.5 kHz",
+        "library": "SI5351_CLKOUT_MIN_FREQ = 4000; 2.5 kHz request silently becomes 4 kHz (R=128, MS 512 kHz)",
+        "spec": "DS Table 7 FCLK min 0.0025 MHz; AN619 §2 'down to 2.5 kHz' (note AN619 §4.2.2 says 8 kHz: docs disagree)",
+        "rules": "OUT_FREQ_ACCURACY",
+        "severity": "low (conservative)",
+    },
+    "DEV-03-CLK67-LOWFREQ-P1-TRUNC": {
+        "title": "CLK6/7 low-frequency request writes MS6_P1 = 0 (uint8 truncation of 256)",
+        "library": "set_freq(<18.454 kHz, CLK6/7) clamps to 4 kHz (CLKOUT_MIN, not CLKOUT67_MIN), select_r_div_ms67 picks R=1, multisynth67_calc clamps to 500 kHz, a=254 -> PLL 127 MHz < VCO_MIN -> a+=2 = 256 -> reg->p1=(uint8_t)256 = 0; set_pll(128 MHz) is clamped to 600 MHz inside pll_calc but pllb_freq stores 128 MHz",
+        "spec": "AN619 Reg 90/91: MS6/7 ratio even integer 6..254; AN619 §2 VCO 600-900 MHz",
+        "rules": "MS67_RATIO_VALID, VCO_REQUEST_RANGE, OUT_FREQ_ACCURACY",
+        "severity": "high",
+    },
+    "DEV-04-MS-RATIO-6-TO-8": {
+        "title": "Library permits output MS ratios in [6,8) other than 6 (odd 7, fractional 6.x, 7.x)",
+        "library": "multisynth_calc(freq, pll_freq) only clamps a<6 / a>1800; set_freq_manual(100 MHz, 700 MHz) -> ratio 7; (90 MHz, 600 MHz) -> 6.666666",
+        "spec": "AN619 §2.1.1 item 1 / §4.1.2: valid ratios 4, 6, 8, or 8+1/1048575 .. 2048",
+        "rules": "MS_RATIO_VALID",
+        "severity": "medium (set_freq_manual / mixed-PLL scenarios)",
+    },
+    "DEV-05-MS-STALE-A": {
+        "title": "multisynth_calc keeps stale a after the a<6 clamp -> programs ratio 5",
+        "library": "a = pll/freq = 5; freq = pll/6 but a is not recomputed; b = 0 -> P1 = 128 (ratio 5). set_freq_manual(140 MHz, 700 MHz)",
+        "spec": "AN619 §2.1.1: ratio 5 invalid",
+        "rules": "MS_RATIO_VALID",
+        "severity": "medium",
+    },
+    "DEV-06-DIVBY4-PRECONDITION": {
+        "title": "set_freq_manual forces DIVBY4 for Fout >= 150 MHz regardless of pll_freq",
+        "library": "set_freq_manual(175 MHz, 800 MHz) writes DIVBY4 (P=0,0,1) -> actual output 200 MHz",
+        "spec": "AN619 §4.1.3 'Set the appropriate feedback Multisynth to generate fVCO = Fout*4'",
+        "rules": "OUT_FREQ_ACCURACY",
+        "severity": "medium (documented 'track settings yourself' API)",
+    },
+    "DEV-07-VCXO-CENTER-112M5": {
+        "title": "VCXO-linked output above 112.5 MHz (library example si5351_vcxo.ino uses 146 MHz)",
+        "library": "No check; example tunes CLK0 = 146 MHz on VCXO PLLB 876 MHz",
+        "spec": "DS §4.2 'Multisynth ... synthesizes the VCXO output's center frequency up to 112.5 MHz'",
+        "rules": "VCXO_CENTER_MAX",
+        "severity": "low (example/precondition)",
+    },
+    "DEV-08-VCXO-C-NOT-PRESERVED": {
+        "title": "VCXO requirement c = 10^6 on MSNB is lost after later set_pll() calls",
+        "library": "set_vcxo() does not update pllb_freq; set_correction()/set_pll_input() re-run set_pll(pllb_freq=800 MHz) -> MSNB a=32,b=0,c=1. set_freq_manual(..., 875 MHz) after set_vcxo(875 MHz) re-runs non-VCXO pll_calc -> b=0 -> c=1",
+        "spec": "AN619 §3.2 & §7: 'Feedback B Multisynth divider ratio must be set such that ... c ... is fixed to 10^6'",
+        "rules": "VCXO_C_FIXED, VCXO_PLL_PRESERVED",
+        "severity": "medium",
+    },
+    "DEV-09-PHOFF-CLK67": {
+        "title": "set_phase(CLK6/7) writes reserved registers 171/172",
+        "library": "si5351_write(SI5351_CLK0_PHASE_OFFSET + clk, phase) with no clk bound",
+        "spec": "AN619 §6 & Reg 165-170: phase offset only for CLK0-5; 171-176 Reserved",
+        "rules": "PHOFF_ADDR",
+        "severity": "low",
+    },
+    "DEV-10-XTAL-CL-0PF": {
+        "title": "SI5351_CRYSTAL_LOAD_0PF writes reserved XTAL_CL = 00b",
+        "library": "init(SI5351_CRYSTAL_LOAD_0PF, ...) -> reg183 = 0x12",
+        "spec": "AN619 Reg 183: XTAL_CL 00 'Reserved. Do not select this option.'",
+        "rules": "XTAL_CL_RESERVED",
+        "severity": "low",
+    },
+    "DEV-11-SET_INT-CLK67-IS-FB_INT": {
+        "title": "set_int(CLK6/7) toggles FBA_INT/FBB_INT (reg 22/23 bit 6), not an MS6/7 integer bit",
+        "library": "set_int() writes bit 6 of SI5351_CLK0_CTRL+clk for any clk; on fractional PLLA this forces MSNA integer mode",
+        "spec": "AN619 Reg 22/23 bit 6 = FBA_INT/FBB_INT; §3.2.1 only for even-integer feedback; §4.1.2.1 MS6/7 have no INT bit",
+        "rules": "FB_INT_ONLY_EVEN_INT",
+        "severity": "medium",
+    },
+    "DEV-12-CLKIN-DIV-RMW": {
+        "title": "set_pll_input ORs CLKIN_DIV into reg 15 without clearing the old field",
+        "library": "reg_val |= clkin_div (the &= ~SI5351_CLKIN_DIV_MASK line is commented out): prior /2 (01b) + new /4 (10b) -> 11b = /8",
+        "spec": "AN619 Reg 15 CLKIN_DIV[1:0] is a 2-bit field (00 /1, 01 /2, 10 /4, 11 /8)",
+        "rules": "CLKIN_DIV_FIELD",
+        "severity": "medium (Si5351C/CLKIN users)",
+    },
+    "DEV-13-PLL-STALE-A": {
+        "title": "pll_calc keeps stale a after a>90 clamp (non-25/27 MHz reference)",
+        "library": "5 MHz reference: a = 160 > 90, freq clamped to 450 MHz but a not recomputed; P1 = 19968 (ratio 160)",
+        "spec": "AN619 §3.2 feedback ratio 15..90; AN619 §3.1.2 PLL input 10-40 MHz; DS Table 6/8 XTAL 25-27 MHz",
+        "rules": "FB_RATIO_RANGE, REF_RANGE",
+        "severity": "low (out-of-spec reference)",
+    },
+    "DEV-14-CLK67-NOT-ENABLED": {
+        "title": "set_freq() on CLK6/CLK7 never enables the output (reg 3 OEB bit stays 1)",
+        "library": "CLK0-5 branch calls output_enable(clk,1) on first set; CLK6/7 branch has no output_enable(); reset() disabled all outputs",
+        "spec": "AN619 Reg 3 CLKx_OEB: 1 = output disabled",
+        "rules": "OUTPUT_ENABLED_AFTER_SET",
+        "severity": "medium (functional; recommend hardware confirmation)",
+    },
+}
+
+DEVIATION_CATALOG["DEV-15-MANUAL-CLK67"] = {
+    "title": "set_freq_manual() on CLK6/7 writes a truncated fractional-MS P1 to reg 90/91",
+    "library": "set_freq_manual(87.4 MHz, 874 MHz, CLK7): multisynth_calc gives a=10,b=0,c=1 -> P1=128*10-512=768; set_ms writes (uint8_t)768 = 0x00 to reg 91",
+    "spec": "AN619 §4.1.2 / Reg 91: 'For MS6 and MS7, set MSx_P1 directly (e.g., MSx_P1 = divide value)' -> 10 (0x0A)",
+    "rules": "MS67_RATIO_VALID, OUT_FREQ_ACCURACY",
+    "severity": "high (silent wrong output)",
+}
+
+# case id -> set of error-severity rules expected to FAIL (xfail)
+KNOWN_DEVIATIONS: Dict[str, Dict[str, Any]] = {
+    "P0-clk6-23MHz": {"devs": ["DEV-14-CLK67-NOT-ENABLED"], "rules": {"OUTPUT_ENABLED_AFTER_SET"}},
+    "P0-clk7-874MHz-even-div-of-clk6-pll": {"devs": ["DEV-14-CLK67-NOT-ENABLED"], "rules": {"OUTPUT_ENABLED_AFTER_SET"}},
+    "P0-vcxo-manual-146MHz-on-876pll": {"devs": ["DEV-07-VCXO-CENTER-112M5"], "rules": {"VCXO_CENTER_MAX"}},
+    "S-clk6-R6div-100kHz": {"devs": ["DEV-14-CLK67-NOT-ENABLED"], "rules": {"OUTPUT_ENABLED_AFTER_SET"}},
+    "S-clk7-R7div-50kHz": {"devs": ["DEV-14-CLK67-NOT-ENABLED"], "rules": {"OUTPUT_ENABLED_AFTER_SET"}},
+    "S-clk6-150MHz-upper-clamp": {"devs": ["DEV-14-CLK67-NOT-ENABLED"], "rules": {"OUTPUT_ENABLED_AFTER_SET"}},
+    "D-clk0-210MHz-above-spec-max": {"devs": ["DEV-01-FOUT-MAX-225"], "rules": {"OUT_FREQ_RANGE", "MS_OUT_RANGE"}},
+    "D-clk0-250MHz-clamped-to-225": {"devs": ["DEV-01-FOUT-MAX-225"],
+                                     "rules": {"OUT_FREQ_RANGE", "MS_OUT_RANGE", "OUT_FREQ_ACCURACY"}},
+    "D-clk0-2p5kHz-clamped-to-4kHz": {"devs": ["DEV-02-FOUT-MIN-4K"], "rules": {"OUT_FREQ_ACCURACY"}},
+    "D-clk6-10kHz-ms6-p1-zero": {"devs": ["DEV-03-CLK67-LOWFREQ-P1-TRUNC", "DEV-14-CLK67-NOT-ENABLED"],
+                                 "rules": {"MS67_RATIO_VALID", "VCO_REQUEST_RANGE", "OUT_FREQ_ACCURACY",
+                                           "OUTPUT_ENABLED_AFTER_SET"}},
+    "D-manual-100MHz-pll700-ratio7": {"devs": ["DEV-04-MS-RATIO-6-TO-8"], "rules": {"MS_RATIO_VALID"}},
+    "D-manual-90MHz-pll600-ratio6p67": {"devs": ["DEV-04-MS-RATIO-6-TO-8"], "rules": {"MS_RATIO_VALID"}},
+    "D-manual-140MHz-pll700-stale-a5": {"devs": ["DEV-05-MS-STALE-A"], "rules": {"MS_RATIO_VALID"}},
+    "D-manual-175MHz-pll800-divby4-precondition": {"devs": ["DEV-06-DIVBY4-PRECONDITION"],
+                                                   "rules": {"OUT_FREQ_ACCURACY"}},
+    "D-vcxo-then-set_correction-clobbers-pllb": {"devs": ["DEV-08-VCXO-C-NOT-PRESERVED"],
+                                                 "rules": {"VCXO_C_FIXED", "VCXO_PLL_PRESERVED"}},
+    "D-vcxo-875MHz-then-manual-rewrites-c1": {"devs": ["DEV-08-VCXO-C-NOT-PRESERVED"], "rules": {"VCXO_C_FIXED"}},
+    "D-manual-clk7-87p4MHz-p1-truncated": {"devs": ["DEV-15-MANUAL-CLK67"],
+                                           "rules": {"MS67_RATIO_VALID", "OUT_FREQ_ACCURACY"}},
+    "D-set_phase-clk6-writes-reserved-171": {"devs": ["DEV-09-PHOFF-CLK67"], "rules": {"PHOFF_ADDR"}},
+    "D-init-crystal-load-0pF-reserved": {"devs": ["DEV-10-XTAL-CL-0PF"], "rules": {"XTAL_CL_RESERVED"}},
+    "D-set_int-clk6-sets-FBA_INT-on-fractional-plla": {"devs": ["DEV-11-SET_INT-CLK67-IS-FB_INT"],
+                                                       "rules": {"FB_INT_ONLY_EVEN_INT"}},
+    "D-set_pll_input-clkin_div-or-without-clear": {"devs": ["DEV-12-CLKIN-DIV-RMW"], "rules": {"CLKIN_DIV_FIELD"}},
+    "D-ref5MHz-pll_calc-stale-a160": {"devs": ["DEV-13-PLL-STALE-A"], "rules": {"FB_RATIO_RANGE", "REF_RANGE"}},
+}
+
+
+def _regs(d: Dict[int, int]) -> Dict[str, int]:
+    return {str(k): v for k, v in d.items()}
+
+
+def _fref(case: Dict[str, Any]) -> F:
+    x = F(case.get("xtal_hz", 25_000_000))
+    return x * (1 + F(case.get("correction_ppb", 0), 10**9))
+
+
+def _cmp(rule: str, lib: Any, spec: Any, cite: str) -> Dict[str, Any]:
+    return S.chk(rule, lib == spec, cite, f"library={lib} spec={spec}")
+
+
+def _eval_feedback(case, checks, pll_key="PLLA", regs_key="lib_pll_regs") -> Optional[F]:
+    if "pll_p1" not in case:
+        return None
+    p1, p2, p3 = case["pll_p1"], case["pll_p2"], case["pll_p3"]
+    checks.append(_cmp("FB_ENCODING", [p1, p2, p3], list(S.encode_abc(case["pll_a"], case["pll_b"], case["pll_c"])),
+                       "AN619 §3.2 P1/P2/P3 equations"))
+    if regs_key in case:
+        checks.append(_cmp("REG_PLL_BLOCK", case[regs_key], _regs(S.feedback_block(pll_key, p1, p2, p3)),
+                           "AN619 §8.1 / Reg 26-33 (MSNA), 34-41 (MSNB)"))
+    fc, ratio, vco = S.check_feedback(p1, p2, p3, _fref(case))
+    checks.extend(fc)
+    return vco
+
+
+def evaluate(case: Dict[str, Any]) -> Dict[str, Any]:
+    checks: List[Dict[str, Any]] = []
+    out: Dict[str, Any] = {}
+    api, path, clk = case.get("api"), case.get("clk_path"), case.get("clk", 0)
+
+    if api == "parity_check":
+        if "auto" in case:
+            a = evaluate(dict(case["auto"], clk=0))
+            m = evaluate(dict(case["manual"], clk=0))
+            out["auto_status"], out["manual_status"] = a["status"], m["status"]
+            checks.append(S.chk("PARITY_SPEC_REGS_EQUAL", a.get("spec_ms_regs") == m.get("spec_ms_regs"),
+                                "AN619 §4.1.2/§4.1.3", "spec MS registers for auto vs manual"))
+        else:
+            checks.append(S.chk("PARITY_MS_MATCH", case["ms_match"], "library parity (no spec rule)", ""))
+        return _finish(case, out, checks)
+
+    if api == "set_ms_rmw":
+        # Spec packing with prior bit7 must match library final byte
+        R = 1 << case["r_div"]
+        divby4 = bool(case["div_by_4"])
+        p = (case["ms_p1"], case["ms_p2"], case["ms_p3"])
+        # Spec ms_block assumes prior unused bits = 0 in the R_DIV/DIVBY4/P1hi field construction;
+        # AN619 marks bit7 unused — preserving a 1 there is library RMW behaviour, not a spec requirement.
+        # Compare bits 6:0 against spec; bit7 separately as RMW lock.
+        spec_ms = S.ms_block(case["clk"], *p, r=R, divby4=divby4)
+        out["spec_ms_regs"] = {str(k): v for k, v in spec_ms.items()}
+        lib = case["lib_ms_regs"]
+        # bytes other than +2 must match exactly
+        for off in (0, 1, 3, 4, 5, 6, 7):
+            addr = str(42 + 8 * case["clk"] + off)
+            checks.append(_cmp(f"REG_MS_B{off}", lib[addr], out["spec_ms_regs"][addr],
+                               "AN619 MS0 parameter block"))
+        addr2 = str(42 + 8 * case["clk"] + 2)
+        spec_byte2 = out["spec_ms_regs"][addr2]  # bit7=0
+        lib_byte2 = lib[addr2]
+        checks.append(S.chk("REG_MS_BYTE2_LOW7", (lib_byte2 & 0x7F) == (spec_byte2 & 0x7F),
+                            "AN619 Reg 44 bits 6:0 (R_DIV|DIVBY4|P1[17:16])",
+                            f"library=0x{lib_byte2:02X} spec_low7=0x{spec_byte2:02X}"))
+        checks.append(S.chk("RMW_BIT7_PRESERVED", (lib_byte2 & 0x80) == (case["prior_byte2"] & 0x80),
+                            "Library set_ms/ms_div RMW preserves unused bit7 (AN619 Reg 44 bit7 Unused)",
+                            f"prior=0x{case['prior_byte2']:02X} final=0x{lib_byte2:02X}"))
+        # Mutation detectors must differ from the lock
+        md = case["rmw_transcript"]["mutation_detectors"]
+        checks.append(S.chk("MUTATION_NOT_NAIVE_MS_DIV", lib_byte2 != md["naive_ms_div_overwrite"],
+                            "Coding PM mutation: naive ms_div overwrite",
+                            f"final=0x{lib_byte2:02X} naive=0x{md['naive_ms_div_overwrite']:02X}"))
+        checks.append(S.chk("MUTATION_NOT_NAIVE_SET_MS", lib_byte2 != md["naive_set_ms_then_correct_ms_div"],
+                            "Coding PM mutation: naive set_ms (no RMW) then correct ms_div",
+                            f"final=0x{lib_byte2:02X} naive=0x{md['naive_set_ms_then_correct_ms_div']:02X}"))
+        # Transcript final agrees
+        checks.append(_cmp("RMW_TRANSCRIPT_FINAL", case["rmw_transcript"]["final"], lib_byte2,
+                           "set_ms+ms_div RMW transcript"))
+        # Also check feedback encoding for completeness
+        _eval_feedback(case, checks, "PLLA")
+        return _finish(case, out, checks)
+
+    if api == "reset_pll_assignment":
+        # Lock default PLL map after reset(); Spec allows either PLL (AN619 §4.1.1)
+        table = case["pll_assignment_table"]
+        checks.append(S.chk("CLK5_RESET_PLLA", table["5"] == "PLLA",
+                            "Library reset() clk5 → PLLA (AN619 §4.1.1 allows either)",
+                            f"pll_assignment[5]={table['5']}"))
+        checks.append(S.chk("CLK7_RESET_PLLB", table["7"] == "PLLB",
+                            "Library reset() clk7 → PLLB (AN619 §4.1.1 allows either)",
+                            f"pll_assignment[7]={table['7']}"))
+        # Encoding of the MSx_SRC bit must match AN619
+        for i in range(8):
+            want = S.clk_ctrl(i, src_pllb=int(table[str(i)] == "PLLB"))
+            got = case["lib_clk_ctrl"][str(16 + i)]
+            checks.append(_cmp(f"REG_CLK_CTRL_{i}", got, want, f"AN619 Reg {16+i} MSx_SRC"))
+        # Focused lock for this case's clk
+        focus = case["clk"]
+        checks.append(_cmp("REG_FOCUS_CTRL", case["lib_write"]["value"],
+                           case["lib_clk_ctrl"][str(16 + focus)],
+                           f"AN619 Reg {16+focus}"))
+        # Document that Spec does not mandate the library's choice
+        checks.append(S.chk("PLL_ASSIGN_SPEC_PERMITS_EITHER", True, "AN619 §4.1.1",
+                            case.get("spec_note", "")))
+        # Soft check: mutation_fail_if values must NOT equal the lock
+        mfi = case.get("mutation_fail_if", {})
+        if focus == 7:
+            checks.append(S.chk("MUTATION_CLK7_NOT_PLLA",
+                                case["lib_write"]["value"] != mfi.get("clk7_ctrl_equals")
+                                and table["7"] != mfi.get("pll_assignment_7"),
+                                "mutation detector (Coding PM)",
+                                f"locked reg23=0x{case['lib_write']['value']:02X} assignment={table['7']}"))
+        if focus == 5:
+            checks.append(S.chk("MUTATION_CLK5_NOT_PLLB",
+                                case["lib_write"]["value"] != mfi.get("clk5_ctrl_equals")
+                                and table["5"] != mfi.get("pll_assignment_5"),
+                                "mutation detector (Coding PM)",
+                                f"locked reg21=0x{case['lib_write']['value']:02X} assignment={table['5']}"))
+        return _finish(case, out, checks)
+
+    if path == "CLK0-5" and "ms_p1" in case:
+        pll = case.get("pll_assignment", "PLLA")
+        vco = _eval_feedback(case, checks, "PLLB" if pll == "PLLB" else "PLLA")
+        divby4 = bool(case["div_by_4"])
+        R = 1 << case["r_div"]
+        p = (case["ms_p1"], case["ms_p2"], case["ms_p3"])
+        if not divby4:
+            checks.append(_cmp("MS_ENCODING", list(p), list(S.encode_abc(case["ms_a"], case["ms_b"], case["ms_c"])),
+                               "AN619 §4.1.2 MSx_P1/P2/P3 equations"))
+            spec_p = S.encode_abc(case["ms_a"], case["ms_b"], case["ms_c"])
+        else:
+            spec_p = S.divby4_params()
+        spec_ms = _regs(S.ms_block(clk, *spec_p, r=R, divby4=divby4))
+        out["spec_ms_regs"] = spec_ms
+        if "lib_ms_regs" in case:
+            checks.append(_cmp("REG_MS_BLOCK", case["lib_ms_regs"], spec_ms,
+                               "AN619 §8.1 / Reg 42-89 (R_DIV 6:4, DIVBY4 3:2, P1[17:16] 1:0 of byte +2)"))
+        if "lib_clk_ctrl" in case:
+            spec_ctrl = {str(16 + clk): S.clk_ctrl(clk, int_bit=case["int_mode"], src_pllb=int(pll == "PLLB"))}
+            out["spec_clk_ctrl"] = spec_ctrl
+            checks.append(_cmp("REG_CLK_CTRL", case["lib_clk_ctrl"], spec_ctrl, "AN619 Reg 16-21"))
+        if "lib_reg3_after" in case:
+            checks.append(S.chk("OUTPUT_ENABLED_AFTER_SET", ((case["lib_reg3_after"] >> clk) & 1) == 0,
+                                "AN619 Reg 3 CLKx_OEB (0 = enabled)", f"reg3=0x{case['lib_reg3_after']:02X}"))
+        f_ms = (vco / 4 if divby4 else vco / S.decode_p(*p)) if vco is not None else None
+        mc, ratio = S.check_ms05(*p, divby4=divby4, ms_int=bool(case["int_mode"]), f_ms_hz=f_ms)
+        checks.extend(mc)
+        realized = f_ms / R if f_ms is not None else None
+        req = F(case["input_freq_lib"], 100)
+        checks.extend(S.check_out_freq(req, realized))
+        if case.get("vcxo_context"):
+            checks.append(S.chk("VCXO_CENTER_MAX", req <= S.VCXO_CENTER_MAX_HZ, "DS §4.2 (VCXO center <= 112.5 MHz)",
+                                f"Fout={float(req)} Hz"))
+            checks.append(S.chk("VCXO_C_FIXED", case["pll_p3"] == S.VCXO_C, "AN619 §3.2/§7 (MSNB c = 10^6)",
+                                f"MSNB P3=c={case['pll_p3']}"))
+        out.update(realized_hz=float(realized) if realized is not None else None,
+                   ms_ratio=str(ratio), fvco_hz=float(vco) if vco is not None else None)
+        return _finish(case, out, checks)
+
+    if path == "CLK6/7":
+        req = F(case["input_freq_lib"], 100)
+        if case.get("rejected"):
+            pllb = F(case.get("pll_freq_lib", 0), 100) if case.get("pll_freq_lib") else None
+            out["spec_expectation"] = "reject: requested freq is not an even-integer division of PLLB"
+            checks.append(S.chk("MS67_REJECT_CONSISTENT", True, "AN619 §2.2 Note (even integers 6..254 only)",
+                                f"library rejected ({case.get('reason')})"))
+            return _finish(case, out, checks)
+        vco = _eval_feedback(case, checks, "PLLB")
+        a = list(case["lib_ms67_regs"].values())[0]   # byte the library actually writes to reg 90/91
+        R = 1 << case["r_div"]
+        req_vco_i = F(case["pll_freq_lib"], 100)
+        intended = req_vco_i / (req * R)
+        if intended.denominator == 1 and intended.numerator % 2 == 0 and S.MS67_MIN <= intended.numerator <= S.MS67_MAX:
+            out["spec_intended_ms67_regs"] = _regs(S.ms67_reg(clk, intended.numerator))
+        checks.extend(S.check_ms67(a))
+        req_vco = F(case["pll_freq_lib"], 100)
+        checks.append(S.chk("VCO_REQUEST_RANGE", S.VCO_MIN_HZ <= req_vco <= S.VCO_MAX_HZ,
+                            "AN619 §2 (600-900 MHz); library stores requested value in pllb_freq",
+                            f"requested PLLB={float(req_vco)} Hz"))
+        valid = a % 2 == 0 and S.MS67_MIN <= a <= S.MS67_MAX
+        if valid:
+            spec67 = _regs(S.ms67_reg(clk, a))
+            out["spec_ms67_regs"] = spec67
+            checks.append(_cmp("REG_MS67", case["lib_ms67_regs"], spec67, "AN619 Reg 90/91"))
+        spec92 = S.reg92(r6=R) if clk == 6 else S.reg92(r7=R)
+        out["spec_reg92"] = spec92
+        checks.append(_cmp("REG_92", case["lib_reg92"], spec92, "AN619 Reg 92 (R7_DIV 6:4, R6_DIV 2:0)"))
+        spec_ctrl = {str(16 + clk): S.clk_ctrl(clk, int_bit=0, src_pllb=1)}
+        checks.append(_cmp("REG_CLK_CTRL", case["lib_clk_ctrl"], spec_ctrl, "AN619 Reg 22/23"))
+        checks.append(S.chk("OUTPUT_ENABLED_AFTER_SET", ((case["lib_reg3_after"] >> clk) & 1) == 0,
+                            "AN619 Reg 3 CLKx_OEB (0 = enabled)", f"reg3=0x{case['lib_reg3_after']:02X}"))
+        realized = vco / a / R if (valid and vco is not None) else None
+        checks.extend(S.check_out_freq(req, realized))
+        if realized is None:
+            checks.append(S.chk("OUT_FREQ_ACCURACY", False, "AN619 Reg 90/91", f"undefined output: MS{clk}_P1={a}"))
+        out.update(realized_hz=float(realized) if realized else None, fvco_hz=float(vco) if vco else None)
+        return _finish(case, out, checks)
+
+    if api == "set_vcxo":
+        _eval_feedback(case, checks, "PLLB")
+        v = S.vcxo_param(case["pll_a"], case["pll_b"], case["ppm"])
+        out["spec_vcxo_exact"] = float(v["exact"])
+        out["spec_vcxo_floor"] = v["floor"]
+        out["spec_vcxo_round"] = v["round"]
+        out["spec_vcxo_regs"] = _regs(v["regs_floor"])
+        checks.append(S.chk("VCXO_C_FIXED", case["pll_c"] == S.VCXO_C and case["pll_p3"] == S.VCXO_C,
+                            "AN619 §3.2/§7 (MSNB c = 10^6)", f"c={case['pll_c']} P3={case['pll_p3']}"))
+        checks.append(S.chk("VCXO_APR_RANGE", S.VCXO_APR_MIN <= case["ppm"] <= S.VCXO_APR_MAX,
+                            "DS Table 5 (±30..±240 ppm)", f"applied ppm={case['ppm']} requested={case.get('requested_ppm', case['ppm'])}"))
+        checks.append(_cmp("VCXO_PARAM_FLOOR", case["vcxo_param"], v["floor"], "AN619 §7 (floor of exact value)"))
+        checks.append(_cmp("REG_VCXO", case["lib_vcxo_regs"], out["spec_vcxo_regs"],
+                           "AN619 Reg 162-164 (164 bits 7:6 'Only write 00b')"))
+        if v["floor"] != v["round"]:
+            checks.append(S.chk("VCXO_PARAM_ROUNDING", False, "AN619 §7 (no rounding rule stated)",
+                                f"exact={float(v['exact']):.4f}: library floors to {v['floor']}; round-half-up would give {v['round']}",
+                                "advisory"))
+        return _finish(case, out, checks)
+
+    if api == "vcxo_sequence":
+        _eval_feedback(case, checks, "PLLB")
+        before = case["pllb_after_set_vcxo"]
+        checks.append(S.chk("VCXO_C_FIXED", case["pll_p3"] == S.VCXO_C, "AN619 §3.2/§7 (MSNB c = 10^6)",
+                            f"MSNB P3 after sequence={case['pll_p3']}"))
+        r0 = S.decode_p(before["p1"], before["p2"], before["p3"])
+        r1 = S.decode_p(case["pll_p1"], case["pll_p2"], case["pll_p3"])
+        checks.append(S.chk("VCXO_PLL_PRESERVED", r0 == r1, "AN619 §7 (PLLB is the VCXO)",
+                            f"MSNB ratio after set_vcxo={float(r0)} after sequence={float(r1)}"))
+        return _finish(case, out, checks)
+
+    if api == "reset_plls":
+        for pll, key in (("PLLA", "lib_plla_regs"), ("PLLB", "lib_pllb_regs")):
+            checks.append(_cmp(f"REG_PLL_BLOCK_{pll}", case[key],
+                               _regs(S.feedback_block(pll, case["pll_p1"], case["pll_p2"], case["pll_p3"])),
+                               "AN619 Reg 26-33 / 34-41"))
+        fc, _, _ = S.check_feedback(case["pll_p1"], case["pll_p2"], case["pll_p3"], _fref(case))
+        checks.extend(fc)
+        checks.append(_cmp("REG_177", case["lib_reg177_writes"],
+                           [S.pll_reset_byte(True, False), S.pll_reset_byte(False, True)],
+                           "AN619 Reg 177 (PLLB_RST bit7, PLLA_RST bit5)"))
+        spec_ctrl = {str(16 + i): S.clk_ctrl(i, src_pllb=int(i >= 6)) for i in range(8)}
+        checks.append(_cmp("REG_CLK_CTRL", case["lib_clk_ctrl"], spec_ctrl,
+                           "AN619 Reg 16-23 (PDN=0, INT=0, SRC per PLL, CLK_SRC=11 own MS, 2 mA)"))
+        return _finish(case, out, checks)
+
+    if api == "set_pll":
+        _eval_feedback(case, checks, case.get("pll_assignment", "PLLA"))
+        xt = case.get("xtal_hz", 25_000_000)
+        checks.append(S.chk("REF_RANGE", S.XTAL_MIN_HZ <= xt <= S.XTAL_MAX_HZ or S.PLL_IN_MIN_HZ <= xt <= S.PLL_IN_MAX_HZ,
+                            "DS Table 6/8 XTAL 25-27 MHz; AN619 §3.1.2 PLL input 10-40 MHz", f"ref={xt} Hz"))
+        return _finish(case, out, checks)
+
+    if api == "set_phase":
+        w = case["lib_write"]
+        ok_addr = 0 <= clk <= 5
+        checks.append(S.chk("PHOFF_ADDR", ok_addr and w["reg"] == S.REG_PHOFF_BASE + clk,
+                            "AN619 §6, Reg 165-170 (CLK0-5 only; 171-176 Reserved)", f"library writes reg {w['reg']}"))
+        checks.append(S.chk("PHOFF_BIT7_ZERO", (w["value"] & 0x80) == 0, "AN619 Reg 165-170 bit 7 'Only write 0'",
+                            f"value=0x{w['value']:02X}"))
+        if ok_addr:
+            checks.append(_cmp("REG_PHOFF", [w["reg"], w["value"]], list(S.phase_reg(clk, case["requested_phase"])),
+                               "AN619 Reg 165-170"))
+        checks.append(S.chk("PHOFF_PRECONDITION", False, "AN619 §6 / §4.1.2.1",
+                            "phase offset needs MSx_INT=0 and fractional MS > 8; library does not enforce", "advisory"))
+        return _finish(case, out, checks)
+
+    if api == "init_xtal_load":
+        codes = {"0pF": 0, "6pF": 1, "8pF": 2, "10pF": 3}
+        for k, v in case["lib_writes"].items():
+            checks.append(_cmp(f"REG_183_{k}", v, S.xtal_cl_byte(codes[k]), "AN619 Reg 183 (bits 5:0 = 010010b)"))
+            checks.append(S.chk("XTAL_CL_RESERVED", (v >> 6) != 0, "AN619 Reg 183 (XTAL_CL=00 reserved)",
+                                f"{k}: reg183=0x{v:02X}"))
+        return _finish(case, out, checks)
+
+    if api == "set_int":
+        w = case["lib_write"]
+        int_bit = (w["value"] >> 6) & 1
+        if case.get("ms_int_target"):
+            # CLK0-5: bit6 is MSx_INT — library behaviour matches AN619 Reg 16-21
+            checks.append(_cmp("REG_MS_INT", w["value"],
+                               S.clk_ctrl(clk, int_bit=1, src_pllb=int(case.get("pll_assignment") == "PLLB")),
+                               f"AN619 Reg {16+clk} bit6 = MSx_INT"))
+            checks.append(S.chk("MS_INT_BIT_SET", int_bit == 1, "AN619 §4.1.2.1 / Reg 16-21 bit6",
+                                f"reg{w['reg']}=0x{w['value']:02X}"))
+            if case.get("plla") and case["plla"] is not None:
+                # optional: also confirm PLLA state when set_correction preceded set_int
+                _ = S.decode_p(case["plla"]["p1"], case["plla"]["p2"], case["plla"]["p3"])
+        else:
+            # CLK6/7: bit6 is FBA_INT / FBB_INT (DEV-11 when set on fractional feedback)
+            pa = case["plla"]
+            r = S.decode_p(pa["p1"], pa["p2"], pa["p3"])
+            even_int = r.denominator == 1 and r.numerator % 2 == 0
+            checks.append(S.chk("FB_INT_ONLY_EVEN_INT", (not int_bit) or even_int,
+                                "AN619 §3.2.1 / Reg 22 bit6 FBA_INT (only for even-integer a+b/c)",
+                                f"reg{w['reg']}=0x{w['value']:02X} -> FBA_INT={int_bit}; MSNA ratio={float(r):.9f}"))
+        return _finish(case, out, checks)
+
+    if api == "set_pll_input":
+        w = case["lib_write"]
+        field = (w["value"] >> 6) & 3
+        want = S.R_VALUES.index(case["intended_clkin_div"])  # /1,/2,/4,/8 -> 0..3
+        checks.append(S.chk("CLKIN_DIV_FIELD", field == want, "AN619 Reg 15 CLKIN_DIV[1:0]",
+                            f"reg15=0x{w['value']:02X} -> CLKIN_DIV={field:02b}b (/{1 << field}); intended /{case['intended_clkin_div']}"))
+        return _finish(case, out, checks)
+
+    checks.append(S.chk("UNHANDLED", False, "", f"no evaluator for api={api}"))
+    return _finish(case, out, checks)
+
+
+def _finish(case, out, checks):
+    errors = sorted({c["rule"] for c in checks if not c["ok"] and c["severity"] == "error"})
+    advisories = sorted({c["rule"] for c in checks if not c["ok"] and c["severity"] == "advisory"})
+    reg_rules = [c for c in checks if c["rule"].startswith("REG_") or c["rule"].endswith("_ENCODING")]
+    out["register_agreement"] = all(c["ok"] for c in reg_rules) if reg_rules else None
+    out["failed_rules"] = errors
+    out["advisories"] = advisories
+    out["status"] = "deviation" if errors else "agree"
+    kd = KNOWN_DEVIATIONS.get(case.get("id", ""))
+    out["known_deviations"] = kd["devs"] if kd else []
+    out["checks"] = checks
+    return out
diff --git a/tests/regression/python/spec_oracle.py b/tests/regression/python/spec_oracle.py
new file mode 100644
index 0000000..4d3c829
--- /dev/null
+++ b/tests/regression/python/spec_oracle.py
@@ -0,0 +1,250 @@
+#!/usr/bin/env python3
+"""
+INDEPENDENT spec oracle for the Si5351, written from:
+  * AN619 Rev 0.8 (Sep 23 2021) "Manually Generating an Si5351 Register Map
+    for 10-MSOP and 20-QFN Devices"            -> cited as AN619 §x / Reg n
+  * Si5351A/B/C-B datasheet Rev 1.3 (Aug 27 2021) -> cited as DS Table n / §x
+
+This module deliberately does NOT import si5351_math.py (the library mirror)
+and does not reuse any of its code. It works in exact rational arithmetic
+(fractions.Fraction) in plain Hz, not the library's Hz*100 units.
+"""
+from __future__ import annotations
+from fractions import Fraction as F
+from typing import Dict, List, Optional, Tuple
+
+# ---------------------------------------------------------------------------
+# Spec limits (with citations)
+# ---------------------------------------------------------------------------
+VCO_MIN_HZ = 600_000_000          # AN619 §2 "VCO ... range of 600 to 900 MHz"
+VCO_MAX_HZ = 900_000_000          # AN619 §2 (datasheet does not state VCO range)
+FB_RATIO_MIN = F(15)              # AN619 §3.2 "valid range of 15 + 0/1,048,575 and 90"
+FB_RATIO_MAX = F(90)
+C_MAX = 1_048_575                 # AN619 §2.1.1 / §3.2 / §4.1.2 (20-bit P3 = c)
+P1_BITS, P2_BITS, P3_BITS = 18, 20, 20   # AN619 §3.2 / §4.1.2 MSx_P1[17:0], P2[19:0], P3[19:0]
+MS_INT_RATIOS = {4, 6, 8}         # AN619 §2.1.1 item 1
+MS_FRAC_MIN = 8 + F(1, C_MAX)     # AN619 §2.1.1 item 1, §4.1.2
+MS_RATIO_MAX = F(2048)            # AN619 §2.1.1 item 1, §4.1.2
+MS67_MIN, MS67_MAX = 6, 254       # AN619 §2.2 Note, §4.1.2, Reg 90/91 (even integers only)
+MS_OUT_MIN_HZ = 500_000           # AN619 §2 "Multisynth ... between 500 kHz and 200 MHz"
+MS_OUT_MAX_HZ = 200_000_000       # AN619 §2, §4.1.3; DS Table 7
+DIVBY4_ABOVE_HZ = 150_000_000     # AN619 §4.1.3 "150 MHz < Fout <= 200 MHz" -> divide by 4
+CLKOUT_MIN_HZ = 2_500             # DS Table 7 FCLK min 0.0025 MHz; AN619 §2 "down to 2.5 kHz"
+CLKOUT_MAX_HZ = 200_000_000       # DS Table 7 FCLK max 200 MHz
+R_VALUES = [1, 2, 4, 8, 16, 32, 64, 128]  # AN619 §4.2.2, Reg 44 R0_DIV / Reg 92
+UNIQUE_ABOVE_HZ = 112_500_000     # DS Table 7 note 1 / §4.2: only two unique freqs > 112.5 MHz
+VCXO_APR_MIN, VCXO_APR_MAX = 30, 240   # DS Table 5 VCXO pull range ±30..±240 ppm
+VCXO_C = 1_000_000                # AN619 §3.2 & §7: MSNB c "fixed to 10^6" for VCXO
+VCXO_MARGIN = F(103, 100)         # AN619 §7 "1.03 is a margining factor"
+VCXO_CENTER_MAX_HZ = 112_500_000  # DS §4.2 "VCXO output's center frequency up to 112.5 MHz"
+XTAL_MIN_HZ, XTAL_MAX_HZ = 25_000_000, 27_000_000   # DS Table 6 / Table 8
+PLL_IN_MIN_HZ, PLL_IN_MAX_HZ = 10_000_000, 40_000_000  # AN619 §3.1.2 (DS §4.1 says CLKIN div limits to 30 MHz)
+PHOFF_BITS = 7                    # AN619 Reg 165-170 CLKx_PHOFF[6:0], bit 7 "Only write 0"
+
+# Register addresses (AN619 §8.1 Register Map Summary)
+REG_OEB = 3
+REG_PLL_INPUT_SRC = 15
+REG_CLK_CTRL_BASE = 16            # regs 16..23
+REG_MSNA_BASE = 26                # 26..33
+REG_MSNB_BASE = 34                # 34..41
+REG_MS0_BASE = 42                 # MSn base = 42 + 8n for n=0..5 (42,50,58,66,74,82)
+REG_MS6_P1 = 90
+REG_MS7_P1 = 91
+REG_R67 = 92
+REG_VCXO = (162, 163, 164)
+REG_PHOFF_BASE = 165              # 165..170 for CLK0..5 only
+REG_PLL_RESET = 177
+REG_XTAL_CL = 183
+
+# ---------------------------------------------------------------------------
+# Encoders / decoders
+# ---------------------------------------------------------------------------
+
+def encode_abc(a: int, b: int, c: int) -> Tuple[int, int, int]:
+    """AN619 §3.2 (feedback) and §4.1.2 (MS0-5):
+       P1 = 128a + floor(128 b/c) - 512 ; P2 = 128b - c*floor(128 b/c) ; P3 = c"""
+    if c < 1:
+        raise ValueError("c must be >= 1")
+    fl = (128 * b) // c
+    return 128 * a + fl - 512, 128 * b - c * fl, c
+
+
+def decode_p(p1: int, p2: int, p3: int) -> F:
+    """Invert AN619 encoding: a + b/c = (P1 + 512 + P2/P3) / 128."""
+    if p3 == 0:
+        raise ValueError("P3 == 0 is not a valid encoding")
+    return (F(p1 + 512) + F(p2, p3)) / 128
+
+
+def r_code(r: int) -> int:
+    """AN619 Reg 44 R0_DIV[2:0]: 000b=/1 ... 111b=/128"""
+    return R_VALUES.index(r)
+
+
+def _param_block(base: int, p1: int, p2: int, p3: int, reg2_hi: int = 0) -> Dict[int, int]:
+    """8-byte parameter block layout, AN619 §8.1 / Reg 26-33, 42-49:
+       +0 P3[15:8]  +1 P3[7:0]  +2 {hi bits | P1[17:16]}  +3 P1[15:8]  +4 P1[7:0]
+       +5 P3[19:16]<<4 | P2[19:16]  +6 P2[15:8]  +7 P2[7:0]"""
+    return {
+        base + 0: (p3 >> 8) & 0xFF,
+        base + 1: p3 & 0xFF,
+        base + 2: (reg2_hi & 0xFC) | ((p1 >> 16) & 0x3),
+        base + 3: (p1 >> 8) & 0xFF,
+        base + 4: p1 & 0xFF,
+        base + 5: (((p3 >> 16) & 0xF) << 4) | ((p2 >> 16) & 0xF),
+        base + 6: (p2 >> 8) & 0xFF,
+        base + 7: p2 & 0xFF,
+    }
+
+
+def feedback_block(pll: str, p1: int, p2: int, p3: int) -> Dict[int, int]:
+    """MSNA regs 26-33 / MSNB regs 34-41. Reg 28/36 bits 3:2 Reserved 'Leave as default, 0', 7:4 unused."""
+    base = REG_MSNA_BASE if pll == "PLLA" else REG_MSNB_BASE
+    return _param_block(base, p1, p2, p3, 0)
+
+
+def ms_block(n: int, p1: int, p2: int, p3: int, r: int = 1, divby4: bool = False) -> Dict[int, int]:
+    """MS0-5 block at 42+8n. Reg 44 (+2): bit7 unused, R_DIV[2:0] bits 6:4,
+       MSx_DIVBY4[1:0] bits 3:2 (11b enable / 00b otherwise), P1[17:16] bits 1:0."""
+    if not 0 <= n <= 5:
+        raise ValueError("ms_block only for MS0..MS5")
+    hi = (r_code(r) << 4) | ((0b11 << 2) if divby4 else 0)
+    return _param_block(REG_MS0_BASE + 8 * n, p1, p2, p3, hi)
+
+
+def divby4_params() -> Tuple[int, int, int]:
+    """AN619 §4.1.3: MSx_P1=0, MSx_P2=0, MSx_P3=1, MSx_INT=1, MSx_DIVBY4=11b"""
+    return 0, 0, 1
+
+
+def ms67_reg(n: int, ratio: int) -> Dict[int, int]:
+    """AN619 §4.1.2 / Reg 90, 91: MSx_P1 = divide value (even integer 6..254)."""
+    return {REG_MS6_P1 + (n - 6): ratio & 0xFF}
+
+
+def reg92(r6: int = 1, r7: int = 1) -> int:
+    """AN619 Reg 92 (summary map): bit7 rsvd, R7_DIV[2:0] bits 6:4, bit3 rsvd, R6_DIV[2:0] bits 2:0."""
+    return (r_code(r7) << 4) | r_code(r6)
+
+
+def clk_ctrl(clk: int, pdn=0, int_bit=0, src_pllb=0, inv=0, clk_src=0b11, idrv=0) -> int:
+    """AN619 Reg 16-23: D7 PDN, D6 MSx_INT (CLK0-5) / FBA_INT (reg22) / FBB_INT (reg23),
+       D5 MSx_SRC (0=PLLA, 1=PLLB/VCXO), D4 INV, D3:2 CLK_SRC (00 XTAL, 01 CLKIN,
+       10 MS0/MS4 (reserved for CLK0), 11 own MS), D1:0 IDRV (00 2mA .. 11 8mA)."""
+    return (pdn << 7) | (int_bit << 6) | (src_pllb << 5) | (inv << 4) | (clk_src << 2) | idrv
+
+
+def pll_reset_byte(plla: bool, pllb: bool) -> int:
+    """AN619 Reg 177: bit7 PLLB_RST, bit5 PLLA_RST, others reserved/default 0."""
+    return (0x80 if pllb else 0) | (0x20 if plla else 0)
+
+
+def xtal_cl_byte(cl_code: int) -> int:
+    """AN619 Reg 183: XTAL_CL[1:0] bits 7:6 (00 reserved, 01 6pF, 10 8pF, 11 10pF),
+       bits 5:0 'should be written to 010010b'."""
+    return ((cl_code & 0x3) << 6) | 0b010010
+
+
+def phase_reg(clk: int, value: int) -> Tuple[int, int]:
+    """AN619 Reg 165-170 (CLK0..5 only); bit7 'Only write 0'."""
+    if not 0 <= clk <= 5:
+        raise ValueError("phase offset only exists for CLK0-5")
+    return REG_PHOFF_BASE + clk, value & 0x7F
+
+
+def phase_word(offset_s: F, fvco_hz: F) -> int:
+    """AN619 §6: CLKx_PHOFF = Round(DesiredOffset[s] * 4 * Fvco)."""
+    x = offset_s * 4 * fvco_hz
+    return int(x + F(1, 2)) if x >= 0 else -int(-x + F(1, 2))
+
+
+def vcxo_param(a: int, b: int, apr: int) -> Dict[str, object]:
+    """AN619 §7: VCXO_Param[21:0] = 1.03 * (128a + b/10^6) * APR, with MSNB c = 10^6.
+       AN619 does not state a rounding rule; we report exact, floor and round."""
+    exact = VCXO_MARGIN * (128 * a + F(b, 10**6)) * apr
+    fl = exact.numerator // exact.denominator
+    rd = int(exact + F(1, 2))
+    return {"exact": exact, "floor": fl, "round": rd,
+            "regs_floor": {162: fl & 0xFF, 163: (fl >> 8) & 0xFF, 164: (fl >> 16) & 0x3F},
+            "fits_22bit": fl < (1 << 22)}
+
+
+# ---------------------------------------------------------------------------
+# Constraint checks. Each returns a dict: rule, ok, severity, cite, detail
+# severity: "error" (spec violation) | "advisory" (recommendation, never fails tests)
+# ---------------------------------------------------------------------------
+
+def chk(rule: str, ok: bool, cite: str, detail: str, severity: str = "error") -> Dict[str, object]:
+    return {"rule": rule, "ok": bool(ok), "severity": severity, "cite": cite, "detail": detail}
+
+
+def check_abc_fields(prefix: str, p1: int, p2: int, p3: int) -> List[Dict]:
+    out = [chk(f"{prefix}_P_WIDTH", p1 < (1 << P1_BITS) and p2 < (1 << P2_BITS) and 1 <= p3 < (1 << P3_BITS),
+               "AN619 §3.2/§4.1.2 P1[17:0], P2[19:0], P3[19:0]",
+               f"P1={p1} P2={p2} P3={p3}"),
+           chk(f"{prefix}_C_MAX", 1 <= p3 <= C_MAX, "AN619 §3.2/§4.1.2 (c <= 1,048,575)", f"c=P3={p3}")]
+    return out
+
+
+def check_feedback(p1: int, p2: int, p3: int, fref_hz: F) -> Tuple[List[Dict], F, F]:
+    ratio = decode_p(p1, p2, p3)
+    vco = fref_hz * ratio
+    out = check_abc_fields("FB", p1, p2, p3)
+    out.append(chk("FB_RATIO_RANGE", FB_RATIO_MIN <= ratio <= FB_RATIO_MAX, "AN619 §3.2 (15 .. 90)",
+                   f"a+b/c={float(ratio):.9f}"))
+    out.append(chk("VCO_RANGE", VCO_MIN_HZ <= vco <= VCO_MAX_HZ, "AN619 §2 (600-900 MHz)",
+                   f"fVCO={float(vco):.3f} Hz"))
+    is_even_int = ratio.denominator == 1 and ratio.numerator % 2 == 0
+    if is_even_int:
+        out.append(chk("FB_INT_ADVISORY", False, "AN619 §3.2.1 / Reg 22-23 bit6 FBx_INT",
+                       f"feedback ratio {ratio} is an even integer; FBx_INT=1 'in most cases ... improve jitter' "
+                       "(optional; library never sets FBx_INT)", "advisory"))
+    return out, ratio, vco
+
+
+def check_ms05(p1: int, p2: int, p3: int, divby4: bool, ms_int: bool, f_ms_hz: Optional[F]) -> Tuple[List[Dict], F]:
+    out: List[Dict] = []
+    if divby4:
+        out.append(chk("DIVBY4_PARAMS", (p1, p2, p3) == divby4_params(), "AN619 §4.1.3 (P1=0,P2=0,P3=1)",
+                       f"P=({p1},{p2},{p3})"))
+        out.append(chk("DIVBY4_MS_INT", ms_int, "AN619 §4.1.3 (MSx_INT=1)", f"MS_INT={int(ms_int)}"))
+        ratio = F(4)
+    else:
+        out += check_abc_fields("MS", p1, p2, p3)
+        ratio = decode_p(p1, p2, p3)
+        valid = (ratio.denominator == 1 and ratio.numerator in MS_INT_RATIOS) or (MS_FRAC_MIN <= ratio <= MS_RATIO_MAX)
+        out.append(chk("MS_RATIO_VALID", valid, "AN619 §2.1.1 item 1 / §4.1.2 (4, 6, 8, or 8+1/1048575 .. 2048)",
+                       f"MS ratio={float(ratio):.9f}" + (f" (={ratio})" if ratio.denominator == 1 else "")))
+        if ratio == 4:
+            out.append(chk("RATIO4_NEEDS_DIVBY4", False, "AN619 §4.1.3", "ratio 4 requires DIVBY4=11b encoding"))
+        is_even_int = ratio.denominator == 1 and ratio.numerator % 2 == 0
+        if ms_int:
+            out.append(chk("MS_INT_ONLY_EVEN_INT", is_even_int, "AN619 §4.1.2.1 / Reg 16-21 bit6",
+                           f"MS_INT=1 with ratio {float(ratio)}"))
+        elif is_even_int:
+            out.append(chk("MS_INT_ADVISORY", False, "AN619 §2.1.1 item 2, §4.1.2.1",
+                           f"MS ratio {ratio} is an even integer; MS_INT=1 'in most cases ... improve jitter' (optional)",
+                           "advisory"))
+    if f_ms_hz is not None:
+        out.append(chk("MS_OUT_RANGE", MS_OUT_MIN_HZ <= f_ms_hz <= MS_OUT_MAX_HZ, "AN619 §2 (MS output 500 kHz - 200 MHz)",
+                       f"f_MS={float(f_ms_hz):.3f} Hz"))
+        if f_ms_hz > DIVBY4_ABOVE_HZ:
+            out.append(chk("DIVBY4_REQUIRED", divby4, "AN619 §4.1.3 (150 < Fout <= 200 MHz needs DIVBY4)",
+                           f"f_MS={float(f_ms_hz):.3f} Hz divby4={int(divby4)}"))
+    return out, ratio
+
+
+def check_ms67(ratio_reg: int) -> List[Dict]:
+    return [chk("MS67_RATIO_VALID", ratio_reg % 2 == 0 and MS67_MIN <= ratio_reg <= MS67_MAX,
+                "AN619 §2.2 Note, §4.1.2, Reg 90/91 (even integer 6..254)", f"MSx_P1={ratio_reg}")]
+
+
+def check_out_freq(requested_hz: F, realized_hz: Optional[F], tol_ppb: int = 1000) -> List[Dict]:
+    out = [chk("OUT_FREQ_RANGE", CLKOUT_MIN_HZ <= requested_hz <= CLKOUT_MAX_HZ,
+               "DS Table 7 FCLK 2.5 kHz - 200 MHz", f"requested={float(requested_hz):.3f} Hz")]
+    if realized_hz is not None:
+        err_ppb = (realized_hz - requested_hz) / requested_hz * 10**9
+        out.append(chk("OUT_FREQ_ACCURACY", abs(err_ppb) <= tol_ppb,
+                       f"programmed registers must realize requested freq (tol {tol_ppb} ppb)",
+                       f"realized={float(realized_hz):.6f} Hz err={float(err_ppb):.3f} ppb"))
+    return out
diff --git a/tests/regression/python/test_golden.py b/tests/regression/python/test_golden.py
new file mode 100644
index 0000000..0e35bca
--- /dev/null
+++ b/tests/regression/python/test_golden.py
@@ -0,0 +1,148 @@
+#!/usr/bin/env python3
+"""LIBRARY regression lock: recompute every case from the library mirror and
+require bit-identical match with golden_cases.json (the `spec` block is
+ignored here; see test_spec.py)."""
+from __future__ import annotations
+import json, sys
+from pathlib import Path
+
+import si5351_math as L
+
+ROOT = Path(__file__).resolve().parent
+
+# APIs Coding PM's C++ harness missed — must remain present + asserted here.
+REQUIRED_API_CASES = {
+    "set_phase": ["S-phase-clk0-mask", "D-set_phase-clk6-writes-reserved-171", "A-set_phase-clk1-0x2A"],
+    "init_xtal_load": ["S-xtal-load-6-8-10pF", "D-init-crystal-load-0pF-reserved", "A-init-crystal-load-8pF"],
+    "set_int": ["D-set_int-clk6-sets-FBA_INT-on-fractional-plla", "A-set_int-clk0-ms-int",
+                "A-set_correction-then-set_int-clk0"],
+    "set_pll_input": ["D-set_pll_input-clkin_div-or-without-clear", "A-set_pll_input-clkin-div4-clean"],
+    "set_pll_5mhz_ref": ["D-ref5MHz-pll_calc-stale-a160"],
+    "set_ref_freq_27mhz": ["A-ref27MHz-set_pll-fixed"],  # sixth / adjacent API
+}
+
+MUTATION_GAP_CASES = [
+    "M-clk7-pllb-assignment",
+    "M-set-ms-byte2-rmw",
+    "M-clk5-reset-plla",
+]
+
+
+def norm(o):
+    return json.loads(json.dumps(o, sort_keys=True, default=str))
+
+
+def main() -> int:
+    stored = json.loads((ROOT / "golden_cases.json").read_text())
+    fresh = {c["id"]: c for c in L.build_golden_suite() + L.build_spec_coverage_cases()}
+    st = {c["id"]: {k: v for k, v in c.items() if k != "spec"} for c in stored["cases"]}
+    errors = []
+    if stored["assumptions"]["xtal_hz_default"] != L.SI5351_XTAL_FREQ:
+        errors.append("xtal assumption drift")
+    if set(st) != set(fresh):
+        errors.append(f"case id mismatch: missing={sorted(set(st) - set(fresh))} extra={sorted(set(fresh) - set(st))}")
+    for cid in sorted(set(st) & set(fresh)):
+        if norm(st[cid]) != norm(fresh[cid]):
+            errors.append(f"library mismatch in {cid}")
+
+    f = fresh
+    # ---- classic anchors ----
+    c = f["P0-clk0-common-1-14MHz"]
+    assert (c["ms_a"], c["ms_b"], c["ms_c"], c["ms_p1"], c["ms_p2"], c["ms_p3"]) == (57, 142857, 1_000_000, 6802, 285696, 1_000_000)
+    assert f["P0-clk6-23MHz"]["pll_freq_hz"] == 874_000_000 and f["P0-clk6-23MHz"]["ms_a"] == 38
+    assert f["P0-vcxo-876MHz-40ppm"]["vcxo_bytes"] == [1, 209, 2]
+    assert f["P0-clk0-DIVBY4-200MHz"]["ms_a"] == 4
+    assert f["S-divby4-block-clk3-200MHz"]["lib_ms_regs"]["68"] == 0x0C
+    assert f["S-divby4-block-clk3-200MHz"]["lib_clk_ctrl"]["19"] == 0x4C
+    assert f["S-rdiv-placement-clk2-5kHz"]["lib_ms_regs"]["60"] == 0x72
+    assert f["S-clk6-R6div-100kHz"]["lib_reg92"] == 0x05 and f["S-clk7-R7div-50kHz"]["lib_reg92"] == 0x60
+    assert f["D-clk6-10kHz-ms6-p1-zero"]["lib_ms67_regs"] == {"90": 0}
+    assert f["D-manual-clk7-87p4MHz-p1-truncated"]["lib_ms67_regs"] == {"91": 0}
+    assert f["P1-parity-set_freq-vs-manual-14MHz-pll800"]["ms_match"] is True
+    p2 = f["P1-parity-gt100-set_freq-vs-manual-175MHz"]
+    assert p2["ms_match"] is True and p2["pll_match"] is True
+
+    # ---- Mutation gaps (Coding PM) ----
+    for cid in MUTATION_GAP_CASES:
+        assert cid in f, f"missing mutation-gap case {cid}"
+
+    # M1: CLK7 locked to PLLB (reg 23 = 0x2C); must NOT equal PLLA encoding 0x0C
+    m7 = f["M-clk7-pllb-assignment"]
+    assert m7["pll_assignment"] == "PLLB"
+    assert m7["pll_assignment_table"]["7"] == "PLLB"
+    assert m7["lib_write"] == {"reg": 23, "value": 0x2C}
+    assert m7["lib_write"]["value"] != m7["mutation_fail_if"]["clk7_ctrl_equals"]  # 0x0C
+    assert m7["pll_assignment_table"]["7"] != m7["mutation_fail_if"]["pll_assignment_7"]
+
+    # M2: set_ms + ms_div RMW — final byte 0xF2; naive mutations 0x70 / 0x72 must differ
+    mrmw = f["M-set-ms-byte2-rmw"]
+    assert mrmw["prior_byte2"] == 0xFF
+    assert mrmw["lib_ms_regs"]["44"] == 0xF2
+    assert (mrmw["lib_ms_regs"]["44"] & 0x80) == 0x80  # bit7 preserved
+    assert (mrmw["lib_ms_regs"]["44"] & 0x03) == 0x02  # P1[17:16]
+    assert (mrmw["lib_ms_regs"]["44"] >> 4) & 0x07 == 7  # R_DIV=128
+    md = mrmw["rmw_transcript"]["mutation_detectors"]
+    assert md["naive_ms_div_overwrite"] == 0x70
+    assert md["naive_set_ms_then_correct_ms_div"] == 0x72
+    assert mrmw["lib_ms_regs"]["44"] not in (0x70, 0x72)
+    assert mrmw["rmw_transcript"]["final"] == 0xF2
+    assert "si5351_read" in mrmw["rmw_transcript"]["steps"][0]["op"]
+
+    # M3: CLK5 locked to PLLA (reg 21 = 0x0C); must NOT equal PLLB encoding 0x2C
+    m5 = f["M-clk5-reset-plla"]
+    assert m5["pll_assignment"] == "PLLA"
+    assert m5["pll_assignment_table"]["5"] == "PLLA"
+    assert m5["lib_write"] == {"reg": 21, "value": 0x0C}
+    assert m5["lib_write"]["value"] != m5["mutation_fail_if"]["clk5_ctrl_equals"]  # 0x2C
+    assert m5["pll_assignment_table"]["5"] != m5["mutation_fail_if"]["pll_assignment_5"]
+
+    # ---- Six APIs Coding PM harness missed (explicit automation) ----
+    for api, ids in REQUIRED_API_CASES.items():
+        for cid in ids:
+            assert cid in f, f"API {api}: missing case {cid}"
+
+    # set_phase
+    assert f["S-phase-clk0-mask"]["lib_write"] == {"reg": 165, "value": 0x7F}
+    assert f["D-set_phase-clk6-writes-reserved-171"]["lib_write"] == {"reg": 171, "value": 10}  # DEV-09
+    assert f["A-set_phase-clk1-0x2A"]["lib_write"] == {"reg": 166, "value": 0x2A}
+
+    # crystal load
+    assert f["S-xtal-load-6-8-10pF"]["lib_writes"] == {"6pF": 0x52, "8pF": 0x92, "10pF": 0xD2}
+    assert f["D-init-crystal-load-0pF-reserved"]["lib_writes"] == {"0pF": 0x12}  # DEV-10
+    assert f["A-init-crystal-load-8pF"]["lib_writes"] == {"8pF": 0x92}
+
+    # set_int
+    assert f["D-set_int-clk6-sets-FBA_INT-on-fractional-plla"]["lib_write"] == {"reg": 22, "value": 0x6C}  # DEV-11
+    assert f["A-set_int-clk0-ms-int"]["lib_write"] == {"reg": 16, "value": 0x4C}
+    assert f["A-set_correction-then-set_int-clk0"]["lib_write"] == {"reg": 16, "value": 0x4C}
+
+    # set_pll_input
+    assert f["D-set_pll_input-clkin_div-or-without-clear"]["lib_write"]["value"] == 0xC4  # DEV-12
+    assert f["A-set_pll_input-clkin-div4-clean"]["lib_write"] == {"reg": 15, "value": 0x84}
+
+    # 5 MHz-ref set_pll (DEV-13)
+    r5 = f["D-ref5MHz-pll_calc-stale-a160"]
+    assert r5["xtal_hz"] == 5_000_000 and r5["pll_a"] == 160
+    assert r5["lib_pll_regs"]["29"] == 0x4E and r5["lib_pll_regs"]["30"] == 0x00
+
+    # sixth / adjacent: 27 MHz in-spec ref via set_ref_freq + set_pll
+    r27 = f["A-ref27MHz-set_pll-fixed"]
+    assert r27["xtal_hz"] == 27_000_000
+    assert r27["pll_a"] == 29  # floor(800e6/27e6)=29
+    assert "lib_pll_regs" in r27
+
+    if errors:
+        print("FAIL:")
+        for e in errors:
+            print(" -", e)
+        return 1
+    print(f"OK: {len(fresh)} library golden cases bit-identical "
+          f"({stored['original_case_count']} original + {stored['new_case_count']} new)")
+    print(f"    mutation gaps locked: {', '.join(MUTATION_GAP_CASES)}")
+    print(f"    APIs automated: {', '.join(REQUIRED_API_CASES)}")
+    print(f"    XTAL={L.SI5351_XTAL_FREQ} PLL_FIXED={L.SI5351_PLL_FIXED} MULT={L.SI5351_FREQ_MULT}")
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/tests/regression/python/test_spec.py b/tests/regression/python/test_spec.py
new file mode 100644
index 0000000..0881524
--- /dev/null
+++ b/tests/regression/python/test_spec.py
@@ -0,0 +1,86 @@
+#!/usr/bin/env python3
+"""SPEC conformance: evaluate every library case against the independent
+AN619/datasheet oracle.
+
+Outcomes per case:
+  PASS   no error-severity rule failed and none expected
+  XFAIL  exactly the expected (known-deviation) rules failed  -> library behaviour
+         is locked, spec deviation is documented in DEVIATION_CATALOG
+  XPASS  a known deviation no longer reproduces -> FAIL (strict): the library
+         changed behaviour; update goldens + catalogue deliberately
+  FAIL   unexpected spec failure, register-encoding disagreement, or the stored
+         spec block drifted
+Exit code 0 iff no FAIL/XPASS.
+"""
+from __future__ import annotations
+import json, sys
+from pathlib import Path
+
+import si5351_math as L
+import spec_oracle as S
+from spec_crosscheck import evaluate, KNOWN_DEVIATIONS, DEVIATION_CATALOG
+
+ROOT = Path(__file__).resolve().parent
+
+
+def norm(o):
+    return json.loads(json.dumps(o, sort_keys=True, default=str))
+
+
+def unit_checks():
+    """Spot checks of the oracle itself against numbers stated in AN619."""
+    assert S.encode_abc(4, 0, 1) == (0, 0, 1)                       # ratio 4 -> P1=0 (DIVBY4 encoding consistent)
+    assert S.decode_p(*S.encode_abc(57, 142857, 1_000_000)) == 57 + S.F(142857, 1_000_000)
+    assert S.feedback_block("PLLB", 1, 2, 0xABCDE)[39] == 0xA0       # P3[19:16] high nibble of reg 39
+    assert S.feedback_block("PLLA", 0x3FFFF, 0xFFFFF, 1)[28] == 0x03 and S.feedback_block("PLLA", 0, 0xF0000, 1)[31] == 0x0F
+    assert S.ms_block(0, 0, 0, 1, r=128, divby4=True)[44] == 0x7C
+    assert S.reg92(r6=128, r7=128) == 0x77
+    assert S.clk_ctrl(0) == 0x0C and S.clk_ctrl(6, src_pllb=1) == 0x2C and S.clk_ctrl(0, int_bit=1) == 0x4C
+    assert S.pll_reset_byte(True, True) == 0xA0
+    assert S.xtal_cl_byte(3) == 0xD2
+    assert S.phase_reg(5, 0xFF) == (170, 0x7F)
+    assert S.vcxo_param(32, 0, 100)["floor"] == 421888                # 1.03*128*32*100 exactly
+    assert S.phase_word(S.F(1, 10**9), S.F(800_000_000)) == 3         # 1 ns at 800 MHz = 3.2 LSB -> 3 (DS PSTEP ~333 ps)
+
+
+def main() -> int:
+    unit_checks()
+    stored = {c["id"]: c for c in json.loads((ROOT / "golden_cases.json").read_text())["cases"]}
+    cases = L.build_golden_suite() + L.build_spec_coverage_cases()
+    counts = {"PASS": 0, "XFAIL": 0, "XPASS": 0, "FAIL": 0}
+    lines = []
+    for c in cases:
+        s = evaluate(c)
+        exp = KNOWN_DEVIATIONS.get(c["id"], {}).get("rules", set())
+        got = set(s["failed_rules"])
+        problems = []
+        if s["register_agreement"] is False:
+            problems.append("register encoding disagrees with AN619")
+        if c["id"] in stored and norm(stored[c["id"]].get("spec")) != norm(s):
+            problems.append("stored spec block drifted (regenerate deliberately)")
+        if got - exp:
+            problems.append(f"unexpected spec failures {sorted(got - exp)}")
+        if exp - got:
+            outcome = "XPASS"
+            problems.append(f"expected deviation no longer reproduces: {sorted(exp - got)}")
+        elif problems:
+            outcome = "FAIL"
+        elif exp:
+            outcome = "XFAIL"
+        else:
+            outcome = "PASS"
+        counts[outcome] += 1
+        devs = ",".join(KNOWN_DEVIATIONS.get(c["id"], {}).get("devs", []))
+        lines.append(f"{outcome:5s} {c['id']}" + (f"  [{devs}]" if devs else "") +
+                     (f"  !! {'; '.join(problems)}" if problems else ""))
+    print("\n".join(lines))
+    print()
+    print(f"spec oracle unit checks: OK")
+    print(f"summary: {counts['PASS']} passed, {counts['XFAIL']} xfailed (known deviations), "
+          f"{counts['XPASS']} xpassed, {counts['FAIL']} failed  — {len(cases)} cases, "
+          f"{len(DEVIATION_CATALOG)} catalogued deviations")
+    return 0 if counts["FAIL"] == 0 and counts["XPASS"] == 0 else 1
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/tests/regression/reference/master_1ddd43e/SHA256SUMS b/tests/regression/reference/master_1ddd43e/SHA256SUMS
new file mode 100644
index 0000000..80c8e60
--- /dev/null
+++ b/tests/regression/reference/master_1ddd43e/SHA256SUMS
@@ -0,0 +1,2 @@
+3b412924878d7de963a31f47d40ac52bd60f750b7047066cb68fe203e82c18ab  master_1ddd43e/si5351.cpp
+a98427cf3e53ebdafddafbc4f87a40a3047ee14d8d4fad884b9fbbd673f86012  master_1ddd43e/si5351.h
diff --git a/tests/regression/reference/master_1ddd43e/si5351.cpp b/tests/regression/reference/master_1ddd43e/si5351.cpp
new file mode 100644
index 0000000..a6bfcf7
--- /dev/null
+++ b/tests/regression/reference/master_1ddd43e/si5351.cpp
@@ -0,0 +1,1603 @@
+/*
+ * si5351.cpp - Si5351 library for Arduino
+ *
+ * Copyright (C) 2015 - 2019 Jason Milldrum <milldrum@gmail.com>
+ *                           Dana H. Myers <k6jq@comcast.net>
+ *
+ * Some tuning algorithms derived from clk-si5351.c in the Linux kernel.
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdint.h>
+
+#include "Arduino.h"
+#include "Wire.h"
+#include "si5351.h"
+
+
+/*********************/
+/* File-local helpers */
+/*********************/
+
+/* Pack p1/p2/p3 into the 8-byte Si5351 parameter block used by PLL/MS regs.
+ * p1_extra is ORed into the p1[17:16] byte (byte 2); set_ms uses this to
+ * preserve other bits already in that register. set_pll/set_vcxo pass 0. */
+// Set while set_freq() re-plans a PLL: it resets that PLL once after all
+// PLL and MS writes, so set_ms() must not issue its own DIVBY4-exit reset.
+static uint8_t defer_pll_reset;
+
+static void pack_reg_set(const struct Si5351RegSet *reg, uint8_t *params, uint8_t p1_extra)
+{
+	params[0] = (uint8_t)((reg->p3 >> 8) & 0xFF);
+	params[1] = (uint8_t)(reg->p3 & 0xFF);
+	params[2] = (uint8_t)(((reg->p1 >> 16) & 0x03) | p1_extra);
+	params[3] = (uint8_t)((reg->p1 >> 8) & 0xFF);
+	params[4] = (uint8_t)(reg->p1 & 0xFF);
+	params[5] = (uint8_t)(((reg->p3 >> 12) & 0xF0) | ((reg->p2 >> 16) & 0x0F));
+	params[6] = (uint8_t)((reg->p2 >> 8) & 0xFF);
+	params[7] = (uint8_t)(reg->p2 & 0xFF);
+}
+
+/* Fractional feedback a + b/c -> {p1,p2,p3}; compute (128*b)/c once. */
+static void frac_to_reg(uint32_t a, uint32_t b, uint32_t c, struct Si5351RegSet *reg)
+{
+	uint32_t rem = (128 * b) / c;
+	reg->p1 = 128 * a + rem - 512;
+	reg->p2 = 128 * b - c * rem;
+	reg->p3 = c;
+}
+
+
+
+/********************/
+/* Public functions */
+/********************/
+
+Si5351::Si5351(uint8_t i2c_addr):
+	i2c_bus_addr(i2c_addr)
+{
+	xtal_freq[0] = SI5351_XTAL_FREQ;
+
+	// Start by using XO ref osc as default for each PLL
+	plla_ref_osc = SI5351_PLL_INPUT_XO;
+	pllb_ref_osc = SI5351_PLL_INPUT_XO;
+	clkin_div = SI5351_CLKIN_DIV_1;
+}
+
+/*
+ * init(uint8_t xtal_load_c, uint32_t ref_osc_freq, int32_t corr)
+ *
+ * Setup communications to the Si5351 and set the crystal
+ * load capacitance.
+ *
+ * xtal_load_c - Crystal load capacitance. Use the SI5351_CRYSTAL_LOAD_*PF
+ * defines in the header file
+ * xo_freq - Crystal/reference oscillator frequency in 1 Hz increments.
+ * Defaults to 25000000 if a 0 is used here.
+ * corr - Frequency correction constant in parts-per-billion
+ *
+ * Returns a boolean that indicates whether a device was found on the desired
+ * I2C address.
+ *
+ */
+bool Si5351::init(uint8_t xtal_load_c, uint32_t xo_freq, int32_t corr)
+{
+	// Start I2C comms
+	Wire.begin();
+
+	// Check for a device on the bus, bail out if it is not there
+	Wire.beginTransmission(i2c_bus_addr);
+	uint8_t reg_val;
+  reg_val = Wire.endTransmission();
+
+	if(reg_val == 0)
+	{
+		// Wait for SYS_INIT flag to be clear, indicating that device is ready
+		uint8_t status_reg = 0;
+		do
+		{
+			status_reg = si5351_read(SI5351_DEVICE_STATUS);
+		} while (status_reg >> 7 == 1);
+
+		// Set crystal load capacitance
+		si5351_write(SI5351_CRYSTAL_LOAD, (xtal_load_c & SI5351_CRYSTAL_LOAD_MASK) | 0b00010010);
+
+		// Set up the XO and CLKIN reference frequencies
+		if (xo_freq != 0)
+		{
+			set_ref_freq(xo_freq, SI5351_PLL_INPUT_XO);
+            set_ref_freq(xo_freq, SI5351_PLL_INPUT_CLKIN);          //Also CLKIN
+		}
+		else
+		{
+			set_ref_freq(SI5351_XTAL_FREQ, SI5351_PLL_INPUT_XO);
+            set_ref_freq(SI5351_XTAL_FREQ, SI5351_PLL_INPUT_CLKIN); //Also CLKIN
+		}
+
+		// Set the frequency calibrations for the XO and CLKIN
+		set_correction(corr, SI5351_PLL_INPUT_XO);
+        set_correction(corr, SI5351_PLL_INPUT_CLKIN);
+
+		reset();
+
+		return true;
+	}
+	else
+	{
+		return false;
+	}
+}
+
+/*
+ * reset(void)
+ *
+ * Call to reset the Si5351 to the state initialized by the library.
+ *
+ */
+void Si5351::reset(void)
+{
+	uint8_t i;
+
+	// Initialize the CLK outputs according to flowchart in datasheet
+	// First, turn them off
+	for(i = 0; i < 8; i++)
+	{
+		si5351_write(SI5351_CLK0_CTRL + i, 0x80);
+	}
+
+	// Turn the clocks back on...
+	for(i = 0; i < 8; i++)
+	{
+		si5351_write(SI5351_CLK0_CTRL + i, 0x0c);
+	}
+
+	// Set PLLA and PLLB to 800 MHz for automatic tuning
+	set_pll(SI5351_PLL_FIXED, SI5351_PLLA);
+	set_pll(SI5351_PLL_FIXED, SI5351_PLLB);
+
+	// Make PLL to CLK assignments for automatic tuning
+	// set_ms_source also updates pll_assignment[]
+	for(i = 0; i < 6; i++)
+	{
+		set_ms_source((enum si5351_clock)i, SI5351_PLLA);
+	}
+	for(i = 6; i < 8; i++)
+	{
+		set_ms_source((enum si5351_clock)i, SI5351_PLLB);
+	}
+
+	// Reset the VCXO param
+	si5351_write(SI5351_VXCO_PARAMETERS_LOW, 0);
+	si5351_write(SI5351_VXCO_PARAMETERS_MID, 0);
+	si5351_write(SI5351_VXCO_PARAMETERS_HIGH, 0);
+
+	// Then reset the PLLs
+	pll_reset(SI5351_PLLA);
+	pll_reset(SI5351_PLLB);
+
+	// Set initial frequencies
+	for(i = 0; i < 8; i++)
+	{
+		clk_freq[i] = 0;
+		output_enable((enum si5351_clock)i, 0);
+		clk_first_set[i] = false;
+	}
+}
+
+/*
+ * set_freq(uint64_t freq, enum si5351_clock clk)
+ *
+ * Sets the clock frequency of the specified CLK output.
+ * Frequency range of 8 kHz to 150 MHz
+ *
+ * freq - Output frequency in Hz
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ */
+uint8_t Si5351::set_freq(uint64_t freq, enum si5351_clock clk)
+{
+	struct Si5351RegSet ms_reg;
+	uint64_t pll_freq;
+	uint8_t int_mode = 0;
+	uint8_t div_by_4 = 0;
+	uint8_t r_div = 0;
+
+	// Check which Multisynth is being set
+	if((uint8_t)clk <= (uint8_t)SI5351_CLK5)
+	{
+		// MS0 through MS5 logic
+		// ---------------------
+
+		// Lower bounds check
+		if(freq > 0 && freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT)
+		{
+			freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT;
+		}
+
+		// Upper bounds check
+		if(freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT)
+		{
+			freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT;
+		}
+
+		// Is another output on the same PLL already >100 MHz (and so
+		// holding the PLL at a frequency chosen for it)?
+		uint8_t i;
+		uint8_t pll_held = 0;
+		for(i = 0; i < 6; i++)
+		{
+			if(clk_freq[i] > (SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT)
+				&& i != (uint8_t)clk && pll_assignment[i] == pll_assignment[clk])
+			{
+				pll_held = 1;
+			}
+		}
+
+		// Enable the output on first set_freq only
+		// (a >100 MHz request is refused below if the PLL is held)
+		if(!(pll_held && freq > (SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT))
+			&& clk_first_set[(uint8_t)clk] == false)
+		{
+			output_enable(clk, 1);
+			clk_first_set[(uint8_t)clk] = true;
+		}
+
+		// If requested freq >100 MHz and no other outputs are already >100 MHz,
+		// we need to recalculate PLLA and then recalculate all other CLK outputs
+		// on same PLL
+		if(freq > (SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT))
+		{
+			if(pll_held)
+			{
+				return 1; // won't set if any other clks already >100 MHz
+			}
+
+			// Set the freq in memory
+			clk_freq[(uint8_t)clk] = freq;
+
+			// Calculate the proper PLL frequency
+			pll_freq = multisynth_calc(freq, 0, &ms_reg);
+		}
+		else
+		{
+			clk_freq[(uint8_t)clk] = freq;
+
+			// Select the proper R div value
+			r_div = select_r_div(&freq, SI5351_CLKOUT_MIN_FREQ);
+
+			pll_freq = (pll_assignment[clk] == SI5351_PLLA) ? plla_freq : pllb_freq;
+
+			// A >100 MHz setting can leave the PLL low (e.g. 620 MHz for 155 MHz),
+			// making the MS ratio for this output < 8, outside the valid
+			// fractional range (155 -> 96 MHz gave ~88.5 MHz, issue #65). If no
+			// other output holds the PLL, re-plan it at the fixed 800 MHz below.
+			uint8_t replan = 0;
+			if(pll_freq < freq * 8)
+			{
+				replan = 1;
+				if(pll_held)
+				{
+					// The PLL is held above 100 MHz by another output (#65:
+					// 155 MHz on CLK0, then 99 MHz on CLK2), so move this output
+					// to the other PLL: reuse it as is if it gives a valid ratio,
+					// or re-plan it if no other output uses it. Otherwise keep
+					// the old behaviour.
+					enum si5351_pll other = (pll_assignment[clk] == SI5351_PLLA) ? SI5351_PLLB : SI5351_PLLA;
+					uint64_t other_freq = (other == SI5351_PLLA) ? plla_freq : pllb_freq;
+					uint8_t other_used = 0;
+					for(i = 0; i < 8; i++)
+					{
+						if(i != (uint8_t)clk && clk_freq[i] != 0 && pll_assignment[i] == other)
+						{
+							other_used = 1;
+						}
+					}
+
+					replan = 0;
+					if(other_freq >= freq * 8)
+					{
+						set_ms_source(clk, other);
+						pll_freq = other_freq;
+					}
+					else if(!other_used)
+					{
+						set_ms_source(clk, other);
+						replan = 1;
+					}
+				}
+			}
+
+			if(!replan)
+			{
+				// Calculate the synth parameters
+				multisynth_calc(freq, pll_freq, &ms_reg);
+
+				// Set multisynth registers
+				set_ms(clk, ms_reg, int_mode, r_div, div_by_4);
+
+				return 0;
+			}
+
+			pll_freq = SI5351_PLL_FIXED;
+		}
+
+		// Set PLL
+		set_pll(pll_freq, pll_assignment[clk]);
+
+		// Recalculate params for other synths on same PLL
+		defer_pll_reset = 1;
+		for(i = 0; i < 6; i++)
+		{
+			if(clk_freq[i] != 0 && pll_assignment[i] == pll_assignment[clk])
+			{
+				struct Si5351RegSet temp_reg;
+				uint64_t temp_freq;
+
+				// Select the proper R div value
+				temp_freq = clk_freq[i];
+				r_div = select_r_div(&temp_freq, SI5351_CLKOUT_MIN_FREQ);
+
+				multisynth_calc(temp_freq, pll_freq, &temp_reg);
+
+				// If freq > 150 MHz, we need to use DIVBY4 and integer mode
+				div_by_4 = (temp_freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT);
+
+				// Set multisynth registers
+				set_ms((enum si5351_clock)i, temp_reg, div_by_4, r_div, div_by_4);
+			}
+		}
+
+		// Reset the PLL (once, after all PLL and MS writes)
+		defer_pll_reset = 0;
+		pll_reset(pll_assignment[clk]);
+
+		return 0;
+	}
+	else
+	{
+		// MS6 and MS7 logic
+		// -----------------
+		uint8_t peer = (clk == SI5351_CLK6) ? (uint8_t)SI5351_CLK7 : (uint8_t)SI5351_CLK6;
+
+		// Lower bounds check
+		// Note: clamps to SI5351_CLKOUT_MIN_FREQ (not CLKOUT67) — preserved as-is
+		if(freq > 0 && freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT)
+		{
+			freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT;
+		}
+
+		// Upper bounds check
+		if(freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT)
+		{
+			freq = SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT - 1;
+		}
+
+		// If one of CLK6 or CLK7 is already set when trying to set the other,
+		// we have to ensure that it will also have an integer division ratio
+		// with the same PLL, otherwise do not set it.
+		if(clk_freq[peer] != 0)
+		{
+			if(pllb_freq % freq == 0)
+			{
+				if((pllb_freq / freq) % 2 != 0)
+				{
+					// Not an even divide ratio, no bueno
+					return 1;
+				}
+				else
+				{
+					// Set the freq in memory
+					clk_freq[(uint8_t)clk] = freq;
+
+					// Select the proper R div value
+					r_div = select_r_div(&freq, SI5351_CLKOUT67_MIN_FREQ);
+
+					multisynth67_calc(freq, pllb_freq, &ms_reg);
+				}
+			}
+			else
+			{
+				// Not an integer divide ratio, no good
+				return 1;
+			}
+		}
+		else
+		{
+			// No previous assignment, so set PLLB based on this clock
+
+			// Set the freq in memory
+			clk_freq[(uint8_t)clk] = freq;
+
+			// Select the proper R div value
+			r_div = select_r_div(&freq, SI5351_CLKOUT67_MIN_FREQ);
+
+			pll_freq = multisynth67_calc(freq, 0, &ms_reg);
+			// Preserve original asymmetry: CLK6 hardcodes PLLB; CLK7 uses assignment
+			if(clk == SI5351_CLK6)
+			{
+				set_pll(pll_freq, SI5351_PLLB);
+			}
+			else
+			{
+				set_pll(pll_freq, pll_assignment[clk]);
+			}
+		}
+
+		div_by_4 = 0;
+		int_mode = 0;
+
+		// Set multisynth registers (MS must be set before PLL)
+		set_ms(clk, ms_reg, int_mode, r_div, div_by_4);
+
+		return 0;
+	}
+}
+
+/*
+ * set_freq_manual(uint64_t freq, uint64_t pll_freq, enum si5351_clock clk)
+ *
+ * Sets the clock frequency of the specified CLK output using the given PLL
+ * frequency. You must ensure that the MS is assigned to the correct PLL and
+ * that the PLL is set to the correct frequency before using this method.
+ *
+ * It is important to note that if you use this method, you will have to
+ * track that all settings are sane yourself.
+ *
+ * freq - Output frequency in Hz
+ * pll_freq - Frequency of the PLL driving the Multisynth in Hz * 100
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ */
+uint8_t Si5351::set_freq_manual(uint64_t freq, uint64_t pll_freq, enum si5351_clock clk)
+{
+	struct Si5351RegSet ms_reg;
+	uint8_t int_mode = 0;
+	uint8_t div_by_4 = 0;
+
+	// Lower bounds check
+	if(freq > 0 && freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT;
+	}
+
+	// Upper bounds check
+	if(freq > SI5351_CLKOUT_MAX_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_CLKOUT_MAX_FREQ * SI5351_FREQ_MULT;
+	}
+
+	uint8_t r_div;
+
+	clk_freq[(uint8_t)clk] = freq;
+
+	set_pll(pll_freq, pll_assignment[clk]);
+
+	// Enable the output
+	output_enable(clk, 1);
+
+	// Select the proper R div value
+	r_div = select_r_div(&freq, SI5351_CLKOUT_MIN_FREQ);
+
+	// Calculate the synth parameters
+	multisynth_calc(freq, pll_freq, &ms_reg);
+
+	// If freq > 150 MHz, we need to use DIVBY4 and integer mode
+	if(freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT)
+	{
+		div_by_4 = 1;
+		int_mode = 1;
+	}
+
+	// Set multisynth registers (MS must be set before PLL)
+	set_ms(clk, ms_reg, int_mode, r_div, div_by_4);
+
+    return 0;
+}
+
+/*
+ * set_pll(uint64_t pll_freq, enum si5351_pll target_pll)
+ *
+ * Set the specified PLL to a specific oscillation frequency
+ *
+ * pll_freq - Desired PLL frequency in Hz * 100
+ * target_pll - Which PLL to set
+ *     (use the si5351_pll enum)
+ */
+void Si5351::set_pll(uint64_t pll_freq, enum si5351_pll target_pll)
+{
+	struct Si5351RegSet pll_reg;
+	uint8_t params[SI5351_PARAMETERS_LENGTH];
+
+	if(target_pll == SI5351_PLLA)
+	{
+		pll_calc(SI5351_PLLA, pll_freq, &pll_reg, ref_correction[plla_ref_osc], 0);
+	}
+	else
+	{
+		pll_calc(SI5351_PLLB, pll_freq, &pll_reg, ref_correction[pllb_ref_osc], 0);
+	}
+
+	// Derive the register values to write
+	pack_reg_set(&pll_reg, params, 0);
+
+	// Write the parameters
+	if(target_pll == SI5351_PLLA)
+	{
+		si5351_write_bulk(SI5351_PLLA_PARAMETERS, SI5351_PARAMETERS_LENGTH, params);
+		plla_freq = pll_freq;
+	}
+	else if(target_pll == SI5351_PLLB)
+	{
+		si5351_write_bulk(SI5351_PLLB_PARAMETERS, SI5351_PARAMETERS_LENGTH, params);
+		pllb_freq = pll_freq;
+	}
+}
+
+/*
+ * set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4)
+ *
+ * Set the specified multisynth parameters. Not normally needed, but public for advanced users.
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * int_mode - Set integer mode
+ *  Set to 1 to enable, 0 to disable
+ * r_div - Desired r_div ratio
+ * div_by_4 - Set Divide By 4 mode
+ *   Set to 1 to enable, 0 to disable
+ */
+void Si5351::set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4)
+{
+	uint8_t params[SI5351_PARAMETERS_LENGTH];
+
+	if((uint8_t)clk <= (uint8_t)SI5351_CLK5)
+	{
+		// Preserve non-p1 bits in the p1[17:16] parameter byte
+		uint8_t reg_val = si5351_read((SI5351_CLK0_PARAMETERS + 2) + ((uint8_t)clk * 8));
+		// MS currently in DIVBY4 mode and being switched out of it? (#65)
+		uint8_t leaving_divby4 = ((reg_val & SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) && !div_by_4;
+		reg_val &= ~(0x03);
+		pack_reg_set(&ms_reg, params, reg_val);
+
+		// CLK0..CLK5 parameter blocks are linear: base + clk*8
+		si5351_write_bulk(SI5351_CLK0_PARAMETERS + ((uint8_t)clk * 8),
+			SI5351_PARAMETERS_LENGTH, params);
+		set_int(clk, int_mode);
+		ms_div(clk, r_div, div_by_4);
+
+		// A Multisynth leaving DIVBY4 mode produces no output until its PLL is
+		// reset (issue #65, e.g. 156 MHz -> 80 MHz). Reset only on that
+		// transition so normal tuning stays glitch-free. reset() leaves the
+		// DIVBY4 bits set, so this also covers reset() followed by set_freq().
+		if(leaving_divby4 && !defer_pll_reset)
+		{
+			pll_reset(pll_assignment[clk]);
+		}
+	}
+	else if((uint8_t)clk <= (uint8_t)SI5351_CLK7)
+	{
+		// MS6 and MS7 only use one register (90 / 91).
+		// Bounded to CLK7 so an out-of-range clk writes nothing, as the
+		// original switch() did (otherwise clk=8 would clobber reg 92).
+		si5351_write(SI5351_CLK6_PARAMETERS + ((uint8_t)clk - (uint8_t)SI5351_CLK6),
+			(uint8_t)ms_reg.p1);
+		ms_div(clk, r_div, div_by_4);
+	}
+}
+
+/*
+ * output_enable(enum si5351_clock clk, uint8_t enable)
+ *
+ * Enable or disable a chosen output
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * enable - Set to 1 to enable, 0 to disable
+ */
+void Si5351::output_enable(enum si5351_clock clk, uint8_t enable)
+{
+  uint8_t reg_val;
+
+  reg_val = si5351_read(SI5351_OUTPUT_ENABLE_CTRL);
+
+  if(enable == 1)
+  {
+    reg_val &= ~(1<<(uint8_t)clk);
+  }
+  else
+  {
+    reg_val |= (1<<(uint8_t)clk);
+  }
+
+  si5351_write(SI5351_OUTPUT_ENABLE_CTRL, reg_val);
+}
+
+/*
+ * drive_strength(enum si5351_clock clk, enum si5351_drive drive)
+ *
+ * Sets the drive strength of the specified clock output
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * drive - Desired drive level
+ *   (use the si5351_drive enum)
+ */
+void Si5351::drive_strength(enum si5351_clock clk, enum si5351_drive drive)
+{
+  uint8_t reg_val;
+  const uint8_t mask = 0x03;
+
+  reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+  reg_val &= ~(mask);
+
+  switch(drive)
+  {
+  case SI5351_DRIVE_2MA:
+    reg_val |= 0x00;
+    break;
+  case SI5351_DRIVE_4MA:
+   reg_val |= 0x01;
+    break;
+  case SI5351_DRIVE_6MA:
+    reg_val |= 0x02;
+    break;
+  case SI5351_DRIVE_8MA:
+    reg_val |= 0x03;
+    break;
+  default:
+    break;
+  }
+
+  si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+}
+
+/*
+ * update_status(void)
+ *
+ * Call this to update the status structs, then access them
+ * via the dev_status and dev_int_status global members.
+ *
+ * See the header file for the struct definitions. These
+ * correspond to the flag names for registers 0 and 1 in
+ * the Si5351 datasheet.
+ */
+void Si5351::update_status(void)
+{
+	update_sys_status(&dev_status);
+	update_int_status(&dev_int_status);
+}
+
+/*
+ * set_correction(int32_t corr, enum si5351_pll_input ref_osc)
+ *
+ * corr - Correction factor in ppb
+ * ref_osc - Desired reference oscillator
+ *     (use the si5351_pll_input enum)
+ *
+ * Use this to set the oscillator correction factor.
+ * This value is a signed 32-bit integer of the
+ * parts-per-billion value that the actual oscillation
+ * frequency deviates from the specified frequency.
+ *
+ * The frequency calibration is done as a one-time procedure.
+ * Any desired test frequency within the normal range of the
+ * Si5351 should be set, then the actual output frequency
+ * should be measured as accurately as possible. The
+ * difference between the measured and specified frequencies
+ * should be calculated in Hertz, then multiplied by 10 in
+ * order to get the parts-per-billion value.
+ *
+ * Since the Si5351 itself has an intrinsic 0 PPM error, this
+ * correction factor is good across the entire tuning range of
+ * the Si5351. Once this calibration is done accurately, it
+ * should not have to be done again for the same Si5351 and
+ * crystal.
+ */
+void Si5351::set_correction(int32_t corr, enum si5351_pll_input ref_osc)
+{
+	ref_correction[(uint8_t)ref_osc] = corr;
+
+	// Recalculate and set PLL freqs based on correction value
+	set_pll(plla_freq, SI5351_PLLA);
+	set_pll(pllb_freq, SI5351_PLLB);
+}
+
+/*
+ * set_phase(enum si5351_clock clk, uint8_t phase)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * phase - 7-bit phase word
+ *   (in units of VCO/4 period)
+ *
+ * Write the 7-bit phase register. This must be used
+ * with a user-set PLL frequency so that the user can
+ * calculate the proper tuning word based on the PLL period.
+ */
+void Si5351::set_phase(enum si5351_clock clk, uint8_t phase)
+{
+	// Mask off the upper bit since it is reserved
+	phase = phase & 0b01111111;
+
+	si5351_write(SI5351_CLK0_PHASE_OFFSET + (uint8_t)clk, phase);
+}
+
+/*
+ * get_correction(enum si5351_pll_input ref_osc)
+ *
+ * ref_osc - Desired reference oscillator
+ *     0: crystal oscillator (XO)
+ *     1: external clock input (CLKIN)
+ *
+ * Returns the oscillator correction factor stored
+ * in RAM.
+ */
+int32_t Si5351::get_correction(enum si5351_pll_input ref_osc)
+{
+	return ref_correction[(uint8_t)ref_osc];
+}
+
+/*
+ * pll_reset(enum si5351_pll target_pll)
+ *
+ * target_pll - Which PLL to reset
+ *     (use the si5351_pll enum)
+ *
+ * Apply a reset to the indicated PLL.
+ */
+void Si5351::pll_reset(enum si5351_pll target_pll)
+{
+	if(target_pll == SI5351_PLLA)
+ 	{
+    	si5351_write(SI5351_PLL_RESET, SI5351_PLL_RESET_A);
+	}
+	else if(target_pll == SI5351_PLLB)
+	{
+	    si5351_write(SI5351_PLL_RESET, SI5351_PLL_RESET_B);
+	}
+}
+
+/*
+ * set_ms_source(enum si5351_clock clk, enum si5351_pll pll)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * pll - Which PLL to use as the source
+ *     (use the si5351_pll enum)
+ *
+ * Set the desired PLL source for a multisynth.
+ */
+void Si5351::set_ms_source(enum si5351_clock clk, enum si5351_pll pll)
+{
+	uint8_t reg_val;
+
+	reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+
+	if(pll == SI5351_PLLA)
+	{
+		reg_val &= ~(SI5351_CLK_PLL_SELECT);
+	}
+	else if(pll == SI5351_PLLB)
+	{
+		reg_val |= SI5351_CLK_PLL_SELECT;
+	}
+
+	si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+
+	pll_assignment[(uint8_t)clk] = pll;
+}
+
+/*
+ * set_int(enum si5351_clock clk, uint8_t int_mode)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * enable - Set to 1 to enable, 0 to disable
+ *
+ * Set the indicated multisynth into integer mode.
+ */
+void Si5351::set_int(enum si5351_clock clk, uint8_t enable)
+{
+	uint8_t reg_val;
+	reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+
+	if(enable == 1)
+	{
+		reg_val |= (SI5351_CLK_INTEGER_MODE);
+	}
+	else
+	{
+		reg_val &= ~(SI5351_CLK_INTEGER_MODE);
+	}
+
+	si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+
+	// Integer mode indication
+	/*
+	switch(clk)
+	{
+	case SI5351_CLK0:
+		clk0_int_mode = enable;
+		break;
+	case SI5351_CLK1:
+		clk1_int_mode = enable;
+		break;
+	case SI5351_CLK2:
+		clk2_int_mode = enable;
+		break;
+	default:
+		break;
+	}
+	*/
+}
+
+/*
+ * set_clock_pwr(enum si5351_clock clk, uint8_t pwr)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * pwr - Set to 1 to enable, 0 to disable
+ *
+ * Enable or disable power to a clock output (a power
+ * saving feature).
+ */
+void Si5351::set_clock_pwr(enum si5351_clock clk, uint8_t pwr)
+{
+	uint8_t reg_val; //, reg;
+	reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+
+	if(pwr == 1)
+	{
+		reg_val &= 0b01111111;
+	}
+	else
+	{
+		reg_val |= 0b10000000;
+	}
+
+	si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+}
+
+/*
+ * set_clock_invert(enum si5351_clock clk, uint8_t inv)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * inv - Set to 1 to enable, 0 to disable
+ *
+ * Enable to invert the clock output waveform.
+ */
+void Si5351::set_clock_invert(enum si5351_clock clk, uint8_t inv)
+{
+	uint8_t reg_val;
+	reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+
+	if(inv == 1)
+	{
+		reg_val |= (SI5351_CLK_INVERT);
+	}
+	else
+	{
+		reg_val &= ~(SI5351_CLK_INVERT);
+	}
+
+	si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+}
+
+/*
+ * set_clock_source(enum si5351_clock clk, enum si5351_clock_source src)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * src - Which clock source to use for the multisynth
+ *   (use the si5351_clock_source enum)
+ *
+ * Set the clock source for a multisynth (based on the options
+ * presented for Registers 16-23 in the Silicon Labs AN619 document).
+ * Choices are XTAL, CLKIN, MS0, or the multisynth associated with
+ * the clock output.
+ */
+void Si5351::set_clock_source(enum si5351_clock clk, enum si5351_clock_source src)
+{
+	uint8_t reg_val;
+	reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk);
+
+	// Clear the bits first
+	reg_val &= ~(SI5351_CLK_INPUT_MASK);
+
+	switch(src)
+	{
+	case SI5351_CLK_SRC_XTAL:
+		reg_val |= (SI5351_CLK_INPUT_XTAL);
+		break;
+	case SI5351_CLK_SRC_CLKIN:
+		reg_val |= (SI5351_CLK_INPUT_CLKIN);
+		break;
+	case SI5351_CLK_SRC_MS0:
+		if(clk == SI5351_CLK0)
+		{
+			return;
+		}
+
+		reg_val |= (SI5351_CLK_INPUT_MULTISYNTH_0_4);
+		break;
+	case SI5351_CLK_SRC_MS:
+		reg_val |= (SI5351_CLK_INPUT_MULTISYNTH_N);
+		break;
+	default:
+		return;
+	}
+
+	si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val);
+}
+
+/*
+ * set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state)
+ *
+ * clk - Clock output
+ *   (use the si5351_clock enum)
+ * dis_state - Desired state of the output upon disable
+ *   (use the si5351_clock_disable enum)
+ *
+ * Set the state of the clock output when it is disabled. Per page 27
+ * of AN619 (Registers 24 and 25), there are four possible values: low,
+ * high, high impedance, and never disabled.
+ */
+void Si5351::set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state)
+{
+	uint8_t reg_val, reg;
+
+	if (clk >= SI5351_CLK0 && clk <= SI5351_CLK3)
+	{
+		reg = SI5351_CLK3_0_DISABLE_STATE;
+	}
+	else if(clk >= SI5351_CLK4 && clk <= SI5351_CLK7)
+	{
+		reg = SI5351_CLK7_4_DISABLE_STATE;
+	}
+	else return;
+
+	reg_val = si5351_read(reg);
+
+	if (clk >= SI5351_CLK0 && clk <= SI5351_CLK3)
+	{
+		reg_val &= ~(0b11 << (clk * 2));
+		reg_val |= dis_state << (clk * 2);
+	}
+	else if(clk >= SI5351_CLK4 && clk <= SI5351_CLK7)
+	{
+		reg_val &= ~(0b11 << ((clk - 4) * 2));
+		reg_val |= dis_state << ((clk - 4) * 2);
+	}
+
+	si5351_write(reg, reg_val);
+}
+
+/*
+ * set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable)
+ *
+ * fanout - Desired clock fanout
+ *   (use the si5351_clock_fanout enum)
+ * enable - Set to 1 to enable, 0 to disable
+ *
+ * Use this function to enable or disable the clock fanout options
+ * for individual clock outputs. If you intend to output the XO or
+ * CLKIN on the clock outputs, enable this first.
+ *
+ * By default, only the Multisynth fanout is enabled at startup.
+ */
+void Si5351::set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable)
+{
+	uint8_t reg_val;
+	reg_val = si5351_read(SI5351_FANOUT_ENABLE);
+
+	switch(fanout)
+	{
+	case SI5351_FANOUT_CLKIN:
+		if(enable)
+		{
+			reg_val |= SI5351_CLKIN_ENABLE;
+		}
+		else
+		{
+			reg_val &= ~(SI5351_CLKIN_ENABLE);
+		}
+		break;
+	case SI5351_FANOUT_XO:
+		if(enable)
+		{
+			reg_val |= SI5351_XTAL_ENABLE;
+		}
+		else
+		{
+			reg_val &= ~(SI5351_XTAL_ENABLE);
+		}
+		break;
+	case SI5351_FANOUT_MS:
+		if(enable)
+		{
+			reg_val |= SI5351_MULTISYNTH_ENABLE;
+		}
+		else
+		{
+			reg_val &= ~(SI5351_MULTISYNTH_ENABLE);
+		}
+		break;
+	}
+
+	si5351_write(SI5351_FANOUT_ENABLE, reg_val);
+}
+
+/*
+ * set_pll_input(enum si5351_pll pll, enum si5351_pll_input input)
+ *
+ * pll - Which PLL to use as the source
+ *     (use the si5351_pll enum)
+ * input - Which reference oscillator to use as PLL input
+ *     (use the si5351_pll_input enum)
+ *
+ * Set the desired reference oscillator source for the given PLL.
+ */
+void Si5351::set_pll_input(enum si5351_pll pll, enum si5351_pll_input input)
+{
+	uint8_t reg_val;
+	reg_val = si5351_read(SI5351_PLL_INPUT_SOURCE);
+
+	// Clear the bits first
+	//reg_val &= ~(SI5351_CLKIN_DIV_MASK);
+
+	switch(pll)
+	{
+	case SI5351_PLLA:
+		if(input == SI5351_PLL_INPUT_CLKIN)
+		{
+			reg_val |= SI5351_PLLA_SOURCE;
+			reg_val |= clkin_div;
+			plla_ref_osc = SI5351_PLL_INPUT_CLKIN;
+		}
+		else
+		{
+			reg_val &= ~(SI5351_PLLA_SOURCE);
+			plla_ref_osc = SI5351_PLL_INPUT_XO;
+		}
+		break;
+	case SI5351_PLLB:
+		if(input == SI5351_PLL_INPUT_CLKIN)
+		{
+			reg_val |= SI5351_PLLB_SOURCE;
+			reg_val |= clkin_div;
+			pllb_ref_osc = SI5351_PLL_INPUT_CLKIN;
+		}
+		else
+		{
+			reg_val &= ~(SI5351_PLLB_SOURCE);
+			pllb_ref_osc = SI5351_PLL_INPUT_XO;
+		}
+		break;
+	default:
+		return;
+	}
+
+	si5351_write(SI5351_PLL_INPUT_SOURCE, reg_val);
+
+	set_pll(plla_freq, SI5351_PLLA);
+	set_pll(pllb_freq, SI5351_PLLB);
+}
+
+/*
+ * set_vcxo(uint64_t pll_freq, uint8_t ppm)
+ *
+ * pll_freq - Desired PLL base frequency in Hz * 100
+ * ppm - VCXO pull limit in ppm
+ *
+ * Set the parameters for the VCXO on the Si5351B.
+ */
+void Si5351::set_vcxo(uint64_t pll_freq, uint8_t ppm)
+{
+	struct Si5351RegSet pll_reg;
+	uint64_t vcxo_param;
+
+	// Bounds check
+	if(ppm < SI5351_VCXO_PULL_MIN)
+	{
+		ppm = SI5351_VCXO_PULL_MIN;
+	}
+
+	if(ppm > SI5351_VCXO_PULL_MAX)
+	{
+		ppm = SI5351_VCXO_PULL_MAX;
+	}
+
+	// Set PLLB params
+	vcxo_param = pll_calc(SI5351_PLLB, pll_freq, &pll_reg, ref_correction[pllb_ref_osc], 1);
+
+	// Derive the register values to write
+	uint8_t params[SI5351_PARAMETERS_LENGTH];
+	uint8_t temp;
+
+	pack_reg_set(&pll_reg, params, 0);
+
+	// Write the parameters
+	si5351_write_bulk(SI5351_PLLB_PARAMETERS, SI5351_PARAMETERS_LENGTH, params);
+
+	// Write the VCXO parameters
+	vcxo_param = ((vcxo_param * ppm * SI5351_VCXO_MARGIN) / 100ULL) / 1000000ULL;
+
+	temp = (uint8_t)(vcxo_param & 0xFF);
+	si5351_write(SI5351_VXCO_PARAMETERS_LOW, temp);
+
+	temp = (uint8_t)((vcxo_param >> 8) & 0xFF);
+	si5351_write(SI5351_VXCO_PARAMETERS_MID, temp);
+
+	temp = (uint8_t)((vcxo_param >> 16) & 0x3F);
+	si5351_write(SI5351_VXCO_PARAMETERS_HIGH, temp);
+}
+
+/*
+ * set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc)
+ *
+ * ref_freq - Reference oscillator frequency in Hz
+ * ref_osc - Which reference oscillator frequency to set
+ *    (use the si5351_pll_input enum)
+ *
+ * Set the reference frequency value for the desired reference oscillator
+ */
+void Si5351::set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc)
+{
+	// uint8_t reg_val;
+	//reg_val = si5351_read(SI5351_PLL_INPUT_SOURCE);
+
+	// Clear the bits first
+	//reg_val &= ~(SI5351_CLKIN_DIV_MASK);
+
+	if(ref_freq <= 30000000UL)
+	{
+		xtal_freq[(uint8_t)ref_osc] = ref_freq;
+		//reg_val |= SI5351_CLKIN_DIV_1;
+		if(ref_osc == SI5351_PLL_INPUT_CLKIN)
+		{
+			clkin_div = SI5351_CLKIN_DIV_1;
+		}
+	}
+	else if(ref_freq > 30000000UL && ref_freq <= 60000000UL)
+	{
+		xtal_freq[(uint8_t)ref_osc] = ref_freq / 2;
+		//reg_val |= SI5351_CLKIN_DIV_2;
+		if(ref_osc == SI5351_PLL_INPUT_CLKIN)
+		{
+			clkin_div = SI5351_CLKIN_DIV_2;
+		}
+	}
+	else if(ref_freq > 60000000UL && ref_freq <= 100000000UL)
+	{
+		xtal_freq[(uint8_t)ref_osc] = ref_freq / 4;
+		//reg_val |= SI5351_CLKIN_DIV_4;
+		if(ref_osc == SI5351_PLL_INPUT_CLKIN)
+		{
+			clkin_div = SI5351_CLKIN_DIV_4;
+		}
+	}
+	else
+	{
+		//reg_val |= SI5351_CLKIN_DIV_1;
+	}
+
+	//si5351_write(SI5351_PLL_INPUT_SOURCE, reg_val);
+}
+
+uint8_t Si5351::si5351_write_bulk(uint8_t addr, uint8_t bytes, uint8_t *data)
+{
+	Wire.beginTransmission(i2c_bus_addr);
+	Wire.write(addr);
+	for(int i = 0; i < bytes; i++)
+	{
+		Wire.write(data[i]);
+	}
+	return Wire.endTransmission();
+
+}
+
+uint8_t Si5351::si5351_write(uint8_t addr, uint8_t data)
+{
+	Wire.beginTransmission(i2c_bus_addr);
+	Wire.write(addr);
+	Wire.write(data);
+	return Wire.endTransmission();
+}
+
+uint8_t Si5351::si5351_read(uint8_t addr)
+{
+	uint8_t reg_val = 0;
+
+	Wire.beginTransmission(i2c_bus_addr);
+	Wire.write(addr);
+	Wire.endTransmission();
+
+	Wire.requestFrom(i2c_bus_addr, (uint8_t)1);
+
+	while(Wire.available())
+	{
+		reg_val = Wire.read();
+	}
+
+	return reg_val;
+}
+
+/*********************/
+/* Private functions */
+/*********************/
+
+uint64_t Si5351::pll_calc(enum si5351_pll pll, uint64_t freq, struct Si5351RegSet *reg, int32_t correction, uint8_t vcxo)
+{
+	uint64_t ref_freq;
+	if(pll == SI5351_PLLA)
+	{
+		ref_freq = xtal_freq[(uint8_t)plla_ref_osc] * SI5351_FREQ_MULT;
+	}
+	else
+	{
+		ref_freq = xtal_freq[(uint8_t)pllb_ref_osc] * SI5351_FREQ_MULT;
+	}
+	//ref_freq = 15974400ULL * SI5351_FREQ_MULT;
+	uint32_t a, b, c;
+	uint64_t lltmp; //, denom;
+
+	// Factor calibration value into nominal crystal frequency
+	// Measured in parts-per-billion
+
+	ref_freq = ref_freq + (int32_t)((((((int64_t)correction) << 31) / 1000000000LL) * ref_freq) >> 31);
+
+	// PLL bounds checking
+	if (freq < SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT;
+	}
+	if (freq > SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT;
+	}
+
+	// Determine integer part of feedback equation
+	a = freq / ref_freq;
+
+	if (a < SI5351_PLL_A_MIN)
+	{
+		freq = ref_freq * SI5351_PLL_A_MIN;
+	}
+	if (a > SI5351_PLL_A_MAX)
+	{
+		freq = ref_freq * SI5351_PLL_A_MAX;
+	}
+
+	// Find best approximation for b/c = fVCO mod fIN
+	// denom = 1000ULL * 1000ULL;
+	// lltmp = freq % ref_freq;
+	// lltmp *= denom;
+	// do_div(lltmp, ref_freq);
+
+	//b = (((uint64_t)(freq % ref_freq)) * RFRAC_DENOM) / ref_freq;
+	if(vcxo)
+	{
+		b = (((uint64_t)(freq % ref_freq)) * 1000000ULL) / ref_freq;
+		c = 1000000ULL;
+	}
+	else
+	{
+		b = (((uint64_t)(freq % ref_freq)) * RFRAC_DENOM) / ref_freq;
+		c = b ? RFRAC_DENOM : 1;
+	}
+
+	// Calculate parameters
+	frac_to_reg(a, b, c, reg);
+
+	// Recalculate frequency as fIN * (a + b/c)
+	lltmp = ref_freq;
+	lltmp *= b;
+	do_div(lltmp, c);
+	freq = lltmp;
+	freq += ref_freq * a;
+
+	if(vcxo)
+	{
+		return (uint64_t)(128 * a * 1000000ULL + b);
+	}
+	else
+	{
+		return freq;
+	}
+}
+
+uint64_t Si5351::multisynth_calc(uint64_t freq, uint64_t pll_freq, struct Si5351RegSet *reg)
+{
+	uint64_t lltmp;
+	uint32_t a, b, c;
+	uint8_t divby4 = 0;
+	uint8_t ret_val = 0;
+
+	// Multisynth bounds checking
+	if (freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT;
+	}
+	if (freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT;
+	}
+
+	if (freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT)
+	{
+		divby4 = 1;
+	}
+
+	if(pll_freq == 0)
+	{
+		// Find largest integer divider for max
+		// VCO frequency and given target frequency
+		if(divby4 == 0)
+		{
+			lltmp = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT; // margin needed?
+			do_div(lltmp, freq);
+			if(lltmp == 5)
+			{
+				lltmp = 4;
+			}
+			else if(lltmp == 7)
+			{
+				lltmp = 6;
+			}
+			a = (uint32_t)lltmp;
+		}
+		else
+		{
+			a = 4;
+		}
+
+		b = 0;
+		c = 1;
+		pll_freq = a * freq;
+	}
+	else
+	{
+		// Preset PLL, so return the actual freq for these params instead of PLL freq
+		ret_val = 1;
+
+		// Determine integer part of feedback equation
+		a = pll_freq / freq;
+
+		if (a < SI5351_MULTISYNTH_A_MIN)
+		{
+			freq = pll_freq / SI5351_MULTISYNTH_A_MIN;
+		}
+		if (a > SI5351_MULTISYNTH_A_MAX)
+		{
+			freq = pll_freq / SI5351_MULTISYNTH_A_MAX;
+		}
+
+		b = (pll_freq % freq * RFRAC_DENOM) / freq;
+		c = b ? RFRAC_DENOM : 1;
+	}
+
+	// Calculate parameters
+	if (divby4 == 1)
+	{
+		reg->p1 = 0;
+		reg->p2 = 0;
+		reg->p3 = 1;
+	}
+	else
+	{
+		frac_to_reg(a, b, c, reg);
+	}
+
+	if(ret_val == 0)
+	{
+		return pll_freq;
+	}
+	else
+	{
+		return freq;
+	}
+}
+
+uint64_t Si5351::multisynth67_calc(uint64_t freq, uint64_t pll_freq, struct Si5351RegSet *reg)
+{
+	//uint8_t p1;
+	// uint8_t ret_val = 0;
+	uint32_t a;
+	uint64_t lltmp;
+
+	// Multisynth bounds checking
+	if(freq > SI5351_MULTISYNTH67_MAX_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_MULTISYNTH67_MAX_FREQ * SI5351_FREQ_MULT;
+	}
+	if(freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT)
+	{
+		freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT;
+	}
+
+	if(pll_freq == 0)
+	{
+		// Find largest integer divider for max
+		// VCO frequency and given target frequency
+		lltmp = (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT) - 100000000UL; // margin needed?
+		do_div(lltmp, freq);
+		a = (uint32_t)lltmp;
+
+		// Divisor has to be even
+		if(a % 2 != 0)
+		{
+			a++;
+		}
+
+		// Divisor bounds check
+		if(a < SI5351_MULTISYNTH_A_MIN)
+		{
+			a = SI5351_MULTISYNTH_A_MIN;
+		}
+		if(a > SI5351_MULTISYNTH67_A_MAX)
+		{
+			a = SI5351_MULTISYNTH67_A_MAX;
+		}
+
+		pll_freq = a * freq;
+
+		// PLL bounds checking
+		if(pll_freq > (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT))
+		{
+			a -= 2;
+			pll_freq = a * freq;
+		}
+		else if(pll_freq < (SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT))
+		{
+			a += 2;
+			pll_freq = a * freq;
+		}
+
+		reg->p1 = (uint8_t)a;
+		reg->p2 = 0;
+		reg->p3 = 0;
+		return pll_freq;
+	}
+	else
+	{
+		// Multisynth frequency must be integer division of PLL
+		if(pll_freq % freq)
+		{
+			// No good
+			return 0;
+		}
+		else
+		{
+			a = pll_freq / freq;
+
+			// Division ratio bounds check
+			if(a < SI5351_MULTISYNTH_A_MIN || a > SI5351_MULTISYNTH67_A_MAX)
+			{
+				// No bueno
+				return 0;
+			}
+			else
+			{
+				reg->p1 = (uint8_t)a;
+				reg->p2 = 0;
+				reg->p3 = 0;
+				return 1;
+			}
+		}
+	}
+}
+
+void Si5351::update_sys_status(struct Si5351Status *status)
+{
+  uint8_t reg_val = 0;
+
+  reg_val = si5351_read(SI5351_DEVICE_STATUS);
+
+  // Parse the register
+  status->SYS_INIT = (reg_val >> 7) & 0x01;
+  status->LOL_B = (reg_val >> 6) & 0x01;
+  status->LOL_A = (reg_val >> 5) & 0x01;
+  status->LOS = (reg_val >> 4) & 0x01;
+  status->REVID = reg_val & 0x03;
+}
+
+void Si5351::update_int_status(struct Si5351IntStatus *int_status)
+{
+  uint8_t reg_val = 0;
+
+  reg_val = si5351_read(SI5351_INTERRUPT_STATUS);
+
+  // Parse the register
+  int_status->SYS_INIT_STKY = (reg_val >> 7) & 0x01;
+  int_status->LOL_B_STKY = (reg_val >> 6) & 0x01;
+  int_status->LOL_A_STKY = (reg_val >> 5) & 0x01;
+  int_status->LOS_STKY = (reg_val >> 4) & 0x01;
+}
+
+void Si5351::ms_div(enum si5351_clock clk, uint8_t r_div, uint8_t div_by_4)
+{
+	uint8_t reg_val = 0;
+	uint8_t reg_addr = 0;
+
+	if((uint8_t)clk <= (uint8_t)SI5351_CLK5)
+	{
+		// CLK0..CLK5: parameter byte 2 is linear with clk
+		reg_addr = SI5351_CLK0_PARAMETERS + 2 + ((uint8_t)clk * 8);
+	}
+	else
+	{
+		reg_addr = SI5351_CLK6_7_OUTPUT_DIVIDER;
+	}
+
+	reg_val = si5351_read(reg_addr);
+
+	if((uint8_t)clk <= (uint8_t)SI5351_CLK5)
+	{
+		// Clear the relevant bits
+		reg_val &= ~(0x7c);
+
+		if(div_by_4 == 0)
+		{
+			reg_val &= ~(SI5351_OUTPUT_CLK_DIVBY4);
+		}
+		else
+		{
+			reg_val |= (SI5351_OUTPUT_CLK_DIVBY4);
+		}
+
+		reg_val |= (r_div << SI5351_OUTPUT_CLK_DIV_SHIFT);
+	}
+	else if(clk == SI5351_CLK6)
+	{
+		// Clear the relevant bits
+		reg_val &= ~(0x07);
+
+		reg_val |= r_div;
+	}
+	else if(clk == SI5351_CLK7)
+	{
+		// Clear the relevant bits
+		reg_val &= ~(0x70);
+
+		reg_val |= (r_div << SI5351_OUTPUT_CLK_DIV_SHIFT);
+	}
+
+	si5351_write(reg_addr, reg_val);
+}
+
+uint8_t Si5351::select_r_div(uint64_t *freq, uint32_t min_freq)
+{
+	/* Unified R-divider selection for CLK0-5 (min_freq = CLKOUT_MIN_FREQ)
+	 * and CLK6-7 (min_freq = CLKOUT67_MIN_FREQ). Same band thresholds as
+	 * the former select_r_div / select_r_div_ms67 pair.
+	 * SI5351_OUTPUT_CLK_DIV_n enum values equal log2(n). */
+	uint64_t lower = (uint64_t)min_freq * SI5351_FREQ_MULT;
+	int8_t shift;
+
+	for(shift = 7; shift >= 1; shift--)
+	{
+		uint64_t upper = lower << 1;
+		if((*freq >= lower) && (*freq < upper))
+		{
+			*freq *= (1ULL << shift);
+			return (uint8_t)shift;
+		}
+		lower = upper;
+	}
+
+	return SI5351_OUTPUT_CLK_DIV_1;
+}
diff --git a/tests/regression/reference/master_1ddd43e/si5351.h b/tests/regression/reference/master_1ddd43e/si5351.h
new file mode 100644
index 0000000..132a522
--- /dev/null
+++ b/tests/regression/reference/master_1ddd43e/si5351.h
@@ -0,0 +1,334 @@
+/*
+ * si5351.h - Si5351 library for Arduino
+ *
+ * Copyright (C) 2015 - 2019 Jason Milldrum <milldrum@gmail.com>
+ *                           Dana H. Myers <k6jq@comcast.net>
+ *
+ * Many defines derived from clk-si5351.h in the Linux kernel.
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * do_div() macro derived from /include/asm-generic/div64.h in
+ * the Linux kernel.
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SI5351_H_
+#define SI5351_H_
+
+#include "Arduino.h"
+#include "Wire.h"
+#include <stdint.h>
+
+/* Define definitions */
+
+#define SI5351_BUS_BASE_ADDR            0x60
+#define SI5351_XTAL_FREQ                25000000
+#define SI5351_PLL_FIXED                80000000000ULL
+#define SI5351_FREQ_MULT                100ULL
+#define SI5351_DEFAULT_CLK              1000000000ULL
+
+#define SI5351_PLL_VCO_MIN              600000000
+#define SI5351_PLL_VCO_MAX              900000000
+#define SI5351_MULTISYNTH_MIN_FREQ      500000
+#define SI5351_MULTISYNTH_DIVBY4_FREQ   150000000
+#define SI5351_MULTISYNTH_MAX_FREQ      225000000
+#define SI5351_MULTISYNTH_SHARE_MAX     100000000
+#define SI5351_MULTISYNTH_SHARE_MIN     1024000
+#define SI5351_MULTISYNTH67_MAX_FREQ    SI5351_MULTISYNTH_DIVBY4_FREQ
+#define SI5351_CLKOUT_MIN_FREQ          4000
+#define SI5351_CLKOUT_MAX_FREQ          SI5351_MULTISYNTH_MAX_FREQ
+#define SI5351_CLKOUT67_MS_MIN          SI5351_PLL_VCO_MIN / SI5351_MULTISYNTH67_A_MAX
+#define SI5351_CLKOUT67_MIN_FREQ        SI5351_CLKOUT67_MS_MIN / 128
+#define SI5351_CLKOUT67_MAX_FREQ        SI5351_MULTISYNTH67_MAX_FREQ
+
+#define SI5351_PLL_A_MIN                15
+#define SI5351_PLL_A_MAX                90
+#define SI5351_PLL_B_MAX                (SI5351_PLL_C_MAX-1)
+#define SI5351_PLL_C_MAX                1048575
+#define SI5351_MULTISYNTH_A_MIN         6
+#define SI5351_MULTISYNTH_A_MAX         1800
+#define SI5351_MULTISYNTH67_A_MAX       254
+#define SI5351_MULTISYNTH_B_MAX         (SI5351_MULTISYNTH_C_MAX-1)
+#define SI5351_MULTISYNTH_C_MAX         1048575
+#define SI5351_MULTISYNTH_P1_MAX        ((1<<18)-1)
+#define SI5351_MULTISYNTH_P2_MAX        ((1<<20)-1)
+#define SI5351_MULTISYNTH_P3_MAX        ((1<<20)-1)
+#define SI5351_VCXO_PULL_MIN            30
+#define SI5351_VCXO_PULL_MAX            240
+#define SI5351_VCXO_MARGIN              103
+
+#define SI5351_DEVICE_STATUS            0
+#define SI5351_INTERRUPT_STATUS         1
+#define SI5351_INTERRUPT_MASK           2
+#define SI5351_STATUS_SYS_INIT          (1<<7)
+#define SI5351_STATUS_LOL_B             (1<<6)
+#define SI5351_STATUS_LOL_A             (1<<5)
+#define SI5351_STATUS_LOS               (1<<4)
+#define SI5351_OUTPUT_ENABLE_CTRL       3
+#define SI5351_OEB_PIN_ENABLE_CTRL      9
+#define SI5351_PLL_INPUT_SOURCE         15
+#define SI5351_CLKIN_DIV_MASK           (3<<6)
+#define SI5351_CLKIN_DIV_1              (0<<6)
+#define SI5351_CLKIN_DIV_2              (1<<6)
+#define SI5351_CLKIN_DIV_4              (2<<6)
+#define SI5351_CLKIN_DIV_8              (3<<6)
+#define SI5351_PLLB_SOURCE              (1<<3)
+#define SI5351_PLLA_SOURCE              (1<<2)
+
+#define SI5351_CLK0_CTRL                16
+#define SI5351_CLK1_CTRL                17
+#define SI5351_CLK2_CTRL                18
+#define SI5351_CLK3_CTRL                19
+#define SI5351_CLK4_CTRL                20
+#define SI5351_CLK5_CTRL                21
+#define SI5351_CLK6_CTRL                22
+#define SI5351_CLK7_CTRL                23
+#define SI5351_CLK_POWERDOWN            (1<<7)
+#define SI5351_CLK_INTEGER_MODE         (1<<6)
+#define SI5351_CLK_PLL_SELECT           (1<<5)
+#define SI5351_CLK_INVERT               (1<<4)
+#define SI5351_CLK_INPUT_MASK           (3<<2)
+#define SI5351_CLK_INPUT_XTAL           (0<<2)
+#define SI5351_CLK_INPUT_CLKIN          (1<<2)
+#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
+#define SI5351_CLK_INPUT_MULTISYNTH_N   (3<<2)
+#define SI5351_CLK_DRIVE_STRENGTH_MASK  (3<<0)
+#define SI5351_CLK_DRIVE_STRENGTH_2MA   (0<<0)
+#define SI5351_CLK_DRIVE_STRENGTH_4MA   (1<<0)
+#define SI5351_CLK_DRIVE_STRENGTH_6MA   (2<<0)
+#define SI5351_CLK_DRIVE_STRENGTH_8MA   (3<<0)
+
+#define SI5351_CLK3_0_DISABLE_STATE     24
+#define SI5351_CLK7_4_DISABLE_STATE     25
+#define SI5351_CLK_DISABLE_STATE_MASK   3
+#define SI5351_CLK_DISABLE_STATE_LOW    0
+#define SI5351_CLK_DISABLE_STATE_HIGH   1
+#define SI5351_CLK_DISABLE_STATE_FLOAT  2
+#define SI5351_CLK_DISABLE_STATE_NEVER  3
+
+#define SI5351_PARAMETERS_LENGTH        8
+#define SI5351_PLLA_PARAMETERS          26
+#define SI5351_PLLB_PARAMETERS          34
+#define SI5351_CLK0_PARAMETERS          42
+#define SI5351_CLK1_PARAMETERS          50
+#define SI5351_CLK2_PARAMETERS          58
+#define SI5351_CLK3_PARAMETERS          66
+#define SI5351_CLK4_PARAMETERS          74
+#define SI5351_CLK5_PARAMETERS          82
+#define SI5351_CLK6_PARAMETERS          90
+#define SI5351_CLK7_PARAMETERS          91
+#define SI5351_CLK6_7_OUTPUT_DIVIDER    92
+#define SI5351_OUTPUT_CLK_DIV_MASK      (7 << 4)
+#define SI5351_OUTPUT_CLK6_DIV_MASK     (7 << 0)
+#define SI5351_OUTPUT_CLK_DIV_SHIFT     4
+#define SI5351_OUTPUT_CLK_DIV6_SHIFT    0
+#define SI5351_OUTPUT_CLK_DIV_1         0
+#define SI5351_OUTPUT_CLK_DIV_2         1
+#define SI5351_OUTPUT_CLK_DIV_4         2
+#define SI5351_OUTPUT_CLK_DIV_8         3
+#define SI5351_OUTPUT_CLK_DIV_16        4
+#define SI5351_OUTPUT_CLK_DIV_32        5
+#define SI5351_OUTPUT_CLK_DIV_64        6
+#define SI5351_OUTPUT_CLK_DIV_128       7
+#define SI5351_OUTPUT_CLK_DIVBY4       (3<<2)
+
+#define SI5351_SSC_PARAM0               149
+#define SI5351_SSC_PARAM1               150
+#define SI5351_SSC_PARAM2               151
+#define SI5351_SSC_PARAM3               152
+#define SI5351_SSC_PARAM4               153
+#define SI5351_SSC_PARAM5               154
+#define SI5351_SSC_PARAM6               155
+#define SI5351_SSC_PARAM7               156
+#define SI5351_SSC_PARAM8               157
+#define SI5351_SSC_PARAM9               158
+#define SI5351_SSC_PARAM10              159
+#define SI5351_SSC_PARAM11              160
+#define SI5351_SSC_PARAM12              161
+
+#define SI5351_VXCO_PARAMETERS_LOW      162
+#define SI5351_VXCO_PARAMETERS_MID      163
+#define SI5351_VXCO_PARAMETERS_HIGH     164
+
+#define SI5351_CLK0_PHASE_OFFSET        165
+#define SI5351_CLK1_PHASE_OFFSET        166
+#define SI5351_CLK2_PHASE_OFFSET        167
+#define SI5351_CLK3_PHASE_OFFSET        168
+#define SI5351_CLK4_PHASE_OFFSET        169
+#define SI5351_CLK5_PHASE_OFFSET        170
+
+#define SI5351_PLL_RESET                177
+#define SI5351_PLL_RESET_B              (1<<7)
+#define SI5351_PLL_RESET_A              (1<<5)
+
+#define SI5351_CRYSTAL_LOAD             183
+#define SI5351_CRYSTAL_LOAD_MASK        (3<<6)
+#define SI5351_CRYSTAL_LOAD_0PF         (0<<6)
+#define SI5351_CRYSTAL_LOAD_6PF         (1<<6)
+#define SI5351_CRYSTAL_LOAD_8PF         (2<<6)
+#define SI5351_CRYSTAL_LOAD_10PF        (3<<6)
+
+#define SI5351_FANOUT_ENABLE            187
+#define SI5351_CLKIN_ENABLE             (1<<7)
+#define SI5351_XTAL_ENABLE              (1<<6)
+#define SI5351_MULTISYNTH_ENABLE        (1<<4)
+
+
+/* Macro definitions */
+
+//#define RFRAC_DENOM ((1L << 20) - 1)
+#define RFRAC_DENOM 1000000ULL
+
+/*
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *      uint32_t remainder = *n % base;
+ *      *n = *n / base;
+ *      return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+# define do_div(n,base) ({                                      \
+        uint64_t __base = (base);                               \
+        uint64_t __rem;                                         \
+        __rem = ((uint64_t)(n)) % __base;                       \
+        (n) = ((uint64_t)(n)) / __base;                         \
+        __rem;                                                  \
+ })
+
+/* Enum definitions */
+
+/*
+ * enum si5351_variant - SiLabs Si5351 chip variant
+ * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
+ * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
+ * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
+ * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
+ */
+/*
+enum si5351_variant {
+	SI5351_VARIANT_A = 1,
+	SI5351_VARIANT_A3 = 2,
+	SI5351_VARIANT_B = 3,
+	SI5351_VARIANT_C = 4,
+};
+*/
+
+enum si5351_clock {SI5351_CLK0, SI5351_CLK1, SI5351_CLK2, SI5351_CLK3,
+	SI5351_CLK4, SI5351_CLK5, SI5351_CLK6, SI5351_CLK7};
+
+enum si5351_pll {SI5351_PLLA, SI5351_PLLB};
+
+enum si5351_drive {SI5351_DRIVE_2MA, SI5351_DRIVE_4MA, SI5351_DRIVE_6MA, SI5351_DRIVE_8MA};
+
+enum si5351_clock_source {SI5351_CLK_SRC_XTAL, SI5351_CLK_SRC_CLKIN, SI5351_CLK_SRC_MS0, SI5351_CLK_SRC_MS};
+
+enum si5351_clock_disable {SI5351_CLK_DISABLE_LOW, SI5351_CLK_DISABLE_HIGH, SI5351_CLK_DISABLE_HI_Z, SI5351_CLK_DISABLE_NEVER};
+
+enum si5351_clock_fanout {SI5351_FANOUT_CLKIN, SI5351_FANOUT_XO, SI5351_FANOUT_MS};
+
+enum si5351_pll_input {SI5351_PLL_INPUT_XO, SI5351_PLL_INPUT_CLKIN};
+
+/* Struct definitions */
+
+struct Si5351RegSet
+{
+	uint32_t p1;
+	uint32_t p2;
+	uint32_t p3;
+};
+
+struct Si5351Status
+{
+	uint8_t SYS_INIT;
+	uint8_t LOL_B;
+	uint8_t LOL_A;
+	uint8_t LOS;
+	uint8_t REVID;
+};
+
+struct Si5351IntStatus
+{
+	uint8_t SYS_INIT_STKY;
+	uint8_t LOL_B_STKY;
+	uint8_t LOL_A_STKY;
+	uint8_t LOS_STKY;
+};
+
+class Si5351
+{
+public:
+  Si5351(uint8_t i2c_addr = SI5351_BUS_BASE_ADDR);
+	bool init(uint8_t, uint32_t, int32_t);
+	void reset(void);
+	uint8_t set_freq(uint64_t, enum si5351_clock);
+	uint8_t set_freq_manual(uint64_t, uint64_t, enum si5351_clock);
+	void set_pll(uint64_t, enum si5351_pll);
+	void set_ms(enum si5351_clock, struct Si5351RegSet, uint8_t, uint8_t, uint8_t);
+	void output_enable(enum si5351_clock, uint8_t);
+	void drive_strength(enum si5351_clock, enum si5351_drive);
+	void update_status(void);
+	void set_correction(int32_t, enum si5351_pll_input);
+	void set_phase(enum si5351_clock, uint8_t);
+	int32_t get_correction(enum si5351_pll_input);
+	void pll_reset(enum si5351_pll);
+	void set_ms_source(enum si5351_clock, enum si5351_pll);
+	void set_int(enum si5351_clock, uint8_t);
+	void set_clock_pwr(enum si5351_clock, uint8_t);
+	void set_clock_invert(enum si5351_clock, uint8_t);
+	void set_clock_source(enum si5351_clock, enum si5351_clock_source);
+	void set_clock_disable(enum si5351_clock, enum si5351_clock_disable);
+	void set_clock_fanout(enum si5351_clock_fanout, uint8_t);
+	void set_pll_input(enum si5351_pll, enum si5351_pll_input);
+	void set_vcxo(uint64_t, uint8_t);
+  void set_ref_freq(uint32_t, enum si5351_pll_input);
+	uint8_t si5351_write_bulk(uint8_t, uint8_t, uint8_t *);
+	uint8_t si5351_write(uint8_t, uint8_t);
+	uint8_t si5351_read(uint8_t);
+	struct Si5351Status dev_status = {.SYS_INIT = 0, .LOL_B = 0, .LOL_A = 0,
+    .LOS = 0, .REVID = 0};
+	struct Si5351IntStatus dev_int_status = {.SYS_INIT_STKY = 0, .LOL_B_STKY = 0,
+    .LOL_A_STKY = 0, .LOS_STKY = 0};
+	enum si5351_pll pll_assignment[8];
+	uint64_t clk_freq[8];
+	uint64_t plla_freq;
+	uint64_t pllb_freq;
+  enum si5351_pll_input plla_ref_osc;
+  enum si5351_pll_input pllb_ref_osc;
+	uint32_t xtal_freq[2];
+private:
+	uint64_t pll_calc(enum si5351_pll, uint64_t, struct Si5351RegSet *, int32_t, uint8_t);
+	uint64_t multisynth_calc(uint64_t, uint64_t, struct Si5351RegSet *);
+	uint64_t multisynth67_calc(uint64_t, uint64_t, struct Si5351RegSet *);
+	void update_sys_status(struct Si5351Status *);
+	void update_int_status(struct Si5351IntStatus *);
+	void ms_div(enum si5351_clock, uint8_t, uint8_t);
+	uint8_t select_r_div(uint64_t *, uint32_t);
+	int32_t ref_correction[2];
+  uint8_t clkin_div;
+  uint8_t i2c_bus_addr;
+  bool clk_first_set[8];
+};
+
+#endif /* SI5351_H_ */
diff --git a/tests/regression/run_v231_checks.sh b/tests/regression/run_v231_checks.sh
new file mode 100755
index 0000000..0c66300
--- /dev/null
+++ b/tests/regression/run_v231_checks.sh
@@ -0,0 +1,231 @@
+#!/usr/bin/env bash
+# run_v231_checks.sh - repeatable Si5351Arduino v2.3.1 acceptance + regression checks.
+# Self-contained: everything it needs is vendored next to this script. See README.md.
+set -euo pipefail
+
+CI_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+REPO_URL="https://github.com/etherkit/Si5351Arduino.git"
+SRC=""            # path to a source tree / clone (optional)
+REF=""            # git ref or SHA (optional; default: master of REPO_URL, or HEAD of --src clone)
+OUT=""
+CORES=""          # "" = no board compiles; "all" or comma list of board keys
+REQUIRE_FIXED=0
+INSTALL_CORES=1
+ARDUINO_CLI="${ARDUINO_CLI:-}"
+CXX="${CXX:-g++}"
+PY="${PYTHON:-python3}"
+
+usage() { cat <<'U'
+Usage: run_v231_checks.sh [options]
+  --src PATH         library source: a git clone or a plain source tree (must contain src/si5351.cpp)
+  --ref REF          git ref/branch/tag/SHA. With --src: archived from that clone. Without --src:
+                     fetched read-only from --repo. Default: master HEAD of --repo.
+  --repo URL         upstream repo (default https://github.com/etherkit/Si5351Arduino.git)
+  --out DIR          output dir (default ./runs/<timestamp>_<sha7>)
+  --require-fixed    the 25 v2.3.1 acceptance tests MUST pass (default: failures are expected-fail)
+  --cores [LIST]     also arduino-cli compile on boards: "all" (default when no list) or comma list
+                     of keys from boards.txt (uno,mega,nano_every,esp32,esp8266,bluepill,nano33ble,zero,pico)
+  --no-install       do not install missing arduino cores (missing core => FAIL)
+  --arduino-cli PATH arduino-cli binary (default: $ARDUINO_CLI, ~/bin/arduino-cli, or PATH)
+  -h, --help
+Exit: 0 when every check is PASS/XFAIL/SKIP, 1 on any unexpected failure, 2 on usage/setup error.
+U
+}
+
+while [[ $# -gt 0 ]]; do
+  case "$1" in
+    --src) SRC="$2"; shift 2;;
+    --ref) REF="$2"; shift 2;;
+    --repo) REPO_URL="$2"; shift 2;;
+    --out) OUT="$2"; shift 2;;
+    --require-fixed) REQUIRE_FIXED=1; shift;;
+    --cores) if [[ $# -gt 1 && "$2" != --* ]]; then CORES="$2"; shift 2; else CORES="all"; shift; fi;;
+    --no-install) INSTALL_CORES=0; shift;;
+    --arduino-cli) ARDUINO_CLI="$2"; shift 2;;
+    -h|--help) usage; exit 0;;
+    *) echo "unknown option: $1" >&2; usage >&2; exit 2;;
+  esac
+done
+
+for t in git "$CXX" "$PY" tar; do command -v "$t" >/dev/null || { echo "missing required tool: $t" >&2; exit 2; }; done
+
+STARTED="$(date -u +%Y-%m-%dT%H:%M:%SZ)"
+TMPOUT="${OUT:-$CI_DIR/runs/run_$(date +%Y%m%d_%H%M%S)_$$}"
+mkdir -p "$TMPOUT"; OUT="$(cd "$TMPOUT" && pwd)"
+LOGS="$OUT/logs"; LIB="$OUT/lib"; BUILD="$OUT/build"
+mkdir -p "$LOGS" "$BUILD"
+RESULTS="$OUT/results.tsv"; : > "$RESULTS"
+echo "== run_v231_checks: output in $OUT"
+
+# record NAME STATUS DETAIL LOG   (STATUS: PASS FAIL XFAIL SKIP INFO)
+record() { printf '%s\t%s\t%s\t%s\n' "$1" "$2" "${3//$'\t'/ }" "${4:-}" >> "$RESULTS"; printf '  %-34s %-5s %s\n' "$1" "$2" "$3"; }
+
+# ---------------------------------------------------------------- 1. pin the library source
+SRC_KIND=""; SHA="unknown"; DIRTY="n/a"; DESC=""
+rm -rf "$LIB"; mkdir -p "$LIB"
+if [[ -z "$SRC" ]]; then
+  SRC_KIND="fetched"; R="${REF:-master}"
+  W="$OUT/work/repo"; rm -rf "$W"; mkdir -p "$W"
+  git -C "$W" init -q
+  git -C "$W" remote add origin "$REPO_URL"
+  git -C "$W" -c protocol.version=2 fetch -q --depth 1 origin "$R" > "$LOGS/git_fetch.log" 2>&1 \
+    || { cat "$LOGS/git_fetch.log" >&2; echo "fetch of '$R' from $REPO_URL failed" >&2; exit 2; }
+  SHA="$(git -C "$W" rev-parse FETCH_HEAD)"; DESC="$REPO_URL $R"
+  git -C "$W" archive "$SHA" | tar -x -C "$LIB"
+elif [[ -d "$SRC/.git" ]] || git -C "$SRC" rev-parse --git-dir >/dev/null 2>&1; then
+  SRC_KIND="git-clone"; R="${REF:-HEAD}"
+  SHA="$(git -C "$SRC" rev-parse --verify "$R^{commit}")"; DESC="$(cd "$SRC" && pwd) $R"
+  if [[ -z "$REF" && -n "$(git -C "$SRC" status --porcelain -- src 2>/dev/null)" ]]; then DIRTY="yes (uncommitted src/ changes ignored: tested $SHA as committed)"; else DIRTY="no"; fi
+  git -C "$SRC" archive "$SHA" | tar -x -C "$LIB"      # pinned: unaffected by later edits to the clone
+elif [[ -f "$SRC/src/si5351.cpp" || -f "$SRC/si5351.cpp" ]]; then
+  SRC_KIND="tree"; DESC="$(cd "$SRC" && pwd)"
+  [[ -n "$REF" ]] && { echo "--ref needs a git clone; $SRC is a plain tree" >&2; exit 2; }
+  if [[ -f "$SRC/src/si5351.cpp" ]]; then (cd "$SRC" && tar --exclude=.git -cf - .) | tar -x -C "$LIB"
+  else mkdir -p "$LIB/src"; cp "$SRC"/si5351.{cpp,h} "$LIB/src/"; fi
+  SHA="tree-sha256:$(cat "$LIB/src/si5351.cpp" "$LIB/src/si5351.h" | sha256sum | cut -c1-16)"
+else
+  echo "--src $SRC: neither a git clone nor a tree containing src/si5351.cpp" >&2; exit 2
+fi
+[[ -f "$LIB/src/si5351.cpp" && -f "$LIB/src/si5351.h" ]] || { echo "pinned tree lacks src/si5351.{cpp,h}" >&2; exit 2; }
+( cd "$LIB" && sha256sum src/si5351.cpp src/si5351.h ) > "$OUT/PINNED_SHA256SUMS"
+echo "$SHA" > "$OUT/PINNED_SHA"
+LIBVER="$(sed -n 's/^version=//p' "$LIB/library.properties" 2>/dev/null || true)"
+HAS_TWOWIRE=0; grep -q 'TwoWire *\*' "$LIB/src/si5351.h" && HAS_TWOWIRE=1
+echo "   source: $SRC_KIND $DESC -> $SHA (library.properties version ${LIBVER:-?}, TwoWire ctor: $HAS_TWOWIRE)"
+cat > "$OUT/meta.env" <<M
+SHA=$SHA
+SRC_KIND=$SRC_KIND
+SRC_DESC=$DESC
+DIRTY=$DIRTY
+LIBVER=$LIBVER
+HAS_TWOWIRE=$HAS_TWOWIRE
+REQUIRE_FIXED=$REQUIRE_FIXED
+CORES=$CORES
+STARTED=$STARTED
+HOST=$(hostname)
+OS=$(uname -srm)
+CXX_VERSION=$($CXX --version | head -1)
+PY_VERSION=$($PY --version 2>&1)
+M
+
+CXXFLAGS="-std=gnu++17 -O1 -g -Wall -Wno-unused-variable -Wno-unused-result"
+# pattern-init makes reads of uninitialised locals deterministic (needs gcc>=12 / clang>=8); drop if unsupported
+echo 'int main(){return 0;}' > "$BUILD/probe.cpp"
+if $CXX -ftrivial-auto-var-init=pattern "$BUILD/probe.cpp" -o "$BUILD/probe" 2>/dev/null; then CXXFLAGS="$CXXFLAGS -ftrivial-auto-var-init=pattern"
+else echo "   note: $CXX lacks -ftrivial-auto-var-init=pattern; equivalence transcripts may differ on uninitialised paths"; fi
+
+# ---------------------------------------------------------------- 2. v2.3.1 acceptance + must-not-break
+echo "== host checks"
+ACC="$BUILD/acc"; ACCJ="$LOGS/acc.jsonl"
+if $CXX $CXXFLAGS -I"$CI_DIR/v231" -I"$CI_DIR/stubs" -I"$LIB/src" "$CI_DIR/v231/acceptance.cpp" "$CI_DIR/stubs/Wire.cpp" "$LIB/src/si5351.cpp" -o "$ACC" > "$LOGS/build_acceptance.log" 2>&1; then
+  record build_acceptance PASS "acceptance runner built against pinned source" logs/build_acceptance.log
+  if "$ACC" "$ACCJ" > "$LOGS/run_acceptance.log" 2>&1; then
+    record run_acceptance PASS "$(wc -l < "$ACCJ") JSONL runs" logs/run_acceptance.log
+    MODE=""; [[ $REQUIRE_FIXED == 1 ]] && MODE="--require-fixed"
+    set +e; $PY "$CI_DIR/v231/test_v231.py" "$ACCJ" $MODE > "$LOGS/test_v231.log" 2>&1; TRC=$?; set -e
+    while read -r st id rest; do
+      if [[ $st == PASS ]]; then record "acceptance_$id" PASS "$rest" logs/test_v231.log
+      elif [[ $REQUIRE_FIXED == 1 ]]; then record "acceptance_$id" FAIL "$rest" logs/test_v231.log
+      else record "acceptance_$id" XFAIL "$rest (expected to fail until v2.3.1)" logs/test_v231.log; fi
+    done < <(grep -E '^(PASS|FAIL) A[0-9]+ ' "$LOGS/test_v231.log")
+    NACC=$(grep -cE '^(PASS|FAIL) A[0-9]+ ' "$LOGS/test_v231.log" || true)
+    [[ $NACC == 25 ]] || record acceptance_count FAIL "expected 25 acceptance results, parsed $NACC" logs/test_v231.log
+    MNB="$(grep -E '^== MUST-NOT-BREAK' "$LOGS/test_v231.log" || true)"
+    if [[ $MNB =~ ([0-9]+)\ checks,\ ([0-9]+)\ failures ]] && [[ ${BASH_REMATCH[2]} == 0 ]]; then
+      record must_not_break PASS "${BASH_REMATCH[1]} checks, 0 failures" logs/test_v231.log
+    else record must_not_break FAIL "${MNB:-no MUST-NOT-BREAK summary} (test_v231 rc=$TRC)" logs/test_v231.log; fi
+  else record run_acceptance FAIL "runner crashed (rc=$?)" logs/run_acceptance.log; fi
+else record build_acceptance FAIL "compile error" logs/build_acceptance.log; fi
+
+# ---------------------------------------------------------------- 3. issue #106 TwoWire test
+if [[ $HAS_TWOWIRE == 1 ]]; then
+  if $CXX -std=gnu++17 -Dprivate=public -I"$CI_DIR/issue106/stubs" -I"$LIB/src" "$CI_DIR/issue106/t106.cpp" "$LIB/src/si5351.cpp" -o "$BUILD/t106" > "$LOGS/build_t106.log" 2>&1; then
+    if "$BUILD/t106" > "$LOGS/t106.log" 2>&1 && grep -q '^ALL PASS' "$LOGS/t106.log"; then
+      record t106_twowire PASS "$(grep -c '^PASS' "$LOGS/t106.log") checks, $(tail -1 "$LOGS/t106.log")" logs/t106.log
+    else record t106_twowire FAIL "$(grep -c '^FAIL' "$LOGS/t106.log" || true) failing checks" logs/t106.log; fi
+  else record t106_twowire FAIL "compile error" logs/build_t106.log; fi
+else record t106_twowire SKIP "source has no TwoWire* constructor (pre-#106)"; fi
+
+# ---------------------------------------------------------------- 4. goldens + equivalence vs master 1ddd43e (C++ harness)
+EQ="$CI_DIR/equiv"
+if $CXX $CXXFLAGS -I"$EQ" -I"$CI_DIR/stubs" -I"$LIB/src" "$EQ/harness.cpp" "$CI_DIR/stubs/Wire.cpp" "$LIB/src/si5351.cpp" -o "$BUILD/h_lib" > "$LOGS/build_harness_lib.log" 2>&1 \
+ && $CXX $CXXFLAGS -I"$EQ" -I"$CI_DIR/stubs" -I"$CI_DIR/reference/master_1ddd43e" "$EQ/harness.cpp" "$CI_DIR/stubs/Wire.cpp" "$CI_DIR/reference/master_1ddd43e/si5351.cpp" -o "$BUILD/h_ref" > "$LOGS/build_harness_ref.log" 2>&1; then
+  "$BUILD/h_lib" "$LOGS/harness_lib.jsonl" 2> "$LOGS/run_harness_lib.log" || record run_harness_lib FAIL "harness crashed" logs/run_harness_lib.log
+  "$BUILD/h_ref" "$LOGS/harness_master1ddd43e.jsonl" 2> "$LOGS/run_harness_ref.log" || record run_harness_ref FAIL "harness crashed" logs/run_harness_ref.log
+  set +e; $PY "$EQ/compare.py" "$LOGS/harness_lib.jsonl" "$LOGS/harness_master1ddd43e.jsonl" "$LOGS/equiv_report.txt" > "$LOGS/compare.log" 2>&1; set -e
+  G="$(grep -E '^Goldens vs ORIGINAL C\+\+' "$LOGS/equiv_report.txt" || true)"
+  if [[ $G =~ ([0-9]+)\ field\ checks,\ ([0-9]+)\ mismatches ]]; then
+    if [[ ${BASH_REMATCH[2]} == 0 ]]; then record goldens27_vs_lib PASS "27 golden cases, ${BASH_REMATCH[1]} field checks, 0 mismatches" logs/equiv_report.txt
+    elif [[ $REQUIRE_FIXED == 1 ]]; then record goldens27_vs_lib INFO "${BASH_REMATCH[2]} golden mismatches (goldens lock v2.2.0/2.3.0 behaviour; fixes may change some, review the list)" logs/equiv_report.txt
+    else record goldens27_vs_lib FAIL "${BASH_REMATCH[2]} mismatches of ${BASH_REMATCH[1]} field checks" logs/equiv_report.txt; fi
+  else record goldens27_vs_lib FAIL "compare.py produced no golden summary" logs/compare.log; fi
+  EQL="$(grep -E '^Equivalence:' "$LOGS/equiv_report.txt" || true)"
+  if [[ $EQL =~ differing\ runs:\ ([0-9]+) ]]; then
+    record equiv_vs_master_1ddd43e INFO "${BASH_REMATCH[1]} differing runs vs master 1ddd43e (0 = behaviourally identical; fixes are expected to differ)" logs/equiv_report.txt
+  else record equiv_vs_master_1ddd43e FAIL "no equivalence summary" logs/compare.log; fi
+  NB="$(grep -E '^Bonus' "$LOGS/equiv_report.txt" || true)"; [[ -n $NB ]] && record goldens_newer_vs_lib INFO "${NB#Bonus - }" logs/equiv_report.txt
+else record harness_build FAIL "compile error (see build_harness_*.log)" logs/build_harness_lib.log; fi
+
+# ---------------------------------------------------------------- 5. Python golden/spec suites (oracle self-consistency)
+for t in test_golden test_spec; do
+  if (cd "$CI_DIR/python" && $PY "$t.py") > "$LOGS/py_$t.log" 2>&1; then record "py_$t" PASS "$(grep -vE '^\s*$' "$LOGS/py_$t.log" | tail -1)" "logs/py_$t.log"
+  else record "py_$t" FAIL "rc!=0" "logs/py_$t.log"; fi
+done
+
+# ---------------------------------------------------------------- 6. C++98 compatibility (informational)
+if $CXX -std=c++98 -pedantic -fsyntax-only -I"$CI_DIR/stubs" -I"$LIB/src" "$LIB/src/si5351.cpp" > "$LOGS/cxx98.log" 2>&1; then
+  record cxx98_syntax INFO "builds with -std=c++98 -pedantic; $(grep -c 'warning:' "$LOGS/cxx98.log" || true) pedantic warnings (master 1ddd43e: 73)" logs/cxx98.log
+else record cxx98_syntax INFO "does NOT build with -std=c++98 (informational)" logs/cxx98.log; fi
+
+# ---------------------------------------------------------------- 7. optional arduino-cli board compiles
+if [[ -n $CORES ]]; then
+  echo "== board compiles ($CORES)"
+  if [[ -z $ARDUINO_CLI ]]; then
+    if [[ -x "$HOME/bin/arduino-cli" ]]; then ARDUINO_CLI="$HOME/bin/arduino-cli"; else ARDUINO_CLI="$(command -v arduino-cli || true)"; fi
+  fi
+  if [[ -z $ARDUINO_CLI || ! -x $ARDUINO_CLI ]]; then
+    record arduino_cli FAIL "arduino-cli not found (install to ~/bin, see README)"
+  else
+    # Version-manager shims (mise/asdf/pyenv) on PATH can break the python3 that some cores (esp8266) call
+    # during the build; give arduino-cli a PATH without them when a real python3 is still reachable.
+    AC_PATH="$(printf '%s' "$PATH" | tr ':' '\n' | grep -vE '/(mise|asdf|\.pyenv)/shims' | paste -sd: -)"
+    if PATH="$AC_PATH" command -v python3 >/dev/null 2>&1 && [[ "$AC_PATH" != "$PATH" ]]; then
+      echo "   note: running arduino-cli with version-manager shims removed from PATH"; ACENV=(env "PATH=$AC_PATH")
+    else ACENV=(env); fi
+    AC="$ARDUINO_CLI"; echo "ARDUINO_CLI=$AC ($($AC version 2>&1 | head -1))" >> "$OUT/meta.env"
+    URLS="$(grep -E '^url\|' "$CI_DIR/boards.txt" | cut -d'|' -f2 | paste -sd, -)"
+    $AC core update-index --additional-urls "$URLS" > "$LOGS/core_update_index.log" 2>&1 || true
+    $AC core list --additional-urls "$URLS" > "$LOGS/core_list_before.log" 2>&1 || true
+    SK="$OUT/sketches"; rm -rf "$SK"; mkdir -p "$SK"
+    cp -r "$LIB/examples/si5351_example" "$LIB/examples/si5351_vcxo" "$SK/" 2>/dev/null || true
+    # Ctor106 is stored as .ino.txt so arduino-lint does not flag a sketch outside examples/
+    [[ $HAS_TWOWIRE == 1 ]] && { mkdir -p "$SK/Ctor106"; cp "$CI_DIR/sketches/Ctor106/Ctor106.ino.txt" "$SK/Ctor106/Ctor106.ino"; }
+    while IFS='|' read -r key fqbn core; do
+      [[ -z $key || $key == \#* || $key == url ]] && continue
+      [[ $CORES != all && ",$CORES," != *",$key,"* ]] && continue
+      if ! grep -q "^${core} " "$LOGS/core_list_before.log" && ! $AC core list --additional-urls "$URLS" 2>/dev/null | grep -q "^${core} "; then
+        if [[ $INSTALL_CORES == 1 ]]; then
+          echo "   installing core $core ..."
+          if ! "${ACENV[@]}" $AC core install "$core" --additional-urls "$URLS" > "$LOGS/core_install_${core//:/_}.log" 2>&1; then
+            record "core_$key" FAIL "core install $core failed" "logs/core_install_${core//:/_}.log"; continue; fi
+        else record "core_$key" FAIL "core $core not installed (--no-install)"; continue; fi
+      fi
+      for s in "$SK"/*/; do
+        s="${s%/}"; n="$(basename "$s")"; lg="logs/compile_${key}_${n}.log"
+        if "${ACENV[@]}" $AC compile --fqbn "$fqbn" --library "$LIB" --warnings all --additional-urls "$URLS" --build-path "$BUILD/ac_${key}_${n}" "$s" > "$OUT/$lg" 2>&1; then
+          sz="$( { grep -oE 'Sketch uses [0-9]+ bytes' "$OUT/$lg" || grep -oE 'IROM +[0-9]+' "$OUT/$lg" || echo '?'; } | grep -oE '[0-9]+|\?' | head -1)"
+          lw="$( { grep -E "$LIB/src/.*warning" "$OUT/$lg" || true; } | sort -u | wc -l)"
+          record "compile_${key}_${n}" PASS "$sz B flash, $lw library warnings" "$lg"
+        elif [[ $n == si5351_vcxo ]] && grep -q 'get_correction' "$OUT/$lg" && [[ $REQUIRE_FIXED == 0 ]]; then
+          record "compile_${key}_${n}" XFAIL "known v2.3.0 example bug (get_correction() needs an argument; fixed in v2.4.0)" "$lg"
+        else record "compile_${key}_${n}" FAIL "compile error" "$lg"; fi
+      done
+    done < "$CI_DIR/boards.txt"
+  fi
+fi
+
+# ---------------------------------------------------------------- 8. summary
+FINISHED="$(date -u +%Y-%m-%dT%H:%M:%SZ)"; echo "FINISHED=$FINISHED" >> "$OUT/meta.env"
+set +e; $PY "$CI_DIR/tools/summarize.py" "$OUT"; RC=$?; set -e
+echo "== summary: $OUT/summary.md  $OUT/summary.json  (exit $RC)"
+exit $RC
diff --git a/tests/regression/sketches/Ctor106/Ctor106.ino.txt b/tests/regression/sketches/Ctor106/Ctor106.ino.txt
new file mode 100644
index 0000000..ec1306b
--- /dev/null
+++ b/tests/regression/sketches/Ctor106/Ctor106.ino.txt
@@ -0,0 +1,30 @@
+// Issue #103/#106 review: every constructor form must compile on every core.
+#include <Wire.h>
+#include <si5351.h>
+
+Si5351 s_default;            // default: &Wire, 0x60
+Si5351 s_addr(0x61);         // address only (uint8_t)
+Si5351 s_wire(&Wire);        // bus only
+Si5351 s_zero(0);            // reviewer finding 1: must not be ambiguous
+Si5351 s_null(NULL);         // reviewer finding 1: must not be ambiguous
+#if defined(ESP32) || defined(ARDUINO_ARCH_MBED) || (defined(WIRE_INTERFACES_COUNT) && WIRE_INTERFACES_COUNT > 1) || defined(ARDUINO_ARCH_RP2040)
+#define HAVE_WIRE1 1
+Si5351 s_wire1(&Wire1, 0x61);
+#elif defined(ARDUINO_ARCH_STM32)
+#define HAVE_WIRE1 1
+TwoWire Wire1x(PB11, PB10);
+Si5351 s_wire1(&Wire1x, 0x61);
+#endif
+
+void setup() {
+  s_default.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+  s_addr.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+  s_wire.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+  s_zero.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+  s_null.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+#ifdef HAVE_WIRE1
+  s_wire1.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
+#endif
+  s_default.set_freq(1000000000ULL, SI5351_CLK0);
+}
+void loop() {}
diff --git a/tests/regression/stubs/Arduino.h b/tests/regression/stubs/Arduino.h
new file mode 100644
index 0000000..438cc43
--- /dev/null
+++ b/tests/regression/stubs/Arduino.h
@@ -0,0 +1,9 @@
+// Minimal host stub of Arduino.h for native Si5351 harness
+#ifndef ARDUINO_STUB_H
+#define ARDUINO_STUB_H
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+typedef bool boolean;
+typedef uint8_t byte;
+#endif
diff --git a/tests/regression/stubs/Wire.cpp b/tests/regression/stubs/Wire.cpp
new file mode 100644
index 0000000..29bac60
--- /dev/null
+++ b/tests/regression/stubs/Wire.cpp
@@ -0,0 +1,92 @@
+#include "Wire.h"
+#include "sim.h"
+#include <stdio.h>
+#include <string.h>
+
+TwoWire Wire;
+Si5351Sim g_sim;
+
+static std::string hexbytes(const uint8_t *p, size_t n) {
+  std::string s = "[";
+  char b[8];
+  for (size_t i = 0; i < n; i++) {
+    snprintf(b, sizeof b, i ? " %02X" : "%02X", p[i]);
+    s += b;
+  }
+  return s + "]";
+}
+
+void Si5351Sim::reset(int pattern, bool present_) {
+  // pattern 0: all-zero register file; pattern 1: deterministic non-zero
+  // fill so read-modify-write bugs (lost/extra bits) become visible.
+  for (int i = 0; i < 256; i++)
+    regs[i] = pattern ? (uint8_t)((i * 37 + 11) ^ 0xA5) : 0;
+  regs[0] &= 0x7F;  // SYS_INIT clear => device ready (init() polls bit 7)
+  ptr = 0; dev_addr = 0x60; present = present_;
+  in_tx = false; tx_addr = 0; tx_buf.clear();
+  rx_buf.clear(); rx_pos = 0;
+  events.clear(); n_writes = n_reads = 0;
+}
+
+void TwoWire::begin() { g_sim.events.push_back("BEGIN"); }
+
+void TwoWire::beginTransmission(uint8_t addr) {
+  g_sim.in_tx = true; g_sim.tx_addr = addr; g_sim.tx_buf.clear();
+}
+
+size_t TwoWire::write(uint8_t b) {
+  if (!g_sim.in_tx) { g_sim.events.push_back("ERR write-outside-tx"); return 0; }
+  g_sim.tx_buf.push_back(b);
+  return 1;
+}
+
+uint8_t TwoWire::endTransmission(uint8_t) { return endTransmission(); }
+
+uint8_t TwoWire::endTransmission(void) {
+  char line[64];
+  Si5351Sim &s = g_sim;
+  s.in_tx = false;
+  bool ack = s.present && s.tx_addr == s.dev_addr;
+  if (s.tx_buf.empty()) {
+    snprintf(line, sizeof line, "PROBE a=%02X ack=%d", s.tx_addr, ack);
+    s.events.push_back(line);
+  } else if (s.tx_buf.size() == 1) {
+    snprintf(line, sizeof line, "PTR a=%02X r=%u", s.tx_addr, s.tx_buf[0]);
+    s.events.push_back(line);
+    if (ack) s.ptr = s.tx_buf[0];
+  } else {
+    uint8_t reg = s.tx_buf[0];
+    snprintf(line, sizeof line, "W a=%02X r=%u n=%u ", s.tx_addr, reg,
+             (unsigned)(s.tx_buf.size() - 1));
+    s.events.push_back(line + hexbytes(&s.tx_buf[1], s.tx_buf.size() - 1));
+    if (ack) {
+      for (size_t i = 1; i < s.tx_buf.size(); i++) s.regs[(uint8_t)(reg + i - 1)] = s.tx_buf[i];
+      s.ptr = (uint8_t)(reg + s.tx_buf.size() - 1);
+      s.n_writes++;
+    }
+  }
+  s.tx_buf.clear();
+  return ack ? 0 : 2;
+}
+
+uint8_t TwoWire::requestFrom(uint8_t addr, uint8_t quantity) {
+  Si5351Sim &s = g_sim;
+  s.rx_buf.clear(); s.rx_pos = 0;
+  bool ack = s.present && addr == s.dev_addr;
+  if (ack) {
+    for (uint8_t i = 0; i < quantity; i++) s.rx_buf.push_back(s.regs[(uint8_t)(s.ptr + i)]);
+    s.ptr = (uint8_t)(s.ptr + quantity);
+    s.n_reads++;
+  }
+  char line[48];
+  snprintf(line, sizeof line, "R a=%02X n=%u -> ", addr, quantity);
+  s.events.push_back(line + hexbytes(s.rx_buf.data(), s.rx_buf.size()));
+  return (uint8_t)s.rx_buf.size();
+}
+
+int TwoWire::available(void) { return (int)(g_sim.rx_buf.size() - g_sim.rx_pos); }
+
+int TwoWire::read(void) {
+  if (g_sim.rx_pos >= g_sim.rx_buf.size()) return -1;
+  return g_sim.rx_buf[g_sim.rx_pos++];
+}
diff --git a/tests/regression/stubs/Wire.h b/tests/regression/stubs/Wire.h
new file mode 100644
index 0000000..5413f5c
--- /dev/null
+++ b/tests/regression/stubs/Wire.h
@@ -0,0 +1,19 @@
+// Host stub of Arduino Wire (TwoWire) backed by a simulated Si5351 register file.
+#ifndef WIRE_STUB_H
+#define WIRE_STUB_H
+#include <stdint.h>
+#include <stddef.h>
+
+class TwoWire {
+public:
+  void begin();
+  void beginTransmission(uint8_t addr);
+  size_t write(uint8_t b);
+  uint8_t endTransmission(void);
+  uint8_t endTransmission(uint8_t sendStop);
+  uint8_t requestFrom(uint8_t addr, uint8_t quantity);
+  int available(void);
+  int read(void);
+};
+extern TwoWire Wire;
+#endif
diff --git a/tests/regression/stubs/sim.h b/tests/regression/stubs/sim.h
new file mode 100644
index 0000000..e265075
--- /dev/null
+++ b/tests/regression/stubs/sim.h
@@ -0,0 +1,27 @@
+#ifndef SI5351_SIM_H
+#define SI5351_SIM_H
+#include <stdint.h>
+#include <string>
+#include <vector>
+
+struct Si5351Sim {
+  uint8_t regs[256];
+  uint8_t ptr;              // device register pointer (auto-increments)
+  uint8_t dev_addr;         // address the simulated device answers on
+  bool present;             // device ACKs?
+  // current transmission
+  bool in_tx;
+  uint8_t tx_addr;
+  std::vector<uint8_t> tx_buf;
+  // pending read data
+  std::vector<uint8_t> rx_buf;
+  size_t rx_pos;
+  // transcript
+  std::vector<std::string> events;
+  unsigned long n_writes, n_reads;
+
+  void reset(int pattern, bool present_ = true);
+  void mark(const std::string &s) { events.push_back("CALL " + s); }
+};
+extern Si5351Sim g_sim;
+#endif
diff --git a/tests/regression/tools/summarize.py b/tests/regression/tools/summarize.py
new file mode 100644
index 0000000..c8ebeb1
--- /dev/null
+++ b/tests/regression/tools/summarize.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+"""Build summary.json + summary.md from results.tsv + meta.env. Exit 1 on any FAIL."""
+import json, sys
+from pathlib import Path
+out = Path(sys.argv[1])
+meta = dict(l.split("=", 1) for l in (out / "meta.env").read_text().splitlines() if "=" in l)
+rows = []
+for l in (out / "results.tsv").read_text().splitlines():
+    n, s, d, lg = (l.split("\t") + [""] * 4)[:4]
+    rows.append({"check": n, "status": s, "detail": d, "log": lg})
+cnt = {}
+for r in rows: cnt[r["status"]] = cnt.get(r["status"], 0) + 1
+overall = "FAIL" if cnt.get("FAIL") else "PASS"
+mode = "require-fixed" if meta.get("REQUIRE_FIXED") == "1" else "default (acceptance failures = expected-fail)"
+doc = {"overall": overall, "mode": mode, "pinned_sha": meta.get("SHA"), "source": meta.get("SRC_KIND", "") + " " + meta.get("SRC_DESC", ""),
+       "library_version": meta.get("LIBVER"), "dirty": meta.get("DIRTY"), "started_utc": meta.get("STARTED"), "finished_utc": meta.get("FINISHED"),
+       "host": meta.get("HOST"), "os": meta.get("OS"), "cxx": meta.get("CXX_VERSION"), "python": meta.get("PY_VERSION"),
+       "arduino_cli": meta.get("ARDUINO_CLI"), "cores": meta.get("CORES") or None, "counts": cnt, "checks": rows}
+(out / "summary.json").write_text(json.dumps(doc, indent=1) + "\n")
+md = [f"# Si5351Arduino v2.3.1 checks: **{overall}**", "",
+      f"- Pinned SHA: `{doc['pinned_sha']}` (library.properties version {doc['library_version'] or '?'})",
+      f"- Source: {doc['source']}" + (f" (dirty: {doc['dirty']})" if doc['dirty'] not in ("n/a", "no", None) else ""),
+      f"- Mode: {mode}", f"- Started {doc['started_utc']}, finished {doc['finished_utc']} (UTC)",
+      f"- Host: {doc['host']} ({doc['os']}); {doc['cxx']}; {doc['python']}" + (f"; {doc['arduino_cli']}" if doc['arduino_cli'] else ""),
+      f"- Counts: " + ", ".join(f"{k} {v}" for k, v in sorted(cnt.items())), "",
+      "| Check | Status | Detail | Log |", "|---|---|---|---|"]
+for r in rows:
+    md.append(f"| {r['check']} | {'**FAIL**' if r['status']=='FAIL' else r['status']} | {r['detail'].replace('|','/')} | {r['log']} |")
+md += ["", "Statuses: PASS; FAIL = unexpected failure (exit 1); XFAIL = expected failure (v2.3.1 acceptance tests in default mode, known v2.3.0 vcxo example bug); SKIP = not applicable to this source; INFO = reported, not gating."]
+(out / "summary.md").write_text("\n".join(md) + "\n")
+print(f"OVERALL {overall}: " + ", ".join(f"{k} {v}" for k, v in sorted(cnt.items())))
+sys.exit(1 if overall == "FAIL" else 0)
diff --git a/tests/regression/v231/DEBATABLE.md b/tests/regression/v231/DEBATABLE.md
new file mode 100644
index 0000000..c25891e
--- /dev/null
+++ b/tests/regression/v231/DEBATABLE.md
@@ -0,0 +1,14 @@
+# Debatable expectations (decide before finalising the fix)
+
+For these items the tests only check the **policy-neutral spec invariants** and accept any listed option. The machine-readable copy is the `debatable` block in `v231_acceptance.json`.
+
+| ID | Tests | Question | Options | Test currently accepts |
+|---|---|---|---|---|
+| D1 | A01, A02 | `set_freq(f < 18.454 kHz)` on CLK6/7 (10 kHz, 15 kHz). The lowest legal output is 600 MHz/254/128 ≈ 18454 Hz | (a) reject: ret 1, no writes (like the CLK7 non-integer reject); (b) clamp to the CLK6/7 minimum and return 0 (like the CLK0-5 clamp); (c) clamp and return a non-zero code | (a), (b) or (c), provided reg90 is even 6..254, `pllb_freq` is 600..900 MHz and the output is ≥ 18454 Hz. **Gotcha:** `SI5351_CLKOUT67_MIN_FREQ` truncates to 18454. 254×128×18454 Hz = 599.98 MHz < VCO_MIN, so clamping to the constant itself trips the `a += 2` path again and writes MS6 = 256 → 0x00. Round up (18455) or guard `a += 2` beyond 254 |
+| D2 | A09, A10 | `set_freq(0)` on CLK6/7. Today it crashes with a peer set; without a peer it writes MS6_P1 = 0 | (a) return 1, no writes; (b) treat 0 as "disable output"; (c) mirror CLK0-5, which today writes a 500 kHz MS and enables the output | anything without a crash or an invalid reg90/91 value. Consider making CLK0-5 consistent too (it is not locked) |
+| D3 | A11-A13 | Requests > 200 MHz on CLK0-5 (210/225 MHz; `SI5351_MULTISYNTH_MAX_FREQ` is 225 MHz) | (a) clamp to 200 MHz (DIVBY4, PLL 800 MHz); (b) reject with ret 1 | either. For `set_freq_manual`, clamping `freq` is not enough: DIVBY4 outputs PLL/4, so 900 MHz still gives 225 MHz. The fix must reject or refuse DIVBY4 when pll ≠ 4×freq (DEV-06 overlap) |
+| D4 | A14-A16 | `set_freq_manual` with an illegal MS ratio (5, 6.667, 7) | (a) return 1 without writing MS; (b) round to a legal ratio; (c) write, but return non-zero | (a) with no MS0 block written, or any legal written ratio. Open sub-question: may a rejected call still write the PLL? 1ddd43e writes the PLL first |
+| D5 | A22 | `init(SI5351_CRYSTAL_LOAD_0PF)`: XTAL_CL = 00b is reserved | (a) map to 6 pF (01b); (b) leave the 10 pF default (11b); (c) deprecate/remove the constant (API change) | any XTAL_CL ≠ 00b with bits 5:0 = 010010b |
+| D6 | A25 | 5 MHz reference (DEV-13). PLL input range is 10-40 MHz, and no legal feedback ratio exists for 600-900 MHz | (a) `init()`/`set_ref_freq` reject < 10 MHz. Careful: `xtal_freq` = 0 then divides by zero in `pll_calc`; (b) recompute `a` after the clamp → ratio 90, VCO 450 MHz (still out of spec); (c) never write an out-of-range feedback block | any policy that writes no PLL block with a ratio outside 15..90. The validation prototype used (b), which passes the test but leaves the VCO at 450 MHz: flag it if chosen |
+
+Also worth a decision, though not a test: should A08's reject (`set_freq` returns 1 when the CLK6/7 peer is set and no legal MS×R exists) also cover the case where `pllb_freq % freq == 0` but the R divider makes it non-integer? It is the same code path, and A08 is exactly that case.
diff --git a/tests/regression/v231/FAILS_ON_MASTER.md b/tests/regression/v231/FAILS_ON_MASTER.md
new file mode 100644
index 0000000..049b13f
--- /dev/null
+++ b/tests/regression/v231/FAILS_ON_MASTER.md
@@ -0,0 +1,53 @@
+# FAILS_ON_MASTER: v2.3.1 acceptance tests vs master 1ddd43e
+
+Evidence comes from real runs. `acceptance.cpp` with `scenarios_v231.inc` was compiled against the **pinned 1ddd43e source** (`master_1ddd43e/`, extracted with `git show 1ddd43e:src/si5351.{cpp,h}`; SHA-256 in `master_1ddd43e/SHA256SUMS`). The live `/workspace/Si5351Arduino` working tree was not used, because another agent is committing on `v2.3.1-fixes`. The stubs are the Coding PM harness stubs (`/workspace/si5351-equiv/stubs`). Each scenario runs in a forked child on both register-file patterns (p0 zero-filled, p1 pattern-filled).
+
+Run log: `logs/test_v231_master.log` (`python3 test_v231.py logs/acc_master.jsonl --expect-master`, exit 0). Raw output: `logs/acc_master.jsonl`.
+
+**Result: 25/25 acceptance tests FAIL on 1ddd43e, on both patterns. Must-not-break: 776/776 checks pass.**
+
+Observed values are from p0. p1 is identical except where noted.
+
+| Test | Item | Call sequence | Expected (correct) | Observed on 1ddd43e |
+|---|---|---|---|---|
+| **A01** FAIL | 1 DEV-03 | `init0(); sf(10000 * M, 6);` | every reg90 write by set_freq is an even integer 6..254: even 6..254 (AN619 Reg 90, AN619.txt:2696); stored pllb_freq within VCO 600..900 MHz: 600..900 MHz (AN619.txt:37); either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz: reject or clamp>=18454 Hz (DEBATABLE D1) | ['0x00']; 128 MHz; ret=0 clk_freq[6]=4000 Hz realized=None Hz |
+| **A02** FAIL | 4 CLK67 clamp | `init0(); sf(15000 * M, 6);` | every reg90 write by set_freq is an even integer 6..254: even 6..254 (AN619 Reg 90, AN619.txt:2696); stored pllb_freq within VCO 600..900 MHz: 600..900 MHz (AN619.txt:37); either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz: reject or clamp>=18454 Hz (DEBATABLE D1) | ['0x00']; 128 MHz; ret=0 clk_freq[6]=4000 Hz realized=None Hz |
+| **A03** FAIL | 1 DEV-15 | `init0(); sfm(87400000 * M, 874000000 * M, 7);` | reg91 (MS7_P1): 0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10); realized CLK7: 87.4 MHz | 0x00; None MHz |
+| **A04** FAIL | 1 DEV-15 | `init0(); sfm(87400000 * M, 874000000 * M, 6);` | reg90 (MS6_P1): 0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10); realized CLK6: 87.4 MHz | 0x00; None MHz |
+| **A05** FAIL | 2 DEV-14 | `init0(); sf(23000000 * M, 6);` | reg3 CLK6_OEB after set_freq: 0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch) | 1 |
+| **A06** FAIL | 2 DEV-14 | `init0(); sf(23000000 * M, 6); sf(87400000 * M, 7);` | reg3 CLK6_OEB after set_freq: 0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch); reg3 CLK7_OEB after set_freq: 0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch) | 1; 1 |
+| **A07** FAIL | 2 DEV-14 | `init0(); sf(23000000 * M, 7);` | reg3 CLK7_OEB after set_freq: 0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch) | 1 |
+| **A08** FAIL | 4 uninit | `init0(); sf(23000000 * M, 6); sf(1000000 * M, 7);` | set_freq(1 MHz, CLK7) return: 1: 874 MHz/1 MHz = 874 = 2x437, no even MS7 6..254 x R=2^k exists (AN619.txt:74, Reg 92 R7); no write to reg 91 (uninitialised ms_reg.p1): no write; clk_freq[7] unchanged: 0 | 0; ['0xFE']; 1000000.0 |
+| **A09** FAIL | 4 div0 | `init0(); sf(23000000 * M, 6); sf(0, 7);` | set_freq(0, CLK7) with peer set does not crash: no crash (no '% 0') | Floating point exception |
+| **A10** FAIL | 4 div0 | `init0(); sf(23000000 * M, 7); sf(0, 6);` | set_freq(0, CLK6) with peer set does not crash: no crash (no '% 0') | Floating point exception |
+| **A11** FAIL | 4 fmax | `init0(); sf(210000000 * M, 0);` | realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written): <= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp); stored clk_freq[0] <= 200 MHz: <= 200 MHz | ret=0 realized=210.0 MHz; 210 MHz |
+| **A12** FAIL | 4 fmax | `init0(); sf(225000000 * M, 0);` | realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written): <= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp); stored clk_freq[0] <= 200 MHz: <= 200 MHz | ret=0 realized=225.0 MHz; 225 MHz |
+| **A13** FAIL | 4 fmax | `init0(); sfm(225000000 * M, 900000000 * M, 0);` | realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written): <= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp); stored clk_freq[0] <= 200 MHz: <= 200 MHz | ret=0 realized=225.0 MHz; 225 MHz |
+| **A14** FAIL | 4 ms ratio | `init0(); sfm(140000000 * M, 700000000 * M, 0);` | MS0 ratio valid (or call rejected without writing MS0): 4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4) | ret=0 ratio=5 |
+| **A15** FAIL | 4 ms ratio | `init0(); sfm(90000000 * M, 600000000 * M, 0);` | MS0 ratio valid (or call rejected without writing MS0): 4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4) | ret=0 ratio=6.66667 |
+| **A16** FAIL | 4 ms ratio | `init0(); sfm(100000000 * M, 700000000 * M, 0);` | MS0 ratio valid (or call rejected without writing MS0): 4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4) | ret=0 ratio=7 |
+| **A17** FAIL | 4 phase | `init0(); phase_(6, 10);` | no write to reserved reg 171: none (AN619.txt:582 'Reg 171-176 Reserved') | [10] |
+| **A18** FAIL | 4 phase | `init0(); phase_(7, 10);` | no write to reserved reg 172: none (AN619.txt:582 'Reg 171-176 Reserved') | [10] |
+| **A19** FAIL | 4 set_int | `init0(); corr_(100000, 0); setint_(6, 1);` | reg22 bit6 (FBA_INT) unchanged by set_int(CLK6): bit6 unchanged: FBA_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit | 0x6C (before 0x2C) |
+| **A20** FAIL | 4 set_int | `init0(); corr_(100000, 0); setint_(7, 1);` | reg23 bit6 (FBB_INT) unchanged by set_int(CLK7): bit6 unchanged: FBB_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit | 0x6C (before 0x2C) |
+| **A21** FAIL | 4 clkin div | `init0(); reff(50000000, 1); pllin(0, 1); reff(80000000, 1); pllin(0, 1);` | reg15 CLKIN_DIV[1:0] after 80 MHz CLKIN: 10b = /4 (AN619.txt:834-840; 80 MHz needs /4 for 10-40 MHz, AN619.txt:94) | 11b (reg15=0xC4) (p1: 11b (reg15=0xD7)) |
+| **A22** FAIL | 4 0pF | `init_(SI5351_CRYSTAL_LOAD_0PF, 0, 0);` | reg183: XTAL_CL != 00b, bits5:0 = 010010b (AN619.txt:3134-3141; DEBATABLE D5 which value) | 0x12 (XTAL_CL=00b) |
+| **A23** FAIL | 4 vcxo | `init0(); svcxo(876000000 * M, 40); corr_(0, 0);` | MSNB c (P3): 1000000 (AN619.txt:418 'c ... fixed to 10^6'); PLLB VCO: 876 MHz (set_vcxo value preserved); PLLB regs 34..41 == set_vcxo() result: [66, 64, 0, 15, 133, 241, 212, 192] | 1; 800.0 MHz; [0, 1, 0, 14, 0, 0, 0, 0] |
+| **A24** FAIL | 4 vcxo | `init0(); svcxo(876000000 * M, 40); pllin(0, 0);` | MSNB c (P3): 1000000 (AN619.txt:418 'c ... fixed to 10^6'); PLLB VCO: 876 MHz (set_vcxo value preserved); PLLB regs 34..41 == set_vcxo() result: [66, 64, 0, 15, 133, 241, 212, 192] | 1; 800.0 MHz; [0, 1, 0, 14, 0, 0, 0, 0] |
+| **A25** FAIL | 4 DEV-13 | `init_(L8, 5000000, 0);` | every PLLA/PLLB feedback block written has a+b/c in 15..90: 15..90 (AN619.txt:116; DEBATABLE D6 for the 5 MHz policy) | [(26, 120.0), (26, 120.0), (26, 160.0), (34, 120.0), (34, 120.0), (34, 160.0)] |
+
+Notes
+- A08: the build uses `-ftrivial-auto-var-init=pattern`, so the uninitialised `ms_reg.p1` reads as 0xFE (it looks like a legal 254). On an AVR it is stack garbage. The test checks for *no write* to reg 91 and `ret == 1`, so the result does not depend on the garbage value. R7 is also written as /4 (reg92 = 0x20).
+- A09/A10: the child process dies with SIGFPE (`pllb_freq % 0`). On an AVR the result of the division is undefined (no trap).
+- A25: the blocks with ratio 120 come from `init()` → `set_correction()` → `set_pll(plla_freq = 0)` before `reset()` (VCO clamped to 600 MHz / 5 MHz = 120). Ratio 160 is from `reset()` → `set_pll(800 MHz)`.
+- A13 shows that clamping `freq` alone is not enough: `set_freq_manual(225 MHz, 900 MHz)` forces DIVBY4, so the output is PLL/4 = 225 MHz whatever the clamped `freq` is (overlaps DEV-06).
+
+## The tests can pass (validation)
+`proto_fix/` is a TEST-VALIDATION-ONLY patch of the pinned source (`proto_fix/proto_patch.py`, `proto_fix/proto.diff`). It picks one arbitrary option for each debatable item and is not a proposed fix. Result: **25/25 acceptance pass, 776/776 must-not-break pass** (`logs/test_v231_proto.log`, `--require-fixed`, exit 0). So no test is unsatisfiable and none contradicts the must-not-break locks.
+
+## Informational: live `v2.3.1-fixes` working tree (snapshot)
+`snap_wip_*/` is a copy of `/workspace/Si5351Arduino/src` (HEAD 8f3fef6 plus uncommitted edits) taken during this run. Result: 21/25 pass. **A13, A15, A16 and A25 still fail.** Must-not-break: 0 failures (`logs/test_v231_wip.log`). This is a moving target; re-run before relying on it.
+
+## Reference: v2.2.0 (0559cbf)
+`logs/test_v231_v220.log`: 0/25 acceptance pass. Must-not-break has 68 failures, all in the three 2.3.0 behaviours (#65 DIVBY4-exit reset, ratio<8 re-plan, low clock moves to the other PLL). This is expected and shows that those locks detect a regression to 2.2.0 behaviour.
+
diff --git a/tests/regression/v231/MUST_NOT_BREAK.md b/tests/regression/v231/MUST_NOT_BREAK.md
new file mode 100644
index 0000000..5c1047b
--- /dev/null
+++ b/tests/regression/v231/MUST_NOT_BREAK.md
@@ -0,0 +1,43 @@
+# MUST_NOT_BREAK: behaviours the v2.3.1 fix must preserve
+
+The checks are in `test_v231.py` (`run_mnb`), with locks in `must_not_break.json`. They run on the same JSONL as the acceptance tests. **Current status on 1ddd43e: 36 scenarios × 2 register patterns, 776 checks, 0 failures** (`logs/test_v231_master.log`).
+
+Each scenario is checked in two layers:
+1. **Golden layer** (pattern 0): every `lib_*` register field from the existing 67-case suite (`../golden_cases.json`) for the mapped golden id.
+2. **1ddd43e lock** (both patterns): the full locked register set is checked: reg 3, 15, 16-23 (CLK ctrl), 26-41 (PLLA/PLLB), 42-89 (MS0-5), 90-92, 162-164 (VCXO), 165-170 (phase), 183. The lock also covers return codes, `plla_freq`/`pllb_freq`/`clk_freq[]`/`pll_assignment[]`, and the exact sequence of PLL-reset (reg 177) writes.
+
+Separate evidence that 1ddd43e still matches the existing goldens: the Coding PM harness (`/workspace/si5351-equiv/harness.cpp`) was rebuilt against the pinned 1ddd43e source and checked with `compare.py`. Result: 27 original goldens (292 field checks) and 23 newer lib_* goldens (343 register checks), **0 mismatches** (`logs/goldens_vs_master_report.txt`). The 17 goldens that harness lacks (F-, M-, A-, phase/xtal) are covered below.
+
+## Locked scenarios
+| Group | Scenario | Golden id | What is locked |
+|---|---|---|---|
+| FREQ_CHECKS #1 | clk0-10MHz | P0-clk0-common-2-10MHz | MS0 80/0/1, P1 9728, PLLA 800 MHz untouched |
+| FREQ_CHECKS #2 | clk0-14p07MHz | P0-clk0-fractional-MS-14p07MHz | fractional MS P 6765/896192/1e6 |
+| FREQ_CHECKS #4 | clk0-100MHz | F-clk0-100MHz-share-max-boundary | ≤100 MHz path keeps PLL, P 512/0/1 |
+| FREQ_CHECKS #5 | clk0-112p5MHz | S-boundary-112p5MHz-ratio8 | >100 MHz PLL recalc → 900 MHz |
+| DIVBY4 | clk0-150MHz-divby4 / clk0-200 / clk3-200 | P0-…150MHz, P0-…200MHz, S-divby4-block-clk3 | reg44 0x0C, MS_INT, P 0/0/1, PLL 600/800 MHz |
+| R div | clk0-4kHz, clk2-5kHz, clk0-512kHz | F-clk0-4kHz, S-rdiv-placement-clk2, P0-rdiv-1-512kHz | R=128 placement, R=1 boundary |
+| CLK6/7 | clk6-23MHz, clk7-87p4-after-clk6, clk6-100kHz-R6, clk7-50kHz-R7, clk6-150MHz-clamp | P0-clk6-23MHz, P0-clk7-874…, S-clk6-R6div, S-clk7-R7div, S-clk6-150MHz | PLLB 874 MHz (34/960000/1e6), reg90=38, reg91=10, reg92 R fields, 150 MHz clamp → MS6=6 |
+| CLK7 rejects | clk7-reject-12p345678, clk7-reject-odd-ratio | P0-clk7-reject-noninteger | `set_freq` returns 1 and leaves reg91 untouched (non-integer / odd ratio) |
+| manual | manual-clk1-175-700-divby4, manual-clk0-14-800-parity | P0-manual-DIVBY4-175MHz-pll700, P1-parity-14MHz | legal manual calls keep their registers and return 0 |
+| PLL assignment | pll-assign-after-reset, clk7-pll-assignment-lock, clk1-pllb-14MHz | M-clk7-pllb-assignment, M-clk5-reset-plla, P0-clk1-PLLB | after reset CLK0-5→PLLA (reg16-21=0x0C), CLK6/7→PLLB (0x2C); CLK7 first-set uses PLLB |
+| RMW | set_ms-byte2-rmw-5kHz | M-set-ms-byte2-rmw | reg44 = 0xF2 with bit7 preset (byte-2 read-modify-write) |
+| 2.3.0 #65 | divby4-exit-reset-155-96, divby4-exit-reset-156-80 | (new in 2.3.0; locked from 1ddd43e) | PLL reset on DIVBY4 exit, ratio<8 re-plan back to 800 MHz, reg177 write sequence |
+| 2.3.0 move | low-clock-moves-155-clk0-99-clk2 | (new in 2.3.0) | CLK2 moves to PLLB (reg18 0x2C, pll_assignment[2]=1), PLLA stays at 620 MHz |
+| VCXO | vcxo-876-40ppm | P0-vcxo-876MHz-40ppm | PLLB regs [66,64,0,15,133,241,212,192] and VCXO param regs 162-164 |
+| phase/int | phase-clk0-mask, phase-clk5, setint-clk0 | S-phase-clk0-mask, A-set_int-clk0-ms-int | CLK0-5 phase regs 165-170 still written; set_int(CLK0) → reg16 0x4C |
+| xtal | xtal-6pF / 8pF / 10pF | S-xtal-load-6-8-10pF, A-init-crystal-load-8pF | reg183 = 0x52 / 0x92 / 0xD2 |
+| CLKIN | clkin-div4-clean | A-set_pll_input-clkin-div4-clean | reg15 = 0x84 from a clean start |
+| refs/corr | ref-27MHz, corr-100000-14MHz | A-ref27MHz-set_pll-fixed, P0-corr-100000-14MHz | 27 MHz ref PLL regs, +100 ppm correction PLL/MS regs |
+
+## Changes the fix is ALLOWED to make (explicitly unlocked)
+- `reg3` bit 6/7 (CLK6/7 OEB) in the CLK6/7 scenarios. This is the DEV-14 fix; the other reg3 bits stay locked.
+- `state.pllb_freq` in vcxo-876-40ppm. This is a DEV-08 fix component: 1ddd43e leaves `pllb_freq` at 800 MHz although PLLB runs at 876 MHz. The registers stay locked.
+
+## NOT locked (on purpose)
+- `MNB:both-plls-held-return-code` is recorded only. This is item 3 (deferred): return codes for both-PLLs-held / other-PLL-too-low / manual-low-PLL must not be re-baselined by this work.
+- `MNB:clk0-0Hz` is recorded only. On 1ddd43e, `set_freq(0)` on CLK0-5 writes an MS for 500 kHz and enables the output. See debatable D2.
+- Some goldens are expected to change with the fix, so they are not MNB: `D-clk0-210MHz-above-spec-max`, `D-clk0-250MHz-clamped-to-225`, `D-clk6-10kHz-ms6-p1-zero`, `D-manual-*`, `D-vcxo-*`, `D-set_phase-clk6-*`, `D-init-crystal-load-0pF-*`, `D-set_int-clk6-*`, `D-set_pll_input-*` and `D-ref5MHz-*`. The DEV-14 reg3 bits in P0-clk6/7 and S-clk6/7 are also expected to change. **Heads-up:** `../test_golden.py` locks v2.2.0 library behaviour bit-for-bit, so it WILL report these as diffs after the fix. That is intended; those cases are xfail in `../test_spec.py` and should flip to xpass.
+
+## Sensitivity
+On v2.2.0 (0559cbf) the same checks report 68 failures, all in the 2.3.0 scenarios (`logs/test_v231_v220.log`). The 1ddd43e locks detect a regression to pre-2.3.0 behaviour.
diff --git a/tests/regression/v231/Makefile b/tests/regression/v231/Makefile
new file mode 100644
index 0000000..548809a
--- /dev/null
+++ b/tests/regression/v231/Makefile
@@ -0,0 +1,16 @@
+# v2.3.1 acceptance runner, built against PINNED master 1ddd43e source (not the live working tree, which other agents are editing) and v2.2.0 (0559cbf).
+# pinned: git show 1ddd43e:src/si5351.{cpp,h} (see master_1ddd43e/SHA256SUMS)
+MASTER_SRC ?= master_1ddd43e
+EQUIV ?= ..
+CXXFLAGS ?= -std=gnu++17 -O1 -g -Wall -Wno-unused-variable -Wno-unused-result -ftrivial-auto-var-init=pattern
+all: build/acc_master build/acc_v220
+build/acc_master: acceptance.cpp scenarios_v231.inc $(MASTER_SRC)/si5351.cpp $(MASTER_SRC)/si5351.h
+	mkdir -p build logs
+	g++ $(CXXFLAGS) -I. -I$(EQUIV)/stubs -I$(MASTER_SRC) acceptance.cpp $(EQUIV)/stubs/Wire.cpp $(MASTER_SRC)/si5351.cpp -o $@ 2> logs/build_acc_master.log || (cat logs/build_acc_master.log; false)
+build/acc_v220: acceptance.cpp scenarios_v231.inc
+	mkdir -p build logs
+	g++ $(CXXFLAGS) -I. -I$(EQUIV)/stubs -I$(EQUIV)/orig acceptance.cpp $(EQUIV)/stubs/Wire.cpp $(EQUIV)/orig/si5351.cpp -o $@ 2> logs/build_acc_v220.log || (cat logs/build_acc_v220.log; false)
+run: all
+	./build/acc_master logs/acc_master.jsonl
+	./build/acc_v220 logs/acc_v220.jsonl
+	python3 test_v231.py logs/acc_master.jsonl
diff --git a/tests/regression/v231/README.md b/tests/regression/v231/README.md
new file mode 100644
index 0000000..90bea24
--- /dev/null
+++ b/tests/regression/v231/README.md
@@ -0,0 +1,28 @@
+# v231: Si5351Arduino v2.3.1 acceptance tests
+
+Local only (no push, no PR). Library under test: **master 1ddd43e (v2.3.0)**, pinned in `master_1ddd43e/` with `git show`.
+
+| File | Purpose |
+|---|---|
+| `scenarios_v231.inc` | Call sequences in the Coding PM harness DSL (`init_/sf/sfm/svcxo/corr_/mssrc/pllin/reff`, plus `phase_/setint_/wr_`). 25 acceptance + 38 must-not-break/info scenarios |
+| `acceptance.cpp` | Runner. Same stubs and JSONL record format as `/workspace/si5351-equiv/harness.cpp`, plus a per-scenario `fork()` so crashes are recorded (`"crash":"Floating point exception"`) |
+| `Makefile` | `build/acc_master` (pinned 1ddd43e), `build/acc_v220` (0559cbf from `si5351-equiv/orig`); `make run` |
+| `test_v231.py` | Python oracle. Decodes registers (AN619 P1/P2/P3, VCO, MS6/7, R, OEB), runs 25 acceptance tests and the must-not-break checks |
+| `v231_acceptance.json` | Golden JSON: per test, the calls, the expected-correct values with AN619/datasheet citations, the 1ddd43e observed values and the debatable options |
+| `must_not_break.json` | 1ddd43e register/state/return/reg177 locks for the MNB scenarios |
+| `FAILS_ON_MASTER.md` · `MUST_NOT_BREAK.md` · `DEBATABLE.md` | Reports |
+| `proto_fix/` | TEST-VALIDATION ONLY patch showing that all 25 tests can pass with the MNB locks green. Not a proposed fix |
+| `snap_wip_*/` | Snapshot of the live `v2.3.1-fixes` working tree that another agent was editing during this run (informational) |
+| `logs/` | Build logs, raw JSONL, and test logs for master, v2.2.0, proto and wip; harness goldens report |
+
+## Run
+```
+make run                                                     # build both, run, test master
+python3 test_v231.py logs/acc_master.jsonl --expect-master   # 1ddd43e: all 25 FAIL, MNB green -> exit 0
+make build/acc_master MASTER_SRC=/workspace/Si5351Arduino/src && ./build/acc_master logs/acc_fix.jsonl
+python3 test_v231.py logs/acc_fix.jsonl --require-fixed      # v2.3.1 gate: all 25 PASS + MNB green -> exit 0
+```
+(When building against the live tree, use a separate output name and avoid overwriting `build/acc_master`, or rebuild it afterwards from the pinned copy.)
+
+## C++ harness integration
+`scenarios_v231.inc` uses only the harness wrappers, plus three small ones defined in `acceptance.cpp` (`phase_`, `setint_`, `wr_`). To fold it into `si5351-equiv/harness.cpp`, copy those three wrappers and `#include "scenarios_v231.inc"` inside `build()`. Note that harness.cpp's `main` has no fork(), so A09/A10 would SIGFPE and kill the whole run on 1ddd43e. Keep them in this runner or guard them there. The harness `compare.py` equivalence diff then reports every acceptance scenario as a DIFF between master and the fix (expected).
diff --git a/tests/regression/v231/acceptance.cpp b/tests/regression/v231/acceptance.cpp
new file mode 100644
index 0000000..4588abd
--- /dev/null
+++ b/tests/regression/v231/acceptance.cpp
@@ -0,0 +1,81 @@
+// v2.3.1 acceptance runner. Same stubs, wrapper DSL and JSONL record format as
+// /workspace/si5351-equiv/harness.cpp; adds per-scenario fork() so a crash (SIGFPE in
+// set_freq(0) on CLK6/7) is recorded as {"crash":"SIGFPE"} instead of killing the run.
+#include "si5351.h"
+#include "sim.h"
+#include <new>
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include <string>
+#include <vector>
+#include <functional>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <signal.h>
+typedef unsigned long long ull;
+static const ull M = SI5351_FREQ_MULT;
+alignas(Si5351) static unsigned char objbuf[sizeof(Si5351)];
+static Si5351 *S;
+static std::vector<std::string> RETS;
+static void mark(const char *fmt, ...) { char b[160]; va_list ap; va_start(ap, fmt); vsnprintf(b, sizeof b, fmt, ap); va_end(ap); g_sim.mark(b); }
+static void ret(const char *n, long long v) { char b[96]; snprintf(b, sizeof b, "%s=%lld", n, v); RETS.push_back(b); g_sim.events.push_back(std::string("RET ") + b); }
+static bool init_(uint8_t load, uint32_t xo, int32_t corr) { mark("init(%u,%u,%d)", load, xo, corr); bool r = S->init(load, xo, corr); ret("init", r); return r; }
+static uint8_t sf(ull f, int clk) { mark("set_freq(%llu,CLK%d)", f, clk); uint8_t r = S->set_freq(f, (enum si5351_clock)clk); ret("set_freq", r); return r; }
+static uint8_t sfm(ull f, ull p, int clk) { mark("set_freq_manual(%llu,%llu,CLK%d)", f, p, clk); uint8_t r = S->set_freq_manual(f, p, (enum si5351_clock)clk); ret("set_freq_manual", r); return r; }
+static void svcxo(ull p, int ppm) { mark("set_vcxo(%llu,%d)", p, ppm); S->set_vcxo(p, ppm); }
+static void corr_(int32_t c, int ref) { mark("set_correction(%d,%d)", c, ref); S->set_correction(c, (enum si5351_pll_input)ref); }
+static void mssrc(int clk, int pll) { mark("set_ms_source(CLK%d,PLL%c)", clk, pll ? 'B' : 'A'); S->set_ms_source((enum si5351_clock)clk, (enum si5351_pll)pll); }
+static void pllin(int pll, int in) { mark("set_pll_input(%d,%d)", pll, in); S->set_pll_input((enum si5351_pll)pll, (enum si5351_pll_input)in); }
+static void reff(uint32_t f, int ref) { mark("set_ref_freq(%u,%d)", f, ref); S->set_ref_freq(f, (enum si5351_pll_input)ref); }
+static void phase_(int clk, int ph) { mark("set_phase(CLK%d,%d)", clk, ph); S->set_phase((enum si5351_clock)clk, (uint8_t)ph); }
+static void setint_(int clk, int en) { mark("set_int(CLK%d,%d)", clk, en); S->set_int((enum si5351_clock)clk, (uint8_t)en); }
+static void wr_(int reg, int v) { mark("si5351_write(%d,%d)", reg, v); S->si5351_write((uint8_t)reg, (uint8_t)v); }
+static void init0() { init_(SI5351_CRYSTAL_LOAD_8PF, 0, 0); }
+struct Scn { std::string id; std::function<void()> fn; };
+static std::vector<Scn> SC;
+static void add(const std::string &id, std::function<void()> fn) { SC.push_back({id, fn}); }
+static void jstr(FILE *o, const std::string &s) { fputc('"', o); for (char c : s) { if (c == '"' || c == '\\') fputc('\\', o); fputc(c, o); } fputc('"', o); }
+static void build() {
+#include "scenarios_v231.inc"
+}
+int main(int argc, char **argv) {
+  const char *outpath = argc > 1 ? argv[1] : "v231.jsonl";
+  FILE *o = fopen(outpath, "w");
+  build();
+  for (int pattern = 0; pattern < 2; pattern++)
+    for (auto &sc : SC) {
+      fflush(o);
+      int pfd[2]; pipe(pfd);
+      pid_t pid = fork();
+      if (pid == 0) {
+        close(pfd[0]); FILE *w = fdopen(pfd[1], "w");
+        g_sim.reset(pattern, true); RETS.clear();
+        memset(objbuf, 0, sizeof objbuf); S = new (objbuf) Si5351();
+        sc.fn();
+        fprintf(w, "{\"id\":"); jstr(w, sc.id);
+        fprintf(w, ",\"pattern\":%d,\"crash\":null,\"rets\":[", pattern);
+        for (size_t i = 0; i < RETS.size(); i++) { if (i) fputc(',', w); jstr(w, RETS[i]); }
+        fprintf(w, "],\"regs\":[");
+        for (int i = 0; i < 256; i++) fprintf(w, i ? ",%u" : "%u", g_sim.regs[i]);
+        fprintf(w, "],\"state\":{\"plla_freq\":%llu,\"pllb_freq\":%llu,\"clk_freq\":[", (ull)S->plla_freq, (ull)S->pllb_freq);
+        for (int i = 0; i < 8; i++) fprintf(w, i ? ",%llu" : "%llu", (ull)S->clk_freq[i]);
+        fprintf(w, "],\"pll_assignment\":[");
+        for (int i = 0; i < 8; i++) fprintf(w, i ? ",%d" : "%d", (int)S->pll_assignment[i]);
+        fprintf(w, "],\"xtal_freq\":[%u,%u]},\"tx\":[", S->xtal_freq[0], S->xtal_freq[1]);
+        for (size_t i = 0; i < g_sim.events.size(); i++) { if (i) fputc(',', w); jstr(w, g_sim.events[i]); }
+        fprintf(w, "]}\n"); fclose(w); _exit(0);
+      }
+      close(pfd[1]);
+      std::string buf; char b[65536]; ssize_t n;
+      while ((n = read(pfd[0], b, sizeof b)) > 0) buf.append(b, n);
+      close(pfd[0]);
+      int st; waitpid(pid, &st, 0);
+      if (WIFSIGNALED(st)) {
+        fprintf(o, "{\"id\":"); jstr(o, sc.id);
+        fprintf(o, ",\"pattern\":%d,\"crash\":\"%s\",\"rets\":[],\"regs\":null,\"state\":null,\"tx\":[]}\n", pattern, strsignal(WTERMSIG(st)));
+      } else fputs(buf.c_str(), o);
+    }
+  fclose(o);
+  fprintf(stderr, "%zu scenarios x 2 patterns -> %s\n", SC.size(), outpath);
+}
diff --git a/tests/regression/v231/must_not_break.json b/tests/regression/v231/must_not_break.json
new file mode 100644
index 0000000..4e9eae7
--- /dev/null
+++ b/tests/regression/v231/must_not_break.json
@@ -0,0 +1,9036 @@
+{
+ "source": "acc_master.jsonl (library 1ddd43e)",
+ "lock_regs": [
+  3,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  32,
+  33,
+  34,
+  35,
+  36,
+  37,
+  38,
+  39,
+  40,
+  41,
+  42,
+  43,
+  44,
+  45,
+  46,
+  47,
+  48,
+  49,
+  50,
+  51,
+  52,
+  53,
+  54,
+  55,
+  56,
+  57,
+  58,
+  59,
+  60,
+  61,
+  62,
+  63,
+  64,
+  65,
+  66,
+  67,
+  68,
+  69,
+  70,
+  71,
+  72,
+  73,
+  74,
+  75,
+  76,
+  77,
+  78,
+  79,
+  80,
+  81,
+  82,
+  83,
+  84,
+  85,
+  86,
+  87,
+  88,
+  89,
+  90,
+  91,
+  92,
+  162,
+  163,
+  164,
+  165,
+  166,
+  167,
+  168,
+  169,
+  170,
+  183
+ ],
+ "allowed_change": {
+  "MNB:clk6-23MHz": [
+   "reg3.6"
+  ],
+  "MNB:clk7-87p4-after-clk6": [
+   "reg3.6",
+   "reg3.7"
+  ],
+  "MNB:clk7-reject-12p345678": [
+   "reg3.6"
+  ],
+  "MNB:clk7-reject-odd-ratio": [
+   "reg3.6"
+  ],
+  "MNB:clk6-100kHz-R6": [
+   "reg3.6"
+  ],
+  "MNB:clk7-50kHz-R7": [
+   "reg3.7"
+  ],
+  "MNB:clk6-150MHz-clamp": [
+   "reg3.6"
+  ],
+  "MNB:clk7-pll-assignment-lock": [
+   "reg3.7"
+  ]
+ },
+ "allowed_state_change": {
+  "MNB:vcxo-876-40ppm": [
+   "pllb_freq"
+  ]
+ },
+ "golden_map": {
+  "MNB:clk0-10MHz": "P0-clk0-common-2-10MHz",
+  "MNB:clk0-14p07MHz": "P0-clk0-fractional-MS-14p07MHz",
+  "MNB:clk0-100MHz": "F-clk0-100MHz-share-max-boundary",
+  "MNB:clk0-112p5MHz": "S-boundary-112p5MHz-ratio8",
+  "MNB:clk0-150MHz-divby4": "P0-clk0-DIVBY4-boundary-150MHz",
+  "MNB:clk0-200MHz-divby4": "P0-clk0-DIVBY4-200MHz",
+  "MNB:clk3-200MHz-divby4": "S-divby4-block-clk3-200MHz",
+  "MNB:clk0-4kHz": "F-clk0-4kHz-library-min",
+  "MNB:clk2-5kHz": "S-rdiv-placement-clk2-5kHz",
+  "MNB:clk0-512kHz": "P0-rdiv-1-512kHz-boundary",
+  "MNB:clk6-23MHz": "P0-clk6-23MHz",
+  "MNB:clk7-87p4-after-clk6": "P0-clk7-874MHz-even-div-of-clk6-pll",
+  "MNB:clk7-reject-12p345678": "P0-clk7-reject-noninteger-12p345678MHz",
+  "MNB:clk7-reject-odd-ratio": null,
+  "MNB:clk6-100kHz-R6": "S-clk6-R6div-100kHz",
+  "MNB:clk7-50kHz-R7": "S-clk7-R7div-50kHz",
+  "MNB:clk6-150MHz-clamp": "S-clk6-150MHz-upper-clamp",
+  "MNB:manual-clk1-175-700-divby4": "P0-manual-DIVBY4-175MHz-pll700",
+  "MNB:manual-clk0-14-800-parity": "P1-parity-set_freq-vs-manual-14MHz-pll800",
+  "MNB:clk1-pllb-14MHz": "P0-clk1-PLLB-14MHz",
+  "MNB:vcxo-876-40ppm": "P0-vcxo-876MHz-40ppm",
+  "MNB:pll-assign-after-reset": "M-clk7-pllb-assignment",
+  "MNB:clk7-pll-assignment-lock": null,
+  "MNB:set_ms-byte2-rmw-5kHz": "M-set-ms-byte2-rmw",
+  "MNB:divby4-exit-reset-155-96": null,
+  "MNB:divby4-exit-reset-156-80": null,
+  "MNB:low-clock-moves-155-clk0-99-clk2": null,
+  "MNB:phase-clk0-mask": "S-phase-clk0-mask",
+  "MNB:phase-clk5": null,
+  "MNB:setint-clk0": "A-set_int-clk0-ms-int",
+  "MNB:xtal-6pF": "S-xtal-load-6-8-10pF",
+  "MNB:xtal-8pF": "A-init-crystal-load-8pF",
+  "MNB:xtal-10pF": "S-xtal-load-6-8-10pF",
+  "MNB:clkin-div4-clean": "A-set_pll_input-clkin-div4-clean",
+  "MNB:ref-27MHz": "A-ref27MHz-set_pll-fixed",
+  "MNB:corr-100000-14MHz": "P0-corr-100000-14MHz-existing-pll"
+ },
+ "info_only": {
+  "MNB:both-plls-held-return-code": "item 3 deferred: return codes in both-PLLs-held / other-PLL-too-low cases are NOT locked here",
+  "MNB:clk0-0Hz": "set_freq(0) on CLK0-5 recorded only (see D2)"
+ },
+ "locks": {
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+    "22": 44,
+    "23": 44,
+    "26": 66,
+    "27": 64,
+    "28": 0,
+    "29": 12,
+    "30": 208,
+    "31": 249,
+    "32": 10,
+    "33": 128,
+    "34": 66,
+    "35": 64,
+    "36": 0,
+    "37": 12,
+    "38": 208,
+    "39": 249,
+    "40": 10,
+    "41": 128,
+    "42": 184,
+    "43": 231,
+    "44": 194,
+    "45": 41,
+    "46": 20,
+    "47": 115,
+    "48": 94,
+    "49": 133,
+    "50": 224,
+    "51": 207,
+    "52": 42,
+    "53": 17,
+    "54": 124,
+    "55": 91,
+    "56": 134,
+    "57": 237,
+    "58": 200,
+    "59": 55,
+    "60": 18,
+    "61": 121,
+    "62": 164,
+    "63": 131,
+    "64": 238,
+    "65": 213,
+    "66": 48,
+    "67": 31,
+    "68": 122,
+    "69": 161,
+    "70": 140,
+    "71": 235,
+    "72": 214,
+    "73": 61,
+    "74": 24,
+    "75": 71,
+    "76": 162,
+    "77": 137,
+    "78": 244,
+    "79": 211,
+    "80": 62,
+    "81": 101,
+    "82": 64,
+    "83": 175,
+    "84": 138,
+    "85": 241,
+    "86": 220,
+    "87": 59,
+    "88": 102,
+    "89": 77,
+    "90": 168,
+    "91": 151,
+    "92": 242,
+    "162": 0,
+    "163": 0,
+    "164": 0,
+    "165": 65,
+    "166": 172,
+    "167": 139,
+    "168": 246,
+    "169": 221,
+    "170": 56,
+    "183": 146
+   },
+   "rets": [
+    "init=1"
+   ],
+   "state": {
+    "plla_freq": 80000000000,
+    "pllb_freq": 80000000000,
+    "clk_freq": [
+     0,
+     0,
+     0,
+     0,
+     0,
+     0,
+     0,
+     0
+    ],
+    "pll_assignment": [
+     0,
+     0,
+     0,
+     0,
+     0,
+     0,
+     1,
+     1
+    ]
+   },
+   "reg177_writes": [
+    32,
+    128
+   ]
+  },
+  "MNB:corr-100000-14MHz#1": {
+   "regs": {
+    "3": 254,
+    "15": 147,
+    "16": 12,
+    "17": 12,
+    "18": 12,
+    "19": 12,
+    "20": 12,
+    "21": 12,
+    "22": 44,
+    "23": 44,
+    "26": 66,
+    "27": 64,
+    "28": 0,
+    "29": 13,
+    "30": 255,
+    "31": 249,
+    "32": 2,
+    "33": 64,
+    "34": 66,
+    "35": 64,
+    "36": 0,
+    "37": 13,
+    "38": 255,
+    "39": 249,
+    "40": 2,
+    "41": 64,
+    "42": 66,
+    "43": 64,
+    "44": 128,
+    "45": 26,
+    "46": 146,
+    "47": 244,
+    "48": 92,
+    "49": 0,
+    "50": 224,
+    "51": 207,
+    "52": 42,
+    "53": 17,
+    "54": 124,
+    "55": 91,
+    "56": 134,
+    "57": 237,
+    "58": 200,
+    "59": 55,
+    "60": 18,
+    "61": 121,
+    "62": 164,
+    "63": 131,
+    "64": 238,
+    "65": 213,
+    "66": 48,
+    "67": 31,
+    "68": 122,
+    "69": 161,
+    "70": 140,
+    "71": 235,
+    "72": 214,
+    "73": 61,
+    "74": 24,
+    "75": 71,
+    "76": 162,
+    "77": 137,
+    "78": 244,
+    "79": 211,
+    "80": 62,
+    "81": 101,
+    "82": 64,
+    "83": 175,
+    "84": 138,
+    "85": 241,
+    "86": 220,
+    "87": 59,
+    "88": 102,
+    "89": 77,
+    "90": 168,
+    "91": 151,
+    "92": 242,
+    "162": 0,
+    "163": 0,
+    "164": 0,
+    "165": 65,
+    "166": 172,
+    "167": 139,
+    "168": 246,
+    "169": 221,
+    "170": 56,
+    "183": 146
+   },
+   "rets": [
+    "init=1",
+    "set_freq=0"
+   ],
+   "state": {
+    "plla_freq": 80000000000,
+    "pllb_freq": 80000000000,
+    "clk_freq": [
+     1400000000,
+     0,
+     0,
+     0,
+     0,
+     0,
+     0,
+     0
+    ],
+    "pll_assignment": [
+     0,
+     0,
+     0,
+     0,
+     0,
+     0,
+     1,
+     1
+    ]
+   },
+   "reg177_writes": [
+    32,
+    128
+   ]
+  }
+ }
+}
\ No newline at end of file
diff --git a/tests/regression/v231/scenarios_v231.inc b/tests/regression/v231/scenarios_v231.inc
new file mode 100644
index 0000000..dc72e12
--- /dev/null
+++ b/tests/regression/v231/scenarios_v231.inc
@@ -0,0 +1,70 @@
+// v2.3.1 acceptance + must-not-break call sequences.
+// Same wrapper DSL as /workspace/si5351-equiv/harness.cpp (init_/sf/sfm/svcxo/corr_/mssrc/pllin/reff/...),
+// so these add(...) lines can be pasted into harness.cpp build() unchanged.
+// Frequencies are in library units (Hz * 100) via M.
+#define L8 SI5351_CRYSTAL_LOAD_8PF
+// ---------------- acceptance tests (expected to FAIL on 1ddd43e) ----------------
+add("V231:DEV03-clk6-10kHz",            [] { init0(); sf(10000 * M, 6); });
+add("V231:CLK67MIN-clk6-15kHz-clamp",   [] { init0(); sf(15000 * M, 6); });
+add("V231:DEV15-manual-clk7-87p4-874",  [] { init0(); sfm(87400000 * M, 874000000 * M, 7); });
+add("V231:DEV15-manual-clk6-87p4-874",  [] { init0(); sfm(87400000 * M, 874000000 * M, 6); });
+add("V231:DEV14-clk6-23MHz-enable",     [] { init0(); sf(23000000 * M, 6); });
+add("V231:DEV14-clk7-87p4-after-clk6",  [] { init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); });
+add("V231:DEV14-clk7-first-23MHz",      [] { init0(); sf(23000000 * M, 7); });
+add("V231:UNINIT-clk7-1MHz-peer-fail",  [] { init0(); sf(23000000 * M, 6); sf(1000000 * M, 7); });
+add("V231:DIV0-clk7-zero-with-peer",    [] { init0(); sf(23000000 * M, 6); sf(0, 7); });
+add("V231:DIV0-clk6-zero-with-peer",    [] { init0(); sf(23000000 * M, 7); sf(0, 6); });
+add("V231:FMAX-clk0-210MHz",            [] { init0(); sf(210000000 * M, 0); });
+add("V231:FMAX-clk0-225MHz",            [] { init0(); sf(225000000 * M, 0); });
+add("V231:FMAX-manual-clk0-225MHz-900", [] { init0(); sfm(225000000 * M, 900000000 * M, 0); });
+add("V231:MSRATIO-manual-140-700-r5",   [] { init0(); sfm(140000000 * M, 700000000 * M, 0); });
+add("V231:MSRATIO-manual-90-600-r6p67", [] { init0(); sfm(90000000 * M, 600000000 * M, 0); });
+add("V231:MSRATIO-manual-100-700-r7",   [] { init0(); sfm(100000000 * M, 700000000 * M, 0); });
+add("V231:PHASE-clk6-reg171",           [] { init0(); phase_(6, 10); });
+add("V231:PHASE-clk7-reg172",           [] { init0(); phase_(7, 10); });
+add("V231:SETINT-clk6-fba-int",         [] { init0(); corr_(100000, 0); setint_(6, 1); });
+add("V231:SETINT-clk7-fbb-int",         [] { init0(); corr_(100000, 0); setint_(7, 1); });
+add("V231:CLKINDIV-50-then-80MHz",      [] { init0(); reff(50000000, 1); pllin(0, 1); reff(80000000, 1); pllin(0, 1); });
+add("V231:XTAL-0PF-reserved",           [] { init_(SI5351_CRYSTAL_LOAD_0PF, 0, 0); });
+add("V231:VCXO-c-after-set_correction", [] { init0(); svcxo(876000000 * M, 40); corr_(0, 0); });
+add("V231:VCXO-c-after-set_pll_input",  [] { init0(); svcxo(876000000 * M, 40); pllin(0, 0); });
+add("V231:DEV13-ref-5MHz",              [] { init_(L8, 5000000, 0); });
+// ---------------- must-not-break (pass on 1ddd43e; values locked from golden_cases.json / 1ddd43e) ----------------
+add("MNB:clk0-10MHz",                   [] { init0(); sf(10000000 * M, 0); });
+add("MNB:clk0-14p07MHz",                [] { init0(); sf(14070000 * M, 0); });
+add("MNB:clk0-100MHz",                  [] { init0(); sf(100000000 * M, 0); });
+add("MNB:clk0-112p5MHz",                [] { init0(); sf(112500000 * M, 0); });
+add("MNB:clk0-150MHz-divby4",           [] { init0(); sf(150000000 * M, 0); });
+add("MNB:clk0-200MHz-divby4",           [] { init0(); sf(200000000 * M, 0); });
+add("MNB:clk3-200MHz-divby4",           [] { init0(); sf(200000000 * M, 3); });
+add("MNB:clk0-4kHz",                    [] { init0(); sf(4000 * M, 0); });
+add("MNB:clk2-5kHz",                    [] { init0(); sf(5000 * M, 2); });
+add("MNB:clk0-512kHz",                  [] { init0(); sf(512000 * M, 0); });
+add("MNB:clk6-23MHz",                   [] { init0(); sf(23000000 * M, 6); });
+add("MNB:clk7-87p4-after-clk6",         [] { init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); });
+add("MNB:clk7-reject-12p345678",        [] { init0(); sf(23000000 * M, 6); sf(12345678 * M, 7); });
+add("MNB:clk7-reject-odd-ratio",        [] { init0(); sf(23000000 * M, 6); sf(874000000 / 19 * M, 7); });
+add("MNB:clk6-100kHz-R6",               [] { init0(); sf(100000 * M, 6); });
+add("MNB:clk7-50kHz-R7",                [] { init0(); sf(50000 * M, 7); });
+add("MNB:clk6-150MHz-clamp",            [] { init0(); sf(150000000 * M, 6); });
+add("MNB:manual-clk1-175-700-divby4",   [] { init0(); mssrc(1, 1); sfm(175000000 * M, 700000000 * M, 1); });
+add("MNB:manual-clk0-14-800-parity",    [] { init0(); sfm(14000000 * M, 800000000 * M, 0); });
+add("MNB:clk1-pllb-14MHz",              [] { init0(); mssrc(1, 1); sf(14000000 * M, 1); });
+add("MNB:vcxo-876-40ppm",               [] { init0(); svcxo(876000000 * M, 40); });
+add("MNB:pll-assign-after-reset",       [] { init0(); });
+add("MNB:clk7-pll-assignment-lock",     [] { init0(); sf(87400000 * M, 7); });
+add("MNB:set_ms-byte2-rmw-5kHz",        [] { init0(); wr_(44, 0x80); sf(5000 * M, 0); });
+add("MNB:divby4-exit-reset-155-96",     [] { init0(); sf(155000000 * M, 0); sf(96000000 * M, 0); });
+add("MNB:divby4-exit-reset-156-80",     [] { init0(); sf(80000000 * M, 0); sf(156000000 * M, 0); sf(80000000 * M, 0); });
+add("MNB:low-clock-moves-155-clk0-99-clk2", [] { init0(); sf(155000000 * M, 0); sf(99000000 * M, 2); });
+add("MNB:both-plls-held-return-code",   [] { init0(); sf(155000000 * M, 0); mssrc(1, 1); sf(160000000 * M, 1); sf(99000000 * M, 2); });
+add("MNB:phase-clk0-mask",              [] { init0(); phase_(0, 0xFF); });
+add("MNB:phase-clk5",                   [] { init0(); phase_(5, 0x2A); });
+add("MNB:setint-clk0",                  [] { init0(); setint_(0, 1); });
+add("MNB:xtal-6pF",                     [] { init_(SI5351_CRYSTAL_LOAD_6PF, 0, 0); });
+add("MNB:xtal-8pF",                     [] { init_(SI5351_CRYSTAL_LOAD_8PF, 0, 0); });
+add("MNB:xtal-10pF",                    [] { init_(SI5351_CRYSTAL_LOAD_10PF, 0, 0); });
+add("MNB:clkin-div4-clean",             [] { init0(); reff(80000000, 1); pllin(0, 1); });
+add("MNB:ref-27MHz",                    [] { init_(L8, 27000000, 0); });
+add("MNB:corr-100000-14MHz",            [] { init_(L8, 0, 100000); sf(14000000 * M, 0); });
+add("MNB:clk0-0Hz",                     [] { init0(); sf(0, 0); });
diff --git a/tests/regression/v231/test_v231.py b/tests/regression/v231/test_v231.py
new file mode 100644
index 0000000..37c061f
--- /dev/null
+++ b/tests/regression/v231/test_v231.py
@@ -0,0 +1,448 @@
+#!/usr/bin/env python3
+"""Si5351Arduino v2.3.1 acceptance tests + must-not-break locks.
+
+Input: JSONL from the C++ runner (acceptance.cpp + scenarios_v231.inc), built against
+the real library source, e.g. master 1ddd43e  ->  logs/acc_master.jsonl.
+
+  python3 test_v231.py logs/acc_master.jsonl                 # report; exit 0 iff all MUST-NOT-BREAK pass
+  python3 test_v231.py logs/acc_master.jsonl --expect-master # also require every ACCEPTANCE test to FAIL (1ddd43e state)
+  python3 test_v231.py logs/acc_fixed.jsonl --require-fixed  # require every ACCEPTANCE test to PASS (the v2.3.1 gate)
+  python3 test_v231.py logs/acc_master.jsonl --write-golden  # (re)write v231_acceptance.json + must_not_break.json
+
+Expected values are what AN619 / the datasheet require (citations to ref/AN619.txt and
+ref/datasheet.txt line numbers). Where the correct policy is debatable, the test asserts only
+the policy-neutral spec invariants and accepts any of the listed options.
+"""
+import json, re, sys
+from fractions import Fraction
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+GOLDEN67 = HERE.parent / "golden_cases.json"
+XTAL = 25_000_000
+CLKOUT67_MIN = (600_000_000 // 254) // 128          # 18454 Hz, library's own SI5351_CLKOUT67_MIN_FREQ
+
+# ---------------------------------------------------------------- decoding helpers
+def calls(run):
+    """Split the transcript into [(call_text, [events])]."""
+    out = [("<pre>", [])]
+    for e in run["tx"]:
+        if e.startswith("CALL "): out.append((e[5:], []))
+        else: out[-1][1].append(e)
+    return out
+
+def writes(events):
+    """[(reg, value)] for every byte written, bulk writes expanded."""
+    w = []
+    for e in events:
+        m = re.match(r"W a=60 r=(\d+) n=\d+ \[([0-9A-F ]+)\]", e)
+        if m:
+            base = int(m.group(1))
+            for i, h in enumerate(m.group(2).split()): w.append(((base + i) & 0xFF, int(h, 16)))
+    return w
+
+def all_writes(run): return writes(run["tx"])
+def last_call_writes(run, prefix):
+    cs = [c for c in calls(run) if c[0].startswith(prefix)]
+    return writes(cs[-1][1]) if cs else []
+def last_call_ret(run, name):
+    r = [x for x in run["rets"] if x.startswith(name + "=")]
+    return int(r[-1].split("=")[1]) if r else None
+
+def block_writes(run, base):
+    """8-byte parameter blocks written as one bulk write at `base`."""
+    out = []
+    for e in run["tx"]:
+        m = re.match(r"W a=60 r=(\d+) n=8 \[([0-9A-F ]+)\]", e)
+        if m and int(m.group(1)) == base: out.append([int(h, 16) for h in m.group(2).split()])
+    return out
+
+def p123(b):
+    p1 = ((b[2] & 3) << 16) | (b[3] << 8) | b[4]
+    p2 = ((b[5] & 0x0F) << 16) | (b[6] << 8) | b[7]
+    p3 = ((b[5] >> 4) << 16) | (b[0] << 8) | b[1]
+    return p1, p2, p3
+
+def ratio(b):
+    """a + b/c from an AN619 P1/P2/P3 block (AN619 sec 3.2 / 4.1.2 encodings)."""
+    p1, p2, p3 = p123(b)
+    if p3 == 0: return None
+    return (Fraction(p1 + 512) + Fraction(p2, p3)) / 128
+
+def vco(regs, base):
+    r = ratio(regs[base:base + 8])
+    return None if r is None else XTAL * r
+
+def ms67_out(regs, clk):
+    """CLKx out for CLK6/7 = fVCO_B / (MSx_P1 * R)  (AN619 Reg 90/91/92)."""
+    p1 = regs[90 + clk - 6]
+    rsh = (regs[92] & 7) if clk == 6 else ((regs[92] >> 4) & 7)
+    v = vco(regs, 34)
+    return None if (p1 == 0 or v is None) else v / (p1 * (1 << rsh))
+
+def ms05_ratio(regs, clk):
+    b = regs[42 + 8 * clk: 50 + 8 * clk]
+    if (b[2] >> 2) & 3 == 3: return Fraction(4)        # MSx_DIVBY4 = 11b
+    return ratio(b)
+
+def ms05_out(regs, clk):
+    src = 34 if regs[16 + clk] & 0x20 else 26
+    v, r = vco(regs, src), ms05_ratio(regs, clk)
+    rsh = (regs[44 + 8 * clk] >> 4) & 7
+    return None if (v is None or not r) else v / (r * (1 << rsh))
+
+def valid_ms05_ratio(r):  # AN619 sec 2.1.1 item 1 (AN619.txt:58), sec 4.1.2 (AN619.txt:235)
+    return r in (4, 6, 8) or (Fraction(8) < r <= 2048 and r >= 8 + Fraction(1, 1048575))
+
+def valid_ms67(p1):       # AN619.txt:74, :247, Reg 90/91 (AN619.txt:2696-2715)
+    return 6 <= p1 <= 254 and p1 % 2 == 0
+
+def mhz(x): return None if x is None else round(float(x) / 1e6, 6)
+
+# ---------------------------------------------------------------- acceptance tests
+# each check(run_by_pattern) -> list of (ok, what, observed, expected)
+def t_dev03(rp):
+    res = []
+    for pat, run in rp.items():
+        if run["crash"]: res.append((False, f"[p{pat}] no crash", run["crash"], "no crash")); continue
+        bad = [v for (r, v) in all_writes(run) if r == 90 and not valid_ms67(v)
+               and any(c[0].startswith("set_freq(") for c in calls(run))]
+        sf_w = [v for (r, v) in last_call_writes(run, "set_freq(") if r == 90]
+        res.append((all(valid_ms67(v) for v in sf_w), f"[p{pat}] every reg90 write by set_freq is an even integer 6..254",
+                     [f"0x{v:02X}" for v in sf_w], "even 6..254 (AN619 Reg 90, AN619.txt:2696)"))
+        pb = run["state"]["pllb_freq"] / 100
+        res.append((600e6 <= pb <= 900e6, f"[p{pat}] stored pllb_freq within VCO 600..900 MHz", f"{pb/1e6:g} MHz", "600..900 MHz (AN619.txt:37)"))
+        ret = last_call_ret(run, "set_freq"); f6 = run["state"]["clk_freq"][6] / 100
+        out = ms67_out(run["regs"], 6)
+        rejected = ret == 1 and f6 == 0 and not sf_w
+        clamped = ret == 0 and out is not None and float(out) >= CLKOUT67_MIN - 0.5 and f6 >= CLKOUT67_MIN
+        res.append((rejected or clamped, f"[p{pat}] either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN {CLKOUT67_MIN} Hz",
+                     f"ret={ret} clk_freq[6]={f6:g} Hz realized={None if out is None else round(float(out),3)} Hz", "reject or clamp>=18454 Hz (DEBATABLE D1)"))
+    return res
+
+def t_dev15(clk):
+    def f(rp):
+        res = []
+        for pat, run in rp.items():
+            v = run["regs"][90 + clk - 6]
+            res.append((v == 0x0A, f"[p{pat}] reg{90+clk-6} (MS{clk}_P1)", f"0x{v:02X}", "0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10)"))
+            out = ms67_out(run["regs"], clk)
+            res.append((out is not None and abs(float(out) - 87.4e6) < 1, f"[p{pat}] realized CLK{clk}", f"{mhz(out)} MHz", "87.4 MHz"))
+        return res
+    return f
+
+def t_dev14(clks):
+    def f(rp):
+        res = []
+        for pat, run in rp.items():
+            r3 = run["regs"][3]
+            for c in clks:
+                res.append(((r3 >> c) & 1 == 0, f"[p{pat}] reg3 CLK{c}_OEB after set_freq", (r3 >> c) & 1,
+                            "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"))
+        return res
+    return f
+
+def t_uninit(rp):
+    res = []
+    for pat, run in rp.items():
+        ret = last_call_ret(run, "set_freq")
+        w91 = [v for (r, v) in last_call_writes(run, "set_freq(100000000,CLK7)") if r == 91]
+        res.append((ret == 1, f"[p{pat}] set_freq(1 MHz, CLK7) return", ret, "1: 874 MHz/1 MHz = 874 = 2x437, no even MS7 6..254 x R=2^k exists (AN619.txt:74, Reg 92 R7)"))
+        res.append((not w91, f"[p{pat}] no write to reg 91 (uninitialised ms_reg.p1)", [f"0x{v:02X}" for v in w91], "no write"))
+        res.append((run["state"]["clk_freq"][7] == 0, f"[p{pat}] clk_freq[7] unchanged", run["state"]["clk_freq"][7] / 100, 0))
+    return res
+
+def t_div0(clk):
+    def f(rp):
+        res = []
+        for pat, run in rp.items():
+            res.append((run["crash"] is None, f"[p{pat}] set_freq(0, CLK{clk}) with peer set does not crash", run["crash"] or "no crash", "no crash (no '% 0')"))
+            if run["crash"] is None:
+                w = [v for (r, v) in last_call_writes(run, "set_freq(0,") if r == 90 + clk - 6]
+                res.append((all(valid_ms67(v) for v in w), f"[p{pat}] any reg{90+clk-6} write is valid", w, "even 6..254 or none (DEBATABLE D2 for semantics)"))
+        return res
+    return f
+
+def t_fmax(rp):
+    res = []
+    for pat, run in rp.items():
+        out = ms05_out(run["regs"], 0); f0 = run["state"]["clk_freq"][0] / 100
+        ret = last_call_ret(run, "set_freq_manual" if any(x.startswith("set_freq_manual") for x in run["rets"]) else "set_freq")
+        rejected = ret == 1 and not block_writes(run, 42)
+        res.append((rejected or (out is not None and out <= 200e6), f"[p{pat}] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+                    f"ret={ret} realized={mhz(out)} MHz", "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"))
+        res.append((f0 <= 200e6, f"[p{pat}] stored clk_freq[0] <= 200 MHz", f"{f0/1e6:g} MHz", "<= 200 MHz"))
+    return res
+
+def t_msratio(rp):
+    res = []
+    for pat, run in rp.items():
+        ret = last_call_ret(run, "set_freq_manual")
+        ms_w = [w for w in block_writes(run, 42)]
+        r = ms05_ratio(run["regs"], 0)
+        ok = (ret != 0 and len(ms_w) == 0) or (r is not None and valid_ms05_ratio(r))
+        res.append((ok, f"[p{pat}] MS0 ratio valid (or call rejected without writing MS0)",
+                    f"ret={ret} ratio={None if r is None else format(float(r), '.6g')}", "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"))
+    return res
+
+def t_phase(reg):
+    def f(rp):
+        return [((reg not in [r for r, _ in all_writes(run)]), f"[p{pat}] no write to reserved reg {reg}",
+                 [v for r, v in all_writes(run) if r == reg], "none (AN619.txt:582 'Reg 171-176 Reserved')") for pat, run in rp.items()]
+    return f
+
+def t_setint(reg):
+    def f(rp):
+        res = []
+        for pat, run in rp.items():
+            before = [v for r, v in writes(next(c for c in calls(run) if c[0].startswith("set_correction"))[1]) if r == reg]
+            pre = next((v for (r, v) in reversed(writes([e for c in calls(run) if not c[0].startswith("set_int") for e in c[1]])) if r == reg), None)
+            v = run["regs"][reg]
+            res.append(((v & 0x40) == ((pre or 0) & 0x40), f"[p{pat}] reg{reg} bit6 (FB{'A' if reg==22 else 'B'}_INT) unchanged by set_int(CLK{reg-16})",
+                        f"0x{v:02X} (before 0x{(pre or 0):02X})", f"bit6 unchanged: FB{'A' if reg==22 else 'B'}_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit"))
+        return res
+    return f
+
+def t_clkindiv(rp):
+    res = []
+    for pat, run in rp.items():
+        v = run["regs"][15]
+        res.append(((v >> 6) == 0b10, f"[p{pat}] reg15 CLKIN_DIV[1:0] after 80 MHz CLKIN", f"{v>>6:02b}b (reg15=0x{v:02X})", "10b = /4 (AN619.txt:834-840; 80 MHz needs /4 for 10-40 MHz, AN619.txt:94)"))
+    return res
+
+def t_xtal0(rp):
+    res = []
+    for pat, run in rp.items():
+        v = run["regs"][183]
+        res.append(((v >> 6) != 0 and (v & 0x3F) == 0b010010, f"[p{pat}] reg183", f"0x{v:02X} (XTAL_CL={v>>6:02b}b)",
+                    "XTAL_CL != 00b, bits5:0 = 010010b (AN619.txt:3134-3141; DEBATABLE D5 which value)"))
+    return res
+
+def t_vcxo(rp, ref_regs):
+    res = []
+    for pat, run in rp.items():
+        b = run["regs"][34:42]; p1, p2, p3 = p123(b); v = vco(run["regs"], 34)
+        res.append((p3 == 1_000_000, f"[p{pat}] MSNB c (P3)", p3, "1000000 (AN619.txt:418 'c ... fixed to 10^6')"))
+        res.append((v is not None and abs(float(v) - 876e6) < 1, f"[p{pat}] PLLB VCO", f"{mhz(v)} MHz", "876 MHz (set_vcxo value preserved)"))
+        res.append((b == ref_regs, f"[p{pat}] PLLB regs 34..41 == set_vcxo() result", b, ref_regs))
+    return res
+
+def t_ref5(rp):
+    res = []
+    for pat, run in rp.items():
+        bad = []
+        for base in (26, 34):
+            for blk in block_writes(run, base):
+                r = ratio(blk)
+                if r is None or not (15 <= r <= 90): bad.append((base, None if r is None else float(r)))
+        res.append((not bad, f"[p{pat}] every PLLA/PLLB feedback block written has a+b/c in 15..90", bad or "all valid",
+                    "15..90 (AN619.txt:116; DEBATABLE D6 for the 5 MHz policy)"))
+    return res
+
+# id -> (item, scenario, title, checker, debatable-id or None)
+ACCEPT = [
+    ("A01", "1 DEV-03", "V231:DEV03-clk6-10kHz", "set_freq(10 kHz, CLK6): reg90 must not be 0x00, PLLB must stay in 600-900 MHz", t_dev03, "D1"),
+    ("A02", "4 CLK67 clamp", "V231:CLK67MIN-clk6-15kHz-clamp", "CLK6/7 lower clamp must use CLKOUT67_MIN (15 kHz request)", t_dev03, "D1"),
+    ("A03", "1 DEV-15", "V231:DEV15-manual-clk7-87p4-874", "set_freq_manual(87.4 MHz, 874 MHz, CLK7) -> reg91 = 0x0A", t_dev15(7), None),
+    ("A04", "1 DEV-15", "V231:DEV15-manual-clk6-87p4-874", "set_freq_manual(87.4 MHz, 874 MHz, CLK6) -> reg90 = 0x0A", t_dev15(6), None),
+    ("A05", "2 DEV-14", "V231:DEV14-clk6-23MHz-enable", "set_freq(CLK6) enables CLK6 (reg3 bit6 = 0)", t_dev14([6]), None),
+    ("A06", "2 DEV-14", "V231:DEV14-clk7-87p4-after-clk6", "set_freq(CLK6) then set_freq(CLK7) enables both", t_dev14([6, 7]), None),
+    ("A07", "2 DEV-14", "V231:DEV14-clk7-first-23MHz", "set_freq(CLK7) as first 6/7 output enables CLK7", t_dev14([7]), None),
+    ("A08", "4 uninit", "V231:UNINIT-clk7-1MHz-peer-fail", "CLK7 peer accepted but multisynth67_calc fails: must return 1, no reg91 write", t_uninit, None),
+    ("A09", "4 div0", "V231:DIV0-clk7-zero-with-peer", "set_freq(0, CLK7) with CLK6 set must not divide by zero", t_div0(7), "D2"),
+    ("A10", "4 div0", "V231:DIV0-clk6-zero-with-peer", "set_freq(0, CLK6) with CLK7 set must not divide by zero", t_div0(6), "D2"),
+    ("A11", "4 fmax", "V231:FMAX-clk0-210MHz", "set_freq(210 MHz, CLK0) must not output > 200 MHz", t_fmax, "D3"),
+    ("A12", "4 fmax", "V231:FMAX-clk0-225MHz", "set_freq(225 MHz, CLK0) must not output > 200 MHz", t_fmax, "D3"),
+    ("A13", "4 fmax", "V231:FMAX-manual-clk0-225MHz-900", "set_freq_manual(225 MHz, 900 MHz, CLK0) must not output > 200 MHz", t_fmax, "D3"),
+    ("A14", "4 ms ratio", "V231:MSRATIO-manual-140-700-r5", "set_freq_manual(140 MHz, 700 MHz): ratio 5 illegal", t_msratio, "D4"),
+    ("A15", "4 ms ratio", "V231:MSRATIO-manual-90-600-r6p67", "set_freq_manual(90 MHz, 600 MHz): ratio 6.667 illegal", t_msratio, "D4"),
+    ("A16", "4 ms ratio", "V231:MSRATIO-manual-100-700-r7", "set_freq_manual(100 MHz, 700 MHz): ratio 7 illegal", t_msratio, "D4"),
+    ("A17", "4 phase", "V231:PHASE-clk6-reg171", "set_phase(CLK6) must not write reserved reg 171", t_phase(171), None),
+    ("A18", "4 phase", "V231:PHASE-clk7-reg172", "set_phase(CLK7) must not write reserved reg 172", t_phase(172), None),
+    ("A19", "4 set_int", "V231:SETINT-clk6-fba-int", "set_int(CLK6) must not set FBA_INT (PLLA fractional after correction)", t_setint(22), None),
+    ("A20", "4 set_int", "V231:SETINT-clk7-fbb-int", "set_int(CLK7) must not set FBB_INT", t_setint(23), None),
+    ("A21", "4 clkin div", "V231:CLKINDIV-50-then-80MHz", "set_pll_input after CLKIN 50->80 MHz: CLKIN_DIV = /4, not OR'd /8", t_clkindiv, None),
+    ("A22", "4 0pF", "V231:XTAL-0PF-reserved", "init(CRYSTAL_LOAD_0PF) must not write XTAL_CL = 00b", t_xtal0, "D5"),
+    ("A23", "4 vcxo", "V231:VCXO-c-after-set_correction", "set_vcxo(876 MHz) then set_correction(0): MSNB c stays 1e6, VCO 876 MHz", None, None),
+    ("A24", "4 vcxo", "V231:VCXO-c-after-set_pll_input", "set_vcxo(876 MHz) then set_pll_input(PLLA, XO): MSNB c stays 1e6", None, None),
+    ("A25", "4 DEV-13", "V231:DEV13-ref-5MHz", "init(.., 5 MHz ref): no feedback ratio outside 15..90 (master writes 160)", t_ref5, "D6"),
+]
+
+DEBATABLE = {
+    "D1": {"topic": "set_freq(f < 18.454 kHz) on CLK6/7 (e.g. 10 kHz, 15 kHz)",
+           "facts": "Lowest CLK6/7 output = 600 MHz / 254 / 128 = 18454 Hz (MS6/7 even 6..254, R<=128, VCO>=600 MHz). 10 kHz is unreachable.",
+           "options": ["(a) reject: return 1, write nothing, keep clk_freq[clk] (matches CLK7 non-integer reject)",
+                       "(b) clamp to SI5351_CLKOUT67_MIN_FREQ (18454 Hz -> MS 254, R 128, VCO 600 MHz) and return 0 (matches CLK0-5 clamp style)",
+                       "(c) clamp and return a distinct non-zero code"],
+           "test_accepts": "(a) or (b)/(c) as long as reg90 is even 6..254, pllb_freq in 600..900 MHz, output >= 18454 Hz"},
+    "D2": {"topic": "set_freq(0, CLK6/7)",
+           "facts": "freq 0 reaches pllb_freq % freq (SIGFPE). Without a peer it reaches multisynth67_calc and writes MS6_P1 = 0. CLK0-5 set_freq(0) currently clamps to 500 kHz MS and enables the output (MNB-INFO only, not locked).",
+           "options": ["(a) return 1, no writes", "(b) treat 0 as 'disable output' (output_enable(clk,0), clk_freq=0), return 0", "(c) same as CLK0-5 current behavior"],
+           "test_accepts": "any, as long as there is no crash and no invalid reg90/91 value"},
+    "D3": {"topic": "CLK0-5 request > 200 MHz (210, 225 MHz)",
+           "facts": "SI5351_MULTISYNTH_MAX_FREQ = 225 MHz; datasheet/AN619 max output is 200 MHz.",
+           "options": ["(a) clamp to 200 MHz (DIVBY4, PLL 800 MHz, a=32) and return 0", "(b) reject with return 1 and no writes"],
+           "test_accepts": "either; asserts realized <= 200 MHz and stored clk_freq <= 200 MHz"},
+    "D4": {"topic": "set_freq_manual with an illegal MS ratio (5, 6.667, 7)",
+           "facts": "AN619 valid ratios: 4, 6, 8, (8+1/1048575 .. 2048]. set_freq_manual's contract is 'track settings yourself'.",
+           "options": ["(a) return 1 without writing MS (keep PLL write?)", "(b) round to nearest legal ratio (6 or 8) and return the realized-freq error some other way",
+                       "(c) keep writing but return non-zero"],
+           "test_accepts": "(a) with no MS0 block written, or any written MS0 ratio that is legal. NOTE: master also writes the PLL before validating; whether a rejected call may still change the PLL is part of this decision"},
+    "D5": {"topic": "init(SI5351_CRYSTAL_LOAD_0PF)",
+           "facts": "XTAL_CL=00b is 'Reserved. Do not select this option.' (AN619 Reg 183). Reset default is 11b (10 pF).",
+           "options": ["(a) map 0PF to 6 pF (01b, smallest legal, closest to the request)", "(b) leave XTAL_CL at default 10 pF (11b)", "(c) remove/deprecate the SI5351_CRYSTAL_LOAD_0PF constant (API change)"],
+           "test_accepts": "any XTAL_CL != 00b with bits 5:0 = 010010b"},
+    "D6": {"topic": "Reference below 10 MHz (5 MHz XO/CLKIN)",
+           "facts": "PLL input range 10-40 MHz (AN619.txt:94); XTAL 25/27 MHz (DS). With 5 MHz, VCO 600 MHz needs ratio 120 > 90: no legal configuration exists.",
+           "options": ["(a) init() returns false / set_ref_freq rejects < 10 MHz", "(b) clamp feedback a to 90 (recompute a after the clamp) -> VCO 450 MHz, still below VCO_MIN",
+                       "(c) accept but never write an out-of-range feedback block"],
+           "test_accepts": "any policy where no PLLA/PLLB block with ratio outside 15..90 is written. (b) passes this test but leaves the VCO at 450 MHz (out of spec): flag if chosen"},
+}
+
+# ---------------------------------------------------------------- must-not-break
+MNB_MAP = {   # scenario -> (golden id in golden_cases.json or None, notes)
+    "MNB:clk0-10MHz": "P0-clk0-common-2-10MHz", "MNB:clk0-14p07MHz": "P0-clk0-fractional-MS-14p07MHz",
+    "MNB:clk0-100MHz": "F-clk0-100MHz-share-max-boundary", "MNB:clk0-112p5MHz": "S-boundary-112p5MHz-ratio8",
+    "MNB:clk0-150MHz-divby4": "P0-clk0-DIVBY4-boundary-150MHz", "MNB:clk0-200MHz-divby4": "P0-clk0-DIVBY4-200MHz",
+    "MNB:clk3-200MHz-divby4": "S-divby4-block-clk3-200MHz", "MNB:clk0-4kHz": "F-clk0-4kHz-library-min",
+    "MNB:clk2-5kHz": "S-rdiv-placement-clk2-5kHz", "MNB:clk0-512kHz": "P0-rdiv-1-512kHz-boundary",
+    "MNB:clk6-23MHz": "P0-clk6-23MHz", "MNB:clk7-87p4-after-clk6": "P0-clk7-874MHz-even-div-of-clk6-pll",
+    "MNB:clk7-reject-12p345678": "P0-clk7-reject-noninteger-12p345678MHz", "MNB:clk7-reject-odd-ratio": None,
+    "MNB:clk6-100kHz-R6": "S-clk6-R6div-100kHz", "MNB:clk7-50kHz-R7": "S-clk7-R7div-50kHz",
+    "MNB:clk6-150MHz-clamp": "S-clk6-150MHz-upper-clamp", "MNB:manual-clk1-175-700-divby4": "P0-manual-DIVBY4-175MHz-pll700",
+    "MNB:manual-clk0-14-800-parity": "P1-parity-set_freq-vs-manual-14MHz-pll800", "MNB:clk1-pllb-14MHz": "P0-clk1-PLLB-14MHz",
+    "MNB:vcxo-876-40ppm": "P0-vcxo-876MHz-40ppm", "MNB:pll-assign-after-reset": "M-clk7-pllb-assignment",
+    "MNB:clk7-pll-assignment-lock": None, "MNB:set_ms-byte2-rmw-5kHz": "M-set-ms-byte2-rmw",
+    "MNB:divby4-exit-reset-155-96": None, "MNB:divby4-exit-reset-156-80": None, "MNB:low-clock-moves-155-clk0-99-clk2": None,
+    "MNB:phase-clk0-mask": "S-phase-clk0-mask", "MNB:phase-clk5": None, "MNB:setint-clk0": "A-set_int-clk0-ms-int",
+    "MNB:xtal-6pF": "S-xtal-load-6-8-10pF", "MNB:xtal-8pF": "A-init-crystal-load-8pF", "MNB:xtal-10pF": "S-xtal-load-6-8-10pF",
+    "MNB:clkin-div4-clean": "A-set_pll_input-clkin-div4-clean", "MNB:ref-27MHz": "A-ref27MHz-set_pll-fixed",
+    "MNB:corr-100000-14MHz": "P0-corr-100000-14MHz-existing-pll",
+}
+INFO_ONLY = {"MNB:both-plls-held-return-code": "item 3 deferred: return codes in both-PLLs-held / other-PLL-too-low cases are NOT locked here",
+             "MNB:clk0-0Hz": "set_freq(0) on CLK0-5 recorded only (see D2)"}
+# registers a v2.3.1 fix is ALLOWED to change in a MNB scenario
+ALLOWED_CHANGE = {"MNB:clk6-23MHz": {"reg3.6"}, "MNB:clk7-87p4-after-clk6": {"reg3.6", "reg3.7"}, "MNB:clk7-reject-12p345678": {"reg3.6"},
+                  "MNB:clk7-reject-odd-ratio": {"reg3.6"}, "MNB:clk6-100kHz-R6": {"reg3.6"}, "MNB:clk7-50kHz-R7": {"reg3.7"},
+                  "MNB:clk6-150MHz-clamp": {"reg3.6"}, "MNB:clk7-pll-assignment-lock": {"reg3.7"}}
+# object-state fields a v2.3.1 fix is ALLOWED to change (bug component, not behavior to keep)
+ALLOWED_STATE = {"MNB:vcxo-876-40ppm": {"pllb_freq"}}   # DEV-08: set_vcxo() leaves pllb_freq at 800 MHz although PLLB runs at 876 MHz
+LOCK_REGS = [3, 15] + list(range(16, 24)) + list(range(26, 50)) + list(range(50, 90, 8)) + list(range(42, 90)) + [90, 91, 92, 162, 163, 164] + list(range(165, 171)) + [183]
+LOCK_REGS = sorted(set(LOCK_REGS))
+
+def golden_checks(g, run):
+    """lib_* register expectations from golden_cases.json (the v2.2.0 regression lock)."""
+    regs, out = run["regs"], []
+    for k, v in g.items():
+        if k in ("lib_plla_regs", "lib_pllb_regs", "lib_pll_regs", "lib_ms_regs", "lib_ms67_regs", "lib_clk_ctrl", "lib_vcxo_regs"):
+            for reg, val in v.items(): out.append((int(reg), val))
+        elif k == "lib_reg92": out.append((92, v))
+        elif k == "lib_reg3_after": out.append((3, v))
+        elif k == "lib_write": out.append(("write", v["reg"], v["value"]))
+    return out
+
+def run_mnb(runs, lock):
+    res = []
+    gold = {c["id"]: c for c in json.loads(GOLDEN67.read_text())["cases"]} if GOLDEN67.exists() else {}
+    for sid, gid in MNB_MAP.items():
+        allowed = ALLOWED_CHANGE.get(sid, set())
+        for pat in (0, 1):
+            run = runs.get((sid, pat))
+            if run is None: res.append((sid, pat, False, "missing run", "", "")); continue
+            if run["crash"]: res.append((sid, pat, False, "crash", run["crash"], "no crash")); continue
+            # 1) golden_cases.json lib_* fields (pattern 0 only: goldens assume a zeroed register file)
+            if gid and pat == 0 and gid in gold:
+                g = gold[gid]
+                if gid == "S-xtal-load-6-8-10pF":
+                    want = {"MNB:xtal-6pF": 82, "MNB:xtal-10pF": 210}[sid]; ok = run["regs"][183] == want
+                    res.append((sid, pat, ok, f"golden {gid} reg183", run["regs"][183], want))
+                elif gid == "A-init-crystal-load-8pF":
+                    res.append((sid, pat, run["regs"][183] == 146, f"golden {gid} reg183", run["regs"][183], 146))
+                for c in golden_checks(g, run):
+                    if c[0] == "write":
+                        got = [v for r, v in all_writes(run) if r == c[1]]
+                        res.append((sid, pat, c[2] in got, f"golden {gid} write reg{c[1]}", got, c[2]))
+                    else:
+                        reg, val = c; got = run["regs"][reg]
+                        if reg == 3 and allowed: mask = ~sum(1 << int(a.split(".")[1]) for a in allowed) & 0xFF; got, val = got & mask, val & mask
+                        res.append((sid, pat, got == val, f"golden {gid} reg{reg}", got, val))
+            # 2) full lock of the 1ddd43e register map for the locked register set + return codes + PLL/clk state
+            L = lock.get(f"{sid}#{pat}")
+            if L:
+                for reg in LOCK_REGS:
+                    got, want = run["regs"][reg], L["regs"][str(reg)]
+                    if reg == 3 and allowed:
+                        mask = ~sum(1 << int(a.split(".")[1]) for a in allowed) & 0xFF; got, want = got & mask, want & mask
+                    if got != want: res.append((sid, pat, False, f"1ddd43e lock reg{reg}", got, want))
+                for k in ("rets",):
+                    res.append((sid, pat, run[k] == L[k], "1ddd43e lock return codes", run[k], L[k]))
+                for k in ("plla_freq", "pllb_freq", "clk_freq", "pll_assignment"):
+                    if k in ALLOWED_STATE.get(sid, ()): continue
+                    res.append((sid, pat, run["state"][k] == L["state"][k], f"1ddd43e lock state.{k}", run["state"][k], L["state"][k]))
+                rst = [v for r, v in all_writes(run) if r == 177]
+                res.append((sid, pat, rst == L["reg177_writes"], "1ddd43e lock PLL-reset (reg177) write sequence", rst, L["reg177_writes"]))
+    return res
+
+def make_lock(runs):
+    lock = {}
+    for (sid, pat), run in runs.items():
+        if sid in MNB_MAP and not run["crash"]:
+            lock[f"{sid}#{pat}"] = {"regs": {str(r): run["regs"][r] for r in LOCK_REGS}, "rets": run["rets"],
+                                   "state": {k: run["state"][k] for k in ("plla_freq", "pllb_freq", "clk_freq", "pll_assignment")},
+                                   "reg177_writes": [v for r, v in all_writes(run) if r == 177]}
+    return lock
+
+def scenario_text():
+    t = {}
+    for l in (HERE / "scenarios_v231.inc").read_text().splitlines():
+        m = re.match(r'add\("([^"]+)",\s*\[\]\s*\{\s*(.*)\s*\}\);', l.strip())
+        if m: t[m.group(1)] = m.group(2)
+    return t
+
+def main():
+    a = sys.argv[1:]
+    path = Path(a[0]) if a and not a[0].startswith("--") else HERE / "logs/acc_master.jsonl"
+    runs = {}
+    for l in open(path):
+        r = json.loads(l); runs[(r["id"], r["pattern"])] = r
+    vcxo_ref = runs[("MNB:vcxo-876-40ppm", 0)]["regs"][34:42]
+    seq = scenario_text()
+    lock_path = HERE / "must_not_break.json"
+    if "--write-golden" in a:
+        lock_path.write_text(json.dumps({"source": f"{path.name} (library 1ddd43e)", "lock_regs": LOCK_REGS, "allowed_change": {k: sorted(v) for k, v in ALLOWED_CHANGE.items()}, "allowed_state_change": {k: sorted(v) for k, v in ALLOWED_STATE.items()},
+                                         "golden_map": MNB_MAP, "info_only": INFO_ONLY, "locks": make_lock(runs)}, indent=1))
+    lock = json.loads(lock_path.read_text())["locks"] if lock_path.exists() else {}
+
+    print(f"== ACCEPTANCE (expected-correct per AN619/datasheet) on {path.name}")
+    acc_rows, n_pass = [], 0
+    for tid, item, sid, title, fn, deb in ACCEPT:
+        rp = {p: runs[(sid, p)] for p in (0, 1)}
+        if fn is None: fn = lambda rp: t_vcxo(rp, vcxo_ref)
+        checks = fn(rp)
+        ok = all(c[0] for c in checks); n_pass += ok
+        print(f"{'PASS' if ok else 'FAIL'} {tid} [{item}] {title}" + (f"  (debatable {deb})" if deb else ""))
+        for c in checks:
+            if not c[0] or ok: print(f"      {'ok ' if c[0] else 'BAD'} {c[1]}: observed={c[2]}  expected={c[3]}")
+        acc_rows.append({"id": tid, "item": item, "scenario": sid, "calls": seq.get(sid), "title": title, "debatable": deb,
+                         "pass": ok, "checks": [{"ok": c[0], "what": c[1], "observed": str(c[2]), "expected": str(c[3])} for c in checks]})
+    print(f"acceptance: {n_pass}/{len(ACCEPT)} pass, {len(ACCEPT)-n_pass} fail")
+
+    mres = run_mnb(runs, lock)
+    bad = [r for r in mres if not r[2]]
+    print(f"\n== MUST-NOT-BREAK: {len(MNB_MAP)} scenarios x 2 patterns, {len(mres)} checks, {len(bad)} failures")
+    for r in bad[:60]: print(f"   FAIL {r[0]} p{r[1]} {r[3]}: observed={r[4]} expected={r[5]}")
+    for sid, why in INFO_ONLY.items():
+        r = runs.get((sid, 0)); print(f"   INFO {sid}: rets={r['rets'] if r else None}  ({why})")
+
+    if "--write-golden" in a:
+        (HERE / "v231_acceptance.json").write_text(json.dumps({
+            "library": "etherkit/Si5351Arduino master 1ddd43e (v2.3.0)", "runner_output": path.name,
+            "refs": {"AN619": "ref/AN619.txt", "datasheet": "ref/datasheet.txt"},
+            "tests": acc_rows, "debatable": DEBATABLE}, indent=1))
+    rc = 1 if bad else 0
+    if "--expect-master" in a and n_pass != 0: print("ERROR: some acceptance tests already pass on this build"); rc = 1
+    if "--require-fixed" in a and n_pass != len(ACCEPT): print("ERROR: acceptance tests still failing"); rc = 1
+    print("\nRESULT:", "OK" if rc == 0 else "NOT OK"); return rc
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/tests/regression/v231/v231_acceptance.json b/tests/regression/v231/v231_acceptance.json
new file mode 100644
index 0000000..c0ece78
--- /dev/null
+++ b/tests/regression/v231/v231_acceptance.json
@@ -0,0 +1,838 @@
+{
+ "library": "etherkit/Si5351Arduino master 1ddd43e (v2.3.0)",
+ "runner_output": "acc_master.jsonl",
+ "refs": {
+  "AN619": "ref/AN619.txt",
+  "datasheet": "ref/datasheet.txt"
+ },
+ "tests": [
+  {
+   "id": "A01",
+   "item": "1 DEV-03",
+   "scenario": "V231:DEV03-clk6-10kHz",
+   "calls": "init0(); sf(10000 * M, 6); ",
+   "title": "set_freq(10 kHz, CLK6): reg90 must not be 0x00, PLLB must stay in 600-900 MHz",
+   "debatable": "D1",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] every reg90 write by set_freq is an even integer 6..254",
+     "observed": "['0x00']",
+     "expected": "even 6..254 (AN619 Reg 90, AN619.txt:2696)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] stored pllb_freq within VCO 600..900 MHz",
+     "observed": "128 MHz",
+     "expected": "600..900 MHz (AN619.txt:37)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz",
+     "observed": "ret=0 clk_freq[6]=4000 Hz realized=None Hz",
+     "expected": "reject or clamp>=18454 Hz (DEBATABLE D1)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] every reg90 write by set_freq is an even integer 6..254",
+     "observed": "['0x00']",
+     "expected": "even 6..254 (AN619 Reg 90, AN619.txt:2696)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] stored pllb_freq within VCO 600..900 MHz",
+     "observed": "128 MHz",
+     "expected": "600..900 MHz (AN619.txt:37)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz",
+     "observed": "ret=0 clk_freq[6]=4000 Hz realized=None Hz",
+     "expected": "reject or clamp>=18454 Hz (DEBATABLE D1)"
+    }
+   ]
+  },
+  {
+   "id": "A02",
+   "item": "4 CLK67 clamp",
+   "scenario": "V231:CLK67MIN-clk6-15kHz-clamp",
+   "calls": "init0(); sf(15000 * M, 6); ",
+   "title": "CLK6/7 lower clamp must use CLKOUT67_MIN (15 kHz request)",
+   "debatable": "D1",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] every reg90 write by set_freq is an even integer 6..254",
+     "observed": "['0x00']",
+     "expected": "even 6..254 (AN619 Reg 90, AN619.txt:2696)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] stored pllb_freq within VCO 600..900 MHz",
+     "observed": "128 MHz",
+     "expected": "600..900 MHz (AN619.txt:37)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz",
+     "observed": "ret=0 clk_freq[6]=4000 Hz realized=None Hz",
+     "expected": "reject or clamp>=18454 Hz (DEBATABLE D1)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] every reg90 write by set_freq is an even integer 6..254",
+     "observed": "['0x00']",
+     "expected": "even 6..254 (AN619 Reg 90, AN619.txt:2696)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] stored pllb_freq within VCO 600..900 MHz",
+     "observed": "128 MHz",
+     "expected": "600..900 MHz (AN619.txt:37)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] either rejected (ret 1, nothing written) or clamped to >= CLKOUT67_MIN 18454 Hz",
+     "observed": "ret=0 clk_freq[6]=4000 Hz realized=None Hz",
+     "expected": "reject or clamp>=18454 Hz (DEBATABLE D1)"
+    }
+   ]
+  },
+  {
+   "id": "A03",
+   "item": "1 DEV-15",
+   "scenario": "V231:DEV15-manual-clk7-87p4-874",
+   "calls": "init0(); sfm(87400000 * M, 874000000 * M, 7); ",
+   "title": "set_freq_manual(87.4 MHz, 874 MHz, CLK7) -> reg91 = 0x0A",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg91 (MS7_P1)",
+     "observed": "0x00",
+     "expected": "0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] realized CLK7",
+     "observed": "None MHz",
+     "expected": "87.4 MHz"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg91 (MS7_P1)",
+     "observed": "0x00",
+     "expected": "0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] realized CLK7",
+     "observed": "None MHz",
+     "expected": "87.4 MHz"
+    }
+   ]
+  },
+  {
+   "id": "A04",
+   "item": "1 DEV-15",
+   "scenario": "V231:DEV15-manual-clk6-87p4-874",
+   "calls": "init0(); sfm(87400000 * M, 874000000 * M, 6); ",
+   "title": "set_freq_manual(87.4 MHz, 874 MHz, CLK6) -> reg90 = 0x0A",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg90 (MS6_P1)",
+     "observed": "0x00",
+     "expected": "0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] realized CLK6",
+     "observed": "None MHz",
+     "expected": "87.4 MHz"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg90 (MS6_P1)",
+     "observed": "0x00",
+     "expected": "0x0A (AN619.txt:247 'set MSx_P1 directly (= divide value)'; 874/87.4 = 10)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] realized CLK6",
+     "observed": "None MHz",
+     "expected": "87.4 MHz"
+    }
+   ]
+  },
+  {
+   "id": "A05",
+   "item": "2 DEV-14",
+   "scenario": "V231:DEV14-clk6-23MHz-enable",
+   "calls": "init0(); sf(23000000 * M, 6); ",
+   "title": "set_freq(CLK6) enables CLK6 (reg3 bit6 = 0)",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg3 CLK6_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg3 CLK6_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    }
+   ]
+  },
+  {
+   "id": "A06",
+   "item": "2 DEV-14",
+   "scenario": "V231:DEV14-clk7-87p4-after-clk6",
+   "calls": "init0(); sf(23000000 * M, 6); sf(87400000 * M, 7); ",
+   "title": "set_freq(CLK6) then set_freq(CLK7) enables both",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg3 CLK6_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] reg3 CLK7_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg3 CLK6_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg3 CLK7_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    }
+   ]
+  },
+  {
+   "id": "A07",
+   "item": "2 DEV-14",
+   "scenario": "V231:DEV14-clk7-first-23MHz",
+   "calls": "init0(); sf(23000000 * M, 7); ",
+   "title": "set_freq(CLK7) as first 6/7 output enables CLK7",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg3 CLK7_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg3 CLK7_OEB after set_freq",
+     "observed": "1",
+     "expected": "0 = enabled (AN619 Reg 3; parity with CLK0-5 first-set enable, si5351.cpp set_freq CLK0-5 branch)"
+    }
+   ]
+  },
+  {
+   "id": "A08",
+   "item": "4 uninit",
+   "scenario": "V231:UNINIT-clk7-1MHz-peer-fail",
+   "calls": "init0(); sf(23000000 * M, 6); sf(1000000 * M, 7); ",
+   "title": "CLK7 peer accepted but multisynth67_calc fails: must return 1, no reg91 write",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] set_freq(1 MHz, CLK7) return",
+     "observed": "0",
+     "expected": "1: 874 MHz/1 MHz = 874 = 2x437, no even MS7 6..254 x R=2^k exists (AN619.txt:74, Reg 92 R7)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] no write to reg 91 (uninitialised ms_reg.p1)",
+     "observed": "['0xFE']",
+     "expected": "no write"
+    },
+    {
+     "ok": false,
+     "what": "[p0] clk_freq[7] unchanged",
+     "observed": "1000000.0",
+     "expected": "0"
+    },
+    {
+     "ok": false,
+     "what": "[p1] set_freq(1 MHz, CLK7) return",
+     "observed": "0",
+     "expected": "1: 874 MHz/1 MHz = 874 = 2x437, no even MS7 6..254 x R=2^k exists (AN619.txt:74, Reg 92 R7)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] no write to reg 91 (uninitialised ms_reg.p1)",
+     "observed": "['0xFE']",
+     "expected": "no write"
+    },
+    {
+     "ok": false,
+     "what": "[p1] clk_freq[7] unchanged",
+     "observed": "1000000.0",
+     "expected": "0"
+    }
+   ]
+  },
+  {
+   "id": "A09",
+   "item": "4 div0",
+   "scenario": "V231:DIV0-clk7-zero-with-peer",
+   "calls": "init0(); sf(23000000 * M, 6); sf(0, 7); ",
+   "title": "set_freq(0, CLK7) with CLK6 set must not divide by zero",
+   "debatable": "D2",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] set_freq(0, CLK7) with peer set does not crash",
+     "observed": "Floating point exception",
+     "expected": "no crash (no '% 0')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] set_freq(0, CLK7) with peer set does not crash",
+     "observed": "Floating point exception",
+     "expected": "no crash (no '% 0')"
+    }
+   ]
+  },
+  {
+   "id": "A10",
+   "item": "4 div0",
+   "scenario": "V231:DIV0-clk6-zero-with-peer",
+   "calls": "init0(); sf(23000000 * M, 7); sf(0, 6); ",
+   "title": "set_freq(0, CLK6) with CLK7 set must not divide by zero",
+   "debatable": "D2",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] set_freq(0, CLK6) with peer set does not crash",
+     "observed": "Floating point exception",
+     "expected": "no crash (no '% 0')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] set_freq(0, CLK6) with peer set does not crash",
+     "observed": "Floating point exception",
+     "expected": "no crash (no '% 0')"
+    }
+   ]
+  },
+  {
+   "id": "A11",
+   "item": "4 fmax",
+   "scenario": "V231:FMAX-clk0-210MHz",
+   "calls": "init0(); sf(210000000 * M, 0); ",
+   "title": "set_freq(210 MHz, CLK0) must not output > 200 MHz",
+   "debatable": "D3",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=210.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] stored clk_freq[0] <= 200 MHz",
+     "observed": "210 MHz",
+     "expected": "<= 200 MHz"
+    },
+    {
+     "ok": false,
+     "what": "[p1] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=210.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] stored clk_freq[0] <= 200 MHz",
+     "observed": "210 MHz",
+     "expected": "<= 200 MHz"
+    }
+   ]
+  },
+  {
+   "id": "A12",
+   "item": "4 fmax",
+   "scenario": "V231:FMAX-clk0-225MHz",
+   "calls": "init0(); sf(225000000 * M, 0); ",
+   "title": "set_freq(225 MHz, CLK0) must not output > 200 MHz",
+   "debatable": "D3",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=225.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] stored clk_freq[0] <= 200 MHz",
+     "observed": "225 MHz",
+     "expected": "<= 200 MHz"
+    },
+    {
+     "ok": false,
+     "what": "[p1] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=225.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] stored clk_freq[0] <= 200 MHz",
+     "observed": "225 MHz",
+     "expected": "<= 200 MHz"
+    }
+   ]
+  },
+  {
+   "id": "A13",
+   "item": "4 fmax",
+   "scenario": "V231:FMAX-manual-clk0-225MHz-900",
+   "calls": "init0(); sfm(225000000 * M, 900000000 * M, 0); ",
+   "title": "set_freq_manual(225 MHz, 900 MHz, CLK0) must not output > 200 MHz",
+   "debatable": "D3",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=225.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] stored clk_freq[0] <= 200 MHz",
+     "observed": "225 MHz",
+     "expected": "<= 200 MHz"
+    },
+    {
+     "ok": false,
+     "what": "[p1] realized CLK0 <= 200 MHz (or rejected: ret 1, MS0 not written)",
+     "observed": "ret=0 realized=225.0 MHz",
+     "expected": "<= 200 MHz (DS p1 / AN619.txt:38; DEBATABLE D3 reject vs clamp)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] stored clk_freq[0] <= 200 MHz",
+     "observed": "225 MHz",
+     "expected": "<= 200 MHz"
+    }
+   ]
+  },
+  {
+   "id": "A14",
+   "item": "4 ms ratio",
+   "scenario": "V231:MSRATIO-manual-140-700-r5",
+   "calls": "init0(); sfm(140000000 * M, 700000000 * M, 0); ",
+   "title": "set_freq_manual(140 MHz, 700 MHz): ratio 5 illegal",
+   "debatable": "D4",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=5",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=5",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    }
+   ]
+  },
+  {
+   "id": "A15",
+   "item": "4 ms ratio",
+   "scenario": "V231:MSRATIO-manual-90-600-r6p67",
+   "calls": "init0(); sfm(90000000 * M, 600000000 * M, 0); ",
+   "title": "set_freq_manual(90 MHz, 600 MHz): ratio 6.667 illegal",
+   "debatable": "D4",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=6.66667",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=6.66667",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    }
+   ]
+  },
+  {
+   "id": "A16",
+   "item": "4 ms ratio",
+   "scenario": "V231:MSRATIO-manual-100-700-r7",
+   "calls": "init0(); sfm(100000000 * M, 700000000 * M, 0); ",
+   "title": "set_freq_manual(100 MHz, 700 MHz): ratio 7 illegal",
+   "debatable": "D4",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=7",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] MS0 ratio valid (or call rejected without writing MS0)",
+     "observed": "ret=0 ratio=7",
+     "expected": "4, 6, 8 or 8+1/1048575..2048 (AN619.txt:58,235; DEBATABLE D4)"
+    }
+   ]
+  },
+  {
+   "id": "A17",
+   "item": "4 phase",
+   "scenario": "V231:PHASE-clk6-reg171",
+   "calls": "init0(); phase_(6, 10); ",
+   "title": "set_phase(CLK6) must not write reserved reg 171",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] no write to reserved reg 171",
+     "observed": "[10]",
+     "expected": "none (AN619.txt:582 'Reg 171-176 Reserved')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] no write to reserved reg 171",
+     "observed": "[10]",
+     "expected": "none (AN619.txt:582 'Reg 171-176 Reserved')"
+    }
+   ]
+  },
+  {
+   "id": "A18",
+   "item": "4 phase",
+   "scenario": "V231:PHASE-clk7-reg172",
+   "calls": "init0(); phase_(7, 10); ",
+   "title": "set_phase(CLK7) must not write reserved reg 172",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] no write to reserved reg 172",
+     "observed": "[10]",
+     "expected": "none (AN619.txt:582 'Reg 171-176 Reserved')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] no write to reserved reg 172",
+     "observed": "[10]",
+     "expected": "none (AN619.txt:582 'Reg 171-176 Reserved')"
+    }
+   ]
+  },
+  {
+   "id": "A19",
+   "item": "4 set_int",
+   "scenario": "V231:SETINT-clk6-fba-int",
+   "calls": "init0(); corr_(100000, 0); setint_(6, 1); ",
+   "title": "set_int(CLK6) must not set FBA_INT (PLLA fractional after correction)",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg22 bit6 (FBA_INT) unchanged by set_int(CLK6)",
+     "observed": "0x6C (before 0x2C)",
+     "expected": "bit6 unchanged: FBA_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg22 bit6 (FBA_INT) unchanged by set_int(CLK6)",
+     "observed": "0x6C (before 0x2C)",
+     "expected": "bit6 unchanged: FBA_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit"
+    }
+   ]
+  },
+  {
+   "id": "A20",
+   "item": "4 set_int",
+   "scenario": "V231:SETINT-clk7-fbb-int",
+   "calls": "init0(); corr_(100000, 0); setint_(7, 1); ",
+   "title": "set_int(CLK7) must not set FBB_INT",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg23 bit6 (FBB_INT) unchanged by set_int(CLK7)",
+     "observed": "0x6C (before 0x2C)",
+     "expected": "bit6 unchanged: FBB_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg23 bit6 (FBB_INT) unchanged by set_int(CLK7)",
+     "observed": "0x6C (before 0x2C)",
+     "expected": "bit6 unchanged: FBB_INT only for even-integer feedback (AN619.txt:138, :1234); MS6/7 have no INT bit"
+    }
+   ]
+  },
+  {
+   "id": "A21",
+   "item": "4 clkin div",
+   "scenario": "V231:CLKINDIV-50-then-80MHz",
+   "calls": "init0(); reff(50000000, 1); pllin(0, 1); reff(80000000, 1); pllin(0, 1); ",
+   "title": "set_pll_input after CLKIN 50->80 MHz: CLKIN_DIV = /4, not OR'd /8",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg15 CLKIN_DIV[1:0] after 80 MHz CLKIN",
+     "observed": "11b (reg15=0xC4)",
+     "expected": "10b = /4 (AN619.txt:834-840; 80 MHz needs /4 for 10-40 MHz, AN619.txt:94)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg15 CLKIN_DIV[1:0] after 80 MHz CLKIN",
+     "observed": "11b (reg15=0xD7)",
+     "expected": "10b = /4 (AN619.txt:834-840; 80 MHz needs /4 for 10-40 MHz, AN619.txt:94)"
+    }
+   ]
+  },
+  {
+   "id": "A22",
+   "item": "4 0pF",
+   "scenario": "V231:XTAL-0PF-reserved",
+   "calls": "init_(SI5351_CRYSTAL_LOAD_0PF, 0, 0); ",
+   "title": "init(CRYSTAL_LOAD_0PF) must not write XTAL_CL = 00b",
+   "debatable": "D5",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] reg183",
+     "observed": "0x12 (XTAL_CL=00b)",
+     "expected": "XTAL_CL != 00b, bits5:0 = 010010b (AN619.txt:3134-3141; DEBATABLE D5 which value)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] reg183",
+     "observed": "0x12 (XTAL_CL=00b)",
+     "expected": "XTAL_CL != 00b, bits5:0 = 010010b (AN619.txt:3134-3141; DEBATABLE D5 which value)"
+    }
+   ]
+  },
+  {
+   "id": "A23",
+   "item": "4 vcxo",
+   "scenario": "V231:VCXO-c-after-set_correction",
+   "calls": "init0(); svcxo(876000000 * M, 40); corr_(0, 0); ",
+   "title": "set_vcxo(876 MHz) then set_correction(0): MSNB c stays 1e6, VCO 876 MHz",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] MSNB c (P3)",
+     "observed": "1",
+     "expected": "1000000 (AN619.txt:418 'c ... fixed to 10^6')"
+    },
+    {
+     "ok": false,
+     "what": "[p0] PLLB VCO",
+     "observed": "800.0 MHz",
+     "expected": "876 MHz (set_vcxo value preserved)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] PLLB regs 34..41 == set_vcxo() result",
+     "observed": "[0, 1, 0, 14, 0, 0, 0, 0]",
+     "expected": "[66, 64, 0, 15, 133, 241, 212, 192]"
+    },
+    {
+     "ok": false,
+     "what": "[p1] MSNB c (P3)",
+     "observed": "1",
+     "expected": "1000000 (AN619.txt:418 'c ... fixed to 10^6')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] PLLB VCO",
+     "observed": "800.0 MHz",
+     "expected": "876 MHz (set_vcxo value preserved)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] PLLB regs 34..41 == set_vcxo() result",
+     "observed": "[0, 1, 0, 14, 0, 0, 0, 0]",
+     "expected": "[66, 64, 0, 15, 133, 241, 212, 192]"
+    }
+   ]
+  },
+  {
+   "id": "A24",
+   "item": "4 vcxo",
+   "scenario": "V231:VCXO-c-after-set_pll_input",
+   "calls": "init0(); svcxo(876000000 * M, 40); pllin(0, 0); ",
+   "title": "set_vcxo(876 MHz) then set_pll_input(PLLA, XO): MSNB c stays 1e6",
+   "debatable": null,
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] MSNB c (P3)",
+     "observed": "1",
+     "expected": "1000000 (AN619.txt:418 'c ... fixed to 10^6')"
+    },
+    {
+     "ok": false,
+     "what": "[p0] PLLB VCO",
+     "observed": "800.0 MHz",
+     "expected": "876 MHz (set_vcxo value preserved)"
+    },
+    {
+     "ok": false,
+     "what": "[p0] PLLB regs 34..41 == set_vcxo() result",
+     "observed": "[0, 1, 0, 14, 0, 0, 0, 0]",
+     "expected": "[66, 64, 0, 15, 133, 241, 212, 192]"
+    },
+    {
+     "ok": false,
+     "what": "[p1] MSNB c (P3)",
+     "observed": "1",
+     "expected": "1000000 (AN619.txt:418 'c ... fixed to 10^6')"
+    },
+    {
+     "ok": false,
+     "what": "[p1] PLLB VCO",
+     "observed": "800.0 MHz",
+     "expected": "876 MHz (set_vcxo value preserved)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] PLLB regs 34..41 == set_vcxo() result",
+     "observed": "[0, 1, 0, 14, 0, 0, 0, 0]",
+     "expected": "[66, 64, 0, 15, 133, 241, 212, 192]"
+    }
+   ]
+  },
+  {
+   "id": "A25",
+   "item": "4 DEV-13",
+   "scenario": "V231:DEV13-ref-5MHz",
+   "calls": "init_(L8, 5000000, 0); ",
+   "title": "init(.., 5 MHz ref): no feedback ratio outside 15..90 (master writes 160)",
+   "debatable": "D6",
+   "pass": false,
+   "checks": [
+    {
+     "ok": false,
+     "what": "[p0] every PLLA/PLLB feedback block written has a+b/c in 15..90",
+     "observed": "[(26, 120.0), (26, 120.0), (26, 160.0), (34, 120.0), (34, 120.0), (34, 160.0)]",
+     "expected": "15..90 (AN619.txt:116; DEBATABLE D6 for the 5 MHz policy)"
+    },
+    {
+     "ok": false,
+     "what": "[p1] every PLLA/PLLB feedback block written has a+b/c in 15..90",
+     "observed": "[(26, 120.0), (26, 120.0), (26, 160.0), (34, 120.0), (34, 120.0), (34, 160.0)]",
+     "expected": "15..90 (AN619.txt:116; DEBATABLE D6 for the 5 MHz policy)"
+    }
+   ]
+  }
+ ],
+ "debatable": {
+  "D1": {
+   "topic": "set_freq(f < 18.454 kHz) on CLK6/7 (e.g. 10 kHz, 15 kHz)",
+   "facts": "Lowest CLK6/7 output = 600 MHz / 254 / 128 = 18454 Hz (MS6/7 even 6..254, R<=128, VCO>=600 MHz). 10 kHz is unreachable.",
+   "options": [
+    "(a) reject: return 1, write nothing, keep clk_freq[clk] (matches CLK7 non-integer reject)",
+    "(b) clamp to SI5351_CLKOUT67_MIN_FREQ (18454 Hz -> MS 254, R 128, VCO 600 MHz) and return 0 (matches CLK0-5 clamp style)",
+    "(c) clamp and return a distinct non-zero code"
+   ],
+   "test_accepts": "(a) or (b)/(c) as long as reg90 is even 6..254, pllb_freq in 600..900 MHz, output >= 18454 Hz"
+  },
+  "D2": {
+   "topic": "set_freq(0, CLK6/7)",
+   "facts": "freq 0 reaches pllb_freq % freq (SIGFPE). Without a peer it reaches multisynth67_calc and writes MS6_P1 = 0. CLK0-5 set_freq(0) currently clamps to 500 kHz MS and enables the output (MNB-INFO only, not locked).",
+   "options": [
+    "(a) return 1, no writes",
+    "(b) treat 0 as 'disable output' (output_enable(clk,0), clk_freq=0), return 0",
+    "(c) same as CLK0-5 current behavior"
+   ],
+   "test_accepts": "any, as long as there is no crash and no invalid reg90/91 value"
+  },
+  "D3": {
+   "topic": "CLK0-5 request > 200 MHz (210, 225 MHz)",
+   "facts": "SI5351_MULTISYNTH_MAX_FREQ = 225 MHz; datasheet/AN619 max output is 200 MHz.",
+   "options": [
+    "(a) clamp to 200 MHz (DIVBY4, PLL 800 MHz, a=32) and return 0",
+    "(b) reject with return 1 and no writes"
+   ],
+   "test_accepts": "either; asserts realized <= 200 MHz and stored clk_freq <= 200 MHz"
+  },
+  "D4": {
+   "topic": "set_freq_manual with an illegal MS ratio (5, 6.667, 7)",
+   "facts": "AN619 valid ratios: 4, 6, 8, (8+1/1048575 .. 2048]. set_freq_manual's contract is 'track settings yourself'.",
+   "options": [
+    "(a) return 1 without writing MS (keep PLL write?)",
+    "(b) round to nearest legal ratio (6 or 8) and return the realized-freq error some other way",
+    "(c) keep writing but return non-zero"
+   ],
+   "test_accepts": "(a) with no MS0 block written, or any written MS0 ratio that is legal. NOTE: master also writes the PLL before validating; whether a rejected call may still change the PLL is part of this decision"
+  },
+  "D5": {
+   "topic": "init(SI5351_CRYSTAL_LOAD_0PF)",
+   "facts": "XTAL_CL=00b is 'Reserved. Do not select this option.' (AN619 Reg 183). Reset default is 11b (10 pF).",
+   "options": [
+    "(a) map 0PF to 6 pF (01b, smallest legal, closest to the request)",
+    "(b) leave XTAL_CL at default 10 pF (11b)",
+    "(c) remove/deprecate the SI5351_CRYSTAL_LOAD_0PF constant (API change)"
+   ],
+   "test_accepts": "any XTAL_CL != 00b with bits 5:0 = 010010b"
+  },
+  "D6": {
+   "topic": "Reference below 10 MHz (5 MHz XO/CLKIN)",
+   "facts": "PLL input range 10-40 MHz (AN619.txt:94); XTAL 25/27 MHz (DS). With 5 MHz, VCO 600 MHz needs ratio 120 > 90: no legal configuration exists.",
+   "options": [
+    "(a) init() returns false / set_ref_freq rejects < 10 MHz",
+    "(b) clamp feedback a to 90 (recompute a after the clamp) -> VCO 450 MHz, still below VCO_MIN",
+    "(c) accept but never write an out-of-range feedback block"
+   ],
+   "test_accepts": "any policy where no PLLA/PLLB block with ratio outside 15..90 is written. (b) passes this test but leaves the VCO at 450 MHz (out of spec): flag if chosen"
+  }
+ }
+}
\ No newline at end of file