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<!DOCTYPE html>
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<H1>Projects List</H1>
<div class="home">
Most of my time these days is spent working on commercial projects. Some of
these are listed at <A HREF="https://www.arasan.com">arasan.com</A>.</P>
<div class="home">
As of May, 2023, I'm also in the middle of generating the
<A HREF="https://github.com/ZipCPU/eth10g">IP for a 10Gb Ethernet switch</A>.
The project is far from complete, but when finished it should also include
<A HREF="https://github.com/ZipCPU/vgasim">HDMI</A>
and <A HREF="https://github.com/ZipCPU/wbsata">SATA</A> controllers in addition
to the <A HREF="/blog/2023/04/08/vpktfifo.html">virtual
packet FIFOs I've written about</A>.
(The <A HREF="https://github.com/ZipCPU/wbsata">SATA</A> controller is
currently a work in progress, as is the GTX transceiver controller for the
10Gb Ethernet portion.) This project may also be a nice place to showcase my
<A HREF="https://github.com/ZipCPU/wbi2c">universal I2C controller</A>--which
has already started its service driving an
<A HREF="https://www.amazon.com/Teyleten-Robot-Display-SSD1306-Raspberry/dp/B08ZY4YBHL/">OLED display</A> and reading from a temperature sensor.
If this is a project you are interested in, you can track my progress
on the <A HREF="https://github.com/ZipCPU/eth10g/blob/master/doc/eth10g-blocks.png">Ethernet
portion here</A>, and on the
<A HREF="https://github.com/ZipCPU/eth10g/blob/master/doc/eth10g-busblocks.png">project in general here</A>.
As of this writing, we're only working on bringing up the first (draft)
circuit board, so there's a lot more to come. Feel free to write me if you
have further inquiries regarding this board.</P>
<div class="home">
I've also built a number of Open Source projects that may be of value to you:
<UL>
<LI><B><A HREF="https://github.com/ZipCPU/zipcpu">The ZipCPU</A></B>
<P>A fully functional, fully pipelined, 32-bit CPU designed for
resource constrained FPGA environments. Includes GCC, Binutils,
and Newlib support. Although designed to be
powerful enough to run Linux, a Linux port has not yet been written.
Many of the projects that follow use this CPU.</P>
<P>Why doesn't the <A HREF="https://github.com/ZipCPU/zipcpu">ZipCPU</A>
support Linux? For two primary reasons. 1) It's still missing a
functional MMU, and 2) it's worked so well on my current projects
that Linux hasn't been my priority.
<P>If you are interested in reading more about the
<A HREF="https://github.com/ZipCPU/zipcpu">ZipCPU</A>, consider
reading
"<A HREF="/zipcpu/2018/01/01/zipcpu-isa.html">A Quick
Introduction to the ZipCPU's Instruction Set</A>",
"<A HREF="/zipcpu/2018/01/31/cpu-build.html">Instructions for
building the GCC-based toolchain</A>", or
"<A HREF="/zipcpu/2023/05/29/zipcpu-3p0.html">Introducing
the ZipCPU v3.0</A>".</P>
<LI><A HREF="about/zipcpu.html">ZipCPU</A> systems: The following are fully
built, full featured systems for which the
<A HREF="about/zipcpu.html">ZipCPU</A> has been placed inside:
<UL>
<LI><B><A HREF="https://github.com/ZipCPU/s6soc">S6SoC</A></B>
<P>This was one of my very first
<A HREF="about/zipcpu.html">ZipCPU</A> projects. It was a successful
demonstration of how the
<A HREF="about/zipcpu.html">ZipCPU</A> could be made to fit on on even
the smallest of FPGA's. Since the last build, the
<A HREF="about/zipcpu.html">ZipCPU</A> has evolved significantly, and
I haven't used the Spartan 6 to revisit the project. The RTL,
therefore, represents the state of the CPU when this project was last
built and known to work on hardware.
<P>This same is true for the other projects that follow. The RTL
in the master branch is the RTL that was used in the last hardware
test or demonstration, and may not have been updated since even though
the <A HREF="about/zipcpu.html">ZipCPU</A> and/or other components have
gone through many updates.
</P>
<LI><B><A HREF="https://github.com/ZipCPU/arrowzip">ArrowZip</A></B>
<P>The <A HREF="/blog/2017/12/16/max1k.html">MAX-1000
was a very inexpensive FPGA board</A> sold by both Arrow and Trenz.
(I'm not sure you can buy it anymore ...) This project places a
<A HREF="/about/zipcpu.html">ZipCPU</A> on this
board. It's also a demonstration of my (formally verified)
<A HREF="https://github.com/ZipCPU/arrowzip/blob/master/rtl/arrowzip/wbsdram.v">Wishbone
SDRAM</A> controller.</P>
<LI><B><A HREF="https://github.com/ZipCPU/openarty">OpenArty</A></B>
<P>Demonstrates both the
<A HREF="/about/zipcpu.html">ZipCPU</A> and
<A HREF="https://github.com/ZipCPU/autofpga">AutoFPGA</A> on a
Digilent Arty A7 board.</P>
<LI><B><A HREF="https://github.com/ZipCPU/zbasic">ZBasic</A></B>
<P>This is a bare bones, minimal <A HREF="/about/zipcpu.html">ZipCPU</A> system. If you wish to build
a <A HREF="/about/zipcpu.html">ZipCPU</A> system and don't know where to start, this may be just
the place. See <A HREF="/zipcpu/2018/02/12/zbasic-intro.html">this post</A> for a discussion on how to get started with ZBasic.</A>
<P>This was also (at one time) the project where I tested out new
<A HREF="/about/zipcpu.html">ZipCPU</A>
and <A HREF="https://github.com/ZipCPU/autofpga">AutoFPGA"</A>
features. However, with the
<A HREF="/zipcpu/2023/05/29/zipcpu-3p0.html">latest
release</A> of the
<A HREF="/about/zipcpu.html">ZipCPU</A>, I may not
need this test ground anymore.</P>
</P>
<LI>My original <A HREF="/about/zipcpu.html">ZipCPU</A> project was built for the Basys3
<P>Sorry, this project doesn't have a cool name. It was my first
FPGA project, and one from before I was working on open source projects.
One unique feature of this one is that I drive the VGA port from the
flash, and so this project can be used to display arbitrary presentation
types of images (i.e. static images) on a VGA screen.
The <A HREF="https://github.com/ZipCPU/vgasim">VGA simulator</A>
from this project has since been
<A HREF="https://github.com/ZipCPU/vgasim">posted on github</A> as
well.</P>
<LI><A HREF="https://github.com/ZipCPU/videozip">VideoZIP</A> is
another system I'm working on. This one, though, is built
entirely via the
<B><A HREF="https://github.com/ZipCPU/autofpga">AutoFPGA</A></B>
program. The goal was (originally) to both receive HDMI signals, and
transmit HDMI signals. As an unfunded project, it's not complete.
However, I have managed to get the HDMI receive function working
(just not the save to memory part), and it seems to be working well.
Curiously, this <em>unfinished</em> project has formed the basis for
many of my commercial projects. This is just a really capable board.
<P>There is also a <A HREF="https://github.com/ZipCPU/videozip/tree/enet/">
branch offering RGMII based GbE support</A> which has yet to be
merged into the project as a whole. GbE support does work, the
Tri-mode options haven't been well tested yet.
<LI><A HREF="https://github.com/ZipCPU/icozip">ICOZip</A>, unlike the
previous systems is a <A HREF="/about/zipcpu.html">ZipCPU</A> based
system designed for the iCE40 on the
<A HREF="https://www.icoboard.org">ICO board</A>. It can be
built using the entirely open source yosys based tool-chain.
This is another design built using
<B><A HREF="https://github.com/ZipCPU/autofpga">AutoFPGA</A></B>.
Further, like the
<B><A HREF="https://github.com/ZipCPU/s6soc">S6SoC</A></B> design
listed above, this is also a minimum logic design.
</UL></P>
<LI>Digital Signal Processing (DSP) cores
<UL>
<LI><A HREF="https://github.com/ZipCPU/cordic">CORDIC</A>
<P>This core generator will create a one of several sine-wave generators
in Verilog. These include a 1)
<A HREF="https://github.com/ZipCPU/cordic/blob/master/rtl/sintable.v">table based sinewave generator</A>,
2) a <A HREF="https://github.com/ZipCPU/cordic/blob/master/rtl/quarterwav.v">quarter-wave table based sinewave generator</A>,
3) a <A HREF="https://github.com/ZipCPU/cordic/blob/master/rtl/cordic.v">CORDIC based sin/cosine generator</A>,
and 4) a <A HREF="https://github.com/ZipCPU/cordic/blob/master/rtl/quadtbl.v">quadratically interpolated sinewave generator</A>.
The core generator can also generate a
<A HREF="https://github.com/ZipCPU/cordic/blob/master/rtl/topolar.v">CORDIC based arctangent</A>.
By using the core-gen approach, bit widths, precisions, and more are all
adjustable/configurable.
<P>With only a <A HREF="/dsp/2017/12/09/nco.html">touch more logic</A>, any of these cores can be made into
a <A HREF="/dsp/2017/12/09/nco.html">Numerically
Controlled Oscillator</A>
</P>
<LI><A HREF="https://github.com/ZipCPU/dspfilters">DSP Filters</A>
<P>We've discussed many digital filters on the blog. This repository
holds the filters I've presented.
<LI><A HREF="https://github.com/ZipCPU/interpolation">Interpolation</A>
<P>Years ago, I built a
<A HREF="https://github.com/ZipCPU/interpolation/raw/master/tutorial.pdf">tutorial slide deck</A>
presenting a piecewise polynomial approach to interpolation. That
<A HREF="https://github.com/ZipCPU/interpolation/raw/master/tutorial.pdf">tutorial</A>
is housed in this repository. Since then, I've added several
Verilog interpolation implementations as well:
<A HREF="https://github.com/ZipCPU/interpolation/tree/rtl/master/nearest-neighbor">nearest neighbor</A>,
<A HREF="https://github.com/ZipCPU/interpolation/tree/rtl/master/lininterp">linear</A>, and
<A HREF="https://github.com/ZipCPU/interpolation/tree/rtl/master/quadratic">quadratic</A>.</P>
<LI><A HREF="https://github.com/ZipCPU/dblclockfft">Double Clock FFT</A>
<P>This is an open source, pipelined FFT/IFFT generator. The
<A HREF="https://github.com/ZipCPU/dblclockfft/blob/master/sw/fftgen.cpp">core generator software</A>
will create Verilog code for a fairly generic pipelined FFT. It
is very configurable, allowing the user to choose:
<UL>
<LI>The FFT size, and whether a forward or inverse transform is desired
<LI>Input, output, and internal bit widths
<LI>The bit widths of the twiddle factors
<LI>The number of hardware multiplies used. If there aren't enough
hardware multiplies available, the FFT will substitute a
firmware multiplication algorithm.
</UL>
You can read about <A HREF="/dsp/2018/10/02/fft.html">this core and what it took to verify it here</A>.
My goal remains to eventually offer a real (as opposed to complex)
FFT capability as well, but I'm still one stage (and a lot of testing)
away from reaching that goal.</P>
<LI><A HREF="https://github.com/ZipCPU/fftdemo">FFT Demo</A>
<P>This project connects a simulated PModMIC3 to a <A HREF="https://github.com/ZipCPU/vgasim">simulated VGA</A>
output to create a scrolling spectral raster display.
An upgrade to the version on github uses DDR3 SDRAM (instead of large
amounts of block RAM), and an HDMI output.
<P>A further upgrade uses the <A HREF="/dsp/freq-teaser.html">high resolution frequency filters</A>. For another comparison of both with and without
the high resolution filter, see <A HREF="/img/tweets/fq-swepttone.png">this image</a>.
</P>
<LI><A HREF="https://github.com/ZipCPU/dpll">PLLs</A>
<P>I have published the code for two PLLs. The one I call a
<A HREF="/dsp/2017/12/14/logic-pll.html">logic PLL</A>
may be found in <A HREF="https://github.com/ZipCPU/dpll">this
repository</A>. The
<A HREF="/dsp/2017/12/14/logic-pll.html">logic PLL</A>
has the unique feature that it can receive and update within a single
clock. The other PLL can be found in the <A HREF="https://github.com/ZipCPU/openarty/blob/master/rtl/gpsclock.v">GPS schooled clock code</A>.
I have also designed a
<A HREF="/dsp/dpll-teaser.html">couple of
other PLL approaches</A> that will take
more than a single clock. Those should have *much* better performance,
but I have yet to port those PLL designs to an FPGA and test them.</P>
</UL>
<LI>Peripherals which may be used by the <A HREF="/about/zipcpu.html">ZipCPU</A>
<P>Computer systems don't make much sense these days without
peripherals, and the
<A HREF="/about/zipcpu.html">ZipCPU</A>
is no different. The following is a truncated list of peripherals that
have been used with the
<A HREF="/about/zipcpu.html">ZipCPU</A>.</P>
<UL>
<LI><A HREF="https://github.com/ZipCPU/wbuart32">UART controller</A>
<P>Contains both basic, and fully featured, serial port controllers</P>
<P>Two features make this controller particularly valuable. The first
is the four basic UART testing designs in the
<A HREF="https://github.com/ZipCPU/wbuart32/tree/master/bench/verilog">bench/verilog</A>
directory. When starting with any new design, before I know how the
board designer labeled the UART wires, I use these basic designs
to test them. Once tested, I can usually move quickly to a much larger
and more complex design with a
<A HREF="https://github.com/ZipCPU/dbgbus/tree/master/hexbus">debugging bus</A>
within it. The second valuable feature is the Verilator
<A HREF="https://github.com/ZipCPU/wbuart32/blob/master/bench/cpp/uartsim.cpp">UART simulator</A>,
which forwards a simulated designs UART ports to a TCP/IP network
channel.</P>
<LI><A HREF="https://github.com/ZipCPU/wbscope">Wishbone based scope</A>
<P>This plus the <A HREF="https://github.com/ZipCPU/dbgbus">UART
to wishbone bus converter</A> I have might easily be
considered the basics of any project I work on. Using this
<A HREF="https://github.com/ZipCPU/wbscope">wishbone scope</A>,
I have debugged many, many interfaces--some listed here. I would
recommend it for anyone interested in incorporating an internal logic
analyzer (scope) into one of their projects.</P>
<P>There is an <A HREF="https://github.com/ZipCPU/wbscope/blob/master/rtl/axilscope.v">AXI-lite version of the scope</A> in the repository as well.
<LI><A HREF="http://github.com/ZipCPU/qspiflash">QSPI Flash controller</A>
<P>A <A HREF="/blog/2019/03/27/qflexpress.html">"universal" QSPI based flash controller</A>, having <A HREF="https://github.com/ZipCPU/qspiflash/blob/master/rtl/dualflexpress.v">DSPI</A> and <A HREF="https://github.com/ZipCPU/blob/master/rtl/spixpress.v">SPI</A>
options in the same repository. I'm now using <A HREF="https://github.com/ZipCPU/qspiflash/blob/master/rtl/qflexpress.v">this controller</A> on
almost all of my projects.
<P>All of these controllers can execute software in place (XIP).
<LI><A HREF="https://github.com/ZipCPU/wbi2c">I2C Controller</A>
<P>This I2C controller repository began with two I2C controllers, a
<A HREF="https://github.com/ZipCPU/wbi2c/blob/master/rtl/wbi2cslave.v">slave</A>
and a <A HREF="https://github.com/ZipCPU/wbi2c/blob/master/rtl/wbi2cmaster.v">master</A>,
each wishbone controlled. Those two demonstrated themselves
via the ability to read and write EDID display information as part of
an HDMI project.</P>
<P>Since writing the two of those, I've since come back to the project
and added a <A HREF="/blog/2021/11/15/ultimate-i2c.thml">Universal I2C controller.</A>
This controller was originally designed to handle unattended telemetry
collection in a SONAR system. It's since been expanded to periodically
collect temperature in an unattended fashion, or to drive OLED displays.
It's also capable enough that I may even use it to implement
an EDDC/CI capability in a display channel in addition to its original
EDID purpose.</P>
<LI><A HREF="https://github.com/ZipCPU/wbpwmaudio">PWM Audio Controller</A>
<P>We <A HREF="/dsp/2017/09/04/pwm-reinvention.html">discussed this controller</A>
on <A HREF="https://zipcpu.com/">the blog</A>, and even
<A HREF="/dsp/2017/09/16/pwm-demo.html">demonstrated
it as well</A>.
<LI><A HREF="https://github.com/ZipCPU/openarty/blob/master/rtl/gpsclock.v">GPS schooled clock</A>
<P>This project takes, as input, the PPS signal from a
<A HREF="https://store.digilentinc.com/pmod-gps-gps-receiver">PMod GPS</A>
and locks an internal counter to the signal. Using this core, you can
record the time events to a precision of less than a fraction of a
microsecond.
</P>
<P>This project is currently part of my
<A HREF="https://github.com/ZipCPU/openarty">OpenArty project</A>, but
I've applied it to other projects of mine as well. Currently, using
the crystal oscillator on the
<A HREF="https://store.digilentinc.com/arty-artix-7-fpga-development-board-for-makers-and-hobbyists">Arty</A>
and the <A HREF="https://store.digilentinc.com/pmod-gps-gps-receiver">PMod GPS</A> from
<A HREF="https://store.digilentinc.com">Digilent</A>,
it can timestamp events within the design to within about 500ns or so
of absolute time.</P>
<LI><A HREF="https://github.com/ZipCPU/rtcclock">RTC Clock</A>
<P>This is a very simple, almost beginner, exercise to create a
clock in hours, minutes and seconds. It also includes a minutes and
seconds count-down timer, a stop watch, and alarm capability.
</P>
<LI><A HREF="https://github.com/ZipCPU/sdspi">SDSPI SD-card controller</A>
<P>In order to use the SD Card on the XuLA board, I needed a SPI
based SD-Card controller. While I intend to upgrade this to SDIO in
the future, the SPI based controller is still valuable for some
designs.</P>
<P>Since the original usage, I've been able to demonstrate reading and
writing files files from/to the SD Card. Even better, I can boot
the <A HREF="/about/zipcpu.html">ZipCPU</A>
off of a program stored on the SD card. Lord willing, this could make
a nice post.</P>
<LI><A HREF="https://github.com/ZipCPU/wbfmtx">FM transmitter hack</A>
<P>Just to prove FPGA's are in no ways inferior to
<A HREF="https://www.raspberrypi.org/magpi/raspberry-pi-fm-transmitter/">Raspberry
PI's</A>, this peripheral can be used to turn your GPIO pins into an
ad-hoc FM transmitter.</P>
<LI><A HREF="https://github.com/ZipCPU/wbpmic">WBPMIC</A>
<P>A very simple controller designed to read from <A HREF="http://store.digilentinc.com">Digilent</A>'s
<A HREF="https://store.digilentinc.com/pmod-mic3-mems-microphone-with-adjustable-gain/">MEMs microphone PMod</A>.</P>
<LI><A HREF="https://github.com/ZipCPU/openarty/blob/master/rtl/wboled.v">WB
Oled</A>, a controller for the
<A HREF="http://store.digilentinc.com">Digilent</A>
<A HREF="http://store.digilentinc.com/pmod-oledrgb-96-x-64-rgb-oled-display-with-16-bit-color-resolution/">PMod OLEDrgb</A> display
<P>A special feature of this design is the GTKmm based
simulation component, allowing you to visually "see" what the controller
would be placing on the screen.</P>
<LI><A HREF="https://github.com/ZipCPU/wbicapetwo">ICAPE Interface</A>
<P>Xilinx's internal configuration access port provides some very
useful features. Getting it running initially, though, was a touch
of a challenge. This project captures what it takes in a Wishbone
peripheral format.</P>
<LI><A HREF="https://github.com/ZipCPU/vgasim">VGA Simulator</A>
<P>While not technically a "peripheral that may be used by the ZipCPU",
the VGA simulator is a very important part of any graphical development.
A not-yet-released version simulates HDMI as well. Using the simulator,
you will be able to run your code within Verilator and visualize the
output within a GTK window on your computer screen--with no hardware
required beyond your desktop machine.
</P>
</UL>
</UL>
<div class="home">
I've also been known to offer a two day <u>Introduction to Formal
Methods</u> course to teach Verilog and VHDL developers how to use
<A HREF="https://symbiyosys.readthedocs.io/en/latest/">SymbiYosys</A>
in a "formal first" strategy.
<P><UL>
<P>Traditionally, the price of
<A HREF="https://en.wikipedia.org/wiki/Formal_verification">formal
methods</A> has limited their use to small teams of verification
engineers within large corporations. Today,
<A HREF="https://symbiyosys.readthedocs.io/en/latest/">SymbiYosys</A>
lowers the price of
<A HREF="https://en.wikipedia.org/wiki/Formal_verification">formal
verification</A> tools to the point where every RTL developer
can use them.
<P>The course teaches
<A HREF="https://en.wikipedia.org/wiki/Formal_verification">formal
verification</A>
from the basics through
bounded model checking and induction steps. Specific topics discussed
include dissimilar clocking, abstraction, invariants, arbitrary
values, and more. Examples will be drawn from counters, SPI
interactions, SDRAM controllers, cache implementations,
peripheral bus interaction, and more.
<P>This course can be booked for corporate training on-site.
Please contact me for details.
</UL>
<P>Most, but not all, of my projects have been released under the
<A HREF="https://www.gnu.org/licenses/gpl.html">GPLv3 license</A>. They may be
built with <A HREF="https://www.veripool.org/wiki/verilator">Verilator</A>
without violating this license. Indeed, the license allows you to build
your own projects using these components. Sadly, going beyond that limit gets
into a legally gray area at this time. Hence, if you find this license
insufficient for your needs, please contact me and I'll be glad to sell you a
proprietary license customized to meet your needs. A key exception to this
rule is my <A HREF="https://github.com/ZipCPU/wb2axip">Wishbone and AXI bus
interconnects, bridges, and other components</A> project, which has been
released under Apache 2 to encourage its widespread acceptance and adoption.
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