diff --git a/gen_input/ISA b/gen_input/ISA
index 4cb1545..2687e80 160000
--- a/gen_input/ISA
+++ b/gen_input/ISA
@@ -1 +1 @@
-Subproject commit 4cb1545f57007dca155f3453ff9961325aac7246
+Subproject commit 2687e80fc94e2658fc819e424fbe1f9094a67df6
diff --git a/gen_input/templates/CORENAME.cpp.gtl b/gen_input/templates/CORENAME.cpp.gtl
index 05a4f39..f6aba5b 100644
--- a/gen_input/templates/CORENAME.cpp.gtl
+++ b/gen_input/templates/CORENAME.cpp.gtl
@@ -57,14 +57,10 @@ ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv32gc.cpp b/src/iss/arch/rv32gc.cpp
index fa8bcdd..49a8c3d 100644
--- a/src/iss/arch/rv32gc.cpp
+++ b/src/iss/arch/rv32gc.cpp
@@ -50,14 +50,10 @@ rv32gc::rv32gc()  = default;
 rv32gc::~rv32gc() = default;
 
 void rv32gc::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv32gc>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv32gc>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv32gc::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv32gcv.cpp b/src/iss/arch/rv32gcv.cpp
index ffd5b8e..1f8ae650 100644
--- a/src/iss/arch/rv32gcv.cpp
+++ b/src/iss/arch/rv32gcv.cpp
@@ -50,14 +50,10 @@ rv32gcv::rv32gcv()  = default;
 rv32gcv::~rv32gcv() = default;
 
 void rv32gcv::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv32gcv>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv32gcv>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv32gcv::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv32i.cpp b/src/iss/arch/rv32i.cpp
index 2ee95c7..14abafd 100644
--- a/src/iss/arch/rv32i.cpp
+++ b/src/iss/arch/rv32i.cpp
@@ -50,14 +50,10 @@ rv32i::rv32i()  = default;
 rv32i::~rv32i() = default;
 
 void rv32i::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv32i>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv32i>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv32i::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv32imac.cpp b/src/iss/arch/rv32imac.cpp
index fced3e4..92e5445 100644
--- a/src/iss/arch/rv32imac.cpp
+++ b/src/iss/arch/rv32imac.cpp
@@ -50,14 +50,10 @@ rv32imac::rv32imac()  = default;
 rv32imac::~rv32imac() = default;
 
 void rv32imac::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv32imac>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv32imac::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv64gc.cpp b/src/iss/arch/rv64gc.cpp
index d6f81d4..2e8c404 100644
--- a/src/iss/arch/rv64gc.cpp
+++ b/src/iss/arch/rv64gc.cpp
@@ -50,14 +50,10 @@ rv64gc::rv64gc()  = default;
 rv64gc::~rv64gc() = default;
 
 void rv64gc::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv64gc>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv64gc>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv64gc::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv64gcv.cpp b/src/iss/arch/rv64gcv.cpp
index 3264c79..ef992a0 100644
--- a/src/iss/arch/rv64gcv.cpp
+++ b/src/iss/arch/rv64gcv.cpp
@@ -50,14 +50,10 @@ rv64gcv::rv64gcv()  = default;
 rv64gcv::~rv64gcv() = default;
 
 void rv64gcv::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv64gcv>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv64gcv>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv64gcv::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv64i.cpp b/src/iss/arch/rv64i.cpp
index 6cfe725..09c112d 100644
--- a/src/iss/arch/rv64i.cpp
+++ b/src/iss/arch/rv64i.cpp
@@ -50,14 +50,10 @@ rv64i::rv64i()  = default;
 rv64i::~rv64i() = default;
 
 void rv64i::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv64i>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv64i>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv64i::get_regs_base_ptr() {
diff --git a/src/iss/arch/rv64imac.cpp b/src/iss/arch/rv64imac.cpp
index ce78811..41eb39f 100644
--- a/src/iss/arch/rv64imac.cpp
+++ b/src/iss/arch/rv64imac.cpp
@@ -50,14 +50,10 @@ rv64imac::rv64imac()  = default;
 rv64imac::~rv64imac() = default;
 
 void rv64imac::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv64imac>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv64imac>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
+    std::memset(&reg, 0, sizeof(reg));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
 }
 
 uint8_t *rv64imac::get_regs_base_ptr() {
diff --git a/src/vm/asmjit/vm_rv32gc.cpp b/src/vm/asmjit/vm_rv32gc.cpp
index c073d9e..d476c41 100644
--- a/src/vm/asmjit/vm_rv32gc.cpp
+++ b/src/vm/asmjit/vm_rv32gc.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv32gc.h>
 #include <iss/debugger/gdb_session.h>
@@ -10106,8 +10106,8 @@ std::unique_ptr<vm_if> create<arch::rv32gc>(arch::rv32gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp
index 7472635..e4ad6a6 100644
--- a/src/vm/asmjit/vm_rv32gcv.cpp
+++ b/src/vm/asmjit/vm_rv32gcv.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv32gcv.h>
 #include <iss/debugger/gdb_session.h>
@@ -85513,8 +85513,8 @@ std::unique_ptr<vm_if> create<arch::rv32gcv>(arch::rv32gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv32i.cpp b/src/vm/asmjit/vm_rv32i.cpp
index 4231527..70f0bec 100644
--- a/src/vm/asmjit/vm_rv32i.cpp
+++ b/src/vm/asmjit/vm_rv32i.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv32i.h>
 #include <iss/debugger/gdb_session.h>
@@ -2949,8 +2949,8 @@ std::unique_ptr<vm_if> create<arch::rv32i>(arch::rv32i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv32imac.cpp b/src/vm/asmjit/vm_rv32imac.cpp
index 2a505a2..98e72b0 100644
--- a/src/vm/asmjit/vm_rv32imac.cpp
+++ b/src/vm/asmjit/vm_rv32imac.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv32imac.h>
 #include <iss/debugger/gdb_session.h>
@@ -5549,8 +5549,8 @@ std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned sho
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv64gc.cpp b/src/vm/asmjit/vm_rv64gc.cpp
index 59baf1c..dd412d1 100644
--- a/src/vm/asmjit/vm_rv64gc.cpp
+++ b/src/vm/asmjit/vm_rv64gc.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv64gc.h>
 #include <iss/debugger/gdb_session.h>
@@ -12687,8 +12687,8 @@ std::unique_ptr<vm_if> create<arch::rv64gc>(arch::rv64gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp
index c625cb0..54ff0ea 100644
--- a/src/vm/asmjit/vm_rv64gcv.cpp
+++ b/src/vm/asmjit/vm_rv64gcv.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv64gcv.h>
 #include <iss/debugger/gdb_session.h>
@@ -88094,8 +88094,8 @@ std::unique_ptr<vm_if> create<arch::rv64gcv>(arch::rv64gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv64i.cpp b/src/vm/asmjit/vm_rv64i.cpp
index f1cc199..e1de294 100644
--- a/src/vm/asmjit/vm_rv64i.cpp
+++ b/src/vm/asmjit/vm_rv64i.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv64i.h>
 #include <iss/debugger/gdb_session.h>
@@ -3604,8 +3604,8 @@ std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/asmjit/vm_rv64imac.cpp b/src/vm/asmjit/vm_rv64imac.cpp
index b22705b..5e2f240 100644
--- a/src/vm/asmjit/vm_rv64imac.cpp
+++ b/src/vm/asmjit/vm_rv64imac.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+ 
 // clang-format off
 #include <iss/arch/rv64imac.h>
 #include <iss/debugger/gdb_session.h>
@@ -7597,8 +7597,8 @@ std::unique_ptr<vm_if> create<arch::rv64imac>(arch::rv64imac *core, unsigned sho
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp
index fcafda5..e321c05 100644
--- a/src/vm/interp/vm_rv32gc.cpp
+++ b/src/vm/interp/vm_rv32gc.cpp
@@ -156,7 +156,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<32)|val);
+            return (uint64_t)(((uint128_t)(box)<<32)|val);
         }
     }
 
@@ -175,7 +175,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<64)|val);
+            return (uint64_t)(((uint128_t)(box)<<64)|val);
         }
     }
 
@@ -2809,7 +2809,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -3006,13 +3008,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SLLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
-                            fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"),
+                            fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -3026,7 +3028,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rs1 != 0) {
-                                            *(X+rs1) = *(X+rs1) << nzuimm;
+                                            *(X+rs1) = *(X+rs1) << shamt;
                                         }
                                     }
                                 }
@@ -3721,7 +3723,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -3742,7 +3744,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32((((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -4324,8 +4326,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
-                        *(F+rd) = res;
+                        *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
                         uint32_t flags = fget_flags();
                         *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
@@ -4545,7 +4546,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
-                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
+                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]); 
                     auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
                     // calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -4574,7 +4575,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -4595,7 +4596,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64((((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -4861,7 +4862,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
+                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
                                     if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                 }
                     break;
diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp
index e85bd59..dd19c7d 100644
--- a/src/vm/interp/vm_rv32gcv.cpp
+++ b/src/vm/interp/vm_rv32gcv.cpp
@@ -268,7 +268,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<32)|val);
+            return (uint64_t)(((uint128_t)(box)<<32)|val);
         }
     }
 
@@ -287,7 +287,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<64)|val);
+            return (uint64_t)(((uint128_t)(box)<<64)|val);
         }
     }
 
@@ -3780,7 +3780,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -3977,13 +3979,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SLLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
-                            fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"),
+                            fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -3997,7 +3999,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rs1 != 0) {
-                                            *(X+rs1) = *(X+rs1) << nzuimm;
+                                            *(X+rs1) = *(X+rs1) << shamt;
                                         }
                                     }
                                 }
@@ -4692,7 +4694,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -4713,7 +4715,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5295,8 +5297,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
-                        *(F+rd) = res;
+                        *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
                         uint32_t flags = fget_flags();
                         *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
@@ -5516,12 +5517,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
-                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
+                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]); 
+                    auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
                     // calculate next pc value
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
                         *(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
+                        uint32_t flags = fget_flags();
+                        *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5542,7 +5546,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5563,7 +5567,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5829,7 +5833,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
+                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
                                     if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                 }
                     break;
@@ -5880,7 +5884,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow());
                                         uint32_t orig_vstart = *vstart;
                                         *vstart = 0;
-                                        *vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
+                                        *vtype = (uint32_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
                                         if(! valid_sew_lmul()) {
                                             handle_illegal_vtype();
                                             *vstart = orig_vstart;
@@ -5939,7 +5943,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        *vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
+                                        *vtype = (uint32_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
                                         if(! valid_sew_lmul()) {
                                             handle_illegal_vtype();
                                         }
@@ -12574,7 +12578,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         if(illegal_vd_unmasked()) {
                                             raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                         }
-                                        uint32_t _vtype = (bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
+                                        uint32_t _vtype = ((bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint32_t)(1)<<6)|((uint32_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
                                         *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1);
                                     }
                                 }
@@ -12608,7 +12612,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         if(illegal_vd_unmasked()) {
                                             raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                         }
-                                        uint32_t _vtype = (bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
+                                        uint32_t _vtype = ((bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint32_t)(1)<<6)|((uint32_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
                                         *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1);
                                     }
                                 }
diff --git a/src/vm/interp/vm_rv32imac.cpp b/src/vm/interp/vm_rv32imac.cpp
index 2eb6cc0..42415a1 100644
--- a/src/vm/interp/vm_rv32imac.cpp
+++ b/src/vm/interp/vm_rv32imac.cpp
@@ -2714,7 +2714,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2911,13 +2913,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SLLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
-                            fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"),
+                            fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -2931,7 +2933,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rs1 != 0) {
-                                            *(X+rs1) = *(X+rs1) << nzuimm;
+                                            *(X+rs1) = *(X+rs1) << shamt;
                                         }
                                     }
                                 }
diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp
index d6aa745..9a6158d 100644
--- a/src/vm/interp/vm_rv64gc.cpp
+++ b/src/vm/interp/vm_rv64gc.cpp
@@ -156,7 +156,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<32)|val);
+            return (uint64_t)(((uint128_t)(box)<<32)|val);
         }
     }
 
@@ -175,7 +175,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<64)|val);
+            return (uint64_t)(((uint128_t)(box)<<64)|val);
         }
     }
 
@@ -3838,13 +3838,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SRLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.srli"),
-                            fmt::arg("rs1", name(8+rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
+                            fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -3853,7 +3853,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> nzuimm;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -4982,7 +4984,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5003,7 +5005,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32((((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5487,8 +5489,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
-                        *(F+rd) = res;
+                        *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
                         uint32_t flags = fget_flags();
                         *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
@@ -5834,7 +5835,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
-                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
+                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]); 
                     auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
                     // calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -5863,7 +5864,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5884,7 +5885,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64((((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -6204,7 +6205,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    super::template write_mem<uint64_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
+                                    super::template write_mem<uint64_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
                                     if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                 }
                     break;
diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp
index 9705d3b..0046c7a 100644
--- a/src/vm/interp/vm_rv64gcv.cpp
+++ b/src/vm/interp/vm_rv64gcv.cpp
@@ -268,7 +268,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<32)|val);
+            return (uint64_t)(((uint128_t)(box)<<32)|val);
         }
     }
 
@@ -287,7 +287,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
         }
         else {
             uint64_t box = ~((uint64_t)0);
-            return (uint64_t)(((uint128_t)box<<64)|val);
+            return (uint64_t)(((uint128_t)(box)<<64)|val);
         }
     }
 
@@ -4809,13 +4809,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SRLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.srli"),
-                            fmt::arg("rs1", name(8+rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
+                            fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -4824,7 +4824,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> nzuimm;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5953,7 +5955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -5974,7 +5976,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -6458,8 +6460,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
-                        *(F+rd) = res;
+                        *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
                         uint32_t flags = fget_flags();
                         *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
@@ -6805,12 +6806,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
-                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
+                    auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]); 
+                    auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
                     // calculate next pc value
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
                         *(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
+                        uint32_t flags = fget_flags();
+                        *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -6831,7 +6835,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -6852,7 +6856,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                        *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
+                        *(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -7172,7 +7176,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    super::template write_mem<uint64_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
+                                    super::template write_mem<uint64_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
                                     if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                 }
                     break;
@@ -7223,7 +7227,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow());
                                         uint64_t orig_vstart = *vstart;
                                         *vstart = 0;
-                                        *vtype = (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
+                                        *vtype = (uint64_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
                                         if(! valid_sew_lmul()) {
                                             handle_illegal_vtype();
                                             *vstart = orig_vstart;
@@ -7282,7 +7286,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        *vtype = (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
+                                        *vtype = (uint64_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
                                         if(! valid_sew_lmul()) {
                                             handle_illegal_vtype();
                                         }
@@ -13917,7 +13921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         if(illegal_vd_unmasked()) {
                                             raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                         }
-                                        uint64_t _vtype = (bit_sub<uint64_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
+                                        uint64_t _vtype = ((bit_sub<uint64_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint64_t)(1)<<6)|((uint64_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
                                         *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1);
                                     }
                                 }
@@ -13951,7 +13955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         if(illegal_vd_unmasked()) {
                                             raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                         }
-                                        uint64_t _vtype = (bit_sub<uint64_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
+                                        uint64_t _vtype = ((bit_sub<uint64_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint64_t)(1)<<6)|((uint64_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
                                         *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1);
                                     }
                                 }
diff --git a/src/vm/interp/vm_rv64imac.cpp b/src/vm/interp/vm_rv64imac.cpp
index 3ba3883..8100b8b 100644
--- a/src/vm/interp/vm_rv64imac.cpp
+++ b/src/vm/interp/vm_rv64imac.cpp
@@ -3737,13 +3737,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 case arch::traits<ARCH>::opcode_e::C__SRLI: {
-                    uint8_t nzuimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+                    uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.srli"),
-                            fmt::arg("rs1", name(8+rs1)), fmt::arg("nzuimm", nzuimm));
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
+                            fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers
@@ -3752,7 +3752,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 + 8) = *(X+rs1 + 8) >> nzuimm;
+                        if(shamt) {
+                            *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
+                        }
                     }
                     break;
                 }// @suppress("No break at end of case")