diff --git a/.devops/intel.Dockerfile b/.devops/intel.Dockerfile index e8b7e6077045..09daa5fe5d1a 100644 --- a/.devops/intel.Dockerfile +++ b/.devops/intel.Dockerfile @@ -19,7 +19,12 @@ RUN npm ci COPY tools/ui/ ./ RUN LLAMA_BUILD_NUMBER="$APP_VERSION" npm run build -FROM docker.io/intel/oneapi-toolkit:$ONEAPI_VERSION AS build +FROM docker.io/intel/deep-learning-essentials:$ONEAPI_VERSION AS build + +RUN echo "Download oneDNN installation package" && \ + wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/94c3dbac-0852-45be-a57d-21c204cada3e/intel-onednn-2026.0.2.46_offline.sh -O intel-onednn_offline.sh && \ + echo "Install oneDNN components" && \ + bash intel-onednn_offline.sh -s -a --silent --eula accept ARG GGML_SYCL_F16=ON ARG LEVEL_ZERO_VERSION=1.28.2 @@ -45,7 +50,7 @@ RUN if [ "${GGML_SYCL_F16}" = "ON" ]; then \ fi && \ echo "Building with dynamic libs" && \ cmake -B build -DGGML_NATIVE=OFF -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DGGML_BACKEND_DL=ON -DGGML_CPU_ALL_VARIANTS=ON -DLLAMA_BUILD_TESTS=OFF ${OPT_SYCL_F16} && \ - cmake --build build --config Release -j$(nproc) + cmake --build build --config Release -j$((($(nproc)+1)/2)) RUN mkdir -p /app/lib && \ find build -name "*.so*" -exec cp -P {} /app/lib \; @@ -102,7 +107,7 @@ RUN mkdir /tmp/neo/ && cd /tmp/neo/ \ && dpkg --install *.deb RUN apt-get update \ - && apt-get install -y libgomp1 curl ffmpeg \ + && apt-get install -y libgomp1 curl ffmpeg openssl libssl-dev \ && apt autoremove -y \ && apt clean -y \ && rm -rf /tmp/* /var/tmp/* \ diff --git a/.flake8 b/.flake8 index 669d231f1f63..d908f846ad3f 100644 --- a/.flake8 +++ b/.flake8 @@ -5,6 +5,8 @@ exclude = # Do not traverse examples and tools examples, tools, + # Do not traverse .venv directories + .venv*, # Do not include package initializers __init__.py, # No need to traverse our git directory diff --git a/.github/workflows/behavior-check.yml b/.github/workflows/behavior-check.yml new file mode 100644 index 000000000000..73c3b8fe223a --- /dev/null +++ b/.github/workflows/behavior-check.yml @@ -0,0 +1,172 @@ +name: Behavior Check + +on: + workflow_dispatch: # allows manual triggering + push: + branches: + - master + paths: [ + '.github/workflows/behavior-check.yml', + '**/CMakeLists.txt', + '**/.cmake', + '**/*.h', + '**/*.hpp', + '**/*.c', + '**/*.cpp', + '**/*.py', + '**/requirements*.txt', + ] + + pull_request: + types: [opened, synchronize, reopened] + paths: [ + '.github/workflows/behavior-check.yml', + '**/CMakeLists.txt', + '**/.cmake', + '**/*.h', + '**/*.hpp', + '**/*.c', + '**/*.cpp', + '**/*.py', + '**/requirements*.txt', + ] + +cache-mode: none +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref && github.ref || github.run_id }} + cancel-in-progress: true + +env: + GGML_NLOOP: 3 + GGML_N_THREADS: 1 + GGML_SCHED_DEBUG_REALLOC: 1 + LLAMA_ARG_LOG_COLORS: 1 + LLAMA_ARG_LOG_PREFIX: 1 + LLAMA_ARG_LOG_TIMESTAMPS: 1 + +jobs: + ubuntu: + runs-on: ubuntu-26.04-arm + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.24 + with: + restore: false + save: false + + - name: Build Dependencies + id: build_depends + run: | + sudo apt update + sudo apt install -y build-essential libssl-dev git-lfs libjpeg-dev python3 python3-venv python3-pip + + - name: Python Dependencies + id: python_depends + run: | + python3 -m venv .venv + source .venv/bin/activate + pip install -r requirements/requirements-convert_hf_to_gguf.txt + + - name: ccache-buckets-restore + uses: ./.github/actions/ccache-buckets + env: + HF_TOKEN: ${{ secrets.HF_TOKEN_CI }} + with: + key: behavior-check-ubuntu-26.04-arm + folder: llama.cpp + hf_bucket: ggml-org/cache + + - name: Build + id: cmake_build + run: | + cmake -B build \ + -DGGML_NATIVE=OFF \ + -DGGML_BACKEND_DL=OFF \ + -DLLAMA_FATAL_WARNINGS=ON + time cmake --build build --config Release -j $(nproc) + + - name: ccache-buckets-save + if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} + uses: ./.github/actions/ccache-buckets + env: + HF_TOKEN: ${{ secrets.HF_TOKEN_CACHE_OUTPUT }} + with: + key: behavior-check-ubuntu-26.04-arm + folder: llama.cpp + evict-old-files: 1d + hf_bucket: ggml-org/cache + save: true + + - name: Test + id: cmake_test + run: | + source .venv/bin/activate + cd build + ctest -L behavior -LE 'model|backend' --verbose --timeout 900 + + windows: + runs-on: windows-2025 + + cache-mode: write + permissions: + actions: write + contents: read + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.24 + with: + key: behavior-check-windows-2025 + evict-old-files: 1d + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} + + - name: Python Dependencies + id: python_depends + shell: bash + run: | + python3 -m venv .venv + source .venv/Scripts/activate + pip install -r requirements/requirements-convert_hf_to_gguf.txt + + - name: Build + id: cmake_build + shell: cmd + run: | + call "C:\Program Files\Microsoft Visual Studio\18\Enterprise\VC\Auxiliary\Build\vcvarsall.bat" x64 + cmake -B build -G "Ninja Multi-Config" ^ + -DCMAKE_TOOLCHAIN_FILE=cmake/x64-windows-llvm.cmake ^ + -DCMAKE_BUILD_TYPE=Release ^ + -DGGML_NATIVE=OFF ^ + -DGGML_BACKEND_DL=OFF + set /A NINJA_JOBS=%NUMBER_OF_PROCESSORS%-1 + cmake --build build --config Release -j %NINJA_JOBS% + + - name: Test + id: cmake_test + shell: bash + run: | + source .venv/Scripts/activate + cd build + ctest -C Release -L behavior -LE 'model|backend' --verbose --timeout 900 + + - name: ccache-clear + uses: ./.github/actions/ccache-clear + env: + GH_TOKEN: ${{ github.token }} + with: + key: behavior-check-windows-2025 + older: 5m + min: 1 + dry-run: ${{ github.event_name != 'push' || github.ref != 'refs/heads/master' }} diff --git a/.github/workflows/build-and-test-snapdragon.yml b/.github/workflows/build-and-test-snapdragon.yml index d6420b65f141..f7f94d7ee996 100644 --- a/.github/workflows/build-and-test-snapdragon.yml +++ b/.github/workflows/build-and-test-snapdragon.yml @@ -35,7 +35,7 @@ jobs: android-ndk-snapdragon: runs-on: ubuntu-24.04 # previously ubuntu-latest container: - image: 'ghcr.io/snapdragon-toolchain/arm64-android:v0.7' + image: 'ghcr.io/snapdragon-toolchain/arm64-android:v0.8' defaults: run: shell: bash @@ -69,7 +69,7 @@ jobs: linux-iot-snapdragon: runs-on: ubuntu-24.04 # previously ubuntu-latest container: - image: 'ghcr.io/snapdragon-toolchain/arm64-linux:v0.7' + image: 'ghcr.io/snapdragon-toolchain/arm64-linux:v0.8' defaults: run: shell: bash @@ -104,11 +104,11 @@ jobs: name: Test on QDC Device (${{ matrix.device }}) needs: [android-ndk-snapdragon, linux-iot-snapdragon] runs-on: ubuntu-24.04-arm - timeout-minutes: 90 + timeout-minutes: 180 strategy: fail-fast: false matrix: - device: [SM8750, SM8850, QCS9075M] + device: [SM8850, QCS9075M] permissions: actions: read @@ -155,7 +155,7 @@ jobs: --pkg-dir pkg-snapdragon/llama.cpp \ --model-url "https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-Q4_0.gguf" \ --device ${{ matrix.device }} \ - ${{ startsWith(matrix.device, 'QCS') && '--retries 2 --retry-delay 300' || '' }} + ${{ startsWith(matrix.device, 'QCS') && '--job-timeout 5400 --retries 2 --retry-delay 300' || '' }} env: QDC_API_KEY: ${{ secrets.QDC_API_KEY }} diff --git a/.github/workflows/build-apple-daily.yml b/.github/workflows/build-apple-daily.yml new file mode 100644 index 000000000000..27c6e43b4d54 --- /dev/null +++ b/.github/workflows/build-apple-daily.yml @@ -0,0 +1,160 @@ +name: CI (apple - daily) + +on: + workflow_dispatch: # allows manual triggering + schedule: + - cron: '0 0 * * *' + +cache-mode: none +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref && github.ref || github.run_id }} + cancel-in-progress: true + +env: + GGML_NLOOP: 3 + GGML_N_THREADS: 1 + LLAMA_ARG_LOG_COLORS: 1 + LLAMA_ARG_LOG_PREFIX: 1 + LLAMA_ARG_LOG_TIMESTAMPS: 1 + +jobs: + macos-latest-ios-xcode: + runs-on: macos-latest + + permissions: + actions: write + contents: read + + steps: + - name: Checkout code + uses: actions/checkout@v6 + + - name: Setup Xcode + uses: ggml-org/setup-xcode@v1 + with: + xcode-version: latest-stable + + - name: Build + id: cmake_build + run: | + sysctl -a + cmake -B build -G Xcode \ + -DGGML_METAL_EMBED_LIBRARY=ON \ + -DLLAMA_OPENSSL=OFF \ + -DLLAMA_BUILD_APP=OFF \ + -DLLAMA_BUILD_EXAMPLES=OFF \ + -DLLAMA_BUILD_TOOLS=OFF \ + -DLLAMA_BUILD_TESTS=OFF \ + -DLLAMA_BUILD_SERVER=OFF \ + -DCMAKE_SYSTEM_NAME=iOS \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=14.0 \ + -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml + cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO + + - name: xcodebuild for swift package + id: xcodebuild + run: | + ./build-xcframework.sh + + - name: Upload xcframework artifact + uses: actions/upload-artifact@v6 + with: + name: llama-xcframework + path: build-apple/llama.xcframework/ + retention-days: 1 + + - name: Build Xcode project + run: | + xcodebuild -downloadPlatform iOS + xcodebuild -project examples/llama.swiftui/llama.swiftui.xcodeproj -scheme llama.swiftui -sdk iphoneos CODE_SIGNING_REQUIRED=NO CODE_SIGN_IDENTITY= -destination 'generic/platform=iOS' FRAMEWORK_FOLDER_PATH=./build-ios build + + macos-latest-tvos: + runs-on: macos-latest + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: Build + id: cmake_build + run: | + sysctl -a + cmake -B build -G Xcode \ + -DGGML_METAL_EMBED_LIBRARY=ON \ + -DLLAMA_BUILD_COMMON=OFF \ + -DLLAMA_BUILD_APP=OFF \ + -DLLAMA_BUILD_EXAMPLES=OFF \ + -DLLAMA_BUILD_TOOLS=OFF \ + -DLLAMA_BUILD_TESTS=OFF \ + -DLLAMA_BUILD_SERVER=OFF \ + -DCMAKE_SYSTEM_NAME=tvOS \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=14.0 \ + -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml + cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO + + macos-latest-visionos: + runs-on: macos-latest + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: Build + id: cmake_build + run: | + sysctl -a + cmake -B build -G Xcode \ + -DGGML_METAL_EMBED_LIBRARY=ON \ + -DLLAMA_BUILD_COMMON=OFF \ + -DLLAMA_BUILD_APP=OFF \ + -DLLAMA_BUILD_EXAMPLES=OFF \ + -DLLAMA_BUILD_TOOLS=OFF \ + -DLLAMA_BUILD_TESTS=OFF \ + -DLLAMA_BUILD_SERVER=OFF \ + -DCMAKE_SYSTEM_NAME=visionOS \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=1.0 \ + -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml + cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO + + macos-latest-swift: + runs-on: macos-latest + needs: macos-latest-ios-xcode + + permissions: + actions: read + contents: read + + strategy: + matrix: + destination: ['generic/platform=macOS', 'generic/platform=iOS', 'generic/platform=tvOS'] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: Download xcframework artifact + uses: actions/download-artifact@v7 + with: + name: llama-xcframework + path: build-apple/llama.xcframework/ + + - name: Build llama.cpp with CMake + id: cmake_build + run: | + sysctl -a + cmake -B build -G Xcode \ + -DGGML_METAL_EMBED_LIBRARY=ON \ + -DLLAMA_OPENSSL=OFF \ + -DLLAMA_BUILD_APP=OFF \ + -DLLAMA_BUILD_EXAMPLES=OFF \ + -DLLAMA_BUILD_TOOLS=OFF \ + -DLLAMA_BUILD_TESTS=OFF \ + -DLLAMA_BUILD_SERVER=OFF \ + -DCMAKE_OSX_ARCHITECTURES="arm64;x86_64" + cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) diff --git a/.github/workflows/build-apple.yml b/.github/workflows/build-apple.yml index 70aefd5c8081..7fbc4a5499c9 100644 --- a/.github/workflows/build-apple.yml +++ b/.github/workflows/build-apple.yml @@ -105,198 +105,5 @@ jobs: cd build # Metal Paravirtual devices are difficult to support -> disable # ref: https://github.com/ggml-org/llama.cpp/pull/19802#issuecomment-4013704023 - ctest -L main -E "test-llama-archs|test-llama-context" --verbose --timeout 900 + ctest -L main -E "test-llama-archs|test-llama-context|test-speculative-rejection-sampling" --verbose --timeout 900 - macos-latest-x64: - runs-on: macos-15-intel - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: ccache - uses: ggml-org/ccache-action@v1.2.24 - with: - restore: false - save: false - - - name: ccache-buckets-restore - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CI }} - with: - key: apple-x64 - folder: llama.cpp - hf_bucket: ggml-org/cache - - - name: Build - id: cmake_build - run: | - sysctl -a - # Metal is disabled due to intermittent failures with Github runners not having a GPU: - # https://github.com/ggml-org/llama.cpp/actions/runs/8635935781/job/23674807267#step:5:2313 - cmake -B build \ - -DCMAKE_BUILD_RPATH="@loader_path" \ - -DLLAMA_FATAL_WARNINGS=ON \ - -DLLAMA_BUILD_BORINGSSL=ON \ - -DGGML_METAL=OFF \ - -DGGML_RPC=ON \ - -DCMAKE_OSX_DEPLOYMENT_TARGET=13.3 - time cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) - - - name: ccache-buckets-save - if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CACHE_OUTPUT }} - with: - key: apple-x64 - folder: llama.cpp - evict-old-files: 1d - hf_bucket: ggml-org/cache - save: true - - - name: Test - id: cmake_test - run: | - cd build - ctest -L main --verbose --timeout 900 - - macos-latest-ios-xcode: - runs-on: macos-latest - - permissions: - actions: write - contents: read - - steps: - - name: Checkout code - uses: actions/checkout@v6 - - - name: Setup Xcode - uses: ggml-org/setup-xcode@v1 - with: - xcode-version: latest-stable - - - name: Build - id: cmake_build - run: | - sysctl -a - cmake -B build -G Xcode \ - -DGGML_METAL_EMBED_LIBRARY=ON \ - -DLLAMA_OPENSSL=OFF \ - -DLLAMA_BUILD_APP=OFF \ - -DLLAMA_BUILD_EXAMPLES=OFF \ - -DLLAMA_BUILD_TOOLS=OFF \ - -DLLAMA_BUILD_TESTS=OFF \ - -DLLAMA_BUILD_SERVER=OFF \ - -DCMAKE_SYSTEM_NAME=iOS \ - -DCMAKE_OSX_DEPLOYMENT_TARGET=14.0 \ - -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml - cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO - - - name: xcodebuild for swift package - id: xcodebuild - run: | - ./build-xcframework.sh - - - name: Upload xcframework artifact - uses: actions/upload-artifact@v6 - with: - name: llama-xcframework - path: build-apple/llama.xcframework/ - retention-days: 1 - - - name: Build Xcode project - run: | - xcodebuild -downloadPlatform iOS - xcodebuild -project examples/llama.swiftui/llama.swiftui.xcodeproj -scheme llama.swiftui -sdk iphoneos CODE_SIGNING_REQUIRED=NO CODE_SIGN_IDENTITY= -destination 'generic/platform=iOS' FRAMEWORK_FOLDER_PATH=./build-ios build - - macos-latest-tvos: - runs-on: macos-latest - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: Build - id: cmake_build - run: | - sysctl -a - cmake -B build -G Xcode \ - -DGGML_METAL_EMBED_LIBRARY=ON \ - -DLLAMA_BUILD_COMMON=OFF \ - -DLLAMA_BUILD_APP=OFF \ - -DLLAMA_BUILD_EXAMPLES=OFF \ - -DLLAMA_BUILD_TOOLS=OFF \ - -DLLAMA_BUILD_TESTS=OFF \ - -DLLAMA_BUILD_SERVER=OFF \ - -DCMAKE_SYSTEM_NAME=tvOS \ - -DCMAKE_OSX_DEPLOYMENT_TARGET=14.0 \ - -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml - cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO - - macos-latest-visionos: - runs-on: macos-latest - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: Build - id: cmake_build - run: | - sysctl -a - cmake -B build -G Xcode \ - -DGGML_METAL_EMBED_LIBRARY=ON \ - -DLLAMA_BUILD_COMMON=OFF \ - -DLLAMA_BUILD_APP=OFF \ - -DLLAMA_BUILD_EXAMPLES=OFF \ - -DLLAMA_BUILD_TOOLS=OFF \ - -DLLAMA_BUILD_TESTS=OFF \ - -DLLAMA_BUILD_SERVER=OFF \ - -DCMAKE_SYSTEM_NAME=visionOS \ - -DCMAKE_OSX_DEPLOYMENT_TARGET=1.0 \ - -DCMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM=ggml - cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) -- CODE_SIGNING_ALLOWED=NO - - macos-latest-swift: - runs-on: macos-latest - needs: macos-latest-ios-xcode - - permissions: - actions: read - contents: read - - strategy: - matrix: - destination: ['generic/platform=macOS', 'generic/platform=iOS', 'generic/platform=tvOS'] - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: Download xcframework artifact - uses: actions/download-artifact@v7 - with: - name: llama-xcframework - path: build-apple/llama.xcframework/ - - - name: Build llama.cpp with CMake - id: cmake_build - run: | - sysctl -a - cmake -B build -G Xcode \ - -DGGML_METAL_EMBED_LIBRARY=ON \ - -DLLAMA_OPENSSL=OFF \ - -DLLAMA_BUILD_APP=OFF \ - -DLLAMA_BUILD_EXAMPLES=OFF \ - -DLLAMA_BUILD_TOOLS=OFF \ - -DLLAMA_BUILD_TESTS=OFF \ - -DLLAMA_BUILD_SERVER=OFF \ - -DCMAKE_OSX_ARCHITECTURES="arm64;x86_64" - cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) diff --git a/.github/workflows/build-cmake-pkg.yml b/.github/workflows/build-cmake-pkg.yml index e5be1dae1c8d..4e351ecb77db 100644 --- a/.github/workflows/build-cmake-pkg.yml +++ b/.github/workflows/build-cmake-pkg.yml @@ -9,7 +9,7 @@ permissions: jobs: linux: - runs-on: [self-hosted, Linux, CPU] + runs-on: [self-hosted, Linux, fast] steps: - uses: actions/checkout@v6 with: diff --git a/.github/workflows/build-cpu.yml b/.github/workflows/build-cpu.yml index 78d1c5f82558..76a030e67d35 100644 --- a/.github/workflows/build-cpu.yml +++ b/.github/workflows/build-cpu.yml @@ -129,7 +129,7 @@ jobs: id: cmake_test run: | cd build - ctest -L 'main|python' --verbose --timeout 900 + ctest -L main --verbose --timeout 900 - name: Test llama2c conversion id: llama2c_test diff --git a/.github/workflows/build-ibm.yml b/.github/workflows/build-ibm.yml index fcf90ccee9ce..e896b87017ad 100644 --- a/.github/workflows/build-ibm.yml +++ b/.github/workflows/build-ibm.yml @@ -20,7 +20,11 @@ on: paths: [ '.github/workflows/build-ibm.yml', 'ggml/src/ggml-cpu/**', - 'ggml/src/ggml-zdnn/**' + 'ggml/src/ggml-zdnn/**', + 'ggml/src/ggml-quants.c', + 'src/llama-quant.cpp', + 'gguf-py/gguf/scripts/gguf_convert_endian.py', + 'tests/test-quantize-be.sh' ] cache-mode: none @@ -39,9 +43,9 @@ env: LLAMA_ARG_LOG_TIMESTAMPS: 1 jobs: - ubuntu-24-s390x: - name: ubuntu-24-s390x (VXE ${{ matrix.vxe }}) - runs-on: ubuntu-24.04-s390x + ubuntu-26-s390x: + name: ubuntu-26-s390x (VXE ${{ matrix.vxe }}) + runs-on: ubuntu-26.04-s390x strategy: fail-fast: false @@ -62,12 +66,6 @@ jobs: libjpeg-dev build-essential libssl-dev \ git-lfs - - name: Toolchain workaround (GCC 14) - run: | - sudo apt-get install -y gcc-14 g++-14 - echo "CC=gcc-14" >> "$GITHUB_ENV" - echo "CXX=g++-14" >> "$GITHUB_ENV" - - name: Python Dependencies id: python_depends run: | @@ -105,32 +103,26 @@ jobs: wget https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories260K-be.gguf ./bin/llama-completion -m stories260K-be.gguf -p "One day, Lily met a Shoggoth" -n 500 -c 256 + - name: Test quantize (s390x) + id: quantize_test_s390x + run: | + ./tests/test-quantize-be.sh ./build/bin/llama-quantize ./build/bin/llama-perplexity 2>&1 + ubuntu-26-zdnn-s390x: name: ubuntu-26-zdnn-s390x - runs-on: ubuntu-24.04-s390x - container: ubuntu:26.04 # required to get GCC 15.1 and binutils 2.44 - defaults: - run: - shell: bash + runs-on: ubuntu-26.04-s390x steps: - - name: Build Dependencies - id: build_depends - run: | - apt-get update - apt-get install -y --no-install-recommends \ - build-essential cmake git ca-certificates \ - libssl-dev libzdnn-dev - - name: Clone id: checkout uses: actions/checkout@v6 - - name: Toolchain workaround (GCC 15) + - name: Build Dependencies + id: build_depends run: | - apt-get install -y gcc-15 g++-15 - echo "CC=gcc-15" >> "$GITHUB_ENV" - echo "CXX=g++-15" >> "$GITHUB_ENV" + sudo apt-get update + sudo apt-get install -y --no-install-recommends \ + build-essential libssl-dev libzdnn-dev - name: Build with zDNN Backend id: cmake_build diff --git a/.github/workflows/build-sanitize.yml b/.github/workflows/build-sanitize.yml index 3a78c4d092a0..ed75a2dc1cee 100644 --- a/.github/workflows/build-sanitize.yml +++ b/.github/workflows/build-sanitize.yml @@ -49,7 +49,7 @@ jobs: - sanitizer: THREAD machine: ubuntu-24.04 - sanitizer: UNDEFINED - machine: [self-hosted, X64, Linux] + machine: [self-hosted, X64, Linux, CPU] runs-on: ${{ matrix.machine }} diff --git a/.github/workflows/build-sycl.yml b/.github/workflows/build-sycl.yml index 741c9ce77c1c..ecfab4e52403 100644 --- a/.github/workflows/build-sycl.yml +++ b/.github/workflows/build-sycl.yml @@ -67,8 +67,15 @@ jobs: shell: bash run: | cd /tmp - wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/5996e26b-f48a-42b1-8db0-b002ad0bd8d7/intel-oneapi-toolkit-2026.1.1.33_offline.sh -O intel-oneapi-toolkit_offline.sh - sudo bash intel-oneapi-toolkit_offline.sh -s -a --silent --eula accept + echo "Download oneAPI Deep Learning Essentials installation package" + wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/b5c100a7-8052-4e88-90e2-63d9916a998b/intel-deep-learning-essentials-2026.1.4.17_offline.sh -O intel-deep-learning-essentials_offline.sh + echo "Install oneAPI Deep Learning Essentials components" + sudo bash intel-deep-learning-essentials_offline.sh -s -a --silent --eula accept + + echo "Download oneDNN installation package" + wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/94c3dbac-0852-45be-a57d-21c204cada3e/intel-onednn-2026.0.2.46_offline.sh -O intel-onednn_offline.sh + echo "Install oneDNN components" + sudo bash intel-onednn_offline.sh -s -a --silent --eula accept - name: Install Level Zero SDK shell: bash @@ -79,6 +86,12 @@ jobs: wget -q "https://github.com/oneapi-src/level-zero/releases/download/v${LEVEL_ZERO_VERSION}/libze-dev_${LEVEL_ZERO_VERSION}%2B${LEVEL_ZERO_UBUNTU_VERSION}_amd64.deb" -O libze-dev.deb sudo apt-get install -y ./libze1.deb ./libze-dev.deb + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install -y libssl-dev + - name: ccache uses: ggml-org/ccache-action@v1.2.24 with: @@ -104,7 +117,6 @@ jobs: -DGGML_SYCL=ON \ -DCMAKE_C_COMPILER=icx \ -DCMAKE_CXX_COMPILER=icpx \ - -DLLAMA_OPENSSL=OFF \ -DGGML_NATIVE=OFF \ -DGGML_SYCL_F16=${{ matrix.fp16 }} \ -DGGML_SYCL_SUPPORT_LEVEL_ZERO_API=ON \ @@ -138,8 +150,10 @@ jobs: shell: bash env: - WINDOWS_BASEKIT_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/0cb67a0d-67f6-410b-868b-f4a0a17ff0cf/intel-oneapi-toolkit-2026.1.1.32_offline.exe - WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel:intel.oneapi.win.dnnl:intel.oneapi.win.tbb.devel + WINDOWS_DLE_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/a51104eb-6f4a-4a0e-9dae-1b81b0c81ae1/intel-deep-learning-essentials-2026.1.4.16_offline.exe + WINDOWS_ONEDNN_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/34e28083-d04b-46a3-826c-8c1d00bf1e1c/intel-onednn-2026.0.2.47_offline.exe + WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel:intel.oneapi.win.tbb.devel + WINDOWS_DNNL: intel.oneapi.win.dnnl LEVEL_ZERO_SDK_URL: https://github.com/oneapi-src/level-zero/releases/download/v1.33.1/level-zero-win-sdk-1.33.1.zip ONEAPI_ROOT: "C:/Program Files (x86)/Intel/oneAPI" ONEAPI_INSTALLER_VERSION: "2026.1" @@ -151,7 +165,8 @@ jobs: - name: Download & Install oneAPI shell: bash run: | - scripts/install-oneapi.bat $WINDOWS_BASEKIT_URL $WINDOWS_DPCPP_MKL + scripts/install-oneapi.bat $WINDOWS_DLE_URL $WINDOWS_DPCPP_MKL + scripts/install-oneapi.bat $WINDOWS_ONEDNN_URL $WINDOWS_DNNL - name: Install Level Zero SDK shell: pwsh diff --git a/.github/workflows/build-wasi.yml b/.github/workflows/build-wasi.yml new file mode 100644 index 000000000000..c6dbd66665bc --- /dev/null +++ b/.github/workflows/build-wasi.yml @@ -0,0 +1,142 @@ +name: CI (wasi) + +on: + workflow_dispatch: # allows manual triggering + push: + branches: + - master + paths: [ + '.github/workflows/build-wasi.yml', + '**/CMakeLists.txt', + '**/.cmake', + '**/*.h', + '**/*.hpp', + '**/*.c', + '**/*.cpp', + '**/*.wgsl', + '**/*.tmpl', + 'ggml/src/ggml-webgpu/wgsl-shaders/embed_wgsl.py' + ] + + pull_request: + types: [opened, synchronize, reopened] + paths: [ + '.github/workflows/build-wasi.yml', + '**/CMakeLists.txt', + '**/.cmake', + '**/*.h', + '**/*.hpp', + '**/*.c', + '**/*.cpp', + '**/*.wgsl', + '**/*.tmpl', + 'ggml/src/ggml-webgpu/wgsl-shaders/embed_wgsl.py' + ] + +cache-mode: none +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref && github.ref || github.run_id }} + cancel-in-progress: true + +env: + WASI_SDK_VERSION: 34 + DAWN_VERSION: v20260908.214631 + DAWN_COMMIT: 94c3c9cc0d5fb2e85aebb370fa8d37b71aa34655 + WASI_WEBGPU_HEADERS_COMMIT: 917765edd7cb8f8cf95bda1217514c78f71b582b + +jobs: + ubuntu-webgpu: + runs-on: ubuntu-24.04-arm + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.24 + with: + restore: false + save: false + + - name: Install wasi-sdk + uses: bytecodealliance/setup-wasi-sdk-action@77d09f3df1e8da344d8403cf8631af8977938b4c # v1.0.0 + with: + version: ${{ env.WASI_SDK_VERSION }} + add-to-path: false + + - name: wasi:webgpu Dependency + run: | + mkdir -p wasi-webgpu/dawn-headers + curl -fL "https://github.com/google/dawn/releases/download/${DAWN_VERSION}/dawn-headers-${DAWN_COMMIT}.tar.gz" | + tar -xz -C wasi-webgpu/dawn-headers --strip-components=1 + + git init -q wasi-webgpu/wasi-webgpu-headers + cd wasi-webgpu/wasi-webgpu-headers + git fetch -q --depth 1 https://github.com/wasi-gfx/wasi-webgpu-headers.git ${WASI_WEBGPU_HEADERS_COMMIT} + git checkout -q FETCH_HEAD + git submodule update -q --init --depth 1 + cd ../.. + + # ggml-webgpu does find_package(Dawn) and links dawn::webgpu_dawn. There is no Dawn on WASI, + # so this target instead compiles wasi-webgpu-headers (webgpu.h over wasi:webgpu imports) + # and exposes Dawn's webgpu_cpp.h on top of it. + cat > wasi-webgpu/DawnConfig.cmake << 'EOF' + set(_wasi_webgpu "${CMAKE_CURRENT_LIST_DIR}/wasi-webgpu-headers") + add_library(dawn::webgpu_dawn INTERFACE IMPORTED) + set_target_properties(dawn::webgpu_dawn PROPERTIES + INTERFACE_SOURCES "${_wasi_webgpu}/webgpu.c;${_wasi_webgpu}/async_futures.c;${_wasi_webgpu}/imports.c;${_wasi_webgpu}/imports_component_type.o" + INTERFACE_INCLUDE_DIRECTORIES "${CMAKE_CURRENT_LIST_DIR}/dawn-headers/include/webgpu_upstream;${_wasi_webgpu}") + EOF + + - name: ccache-buckets-restore + uses: ./.github/actions/ccache-buckets + env: + HF_TOKEN: ${{ secrets.HF_TOKEN_CI }} + with: + key: webgpu-ubuntu-24.04-arm-wasi + folder: llama.cpp + hf_bucket: ggml-org/cache + + # llama-common does not build for WASI, so the executables are linked by hand + - name: Build + id: cmake_build + run: | + WASI_FLAGS="-msimd128 -D_WASI_EMULATED_SIGNAL -fwasm-exceptions -mllvm -wasm-use-legacy-eh=false" + cmake -B build-wasi \ + -G "Ninja" \ + -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p3.cmake \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_C_FLAGS="${WASI_FLAGS}" \ + -DCMAKE_CXX_FLAGS="${WASI_FLAGS}" \ + -DCMAKE_HAVE_LIBC_PTHREAD=1 \ + -DBUILD_SHARED_LIBS=OFF \ + -DGGML_NATIVE=OFF \ + -DGGML_OPENMP=OFF \ + -DGGML_WEBGPU=ON \ + -DDawn_DIR=$PWD/wasi-webgpu \ + -DLLAMA_BUILD_COMMON=OFF + + time cmake --build build-wasi --config Release --target llama -j $(nproc) + + LIBS="build-wasi/ggml/src/libggml.a build-wasi/ggml/src/ggml-webgpu/libggml-webgpu.a build-wasi/ggml/src/libggml-cpu.a build-wasi/ggml/src/libggml-base.a" + LDFLAGS="-lunwind -ldl -Wl,-z,stack-size=8388608" + CXX="${WASI_SDK_PATH}/bin/clang++ --target=wasm32-wasip3 -O3 -std=c++17 ${WASI_FLAGS} -I include -I ggml/include" + + $CXX examples/simple/simple.cpp build-wasi/src/libllama.a $LIBS $LDFLAGS -o build-wasi/llama-simple.wasm + $CXX tests/test-backend-ops.cpp $LIBS $LDFLAGS -o build-wasi/test-backend-ops.wasm + + - name: ccache-buckets-save + if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} + uses: ./.github/actions/ccache-buckets + env: + HF_TOKEN: ${{ secrets.HF_TOKEN_CACHE_OUTPUT }} + with: + key: webgpu-ubuntu-24.04-arm-wasi + folder: llama.cpp + evict-old-files: 1d + hf_bucket: ggml-org/cache + save: true diff --git a/.github/workflows/build-webgpu.yml b/.github/workflows/build-webgpu.yml index d00106439753..88f2c6f5dfa2 100644 --- a/.github/workflows/build-webgpu.yml +++ b/.github/workflows/build-webgpu.yml @@ -7,15 +7,7 @@ on: - master paths: [ '.github/workflows/build-webgpu.yml', - '**/CMakeLists.txt', - '**/.cmake', - '**/*.h', - '**/*.hpp', - '**/*.c', - '**/*.cpp', - '**/*.wgsl', - '**/*.tmpl', - 'ggml/src/ggml-webgpu/wgsl-shaders/embed_wgsl.py' + 'ggml/src/ggml-webgpu/**' ] pull_request: @@ -63,135 +55,3 @@ jobs: -type f \( -name '*.cpp' -o -name '*.hpp' -o -name '*.h' \) \ -print0 | xargs -0 clang-format-22 --dry-run --Werror - - macos: - runs-on: macos-latest - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: ccache - uses: ggml-org/ccache-action@v1.2.24 - with: - restore: false - save: false - - - name: Dawn Dependency - id: dawn-depends - run: | - DAWN_VERSION="v20260908.214631" - DAWN_OWNER="google" - DAWN_REPO="dawn" - DAWN_ASSET_NAME="Dawn-94c3c9cc0d5fb2e85aebb370fa8d37b71aa34655-macos-latest-Release" - echo "Fetching release asset from https://github.com/google/dawn/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}.tar.gz" - curl -L -o artifact.tar.gz \ - "https://github.com/google/dawn/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}.tar.gz" - mkdir dawn - tar -xvf artifact.tar.gz -C dawn --strip-components=1 - - - name: ccache-buckets-restore - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CI }} - with: - key: webgpu-macos-latest - folder: llama.cpp - hf_bucket: ggml-org/cache - - - name: Build - id: cmake_build - run: | - export CMAKE_PREFIX_PATH=dawn - cmake -B build -G "Ninja" -DCMAKE_BUILD_TYPE=Release -DGGML_WEBGPU=ON -DGGML_METAL=OFF -DGGML_BLAS=OFF - time cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) - - - name: ccache-buckets-save - if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CACHE_OUTPUT }} - with: - key: webgpu-macos-latest - folder: llama.cpp - evict-old-files: 1d - hf_bucket: ggml-org/cache - save: true - - - name: Test - id: cmake_test - run: | - cd build - ctest -L main --verbose --timeout 900 - - ubuntu: - runs-on: ubuntu-24.04 - - steps: - - name: Clone - id: checkout - uses: actions/checkout@v6 - - - name: ccache - uses: ggml-org/ccache-action@v1.2.24 - with: - restore: false - save: false - - - name: Dependencies - id: depends - run: | - sudo add-apt-repository -y ppa:kisak/kisak-mesa - sudo apt-get update -y - sudo apt-get install -y build-essential mesa-vulkan-drivers \ - libxcb-xinput0 libxcb-xinerama0 libxcb-cursor-dev libssl-dev - - - name: Dawn Dependency - id: dawn-depends - run: | - sudo apt-get install -y libxrandr-dev libxinerama-dev libxcursor-dev mesa-common-dev libx11-xcb-dev libxi-dev - DAWN_VERSION="v20260908.214631" - DAWN_OWNER="google" - DAWN_REPO="dawn" - DAWN_ASSET_NAME="Dawn-94c3c9cc0d5fb2e85aebb370fa8d37b71aa34655-ubuntu-latest-Release" - echo "Fetching release asset from https://github.com/google/dawn/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}.tar.gz" - curl -L -o artifact.tar.gz \ - "https://github.com/google/dawn/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}.tar.gz" - mkdir dawn - tar -xvf artifact.tar.gz -C dawn --strip-components=1 - - - name: ccache-buckets-restore - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CI }} - with: - key: webgpu-ubuntu-24.04 - folder: llama.cpp - hf_bucket: ggml-org/cache - - - name: Build - id: cmake_build - run: | - export Dawn_DIR=dawn/lib64/cmake/Dawn - cmake -B build \ - -DGGML_WEBGPU=ON - time cmake --build build --config Release -j $(nproc) - - - name: ccache-buckets-save - if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} - uses: ./.github/actions/ccache-buckets - env: - HF_TOKEN: ${{ secrets.HF_TOKEN_CACHE_OUTPUT }} - with: - key: webgpu-ubuntu-24.04 - folder: llama.cpp - evict-old-files: 1d - hf_bucket: ggml-org/cache - save: true - - - name: Test - id: cmake_test - run: | - cd build - ctest -L main --verbose --timeout 900 diff --git a/.github/workflows/ci-self-hosted-cpu.yml b/.github/workflows/ci-self-hosted-cpu.yml index eb40baa88e6b..7152c4de8725 100644 --- a/.github/workflows/ci-self-hosted-cpu.yml +++ b/.github/workflows/ci-self-hosted-cpu.yml @@ -46,7 +46,7 @@ env: jobs: cpu-x64-high-perf: - runs-on: [self-hosted, Linux, X64] + runs-on: [self-hosted, Linux, X64, CPU] steps: - name: Clone @@ -56,7 +56,7 @@ jobs: - name: Test id: ggml-ci run: | - LLAMA_ARG_THREADS=$(nproc) GG_BUILD_HIGH_PERF=1 GG_BUILD_EXTRA_TESTS_0=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + LLAMA_ARG_THREADS=$(nproc) GG_BUILD_HIGH_PERF=1 GG_BUILD_EXTRA_TESTS_0=1 bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp cpu-arm64-high-perf-graviton4: runs-on: ah-ubuntu_24_04-c8g_8x diff --git a/.github/workflows/ci-self-hosted-metal.yml b/.github/workflows/ci-self-hosted-metal.yml index 5eb20096a484..226bc8f6dd55 100644 --- a/.github/workflows/ci-self-hosted-metal.yml +++ b/.github/workflows/ci-self-hosted-metal.yml @@ -60,4 +60,4 @@ jobs: - name: Test id: ggml-ci run: | - GG_BUILD_METAL=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + GG_BUILD_METAL=1 bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp diff --git a/.github/workflows/ci-self-hosted-vulkan.yml b/.github/workflows/ci-self-hosted-vulkan.yml index e651f2d1db56..1ce68bfe0a0b 100644 --- a/.github/workflows/ci-self-hosted-vulkan.yml +++ b/.github/workflows/ci-self-hosted-vulkan.yml @@ -79,7 +79,7 @@ jobs: id: ggml-ci run: | vulkaninfo --summary - GG_BUILD_VULKAN=1 GGML_VK_DISABLE_COOPMAT2=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + GG_BUILD_VULKAN=1 GGML_VK_DISABLE_COOPMAT2=1 bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp # - name: ccache-buckets-save # if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} @@ -124,7 +124,7 @@ jobs: id: ggml-ci run: | vulkaninfo --summary - GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp # - name: ccache-buckets-save # if: ${{ github.event_name == 'push' && github.ref == 'refs/heads/master' }} @@ -150,7 +150,7 @@ jobs: id: ggml-ci run: | vulkaninfo --summary - GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp gpu-vulkan-intel-linux: runs-on: [self-hosted, Linux, Intel] diff --git a/.github/workflows/ci-self-hosted-webgpu.yml b/.github/workflows/ci-self-hosted-webgpu.yml index 316ed33b91c7..e2ef40cd25d1 100644 --- a/.github/workflows/ci-self-hosted-webgpu.yml +++ b/.github/workflows/ci-self-hosted-webgpu.yml @@ -58,7 +58,12 @@ jobs: - name: Install dependencies run: | sudo apt update - sudo apt install -y build-essential cmake libxcb-xinput0 libxcb-xinerama0 libxcb-cursor-dev libvulkan1 mesa-vulkan-drivers libglvnd0 libgl1 libglx0 libegl1 libgles2 libssl-dev time unzip wget python3 python3-venv python3-pip + sudo apt install -y software-properties-common + sudo add-apt-repository ppa:deadsnakes/ppa + sudo apt update + sudo apt install -y build-essential cmake libxcb-xinput0 libxcb-xinerama0 libxcb-cursor-dev libvulkan1 mesa-vulkan-drivers libglvnd0 libgl1 libglx0 libegl1 libgles2 libssl-dev time unzip wget python3.12 python3.12-venv + sudo update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.12 1 + sudo update-alternatives --config python3 - name: ccache uses: ggml-org/ccache-action@v1.2.24 @@ -131,4 +136,4 @@ jobs: id: ggml-ci run: | GG_BUILD_WEBGPU=1 GG_BUILD_WEBGPU_DAWN_PREFIX="$GITHUB_WORKSPACE/dawn" \ - bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + bash ./ci/run.sh ~/results/llama.cpp/$RUNNER_NAME ~/mnt/llama.cpp diff --git a/.github/workflows/make-release.yml b/.github/workflows/make-release.yml index 57c3a04a577f..2e5e44caaab8 100644 --- a/.github/workflows/make-release.yml +++ b/.github/workflows/make-release.yml @@ -61,8 +61,17 @@ jobs: RELEASE_BRANCH: ${{ github.ref_name }} SKIP_APIABI_CHECK: ${{ github.event.inputs.skip_apiabi_check }} APIABI_COMPARE_TAG: ${{ github.event.inputs.apiabi_compare_tag }} + APIABI_REPORT_DIR: ${{ runner.temp }}/apiabi-reports REQUIRE_DOCKER: ${{ github.event.inputs.require_docker }} + - name: Upload API/ABI reports + if: ${{ always() && github.event.inputs.skip_apiabi_check != 'true' }} + uses: actions/upload-artifact@v7 + with: + name: apiabi-reports + path: ${{ runner.temp }}/apiabi-reports + if-no-files-found: ignore + - name: Create release tag if: ${{ github.event.inputs.dry_run == 'false' }} run: | diff --git a/.github/workflows/python-type-check.yml b/.github/workflows/python-type-check.yml index 5be177e9c504..8fb4ffd47a7c 100644 --- a/.github/workflows/python-type-check.yml +++ b/.github/workflows/python-type-check.yml @@ -35,7 +35,7 @@ jobs: uses: actions/setup-python@v6 with: python-version: "3.11" - pip-install: -r requirements/requirements-all.txt ty==0.0.84 + pip-install: -r requirements/requirements-all.txt ty==0.0.88 # - name: Type-check with Pyright # uses: jakebailey/pyright-action@v2 # with: diff --git a/.github/workflows/release-publish.yml b/.github/workflows/release-publish.yml index 39b6753a16b6..243b870e6664 100644 --- a/.github/workflows/release-publish.yml +++ b/.github/workflows/release-publish.yml @@ -172,6 +172,8 @@ jobs: - [Ubuntu x64 (CPU)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-x64.tar.gz) - [Ubuntu arm64 (CPU)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-arm64.tar.gz) - [Ubuntu s390x (CPU)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-s390x.tar.gz) + - [Ubuntu 26.04 s390x (CPU)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-26.04-s390x.tar.gz) + - [Ubuntu 26.04 s390x (zDNN)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-zdnn-s390x.tar.gz) - [Ubuntu x64 (Vulkan)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-vulkan-x64.tar.gz) - [Ubuntu arm64 (Vulkan)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-vulkan-arm64.tar.gz) - [Ubuntu x64 (CUDA 12)](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/llama-${{ steps.tag.outputs.name }}-bin-ubuntu-cuda-12.8-x64.tar.gz) - [CUDA 12.8 libraries](https://github.com/ggml-org/llama.cpp/releases/download/${{ steps.tag.outputs.name }}/cudart-llama-${{ steps.tag.outputs.name }}-bin-ubuntu-cuda-12.8-x64.tar.gz) diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 9745230f500c..acda37fb9cfc 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -35,7 +35,7 @@ permissions: env: GH_TOKEN: ${{ github.token }} BRANCH_NAME: ${{ github.head_ref || github.ref_name }} - CMAKE_ARGS: "-DLLAMA_BUILD_EXAMPLES=OFF -DLLAMA_BUILD_TESTS=OFF -DLLAMA_BUILD_TOOLS=ON -DLLAMA_BUILD_SERVER=ON -DGGML_RPC=ON" + CMAKE_ARGS: "-DLLAMA_BUILD_EXAMPLES=OFF -DLLAMA_BUILD_TESTS=OFF -DLLAMA_BUILD_TOOLS=ON -DLLAMA_BUILD_SERVER=ON -DGGML_RPC=ON -DLLAMA_CONNECT=ON" # note: run this workflow one at a time for better cache reuse concurrency: @@ -180,6 +180,8 @@ jobs: os: ubuntu-24.04-arm - build: 's390x' os: ubuntu-24.04-s390x + - build: '26.04-s390x' + os: ubuntu-26.04-s390x runs-on: ${{ matrix.os }} @@ -200,7 +202,7 @@ jobs: id: depends run: | sudo apt-get update - sudo apt-get install build-essential libssl-dev + sudo apt-get install -y build-essential libssl-dev - name: Toolchain workaround (GCC 14) if: ${{ contains(matrix.os, 'ubuntu-24.04') }} @@ -210,7 +212,7 @@ jobs: echo "CXX=g++-14" >> "$GITHUB_ENV" - name: ccache - if: ${{ matrix.build != 's390x' }} + if: ${{ !contains(matrix.os, 's390x') }} uses: ggml-org/ccache-action@v1.2.24 with: key: release-${{ matrix.os }}-cpu @@ -242,7 +244,7 @@ jobs: archive: false - name: ccache-clear - if: ${{ matrix.build != 's390x' }} + if: ${{ !contains(matrix.os, 's390x') }} uses: ./.github/actions/ccache-clear with: key: release-${{ matrix.os }}-cpu @@ -547,7 +549,7 @@ jobs: if: ${{ needs.check-release.outputs.should_release == 'true' }} runs-on: ubuntu-latest - container: 'ghcr.io/snapdragon-toolchain/arm64-android:v0.7' + container: 'ghcr.io/snapdragon-toolchain/arm64-android:v0.8' defaults: run: @@ -600,7 +602,7 @@ jobs: if: ${{ needs.check-release.outputs.should_release == 'true' }} runs-on: ubuntu-latest - container: 'ghcr.io/snapdragon-toolchain/arm64-linux:v0.7' + container: 'ghcr.io/snapdragon-toolchain/arm64-linux:v0.8' defaults: run: @@ -968,6 +970,11 @@ jobs: evict-old-files: 1d max-size: "1G" + - name: Tune ccache for ROCm + run: | + # since ROCm 10.1, clang -E output has no GPU code, so the preprocessor fallback can reuse objects with old GPU code + ccache --set-config=depend_mode=true + # - name: Cache ROCm Installation # id: cache-rocm # uses: actions/cache@v5 @@ -1300,8 +1307,11 @@ jobs: shell: bash env: - WINDOWS_BASEKIT_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/0cb67a0d-67f6-410b-868b-f4a0a17ff0cf/intel-oneapi-toolkit-2026.1.1.32_offline.exe - WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel:intel.oneapi.win.dnnl:intel.oneapi.win.tbb.devel + WINDOWS_DLE_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/a51104eb-6f4a-4a0e-9dae-1b81b0c81ae1/intel-deep-learning-essentials-2026.1.4.16_offline.exe + WINDOWS_ONEDNN_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/34e28083-d04b-46a3-826c-8c1d00bf1e1c/intel-onednn-2026.0.2.47_offline.exe + WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel:intel.oneapi.win.tbb.devel + WINDOWS_DNNL: intel.oneapi.win.dnnl + LEVEL_ZERO_SDK_URL: https://github.com/oneapi-src/level-zero/releases/download/v1.33.1/level-zero-win-sdk-1.33.1.zip ONEAPI_ROOT: "C:/Program Files (x86)/Intel/oneAPI" ONEAPI_INSTALLER_VERSION: "2026.1" @@ -1314,7 +1324,8 @@ jobs: - name: Download & Install oneAPI shell: bash run: | - scripts/install-oneapi.bat $WINDOWS_BASEKIT_URL $WINDOWS_DPCPP_MKL + scripts/install-oneapi.bat $WINDOWS_DLE_URL $WINDOWS_DPCPP_MKL + scripts/install-oneapi.bat $WINDOWS_ONEDNN_URL $WINDOWS_DNNL - name: Install Level Zero SDK shell: pwsh @@ -1425,8 +1436,15 @@ jobs: shell: bash run: | cd /tmp - wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/5996e26b-f48a-42b1-8db0-b002ad0bd8d7/intel-oneapi-toolkit-2026.1.1.33_offline.sh -O intel-oneapi-toolkit_offline.sh - sudo bash intel-oneapi-toolkit_offline.sh -s -a --silent --eula accept + echo "Download oneAPI Deep Learning Essentials installation package" + wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/b5c100a7-8052-4e88-90e2-63d9916a998b/intel-deep-learning-essentials-2026.1.4.17_offline.sh -O intel-deep-learning-essentials_offline.sh + echo "Install oneAPI Deep Learning Essentials components" + sudo bash intel-deep-learning-essentials_offline.sh -s -a --silent --eula accept + + echo "Download oneDNN installation package" + wget https://registrationcenter-download.intel.com/akdlm/IRC_NAS/94c3dbac-0852-45be-a57d-21c204cada3e/intel-onednn-2026.0.2.46_offline.sh -O intel-onednn_offline.sh + echo "Install oneDNN components" + sudo bash intel-onednn_offline.sh -s -a --silent --eula accept - name: Install Level Zero SDK shell: bash @@ -1442,6 +1460,12 @@ jobs: name: llama-ui.zip path: tools/ui/dist + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install -y libssl-dev + - name: ccache uses: ggml-org/ccache-action@v1.2.24 with: @@ -1460,8 +1484,8 @@ jobs: -DCMAKE_CXX_COMPILER=icpx \ -DCMAKE_INSTALL_RPATH='$ORIGIN' \ -DCMAKE_BUILD_WITH_INSTALL_RPATH=ON \ - -DLLAMA_OPENSSL=OFF \ -DGGML_NATIVE=OFF \ + -DLLAMA_CONNECT=ON \ -DGGML_SYCL_F16=${{ matrix.fp16 }} time cmake --build build --config Release -j $(nproc) @@ -1528,6 +1552,8 @@ jobs: # builds hit. ccache --set-config=compiler_check=content ccache --set-config=sloppiness=time_macros,include_file_mtime,include_file_ctime + # since ROCm 10.1, clang -E output has no GPU code, so the preprocessor fallback can reuse objects with old GPU code + ccache --set-config=depend_mode=true - name: Dependencies id: depends @@ -1602,6 +1628,60 @@ jobs: with: key: release-ubuntu-24.04-rocm-${{ matrix.ROCM_VERSION }}-${{ matrix.build }} + ubuntu-26-zdnn: + needs: [check-release, ui-build] + if: ${{ needs.check-release.outputs.should_release == 'true' }} + + runs-on: ubuntu-26.04-s390x + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v6 + with: + fetch-depth: 0 + + - name: Download UI build + uses: actions/download-artifact@v8 + with: + name: llama-ui.zip + path: tools/ui/dist + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install -y --no-install-recommends \ + build-essential libssl-dev libzdnn-dev + + - name: Build + id: cmake_build + run: | + cmake -B build \ + -DCMAKE_INSTALL_RPATH='$ORIGIN' \ + -DCMAKE_BUILD_WITH_INSTALL_RPATH=ON \ + -DGGML_BACKEND_DL=ON \ + -DGGML_NATIVE=OFF \ + -DGGML_VXE=ON \ + -DGGML_ZDNN=ON \ + -DCMAKE_C_FLAGS="-march=arch15" \ + -DCMAKE_CXX_FLAGS="-march=arch15" \ + -DLLAMA_FATAL_WARNINGS=ON \ + ${{ env.CMAKE_ARGS }} + cmake --build build --config Release -j $(nproc) + + - name: Pack artifacts + id: pack_artifacts + run: | + cp LICENSE ./build/bin/ + tar -czvf llama-${{ needs.check-release.outputs.tag_name }}-bin-ubuntu-zdnn-s390x.tar.gz --transform "s,^\.,llama-${{ needs.check-release.outputs.tag_name }}," -C ./build/bin . + + - name: Upload artifacts + uses: actions/upload-artifact@v7 + with: + path: llama-${{ needs.check-release.outputs.tag_name }}-bin-ubuntu-zdnn-s390x.tar.gz + archive: false + ios-xcode: needs: [check-release] if: ${{ needs.check-release.outputs.should_release == 'true' }} diff --git a/.pi/gg/APPEND_SYSTEM.md b/.pi/gg/APPEND_SYSTEM.md new file mode 100644 index 000000000000..dd79897e3aa0 --- /dev/null +++ b/.pi/gg/APPEND_SYSTEM.md @@ -0,0 +1,6 @@ + +Project-specific instructions: + +## Coding + +- In `test-backend-ops.cpp`, do not mention specific backends (e.g. Metal, CUDA) in comments diff --git a/.pi/gg/SYSTEM.md b/.pi/gg/SYSTEM.md deleted file mode 100644 index 8b8b8a1586fa..000000000000 --- a/.pi/gg/SYSTEM.md +++ /dev/null @@ -1,33 +0,0 @@ -You are a coding agent. Here are some very important rules that you must follow: - -General: -- Be very precise and concise when writing code, comments, explanations, etc. -- If an inline comment exceeds 2 lines, replace it with: `// note: TODO LATER` -- PR and commit titles format: ` : `. Lookup recents for examples -- Don't try to build or run the code unless you are explicitly asked to do so -- Use the `gh` CLI tool when querying PRs, issues, or other GitHub resources -- When [MODEL] is needed, first try to get it from the `PI_MODEL_NAME` env var before asking the user -- Never read the `AGENTS.md` file - -Coding: -- When in doubt, always refer to the CONTRIBUTING.md file of the project -- In `test-backend-ops.cpp`, do not mention specific backends (e.g. Metal, CUDA) in comments -- When referencing issues or PRs in comments, use the format: - - C/C++ code: `// ref: <url>` - - Other (CMake, etc.): `# ref: <url>` - -Pull requests (PRs): -- New branch names are prefixed with "gg/" -- Before opening a pull request, ask the user to confirm the description -- Don't explicitly wrap lines in the PR description (each paragraph and bullet is a single line) -- When creating a pull request, look for the repository's PR template and follow it -- For the AI usage disclosure section, write "YES. pi:llama.cpp/[MODEL]" -- If `PI_MODEL_NAME` env var is not set, ask the user to tell you what model was used and write it in place of [MODEL] -- Always create the pull requests in draft mode -- Never reply to review comments or post comments on issues/PRs without explicit permission from the user - -Commits: -- On every commit that you make, include a "Assisted-by: pi:llama.cpp/[MODEL]" tag -- Do not explicitly set the git author in commits - rely on the default git config -- Always use `--no-gpg-sign` when committing -- Never `git push` without explicit confirmation from the user diff --git a/AGENTS.md b/AGENTS.md index 3ae583b82bae..36390a6b4ad6 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -246,3 +246,6 @@ Chat template and parser: - [PEG parser](docs/development/parsing.md) - alternative to regex that llama.cpp uses to parse model's output - [Auto parser](docs/autoparser.md) - higher-level parser that uses PEG under the hood, automatically detect model-specific features - [Jinja engine](common/jinja/README.md) + +Testing: +- [Slice model](skills/slice-model/SKILL.md) - build a small slice (few layers/experts) of a big HF model without downloading the full weights, to test conversion and inference diff --git a/AUTHORS b/AUTHORS index ea17fb76e5fc..14921cde5499 100644 --- a/AUTHORS +++ b/AUTHORS @@ -1,4 +1,4 @@ -# date: Fri Sep 4 10:06:46 EEST 2026 +# date: Wed Oct 28 12:38:26 EET 2026 # this file is auto-generated by scripts/gen-authors.sh Нияз Гарифзянов <112617865+garrnizon@users.noreply.github.com> @@ -25,9 +25,13 @@ 4onen <11580688+4onen@users.noreply.github.com> 65a <10104049+65a@users.noreply.github.com> 708-145 <40387547+708-145@users.noreply.github.com> +7konigsberg <77811205+7konigsberg@users.noreply.github.com> +92es <76127081+92es@users.noreply.github.com> A B <abawany@users.noreply.github.com> +a u s t i n <135388519+xarillian@users.noreply.github.com> a-huk <56552991+a-huk@users.noreply.github.com> a-n-n-a-l-e-e <150648636+a-n-n-a-l-e-e@users.noreply.github.com> +A-Raphie <60940271+A-Raphie@users.noreply.github.com> a3894281 <a3894281@gmail.com> a3sh <38979186+A3shTnT@users.noreply.github.com> aa956 <aa956@users.noreply.github.com> @@ -48,10 +52,12 @@ Abhilash Majumder <30946547+abhilash1910@users.noreply.github.com> Abhinay Krishna <abhinaykrishna60@gmail.com> Abhiram <78226909+geckguy@users.noreply.github.com> Abhishek Gopinath K <31348521+overtunned@users.noreply.github.com> +Abir Deol <abir.deol2006@gmail.com> abotsis <github@bots.is> Abraham Gonzalez <theabecaster0@gmail.com> Acly <aclysia@gmail.com> Adam <channeladam@users.noreply.github.com> +Adam Caldwell <2320451+accaldwell@users.noreply.github.com> adavyas <121313528+adavyas@users.noreply.github.com> adel boussaken <netdur@gmail.com> adgup-qti <adgup@qti.qualcomm.com> @@ -72,6 +78,7 @@ ag2s20150909 <19373730+ag2s20150909@users.noreply.github.com> agent-enemy-2 <agentenemy2@gmail.com> AgoraPete <peter.haughie@agora-thinktanks.org> agray3 <agray3@users.noreply.github.com> +Agustín Mista <agustin@mista.me> Ahmad Tameem <113388789+Tameem-10xE@users.noreply.github.com> Ahmet Zeer <ahmed.zeer@std.yildiz.edu.tr> ai-fonsi <length-amiss-7k@icloud.com> @@ -79,6 +86,7 @@ aic0d3r <168572732+aic0d3r@users.noreply.github.com> Aidan <99101158+gSUz92nc@users.noreply.github.com> AidanBeltonS <87009434+AidanBeltonS@users.noreply.github.com> AidanBeltonS <aidan.belton@codeplay.com> +aiqubits <aiqubits@hotmail.com> Aisuko <urakiny@gmail.com> Akarshan Biswas <akarshan.biswas@gmail.com> Akarshan Biswas <akarshan@menlo.ai> @@ -88,6 +96,7 @@ akleine <alb.kleine@gmx.de> Al G <toasting@gmail.com> Al Mochkin <14274697+amochkin@users.noreply.github.com> Alan Gray <agray3@users.noreply.github.com> +Alan Tseng <alan.tseng.cs@gmail.com> Alan Tseng <alanhc.tseng1999@gmail.com> Alawode Oluwandabira <dabiraalawode@yahoo.com> Albert Jin <albert.jin@gmail.com> @@ -105,6 +114,7 @@ Aleksei Nikiforov <103434461+AlekseiNikiforovIBM@users.noreply.github.com> Alessandro de Oliveira Faria (A.K.A.CABELO) <cabelo@opensuse.org> Alessandro98-git <61804547+Alessandro98-git@users.noreply.github.com> Alex <18387287+wadealexc@users.noreply.github.com> +Alex <59368173+AlexGabbia@users.noreply.github.com> Alex <awhill19@icloud.com> Alex Azarov <alex@azarov.by> Alex Azarov <alexander.azarov@mapbox.com> @@ -112,6 +122,7 @@ Alex Brooks <alex.brooks@ibm.com> Alex Fanthome <xfanth@gmail.com> Alex Klinkhamer <from.github.com.917@grencez.dev> Alex Klinkhamer <git@grencez.dev> +Alex Morgan <36094800+amitmi704@users.noreply.github.com> Alex Nguyen <tiendung@users.noreply.github.com> Alex O'Connell <35843486+acon96@users.noreply.github.com> Alex Petenchea <alex.petenchea@gmail.com> @@ -126,6 +137,7 @@ Alexander Heisler <126129661+heislera763@users.noreply.github.com> Alexey Dubrov <nevermind1025@gmail.com> Alexey Kopytko <alexey@kopytko.com> Alexey Parfenov <zxed@alkatrazstudio.net> +alexey-rsi <alexey@recursive.com> Alexis Williams <typedrat@users.noreply.github.com> alexpinel <93524949+alexpinel@users.noreply.github.com> Alfred <zxu3@clemson.edu> @@ -137,9 +149,11 @@ Alon <alonfaraj@gmail.com> alonfaraj <alonfaraj@gmail.com> AlpinDale <52078762+AlpinDale@users.noreply.github.com> alwqx <kenan3015@gmail.com> +Amadeus dyw <74057036+SG-Amadeus@users.noreply.github.com> Aman <amangupta052@gmail.com> Aman Chadha(IVIXMMI) <79802170+ac-mmi@users.noreply.github.com> Aman Gupta <amangupta052@gmail.com> +Aman Karki <amankarki151@gmail.com> Aman Karki <itsamankarki@gmail.com> amd-dwang <dong.wang@amd.com> amd-lalithnc <lalithnc@amd.com> @@ -151,7 +165,9 @@ amritahs-ibm <amritahs@linux.vnet.ibm.com> An Long <aisk@users.noreply.github.com> AN Long <aisk@users.noreply.github.com> Anand Patil <126432639+AnandPatil1@users.noreply.github.com> +Anant Shrivastava <anant@anantshri.info> Ananta Bastola <anantarajbastola@gmail.com> +Anas <alhachemi.anas@proton.me> Anas Ahouzi <112881240+aahouzi@users.noreply.github.com> Anav Prasad <anavp@nvidia.com> anavp-nvidia <anavp@nvidia.com> @@ -160,6 +176,7 @@ Andika Wasisto <andika@wasisto.com> András Salamon <ott2@users.noreply.github.com> Andrea Arcangeli <aarcange@redhat.com> Andrea Richiardi <a.richiardi.work@gmail.com> +Andrea Rossetti <rossettiandrea@proton.me> Andreas (Andi) Kunar <andreask@msn.com> Andreas Kieslinger <47689530+aendk@users.noreply.github.com> Andreas Krebbel <krebbel@linux.ibm.com> @@ -170,6 +187,7 @@ Andrew Canis <andrew.canis@gmail.com> Andrew Downing <andrew2085@gmail.com> Andrew Duffy <a10y@users.noreply.github.com> Andrew Godfrey <AndrewGodfrey@users.noreply.github.com> +Andrew Lee <andysl@gmail.com> Andrew Marshall <andrew@johnandrewmarshall.com> Andrew Minh Nguyen <40281306+amqdn@users.noreply.github.com> Andrew Smith <atsmith19@comcast.net> @@ -179,11 +197,15 @@ Andy Tai <andy-tai@users.noreply.github.com> Andy Williams <8692+sobakasu@users.noreply.github.com> andyluo7 <43718156+andyluo7@users.noreply.github.com> Angel Galindo <131726962+AngelGalindo7@users.noreply.github.com> +Animesh <animeshsri.official@gmail.com> +Anjielon <angelo.mogavero@gmail.com> +Ankit Khandelwal <ankk98@gmail.com> Ankur Verma <31362771+ankurvdev@users.noreply.github.com> anon998 <131767832+anon998@users.noreply.github.com> Anri Lombard <anri.m.lombard@gmail.com> Anthony Umfer <aumfer@gmail.com> Anthony Van de Gejuchte <anthonyvdgent@gmail.com> +Anthony Wang <anthonywang903@gmail.com> antichristHater <142441588+antichristHater@users.noreply.github.com> Antoine Viallon <antoine@lesviallon.fr> Anton Mitkov <anton_b_mitkov@abv.bg> @@ -197,6 +219,7 @@ Aparna M P <aparmp@qti.qualcomm.com> Aparna M P <quic_aparmp@quicinc.com> apaz <aarpazdera@gmail.com> apcameron <37645737+apcameron@users.noreply.github.com> +Apoorv Parle <19315187+apparle@users.noreply.github.com> arch-btw <57669023+arch-btw@users.noreply.github.com> arcrank <arcrank@gmail.com> ardfork <134447697+ardfork@users.noreply.github.com> @@ -205,10 +228,13 @@ Aritro Bandyopadhyay <71339004+AriBandyo@users.noreply.github.com> arlo-phoenix <140345165+arlo-phoenix@users.noreply.github.com> Armen Kaleshian <kriation@users.noreply.github.com> Arsen Arutunan <58118221+limloop@users.noreply.github.com> +Arseniy Obolenskiy <good.doog.2012@gmail.com> Artem <guinmoon@gmail.com> Artem Zinnatullin <ceo@abstractny.gay> Artyom Lebedev <vagran.ast@gmail.com> aryantandon01 <80969509+aryantandon01@users.noreply.github.com> +Asahi-Prv <asahihori7@gmail.com> +asbelin <71226900+asbelin@users.noreply.github.com> Asbjørn Olling <asbjornolling@gmail.com> asf0 <scorpionspfc@gmail.com> Ásgeir Bjarni Ingvarsson <asgeir@fundinn.org> @@ -222,6 +248,7 @@ Atharva Dubey <atharva.dubey@codeplay.com> Atomic-Germ <97569476+Atomic-Germ@users.noreply.github.com> Atsushi Tatsuma <yoshoku@outlook.com> aubreyli <aubreylee@gmail.com> +AuroraRAS <chplee@gmail.com> Austin <77757836+teleprint-me@users.noreply.github.com> AustinMroz <austinmroz@utexas.edu> AUTOMATIC1111 <16777216c@gmail.com> @@ -232,6 +259,7 @@ Bach Le <bach@bullno1.com> BADR <contact@pythops.com> bagheera <59658056+bghira@users.noreply.github.com> Bailey Chittle <39804642+bachittle@users.noreply.github.com> +Bálint Bokros <bbalint96@gmail.com> bandoti <141645996+bandoti@users.noreply.github.com> Bar Haim <barvhaim@gmail.com> BarfingLemurs <128182951+BarfingLemurs@users.noreply.github.com> @@ -242,6 +270,7 @@ Bartowski <ckealty1182@gmail.com> Bas Nijholt <basnijholt@gmail.com> bashayer hijji <bashayer.hijji@gmail.com> BB-fat <45072480+BB-fat@users.noreply.github.com> +begcdn <150344566+begcdn@users.noreply.github.com> Behnam M <58621210+ibehnam@users.noreply.github.com> beiller <beiller@gmail.com> Beinsezii <39478211+Beinsezii@users.noreply.github.com> @@ -253,6 +282,7 @@ Ben Guidarelli <ben.guidarelli@gmail.com> Ben Racicot <1815385+BenRacicot@users.noreply.github.com> Ben Siraphob <bensiraphob@gmail.com> Ben Williams <ben@719ben.com> +Benjamin Babik <ben@curlyben.com> Benjamin Findley <39356821+Kartoffelsaft@users.noreply.github.com> Benjamin Lecaillon <84293038+blecaillon@users.noreply.github.com> Benni <73313922+BenjaminBruenau@users.noreply.github.com> @@ -269,6 +299,7 @@ Bill Sideris <bill88t@feline.gr> Billel Mokeddem <billel.mokeddem.ml@gmail.com> Bingan <70050083+binganao@users.noreply.github.com> Bipin Yadav <83943505+bipinyadav3175@users.noreply.github.com> +bitalov <60072763+bitalov@users.noreply.github.com> Bizhao Shi <37729561+shibizhao@users.noreply.github.com> Bjarke Viksøe <164612031+bviksoe@users.noreply.github.com> Björn Ganster <mail@bjoern-ganster.de> @@ -283,10 +314,12 @@ Boian Berberov <7432115+bberberov@users.noreply.github.com> Bono Lv <lvscar@users.noreply.github.com> Borislav Stanimirov <b.stanimirov@abv.bg> Borislav Stanimirov <b@ibob.bg> +bosh <98094229+boshjerns@users.noreply.github.com> Bowen Han <fancycode@gmail.com> Brad Smith <1472326+infinitewarp@users.noreply.github.com> Branden Butler <bwtbutler@hotmail.com> Brandon Squizzato <35474886+bsquizz@users.noreply.github.com> +bri-prism <288398250+bri-prism@users.noreply.github.com> Brian <mofosyne@gmail.com> Brian Cunnie <brian.cunnie@gmail.com> Bruce MacDonald <brucewmacdonald@gmail.com> @@ -295,12 +328,17 @@ Bryan Honof <bryanhonof@gmail.com> bryanSwk <93190252+bryanSwk@users.noreply.github.com> bsilvereagle <bsilvereagle@users.noreply.github.com> bssrdf <merlintiger@hotmail.com> +budiony <budiony@gmail.com> Buğra Özgürsoy <13810383+ozgursoy@users.noreply.github.com> byte-6174 <88070277+byte-6174@users.noreply.github.com> +Caladrel <jnf333@gmail.com> Caleb DeLeeuw <143902425+SolshineCode@users.noreply.github.com> +calebrio02 <44554763+calebrio02@users.noreply.github.com> Calvin Laurenson <calvin@laurenson.dev> Cameron <csteele@steelecameron.com> Cameron Kaiser <classilla@users.noreply.github.com> +Captain-Tripps <jstaples2@hotmail.com> +CaramelizedCUDA <1418451053@qq.com> Carolinabanana <140120812+Carolinabanana@users.noreply.github.com> CarryFun <76023481+CarryFun@users.noreply.github.com> Carsten Kragelund Jørgensen <carsten@kragelund.me> @@ -318,6 +356,8 @@ Chad Brewbaker <crb002@gmail.com> Chad Voegele <chadvoegele@users.noreply.github.com> chaihahaha <chai836275709@gmail.com> Changyeon Kim <cyzero.kim@samsung.com> +Chanho Lee <chanholxx@gmail.com> +Chanho Lee <ibear6954@gmail.com> chansikpark <chansik.park@gmail.com> Chao Jiang <jc19chaoj@zoho.com> characharm <123120856+characharm@users.noreply.github.com> @@ -333,6 +373,7 @@ Chen Yuan <constantchen525@gmail.com> Cheng Shao <terrorjack@type.dance> Chenguang Li <757486878@qq.com> Chenguang Li <87689256+noemotiovon@users.noreply.github.com> +chiheb ben cheikh <100644963+ChihebBENCHEIKH1@users.noreply.github.com> Chipmunk <101038159+CHIPMUNK-T0T@users.noreply.github.com> chiranko <96988916+chiranko@users.noreply.github.com> Chris Danis <cdanis@gmail.com> @@ -350,6 +391,7 @@ Christian Hoener zu Siederdissen <software@siederdissen.eu> Christian Kastner <ckk@kvr.at> Christian Kögler <ck3d@gmx.de> Christian Köhnenkamp <cvk5@me.com> +Christian Loehnert <krampenschiesser@users.noreply.github.com> Christian Schmitz <support@monkeybreadsoftware.de> Christian Zhou-Zheng <59622928+christianazinn@users.noreply.github.com> Christopher Albert <albert@tugraz.at> @@ -360,6 +402,7 @@ City <125218114+city96@users.noreply.github.com> CJ Pais <cj@cjpais.com> Clark Saben <76020733+csaben@users.noreply.github.com> Clauszy <zhangyub@uniontech.com> +Clemens Wasser <clemens.wasser@gmail.com> clibdev <52199778+clibdev@users.noreply.github.com> Clint Herron <hanclinto@gmail.com> clyang <clyang@clyang.net> @@ -375,6 +418,7 @@ compilade <git@compilade.net> Congcong Cai <congcongcai0907@163.com> Conrad Kramer <conrad@conradkramer.com> Copilot <198982749+Copilot@users.noreply.github.com> +Cordell Blanchard <55163549+CordellBlanchard@users.noreply.github.com> Corentin REGAL <corentin.regal@gmail.com> cphlipot <9103367+cphlipot@users.noreply.github.com> cpumaxx <163466046+cpumaxx@users.noreply.github.com> @@ -389,6 +433,7 @@ Cristiano Pinto <140563307+crowmoed@users.noreply.github.com> crsawyer <7572190+crsawyer@users.noreply.github.com> Csaba Kecskemeti <csaba.kecskemeti@gmail.com> Cuong Trinh Manh <nguoithichkhampha@gmail.com> +cwriter <silvan.niederer@bluewin.ch> daboe01 <daboe01@googlemail.com> daghanerdonmez <44506702+daghanerdonmez@users.noreply.github.com> Damian Stewart <d@damianstewart.com> @@ -407,12 +452,15 @@ Daniel Han <danielhanchen@gmail.com> Daniel Hiltgen <dhiltgen@users.noreply.github.com> Daniel Illescas Romero <illescas.daniel@protonmail.com> Daniel Kleine <53251018+d-kleine@users.noreply.github.com> +Daniel Kuts <kutz@ispras.ru> Daniel Tang <danielzgtg.opensource@gmail.com> +Daniel Varga <vargad88@gmail.com> Daniele <57776841+daniandtheweb@users.noreply.github.com> Daniele <daniele.dilotorres@gmail.com> Daniele Pinna <72076821+pestopoppa@users.noreply.github.com> Danny Milosavljevic <dannym@friendly-machines.com> DannyDaemonic <DannyDaemonic@gmail.com> +Dante <144588016+KafKafrnZ@users.noreply.github.com> Darius Lukas <dariusjlukas@gmail.com> Dat Quoc Nguyen <2412555+datquocnguyen@users.noreply.github.com> Dave <dave-fl@users.noreply.github.com> @@ -422,10 +470,12 @@ Dave Della Costa <ddellacosta+github@gmail.com> Davi Henrique Linhares <38295327+WizardlyBump17@users.noreply.github.com> David Chiu <david20571015@gmail.com> David Friehs <david@friehs.info> +David Garcia <87497958+Dgarc359@users.noreply.github.com> David Huang <1969802+hjc4869@users.noreply.github.com> David Huggins-Daines <dhd@ecolingui.ca> David Kennedy <dakennedyd@gmail.com> David Lima <contato@davidlima.com.br> +David M. Rogers <predictivestatmech@gmail.com> David Pflug <david@pflug.email> david raistrick <keen99@users.noreply.github.com> David Renshaw <dwrenshaw@gmail.com> @@ -458,6 +508,7 @@ Devedse <2350015+devedse@users.noreply.github.com> Developer-Ecosystem-Engineering <65677710+Developer-Ecosystem-Engineering@users.noreply.github.com> Deven Mistry <31466137+deven367@users.noreply.github.com> devojony <61173062+devojony@users.noreply.github.com> +DevVexus <63028748+devvexus@users.noreply.github.com> diannao <55k@outlook.com> Dibakar Gope <dibakar.gope@arm.com> Didzis Gosko <didzis@users.noreply.github.com> @@ -493,11 +544,14 @@ Douglas Hanley <thesecretaryofwar@gmail.com> Dowon <ks2515@naver.com> Dr. Tom Murphy VII Ph.D <499244+tom7@users.noreply.github.com> drbh <david.richard.holtz@gmail.com> +drluoto <155452829+drluoto@users.noreply.github.com> drrros <52050875+drrros@users.noreply.github.com> ds5t5 <145942675+ds5t5@users.noreply.github.com> dskwe <dskwelmcy@163.com> +dsproule <dsproule@qti.qualcomm.com> duduta <simona.gherman@gmail.com> dylan <canardleteer@users.noreply.github.com> +e-mon <emon18@icloud.com> eastriver <lee@eastriver.dev> Ebey Abraham <ebey97@gmail.com> ebraminio <ebrahim@gnu.org> @@ -507,8 +561,10 @@ Ed Addario <29247825+EAddario@users.noreply.github.com> Ed Lee <edilee@mozilla.com> Ed Lepedus <ed.lepedus@googlemail.com> Eddie-Wang <wangjinheng1120@163.com> +Eden <aa9736195201@gmail.com> eduardopessin <100053075+eduardopessin@users.noreply.github.com> Edward Taylor <edeetee@gmail.com> +Ehsan Bateni <ebateni@qti.qualcomm.com> eiery <19350831+eiery@users.noreply.github.com> Elaine <elaine.zosa@gmail.com> Elbios <141279586+Elbios@users.noreply.github.com> @@ -516,6 +572,7 @@ Elton Kola <eltonkola@gmail.com> Emanuil Rusev <hello@erusev.com> Emil Askerov <56842174+EmilAskerov@users.noreply.github.com> Emmanuel Ferdman <emmanuelferdman@gmail.com> +Empressia <sphere.soffie@gmail.com> Emreerdog <34742675+Emreerdog@users.noreply.github.com> Engininja2 <139037756+Engininja2@users.noreply.github.com> Equim <sayaka@ekyu.moe> @@ -525,13 +582,16 @@ Eric Curtin <eric.curtin@docker.com> Eric Curtin <ericcurtin17@gmail.com> Eric Hartford <ehartford@gmail.com> Eric Hsieh <benson.doraemon@gmail.com> +Eric Rodrigues Pires <eric@eric.dev.br> Eric Sommerlade <es0m@users.noreply.github.com> Eric Zhang <34133756+EZForever@users.noreply.github.com> eric8607242 <e0928021388@gmail.com> Erik Garrison <erik.garrison@gmail.com> Erik Scholz <Green-Sky@users.noreply.github.com> +Erik Winter <93544977+ewintr@users.noreply.github.com> Ervin Áron Tasnádi <etasnadi@protonmail.com> Esko Toivonen <eskot98@gmail.com> +Ethan Guo <ethanguo.dev@gmail.com> Ethan Turner <eturner64@gmail.com> Ettore Di Giacinto <mudler@users.noreply.github.com> EugeoSynthesisThirtyTwo <gabriel.dhimoila@gmail.com> @@ -540,6 +600,7 @@ Evan Huus <eapache@gmail.com> Evan Jones <evan.q.jones@gmail.com> Evan Miller <emmiller@gmail.com> Eve <139727413+netrunnereve@users.noreply.github.com> +Evgen Mykhailenko <crosskillo@gmail.com> Evgeny Kurnevsky <kurnevsky@gmail.com> Ewan Crawford <ewan.cr@gmail.com> Ewan Crawford <ewan@codeplay.com> @@ -559,9 +620,12 @@ Fathi Boudra <fathi.boudra@linaro.org> Fattire <528174+fat-tire@users.noreply.github.com> felix <felix314159@users.noreply.github.com> Felix <stenbackfelix@gmail.com> +Felix Ye <felixyjs@gmail.com> fengerhu1 <2748250768@qq.com> +feni6 <fenissova@proton.me> fidoriel <49869342+fidoriel@users.noreply.github.com> fiesh <fiesh@zefix.tv> +FINAL-Bench <kkms1116@koreacu.ac.kr> Finn Voorhees <finnvoorhees@gmail.com> Firat <firatkiral@gmail.com> FirstTimeEZ <179362031+FirstTimeEZ@users.noreply.github.com> @@ -571,13 +635,16 @@ fl0rianr <226492742+fl0rianr@users.noreply.github.com> fl0rianr <f.reinle@otec.de> Florent BENOIT <fbenoit@redhat.com> Florian Badie <florianbadie@odrling.xyz> +Foad Abo Dahood <32059146+masterFoad@users.noreply.github.com> Folko-Ven <71110216+Folko-Ven@users.noreply.github.com> forforever73 <63285796+forforever73@users.noreply.github.com> Foul-Tarnished <107711110+Foul-Tarnished@users.noreply.github.com> Francisco Herrera <ppaanncchhoo507@gmail.com> Francisco Melo <43780565+francis2tm@users.noreply.github.com> Francois Dugast <francois.dugast@intel.com> +François-Xavier Gsell <fxgsell@gmail.com> franitel <franitel@gmx.com> +Frank Dai <soulmachine@gmail.com> Frank Mai <thxcode0824@gmail.com> FrankHB <frankhb1989@gmail.com> Frankie Robertson <frankier@users.noreply.github.com> @@ -587,9 +654,11 @@ Frederik Vogel <Schaltfehler@users.noreply.github.com> Fredrik Hultin <noname@nurd.se> fredzillman <fzillman@gmail.com> frob <rick+github@frob.com.au> +Frost-54 <91168148+Frost-54@users.noreply.github.com> Frosty40 <newjordan@gmail.com> Funtowicz Morgan <mfuntowicz@users.noreply.github.com> fxzjshm <11426482+fxzjshm@users.noreply.github.com> +fzowl <160063452+fzowl@users.noreply.github.com> g2mt <166577174+g2mt@users.noreply.github.com> Gabe Goodhart <gabe.l.hart@gmail.com> Gabe Goodhart <ghart@us.ibm.com> @@ -617,10 +686,12 @@ Gerben van V <gerbenvv@gmail.com> Gezahegne <gezahegne.yirefu@gmail.com> ghleg <aoleg@users.noreply.github.com> Gian-Carlo Pascutto <gcp@sjeng.org> +gianni-cor <gianfrancocordella@gmail.com> GiantPrince <90118823+GiantPrince@users.noreply.github.com> GideonSerf <gdserf.gs@gmail.com> Gilad S <giladgd@users.noreply.github.com> Gilad S. <7817232+giladgd@users.noreply.github.com> +Giovanni Rivera <rivera.giovanni271@gmail.com> github-actions[bot] <github-actions[bot]@users.noreply.github.com> GittyBurstein <g0534163997@gmail.com> Giuseppe Scrivano <giuseppe@scrivano.org> @@ -659,6 +730,7 @@ Han Qingzhe <95479277+hNSBQZ@users.noreply.github.com> Han Yin <han.yin@arm.com> HanishKVC <hanishkvc@gmail.com> hankcs <cnhankmc@gmail.com> +Hans <me@hans00.me> Hans Florian <hansolosan@gmail.com> Hao-Chen2337 <2113996104@qq.com> Haohui Mai <ricetons@gmail.com> @@ -673,6 +745,7 @@ HarrisonSec <gzxharrison@gmail.com> Hatsune Miku <129688334+at8u@users.noreply.github.com> HatsuneMikuUwU33 <173229399+HatsuneMikuUwU33@users.noreply.github.com> Haus1 <haus.xda@gmail.com> +hayder <tprod4242@gmail.com> hcl <chenglunhu@gmail.com> Héctor Estrada Moreno <hectorem2@gmail.com> helanfxz <126638465+helanfxz@users.noreply.github.com> @@ -689,6 +762,7 @@ Henry147147 <44851451+Henry147147@users.noreply.github.com> Herman Semenoff <GermanAizek@yandex.ru> Herman Semenov <GermanAizek@yandex.ru> Hesen Peng <hesen.peng@gmail.com> +hey-gm <heitorgm@outlook.com> HighDoping <highdoping@gmail.com> HimariO <dsfhe49854@gmail.com> hipudding <huafengchun@gmail.com> @@ -697,13 +771,16 @@ hksdpc255 <43977088+hksdpc255@users.noreply.github.com> hmirin <hmirin@users.noreply.github.com> hmscider <201289679+hmscider@users.noreply.github.com> Hoang Nguyen <hugo53@users.noreply.github.com> +Hoang Vien Duy <hoangduy.cqb.2k@gmail.com> hoangmit <hoangmit@users.noreply.github.com> hogeheer499-commits <hogeheer499@gmail.com> hokanosekai <69720899+hokanosekai@users.noreply.github.com> Holger Voormann <github@voormann.de> +homeofe <154892989+homeofe@users.noreply.github.com> HonestQiao <honestqiao@gmail.com> Hong Bo PENG <penghb@cn.ibm.com> hongbo.mo <352280764@qq.com> +HongHuang <honghuang2000@outlook.com> Hongqiang Wang <66336067+wanghqc@users.noreply.github.com> Hongqiang Wang <wangh@qti.qualcomm.com> Hongyu Ouyang <96765450+casavaca@users.noreply.github.com> @@ -712,6 +789,8 @@ hourhl <67227355+hourhl@users.noreply.github.com> Howard Su <howard0su@gmail.com> howlger <eclipse@voormann.de> howlger <github@voormann.de> +Hrishith Thadicherla <99313418+hthadicherla@users.noreply.github.com> +Hrushikesh Ramilla <ramillahrushikesh@gmail.com> hrushitfujitsu <Hrushit.Kakadia@fujitsu.com> Hua Jiang <allenhjiang@outlook.com> Huang Qi <huangqi3@xiaomi.com> @@ -725,11 +804,13 @@ hutli <hutli@hutli.hu> hutli <jensstaermose@hotmail.com> hxer7963 <hxer7963@gmail.com> hydai <z54981220@gmail.com> +I3eg1nner <45710049+I3eg1nner@users.noreply.github.com> iacopPBK <iacopogiottorossi@gmail.com> iacore <74560659+iacore@users.noreply.github.com> Ian Bull <irbull@eclipsesource.com> Ian Bull <irbull@gmail.com> Ian Faust <icfaust@gmail.com> +Ian McKellar <ian@mckellar.org> Ian Scrivener <github@zilogy.asia> ibrahim khadraoui <132432132+ibrahimkhadraoui@users.noreply.github.com> Icecream95 <the.real.icecream95@gmail.com> @@ -738,7 +819,9 @@ icppWorld <124377669+icppWorld@users.noreply.github.com> Ido S <ido.pluto@gmail.com> igardev <49397134+igardev@users.noreply.github.com> igarnier <igarnier@protonmail.com> +Iggy Jackson <notiggy@gmail.com> IgnacioFDM <ignaciofdm@gmail.com> +Igor Matuszewski <Xanewok@gmail.com> Igor Okulist <okigan@gmail.com> Igor Rudenko <iostream64@gmail.com> Igor Smirnov <smirnoviv@rambler.ru> @@ -752,6 +835,7 @@ Ilya Kurdyukov <59548320+ilyakurdyukov@users.noreply.github.com> Imad Saddik <79410781+ImadSaddik@users.noreply.github.com> iMil <imil@NetBSD.org> Incarnas <119618389+bit-incarnas@users.noreply.github.com> +InflexCZE <martin.pavlicek11@gmail.com> Intel AI Get-to Market Customer Success and Solutions <ai.gtm.css@gmail.com> intelmatt <61025942+intelmatt@users.noreply.github.com> iohub <rickyang.pro@gmail.com> @@ -804,6 +888,7 @@ Jared Tweed <jaredtwe@gmail.com> Jared Van Bortel <cebtenzzre@gmail.com> Jared Van Bortel <jared@nomic.ai> Jaromír Hradílek <jhradilek@gmail.com> +Jasmine-tim <403568753@qq.com> Jason C.H <ctrysbita@outlook.com> Jason McCartney <jmac@theroot.org> Jason Ni <jason.ni.py@gmail.com> @@ -813,6 +898,7 @@ Jassieluo <130133492+Jassieluo@users.noreply.github.com> Jay <BusyJay@users.noreply.github.com> Jay Zenith <162098309+JayZenith@users.noreply.github.com> Jayant Lohia <rajiblohia@gmail.com> +jbooth <jaybooth@gmail.com> JC <43374599+MrSMlT@users.noreply.github.com> jdomke <28772296+jdomke@users.noreply.github.com> Jean-Christophe Hoelt <hoelt@fovea.cc> @@ -826,12 +912,14 @@ Jeremy Demeule <jdemeule@users.noreply.github.com> Jeremy Rand <244188+JeremyRand@users.noreply.github.com> Jeroen Mostert <jeroen.mostert@cm.com> jeromew <jerome.wagner@m4x.org> +Jess Sullivan <Jess@sulliwood.org> Jesse <jesse@createthis.com> Jesse Gross <jesse@kernel.org> Jesse Ikonen <jesse.ikonen@gmail.com> Jesse Jojo Johnson <williamsaintgeorge@gmail.com> Jesse LaRose <jesse@taey.ai> Jesse Posner <jesse.posner@gmail.com> +Jesus Gulfo <jesdga95@gmail.com> Jesus Talavera <145992175+jesus-talavera-ibm@users.noreply.github.com> Jetson Tan <tanzongyouyi@outlook.com> Jett Janiak <jettjaniak@gmail.com> @@ -851,11 +939,13 @@ jiez <373447296@qq.com> Jillis ter Hove <j.terhove@gmail.com> Jim Wu <jimw567@users.noreply.github.com> Jingxin (Philip) Li <philipaslee@gmail.com> +jingzhou <jinzho@qti.qualcomm.com> Jinwoo Jeong <33892306+williamjeong2@users.noreply.github.com> Jinyang He <hejinyang@loongson.cn> jinzihao <jinzihao1996@gmail.com> Jiří Podivín <66251151+jpodivin@users.noreply.github.com> Jiří Sejkora <Sejseloid@gmail.com> +Jiwoong Song <55657581+jwsong98@users.noreply.github.com> JJJYmmm <92386084+JJJYmmm@users.noreply.github.com> jklincn <985765408@qq.com> jklincn <jklincn@outlook.com> @@ -868,6 +958,7 @@ Joe Eli McIlvain <joe.eli.mac@gmail.com> Joe Rowell <joerowell4@gmail.com> Joe Todd <joe.todd@codeplay.com> joecryptotoo <80373433+joecryptotoo@users.noreply.github.com> +Joel <agnel.joel@gmail.com> Johan <JohanAR@users.noreply.github.com> Johannes Gäßler <johannesg@5d6.de> Johannes Rudolph <johannes.rudolph@gmail.com> @@ -890,6 +981,7 @@ Jonathan Clohessy <jonathan.clohessy@arm.com> Jonathan Graehl <99024+graehl@users.noreply.github.com> Jorge A <161275481+jorgealias@users.noreply.github.com> Jose Maldonado <63384398+yukiteruamano@users.noreply.github.com> +Joseph Patricio <122133686+JoeyPatricio@users.noreply.github.com> Joseph Stahl <1269177+josephst@users.noreply.github.com> Josh Leverette <josh@ceres1.space> Josh Ramer <josh.ramer@icloud.com> @@ -952,11 +1044,14 @@ Karsten Weiss <knweiss@gmail.com> Karthick <j.karthic2004@gmail.com> Karthik Kumar Viswanathan <195178+guilt@users.noreply.github.com> Karthik Sethuraman <k.seth1993@gmail.com> +Karthik Vijayan <mailkv23@gmail.com> Kartik Gulia <kgulia@nvidia.com> Kartik Sirohi <99896785+sirohikartik@users.noreply.github.com> Kashif Rasul <kashif.rasul@gmail.com> +Kasimir Tanner <31862638+Yezat@users.noreply.github.com> KASR <karim.asrih@gmail.com> Kasumi <90275229+kasumi-1@users.noreply.github.com> +Katara <sohaib.harraoui@ostorlab.dev> Katostrofik <georgiopapairo@gmail.com> katsu560 <118887472+katsu560@users.noreply.github.com> Kawrakow <48489457+ikawrakow@users.noreply.github.com> @@ -986,6 +1081,7 @@ kimminsu <80271594+kimminsu38oo@users.noreply.github.com> KITAITI Makoto <KitaitiMakoto@gmail.com> kiwi <122582483+kiwi142857@users.noreply.github.com> klosax <131523366+klosax@users.noreply.github.com> +KnightYao <KnightYao@users.noreply.github.com> KokerZhou <111279477+KokerZhou@users.noreply.github.com> Kolen Cheung <ickc@users.noreply.github.com> kononnable <kononnable@gmail.com> @@ -993,6 +1089,7 @@ Konrad Moren <kmoren@nvidia.com> konradmb <konradmb@o2.pl> Konstantin Herud <konstantin.herud@denkbares.com> Konstantin Zhuravlyov <konstantin.zhuravlyov@amd.com> +Kris <github@selfref.dev> Krishna Sridhar <99914379+srikris-sridhar@users.noreply.github.com> krystiancha <krystian@krystianch.com> krzsztf <krzysztof@witkowscy.org> @@ -1004,6 +1101,7 @@ Kunshang Ji <kunshang.ji@intel.com> kuronekosaiko <EvanChanJ@163.com> kurquhar <kurquhar@qti.qualcomm.com> Kusha Gharahi <3326002+kushagharahi@users.noreply.github.com> +Kushal Garg <98699239+kushalgarg101@users.noreply.github.com> kustaaya <58045274+kustaaya@users.noreply.github.com> kuvaus <22169537+kuvaus@users.noreply.github.com> kvc0 <3454741+kvc0@users.noreply.github.com> @@ -1033,6 +1131,7 @@ ldwang <ftgreat@163.com> le.chang <cljs118@126.com> Lee <44310445+lx200916@users.noreply.github.com> Lee Drake <b.lee.drake@gmail.com> +Leebr Data Consulting <harrak.amine1987@gmail.com> leejet <leejet714@gmail.com> Leng Yue <lengyue@lengyue.me> Lennart Austenfeld <53152202+l-austenfeld@users.noreply.github.com> @@ -1049,8 +1148,12 @@ lhez <lih@qti.qualcomm.com> lhez <quic_lih@quicinc.com> Li Pengzhan <151381994+Lpzhan931@users.noreply.github.com> Li Tan <tanliboy@gmail.com> +liangliangchang <lichang@amd.com> liminfei-amd <91481003+liminfei-amd@users.noreply.github.com> limitedAtonement <limitedAtonement@users.noreply.github.com> +lingyezhixing <144504450+lingyezhixing@users.noreply.github.com> +linsen458-spec <linsen458@gmail.com> +Linux User <linuxusergd@outlook.com> Linwei Wang <wanix1988@gmail.com> Liu Jia <109258120+Septa2112@users.noreply.github.com> Liu Jia <jia3.liu@intel.com> @@ -1058,10 +1161,12 @@ liuwei-git <14815172+liuwei-git@users.noreply.github.com> lixing-star <104126818+lixing-star@users.noreply.github.com> lksj92hs <134250687+lksj92hs@users.noreply.github.com> lnigam <lnigam@nvidia.com> +Logan Chu <logan.chu@duke.edu> LoganDark <github@logandark.mozmail.com> Loïc Carrère <loic.carrere@gmail.com> lon <114724657+longregen@users.noreply.github.com> loonerin <132926317+loonerin@users.noreply.github.com> +losewayy <1134285612@qq.com> LostRuins <39025047+LostRuins@users.noreply.github.com> LostRuins Concedo <39025047+LostRuins@users.noreply.github.com> lovedheart <6277001+lovedheart@users.noreply.github.com> @@ -1074,6 +1179,7 @@ Ludovic Henry <git@ludovic.dev> Ludovic Henry <ludovic@rivosinc.com> Lukas Straub <lukasstraub2@web.de> Łukasz Ślusarczyk <112692748+lslusarczyk@users.noreply.github.com> +Łukasz Ślusarczyk <lukasz.slusarczyk@intel.com> Lukasz Stolcman <4583553+lstolcman@users.noreply.github.com> LunalFresh <165352784+LunalFresh@users.noreply.github.com> Luo Tian <lt@basecity.com> @@ -1105,12 +1211,15 @@ manayang <jackmanayang@gmail.com> manikbhandari <mbbhandarimanik2@gmail.com> Manuel <44313466+makuche@users.noreply.github.com> maor-ps <154728172+maor-ps@users.noreply.github.com> +Maphist0 <28743569+Maphist0@users.noreply.github.com> Marc Köhlbrugge <subscriptions@marckohlbrugge.com> Marcel Petrick <mail@marcelpetrick.it> Marcello Seri <mseri@users.noreply.github.com> +Marco Colombo <ing.marco.colombo@gmail.com> Marco Matthies <71844+marcom@users.noreply.github.com> Marcos Del Sol Vives <marcos@orca.pet> marcoStocchi <marcostocchi77@gmail.com> +Marcus <marcusds@users.noreply.github.com> Marcus Dunn <51931484+MarcusDunn@users.noreply.github.com> Marek Hradil jr. <marek.hradil@outlook.com> Marian Cepok <marian.cepok@gmail.com> @@ -1120,16 +1229,21 @@ Mario Limonciello <superm1@kernel.org> Marius Gerdes <141485318+mglambda@users.noreply.github.com> Mariusz Woloszyn <emsi@users.noreply.github.com> Mark Fairbairn <thebaron88@gmail.com> +Mark Todorovich <mtodorov@qti.qualcomm.com> Mark Zhuang <zhuangqiubin@gmail.com> Marko Tasic <mtasic85@gmail.com> Markus Ebner <seijikun@users.noreply.github.com> Markus Tavenrath <mtavenrath@users.noreply.github.com> +Marlon Paz <86619221+mairp@users.noreply.github.com> Martin Andersson <zoi@inversi0n.org> Martin Chang <marty1885@users.noreply.github.com> Martin Delille <martin@delille.org> +Martin Emrich <6672718+MartinEmrich@users.noreply.github.com> Martin Klacer <martin.klacer@arm.com> +Martin Kleinberger <martin.kleinberger@gmail.com> Martin Krasser <krasserm@googlemail.com> Martin Schwaighofer <mschwaig@users.noreply.github.com> +martin-cimmino <159526529+martin-cimmino@users.noreply.github.com> Marvin Gießing <marvin.giessing@gmail.com> Marxist-Leninist <31905382+Marxist-Leninist@users.noreply.github.com> Masashi Yoshimura <yoshimura.masashi.frbs@gmail.com> @@ -1153,6 +1267,7 @@ Matt Clayton <156335168+mattjcly@users.noreply.github.com> Matt Corallo <649246+TheBlueMatt@users.noreply.github.com> Matt Jallo <matt@mattjallo.com> Matt Pulver <matt.pulver@heavy.ai> +Matt Rutkowski <mrutkows@us.ibm.com> Matt Stephenson <mstephenson6@users.noreply.github.com> Matt Thompson <111157855+boondocklabs@users.noreply.github.com> matt23654 <193348153+matt23654@users.noreply.github.com> @@ -1177,6 +1292,7 @@ Maxime <672982+maximegmd@users.noreply.github.com> Maximilian Werk <maximilian.werk@gmx.de> Maximilian Winter <maximilian.winter.91@gmail.com> mdrokz <mohammadmunshi@gmail.com> +Me42019 <jeremyh88.jh@gmail.com> meatposes <computerdork@verizon.net> MeeMin <74113151+Meet91721@users.noreply.github.com> megemini <megemini@outlook.com> @@ -1188,6 +1304,7 @@ Mengsheng Wu <mengshen@qti.qualcomm.com> Mengsheng Wu <mengshengwu@outlook.com> Merrick Christensen <merrick.christensen@gmail.com> mgroeber9110 <45620825+mgroeber9110@users.noreply.github.com> +MiaoMing Chen <miaomingc@stumail.nwu.edu.cn> Miaoqian Lin <linmq006@gmail.com> Michael Coppola <m18coppola@gmail.com> Michael de Gans <michael.john.degans@gmail.com> @@ -1203,6 +1320,7 @@ Michael Klimenko <mklimenko29@gmail.com> Michael Lamothe <michael.lamothe@gmail.com> Michael Podvitskiy <podvitskiymichael@gmail.com> Michael Potter <NanoTekGuy@Gmail.com> +Michael Taylor <162068037+mctylr-gh@users.noreply.github.com> Michael Wand <michael@baybridgeaquarium.com> michaeltrabalka-tech <michael.trabalka@gmail.com> Michał Moskal <michal@moskal.me> @@ -1210,11 +1328,13 @@ Michał Piszczek <michal@piszczek.pl> Michał Tuszyński <srgtuszy@gmail.com> Michelle Tan <41475767+MichelleTanPY@users.noreply.github.com> Mickael Desgranges <md-github@mkdgs.fr> +midagedev <139564968+midagedev@users.noreply.github.com> midnight <midnightmagic@users.noreply.github.com> Mihai <mihai.chirculescu@yahoo.com> Mike <ytianhui2004@gmail.com> Mike Abbott <furrysalamander@gmail.com> Mike Abbott <michael.abbott@lvt.com> +Mike van Lammeren <mike@van.lammeren.net> Mikhail Podvitskii <podvitskiymichael@gmail.com> Mikko Juola <mikjuo@gmail.com> Mikolaj Kucharski <mikolaj@kucharski.name> @@ -1232,6 +1352,7 @@ mj-shifu <77107165+mj-shifu@users.noreply.github.com> mkoker <132301062+mkoker@users.noreply.github.com> mmyjona <jonathan.gonse@gmail.com> mnehete32 <33429707+mnehete32@users.noreply.github.com> +Mohamed Elashri <git@elashri.com> Mohammad Athar <157023731+m-atharkhan@users.noreply.github.com> Mohammadreza Hendiani <hendiani.mohammadreza@gmail.com> Mohammadreza Hendiani <mohammad.r.hendiani@gmail.com> @@ -1242,16 +1363,20 @@ MoonRide303 <130458190+MoonRide303@users.noreply.github.com> MoonShadow <moonshadow25@163.com> MorganRO8 <47795945+MorganRO8@users.noreply.github.com> moritzbrantner <31051084+moritzbrantner@users.noreply.github.com> +Mostafa <mostafaaafaheem@gmail.com> mtmcp <141645996+mtmcp@users.noreply.github.com> muggle-stack <promuggle@qq.com> +Muhammad Saad <saadydev@gmail.com> Muhammad Salem <salem.ebo@gmail.com> Murilo Santana <mvrilo@gmail.com> Musab Gultekin <musabgultekin@users.noreply.github.com> musoles <135031143+musoles@users.noreply.github.com> mzcu <milos.cubrilo@gmail.com> +nachobh <ibenitoherrero@gmail.com> Naco Siren <naco-siren@users.noreply.github.com> Nam D. Tran <42194884+namtranase@users.noreply.github.com> nanahi <130121847+na-na-hi@users.noreply.github.com> +Nandan Vallamdasu <nandan.vallamdasu@outlook.com> Nathan Epstein <nate2@umbc.edu> Nathan Wilson <67372905+Nathanw1014@users.noreply.github.com> Nathanw1014 <67372905+Nathanw1014@users.noreply.github.com> @@ -1287,15 +1412,20 @@ Nico <ramicaza@gmail.com> Nico Bosshard <nico@bosshome.ch> Nicolai Weitkemper <kontakt@nicolaiweitkemper.de> Nicolas B. Pierron <nicolas.b.pierron@gmail.com> +Nicolas Budyn <16596345+nbud@users.noreply.github.com> Nicolas Mowen <nickmowen213@gmail.com> Nicolás Pérez <nicolas_perez@brown.edu> Nicolò Scipione <nicolo.scipione@codeplay.com> Nigel Bosch <pnigelb@gmail.com> +Nigel Jones <nigel.l.jones+git@gmail.com> +Nik Bogatyrev <50734723+notforu777@users.noreply.github.com> Nikhil Jain <nikhil.jain0987@gmail.com> +Nikita Gordeev <iamfobey@gmail.com> Nikita Sarychev <42014488+sARY77@users.noreply.github.com> Niklas Korz <niklas@niklaskorz.de> Niklas Sheth <niklassheth@gmail.com> Niklas Wenzel <dev@nikwen.de> +Niko Maroulis <nik.maroulis@gmail.com> NikolaiLyssogor <59844691+NikolaiLyssogor@users.noreply.github.com> Nikolaos Pothitos <pothitos@di.uoa.gr> Nikolas <127742645+nneubacher@users.noreply.github.com> @@ -1347,10 +1477,12 @@ pascal-lc <49066376+pascal-lc@users.noreply.github.com> Pasha Khosravi <khosravipasha@users.noreply.github.com> Patrice Ferlet <metal3d@gmail.com> Patrick Buckley <eous@users.noreply.github.com> +Patrick Hoffmann <patrick@hoffmann.lol> Patrick Peng <retr0@retr0.blog> Patryk Kaminski <kaminpatryk@gmail.com> Paul Dubs <paul.dubs@gmail.com> Paul Flynn <paul@arkavo.com> +Paul Mairhofer <paul@protom.eu> Paul Tsochantaris <ptsochantaris@icloud.com> Pavan Shinde <pavann97@gmail.com> Pavel Zloi <github.com@drteam.rocks> @@ -1364,12 +1496,14 @@ peidaqi <peidaqi@gmail.com> Penglin Cai <1402538448@qq.com> pengxin99 <pengxin.yuan@intel.com> Pepijn de Vos <me@pepijndevos.nl> +Pepper Gray <hello@peppergray.xyz> Percy Piper <piper.percy@googlemail.com> Perry Naseck <4472083+DaAwesomeP@users.noreply.github.com> perserk <perserk@gmail.com> Peter <peter277@users.noreply.github.com> Peter Sideris <petersid2022@gmail.com> Peter Sugihara <peter@campsh.com> +Peter van Velzen <info@pcvanvelzen.nl> Peter0x44 <peter0x44@disroot.org> petterreinholdtsen <pere-github@hungry.com> Phil H <5756783+phiharri@users.noreply.github.com> @@ -1389,6 +1523,7 @@ Piotr Kubaj <pkubaj@anongoth.pl> Piotr Wilkin (ilintar) <piotr.wilkin@syndatis.com> pl752 <pl752@mail.ru> Plamen Minev <pacominev@gmail.com> +Ploo <239304139+xinitrcn1@users.noreply.github.com> pmaybank <113125070+pmaybank@users.noreply.github.com> pmysl <piotr.myslinski@outlook.com> PMZFX <georgiopapairo@gmail.com> @@ -1396,22 +1531,31 @@ pockers21 <134406831+pockers21@users.noreply.github.com> Pop Flamingo <trevor.annedenise@icloud.com> postmasters <namnguyen@google.com> Pouya <PooyaGhahramanian@Gmail.com> +ppAlexa <pallavipriyastm@gmail.com> pqnet <119850+pqnet@users.noreply.github.com> +pr3pony <pr3pony@pm.me> +Prabhsimran Singh <prabhsimrans@nvidia.com> Prabhsimran Singh <pskrunner14@gmail.com> Prabod <prabod@maincode.com> +Pradeep Rao <pradeep.rao@amd.com> Prajwal B Mehendarkar <prajwal.b.mehendarkar@ibm.com> Pranav Dhinakar <pdhinaka@qti.qualcomm.com> Pranav Dhinakar <pranavdhinakar@gmail.com> Pranav Uttarkar <122235768+PranavUttarkar@users.noreply.github.com> Pranesh Gonegandla <pranesh.iitp@gmail.com> Prashant Vithule <119530321+Vithulep@users.noreply.github.com> +pratiknarola-t <pratik.narola@tether.io> +Pratyush Kumar <praty.bachchas@gmail.com> ProgenyAlpha <loveandhappypaws@gmail.com> Przemysław Pawełczyk <przemoc@gmail.com> +PSEUDOTENSOR / Jonathan McKinney <pseudotensor@gmail.com> psocolovsky <50770545+psocolovsky@users.noreply.github.com> pudepiedj <pudepiedj@gmail.com> PureJourney <edward.pong@qq.com> +pzhu <q1091803103@gmail.com> QDelta <60222316+QDelta@users.noreply.github.com> Qeeweew <68716978+Qeeweew@users.noreply.github.com> +qiao_px <84374584+Qiao12-pixel@users.noreply.github.com> Qin Yue Chen <71813199+chenqiny@users.noreply.github.com> qingfengfenga <41416092+qingfengfenga@users.noreply.github.com> qingy1337 <qxli2@students.everettcc.edu> @@ -1435,6 +1579,7 @@ Radoslav Gerganov <rgerganov@gmail.com> Radosław Gryta <radek.gryta@gmail.com> Rafail Giavrimis <47496212+grafail@users.noreply.github.com> Rafal Lewczuk <rafal.lewczuk@gmail.com> +Raffaele Di Donna <raffididonna@gmail.com> ragz4125 <65285549+ragz4125@users.noreply.github.com> Rahul Sathe <150351592+rrsathe@users.noreply.github.com> Rahul Vivek Nair <68507071+RahulVivekNair@users.noreply.github.com> @@ -1470,6 +1615,7 @@ ren <189031187+lathrys-at@users.noreply.github.com> Ren Xuancheng <jklj077@users.noreply.github.com> Renat <rntk@users.noreply.github.com> Rene Leonhardt <65483435+reneleonhardt@users.noreply.github.com> +Renzis <93137239+Renzishi@users.noreply.github.com> Reza Kakhki <rezakakhki.de@gmail.com> Reza Rahemtola <49811529+RezaRahemtola@users.noreply.github.com> RhinoDevel <RhinoDevel@users.noreply.github.com> @@ -1560,11 +1706,14 @@ Sachin Desai <smdesai@gmail.com> Sachin Sharma <sachin@zettabolt.com> Safi Ullah <safiullah.3915@gmail.com> safranowith <bsh155762@gmail.com> +Said Taghadouini <84044788+staghado@users.noreply.github.com> +Sait Furkan Teke <35101659+stfurkan@users.noreply.github.com> SakuraUmi <yukinon244@gmail.com> Salvador E. Tropea <stropea@inti.gob.ar> Salvatore Mesoraca <s.mesoraca16@gmail.com> Sam <sammcj@users.noreply.github.com> Sam Malayek <12037535+SamMalayek@users.noreply.github.com> +Sam Murdoch <hello@burl.au> Sam Spilsbury <smspillaz@gmail.com> Sam/Samuel <57896620+cern1710@users.noreply.github.com> Samanvya Tripathi <samanu09@gmail.com> @@ -1572,17 +1721,22 @@ SamareshSingh <97642706+ssam18@users.noreply.github.com> SAMI <samuel.koesnadi@stud.uni-due.de> Sami Farin <3876865+Safari77@users.noreply.github.com> Sami Kama <samikama@users.noreply.github.com> +Samriddha Sinha <74808231+sam-india-007@users.noreply.github.com> Samuel Maynard <samwmaynard@gmail.com> samuraieng <89817709+samuraieng@users.noreply.github.com> Sandro Hanea <40202887+sandrohanea@users.noreply.github.com> +Sandro Steeger <78495486+Stastez@users.noreply.github.com> sandyiscool <sandyiscool@gmail.com> Sang-Kil Park <sang.park@42dot.ai> Sanjay Ahari <sanjayahari1704@gmail.com> +Sarah Wu <sarahwu185@gmail.com> +Sarah Wu <sarwu@nvidia.com> Sascha Rogmann <59577610+srogmann@users.noreply.github.com> sasha0552 <admin@sasha0552.org> Satinder Grewal <grewal.satinder@gmail.com> Satinder Grewal <grewal@lavabit.com> SATISH K C <157192662+satishkc7@users.noreply.github.com> +Satyam Thakur <personal.thakursatyam@gmail.com> Saurabh Dash <111897126+saurabhdash2512@users.noreply.github.com> SavicStefan <50296686+SavicStefan@users.noreply.github.com> Scott Fudally <sfudally@nvidia.com> @@ -1593,6 +1747,7 @@ Sebastián A <sebastian.aedo29@gmail.com> Sebastian Dröge <sebastian@centricular.com> Sebastian Dröge <slomo@coaxion.net> SebastianApel <13675545+SebastianApel@users.noreply.github.com> +SecondSeed <38520721+SecondSeed@users.noreply.github.com> semidark <me@semidark.net> Senemu <10880819+Senemu@users.noreply.github.com> senhtry <w169q169@gmail.com> @@ -1611,6 +1766,8 @@ seryogakovalyov <seryogakovalyov@gmail.com> Seungmin Kim <8457324+ehfd@users.noreply.github.com> SeungWon Jeong <65549245+redlion0929@users.noreply.github.com> Seyoung Jeong <seyoungjeong@gmail.com> +SG-Amadeus <74057036+SG-Amadeus@users.noreply.github.com> +Sh1m13 <93532735+SomeNobody21112@users.noreply.github.com> ShadovvBeast <ShadovvBeast@gmail.com> Shagun Bera <141054835+notV3NOM@users.noreply.github.com> Shahir BIn Zulfiker <119410932+aorko01@users.noreply.github.com> @@ -1618,6 +1775,7 @@ Shakhar Dasgupta <shakhardasgupta@gmail.com> Shakhnazar Sailaukan <101112128+Sailaukan@users.noreply.github.com> Shakil Ahmed <44522075+ahmedshakill@users.noreply.github.com> shalinib-ibm <Shalini.Salomi.Bodapati@ibm.com> +shamnadxyz <155352697+shamnadxyz@users.noreply.github.com> Shane A <shanea@allenai.org> Shane Tran Whitmire <64436119+dogunbound@users.noreply.github.com> Shangning Xu <32517059+xushangning@users.noreply.github.com> @@ -1642,6 +1800,7 @@ Shobhit <sobhit.me@gmail.com> Shouyu <65317431+joeldushouyu@users.noreply.github.com> Shouzheng Liu <61452103+lshzh-ww@users.noreply.github.com> Shouzheng Liu <lshzh.hi@gmail.com> +Shreya <shreya.agrawal@iitg.ac.in> Shreya Jain <shreya94jain@gmail.com> Shreya Jain <shreyajn@qti.qualcomm.com> Shrivas Shankar <86219405+shrivasshankar@users.noreply.github.com> @@ -1650,18 +1809,25 @@ Shuichi Tsutsumi <shuichi0526@gmail.com> shun095 <8069181+shun095@users.noreply.github.com> Shunta Saito <shunta.saito@gmail.com> Shupei Fan <dymarkfan@outlook.com> +Si Chen <62344747+cs-fisha@users.noreply.github.com> Si1w <139008732+Si1w@users.noreply.github.com> +Siavash Norouzi <35790025+siavashnorouzi@users.noreply.github.com> Sid Mohan <61345237+sidmohan0@users.noreply.github.com> Sid Shaytay <2595088+SidShaytay@users.noreply.github.com> +SIDDARTHA REDDY <75976672+SIDDARTHAREDDY8@users.noreply.github.com> Sigbjørn Skjæret <1629204+CISC@users.noreply.github.com> Sigbjørn Skjæret <ggerganov@gmail.com> Sigbjørn Skjæret <sigbjorn.skjaeret@huggingface.co> Sigbjørn Skjæret <sigbjorn.skjaeret@scala.com> +Sihan Yu <116848194+sihanyu03@users.noreply.github.com> +Silverside <truesilverside@gmail.com> simevo <github@simevo.com> Simon Redman <simon@ergotech.com> +Simon Sudarushkin <68971770+simonether@users.noreply.github.com> Simon Teixidor <simon@flaskpost.me> Simon Willison <swillison@gmail.com> simon886212 <37953122+simon886212@users.noreply.github.com> +Simone Iacomino <92865212+simoneiacomino@users.noreply.github.com> Simranjeet Singh <105192966+simrnsingh@users.noreply.github.com> singularity <12184989+singularity-s0@users.noreply.github.com> Sirui He <143699303+SiruiHe@users.noreply.github.com> @@ -1675,6 +1841,7 @@ slaren <2141330+slaren@users.noreply.github.com> Slaren <2141330+slaren@users.noreply.github.com> slaren <slarengh@gmail.com> Slava Primenko <primenko.s@gmail.com> +sliu39 <russell.liu@intel.com> Slobodan Josic <127323561+slojosic-amd@users.noreply.github.com> Small Grass Forest <zixuanxcl@gmail.com> SmartestWashingMachine <ottobizness@gmail.com> @@ -1693,6 +1860,7 @@ Sou-ly <79574807+Sou-ly@users.noreply.github.com> Sourab Mangrulkar <13534540+pacman100@users.noreply.github.com> Spencer Sutton <spencersutton@users.noreply.github.com> sprayandwipe <spray.and.wipe@gmail.com> +Sreeram <sreeram.sivasubramony@amd.com> SRHMorris <69468379+SRHMorris@users.noreply.github.com> Srihari-mcw <96763064+Srihari-mcw@users.noreply.github.com> Srinivas Billa <nivibilla@gmail.com> @@ -1714,6 +1882,7 @@ Steven Prichard <spprichard20@gmail.com> Steven Roussey <sroussey@gmail.com> stevenkuang <stevenkuang@tencent.com> Steward Garcia <57494570+FSSRepo@users.noreply.github.com> +stormy <82701871+stormyhs@users.noreply.github.com> StrangeBytesDev <141275258+StrangeBytesDev@users.noreply.github.com> strawberrymelonpanda <152940198+strawberrymelonpanda@users.noreply.github.com> Strongtut <Strongtut@users.noreply.github.com> @@ -1725,12 +1894,15 @@ Sundaram krishnan <104441812+sundaram123krishnan@users.noreply.github.com> SuperUserNameMan <yoann@terminajones.com> Sutou Kouhei <kou@cozmixng.org> Svetlozar Georgiev <55534064+sgeor255@users.noreply.github.com> +Swigler <124839156+Swigler@users.noreply.github.com> swittk <switt1995@gmail.com> +SXX <song_xiaoxi@126.com> SXX <sxx1136965276@gmail.com> Tai Duc Nguyen <taiducnguyen.drexel@gmail.com> Taikono-Himazin <kazu@po.harenet.ne.jp> Taimur Ahmad <taimur.ahmad@10xengineers.ai> Tak-RS <snosk.t@gmail.com> +Takamichi Ohara <tokinasin@tutanota.com> takasurazeem <takasurazeem@gmail.com> takov751 <40316768+takov751@users.noreply.github.com> takuya kodama <a.s.takuya1026@gmail.com> @@ -1741,6 +1913,7 @@ Tamar <Tamar0812@outlook.co.il> tamarPal <tamarp3385@gmail.com> Tameem <113388789+AhmadTameem@users.noreply.github.com> Tamotsu Takahashi <ttakah+github@gmail.com> +TANGBUDU <79953480+TANGBUDU@users.noreply.github.com> Tanner Bruhn <66120666+tannerbruhn@users.noreply.github.com> tarcey <cey.tarik@gmail.com> Tarek Dakhran <t.dakhran@gmail.com> @@ -1755,14 +1928,18 @@ Tekin Ertekin <tekin.ertekin@gmail.com> Tekin Ertekin <tekinertekin@gmail.com> tempstudio <49735574+tempstudio@users.noreply.github.com> teo <TeoZosa@users.noreply.github.com> +Terrence Zhao <32208165+Terrencezzj@users.noreply.github.com> texasich <101962694+texasich@users.noreply.github.com> texmex76 <40733439+texmex76@users.noreply.github.com> tha80 <7176001+tha80@users.noreply.github.com> Thái Hoàng Tâm <75922889+RoyalHeart@users.noreply.github.com> Thammachart Chinvarapon <1731496+Thammachart@users.noreply.github.com> Thatcher Chamberlin <j.thatcher.c@gmail.com> +TheArchitectit <roger@vroger.com> thecaptain789 <257642323+thecaptain789@users.noreply.github.com> +Theera K. <tkittich@hotmail.com> Theia Vogel <theia@vgel.me> +thelittlefireman <5165783+thelittlefireman@users.noreply.github.com> thement <40525767+thement@users.noreply.github.com> theo77186 <theo77186@users.noreply.github.com> theraininsky <76763719+theraininsky@users.noreply.github.com> @@ -1785,6 +1962,7 @@ Tillerino <Tillerino@users.noreply.github.com> Tim Miller <drasticactions@users.noreply.github.com> Tim Neumann <mail@timnn.me> Tim Neumann <timnn@google.com> +Tim Wang <149349643+timothywang21@users.noreply.github.com> Tim Wang <overocean@gmail.com> timkhronos <timkhronos@gmail.com> Timmy Knight <r2d2fish@gmail.com> @@ -1795,10 +1973,13 @@ Ting Sun <suntcrick@gmail.com> Titaniumtown <titaniumtown@proton.me> Tiwei Bie <tiwei.btw@antgroup.com> tjohnman <tjohnman@users.noreply.github.com> +tkran2 <157059462+tkran2@users.noreply.github.com> Tobias Lütke <tobi@shopify.com> Toby <25832191+aetherbird@users.noreply.github.com> Todd Malsbary <todd.malsbary@intel.com> +Todor Boinovski <tboinovski@gmail.com> Todor Boinovski <todorb@qti.qualcomm.com> +Toki Nasin <141258697+tokinasin@users.noreply.github.com> Tom C <tom.corelis@gmail.com> Tom Hillbrunner <thillbrunner@gmail.com> Tom Jobbins <784313+TheBloke@users.noreply.github.com> @@ -1815,8 +1996,10 @@ TriDefender <nitric.trioxide@gmail.com> triplenom <79777178+triplenom@users.noreply.github.com> Tristan Druyen <tristan@vault81.mozmail.com> Tristan Ross <rosscomputerguy@protonmail.com> +Trivalik <3148279+trivalik@users.noreply.github.com> Trivikram Kamat <16024985+trivikr@users.noreply.github.com> Trivikram Reddy <127072883+trivikram-reddy1@users.noreply.github.com> +Trunk Trick <2451421621@qq.com> Ts-sound <44093942+Ts-sound@users.noreply.github.com> tslmy <tslmy@users.noreply.github.com> tt <291400568@qq.com> @@ -1835,12 +2018,14 @@ uint256_t <maekawatoshiki1017@gmail.com> Ujjawal Panchal <31011628+Ujjawal-K-Panchal@users.noreply.github.com> Ulrich Drepper <drepper@gmail.com> unbounded <haakon@likedan.net> +Unbug Lee <tidelgl@gmail.com> unraido <127105806+unraido@users.noreply.github.com> uvos <carl@uvos.xyz> uvos <devnull@uvos.xyz> uvos <philipp@uvos.xyz> Uzo Nweke <uzoechi@gmail.com> Vaibhav Srivastav <vaibhavs10@gmail.com> +vaibhavdedhia <vaibhavdedhia@gmail.com> Val Kharitonov <mail@kharvd.com> ValdikSS <iam@valdikss.org.ru> Valentin Konovalov <valle.ketsujin@gmail.com> @@ -1867,6 +2052,7 @@ Vinkal <vinkal-chudgar@users.noreply.github.com> virajwad <84867530+virajwad@users.noreply.github.com> viric <viric@viric.name> Vishal Agarwal <vishalagarwal.jss@gmail.com> +Vishal Singh <63198658+vishalMCE@users.noreply.github.com> Vishal Singh <vishal@zettabolt.com> Vitali Lovich <vlovich+github@gmail.com> Vivian <vynride@gmail.com> @@ -1885,7 +2071,9 @@ Volodymyr Vitvitskyi <72226+signalpillar@users.noreply.github.com> vvhg1 <94630311+vvhg1@users.noreply.github.com> vxiiduu <73044267+vxiiduu@users.noreply.github.com> Wagner Bruna <wbruna@users.noreply.github.com> +WakeUpMorty <balogkarlo4@gmail.com> Wallentri <wallentridan88@proton.me> +WalterCool <waltercool@slash.cl> Wang Qin <37098874+wangqin0@users.noreply.github.com> Wang Ran (汪然) <wangr@smail.nju.edu.cn> Wang Weixuan <wangweixvan@gmail.com> @@ -1902,14 +2090,18 @@ Welby Seely <welbyseely@gmail.com> welix <taichitary@gmail.com> wencan <wencan@live.cn> wendadawen <130649302+wendadawen@users.noreply.github.com> +WenqiangJia2026 <wenqijia@amd.com> Wentai Zhang <rchardx@gmail.com> +wes <huangwei858@126.com> whoreson <139810751+whoreson@users.noreply.github.com> Wilken Gottwalt <12194808+wgottwalt@users.noreply.github.com> +Will <willie37555@gmail.com> will-lms <will@lmstudio.ai> WillCorticesAI <150854901+WillCorticesAI@users.noreply.github.com> william pan <61359596+wp4032@users.noreply.github.com> William Tambellini <william.tambellini@gmail.com> William Tambellini <wtambellini@sdl.com> +William Tan <1284324+Ninja3047@users.noreply.github.com> willjoha <github.com@brute-force.org> Willy Tarreau <w@1wt.eu> Winston Ma <winstonma@ymail.com> @@ -1932,12 +2124,14 @@ xctan <axunlei@gmail.com> xctan <xc-tan@outlook.com> Xiake Sun <xiake.sun@intel.com> Xiang (Kevin) Li <kevinli020508@gmail.com> +Xiang Chen <46052474+x14ngch3n@users.noreply.github.com> Xiangyan Sun <wishstudio@gmail.com> Xiao-Yong Jin <jinxiaoyong@gmail.com> xiaobing318 <71554036+xiaobing318@users.noreply.github.com> xiaofei <hbuxiaofei@gmail.com> XiaotaoChen <chenxiaotao1234@gmail.com> Xiaoyi Chen <cxychina@gmail.com> +Xie Wenxiang <123370282+DreamingWater@users.noreply.github.com> Xie Yanbo <xieyanbo@gmail.com> Xingchen Song(宋星辰) <xingchensong1996@163.com> Xinpeng Dou <15529241576@163.com> @@ -1947,19 +2141,25 @@ xris99 <79798089+xris99@users.noreply.github.com> Xuan Son Nguyen <thichthat@gmail.com> Xuan-Son Nguyen <son@huggingface.co> Xuan-Son Nguyen <thichthat@gmail.com> +Xue Zhenliang <riteme@users.noreply.github.com> +XZiar <15145384+XZiar@users.noreply.github.com> y198 <90976397+y198nt@users.noreply.github.com> yael-works <106673277+yael-works@users.noreply.github.com> YaelGitAccount <38328157276@mby.co.il> YaelLogic <y0548591250@gmail.com> Yaiko <elyaiko@hotmail.com> Yakine Tahtah <96926916+ReinforcedKnowledge@users.noreply.github.com> +yanghong <228148915+YangHong7@users.noreply.github.com> YangLe <smilingpoplar@gmail.com> yangli2 <yangli2@gmail.com> +Yangyu Chen <cyy@cyyself.name> Yaniss Amazouz <yaniss91600@gmail.com> Yann Follet <131855179+YannFollet@users.noreply.github.com> Yanzhao Wang <yanzhaow@qti.qualcomm.com> +Yanzhao Wang <yzwang1996@gmail.com> Yarden Tal <yardent@qti.qualcomm.com> YardenTal44 <yardent@qti.qualcomm.com> +yarik <158273159+dazzywi@users.noreply.github.com> Yaroslav <yaroslav.yashin@me.com> Yash Raj Pandey <55940078+devYRPauli@users.noreply.github.com> Yavor Ivanov <yavorgenadiev@gmail.com> @@ -1979,15 +2179,19 @@ Yishuo Wang <MeouSker77@outlook.com> Yiwei Shao <44545837+njsyw1997@users.noreply.github.com> ymcki <84055651+ymcki@users.noreply.github.com> ynankani <ynankani@nvidia.com> +yomi <3527628634@qq.com> +Yonghye Kwon <developer.0hye@gmail.com> Yongmin Yoo 유용민 <yymin1022@gmail.com> Yongyue Sun <abioy.sun@gmail.com> Yoshi Suhara <y.suhara@gmail.com> Yoshi Suhara <ysuhara@nvidia.com> Yoshi_likes_e4 <104140648+pt13762104@users.noreply.github.com> Younes Belkada <49240599+younesbelkada@users.noreply.github.com> +Yu Chengye <60293095+kabu1204@users.noreply.github.com> Yuanhao Ji <jiyuanhao@apache.org> Yuannan <yuannan@users.noreply.github.com> Yueh-Po Peng <94939112+y10ab1@users.noreply.github.com> +Yufeng He <40085740+he-yufeng@users.noreply.github.com> Yüg <eugeniosegalaweb@gmail.com> Yui <dev@sleepyyui.com> Yuichiro Utsumi <81412151+utsumi-fj@users.noreply.github.com> @@ -2003,6 +2207,7 @@ Yuval Peled <31162840+Yuval-Peled@users.noreply.github.com> Yuxuan Zhang <2448370773@qq.com> yzyyzyhhh <96101183+happyyzy@users.noreply.github.com> Z <coffeevampirebusiness@gmail.com> +z <faichou.zh@gmail.com> Zach Winter <contact@zachwinter.com> Zack Li <39573601+zhiyuan8@users.noreply.github.com> Zagaj <m.zagajewska@gmail.com> @@ -2017,6 +2222,7 @@ zhangkaihuo <zhangkaihuo@gmail.com> zhangrunda <zhangrunda1234@outlook.com> zhangtao2-1 <478679312@qq.com> ZHAOKAI WANG <sanxianwei@163.com> +Zhaolun Yin <129580161+ZhaolunYin@users.noreply.github.com> Zheng.Deng <32841220+dengzheng-cloud@users.noreply.github.com> zhentaoyu <zhentao.yu@intel.com> Zhenwei Jin <109658203+kylo5aby@users.noreply.github.com> diff --git a/CMakeLists.txt b/CMakeLists.txt index 3086e81b1972..e37c8aa4cbe7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ include(CheckIncludeFileCXX) ### llama.cpp version set(LLAMA_VERSION_MAJOR 0) -set(LLAMA_VERSION_MINOR 6) +set(LLAMA_VERSION_MINOR 8) set(LLAMA_VERSION_PATCH 0) set(LLAMA_VERSION_BASE "${LLAMA_VERSION_MAJOR}.${LLAMA_VERSION_MINOR}.${LLAMA_VERSION_PATCH}") @@ -103,7 +103,7 @@ endif() # subprocess spawning isn't a supported/sandbox-friendly operation on mobile OSes or in WASM if (CMAKE_SYSTEM_NAME STREQUAL "iOS" OR CMAKE_SYSTEM_NAME STREQUAL "Android" OR ANDROID - OR CMAKE_SYSTEM_NAME STREQUAL "Emscripten" OR EMSCRIPTEN) + OR CMAKE_SYSTEM_NAME STREQUAL "Emscripten" OR EMSCRIPTEN OR CMAKE_SYSTEM_NAME STREQUAL "WASI") set(LLAMA_SUBPROCESS_DEFAULT OFF) else() set(LLAMA_SUBPROCESS_DEFAULT ON) @@ -136,6 +136,7 @@ option(LLAMA_BUILD_SERVER "llama: build server example" option(LLAMA_BUILD_APP "llama: build the unified binary" ${LLAMA_STANDALONE}) option(LLAMA_BUILD_UI "llama: build the embedded Web UI for server" OFF) option(LLAMA_USE_PREBUILT_UI "llama: use prebuilt UI from HF Bucket when available" ON) +option(LLAMA_CONNECT "llama: include the llama-connect tool (downloads a prebuilt binary)" OFF) option(LLAMA_TOOLS_INSTALL "llama: install tools" ${LLAMA_TOOLS_INSTALL_DEFAULT}) option(LLAMA_TESTS_INSTALL "llama: install tests" ON) @@ -149,6 +150,7 @@ option(LLAMA_LLGUIDANCE "llama-common: include LLGuidance library for structured # Required for relocatable CMake package include(${CMAKE_CURRENT_SOURCE_DIR}/cmake/build-info.cmake) include(${CMAKE_CURRENT_SOURCE_DIR}/cmake/common.cmake) +include(${CMAKE_CURRENT_SOURCE_DIR}/cmake/win-app.cmake) if (NOT DEFINED LLAMA_BUILD_NUMBER) set(LLAMA_BUILD_NUMBER ${BUILD_NUMBER}) @@ -268,6 +270,8 @@ if (LLAMA_BUILD_MTMD AND NOT (LLAMA_BUILD_COMMON AND LLAMA_BUILD_TOOLS)) add_subdirectory(tools/mtmd) endif() +llama_apply_app_manifests() + # # install # diff --git a/CODEOWNERS b/CODEOWNERS index b9762685b5bd..a1e27dec368f 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -2,20 +2,29 @@ # multiple collaborators per item can be specified # # ggml-org/ci : CISC, danbev, ggerganov, netrunnereve, ngxson, taronaeo +# ggml-org/ggml-base : aendk, fairydreaming, ggerganov # ggml-org/ggml-cann : hipudding -# ggml-org/ggml-cuda : JohannesGaessler, am17an, IMbackK, ORippler +# ggml-org/ggml-cpu : angt, chaxu01, ggerganov, max-krasnyansky, taronaeo +# ggml-org/ggml-cuda : am17an, gaugarg-nv, IMbackK, JohannesGaessler, ORippler, thelittlefireman, ynankani +# ggml-org/ggml-et : marty1885 # ggml-org/ggml-hexagon : lhez, max-krasnyansky -# ggml-org/ggml-metal : ggerganov +# ggml-org/ggml-hip : IMbackK, thelittlefireman +# ggml-org/ggml-metal : forforever73, ggerganov, jhen0409, masterFoad # ggml-org/ggml-opencl : lhez, max-krasnyansky -# ggml-org/ggml-rpc : rgerganov -# ggml-org/ggml-sycl : arthw +# ggml-org/ggml-openvino : ravi9, wine99 +# ggml-org/ggml-riscv : xctan +# ggml-org/ggml-rpc : am17an, rgerganov +# ggml-org/ggml-sycl : arthw, Titaniumtown # ggml-org/ggml-vulkan : 0cc4m, jeffbolznv # ggml-org/ggml-webgpu : reeselevine, yomaytk -# ggml-org/ggml-zdnn : taronaeo -# ggml-org/llama-common : ggerganov, aldehir, angt, danbev, ngxson, pwilkin +# ggml-org/ggml-zdnn : AlekseiNikiforovIBM, Andreas-Krebbel, taronaeo +# ggml-org/llama-base : am17an, CISC, ggerganov, ngxson, sanmai, ServeurpersoCom +# ggml-org/llama-common : aldehir, angt, bartowski1182, danbev, ggerganov, ngxson, nikwen, pwilkin, ruixiang63, sanmai +# ggml-org/llama-examples : ggerganov +# ggml-org/llama-models : CISC, danbev, ggerganov, ngxson # ggml-org/llama-mtmd : ngxson -# ggml-org/llama-server : ggerganov, ngxson, allozaur, angt, ServeurpersoCom -# ggml-org/llama-ui : allozaur +# ggml-org/llama-server : allozaur, angt, ggerganov, ngxson, ServeurpersoCom +# ggml-org/llama-ui : allozaur /.devops/*.Dockerfile @ngxson /.github/actions/ @ggml-org/ci @@ -29,28 +38,12 @@ /conversion/ @CISC /convert_*.py @CISC /docs/backend/snapdragon/ @ggml-org/ggml-hexagon -/examples/batched.swift/ @ggerganov -/examples/batched/ @ggerganov -/examples/convert-llama2c-to-ggml/ @ggerganov +/examples/ @ggml-org/llama-examples /examples/debug/ @danbev @pwilkin -/examples/deprecation-warning/ @ggerganov /examples/diffusion/ @am17an -/examples/embedding/ @ggerganov -/examples/eval-callback/ @ggerganov -/examples/export-docs/ @ggerganov -/examples/gen-docs/ @ggerganov -/examples/gguf/ @ggerganov /examples/llama.android/ @ggerganov @hanyin-arm @naco-siren -/examples/llama.swiftui/ @ggerganov -/examples/llama.vim @ggerganov -/examples/lookahead/ @ggerganov /examples/lookup/ @JohannesGaessler /examples/model-conversion/ @danbev -/examples/parallel/ @ggerganov -/examples/passkey/ @ggerganov -/examples/retrieval/ @ggerganov -/examples/speculative-simple/ @ggerganov -/examples/speculative/ @ggerganov /ggml/cmake/ @ggerganov /ggml/include/ @ggerganov /ggml/src/ggml-backend-meta.cpp @JohannesGaessler @@ -62,7 +55,7 @@ /ggml/src/ggml-cuda/ @ggml-org/ggml-cuda /ggml/src/ggml-cuda/vendors/hip.h @IMbackK /ggml/src/ggml-hexagon/ @ggml-org/ggml-hexagon -/ggml/src/ggml-hip/ @IMbackK +/ggml/src/ggml-hip/ @ggml-org/ggml-hip /ggml/src/ggml-et/ @marty1885 /ggml/src/ggml-impl.h @ggerganov /ggml/src/ggml-metal/ @ggml-org/ggml-metal @@ -76,7 +69,7 @@ /ggml/src/ggml-virtgpu/ @kpouget /ggml/src/ggml-vulkan/ @ggml-org/ggml-vulkan /ggml/src/ggml-webgpu/ @ggml-org/ggml-webgpu -/ggml/src/ggml-zdnn/ @ggml-org/ggml-zdnn @Andreas-Krebbel @AlekseiNikiforovIBM +/ggml/src/ggml-zdnn/ @ggml-org/ggml-zdnn /ggml/src/ggml-zendnn/ @avinashcpandey @Jiten1parmar /ggml/src/ggml.c @ggerganov /ggml/src/ggml.cpp @ggerganov @@ -87,14 +80,14 @@ /scripts/get* @ggerganov /scripts/sync* @ggerganov /scripts/snapdragon/ @ggml-org/ggml-hexagon -/src/ @ggerganov +/src/ @ggml-org/llama-base /src/llama-adapter.* @CISC /src/llama-arch.* @CISC /src/llama-chat.* @ngxson /src/llama-graph.* @CISC /src/llama-model.* @CISC /src/llama-vocab.* @CISC -/src/models/ @CISC +/src/models/ @ggml-org/llama-models /tests/ @ggerganov /tests/test-chat.* @pwilkin /tests/test-server-component.cpp @ggml-org/llama-server diff --git a/ci/run.sh b/ci/run.sh index 8bebb8b9ad9d..30a6bf329147 100755 --- a/ci/run.sh +++ b/ci/run.sh @@ -185,18 +185,28 @@ fi ## helpers -# download a file if it does not exist or if it is outdated +# download a file unless already cached in $MNT function gg_wget { local out=$1 local url=$2 local cwd=`pwd` + local name=`basename $url` + local tmp=.gg-wget.$$.tmp mkdir -p $out cd $out - # should not re-download if file is the same - wget -nv -c -N $url + # cache first: HF artifacts are static, HF sends no Last-Modified for -N + if [ ! -s $name ]; then + # publish with mv: concurrent runners never read partial files + rm -rf $tmp && mkdir $tmp + (cd $tmp && wget -nv $url) + if [ -s $tmp/$name ]; then + mv -f $tmp/$name $name + fi + rm -rf $tmp + fi cd $cwd } @@ -254,7 +264,7 @@ function gg_run_ctest_release { (time cmake --build . --config Release -j$(nproc)) 2>&1 | tee -a $OUT/${ci}-make.log if [ -z ${GG_BUILD_LOW_PERF} ]; then - (time ctest -C Release --output-on-failure -L 'main|python' ${CTEST_EXTRA}) 2>&1 | tee -a $OUT/${ci}-ctest.log + (time ctest -C Release --output-on-failure -L main ${CTEST_EXTRA}) 2>&1 | tee -a $OUT/${ci}-ctest.log else (time ctest -C Release --output-on-failure -L main -E test-opt ${CTEST_EXTRA}) 2>&1 | tee -a $OUT/${ci}-ctest.log fi @@ -312,8 +322,8 @@ function gg_run_test_scripts { set -e - (cd ./tools/gguf-split && time bash tests.sh "$SRC/build-ci-release/bin" "$MNT/models") 2>&1 | tee -a $OUT/${ci}-scripts.log - (cd ./tools/quantize && time bash tests.sh "$SRC/build-ci-release/bin" "$MNT/models") 2>&1 | tee -a $OUT/${ci}-scripts.log + (cd ./tools/gguf-split && time bash tests.sh "$SRC/build-ci-release/bin" "$OUT/scratch") 2>&1 | tee -a $OUT/${ci}-scripts.log + (cd ./tools/quantize && time bash tests.sh "$SRC/build-ci-release/bin" "$OUT/scratch") 2>&1 | tee -a $OUT/${ci}-scripts.log set +e } @@ -374,10 +384,14 @@ function gg_run_qwen3_0_6b { gg_wget models-mnt/wikitext/ https://huggingface.co/datasets/ggml-org/ci/resolve/main/wikitext-2-raw-v1.zip - unzip -o models-mnt/wikitext/wikitext-2-raw-v1.zip -d models-mnt/wikitext/ + + rm -rf $OUT/scratch/qwen3-0.6B $OUT/scratch/wikitext + mkdir -p $OUT/scratch/qwen3-0.6B + unzip -o models-mnt/wikitext/wikitext-2-raw-v1.zip -d $OUT/scratch/wikitext/ path_models="../models-mnt/qwen3/0.6B" - path_wiki="../models-mnt/wikitext/wikitext-2-raw" + path_local="$OUT/scratch/qwen3-0.6B" + path_wiki="$OUT/scratch/wikitext/wikitext-2-raw" rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release @@ -386,99 +400,78 @@ function gg_run_qwen3_0_6b { (cmake -G "${CMAKE_GENERATOR}" -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log (time cmake --build . --config Release -j$(nproc)) 2>&1 | tee -a $OUT/${ci}-make.log - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf --outtype f16 - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-bf16.gguf --outtype bf16 - - model_f16="${path_models}/ggml-model-f16.gguf" - model_bf16="${path_models}/ggml-model-bf16.gguf" - model_q8_0="${path_models}/ggml-model-q8_0.gguf" - model_q4_0="${path_models}/ggml-model-q4_0.gguf" - model_q4_1="${path_models}/ggml-model-q4_1.gguf" - model_q5_0="${path_models}/ggml-model-q5_0.gguf" - model_q5_1="${path_models}/ggml-model-q5_1.gguf" - model_q2_k="${path_models}/ggml-model-q2_k.gguf" - model_q3_k="${path_models}/ggml-model-q3_k.gguf" - model_q4_k="${path_models}/ggml-model-q4_k.gguf" - model_q5_k="${path_models}/ggml-model-q5_k.gguf" - model_q6_k="${path_models}/ggml-model-q6_k.gguf" + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_local}/ggml-model-f16.gguf --outtype f16 + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_local}/ggml-model-bf16.gguf --outtype bf16 + + model_f16="${path_local}/ggml-model-f16.gguf" + model_bf16="${path_local}/ggml-model-bf16.gguf" + model_q4_0="${path_local}/ggml-model-q4_0.gguf" wiki_test="${path_wiki}/wiki.test.raw" - ./bin/llama-quantize ${model_bf16} ${model_q8_0} q8_0 $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q4_0} q4_0 $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q4_1} q4_1 $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q5_0} q5_0 $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q5_1} q5_1 $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q2_k} q2_k $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q3_k} q3_k $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q4_k} q4_k $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q5_k} q5_k $(nproc) - ./bin/llama-quantize ${model_bf16} ${model_q6_k} q6_k $(nproc) + function check_ppl { + qnt="$1" + ppl=$(echo "$2" | grep -oE "[0-9]+\.[0-9]+" | tail -n 1) + + if [ $(echo "$ppl > 20.0" | bc) -eq 1 ]; then + printf ' - %s @ %s (FAIL: ppl > 20.0)\n' "$qnt" "$ppl" + return 20 + fi + + printf ' - %s @ %s OK\n' "$qnt" "$ppl" + return 0 + } + + for qnt in q8_0 q4_0 q4_1 q5_0 q5_1 q2_k q3_k q4_k q5_k q6_k; do + model="${path_local}/ggml-model-${qnt}.gguf" + + ./bin/llama-quantize ${model_bf16} ${model} ${qnt} $(nproc) + + (time ./bin/llama-completion -no-cnv --model ${model} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-${qnt}.log + (time ./bin/llama-perplexity --model ${model} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-${qnt}.log + + # note: ppl > 20.0 for q2_k with this model + if [ "${qnt}" != "q2_k" ]; then + check_ppl "${qnt}" "$(cat $OUT/${ci}-tg-${qnt}.log | grep "^\[1\]")" + fi + + if [ "${qnt}" = "q4_0" ]; then + # q4_0 is kept for other tests + q4_0="${path_models}/ggml-model-q4_0.gguf" + ln ${model} "$q4_0" 2>/dev/null || { cp ${model} $q4_0.tmp.$$ && mv -f $q4_0.tmp.$$ $q4_0; } + else + rm -f ${model} + fi + done (time ./bin/llama-fit-params --model ${model_f16} 2>&1 | tee -a $OUT/${ci}-fp-f16.log) (time ./bin/llama-completion -no-cnv --model ${model_f16} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log (time ./bin/llama-completion -no-cnv --model ${model_bf16} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-bf16.log - (time ./bin/llama-completion -no-cnv --model ${model_q8_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-completion -no-cnv --model ${model_q4_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-completion -no-cnv --model ${model_q4_1} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-completion -no-cnv --model ${model_q5_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-completion -no-cnv --model ${model_q5_1} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-completion -no-cnv --model ${model_q2_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-completion -no-cnv --model ${model_q3_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-completion -no-cnv --model ${model_q4_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-completion -no-cnv --model ${model_q5_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-completion -no-cnv --model ${model_q6_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log (time ./bin/llama-perplexity --model ${model_f16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log if [ -z ${GG_BUILD_NO_BF16} ]; then (time ./bin/llama-perplexity --model ${model_bf16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-bf16.log fi - (time ./bin/llama-perplexity --model ${model_q8_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-perplexity --model ${model_q4_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-perplexity --model ${model_q4_1} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-perplexity --model ${model_q5_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-perplexity --model ${model_q5_1} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-perplexity --model ${model_q2_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-perplexity --model ${model_q3_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-perplexity --model ${model_q4_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-perplexity --model ${model_q5_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-perplexity --model ${model_q6_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log (time ./bin/llama-imatrix --model ${model_f16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-imatrix.log - (time ./bin/test-llama-context --model ${model_q4_0} -ngl 10 -c 1024 -fa off --no-op-offload) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log + # TODO: these tests are extremely slow on WebGPU - re-enable when fixed + # https://github.com/ggml-org/llama.cpp/actions/runs/39639985732 + if [ -z ${GG_BUILD_WEBGPU} ]; then + (time ./bin/test-llama-context --model ${model_q4_0} -ngl 10 -c 1024 -fa off --no-op-offload) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log + (time ./bin/test-llama-context --model ${model_q4_0} -ngl 99 -c 1024 -fa off ) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log + fi (time ./bin/test-llama-context --model ${model_q4_0} -ngl 10 -c 1024 -fa on --no-op-offload) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log - (time ./bin/test-llama-context --model ${model_q4_0} -ngl 99 -c 1024 -fa off ) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log (time ./bin/test-llama-context --model ${model_q4_0} -ngl 99 -c 1024 -fa on ) 2>&1 | tee -a $OUT/${ci}-test-llama-context.log - function check_ppl { - qnt="$1" - ppl=$(echo "$2" | grep -oE "[0-9]+\.[0-9]+" | tail -n 1) - - if [ $(echo "$ppl > 20.0" | bc) -eq 1 ]; then - printf ' - %s @ %s (FAIL: ppl > 20.0)\n' "$qnt" "$ppl" - return 20 - fi - - printf ' - %s @ %s OK\n' "$qnt" "$ppl" - return 0 - } - check_ppl "f16" "$(cat $OUT/${ci}-tg-f16.log | grep "^\[1\]")" if [ -z ${GG_BUILD_NO_BF16} ]; then check_ppl "bf16" "$(cat $OUT/${ci}-tg-bf16.log | grep "^\[1\]")" fi - check_ppl "q8_0" "$(cat $OUT/${ci}-tg-q8_0.log | grep "^\[1\]")" - check_ppl "q4_0" "$(cat $OUT/${ci}-tg-q4_0.log | grep "^\[1\]")" - check_ppl "q4_1" "$(cat $OUT/${ci}-tg-q4_1.log | grep "^\[1\]")" - check_ppl "q5_0" "$(cat $OUT/${ci}-tg-q5_0.log | grep "^\[1\]")" - check_ppl "q5_1" "$(cat $OUT/${ci}-tg-q5_1.log | grep "^\[1\]")" - #check_ppl "q2_k" "$(cat $OUT/${ci}-tg-q2_k.log | grep "^\[1\]")" # note: ppl > 20.0 for this quant and model - check_ppl "q3_k" "$(cat $OUT/${ci}-tg-q3_k.log | grep "^\[1\]")" - check_ppl "q4_k" "$(cat $OUT/${ci}-tg-q4_k.log | grep "^\[1\]")" - check_ppl "q5_k" "$(cat $OUT/${ci}-tg-q5_k.log | grep "^\[1\]")" - check_ppl "q6_k" "$(cat $OUT/${ci}-tg-q6_k.log | grep "^\[1\]")" + + # scratch is rebuilt on every run; q4_0 is already published to $MNT + rm -rf $OUT/scratch/qwen3-0.6B $OUT/scratch/wikitext set +e } @@ -501,6 +494,8 @@ function gg_run_embd_bge_small { gg_wget models-mnt/bge-small/1_Pooling https://huggingface.co/BAAI/bge-small-en-v1.5/raw/main/1_Pooling/config.json path_models="../models-mnt/bge-small" + path_local="$OUT/scratch/bge-small" + rm -rf $path_local && mkdir -p $path_local rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release @@ -509,10 +504,10 @@ function gg_run_embd_bge_small { (cmake -G "${CMAKE_GENERATOR}" -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log (time cmake --build . --config Release -j$(nproc)) 2>&1 | tee -a $OUT/${ci}-make.log - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_local}/ggml-model-f16.gguf - model_f16="${path_models}/ggml-model-f16.gguf" - model_q8_0="${path_models}/ggml-model-q8_0.gguf" + model_f16="${path_local}/ggml-model-f16.gguf" + model_q8_0="${path_local}/ggml-model-q8_0.gguf" ./bin/llama-quantize ${model_f16} ${model_q8_0} q8_0 @@ -521,6 +516,8 @@ function gg_run_embd_bge_small { (time ./bin/llama-embedding --model ${model_f16} -p "I believe the meaning of life is" -ngl 99 -c 0 --no-op-offload) 2>&1 | tee -a $OUT/${ci}-tg-f16.log (time ./bin/llama-embedding --model ${model_q8_0} -p "I believe the meaning of life is" -ngl 99 -c 0 --no-op-offload) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log + rm -rf $path_local + set +e } @@ -537,6 +534,8 @@ function gg_run_rerank_tiny { gg_wget models-mnt/rerank-tiny/ https://huggingface.co/jinaai/jina-reranker-v1-tiny-en/raw/main/vocab.json path_models="../models-mnt/rerank-tiny" + path_local="$OUT/scratch/rerank-tiny" + rm -rf $path_local && mkdir -p $path_local rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release @@ -545,9 +544,9 @@ function gg_run_rerank_tiny { (cmake -G "${CMAKE_GENERATOR}" -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log (time cmake --build . --config Release -j$(nproc)) 2>&1 | tee -a $OUT/${ci}-make.log - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_local}/ggml-model-f16.gguf - model_f16="${path_models}/ggml-model-f16.gguf" + model_f16="${path_local}/ggml-model-f16.gguf" (time ./bin/llama-fit-params --model ${model_f16} 2>&1 | tee -a $OUT/${ci}-fp-f16.log) @@ -577,6 +576,8 @@ function gg_run_rerank_tiny { check_score "rerank score 1" "$(cat $OUT/${ci}-rk-f16.log | grep "rerank score 1")" "0.00" "0.05" | tee -a $OUT/${ci}-rk-f16.log check_score "rerank score 2" "$(cat $OUT/${ci}-rk-f16.log | grep "rerank score 2")" "0.10" "0.30" | tee -a $OUT/${ci}-rk-f16.log + rm -rf $path_local + set +e } @@ -683,11 +684,11 @@ if [ -z ${GG_BUILD_LOW_PERF} ]; then ln -sfn ${mnt_models} ${SRC}/models-mnt # Create a fresh python3 venv and enter it - if ! python3 -m venv "$MNT/venv"; then - echo "Error: Failed to create Python virtual environment at $MNT/venv." + if ! python3 -m venv "$OUT/venv"; then + echo "Error: Failed to create Python virtual environment at $OUT/venv." exit 1 fi - source "$MNT/venv/bin/activate" + source "$OUT/venv/bin/activate" pip install -r ${SRC}/requirements.txt --disable-pip-version-check pip install --editable gguf-py --disable-pip-version-check diff --git a/cmake/common.cmake b/cmake/common.cmake index bcf403e0ee37..ee8d5bf7b1f2 100644 --- a/cmake/common.cmake +++ b/cmake/common.cmake @@ -2,7 +2,7 @@ include("ggml/cmake/common.cmake") function(llama_add_compile_flags) if (LLAMA_FATAL_WARNINGS) - if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" OR CMAKE_CXX_COMPILER_ID MATCHES "Clang") + if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" OR CMAKE_CXX_COMPILER_ID MATCHES "Clang" OR CMAKE_CXX_COMPILER_ID MATCHES "IntelLLVM") list(APPEND C_FLAGS -Werror) list(APPEND CXX_FLAGS -Werror) elseif (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC") diff --git a/cmake/win-app.cmake b/cmake/win-app.cmake new file mode 100644 index 000000000000..5456e48fd2c6 --- /dev/null +++ b/cmake/win-app.cmake @@ -0,0 +1,66 @@ +set(LLAMA_WIN_APP_MANIFEST "${CMAKE_CURRENT_LIST_DIR}/../common/win-app.manifest") + +if(WIN32) + if(MSVC OR CMAKE_CXX_SIMULATE_ID STREQUAL "MSVC") + set(LLAMA_WIN_APP_MSVC_ABI TRUE) + else() + set(LLAMA_WIN_APP_MSVC_ABI FALSE) + endif() + + if(NOT LLAMA_WIN_APP_MSVC_ABI) + if(CMAKE_VERSION VERSION_LESS 3.21) + message(FATAL_ERROR "CMake 3.21 or newer is required to build for Windows with the GNU ABI") + endif() + enable_language(RC) + set(LLAMA_WIN_APP_MANIFEST_RC "${CMAKE_CURRENT_BINARY_DIR}/win-app-manifest.rc") + configure_file("${CMAKE_CURRENT_LIST_DIR}/win-app.rc.in" "${LLAMA_WIN_APP_MANIFEST_RC}" @ONLY) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS "${LLAMA_WIN_APP_MANIFEST}") + endif() +endif() + +function(llama_add_app_manifest target) + if(NOT WIN32) + return() + endif() + get_target_property(_aliased ${target} ALIASED_TARGET) + if(_aliased) + return() + endif() + get_target_property(_type ${target} TYPE) + if(NOT _type STREQUAL "EXECUTABLE") + return() + endif() + if(LLAMA_WIN_APP_MSVC_ABI) + target_sources(${target} PRIVATE "${LLAMA_WIN_APP_MANIFEST}") + else() + if(NOT TARGET llama-win-app-manifest-res) + add_library(llama-win-app-manifest-res OBJECT ${LLAMA_WIN_APP_MANIFEST_RC}) + set_source_files_properties(${LLAMA_WIN_APP_MANIFEST_RC} PROPERTIES OBJECT_DEPENDS "${LLAMA_WIN_APP_MANIFEST}") + endif() + target_link_libraries(${target} PRIVATE "$<TARGET_OBJECTS:llama-win-app-manifest-res>") + endif() +endfunction() + +function(llama_apply_app_manifests_dir dir) + get_property(_targets DIRECTORY "${dir}" PROPERTY BUILDSYSTEM_TARGETS) + foreach(_target IN LISTS _targets) + llama_add_app_manifest(${_target}) + endforeach() + get_property(_subdirs DIRECTORY "${dir}" PROPERTY SUBDIRECTORIES) + foreach(_subdir IN LISTS _subdirs) + llama_apply_app_manifests_dir("${_subdir}") + endforeach() +endfunction() + +function(llama_apply_app_manifests) + if(NOT WIN32) + return() + endif() + get_property(_subdirs DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" PROPERTY SUBDIRECTORIES) + foreach(_dir IN LISTS _subdirs) + get_filename_component(_name "${_dir}" NAME) + if(_name STREQUAL "app" OR _name STREQUAL "examples" OR _name STREQUAL "pocs" OR _name STREQUAL "tests" OR _name STREQUAL "tools") + llama_apply_app_manifests_dir("${_dir}") + endif() + endforeach() +endfunction() diff --git a/cmake/win-app.rc.in b/cmake/win-app.rc.in new file mode 100644 index 000000000000..38288a5f848d --- /dev/null +++ b/cmake/win-app.rc.in @@ -0,0 +1,3 @@ +// generated from cmake/win-app.rc.in - do not edit +// RT_MANIFEST (24), ID 1: the application manifest shared by all llama.cpp executables +1 24 "@LLAMA_WIN_APP_MANIFEST@" diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 2b307c59d32d..8e3c88dac9dc 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -78,6 +78,8 @@ add_library(${TARGET} download.h fit.cpp fit.h + file-lock.cpp + file-lock.h hf-cache.cpp hf-cache.h http.h @@ -184,3 +186,8 @@ if (LLAMA_LLGUIDANCE) endif() target_link_libraries(${TARGET} PUBLIC llama Threads::Threads) + +if (CMAKE_SYSTEM_NAME MATCHES "AIX") + # AIX's flock() function comes from libbsd.a + target_link_libraries(${TARGET} PRIVATE -lbsd) +endif() diff --git a/common/arg.cpp b/common/arg.cpp index 29f6df32fe5f..e3ab084c67f9 100644 --- a/common/arg.cpp +++ b/common/arg.cpp @@ -12,16 +12,6 @@ #include "speculative.h" #include "preset.h" -// fix problem with std::min and std::max -#if defined(_WIN32) -#define WIN32_LEAN_AND_MEAN -#ifndef NOMINMAX -# define NOMINMAX -#endif -#include <windows.h> -#include <shellapi.h> -#endif - #include <algorithm> #include <cinttypes> #include <climits> @@ -38,20 +28,6 @@ #include <thread> // for hardware_concurrency #include <vector> -#ifndef __EMSCRIPTEN__ -#ifdef __linux__ -#include <linux/limits.h> -#elif defined(_WIN32) -# if !defined(PATH_MAX) -# define PATH_MAX MAX_PATH -# endif -#elif defined(_AIX) -#include <sys/limits.h> -#else -#include <sys/syslimits.h> -#endif -#endif - #define LLAMA_MAX_URL_LENGTH 2084 // Maximum URL Length in Chrome: 2083 using json = common_json; @@ -351,7 +327,7 @@ static bool parse_bool_value(const std::string & value) { static std::string get_default_local_path(const std::string & url) { auto f = string_split<std::string>(url, '#').front(); f = string_split<std::string>(f, '?').front(); - return fs_path_to_utf8(fs_get_cache_file(string_split<std::string>(f, '/').back())); + return fs_get_cache_file(string_split<std::string>(f, '/').back()).string(); } static bool spec_types_is_default(const common_params & params) { @@ -470,6 +446,14 @@ void common_models_handler_apply(common_models_handler & handler, common_params auto opts = handler.opts; // copy opts.callback = callback; + // another process may hold the cache lock during finalization: + // let the download callback cancel that wait too + auto finalize = [callback](const hf_cache::hf_file & f) { + return hf_cache::finalize_file(f, [callback]() { + return !(callback && callback->is_cancelled()); + }); + }; + // handle plain "url" if needed auto handle_url = [&](common_params_model & model) { if (!model.url.empty()) { @@ -518,7 +502,7 @@ void common_models_handler_apply(common_models_handler & handler, common_params } // handle hf_plan tasks - auto add_tasks = [&opts, &tasks](const hf_cache::hf_files & model_files, + auto add_tasks = [&opts, &tasks, &finalize](const hf_cache::hf_files & model_files, const hf_cache::hf_file & primary, common_params_model & model) { for (size_t i = 0; i < model_files.size(); ++i) { @@ -527,9 +511,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(model_file, opts, [&, is_primary]() { if (is_primary) { // the primary file is the first split (00001-of), use it as model path - model.path = hf_cache::finalize_file(model_file); + model.path = finalize(model_file); } else { - hf_cache::finalize_file(model_file); + finalize(model_file); } }); } @@ -581,9 +565,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan_spec.mtp, opts, [&]() { // only use the discovered MTP head when no draft path is set yet if (params.speculative.draft.mparams.path.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan_spec.mtp); + params.speculative.draft.mparams.path = finalize(plan_spec.mtp); } else { - hf_cache::finalize_file(plan_spec.mtp); + finalize(plan_spec.mtp); } }); } @@ -591,9 +575,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan_spec.dflash, opts, [&]() { // only use the discovered DFlash sidecar when no draft path is set yet if (params.speculative.draft.mparams.path.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan_spec.dflash); + params.speculative.draft.mparams.path = finalize(plan_spec.dflash); } else { - hf_cache::finalize_file(plan_spec.dflash); + finalize(plan_spec.dflash); } }); } @@ -601,9 +585,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan_spec.eagle3, opts, [&]() { // only use the discovered Eagle3 sidecar when no draft path is set yet if (params.speculative.draft.mparams.path.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan_spec.eagle3); + params.speculative.draft.mparams.path = finalize(plan_spec.eagle3); } else { - hf_cache::finalize_file(plan_spec.eagle3); + finalize(plan_spec.eagle3); } }); } @@ -611,9 +595,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan_spec.dspark, opts, [&]() { // only use the discovered DSpark sidecar when no draft path is set yet if (params.speculative.draft.mparams.path.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan_spec.dspark); + params.speculative.draft.mparams.path = finalize(plan_spec.dspark); } else { - hf_cache::finalize_file(plan_spec.dspark); + finalize(plan_spec.dspark); } }); } @@ -634,16 +618,16 @@ void common_models_handler_apply(common_models_handler & handler, common_params } if (!plan.mmproj.local_path.empty()) { tasks.emplace_back(plan.mmproj, opts, [&]() { - params.mmproj.path = hf_cache::finalize_file(plan.mmproj); + params.mmproj.path = finalize(plan.mmproj); }); } if (!plan.mtp.local_path.empty() && !had_spec_url) { tasks.emplace_back(plan.mtp, opts, [&]() { // only fall back to the discovered MTP head when no draft was explicitly provided if (params.speculative.draft.mparams.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan.mtp); + params.speculative.draft.mparams.path = finalize(plan.mtp); } else { - hf_cache::finalize_file(plan.mtp); + finalize(plan.mtp); } }); } @@ -651,9 +635,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan.dflash, opts, [&]() { // only fall back to the discovered DFlash sidecar when no draft was explicitly provided if (params.speculative.draft.mparams.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan.dflash); + params.speculative.draft.mparams.path = finalize(plan.dflash); } else { - hf_cache::finalize_file(plan.dflash); + finalize(plan.dflash); } }); } @@ -661,9 +645,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan.eagle3, opts, [&]() { // only fall back to the discovered Eagle3 sidecar when no draft was explicitly provided if (params.speculative.draft.mparams.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan.eagle3); + params.speculative.draft.mparams.path = finalize(plan.eagle3); } else { - hf_cache::finalize_file(plan.eagle3); + finalize(plan.eagle3); } }); } @@ -671,9 +655,9 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan.dspark, opts, [&]() { // only fall back to the discovered DSpark sidecar when no draft was explicitly provided if (params.speculative.draft.mparams.empty()) { - params.speculative.draft.mparams.path = hf_cache::finalize_file(plan.dspark); + params.speculative.draft.mparams.path = finalize(plan.dspark); } else { - hf_cache::finalize_file(plan.dspark); + finalize(plan.dspark); } }); } @@ -681,7 +665,7 @@ void common_models_handler_apply(common_models_handler & handler, common_params tasks.emplace_back(plan.preset, opts, [&]() { // if HF repo is a preset repo, we simply run server in router mode with the preset.ini file params.models_preset_hf = params.model.hf_repo; // only for showing a warning - params.models_preset = hf_cache::finalize_file(plan.preset); + params.models_preset = finalize(plan.preset); // clear the model so the server starts in router mode params.model.path.clear(); params.model.hf_repo.clear(); @@ -754,7 +738,7 @@ static void common_params_apply_system_config(common_params & params, llama_exam common_preset_context ctx(ex); ctx.ignore_unknown_keys = true; // the same config file is shared by all programs for (const auto & path : found) { - LOG_INF("using config file: %s\n", fs_path_to_utf8(path).c_str()); + LOG_INF("using config file: %s\n", path.string().c_str()); common_preset global; common_presets presets = ctx.load_from_ini(path, global); global.apply_to_params(params); @@ -916,7 +900,7 @@ static bool common_params_parse_ex(int argc, char ** argv, common_params_context // TODO @ngxson : maybe show a list of available models in CLI in this case bool can_skip_model = params.usage || params.completion || !params.server_base.empty(); if (!can_skip_model && params.model.path.empty()) { - throw std::invalid_argument("error: --model is required\n"); + throw std::invalid_argument("error: --model or -hf is required\n"); } } @@ -1251,44 +1235,7 @@ bool common_params_to_map(int argc, char ** argv, llama_example ex, std::map<com return true; } -#ifdef _WIN32 -struct utf8_argv { - std::vector<std::string> buf; - std::vector<char*> ptrs; -}; - -static utf8_argv make_utf8_argv() { - utf8_argv out; - int wargc = 0; - LPWSTR* wargv = CommandLineToArgvW(GetCommandLineW(), &wargc); - if (!wargv) return out; - - out.buf.reserve(wargc); - for (int i = 0; i < wargc; ++i) { - int n = WideCharToMultiByte(CP_UTF8, WC_ERR_INVALID_CHARS, wargv[i], -1, nullptr, 0, nullptr, nullptr); - if (n <= 0) { out.buf.emplace_back(); continue; } - auto& s = out.buf.emplace_back(); - s.resize(static_cast<size_t>(n - 1)); - (void)WideCharToMultiByte(CP_UTF8, 0, wargv[i], -1, s.data(), n, nullptr, nullptr); - } - LocalFree(wargv); - - out.ptrs.reserve(out.buf.size() + 1); - for (auto& s : out.buf) out.ptrs.push_back(s.data()); - out.ptrs.push_back(nullptr); - return out; -} -#endif - bool common_params_parse(int argc, char ** argv, common_params & params, llama_example ex, void(*print_usage)(int, char **)) { -#ifdef _WIN32 - auto utf8 = make_utf8_argv(); - // repair argv only when it matches the process command line - if (static_cast<int>(utf8.buf.size()) == argc) { - argv = utf8.ptrs.data(); - } -#endif - auto ctx_arg = common_params_parser_init(params, ex, print_usage); const common_params params_org = ctx_arg.params; // the example can modify the default params @@ -1717,10 +1664,11 @@ common_params_context common_params_parser_init(common_params & params, llama_ex ).set_env("LLAMA_ARG_CHECKPOINT_MIN_SPACING_NT").set_examples({LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-cram", "--cache-ram"}, "N", - string_format("set the maximum cache size in MiB (default: %d, -1 - no limit, 0 - disable)" + string_format("set the maximum cache size in MiB (default: %d, 0 for decision models, -1 - no limit, 0 - disable)" "[(more info)](https://github.com/ggml-org/llama.cpp/pull/16391)", params.cache_ram_mib), [](common_params & params, int value) { params.cache_ram_mib = value; + params.cache_ram_explicit = true; } ).set_env("LLAMA_ARG_CACHE_RAM").set_examples({LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_CLI})); add_opt(common_arg( @@ -3493,6 +3441,26 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.ui = value; } ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_UI")); + add_opt(common_arg( + {"--connect"}, + string_format("(experimental) open a peer-to-peer tunnel for server using llama-connect (default: %s)", params.server_connect ? "enabled" : "disabled"), + [](common_params & params) { + params.server_connect = true; + } + ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_CONNECT")); + add_opt(common_arg( + {"--connect-code"}, "CODE", + "manually specify a 40-character code for --connect (default: generate a new one for each run)", + [](common_params & params, const std::string & value) { + std::string val = value; + string_replace_all(val, "-", ""); + string_replace_all(val, " ", ""); + if (val.size() != 40) { + throw std::invalid_argument(string_format("error: invalid connect code '%s', must be 40 characters\n", value.c_str())); + } + params.server_connect_code = val; + } + ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_CONNECT_CODE")); add_opt(common_arg( {"--embedding", "--embeddings"}, string_format("restrict to only support embedding use case; use only with dedicated embedding models (default: %s)", params.embedding ? "enabled" : "disabled"), @@ -3679,6 +3647,13 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.models_max = value; } ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_MODELS_MAX")); + add_opt(common_arg( + {"--models-memory-margin"}, "N", + string_format("for router server, MiB of device memory to keep free per device, unload LRU models until a new one fits (default: %d, 0 = disabled)", params.models_memory_margin), + [](common_params & params, int value) { + params.models_memory_margin = value; + } + ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_MODELS_MEMORY_MARGIN")); add_opt(common_arg( {"--models-autoload"}, {"--no-models-autoload"}, @@ -4476,6 +4451,14 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.tts_lang = value; } ).set_examples({LLAMA_EXAMPLE_TTS})); + add_opt(common_arg( + {"--tts-voice"}, "VOICE", + "voice for audio generation (model-dependent)\n" + "see tts/README.md for per-model usage notes", + [](common_params & params, const std::string & value) { + params.tts_voice = value; + } + ).set_examples({LLAMA_EXAMPLE_TTS})); add_opt(common_arg( {"--tts-speaker-file"}, "FNAME", "speaker file path for audio generation", diff --git a/common/chat.cpp b/common/chat.cpp index 4856713082ac..5f956e64e6f3 100644 --- a/common/chat.cpp +++ b/common/chat.cpp @@ -190,10 +190,17 @@ json common_chat_msg::to_json_oaicompat(bool concat_typed_text) const { } else { auto & parts = jmsg["content"] = json::array(); for (const auto & part : content_parts) { - parts.push_back({ - {"type", part.type}, - {"text", part.text}, - }); + if (part.type == "tool_reference") { + parts.push_back({ + {"type", part.type}, + {"name", part.name}, + }); + } else { + parts.push_back({ + {"type", part.type}, + {"text", part.text}, + }); + } } } } else { @@ -309,6 +316,7 @@ struct common_chat_templates { bool has_explicit_template; // Model had builtin template or template overridden was specified. std::unique_ptr<common_chat_template> template_default; // always set (defaults to chatml) std::unique_ptr<common_chat_template> template_tool_use; + std::unique_ptr<common_chat_template> template_tts; // the prompt of a text to speak }; common_chat_tool_choice common_chat_tool_choice_parse_oaicompat(const std::string & tool_choice) { @@ -370,12 +378,16 @@ std::vector<common_chat_msg> common_chat_msgs_parse_oaicompat(const json & messa throw std::invalid_argument("Missing content part type: " + part.dump()); } const auto & type = part.at("type"); - if (type != "text" && type != "media_marker") { - throw std::invalid_argument("Unsupported content part type: " + type.dump()); - } common_chat_msg_content_part msg_part; msg_part.type = type; - msg_part.text = part.at("text"); + if (type == "text" || type == "media_marker") { + msg_part.text = part.at("text"); + } else if (type == "tool_reference") { + // names a request tool, the template renders its definition + msg_part.name = part.at("name"); + } else { + throw std::invalid_argument("Unsupported content part type: " + type.dump()); + } msg.content_parts.push_back(msg_part); } } else if (!content.is_null()) { @@ -428,6 +440,41 @@ std::vector<common_chat_msg> common_chat_msgs_parse_oaicompat(const json & messa if (message.contains("tool_call_id")) { msg.tool_call_id = message.at("tool_call_id"); } + { + json extra = json::object(); + for (const auto & [k, v] : message.items()) { + if (k != "role" && k != "content" && k != "tool_calls" && k != "reasoning_content" && + k != "name" && k != "tool_call_id") { + extra[k] = v; + } + } + if (has_tool_calls) { + // per tool call: keys besides type/function/id, and function keys besides name/arguments + json tc_extra = json::array(); + bool any = false; + for (const auto & tool_call : message.at("tool_calls")) { + json e = json::object(); + for (const auto & [k, v] : tool_call.items()) { + if (k != "type" && k != "function" && k != "id") { + e[k] = v; + } + } + for (const auto & [k, v] : tool_call.at("function").items()) { + if (k != "name" && k != "arguments") { + e["function"][k] = v; + } + } + any = any || !e.empty(); + tc_extra.push_back(e); + } + if (any) { + extra["__tool_call_extras"] = tc_extra; + } + } + if (!extra.empty()) { + msg.extra_json = extra.dump(); + } + } msgs.push_back(msg); } @@ -516,6 +563,50 @@ static json render_message_to_json(const std::vector<common_chat_msg> & msgs, co return messages_inp_normalizer(c).normalize(messages); } +// DeepSeek V4.1 reads non-OpenAI message keys and joins content blocks with "\n\n" around images, +// so keep media markers as separate text parts and restore the extra keys +static json render_message_to_json_deepseek_v4_1(const std::vector<common_chat_msg> & msgs, const jinja::caps & c) { + json messages = json::array(); + for (const auto & msg : msgs) { + json jmsg; + if (msg.contains_media() && msg.content.empty()) { + common_chat_msg typed = msg; + for (auto & part : typed.content_parts) { + part.type = "text"; + } + jmsg = typed.to_json_oaicompat(/* concat_typed_text= */ false); + } else { + jmsg = msg.to_json_oaicompat(/* concat_typed_text= */ false); + } + if (!msg.extra_json.empty()) { + const json extra = json::parse(msg.extra_json); + for (const auto & [k, v] : extra.items()) { + if (k == "__tool_call_extras") { + if (!jmsg.contains("tool_calls")) { + continue; + } + auto & tcs = jmsg.at("tool_calls"); + for (size_t i = 0; i < tcs.size() && i < v.size(); i++) { + for (const auto & [tk, tv] : v[i].items()) { + if (tk == "function") { + for (const auto & [fk, fv] : tv.items()) { + tcs[i]["function"][fk] = fv; + } + } else { + tcs[i][tk] = tv; + } + } + } + } else if (!jmsg.contains(k)) { + jmsg[k] = v; + } + } + } + messages.push_back(std::move(jmsg)); + } + return messages_inp_normalizer(c).normalize(messages); +} + // DEPRECATED: only used in tests json common_chat_msgs_to_json_oaicompat(const std::vector<common_chat_msg> & msgs, bool concat_typed_text) { jinja::caps c; @@ -531,13 +622,17 @@ json common_chat_tools_to_json_oaicompat(const std::vector<common_chat_tool> & t auto result = json::array(); for (const auto & tool : tools) { + json function { + { "name", tool.name }, + { "description", tool.description }, + { "parameters", json::parse(tool.parameters) }, + }; + if (tool.defer_loading) { + function["defer_loading"] = true; + } result.push_back({ { "type", "function" }, - { "function", { - { "name", tool.name }, - { "description", tool.description }, - { "parameters", json::parse(tool.parameters) }, - }}, + { "function", function }, }); } return result; @@ -574,10 +669,19 @@ std::vector<common_chat_tool> common_chat_tools_parse_oaicompat(const json & too } const auto & function = tool.at("function"); + + // "defer_loading" sits on the function, or on the tool next to "type"; the function wins + const json & defer = function.contains("defer_loading") ? function.at("defer_loading") + : tool.value("defer_loading", json(false)); + if (!defer.is_boolean()) { + throw std::invalid_argument("Expected 'defer_loading' to be a boolean, got " + defer.dump()); + } + result.push_back({ /* .name = */ function.at("name"), /* .description = */ function.value("description", ""), /* .parameters = */ function.value("parameters", json::object()).dump(), + /* .defer_loading = */ defer.get<bool>(), }); } } @@ -700,19 +804,70 @@ bool common_chat_templates_was_explicit(const struct common_chat_templates * tmp return tmpls->has_explicit_template; } -common_chat_prompt_preset common_chat_get_asr_prompt(const common_chat_templates * chat_templates) { +// renders a task template (e.g. "tts") with the given variables +static std::string common_chat_template_render(const common_chat_template & tmpl, const json & vars) { + jinja::context ctx(tmpl.source()); + jinja::global_from_json(ctx, vars, false); + ctx.set_val("bos_token", jinja::mk_val<jinja::value_string>(tmpl.bos_token())); + ctx.set_val("eos_token", jinja::mk_val<jinja::value_string>(tmpl.eos_token())); + jinja::runtime runtime(ctx); + return jinja::runtime::gather_string_parts(runtime.execute(tmpl.prog))->as_string().str(); +} + +// LFM3 format detection: template renders deferred tools inside <additional_tools>...</additional_tools> +static bool is_lfm3_template(const std::string & src) { + return src.find("<additional_tools>") != std::string::npos; +} + +// LFM3-Audio: a known language code maps to its name, no language lets the model detect it +static std::string lfm3_asr_system_prompt(const std::string & language) { + static const std::map<std::string, std::string> names = { + { "ar", "Arabic" }, { "da", "Danish" }, { "de", "German" }, { "el", "Greek" }, { "en", "English" }, + { "es", "Spanish" }, { "fi", "Finnish" }, { "fr", "French" }, { "he", "Hebrew" }, { "it", "Italian" }, + { "ja", "Japanese" }, { "ko", "Korean" }, { "nl", "Dutch" }, { "pl", "Polish" }, { "pt", "Portuguese" }, + { "sv", "Swedish" }, { "tr", "Turkish" }, { "zh", "Chinese" }, + }; + if (language.empty()) { + return "Perform ASR."; + } + std::string code = language; + std::transform(code.begin(), code.end(), code.begin(), [](unsigned char c) { return (char) std::tolower(c); }); + const auto it = names.find(code); + return "Perform ASR in " + (it != names.end() ? it->second : language) + "."; +} + +common_chat_prompt_preset common_chat_get_asr_prompt(const common_chat_templates * chat_templates, const std::string & language) { common_chat_prompt_preset asr_preset; asr_preset.system = ""; asr_preset.user = "Transcribe audio to text"; - if (chat_templates && chat_templates->template_default && is_lfm2_template(chat_templates->template_default->source())) { - asr_preset.system = "Perform ASR."; - asr_preset.user = ""; + if (chat_templates && chat_templates->template_default) { + const std::string src = chat_templates->template_default->source(); + if (is_lfm2_template(src)) { + asr_preset.system = "Perform ASR."; + asr_preset.user = ""; + } else if (is_lfm3_template(src)) { + asr_preset.system = lfm3_asr_system_prompt(language); + asr_preset.user = ""; + asr_preset.has_language = true; + } } return asr_preset; } +std::string common_chat_get_tts_prompt(const common_chat_templates * chat_templates, const std::string & text, + const std::string & language, const std::string & voice) { + if (!chat_templates || !chat_templates->template_tts) { + return ""; + } + return common_chat_template_render(*chat_templates->template_tts, { + {"messages", json::array({{{"role", "user"}, {"content", text}}})}, + {"language", language}, + {"voice", voice}, + }); +} + std::string common_chat_templates_source(const struct common_chat_templates * tmpls, const std::string & variant) { if (!variant.empty()) { if (variant == "tool_use") { @@ -823,6 +978,16 @@ common_chat_templates_ptr common_chat_templates_init(const struct llama_model * LOG_ERR("%s: failed to parse tool use chat template (ignoring it): %s\n", __func__, e.what()); } } + // task templates of the model, kept with a chat template override + if (model) { + if (const char * src = llama_model_chat_template(model, "tts")) { + try { + tmpls->template_tts = std::make_unique<common_chat_template>(src, token_bos, token_eos); + } catch (const std::exception & e) { + LOG_ERR("%s: failed to parse the tts chat template (ignoring it): %s\n", __func__, e.what()); + } + } + } return tmpls; } @@ -1104,12 +1269,25 @@ static common_chat_params_init_fn common_chat_template_detect_params_init(const return common_chat_params_init_llm_jp_harmony; } + // Harmony XML tool calls, checked before the GPT-OSS JSON calls + if (src.find("<|channel|>") != std::string::npos && src.find("<|constrain|>xml") != std::string::npos && + src.find("rfl:parameter") != std::string::npos) { + LOG_DBG("Using specialized template: Harmony XML\n"); + return common_chat_params_init_harmony_xml; + } + // GPT-OSS - has unique channel-based structure that needs dedicated handler if (src.find("<|channel|>") != std::string::npos) { LOG_DBG("Using specialized template: GPT-OSS\n"); return common_chat_params_init_gpt_oss; } + // Muse Spark shares the Muse recipient protocol and adds a commentary recipient. + if (src.find("to=commentary") != std::string::npos && src.find("<|eom|>") != std::string::npos) { + LOG_DBG("Using specialized template: Muse Spark\n"); + return common_chat_params_init_muse_spark; + } + // Muse Glimmer format using " to=<recipient>" recipients and <|eom|>/<|eot|> message terminators. if (src.find("<atem:function_calls>") != std::string::npos && src.find("<|eom|>") != std::string::npos) { LOG_DBG("Using specialized template: Muse Glimmer\n"); @@ -1195,11 +1373,13 @@ static common_chat_params_init_fn common_chat_template_detect_params_init(const // DeepSeek V3.2/V4 format detection: template defines dsml_token and uses it for tool calls. // The template source contains the token as a variable assignment, not as a literal in markup. // V3.2 names the tool call block "function_calls", V4 names it "tool_calls". - if (src.find("dsml_token") != std::string::npos && - src.find("DSML") != std::string::npos && - (src.find("function_calls") != std::string::npos || - src.find("tool_calls") != std::string::npos)) { - LOG_DBG("Using specialized template: DeepSeek V3.2/V4\n"); + // V4.1 tag names have a leading space and its template does not name the dsml_token variable. + if ((src.find("dsml_token") != std::string::npos && + src.find("DSML") != std::string::npos && + (src.find("function_calls") != std::string::npos || + src.find("tool_calls") != std::string::npos)) || + src.find("｜DSML｜ calls>") != std::string::npos) { + LOG_DBG("Using specialized template: DeepSeek V3.2/V4/V4.1\n"); return common_chat_params_init_deepseek_v3_2; } @@ -1300,7 +1480,9 @@ static common_chat_params common_chat_templates_apply_jinja(const struct common_ workaround::trim_all_content(trimmed_messages); messages_to_render = &trimmed_messages; } - params.messages = render_message_to_json(*messages_to_render, tmpl.original_caps()); + params.messages = src.find("｜DSML｜ calls>") != std::string::npos ? + render_message_to_json_deepseek_v4_1(*messages_to_render, tmpl.original_caps()) : + render_message_to_json(*messages_to_render, tmpl.original_caps()); params.tool_choice = inputs.tool_choice; params.reasoning_format = inputs.reasoning_format; params.enable_thinking = inputs.enable_thinking; @@ -1621,6 +1803,9 @@ common_chat_msg common_chat_peg_parse(const common_peg_arena & src_pars //LOG_DBG("Parsing PEG input with format %s: %s\n", common_chat_format_name(params.format), effective_input.text.c_str()); common_peg_parse_flags flags = COMMON_PEG_PARSE_FLAG_LENIENT; + if (!is_partial) { + flags |= COMMON_PEG_PARSE_FLAG_COMPLETE; + } if (params.debug) { flags |= COMMON_PEG_PARSE_FLAG_DEBUG; } @@ -1758,12 +1943,13 @@ const common_chat_msg & common_chat_session::finish(const common_chat_input & ch return result; } -std::map<std::string, bool> common_chat_templates_get_caps(const common_chat_templates * chat_templates) { +common_json common_chat_templates_get_caps(const common_chat_templates * chat_templates) { GGML_ASSERT(chat_templates != nullptr); GGML_ASSERT(chat_templates->template_default != nullptr); - if (chat_templates->template_tool_use != nullptr) { - // take the more expressive template when available - return chat_templates->template_tool_use->caps.to_map(); - } - return chat_templates->template_default->caps.to_map(); + // take the more expressive template when available + const auto & caps = chat_templates->template_tool_use != nullptr ? chat_templates->template_tool_use->caps + : chat_templates->template_default->caps; + common_json result = caps.to_map(); + result["reasoning_effort_levels"] = caps.reasoning_effort_levels; + return result; } diff --git a/common/chat.h b/common/chat.h index dcff94919819..ebfc80f51258 100644 --- a/common/chat.h +++ b/common/chat.h @@ -45,6 +45,7 @@ struct common_chat_tool_call { struct common_chat_msg_content_part { std::string type; std::string text; + std::string name; // tool_reference: name of a tool from the request tools // TODO @ngxson : no known chat templates support reasoning_content in content parts yet // this can be useful for models with interleaved thinking (like Kimi-K2) @@ -52,7 +53,7 @@ struct common_chat_msg_content_part { // std::string reasoning_content; bool operator==(const common_chat_msg_content_part & other) const { - return type == other.type && text == other.text; + return type == other.type && text == other.text && name == other.name; } }; @@ -94,6 +95,8 @@ struct common_chat_msg { std::string reasoning_content; std::string tool_name; std::string tool_call_id; + // non-OpenAI message keys as a JSON object string, only for templates that read them (DeepSeek V4.1) + std::string extra_json; common_json to_json_oaicompat(bool concat_typed_text = false) const; @@ -224,6 +227,9 @@ struct common_chat_tool { std::string name; std::string description; std::string parameters; + + // withheld from the system prompt, a tool_reference reveals it later in the conversation + bool defer_loading = false; }; enum common_chat_tool_choice { @@ -466,7 +472,7 @@ common_json common_chat_tools_to_json_oaicompat(const std::vector<common_chat_to common_json common_chat_tool_parameters(const common_json & function); // get template caps, useful for reporting to server /props endpoint -std::map<std::string, bool> common_chat_templates_get_caps(const common_chat_templates * chat_templates); +common_json common_chat_templates_get_caps(const common_chat_templates * chat_templates); common_chat_prompt common_chat_template_direct_apply( const common_chat_template & tmpl, @@ -485,6 +491,12 @@ std::optional<common_chat_params> common_chat_try_specialized_template( struct common_chat_prompt_preset { std::string system; std::string user; + bool has_language = false; // the preset already names the requested language }; -common_chat_prompt_preset common_chat_get_asr_prompt(const common_chat_templates * chat_templates); +common_chat_prompt_preset common_chat_get_asr_prompt(const common_chat_templates * chat_templates, const std::string & language = ""); + +// prompt of the model's "tts" chat template for the text to speak, empty if the model has none +// language and voice are optional, the template defines their defaults +std::string common_chat_get_tts_prompt(const common_chat_templates * chat_templates, const std::string & text, + const std::string & language = "", const std::string & voice = ""); diff --git a/common/common.cpp b/common/common.cpp index c5db228329f5..04e348805ba3 100644 --- a/common/common.cpp +++ b/common/common.cpp @@ -26,6 +26,7 @@ #include <fstream> #include <iostream> #include <iterator> +#include <random> #include <regex> #include <sstream> #include <string> @@ -218,6 +219,23 @@ int32_t common_cpu_get_num_math() { } } } +#elif defined(__riscv) && defined(__linux__) + std::ifstream cpuinfo("/proc/cpuinfo"); + std::string line; + int32_t n_a100 = 0; + while (std::getline(cpuinfo, line)) { + std::istringstream fields(line); + std::string key; + std::string separator; + uint64_t marchid; + if (fields >> key >> separator >> std::hex >> marchid && + key == "marchid" && separator == ":" && marchid == UINT64_C(0x8000000041000002)) { + ++n_a100; + } + } + if (n_a100 > 0) { + return n_a100; + } #elif defined(__powerpc64__) || defined(__powerpc__) int32_t smt_factor = 1; int phy_cpus = common_cpu_get_num_physical_cores(); @@ -741,50 +759,56 @@ static inline bool glob_class_match(const char c, const char * pattern, const ch } // simple glob: * matches non-/ chars, ** matches anything including /, [] matches character class -static inline bool glob_match(const char * pattern, const char * str) { - if (*pattern == '\0') { - return *str == '\0'; - } - if (pattern[0] == '*' && pattern[1] == '*') { - const char * p = pattern + 2; - if (glob_match(p, str)) return true; - if (*str != '\0') return glob_match(pattern, str + 1); +// only wildcards recurse, too many wildcards: no match +static bool glob_match(const char * pattern, const char * str, int depth = 0) { + if (depth >= COMMON_RECURSIVE_LIMIT) { return false; } - if (*pattern == '*') { - const char * p = pattern + 1; - for (; *str != '\0' && *str != '/'; str++) { - if (glob_match(p, str)) return true; - } - return glob_match(p, str); - } - if (*pattern == '?' && *str != '\0' && *str != '/') { - return glob_match(pattern + 1, str + 1); - } - if (*pattern == '[') { - const char * class_end = pattern + 1; - // If first character after '[' is ']' or '-', treat it as literal - if (*class_end == ']' || *class_end == '-') { - class_end++; - } - while (*class_end != '\0' && *class_end != ']') { - class_end++; + while (*pattern != '\0') { + if (pattern[0] == '*' && pattern[1] == '*') { + const char * p = pattern + 2; + for (;; str++) { + if (glob_match(p, str, depth + 1)) return true; + if (*str == '\0') return false; + } } - if (*class_end == ']') { - if (*str == '\0') return false; - bool matched = glob_class_match(*str, pattern + 1, class_end); - return matched && glob_match(class_end + 1, str + 1); - } else { - if (*str == '[') { - return glob_match(pattern + 1, str + 1); + if (*pattern == '*') { + const char * p = pattern + 1; + for (; *str != '\0' && *str != '/'; str++) { + if (glob_match(p, str, depth + 1)) return true; } - return false; + return glob_match(p, str, depth + 1); + } + if (*pattern == '?' && *str != '\0' && *str != '/') { + pattern++; + str++; + continue; + } + if (*pattern == '[') { + const char * class_end = pattern + 1; + // If first character after '[' is ']' or '-', treat it as literal + if (*class_end == ']' || *class_end == '-') { + class_end++; + } + while (*class_end != '\0' && *class_end != ']') { + class_end++; + } + if (*class_end == ']') { + if (*str == '\0' || !glob_class_match(*str, pattern + 1, class_end)) return false; + pattern = class_end + 1; + str++; + continue; + } + if (*str != '[') return false; + pattern++; + str++; + continue; } + if (*pattern != *str) return false; + pattern++; + str++; } - if (*pattern == *str) { - return glob_match(pattern + 1, str + 1); - } - return false; + return *str == '\0'; } bool glob_match(const std::string & pattern, const std::string & str) { @@ -910,16 +934,14 @@ std::string wstring_to_utf8(const std::wstring & str) { } #endif -// returns the path as a UTF-8 string, preserving its separators -std::string fs_path_to_utf8(const std::filesystem::path & path) { - const auto value = path.u8string(); - return std::string(value.begin(), value.end()); -} - void fs_write_atomic(const std::filesystem::path & path, const std::string & data) { + // a random suffix gives every writer its own temporary file, across processes and containers + std::random_device rd; + const uint64_t id = ((uint64_t) rd() << 32) | rd(); + std::error_code ec; std::filesystem::path path_tmp = path; - path_tmp += ".tmp"; + path_tmp += "." + std::to_string(id) + ".tmp"; if (path.has_parent_path()) { std::filesystem::create_directories(path.parent_path(), ec); @@ -935,7 +957,7 @@ void fs_write_atomic(const std::filesystem::path & path, const std::string & dat if (file.fail() || ec) { std::filesystem::remove(path_tmp, ec); - throw std::runtime_error("failed to write file: " + fs_path_to_utf8(path)); + throw std::runtime_error("failed to write file: " + path.string()); } } @@ -1029,7 +1051,7 @@ std::filesystem::path fs_get_cache_file(const std::string & filename) { std::error_code ec; common_create_directories(cache_directory, ec); if (ec) { - throw std::runtime_error("failed to create cache directory: " + fs_path_to_utf8(cache_directory)); + throw std::runtime_error("failed to create cache directory: " + cache_directory.string()); } return cache_directory / std::filesystem::u8path(filename); } @@ -1174,6 +1196,11 @@ static const std::map<common_decision_type, std::string> COMMON_DECISION_TYPE_NA { COMMON_DECISION_TYPE_VLLM_D3, "vllm-d3" }, { COMMON_DECISION_TYPE_LFM2_D1, "lfm2-d1" }, { COMMON_DECISION_TYPE_LFM2_D1_OMNI, "lfm2-d1-omni" }, + { COMMON_DECISION_TYPE_GRANITE_SWITCH, "granite-switch"}, + { COMMON_DECISION_TYPE_H2O_LIGHTNING, "h2o-lightning" }, + { COMMON_DECISION_TYPE_MINICPM_OCR_JEV, "openbmb-minicpm-ocr-jev" }, + { COMMON_DECISION_TYPE_LFM3_D1, "lfm3-d1" }, + { COMMON_DECISION_TYPE_LFM3_D1_OMNI, "lfm3-d1-omni" }, // for future models, ALWAYS add org name prefix to avoid name collisions, e.g. "orgname-modelname" }; @@ -1233,47 +1260,56 @@ common_gguf_info common_get_gguf_info(const std::string & fname) { info.n_ctx_train = gguf_get_val_u32(gguf_ctx.get(), ctx_id); } + // same key as llama_model_chat_template(model, nullptr) + info.has_chat_tmpl = gguf_find_key(gguf_ctx.get(), "tokenizer.chat_template") >= 0; + return info; } -common_init_result::common_init_result(common_params & params, bool model_only) : - pimpl(new impl{}) { - auto mparams = common_model_params_to_llama(params); - auto cparams = common_context_params_to_llama(params); +void common_fit_apply(common_params & params, llama_model_params & mparams, llama_context_params & cparams) { + if (!params.fit_params) { + return; + } - if (params.fit_params) { - COM_TRC("%s", "fitting params to device memory ...\n"); - COM_TRC("%s", "(for bugs during this step try to reproduce them with -fit off, or provide --verbose logs if the bug only occurs with -fit on)\n"); + COM_TRC("%s", "fitting params to device memory ...\n"); + COM_TRC("%s", "(for bugs during this step try to reproduce them with -fit off, or provide --verbose logs if the bug only occurs with -fit on)\n"); - // the draft context is created from the same base params and follows the main context, fit both together - const bool has_draft = params.speculative.has_dft(); - const bool spec_mtp = std::find(params.speculative.types.begin(), params.speculative.types.end(), - COMMON_SPECULATIVE_TYPE_DRAFT_MTP) != params.speculative.types.end(); + // the draft context is created from the same base params and follows the main context, fit both together + const bool has_draft = params.speculative.has_dft(); + const bool spec_mtp = std::find(params.speculative.types.begin(), params.speculative.types.end(), + COMMON_SPECULATIVE_TYPE_DRAFT_MTP) != params.speculative.types.end(); - common_params params_dft = common_base_params_to_speculative(params); + common_params params_dft = common_base_params_to_speculative(params); - auto mparams_dft = common_model_params_to_llama(params_dft); - auto cparams_dft = common_context_params_to_llama(params_dft); - if (spec_mtp) { - cparams_dft.ctx_type = LLAMA_CONTEXT_TYPE_MTP; - } - cparams_dft.n_rs_seq = 0; + auto mparams_dft = common_model_params_to_llama(params_dft); + auto cparams_dft = common_context_params_to_llama(params_dft); + if (spec_mtp) { + cparams_dft.ctx_type = LLAMA_CONTEXT_TYPE_MTP; + } + cparams_dft.n_rs_seq = 0; - const common_fit_extra_model extra = { - /*.path_model =*/ params_dft.model.path.c_str(), - /*.mparams =*/ &mparams_dft, - /*.cparams =*/ &cparams_dft, - /*.shares_model =*/ !has_draft, // an MTP context runs on the weights of the main model - }; + const common_fit_extra_model extra = { + /*.path_model =*/ params_dft.model.path.c_str(), + /*.mparams =*/ &mparams_dft, + /*.cparams =*/ &cparams_dft, + /*.shares_model =*/ !has_draft, // an MTP context runs on the weights of the main model + }; - common_fit_params(params.model.path.c_str(), &mparams, &cparams, - params.tensor_split, - params.tensor_buft_overrides.data(), - params.fit_params_target.data(), - params.fit_params_min_ctx, - has_draft || spec_mtp ? &extra : nullptr, - params.verbosity >= LOG_LEVEL_DEBUG ? GGML_LOG_LEVEL_DEBUG : GGML_LOG_LEVEL_ERROR); - } + common_fit_params(params.model.path.c_str(), &mparams, &cparams, + params.tensor_split, + params.tensor_buft_overrides.data(), + params.fit_params_target.data(), + params.fit_params_min_ctx, + has_draft || spec_mtp ? &extra : nullptr, + params.verbosity >= LOG_LEVEL_DEBUG ? GGML_LOG_LEVEL_DEBUG : GGML_LOG_LEVEL_ERROR); +} + +common_init_result::common_init_result(common_params & params, bool model_only) : + pimpl(new impl{}) { + auto mparams = common_model_params_to_llama(params); + auto cparams = common_context_params_to_llama(params); + + common_fit_apply(params, mparams, cparams); llama_model * model = llama_model_load_from_file(params.model.path.c_str(), mparams); if (model == NULL) { @@ -1291,13 +1327,17 @@ common_init_result::common_init_result(common_params & params, bool model_only) // these decision models return a score for each token via the embeddings output // TODO: maybe improve this in the future const auto decision_type = common_get_decision_type(model); + // minicpm-ocr-jev reads its class scores from the pooled output, the pooling type is the one of the GGUF if (decision_type == COMMON_DECISION_TYPE_LAYA || decision_type == COMMON_DECISION_TYPE_KEV || decision_type == COMMON_DECISION_TYPE_CLEF || - decision_type == COMMON_DECISION_TYPE_LFM2_D1_OMNI || decision_type == COMMON_DECISION_TYPE_VLLM_DECISION2) { + decision_type == COMMON_DECISION_TYPE_LFM2_D1_OMNI || decision_type == COMMON_DECISION_TYPE_VLLM_DECISION2 || + decision_type == COMMON_DECISION_TYPE_MINICPM_OCR_JEV) { + const auto pooling_type = decision_type == COMMON_DECISION_TYPE_MINICPM_OCR_JEV ? LLAMA_POOLING_TYPE_UNSPECIFIED : LLAMA_POOLING_TYPE_NONE; + params.embedding = true; - params.pooling_type = LLAMA_POOLING_TYPE_NONE; + params.pooling_type = pooling_type; cparams.embeddings = true; - cparams.pooling_type = LLAMA_POOLING_TYPE_NONE; + cparams.pooling_type = pooling_type; cparams.n_outputs_max = cparams.n_batch; cparams.n_outputs_max_per_seq = 1; @@ -1444,7 +1484,7 @@ common_init_result_ptr common_init_from_params(common_params & params, bool mode if (params.control_vector_layer_start <= 0) params.control_vector_layer_start = 1; if (params.control_vector_layer_end <= 0) params.control_vector_layer_end = llama_model_n_layer(model); - const auto cvec = common_control_vector_load(params.control_vectors); + const auto cvec = common_control_vector_load(params.control_vectors, llama_model_n_layer(model)); if (cvec.n_embd == -1) { return res; } @@ -1966,7 +2006,7 @@ float common_embd_similarity_cos(const float * embd1, const float * embd2, int n // Control vector utils // -static common_control_vector_data common_control_vector_load_one(const common_control_vector_load_info & load_info) { +static common_control_vector_data common_control_vector_load_one(const common_control_vector_load_info & load_info, int32_t n_layer) { common_control_vector_data result = { -1, {} }; ggml_context * ctx = nullptr; @@ -2007,6 +2047,10 @@ static common_control_vector_data common_control_vector_load_one(const common_co COM_ERR("invalid (zero) direction tensor layer index in %s\n", load_info.fname.c_str()); result.n_embd = -1; break; + } else if (layer_idx > n_layer) { + COM_ERR("direction tensor layer index %d exceeds the model layer count %d in %s\n", layer_idx, n_layer, load_info.fname.c_str()); + result.n_embd = -1; + break; } struct ggml_tensor * tensor = ggml_get_tensor(ctx, name.c_str()); @@ -2030,10 +2074,10 @@ static common_control_vector_data common_control_vector_load_one(const common_co } // extend if necessary - do not store data for layer 0 (it's not used) - result.data.resize(std::max(result.data.size(), static_cast<size_t>(result.n_embd * layer_idx)), 0.0f); + result.data.resize(std::max(result.data.size(), (size_t) result.n_embd * layer_idx), 0.0f); const float * src = (const float *) tensor->data; - float * dst = result.data.data() + result.n_embd * (layer_idx - 1); // layer 1 at [0] + float * dst = result.data.data() + (size_t) result.n_embd * (layer_idx - 1); // layer 1 at [0] for (int j = 0; j < result.n_embd; j++) { dst[j] += src[j] * load_info.strength; // allows multiple directions for same layer in same file } @@ -2051,11 +2095,11 @@ static common_control_vector_data common_control_vector_load_one(const common_co return result; } -common_control_vector_data common_control_vector_load(const std::vector<common_control_vector_load_info> & load_infos) { +common_control_vector_data common_control_vector_load(const std::vector<common_control_vector_load_info> & load_infos, int32_t n_layer) { common_control_vector_data result = { -1, {} }; for (const auto & info : load_infos) { - auto cur = common_control_vector_load_one(info); + auto cur = common_control_vector_load_one(info, n_layer); if (cur.n_embd == -1) { result.n_embd = -1; diff --git a/common/common.h b/common/common.h index 2048d6a79585..d0e33fb7500d 100644 --- a/common/common.h +++ b/common/common.h @@ -31,6 +31,8 @@ #define DIRECTORY_SEPARATOR '/' #endif // _WIN32 +#define COMMON_RECURSIVE_LIMIT 128 + #define COM_DBG(fmt, ...) LOG_DBG("cmn %12.*s: " fmt, 12, __func__, __VA_ARGS__) #define COM_TRC(fmt, ...) LOG_TRC("cmn %12.*s: " fmt, 12, __func__, __VA_ARGS__) #define COM_INF(fmt, ...) LOG_INF("cmn %12.*s: " fmt, 12, __func__, __VA_ARGS__) @@ -640,6 +642,11 @@ struct common_params { int32_t kv_unified_per_slot = 0; // max context per parallel slot; 0 = unset int32_t checkpoint_min_step = 8192; // minimum spacing between context checkpoints int32_t cache_ram_mib = 8192; // -1 = no limit, 0 - disable, 1 = 1 MiB, etc. + bool cache_ram_explicit = false; // set by --cache-ram, decision models disable the cache otherwise + + // llama-connect params + bool server_connect = false; + std::string server_connect_code = ""; std::string public_path = ""; // NOLINT std::string api_prefix = ""; // NOLINT @@ -694,6 +701,7 @@ struct common_params { std::string models_dir = ""; // directory containing models for the router server std::string models_preset = ""; // directory containing model presets for the router server int models_max = 4; // maximum number of models to load simultaneously + int models_memory_margin = 0; // MiB of device memory to keep free when loading models (0 = no memory accounting) bool models_autoload = true; // automatically load models when requested via the router server std::string models_preset_hf = ""; // show a warning about remote presets on router loaded (if not empty) @@ -764,6 +772,7 @@ struct common_params { // TTS params std::string tts_lang = ""; + std::string tts_voice = ""; std::string tts_speaker_file = ""; bool is_gen_docs = false; // whether we are running inside llama-gen-docs @@ -901,9 +910,6 @@ std::wstring utf8_to_wstring(const std::string & str); std::string wstring_to_utf8(const std::wstring & str); #endif -// returns the path as a UTF-8 string, preserving its separators -std::string fs_path_to_utf8(const std::filesystem::path & path); - // // Environment utils // @@ -969,6 +975,11 @@ enum common_decision_type { COMMON_DECISION_TYPE_VLLM_D3, // same as pplx-decider, non-causal attention COMMON_DECISION_TYPE_LFM2_D1, // same as openjev, the labels depend on the question type COMMON_DECISION_TYPE_LFM2_D1_OMNI, // same as laya, other prompt layout + COMMON_DECISION_TYPE_GRANITE_SWITCH, // same as openjev, run by the decision aLoRA of granite switch + COMMON_DECISION_TYPE_H2O_LIGHTNING, // same as openjev, the labels are read after an answer prefill + COMMON_DECISION_TYPE_MINICPM_OCR_JEV, // one score per class, the pooled embeddings output of the last token + COMMON_DECISION_TYPE_LFM3_D1, // same as lfm2-d1, non-causal, label codes A..Z then AA, AB.. + COMMON_DECISION_TYPE_LFM3_D1_OMNI, // same as lfm3-d1 COMMON_DECISION_TYPE_UNKNOWN, // a decision model of a type that is not supported }; @@ -978,6 +989,7 @@ common_decision_type common_get_decision_type(const struct llama_model * model); struct common_gguf_info { common_decision_type decision_type = COMMON_DECISION_TYPE_UNKNOWN; // UNKNOWN if the file is missing, unreadable, or invalid uint32_t n_ctx_train = 0; // 0 if unknown + bool has_chat_tmpl = false; // has the default tokenizer.chat_template }; common_gguf_info common_get_gguf_info(const std::string & fname); @@ -1007,6 +1019,9 @@ common_init_result_ptr common_init_from_params(common_params & params, bool mode struct llama_model_params common_model_params_to_llama ( common_params & params); struct llama_context_params common_context_params_to_llama(const common_params & params); +// apply --fit to mparams and cparams, no-op if params.fit_params is false +void common_fit_apply(common_params & params, struct llama_model_params & mparams, struct llama_context_params & cparams); + // clear LoRA adapters from context, then apply new list of adapters void common_set_adapter_lora(struct llama_context * ctx, std::vector<common_adapter_lora_info> & lora); @@ -1219,8 +1234,9 @@ struct common_control_vector_load_info { }; // Load control vectors, scale each by strength, and add them together. +// Direction layer indices must be in [1, n_layer]. // On error, returns {-1, empty} -common_control_vector_data common_control_vector_load(const std::vector<common_control_vector_load_info> & load_infos); +common_control_vector_data common_control_vector_load(const std::vector<common_control_vector_load_info> & load_infos, int32_t n_layer); // // Split utils diff --git a/common/download.cpp b/common/download.cpp index ae0f7ffede42..08531a2d09d4 100644 --- a/common/download.cpp +++ b/common/download.cpp @@ -4,6 +4,7 @@ #include "common.h" #include "log.h" #include "download.h" +#include "file-lock.h" #include "hf-cache.h" #include "json.h" @@ -39,6 +40,9 @@ // downloader // +// the suffix of the file a download writes until it completes +static const std::string PARTIAL_SUFFIX = ".downloadInProgress"; + static void write_etag(const std::string & path, const std::string & etag) { const std::string etag_path = path + ".etag"; fs_write_atomic(std::filesystem::u8path(etag_path), etag); @@ -74,6 +78,18 @@ std::pair<std::string, std::string> common_download_split_repo_tag(const std::st return {hf_repo, tag}; } +// file name from url, without the query string +static std::string url_get_filename(const std::string & url) { + std::string filename = url; + if (auto pos = filename.rfind('/'); pos != std::string::npos) { + filename = filename.substr(pos + 1); + } + if (auto pos = filename.find('?'); pos != std::string::npos) { + filename = filename.substr(0, pos); + } + return filename; +} + class ProgressBar : public common_download_callback { static inline std::mutex mutex; static inline std::map<const ProgressBar *, int> lines; @@ -97,14 +113,8 @@ class ProgressBar : public common_download_callback { ProgressBar() = default; void on_start(const common_download_progress & p) override { - filename = p.url; + filename = url_get_filename(p.url); - if (auto pos = filename.rfind('/'); pos != std::string::npos) { - filename = filename.substr(pos + 1); - } - if (auto pos = filename.find('?'); pos != std::string::npos) { - filename = filename.substr(0, pos); - } for (size_t i = 0; i < filename.size(); ++i) { if ((filename[i] & 0xC0) != 0x80) { if (len++ == 39) { @@ -186,6 +196,13 @@ static bool common_pull_file(httplib::Client & cli, [&](const httplib::Response &response) { if (p.downloaded > 0 && response.status != 206) { LOG_WRN("%s: server did not respond with 206 Partial Content for a resume request. Status: %d\n", func, response.status); + if (response.status == 416 || response.status == 200) { + // the kept partial cannot be resumed: 416 for a complete or stale one, + // 200 from a server that ignores the range; drop it, so the next + // attempt starts over instead of wedging on the same answer + ofs.close(); + remove(path_tmp.c_str()); + } return false; } if (p.downloaded == 0 && response.status != 200) { @@ -214,7 +231,7 @@ static bool common_pull_file(httplib::Client & cli, if (progress_step >= p.total / 1000 || p.downloaded == p.total) { if (callback) { callback->on_update(p); - if (callback->is_cancelled()) { + if (callback->is_cancelled() && (p.total == 0 || p.downloaded != p.total)) { return false; } } @@ -247,15 +264,62 @@ static bool common_pull_file(httplib::Client & cli, static int common_download_file_single_online(const std::string & url, const std::string & path, const common_download_opts & opts, - bool skip_etag) { + bool skip_etag, + const std::string & lock_path, + const std::string & alt_path) { static const int max_attempts = 3; static const int retry_delay_seconds = 2; - const bool file_exists = std::filesystem::exists(std::filesystem::u8path(path)); + const std::string path_temporary = path + PARTIAL_SUFFIX; + const std::string path_lock = lock_path.empty() ? path + ".lock" : lock_path; + + common_download_progress p; + p.url = url; + + if (opts.callback) { + opts.callback->on_start(p); + } + + // the completion callback may itself take the same lock (the HF cache + // finalizes blobs under it), so every exit goes through finish() + common_file_lock lock(path_lock); + auto finish = [&](int status) { + lock.close(); + if (opts.callback) { + opts.callback->on_done(p, is_http_status_ok(status)); + } + return status; + }; + + // alt_path is the HF snapshot: the blob may have been moved there when symlinks are unavailable + auto cache_hit = [&] { + return std::filesystem::exists(std::filesystem::u8path(path)) || + (!alt_path.empty() && std::filesystem::exists(std::filesystem::u8path(alt_path))); + }; + + if (skip_etag && cache_hit()) { + LOG_DBG("%s: using cached file: %s\n", __func__, path.c_str()); + return finish(304); // 304 Not Modified - fake cached response + } + + // take the lock before touching the cache, so two processes cannot race on the same file + bool waited = false; + if (!lock.acquire([&] { + if (!waited) { + LOG_INF("%s: file '%s' is being downloaded by another process, waiting...\n", __func__, url_get_filename(url).c_str()); + waited = true; + } + return !(opts.callback && opts.callback->is_cancelled()); + })) { + return finish(-1); + } + + // under the lock: another process may have finished while we waited + bool file_exists = cache_hit(); if (file_exists && skip_etag) { LOG_DBG("%s: using cached file: %s\n", __func__, path.c_str()); - return 304; // 304 Not Modified - fake cached response + return finish(304); // 304 Not Modified - fake cached response } auto [cli, parts] = common_http_client(url); @@ -284,9 +348,9 @@ static int common_download_file_single_online(const std::string & url, LOG_TRC("%s: HEAD failed, status: %d\n", __func__, head ? head->status : -1); if (file_exists) { LOG_TRC("%s: using cached file (HEAD failed): %s\n", __func__, path.c_str()); - return 304; // 304 Not Modified - fake cached response + return finish(304); // 304 Not Modified - fake cached response } - return head ? head->status : -1; + return finish(head ? head->status : -1); } std::string etag; @@ -294,8 +358,6 @@ static int common_download_file_single_online(const std::string & url, etag = head->get_header_value("ETag"); } - common_download_progress p; - p.url = url; if (head->has_header("Content-Length")) { try { p.total = std::stoull(head->get_header_value("Content-Length")); @@ -312,16 +374,16 @@ static int common_download_file_single_online(const std::string & url, if (file_exists) { if (etag.empty()) { LOG_DBG("%s: using cached file (no server etag): %s\n", __func__, path.c_str()); - return 304; // 304 Not Modified - fake cached response + return finish(304); // 304 Not Modified - fake cached response } if (!last_etag.empty() && last_etag == etag) { LOG_DBG("%s: using cached file (same etag): %s\n", __func__, path.c_str()); - return 304; // 304 Not Modified - fake cached response + return finish(304); // 304 Not Modified - fake cached response } // pass this point, the file exists but is different from the server version, so we need to redownload it if (remove(path.c_str()) != 0) { LOG_ERR("%s: unable to delete file: %s\n", __func__, path.c_str()); - return -1; + return finish(-1); } } @@ -331,11 +393,24 @@ static int common_download_file_single_online(const std::string & url, } bool success = false; - const std::string path_temporary = path + ".downloadInProgress"; int delay = retry_delay_seconds; + if (!skip_etag && !etag.empty()) { + if (std::filesystem::exists(path_temporary) && read_etag(path_temporary) != etag) { + LOG_WRN("%s: partial file does not match the server etag, discarding it: %s\n", __func__, path_temporary.c_str()); + if (remove(path_temporary.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path_temporary.c_str()); + return finish(-1); + } + } + write_etag(path_temporary, etag); + } + if (opts.callback) { - opts.callback->on_start(p); + // report the resume offset, so a resumed file does not start at 0 + p.downloaded = supports_ranges && std::filesystem::exists(path_temporary) ? + std::filesystem::file_size(path_temporary) : 0; + opts.callback->on_update(p); } for (int i = 0; i < max_attempts; ++i) { @@ -372,27 +447,19 @@ static int common_download_file_single_online(const std::string & url, } if (!etag.empty() && !skip_etag) { write_etag(path, etag); + remove((path_temporary + ".etag").c_str()); } success = true; break; } } - if (opts.callback) { - opts.callback->on_done(p, success); - } - if (opts.callback && opts.callback->is_cancelled() && - std::filesystem::exists(path_temporary)) { - if (remove(path_temporary.c_str()) != 0) { - LOG_ERR("%s: unable to delete temporary file: %s\n", __func__, path_temporary.c_str()); - } - } + // a stopped download keeps path_temporary, so the next attempt resumes from it if (!success) { LOG_ERR("%s: download failed after %d attempts\n", __func__, max_attempts); - return -1; // max attempts reached } - return head->status; + return finish(success ? head->status : -1); } std::pair<long, std::vector<char>> common_remote_get_content(const std::string & url, @@ -432,14 +499,16 @@ std::pair<long, std::vector<char>> common_remote_get_content(const std::string int common_download_file_single(const std::string & url, const std::string & path, const common_download_opts & opts, - bool skip_etag) { + bool skip_etag, + const std::string & lock_path, + const std::string & alt_path) { if (!opts.offline) { ProgressBar tty_cb; common_download_opts online_opts = opts; if (!online_opts.callback) { online_opts.callback = &tty_cb; } - return common_download_file_single_online(url, path, online_opts, skip_etag); + return common_download_file_single_online(url, path, online_opts, skip_etag, lock_path, alt_path); } if (!std::filesystem::exists(std::filesystem::u8path(path))) { @@ -594,33 +663,65 @@ static hf_cache::hf_file find_best_sibling(const hf_cache::hf_files & files, return best; } -static hf_cache::hf_file find_best_mmproj(const hf_cache::hf_files & files, - const std::string & model) { - return find_best_sibling(files, model, "mmproj"); +static const std::vector<common_download_sidecar> sidecars = { + { "mmproj", "mmproj", false, &common_download_opts::download_mmproj, &common_download_hf_plan::mmproj }, + { "mtp", "mtp-", true, &common_download_opts::download_mtp, &common_download_hf_plan::mtp }, + { "dflash", "dflash-", true, &common_download_opts::download_dflash, &common_download_hf_plan::dflash }, + { "eagle3", "eagle3-", true, &common_download_opts::download_eagle3, &common_download_hf_plan::eagle3 }, + { "dspark", "dspark-", true, &common_download_opts::download_dspark, &common_download_hf_plan::dspark }, +}; + +const std::vector<common_download_sidecar> & common_download_sidecars() { + return sidecars; } -static hf_cache::hf_file find_best_mtp(const hf_cache::hf_files & files, - const std::string & model, - const std::string & tag = "") { - return find_best_sibling(files, model, "mtp-", tag); +bool common_download_opts_add_sidecar(common_download_opts & opts, const std::string & kind) { + for (const auto & s : sidecars) { + if (kind == s.name) { + opts.*s.opt = true; + return true; + } + } + return false; } -static hf_cache::hf_file find_best_eagle3(const hf_cache::hf_files & files, - const std::string & model, - const std::string & tag = "") { - return find_best_sibling(files, model, "eagle3-", tag); +std::vector<std::string> common_download_plan_sidecars(const common_download_hf_plan & plan) { + std::vector<std::string> out; + for (const auto & s : sidecars) { + if (!(plan.*s.file).path.empty()) { + out.emplace_back(s.name); + } + } + return out; } -static hf_cache::hf_file find_best_dflash(const hf_cache::hf_files & files, - const std::string & model, - const std::string & tag = "") { - return find_best_sibling(files, model, "dflash-", tag); +std::vector<common_download_partial> common_download_plan_partials(const common_download_hf_plan & plan) { + std::vector<common_download_partial> out; + + // a file in the cache resolves to its snapshot entry, a file still to download to its blob + auto add = [&](const std::string & kind, const hf_cache::hf_file & f) { + if (!f.local_path.empty() && f.local_path != f.final_path) { + out.push_back({ kind, f.local_path + PARTIAL_SUFFIX }); + } + }; + + for (const auto & f : plan.model_files) { + add("", f); + } + for (const auto & s : sidecars) { + add(s.name, plan.*s.file); + } + return out; } -static hf_cache::hf_file find_best_dspark(const hf_cache::hf_files & files, - const std::string & model, - const std::string & tag = "") { - return find_best_sibling(files, model, "dspark-", tag); +// true when `name` carries the keyword of a sidecar kind +static bool name_is_sidecar(const std::string & name) { + for (const auto & s : sidecars) { + if (name.find(s.keyword) != std::string::npos) { + return true; + } + } + return false; } static bool gguf_filename_is_model(const std::string & filepath) { @@ -633,12 +734,7 @@ static bool gguf_filename_is_model(const std::string & filepath) { filename = filename.substr(pos + 1); } - return filename.find("mmproj") == std::string::npos && - filename.find("imatrix") == std::string::npos && - filename.find("mtp-") == std::string::npos && - filename.find("eagle3-") == std::string::npos && - filename.find("dflash-") == std::string::npos && - filename.find("dspark-") == std::string::npos; + return filename.find("imatrix") == std::string::npos && !name_is_sidecar(filename); } static hf_cache::hf_file find_best_model(const hf_cache::hf_files & files, @@ -730,8 +826,11 @@ common_download_hf_plan common_download_get_hf_plan(const common_params_model & } } else { primary = find_best_model(all, tag); - // a requested sidecar can resolve on its own, without a full model of the same tag - if (primary.path.empty() && !opts.download_mtp && !opts.download_dflash && !opts.download_eagle3 && !opts.download_dspark) { + // a requested draft can resolve on its own, without a full model of the same tag + const bool want_draft = std::any_of(sidecars.begin(), sidecars.end(), [&](const common_download_sidecar & s) { + return s.draft && opts.*s.opt; + }); + if (primary.path.empty() && !want_draft) { LOG_ERR("%s: no GGUF files found in repository %s\n", __func__, repo.c_str()); list_available_gguf_files(all); return plan; @@ -743,24 +842,22 @@ common_download_hf_plan common_download_get_hf_plan(const common_params_model & plan.model_files = get_split_files(all, primary); } - if (opts.download_mmproj && !primary.path.empty()) { - plan.mmproj = find_best_mmproj(all, primary.path); - } - if (opts.download_mtp) { - plan.mtp = find_best_mtp(all, primary.path, tag); - } - if (opts.download_dflash) { - plan.dflash = find_best_dflash(all, primary.path, tag); - } - if (opts.download_eagle3) { - plan.eagle3 = find_best_eagle3(all, primary.path, tag); - } - if (opts.download_dspark) { - plan.dspark = find_best_dspark(all, primary.path, tag); + // a draft resolves at the tag, the mmproj pairs with the model + for (const auto & s : sidecars) { + if (!(opts.*s.opt)) { + continue; + } + if (s.draft) { + plan.*s.file = find_best_sibling(all, primary.path, s.keyword, tag); + } else if (!primary.path.empty()) { + plan.*s.file = find_best_sibling(all, primary.path, s.keyword); + } } - if (primary.path.empty() && - plan.mtp.local_path.empty() && plan.dflash.local_path.empty() && plan.eagle3.local_path.empty() && plan.dspark.local_path.empty()) { + const bool has_draft = std::any_of(sidecars.begin(), sidecars.end(), [&](const common_download_sidecar & s) { + return s.draft && !(plan.*s.file).local_path.empty(); + }); + if (primary.path.empty() && !has_draft) { LOG_ERR("%s: no GGUF files found in repository %s\n", __func__, repo.c_str()); list_available_gguf_files(all); } @@ -773,7 +870,7 @@ void common_download_run_tasks(const std::vector<common_download_task> & tasks) for (const auto & task : tasks) { futures.push_back(std::async(std::launch::async, [&task]() { - return common_download_file_single(task.url, task.local_path, task.opts, task.is_hf); + return common_download_file_single(task.url, task.local_path, task.opts, task.is_hf, task.lock_path, task.alt_path); } )); } @@ -908,7 +1005,7 @@ std::string common_docker_resolve_model(const std::string & docker) { std::string model_filename = repo; std::replace(model_filename.begin(), model_filename.end(), '/', '_'); model_filename += "_" + tag + ".gguf"; - std::string local_path = fs_path_to_utf8(fs_get_cache_file(model_filename)); + std::string local_path = fs_get_cache_file(model_filename).string(); const std::string blob_url = url_prefix + "/blobs/" + gguf_digest; common_download_opts opts; @@ -926,6 +1023,11 @@ std::string common_docker_resolve_model(const std::string & docker) { } } +// a cached file that lists a model under its tag: the first split of a model, not a sidecar +static bool is_listed_model(const gguf_split_info & split) { + return split.index == 1 && !split.tag.empty() && !name_is_sidecar(split.prefix); +} + std::vector<common_cached_model_info> common_list_cached_models() { std::unordered_set<std::string> seen; std::vector<common_cached_model_info> result; @@ -934,12 +1036,7 @@ std::vector<common_cached_model_info> common_list_cached_models() { for (const auto & f : files) { auto split = get_gguf_split_info(f.path); - if (split.index != 1 || split.tag.empty() || - split.prefix.find("mmproj") != std::string::npos || - split.prefix.find("mtp-") != std::string::npos || - split.prefix.find("eagle3-") != std::string::npos || - split.prefix.find("dflash-") != std::string::npos || - split.prefix.find("dspark-") != std::string::npos) { + if (!is_listed_model(split)) { continue; } if (seen.insert(f.repo_id + ":" + split.tag).second) { @@ -970,6 +1067,44 @@ std::string common_download_resolve_path(const std::string & hf_repo_with_tag, c return find_best_model(files, tag).local_path; } +// the files -hf loads from the cache, the model with every sidecar, for each cached +// tag of `repo_id` other than `tag` +static std::unordered_set<std::string> files_in_use(const std::string & repo_id, const std::string & tag) { + common_download_opts opts; + opts.offline = true; + for (const auto & s : sidecars) { + opts.*s.opt = true; + } + + std::unordered_set<std::string> tags; + std::unordered_set<std::string> used; + + for (const auto & f : hf_cache::get_cached_files(repo_id)) { + auto split = get_gguf_split_info(f.path); + if (!is_listed_model(split) || split.tag == tag || !tags.insert(split.tag).second) { + continue; + } + + common_params_model model; + model.hf_repo = repo_id + ":" + split.tag; + + auto plan = common_download_get_hf_plan(model, opts); + + for (const auto & m : plan.model_files) { + used.insert(m.local_path); + } + for (const auto & s : sidecars) { + const auto & sf = plan.*s.file; + if (!sf.local_path.empty()) { + used.insert(sf.local_path); + } + } + } + return used; +} + +static bool remove_snapshot_entries(const std::string & repo_id, const std::vector<std::filesystem::path> & to_remove); + bool common_download_remove(const std::string & hf_repo_with_tag) { namespace fs = std::filesystem; @@ -989,11 +1124,13 @@ bool common_download_remove(const std::string & hf_repo_with_tag) { return false; } - // collect snapshot entries whose tag matches + // collect snapshot entries whose tag matches, but a file another tag loads stays + const auto used = files_in_use(repo_id, tag_upper); + std::vector<fs::path> to_remove; for (const auto & f : files) { auto split = get_gguf_split_info(f.path); - if (split.tag == tag_upper) { + if (split.tag == tag_upper && used.find(f.local_path) == used.end()) { to_remove.emplace_back(f.local_path); } } @@ -1002,6 +1139,13 @@ bool common_download_remove(const std::string & hf_repo_with_tag) { return false; } + return remove_snapshot_entries(repo_id, to_remove); +} + +// remove snapshot entries of `repo_id`, then the blobs no remaining entry references +static bool remove_snapshot_entries(const std::string & repo_id, const std::vector<std::filesystem::path> & to_remove) { + namespace fs = std::filesystem; + // resolve blob paths from symlinks before deleting snapshot entries std::vector<fs::path> blobs_to_check; for (const auto & p : to_remove) { @@ -1053,3 +1197,26 @@ bool common_download_remove(const std::string & hf_repo_with_tag) { return true; } + +bool common_download_remove_sidecars(const std::string & hf_repo_with_tag, const common_download_opts & opts) { + common_params_model model; + model.hf_repo = hf_repo_with_tag; + + common_download_opts cached = opts; + cached.offline = true; + + auto plan = common_download_get_hf_plan(model, cached); + + std::vector<std::filesystem::path> to_remove; + for (const auto & s : sidecars) { + const auto & f = plan.*s.file; + if (!f.local_path.empty()) { + to_remove.emplace_back(std::filesystem::u8path(f.local_path)); + } + } + if (to_remove.empty()) { + return false; + } + + return remove_snapshot_entries(common_download_split_repo_tag(hf_repo_with_tag).first, to_remove); +} diff --git a/common/download.h b/common/download.h index 8c30cfc3eadb..dd09d68eeff9 100644 --- a/common/download.h +++ b/common/download.h @@ -69,12 +69,15 @@ struct common_download_task { std::string local_path; std::function<void()> on_done; bool is_hf = false; + std::string lock_path; + std::string alt_path; // HF snapshot path, also treated as cached (the blob may be moved there) common_download_task() = default; common_download_task(hf_cache::hf_file f, const common_download_opts & opts, std::function<void()> on_done = nullptr) - : opts(opts), url(f.url), local_path(f.local_path), on_done(on_done), is_hf(true) {} + : opts(opts), url(f.url), local_path(f.local_path), on_done(on_done), is_hf(true), + lock_path(hf_cache::get_lock_path(f.repo_id, f.oid)), alt_path(f.final_path) {} }; void common_download_run_tasks(const std::vector<common_download_task> & tasks); @@ -92,10 +95,14 @@ std::string common_download_resolve_path(const std::string & hf_repo_with_tag, c // download single file from url to local path // returns status code or -1 on error // skip_etag: if true, don't read/write .etag files (for HF cache where filename is the hash) +// lock_path: lock file used to serialize downloads of the same file; when empty, "<path>.lock" is used +// alt_path: additional path treated as present in cache (see cache_hit in download.cpp) int common_download_file_single(const std::string & url, const std::string & path, const common_download_opts & opts = {}, - bool skip_etag = false); + bool skip_etag = false, + const std::string & lock_path = "", + const std::string & alt_path = ""); // resolve and download model from Docker registry // return local path to downloaded model file @@ -104,10 +111,17 @@ std::string common_docker_resolve_model(const std::string & docker); // Remove a cached model from disk // input format: "user/model" or "user/model:tag" // - if tag is omitted, removes the entire repo cache directory -// - if tag is present, removes only files matching that tag (and orphaned blobs) +// - if tag is present, removes only files matching that tag (and orphaned blobs), +// except the files another cached tag of the repo still loads // returns true if anything was removed bool common_download_remove(const std::string & hf_repo_with_tag); +// remove the cached sidecar files `opts` selects for "user/model:tag", as the cached +// plan resolves them, and leave the model files in place; a sidecar file another tag +// shares goes for every tag that resolves it +// returns true if anything was removed +bool common_download_remove_sidecars(const std::string & hf_repo_with_tag, const common_download_opts & opts); + struct common_download_hf_plan { hf_cache::hf_file primary; hf_cache::hf_files model_files; @@ -119,3 +133,33 @@ struct common_download_hf_plan { hf_cache::hf_file preset; // if set, only this file is downloaded }; common_download_hf_plan common_download_get_hf_plan(const common_params_model & model, const common_download_opts & opts); + +// a sidecar kind a download can pull next to its model: mmproj, and the draft heads +// of --spec-type draft-<name> +struct common_download_sidecar { + const char * name; // the kind, as the API names it + const char * keyword; // the part of a file name that marks a file of this kind + bool draft; // a draft head, resolved at the tag even without a model + + bool common_download_opts::* opt; // the option that requests it + hf_cache::hf_file common_download_hf_plan::* file; // the plan file it resolves to +}; + +// every sidecar kind, the single list the resolution, the listing and the removal follow +const std::vector<common_download_sidecar> & common_download_sidecars(); + +// select the sidecar `kind` in `opts`; returns false for an unknown kind +bool common_download_opts_add_sidecar(common_download_opts & opts, const std::string & kind); + +// the sidecar kinds `plan` resolves a file for +std::vector<std::string> common_download_plan_sidecars(const common_download_hf_plan & plan); + +// a file `plan` still has to download, at the path its partial takes while it is +// incomplete; kind is the sidecar it belongs to, empty for the model files +struct common_download_partial { + std::string kind; + std::string path; +}; + +// the partials the download of `plan` writes, for the files not in the cache yet +std::vector<common_download_partial> common_download_plan_partials(const common_download_hf_plan & plan); diff --git a/common/file-lock.cpp b/common/file-lock.cpp new file mode 100644 index 000000000000..553a06687f9e --- /dev/null +++ b/common/file-lock.cpp @@ -0,0 +1,179 @@ +#include "file-lock.h" + +#include "log.h" + +#include <chrono> +#include <filesystem> +#include <thread> + +#include <fcntl.h> +#include <sys/stat.h> + +#if defined(_WIN32) +#define WIN32_LEAN_AND_MEAN +#ifndef NOMINMAX +#define NOMINMAX +#endif +#include <windows.h> +#include <io.h> +#else +#include <sys/file.h> +#include <unistd.h> +#include <cerrno> +#include <cstring> +#endif + +common_file_lock::common_file_lock(const std::string & lock_path) { + this->lock_path = lock_path; +} + +#if defined(_WIN32) +// the \\?\ prefix (for paths longer than 255 chars) is only accepted on absolute paths +// with backslash separators: normalize first, then check the length of the absolute form +static std::wstring as_extended_path(const std::string & path) { + // convert from the narrow encoding std::filesystem uses on this system + int wlen = MultiByteToWideChar(CP_ACP, 0, path.c_str(), (int) path.size(), nullptr, 0); + if (wlen <= 0) { + return std::wstring(path.begin(), path.end()); // best effort for exotic encodings + } + std::wstring wide(wlen, L'\0'); + MultiByteToWideChar(CP_ACP, 0, path.c_str(), (int) path.size(), wide.data(), wlen); + + if (wide.rfind(L"\\\\?\\", 0) == 0) { + return wide; + } + + // GetFullPathNameW resolves relative paths and normalizes separators + DWORD size = GetFullPathNameW(wide.c_str(), 0, nullptr, nullptr); + if (size == 0) { + return wide; + } + std::wstring full(size, L'\0'); + DWORD written = GetFullPathNameW(wide.c_str(), size, full.data(), nullptr); + if (written == 0 || written >= size) { + return wide; + } + full.resize(written); + + if (full.size() <= 255) { + return wide; // short enough: open the path exactly as given + } + if (full.rfind(L"\\\\", 0) == 0) { + return L"\\\\?\\UNC\\" + full.substr(2); // \\server\share -> \\?\UNC\server\share + } + return L"\\\\?\\" + full; +} +#endif + +common_file_lock::status common_file_lock::try_lock() { + if (lock_path.empty()) { + return status::acquired; // no lock path, nothing to lock + } +#if defined(_WIN32) + if (fd < 0) { + // opened with a wide path: extended paths cannot go through the narrow CRT + std::wstring lock_path_w = as_extended_path(lock_path); + fd = _wopen(lock_path_w.c_str(), _O_RDWR | _O_CREAT | _O_BINARY | _O_NOINHERIT, _S_IREAD | _S_IWRITE); + if (fd < 0) { + LOG_ERR("%s: cannot open lock file: %s\n", __func__, lock_path.c_str()); + return status::error; + } + } + // lock the first byte, the file itself stays empty + OVERLAPPED ov = {}; + locked = LockFileEx((HANDLE) _get_osfhandle(fd), + LOCKFILE_EXCLUSIVE_LOCK | LOCKFILE_FAIL_IMMEDIATELY, 0, 1, 0, &ov); + if (locked) { + return status::acquired; + } + if (GetLastError() == ERROR_LOCK_VIOLATION) { + return status::busy; + } + LOG_ERR("%s: file locking failed (%d)\n", __func__, (int) GetLastError()); + return status::error; +#else + if (fd < 0) { + int open_flags = O_RDWR | O_CREAT | O_CLOEXEC; +#ifdef O_NOFOLLOW + open_flags |= O_NOFOLLOW; +#endif + // group-writable, so users sharing a cache can wait on the lock + fd = open(lock_path.c_str(), open_flags, 0664); + if (fd < 0) { + LOG_ERR("%s: cannot open lock file: %s\n", __func__, lock_path.c_str()); + return status::error; + } + // open() filters the mode through the umask + (void) fchmod(fd, 0664); + } + + if (flock(fd, LOCK_EX | LOCK_NB) == 0) { + locked = true; + return status::acquired; + } + // EACCES is reported as contention on some filesystems + if (errno == EWOULDBLOCK || errno == EAGAIN || errno == EACCES) { + return status::busy; + } + // flock is not implemented (some NFS/FUSE mounts): report it instead of racing + LOG_ERR("%s: file locking failed (%s)\n", __func__, strerror(errno)); + return status::error; +#endif +} + +bool common_file_lock::acquire(const std::function<bool()> & keep_waiting) { + // the lock file is opened by try_lock, its parent must exist by then + if (!lock_path.empty()) { + std::error_code ec; + auto lock_dir = std::filesystem::path(lock_path).parent_path(); + if (!lock_dir.empty()) { + std::filesystem::create_directories(lock_dir, ec); + if (ec) { + LOG_ERR("%s: unable to create lock directory '%s': %s\n", __func__, lock_dir.string().c_str(), ec.message().c_str()); + return false; + } + } + } + + while (true) { + switch (try_lock()) { + case status::acquired: + return true; + case status::busy: + if (keep_waiting && !keep_waiting()) { + return false; + } + std::this_thread::sleep_for(std::chrono::milliseconds(100)); + continue; + case status::error: + return false; + } + } +} + +// the lock file is never deleted: another process could then create a fresh +// file at the same path and lock that +void common_file_lock::close() { +#if defined(_WIN32) + if (fd >= 0) { + if (locked) { + OVERLAPPED ov = {}; + UnlockFileEx((HANDLE) _get_osfhandle(fd), 0, 1, 0, &ov); + } + _close(fd); + } +#else + if (fd >= 0) { + if (locked) { + flock(fd, LOCK_UN); + } + ::close(fd); + } +#endif + fd = -1; + locked = false; +} + +common_file_lock::~common_file_lock() { + close(); +} diff --git a/common/file-lock.h b/common/file-lock.h new file mode 100644 index 000000000000..6f9443ff81a0 --- /dev/null +++ b/common/file-lock.h @@ -0,0 +1,36 @@ +#pragma once + +#include <functional> +#include <string> + +// Cross-process exclusive lock (flock on POSIX, LockFileEx on Windows). +// Lazy: acquire() opens the lock file, so a read-only cache works if the lock is never acquired. +class common_file_lock { +public: + common_file_lock(const std::string & lock_path); + ~common_file_lock(); + + // take the lock, waiting while another process holds it; + // keep_waiting is polled before each retry, false cancels the wait. + // Also returns false when locking is unavailable. + bool acquire(const std::function<bool()> & keep_waiting = {}); + + void close(); + + common_file_lock(const common_file_lock &) = delete; + common_file_lock & operator=(const common_file_lock &) = delete; + +private: + enum class status { + acquired, + busy, // another process holds the lock + error, // file locking is unavailable: no exclusion is possible + }; + + status try_lock(); + + std::string lock_path; + + int fd = -1; + bool locked = false; +}; diff --git a/common/fit.cpp b/common/fit.cpp index 7a0300829508..55b457e1060d 100644 --- a/common/fit.cpp +++ b/common/fit.cpp @@ -1,6 +1,8 @@ #include "fit.h" +#include "common.h" #include "json.h" +#include "llama-cpp.h" #include "log.h" #include "../src/llama-ext.h" @@ -27,6 +29,32 @@ class common_params_fit_exception : public std::runtime_error { using std::runtime_error::runtime_error; }; +// RAII: send llama logs below min_level to the debug log +struct common_fit_log_scope { + common_fit_log_scope(ggml_log_level min_level) : min_level(min_level) { + llama_log_get(&original_logger.callback, &original_logger.user_data); + llama_log_set([](ggml_log_level level, const char * text, void * user_data) { + const common_fit_log_scope * self = (const common_fit_log_scope *) user_data; + const ggml_log_level level_eff = level >= self->min_level ? level : GGML_LOG_LEVEL_DEBUG; + self->original_logger.callback(level_eff, text, self->original_logger.user_data); + }, this); + } + + ~common_fit_log_scope() { + llama_log_set(original_logger.callback, original_logger.user_data); + } + + common_fit_log_scope(const common_fit_log_scope &) = delete; + common_fit_log_scope & operator=(const common_fit_log_scope &) = delete; + +private: + struct { + ggml_log_callback callback; + void * user_data; + } original_logger; + ggml_log_level min_level; +}; + static std::vector<llama_device_memory_data> common_get_device_memory_data_impl( const char * path_model, const llama_model_params * mparams, @@ -36,22 +64,7 @@ static std::vector<llama_device_memory_data> common_get_device_memory_data_impl( uint32_t & hp_n_ctx_train, uint32_t & hp_n_expert, ggml_log_level log_level) { - struct user_data_t { - struct { - ggml_log_callback callback; - void * user_data; - } original_logger; - ggml_log_level min_level; // prints below this log level go to debug log - }; - user_data_t ud; - llama_log_get(&ud.original_logger.callback, &ud.original_logger.user_data); - ud.min_level = log_level; - - llama_log_set([](ggml_log_level level, const char * text, void * user_data) { - const user_data_t * ud = (const user_data_t *) user_data; - const ggml_log_level level_eff = level >= ud->min_level ? level : GGML_LOG_LEVEL_DEBUG; - ud->original_logger.callback(level_eff, text, ud->original_logger.user_data); - }, &ud); + common_fit_log_scope log_scope(log_level); llama_model_params mparams_copy = *mparams; mparams_copy.no_alloc = true; @@ -59,14 +72,12 @@ static std::vector<llama_device_memory_data> common_get_device_memory_data_impl( llama_model * model = llama_model_load_from_file(path_model, mparams_copy); if (model == nullptr) { - llama_log_set(ud.original_logger.callback, ud.original_logger.user_data); throw std::runtime_error("failed to load model"); } llama_context * ctx = llama_init_from_model(model, *cparams); if (ctx == nullptr) { llama_model_free(model); - llama_log_set(ud.original_logger.callback, ud.original_logger.user_data); throw std::runtime_error("failed to create llama_context from model"); } @@ -148,11 +159,81 @@ static std::vector<llama_device_memory_data> common_get_device_memory_data_impl( llama_free(ctx); llama_model_free(model); - llama_log_set(ud.original_logger.callback, ud.original_logger.user_data); return ret; } +std::vector<common_memory_breakdown_row> common_fit_measure( + const char * path_model, + const llama_model_params * mparams, + const llama_context_params * cparams, + uint32_t * n_ctx_train, + uint32_t * n_ctx, + ggml_log_level log_level) { + common_fit_log_scope log_scope(log_level); + + llama_model_params mparams_copy = *mparams; + mparams_copy.no_alloc = true; + mparams_copy.load_mode = LLAMA_LOAD_MODE_NONE; + + llama_model_ptr model(llama_model_load_from_file(path_model, mparams_copy)); + if (!model) { + throw std::runtime_error("failed to load model"); + } + + llama_context_ptr ctx(llama_init_from_model(model.get(), *cparams)); + if (!ctx) { + throw std::runtime_error("failed to create llama_context from model"); + } + + if (n_ctx_train) { + *n_ctx_train = llama_model_n_ctx_train(model.get()); + } + if (n_ctx) { + *n_ctx = llama_n_ctx(ctx.get()); + } + + return common_memory_breakdown_rows(ctx.get()); +} + +common_memory_reports common_measure_memory(common_params & params) { + const ggml_log_level log_level = params.verbosity >= LOG_LEVEL_DEBUG ? GGML_LOG_LEVEL_DEBUG : GGML_LOG_LEVEL_ERROR; + const char * path_model = params.model.path.c_str(); + + common_memory_reports res; + + auto mparams = common_model_params_to_llama(params); + auto cparams = common_context_params_to_llama(params); + + // max: what --fit picks now, no-op with -fit off + { + auto mparams_fit = mparams; + auto cparams_fit = cparams; + common_fit_apply(params, mparams_fit, cparams_fit); + res.info_max = common_fit_measure(path_model, &mparams_fit, &cparams_fit, &res.n_ctx_train, &res.n_ctx_max, log_level); + } + + // min: the smallest context --fit may pick (--fit only changes n_ctx when it is 0) + uint32_t n_ctx_min = cparams.n_ctx; + if (n_ctx_min == 0 && params.fit_params) { + const uint32_t n_streams = cparams.kv_unified ? 1 : std::max<uint32_t>(1, cparams.n_seq_max); + // -c 0 sets fit_params_min_ctx to UINT32_MAX, cap at n_ctx_train like --fit + n_ctx_min = (uint32_t) std::min<uint64_t>( + uint64_t(params.fit_params_min_ctx) * n_streams, + uint64_t(res.n_ctx_train) * n_streams); + } + if (n_ctx_min == 0 || n_ctx_min >= res.n_ctx_max) { + // nothing to reduce, or -fit off with the trained context + res.n_ctx_min = res.n_ctx_max; + res.info_min = res.info_max; + } else { + cparams.n_ctx = n_ctx_min; + res.info_min = common_fit_measure(path_model, &mparams, &cparams, nullptr, &res.n_ctx_min, log_level); + } + + return res; +} + common_device_memory_data_vec common_get_device_memory_data( const char * path_model, const llama_model_params * mparams, @@ -903,8 +984,7 @@ enum common_params_fit_status common_fit_params( return status; } -void common_memory_breakdown_print(const struct llama_context * ctx) { - //const auto & devices = ctx->get_model().devices; +std::vector<common_memory_breakdown_row> common_memory_breakdown_rows(const struct llama_context * ctx) { const auto * model = llama_get_model(ctx); std::vector<ggml_backend_dev_t> devices; @@ -914,18 +994,6 @@ void common_memory_breakdown_print(const struct llama_context * ctx) { llama_memory_breakdown memory_breakdown = llama_get_memory_breakdown(ctx); - std::vector<std::array<std::string, 9>> table_data; - table_data.reserve(devices.size()); - - // same data as the table below, for --log-jsonl consumers - common_json rows = common_json::array(); - const std::string template_header = "%s: | %s | %s %s %s %s %s %s %s |\n"; - const std::string template_gpu = "%s: | %s | %s = %s + (%s = %s + %s + %s) + %s |\n"; - const std::string template_other = "%s: | %s | %s %s %s = %s + %s + %s %s |\n"; - - table_data.push_back({template_header, "memory breakdown [MiB]", "total", "free", "self", "model", "context", "compute", "unaccounted"}); - - constexpr size_t MiB = 1024 * 1024; const std::vector<std::string> desc_prefixes_strip = {"NVIDIA ", "GeForce ", "Tesla ", "AMD ", "Radeon ", "Instinct "}; // track seen buffer types to avoid double counting: @@ -964,104 +1032,130 @@ void common_memory_breakdown_print(const struct llama_context * ctx) { } } - // print memory breakdown for each device: + std::vector<common_memory_breakdown_row> rows; + rows.reserve(devices.size() + 1 + memory_breakdown.size()); + for (size_t i = 0; i < devices.size(); i++) { ggml_backend_dev_t dev = devices[i]; - llama_memory_breakdown_data mb = mb_dev[i]; - const std::string name = ggml_backend_dev_name(dev); - std::string desc = ggml_backend_dev_description(dev); + common_memory_breakdown_row row; + row.kind = common_memory_breakdown_row::DEVICE; + row.name = ggml_backend_dev_name(dev); + row.description = ggml_backend_dev_description(dev); for (const std::string & prefix : desc_prefixes_strip) { - if (desc.length() >= prefix.length() && desc.substr(0, prefix.length()) == prefix) { - desc = desc.substr(prefix.length()); + if (row.description.length() >= prefix.length() && row.description.substr(0, prefix.length()) == prefix) { + row.description = row.description.substr(prefix.length()); } } size_t free, total; ggml_backend_dev_memory(dev, &free, &total); - - const size_t self = mb.model + mb.context + mb.compute; - const int64_t unaccounted = static_cast<int64_t>(total) - static_cast<int64_t>(free) - static_cast<int64_t>(self); - - table_data.push_back({ - template_gpu, - " - " + name + " (" + desc + ")", - std::to_string(total / MiB), - std::to_string(free / MiB), - std::to_string(self / MiB), - std::to_string(mb.model / MiB), - std::to_string(mb.context / MiB), - std::to_string(mb.compute / MiB), - std::to_string(unaccounted / static_cast<int64_t>(MiB))}); - - rows.push_back({ - {"kind", "device"}, - {"name", name}, - {"description", desc}, - {"total", total / MiB}, - {"free", free / MiB}, - {"self", self / MiB}, - {"model", mb.model / MiB}, - {"context", mb.context / MiB}, - {"compute", mb.compute / MiB}, - {"unaccounted", unaccounted / static_cast<int64_t>(MiB)}, - }); + row.total = total; + row.free = free; + row.model = mb_dev[i].model; + row.context = mb_dev[i].context; + row.compute = mb_dev[i].compute; + rows.push_back(std::move(row)); } - // print memory breakdown for host: { - const size_t self = mb_host.model + mb_host.context + mb_host.compute; - table_data.push_back({ - template_other, - " - Host", - "", // total - "", // free - std::to_string(self / MiB), - std::to_string(mb_host.model / MiB), - std::to_string(mb_host.context / MiB), - std::to_string(mb_host.compute / MiB), - ""}); // unaccounted - - rows.push_back({ - {"kind", "host"}, - {"name", "Host"}, - {"self", self / MiB}, - {"model", mb_host.model / MiB}, - {"context", mb_host.context / MiB}, - {"compute", mb_host.compute / MiB}, - }); + common_memory_breakdown_row row; + row.kind = common_memory_breakdown_row::HOST; + row.name = "Host"; + row.model = mb_host.model; + row.context = mb_host.context; + row.compute = mb_host.compute; + rows.push_back(std::move(row)); } - // print memory breakdown for all remaining buffer types: + // all remaining buffer types: for (const auto & buft_mb : memory_breakdown) { ggml_backend_buffer_type_t buft = buft_mb.first; const llama_memory_breakdown_data & mb = buft_mb.second; if (seen_buffer_types.count(buft) == 1) { continue; } - const std::string name = ggml_backend_buft_name(buft); - const size_t self = mb.model + mb.context + mb.compute; + common_memory_breakdown_row row; + row.kind = common_memory_breakdown_row::BUFFER_TYPE; + row.name = ggml_backend_buft_name(buft); + row.model = mb.model; + row.context = mb.context; + row.compute = mb.compute; + rows.push_back(std::move(row)); + + seen_buffer_types.insert(buft); + } + + return rows; +} + +void common_memory_breakdown_print(const struct llama_context * ctx) { + const std::vector<common_memory_breakdown_row> rows = common_memory_breakdown_rows(ctx); + + std::vector<std::array<std::string, 9>> table_data; + table_data.reserve(rows.size() + 1); + + // same data as the table below, for --log-jsonl consumers + common_json json_rows = common_json::array(); + const std::string template_header = "%s: | %s | %s %s %s %s %s %s %s |\n"; + const std::string template_gpu = "%s: | %s | %s = %s + (%s = %s + %s + %s) + %s |\n"; + const std::string template_other = "%s: | %s | %s %s %s = %s + %s + %s %s |\n"; + + table_data.push_back({template_header, "memory breakdown [MiB]", "total", "free", "self", "model", "context", "compute", "unaccounted"}); + + constexpr size_t MiB = 1024 * 1024; + + for (const auto & row : rows) { + const size_t self = row.model + row.context + row.compute; + + if (row.kind == common_memory_breakdown_row::DEVICE) { + const int64_t unaccounted = row.total - row.free - static_cast<int64_t>(self); + + table_data.push_back({ + template_gpu, + " - " + row.name + " (" + row.description + ")", + std::to_string(row.total / MiB), + std::to_string(row.free / MiB), + std::to_string(self / MiB), + std::to_string(row.model / MiB), + std::to_string(row.context / MiB), + std::to_string(row.compute / MiB), + std::to_string(unaccounted / static_cast<int64_t>(MiB))}); + + json_rows.push_back({ + {"kind", "device"}, + {"name", row.name}, + {"description", row.description}, + {"total", row.total / MiB}, + {"free", row.free / MiB}, + {"self", self / MiB}, + {"model", row.model / MiB}, + {"context", row.context / MiB}, + {"compute", row.compute / MiB}, + {"unaccounted", unaccounted / static_cast<int64_t>(MiB)}, + }); + continue; + } + table_data.push_back({ template_other, - " - " + name, + " - " + row.name, "", // total "", // free std::to_string(self / MiB), - std::to_string(mb.model / MiB), - std::to_string(mb.context / MiB), - std::to_string(mb.compute / MiB), + std::to_string(row.model / MiB), + std::to_string(row.context / MiB), + std::to_string(row.compute / MiB), ""}); // unaccounted - rows.push_back({ - {"kind", "buffer_type"}, - {"name", name}, + json_rows.push_back({ + {"kind", row.kind == common_memory_breakdown_row::HOST ? "host" : "buffer_type"}, + {"name", row.name}, {"self", self / MiB}, - {"model", mb.model / MiB}, - {"context", mb.context / MiB}, - {"compute", mb.compute / MiB}, + {"model", row.model / MiB}, + {"context", row.context / MiB}, + {"compute", row.compute / MiB}, }); - - seen_buffer_types.insert(buft); } for (size_t j = 1; j < table_data[0].size(); j++) { @@ -1081,7 +1175,7 @@ void common_memory_breakdown_print(const struct llama_context * ctx) { LOG_JSON("fit_memory_breakdown", common_json({ {"unit", "MiB"}, - {"rows", rows}, + {"rows", json_rows}, })); } diff --git a/common/fit.h b/common/fit.h index 824d386b07a1..47478bba12e0 100644 --- a/common/fit.h +++ b/common/fit.h @@ -3,6 +3,7 @@ #include "ggml.h" #include "llama.h" +#include <string> #include <vector> enum common_params_fit_status { @@ -45,6 +46,47 @@ void common_fit_print( void common_memory_breakdown_print(const llama_context * ctx); +// one row of the memory breakdown: a device, the host or another buffer type +struct common_memory_breakdown_row { + enum kind_t { DEVICE, HOST, BUFFER_TYPE }; + + kind_t kind = DEVICE; + std::string name; // device or buffer type name, "Host" for the host row + std::string description; // device description, empty otherwise + int64_t total = 0; // device memory in bytes, 0 unless kind == DEVICE + int64_t free = 0; // free device memory in bytes, 0 unless kind == DEVICE + size_t model = 0; // bytes held by this context, by kind of buffer + size_t context = 0; + size_t compute = 0; +}; + +// memory a model needs at the min and max context --fit may pick +struct common_memory_reports { + uint32_t n_ctx_train = 0; + uint32_t n_ctx_max = 0; // the largest context that fits the free device memory right now + uint32_t n_ctx_min = 0; // --fit-ctx (the smallest context --fit may pick), with the placement set in params + std::vector<common_memory_breakdown_row> info_max; // breakdown at n_ctx_max + std::vector<common_memory_breakdown_row> info_min; // breakdown at n_ctx_min +}; + +// rows of common_memory_breakdown_print: model devices first, then host +std::vector<common_memory_breakdown_row> common_memory_breakdown_rows(const llama_context * ctx); + +// load model + context with no_alloc and return the memory breakdown, params are used as-is +// n_ctx_train and n_ctx are optional outputs; throws on failure +std::vector<common_memory_breakdown_row> common_fit_measure( + const char * path_model, + const llama_model_params * mparams, + const llama_context_params * cparams, + uint32_t * n_ctx_train, + uint32_t * n_ctx, + ggml_log_level log_level); + +struct common_params; + +// measure min and max without allocating, params may be modified as with --fit; throws on failure +common_memory_reports common_measure_memory(common_params & params); + struct common_device_memory_data { int64_t total; int64_t free; diff --git a/common/hf-cache.cpp b/common/hf-cache.cpp index 4241d005af27..aafc940c5789 100644 --- a/common/hf-cache.cpp +++ b/common/hf-cache.cpp @@ -2,6 +2,7 @@ #include "build-info.h" #include "common.h" +#include "file-lock.h" #include "log.h" #include "http.h" #include "json.h" @@ -62,7 +63,7 @@ static fs::path get_cache_directory() { } std::string get_cache_path() { - return fs_path_to_utf8(get_cache_directory()); + return get_cache_directory().string(); } static std::string folder_name_to_repo(const std::string & folder) { @@ -161,6 +162,14 @@ static bool is_valid_oid(const std::string & oid) { return is_hex_string(oid, 40) || is_hex_string(oid, 64); } +std::string get_lock_path(const std::string & repo_id, const std::string & oid) { + if (!is_valid_repo_id(repo_id) || !is_valid_oid(oid)) { + return {}; + } + fs::path lock_path = fs::path(get_cache_path()) / ".locks" / repo_to_folder_name(repo_id) / (oid + ".lock"); + return lock_path.string(); +} + static bool is_valid_subpath(const fs::path & path, const fs::path & subpath) { if (subpath.is_absolute()) { return false; // never do a / b with b absolute @@ -331,11 +340,11 @@ hf_files get_repo_files(const std::string & repo_id, file.url = endpoint + repo_id + "/resolve/" + commit + "/" + file.path; fs::path final_path = commit_path / subpath; - file.final_path = fs_path_to_utf8(final_path); + file.final_path = final_path.string(); if (!file.oid.empty() && !fs::exists(final_path)) { fs::path local_path = blobs_path / file.oid; - file.local_path = fs_path_to_utf8(local_path); + file.local_path = local_path.string(); } else { file.local_path = file.final_path; } @@ -402,7 +411,7 @@ hf_files get_cached_files(const std::string & repo_id) { if (!fs::exists(snapshots_path)) { continue; } - std::string _repo_id = folder_name_to_repo(fs_path_to_utf8(repo.path().filename())); + std::string _repo_id = folder_name_to_repo(repo.path().filename().string()); if (!is_valid_repo_id(_repo_id)) { continue; @@ -427,7 +436,7 @@ hf_files get_cached_files(const std::string & repo_id) { file.repo_id = _repo_id; const auto generic_path = path.generic_u8string(); file.path = std::string(generic_path.begin(), generic_path.end()); - file.local_path = fs_path_to_utf8(entry.path()); + file.local_path = entry.path().string(); file.final_path = file.local_path; files.push_back(std::move(file)); } @@ -437,7 +446,7 @@ hf_files get_cached_files(const std::string & repo_id) { return files; } -std::string finalize_file(const hf_file & file) { +std::string finalize_file(const hf_file & file, const std::function<bool()> & keep_waiting) { static std::atomic<bool> symlinks_disabled{false}; std::error_code ec; @@ -452,6 +461,24 @@ std::string finalize_file(const hf_file & file) { return file.final_path; } + // the lock file is shared with huggingface_hub: another process may be + // finalizing the same blob + common_file_lock lock(get_lock_path(file.repo_id, file.oid)); + if (!lock.acquire(keep_waiting)) { + // without the lock, another process could move the blob while we check it + throw std::runtime_error("failed to lock cache for finalization: " + file.final_path); + } + + // acquire() only polls keep_waiting while waiting for a busy lock + if (keep_waiting && !keep_waiting()) { + throw std::runtime_error("download cancelled before finalization: " + file.final_path); + } + + // re-check under the lock: the winner may have created the link already + if (fs::exists(final_path, ec)) { + return file.final_path; + } + fs::create_directories(final_path.parent_path(), ec); if (!symlinks_disabled) { @@ -489,7 +516,7 @@ bool remove_cached_repo(const std::string & repo_id) { std::error_code ec; auto removed = fs::remove_all(repo_path, ec); if (ec) { - LOG_ERR("%s: failed to remove repo cache %s: %s\n", __func__, fs_path_to_utf8(repo_path).c_str(), ec.message().c_str()); + LOG_ERR("%s: failed to remove repo cache %s: %s\n", __func__, repo_path.string().c_str(), ec.message().c_str()); return false; } return removed > 0; diff --git a/common/hf-cache.h b/common/hf-cache.h index 41842db788cb..c03e5718260e 100644 --- a/common/hf-cache.h +++ b/common/hf-cache.h @@ -1,5 +1,6 @@ #pragma once +#include <functional> #include <string> #include <vector> @@ -26,8 +27,14 @@ hf_files get_repo_files( hf_files get_cached_files(const std::string & repo_id = {}); -// Create snapshot path (link or move/copy) and return it -std::string finalize_file(const hf_file & file); +// Lock file path for a blob, shared with the hf CLI: <cache>/.locks/<repo folder>/<oid>.lock +// Pure path computation: creates nothing. Returns an empty string on invalid repo or oid. +std::string get_lock_path(const std::string & repo_id, const std::string & oid); + +// Create snapshot path (link or move/copy) and return it. +// Throws when the lock cannot be taken or keep_waiting returns false. +// A completed snapshot (final_path present) is returned without the lock, so a read-only cache works. +std::string finalize_file(const hf_file & file, const std::function<bool()> & keep_waiting = {}); // Remove the entire cached directory for a repo, returns true if removed bool remove_cached_repo(const std::string & repo_id); diff --git a/common/http.h b/common/http.h index 878ad1ce28a4..10d017f17ed5 100644 --- a/common/http.h +++ b/common/http.h @@ -1,5 +1,7 @@ #pragma once +#include "log.h" + #include <cpp-httplib/httplib.h> #ifdef _WIN32 @@ -97,6 +99,118 @@ static common_http_url common_http_parse_url(const std::string & url) { return parts; } +// match a loopback destination: a remote proxy can never reach the client machine's own +// loopback, so these hosts are always contacted directly, before NO_PROXY is consulted +// (similar to Go's net/http) +static bool common_http_is_loopback(const std::string & host) { + auto lower = [](std::string s) { + for (auto & c : s) { + if (c >= 'A' && c <= 'Z') { + c += 'a' - 'A'; + } + } + return s; + }; + + const std::string h = lower(host); + + if (h == "localhost" || h == "::1" || h == "0.0.0.0") { + return true; + } + + if (h.size() > 10 && h.compare(h.size() - 10, 10, ".localhost") == 0) { + return true; + } + + // IPv4 literal: exactly four all-digit octets with values 0-255, loopback is 127.0.0.0/8 + int octets[4] = { 0, 0, 0, 0 }; + size_t pos = 0; + int n = 0; + bool complete = false; + while (n < 4 && pos <= h.size()) { + size_t dot = h.find('.', pos); + if (dot == std::string::npos) { + dot = h.size(); + } + if (dot == pos || dot - pos > 3) { + return false; + } + int val = 0; + for (size_t i = pos; i < dot; i++) { + if (h[i] < '0' || h[i] > '9') { + return false; + } + val = val * 10 + (h[i] - '0'); + } + if (val > 255) { + return false; + } + octets[n++] = val; + if (dot == h.size()) { + complete = (n == 4); + break; + } + pos = dot + 1; + } + + return complete && octets[0] == 127; +} + +// match a host against a NO_PROXY list: comma separated entries, "*" bypasses the proxy for every host, +// an entry matches the host itself or any of its subdomains, a leading dot is optional, ports are ignored +static bool common_http_proxy_bypass(const std::string & no_proxy, const std::string & host) { + auto lower = [](std::string s) { + for (auto & c : s) { + if (c >= 'A' && c <= 'Z') { + c += 'a' - 'A'; + } + } + return s; + }; + + const std::string h = lower(host); + + for (size_t pos = 0; pos < no_proxy.size(); ) { + size_t end = no_proxy.find(',', pos); + if (end == std::string::npos) { + end = no_proxy.size(); + } + + std::string entry = lower(no_proxy.substr(pos, end - pos)); + pos = end + 1; + + entry.erase(0, entry.find_first_not_of(" \t")); + auto last = entry.find_last_not_of(" \t"); + if (last == std::string::npos) { + continue; + } + entry.erase(last + 1); + + if (entry == "*") { + return true; + } + + if (entry.front() == '.') { + entry.erase(0, 1); + } + + if (entry.empty()) { + continue; + } + + if (h == entry) { + return true; + } + + if (h.size() > entry.size() && h[h.size() - entry.size() - 1] == '.' && + h.compare(h.size() - entry.size(), entry.size(), entry) == 0) { + return true; + } + } + + return false; +} + static std::pair<httplib::Client, common_http_url> common_http_client(const std::string & url) { common_http_url parts = common_http_parse_url(url); @@ -123,6 +237,33 @@ static std::pair<httplib::Client, common_http_url> common_http_client(const std: cli.set_follow_location(true); + // Honor HTTP_PROXY / HTTPS_PROXY environment variables (both lower- and upper-case). + auto getenv_s = [](const char * upper, const char * lower) -> std::string { + const char * val = std::getenv(upper); + if (!val) { + val = std::getenv(lower); + } + return val ? val : ""; + }; + + const std::string proxy_url = (parts.scheme == "https") + ? getenv_s("HTTPS_PROXY", "https_proxy") + : getenv_s("HTTP_PROXY", "http_proxy"); + + if (!proxy_url.empty() && !common_http_is_loopback(parts.host) && + !common_http_proxy_bypass(getenv_s("NO_PROXY", "no_proxy"), parts.host)) { + try { + common_http_url proxy = common_http_parse_url(proxy_url); + cli.set_proxy(proxy.host, proxy.port); + if (!proxy.user.empty()) { + cli.set_proxy_basic_auth(proxy.user, proxy.password); + } + } catch (const std::exception & e) { + // fall back to a direct connection, the URL itself is not logged as it can carry credentials + LOG_WRN("%s: ignoring malformed proxy URL from the environment: %s\n", __func__, e.what()); + } + } + return { std::move(cli), std::move(parts) }; } diff --git a/common/jinja/caps.cpp b/common/jinja/caps.cpp index 6ff17d10bb74..de7780bdf77c 100644 --- a/common/jinja/caps.cpp +++ b/common/jinja/caps.cpp @@ -6,7 +6,9 @@ // we can remove it in the future when we figure out a better way to define inputs using jinja::value #include "json.h" +#include <algorithm> #include <functional> +#include <optional> #include <sstream> #define FILENAME "jinja-caps" @@ -184,6 +186,10 @@ caps caps_get(jinja::program & prog) { { {"role", "user"}, {"content", json::array({ + { + {"type", "text"}, + {"text", content_marker} + } })} } }); @@ -584,6 +590,58 @@ caps caps_get(jinja::program & prog) { } ); + if (result.supports_reasoning_effort) { + JJ_DEBUG("%s\n", ">>> Running capability check: reasoning effort levels"); + + static const std::vector<std::string> candidates = { "minimal", "low", "medium", "high", "xhigh", "max" }; + + // renders a single user turn with the given effort, nothing when the template raises + const auto render = [&](const std::string & effort) { + std::optional<std::string> rendered; + caps_try_execute( + prog, + [&]() { + // messages + return json::array({ + { + {"role", "user"}, + {"content", "User message"} + }, + }); + }, + [&](context & ctx) { + ctx.set_val("enable_thinking", mk_val<value_bool>(true)); + caps_apply_reasoning_effort(ctx, effort); + }, + nullptr, // tools_fn + [&](context &, bool success, value &, value &, const std::string & output) { + if (success) { + rendered = output; + } + } + ); + return rendered; + }; + + // an unknown level shows the render of the template fallback, a level that renders the same is not honored + // levels sharing a render are aliases and the highest one is kept + const auto unknown = render("REASONING_EFFORT_UNKNOWN"); + std::vector<std::string> renders; + for (const auto & level : candidates) { + const auto rendered = render(level); + if (!rendered || rendered == unknown) { + continue; + } + const auto it = std::find(renders.begin(), renders.end(), *rendered); + if (it != renders.end()) { + result.reasoning_effort_levels[it - renders.begin()] = level; + } else { + renders.push_back(*rendered); + result.reasoning_effort_levels.push_back(level); + } + } + } + JJ_DEBUG("%s\n", result.to_string().c_str()); return result; diff --git a/common/jinja/caps.h b/common/jinja/caps.h index b81dd95f2ed6..108501e06b7c 100644 --- a/common/jinja/caps.h +++ b/common/jinja/caps.h @@ -4,6 +4,7 @@ #include <string> #include <map> +#include <vector> namespace jinja { @@ -19,6 +20,9 @@ struct caps { // supports reasoning effort levels bool supports_reasoning_effort = false; + // reasoning effort levels the template renders distinctly, from lowest to highest + std::vector<std::string> reasoning_effort_levels; + // one of the 2 content capabilities must be true bool supports_string_content = true; bool supports_typed_content = false; diff --git a/common/jinja/lexer.cpp b/common/jinja/lexer.cpp index 598982c2fe4a..bf2dfacdadd2 100644 --- a/common/jinja/lexer.cpp +++ b/common/jinja/lexer.cpp @@ -1,7 +1,9 @@ #include "lexer.h" #include "runtime.h" +#include "unicode.h" #include <cctype> +#include <charconv> #include <functional> #include <map> #include <string> @@ -75,6 +77,24 @@ lexer_result lexer::tokenize(const std::string & source) { } // add escaped char char escaped_char = src[pos++]; + if (escaped_char == 'x') { + if (pos + 1 >= src.size()) { + throw lexer_exception("incomplete hexadecimal escape", source, pos); + } + + unsigned int value = 0; + const char * first = &src[pos]; + const char * last = first + 2; + + auto [ptr, ec] = std::from_chars(first, last, value, 16); + if (ec != std::errc{} || ptr != last) { + throw lexer_exception("invalid hexadecimal escape", source, pos); + } + + str += common_unicode_cpt_to_utf8(value); + pos += 2; + continue; + } if (escape_chars.find(escaped_char) == escape_chars.end()) { throw lexer_exception(std::string("unknown escape character \\") + escaped_char, source, pos); } diff --git a/common/jinja/parser.cpp b/common/jinja/parser.cpp index 67dcafe17fed..7e99a1ac8fd0 100644 --- a/common/jinja/parser.cpp +++ b/common/jinja/parser.cpp @@ -21,6 +21,17 @@ static bool is_type(const statement_ptr & ptr) { class parser { const std::vector<token> & tokens; size_t current = 0; + int depth = 0; + + struct depth_guard { + parser & p; + depth_guard(parser & p) : p(p) { + if (++p.depth > JINJA_RECURSIVE_LIMIT) { + throw parser_exception("Parser Error: template is nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep", p.source, p.peek().pos); + } + } + ~depth_guard() { p.depth--; } + }; std::string source; // for error reporting @@ -94,6 +105,7 @@ class parser { } statement_ptr parse_any() { + depth_guard guard(*this); size_t start_pos = current; switch (peek().t) { case token::comment: @@ -254,6 +266,7 @@ class parser { size_t pos0 = current; ++current; // consume {% ++current; // consume 'elif' + depth_guard guard(*this); alternate.push_back(parse_if_statement(pos0)); // nested If } else if (is_statement({"else"})) { ++current; // consume {% @@ -330,6 +343,7 @@ class parser { } statement_ptr parse_if_expression() { + depth_guard guard(*this); auto a = parse_logical_or_expression(); if (is_identifier("if")) { // Ternary expression @@ -373,6 +387,7 @@ class parser { statement_ptr parse_logical_negation_expression() { // Try parse unary operators if (is_identifier("not")) { + depth_guard guard(*this); size_t start_pos = current; auto op = next(); return mk_stmt<unary_expression>(start_pos, op, parse_logical_negation_expression()); @@ -458,6 +473,7 @@ class parser { statement_ptr parse_unary_expression() { if (is(token::unary_operator)) { + depth_guard guard(*this); size_t start_pos = current; auto op = next(); return mk_stmt<unary_expression>(start_pos, op, parse_unary_expression()); @@ -477,9 +493,11 @@ class parser { size_t start_pos = current; auto expr = mk_stmt<call_expression>(start_pos, std::move(callee), parse_args()); auto member = parse_member_expression(std::move(expr)); // foo.x().y - return is(token::open_paren) - ? parse_call_expression(std::move(member)) // foo.x()() - : std::move(member); + if (!is(token::open_paren)) { + return member; + } + depth_guard guard(*this); + return parse_call_expression(std::move(member)); // foo.x()() } statements parse_args() { diff --git a/common/jinja/runtime.cpp b/common/jinja/runtime.cpp index b8a69995b0ab..d32c79fa5cb5 100644 --- a/common/jinja/runtime.cpp +++ b/common/jinja/runtime.cpp @@ -3,6 +3,7 @@ #include "value.h" #include "utils.h" +#include <exception> #include <string> #include <vector> #include <memory> @@ -52,32 +53,39 @@ static void ensure_key_type_allowed(const value & val) { // execute with error handling value statement::execute(context & ctx) const { + std::exception_ptr pending; + std::string message; try { return execute_impl(ctx); } catch (const continue_statement::signal & /* ex */) { - throw; + pending = std::current_exception(); } catch (const break_statement::signal & /* ex */) { - throw; + pending = std::current_exception(); } catch (const rethrown_exception & /* ex */) { - throw; + pending = std::current_exception(); } catch (const not_implemented_exception & /* ex */) { - throw; + pending = std::current_exception(); } catch (const std::exception & e) { const std::string & source = *ctx.src; if (source.empty()) { std::ostringstream oss; oss << "\nError executing " << type() << " at position " << pos << ": " << e.what(); - throw rethrown_exception(oss.str()); + message = oss.str(); } else { std::ostringstream oss; oss << "\n------------\n"; oss << "While executing " << type() << " at " << get_line_col(source, pos) << " in source:\n"; oss << peak_source(source, pos) << "\n"; oss << "Error: " << e.what(); - // throw as another exception to avoid repeated formatting - throw rethrown_exception(oss.str()); + message = oss.str(); } } + // throw outside the catch: MSVC keeps the unwound frames on the stack while a catch block runs + if (pending) { + std::rethrow_exception(pending); + } + // throw as another exception to avoid repeated formatting + throw rethrown_exception(message); } value identifier::execute_impl(context & ctx) const { @@ -299,58 +307,13 @@ value binary_expression::execute_impl(context & ctx) const { throw std::runtime_error("Unknown operator \"" + op.value + "\" between " + left_val->type() + " and " + right_val->type()); } -static value try_builtin_func(context & ctx, const std::string & name, value & input, bool undef_on_missing = false) { - JJ_DEBUG("Trying built-in function '%s' for type %s", name.c_str(), input->type().c_str()); - if (ctx.is_get_stats) { - value_t::stats_t::mark_used(input); - input->stats.ops.insert(name); - } - auto builtins = input->get_builtins(); - auto it = builtins.find(name); - if (it != builtins.end()) { - JJ_DEBUG("Binding built-in '%s'", name.c_str()); - return mk_val<value_func>(name, it->second, input); - } - if (undef_on_missing) { - return mk_val<value_undefined>(name); - } - throw std::runtime_error("Unknown (built-in) filter '" + name + "' for type " + input->type()); -} - static value apply_filter(context & ctx, const statement_ptr & filter, value input) { JJ_DEBUG("Applying filter to %s", input->type().c_str()); - auto set_filter_alias = [](auto & filter_id) { - if (filter_id == "count") { - filter_id = "length"; - } else if (filter_id == "d") { - filter_id = "default"; - } else if (filter_id == "e") { - filter_id = "escape"; - } else if (filter_id == "trim") { - filter_id = "strip"; - } - }; - if (is_stmt<identifier>(filter)) { auto filter_id = cast_stmt<identifier>(filter)->val; - - set_filter_alias(filter_id); JJ_DEBUG("Applying filter '%s' to %s", filter_id.c_str(), input->type().c_str()); - // TODO: Refactor filters so this coercion can be done automatically - if (!input->is_undefined() && !is_val<value_string>(input) && ( - filter_id == "capitalize" || - filter_id == "lower" || - filter_id == "replace" || - filter_id == "strip" || - filter_id == "title" || - filter_id == "upper" || - filter_id == "wordcount" - )) { - JJ_DEBUG("Coercing %s to String for '%s' filter", input->type().c_str(), filter_id.c_str()); - input = mk_val<value_string>(input->as_string()); - } - return try_builtin_func(ctx, filter_id, input)->invoke(func_args(ctx)); + return apply_filter_by_name(ctx, filter_id, input, func_args(ctx)); } else if (is_stmt<call_expression>(filter)) { auto call = cast_stmt<call_expression>(filter); @@ -359,14 +322,13 @@ static value apply_filter(context & ctx, const statement_ptr & filter, value inp } auto filter_id = cast_stmt<identifier>(call->callee)->val; - set_filter_alias(filter_id); JJ_DEBUG("Applying filter '%s' with arguments to %s", filter_id.c_str(), input->type().c_str()); func_args args(ctx); for (const auto & arg_expr : call->args) { args.push_back(arg_expr->execute(ctx)); } - return try_builtin_func(ctx, filter_id, input)->invoke(args); + return apply_filter_by_name(ctx, filter_id, input, args); } else { throw std::runtime_error("Invalid filter expression"); @@ -600,6 +562,7 @@ value for_statement::execute_impl(context & ctx) const { bool noIteration = true; for (size_t i = 0; i < filtered_items.size(); i++) { JJ_DEBUG("For loop iteration %zu/%zu", i + 1, filtered_items.size()); + context loop_scope(scope); value_object loop_obj = mk_val<value_object>(); loop_obj->has_builtins = false; // loop object has no builtins loop_obj->insert("index", mk_val<value_int>(i + 1)); @@ -611,11 +574,11 @@ value for_statement::execute_impl(context & ctx) const { loop_obj->insert("length", mk_val<value_int>(filtered_items.size())); loop_obj->insert("previtem", i > 0 ? filtered_items[i - 1] : mk_val<value_undefined>("previtem")); loop_obj->insert("nextitem", i < filtered_items.size() - 1 ? filtered_items[i + 1] : mk_val<value_undefined>("nextitem")); - scope.set_val("loop", loop_obj); - scope_update_fns[i](scope); + loop_scope.set_val("loop", loop_obj); + scope_update_fns[i](loop_scope); try { for (auto & stmt : body) { - value val = stmt->execute(scope); + value val = stmt->execute(loop_scope); result->push_back(val); } } catch (const continue_statement::signal &) { @@ -746,7 +709,11 @@ value macro_statement::execute_impl(context & ctx) const { std::string name = cast_stmt<identifier>(this->name)->val; const func_handler func = [this, name](const func_args & args) -> value { + if (args.ctx.macro_depth >= JINJA_RECURSIVE_LIMIT) { + throw std::runtime_error("macro calls are nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); + } context macro_ctx(args.ctx); // new scope for macro execution + macro_ctx.macro_depth = args.ctx.macro_depth + 1; bind_parameters(name, this->args, args, macro_ctx); @@ -777,7 +744,11 @@ value call_statement::execute_impl(context & ctx) const { context caller_ctx(ctx); // new scope for caller execution const func_handler func = [this, caller_ctx = std::move(caller_ctx)](const func_args & args) -> value { + if (args.ctx.macro_depth >= JINJA_RECURSIVE_LIMIT) { + throw std::runtime_error("macro calls are nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); + } context block_ctx(caller_ctx); // new scope for block execution + block_ctx.macro_depth = args.ctx.macro_depth + 1; bind_parameters("caller", this->caller_args, args, block_ctx); diff --git a/common/jinja/runtime.h b/common/jinja/runtime.h index bbd0c5caeacc..101e927c4b7f 100644 --- a/common/jinja/runtime.h +++ b/common/jinja/runtime.h @@ -58,6 +58,8 @@ struct context { bool is_get_stats = false; // whether to collect stats + int macro_depth = 0; + visitor_fn visitor; // src is optional, used for error reporting @@ -74,16 +76,13 @@ struct context { } ~context() = default; - context(const context & parent) : context() { + context(const context & parent) : + src(parent.src), + current_time(parent.current_time), + is_get_stats(parent.is_get_stats), + macro_depth(parent.macro_depth), // inherit variables (for example, when entering a new scope) - auto & pvar = parent.env->as_ordered_object(); - for (const auto & pair : pvar) { - set_val(pair.first, pair.second); - } - current_time = parent.current_time; - is_get_stats = parent.is_get_stats; - src = parent.src; - } + env(mk_val<value_object>(*parent.env)) {} value get_val(const std::string & name) { value default_val = mk_val<value_undefined>(name); @@ -714,7 +713,7 @@ struct rethrown_exception : public std::exception { ////////////////////// -static void gather_string_parts_recursive(const value & val, value_string & parts) { +static void gather_string_parts_recursive(const value & val, value_string & parts, int depth = 0) { // TODO: probably allow print value_none as "None" string? currently this breaks some templates if (is_val<value_string>(val)) { const auto & str_val = cast_val<value_string>(val)->val_str; @@ -722,10 +721,12 @@ static void gather_string_parts_recursive(const value & val, value_string & part } else if (is_val<value_int>(val) || is_val<value_float>(val) || is_val<value_bool>(val)) { std::string str_val = val->as_string().str(); parts->val_str.append(str_val); + } else if (is_val<value_array>(val) && depth >= JINJA_RECURSIVE_LIMIT) { + throw std::runtime_error("value is nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); } else if (is_val<value_array>(val)) { auto items = cast_val<value_array>(val)->as_array(); for (const auto & item : items) { - gather_string_parts_recursive(item, parts); + gather_string_parts_recursive(item, parts, depth + 1); } } } diff --git a/common/jinja/utils.h b/common/jinja/utils.h index de6947fc28f3..da3757a4aae6 100644 --- a/common/jinja/utils.h +++ b/common/jinja/utils.h @@ -6,6 +6,8 @@ #include <cstdint> #include <cstring> +#define JINJA_RECURSIVE_LIMIT 128 + namespace jinja { static void string_replace_all(std::string & s, const std::string & search, const std::string & replace) { diff --git a/common/jinja/value.cpp b/common/jinja/value.cpp index aed834ce460b..333241d7a9e7 100644 --- a/common/jinja/value.cpp +++ b/common/jinja/value.cpp @@ -6,6 +6,7 @@ #include "json.h" #include <sstream> +#include <stdexcept> #include <string> #include <cctype> #include <cfloat> @@ -71,6 +72,17 @@ const std::vector<value> & func_args::get_args() const { return args; } +void func_args::ensure_kwargs(std::initializer_list<const char *> names) const { + for (const auto & arg : args) { + if (is_val<value_kwarg>(arg)) { + auto * kwarg = cast_val<value_kwarg>(arg); + if (std::find(names.begin(), names.end(), kwarg->key) == names.end()) { + throw raised_exception("Function '" + func_name + "' got an unexpected keyword argument '" + kwarg->key + "'"); + } + } + } +} + /** * Function that mimics Python's array slicing. */ @@ -133,6 +145,14 @@ static value empty_value_fn(const func_args &) { return mk_val<T>(); } } + +template<typename T> +static value empty_value_no_args_fn(const func_args & args) { + args.ensure_kwargs(); + args.ensure_count(1, 1); + return empty_value_fn<T>(args); +} + template<typename T> static value test_type_fn(const func_args & args) { args.ensure_count(1); @@ -244,6 +264,8 @@ static std::string json_ensure_ascii_preserving_format(const std::string & json_ return output; } +static std::string float_repr(double val); + static value tojson(const func_args & args) { args.ensure_count(1, 5); value val_ascii = args.get_kwarg_or_pos("ensure_ascii", 1); @@ -297,74 +319,53 @@ static value & get_attribute(const value & val, const value & attr, value & defa return default_val; } -template<bool is_reject> -static value selectattr(const func_args & args) { - args.ensure_count(2, 4); - args.ensure_vals<value_array, value_string, value_string, value_string>(true, true, false, false); +template<bool is_reject, bool lookup_attr> +static value select_or_reject(const func_args & args) { + // example: array | select("odd") -> test_is_odd(item) + // example: array | selectattr("status", "equalto", "active") -> test_is_equalto(item.status, "active") + constexpr size_t test_pos = lookup_attr ? 2 : 1; + args.ensure_count(test_pos); + args.ensure_val<value_array>(args.get_pos(0)); + value attr; + if constexpr (lookup_attr) { + attr = args.get_pos(1); + args.ensure_val<value_string>(attr); + } + + auto & builtins = global_builtins(); + auto test_it = builtins.end(); + if (args.count() > test_pos) { + args.ensure_val<value_string>(args.get_pos(test_pos)); + std::string test_name = args.get_pos(test_pos)->as_string().str(); + test_it = builtins.find("test_is_" + test_name); + if (test_it == builtins.end()) { + throw raised_exception(args.func_name + ": unknown test '" + test_name + "'"); + } + } auto arr = args.get_pos(0)->as_array(); - auto attribute = args.get_pos(1); auto out = mk_val<value_array>(); value val_default = mk_val<value_undefined>(); - if (args.count() == 2) { - // example: array | selectattr("active") - for (const auto & item : arr) { - value attr_val = get_attribute(item, attribute, val_default); - bool is_selected = attr_val->as_bool(); - if constexpr (is_reject) is_selected = !is_selected; - if (is_selected) out->push_back(item); - } - return out; - - } else if (args.count() == 3) { - // example: array | selectattr("equalto", "text") - // translated to: test_is_equalto(item, "text") - std::string test_name = args.get_pos(1)->as_string().str(); - value test_val = args.get_pos(2); - auto & builtins = global_builtins(); - auto it = builtins.find("test_is_" + test_name); - if (it == builtins.end()) { - throw raised_exception("selectattr: unknown test '" + test_name + "'"); - } - auto test_fn = it->second; - for (const auto & item : arr) { - func_args test_args(args.ctx); - test_args.push_back(item); // current object - test_args.push_back(test_val); // extra argument - value test_result = test_fn(test_args); - bool is_selected = test_result->as_bool(); - if constexpr (is_reject) is_selected = !is_selected; - if (is_selected) out->push_back(item); - } - return out; - - } else if (args.count() == 4) { - // example: array | selectattr("status", "equalto", "active") - // translated to: test_is_equalto(item.status, "active") - std::string test_name = args.get_pos(2)->as_string().str(); - auto extra_arg = args.get_pos(3); - auto & builtins = global_builtins(); - auto it = builtins.find("test_is_" + test_name); - if (it == builtins.end()) { - throw raised_exception("selectattr: unknown test '" + test_name + "'"); + for (const auto & item : arr) { + value val = item; + if constexpr (lookup_attr) { + val = get_attribute(item, attr, val_default); } - auto test_fn = it->second; - for (const auto & item : arr) { - value attr_val = get_attribute(item, attribute, val_default); + bool is_selected; + if (test_it == builtins.end()) { + is_selected = val->as_bool(); + } else { func_args test_args(args.ctx); - test_args.push_back(attr_val); // attribute value - test_args.push_back(extra_arg); // extra argument - value test_result = test_fn(test_args); - bool is_selected = test_result->as_bool(); - if constexpr (is_reject) is_selected = !is_selected; - if (is_selected) out->push_back(item); + test_args.push_back(val); + for (size_t i = test_pos + 1; i < args.count(); i++) { + test_args.push_back(args.get_pos(i)); + } + is_selected = test_it->second(test_args)->as_bool(); } - return out; - } else { - throw raised_exception("selectattr: invalid number of arguments"); + if constexpr (is_reject) is_selected = !is_selected; + if (is_selected) out->push_back(item); } - return out; } @@ -423,7 +424,12 @@ const func_builtins & global_builtins() { throw raised_exception("Jinja Exception: " + msg); }}, {"dict", toobject}, - {"namespace", toobject}, + {"namespace", [](const func_args & args) -> value { + // unlike a dict, a namespace has no methods: ns.items is the attribute, as in jinja2 + value out = toobject(args); + cast_val<value_object>(out)->has_builtins = false; + return out; + }}, {"strftime_now", [](const func_args & args) -> value { args.ensure_vals<value_string>(); std::string format = args.get_pos(0)->as_string().str(); @@ -607,6 +613,52 @@ const func_builtins & global_builtins() { return builtins; } +value try_builtin_func(context & ctx, const std::string & name, value & input, bool undef_on_missing) { + JJ_DEBUG("Trying built-in function '%s' for type %s", name.c_str(), input->type().c_str()); + if (ctx.is_get_stats) { + value_t::stats_t::mark_used(input); + input->stats.ops.insert(name); + } + auto builtins = input->get_builtins(); + auto it = builtins.find(name); + if (it != builtins.end()) { + JJ_DEBUG("Binding built-in '%s'", name.c_str()); + return mk_val<value_func>(name, it->second, input); + } + if (undef_on_missing) { + return mk_val<value_undefined>(name); + } + throw std::runtime_error("Unknown (built-in) filter '" + name + "' for type " + input->type()); +} + +value apply_filter_by_name(context & ctx, std::string filter_id, value input, const func_args & args) { + if (filter_id == "count") { + filter_id = "length"; + } else if (filter_id == "d") { + filter_id = "default"; + } else if (filter_id == "e") { + filter_id = "escape"; + } else if (filter_id == "trim") { + filter_id = "strip"; + } + + // TODO: Refactor filters so this coercion can be done automatically + if (!input->is_undefined() && !is_val<value_string>(input) && ( + filter_id == "capitalize" || + filter_id == "lower" || + filter_id == "replace" || + filter_id == "strip" || + filter_id == "title" || + filter_id == "upper" || + filter_id == "wordcount" + )) { + JJ_DEBUG("Coercing %s to String for '%s' filter", input->type().c_str(), filter_id.c_str()); + input = mk_val<value_string>(input->as_string()); + } + + return try_builtin_func(ctx, filter_id, input)->invoke(args); +} + const func_builtins & value_int_t::get_builtins() const { static const func_builtins builtins = { @@ -634,6 +686,11 @@ const func_builtins & value_int_t::get_builtins() const { const func_builtins & value_float_t::get_builtins() const { + // Python's str() of a float, nan and inf stay as they are (tojson writes NaN and Infinity) + static const func_handler tostring = [](const func_args & args) -> value { + args.ensure_vals<value_float>(); + return mk_val<value_string>(float_repr(args.get_pos(0)->as_float())); + }; static const func_builtins builtins = { {"default", default_value}, {"abs", [](const func_args & args) -> value { @@ -650,8 +707,8 @@ const func_builtins & value_float_t::get_builtins() const { args.ensure_vals<value_float>(); return mk_val<value_float>(args.get_pos(0)->as_float()); }}, - {"safe", tojson}, - {"string", tojson}, + {"safe", tostring}, + {"string", tostring}, {"tojson", tojson}, }; return builtins; @@ -675,16 +732,22 @@ const func_builtins & value_string_t::get_builtins() const { static const func_builtins builtins = { {"default", default_value}, {"upper", [](const func_args & args) -> value { + args.ensure_kwargs(); + args.ensure_count(1, 1); args.ensure_vals<value_string>(); jinja::string str = args.get_pos(0)->as_string().uppercase(); return mk_val<value_string>(str); }}, {"lower", [](const func_args & args) -> value { + args.ensure_kwargs(); + args.ensure_count(1, 1); args.ensure_vals<value_string>(); jinja::string str = args.get_pos(0)->as_string().lowercase(); return mk_val<value_string>(str); }}, {"strip", [](const func_args & args) -> value { + args.ensure_kwargs({"chars"}); + args.ensure_count(1, 2); value val_input = args.get_pos(0); if (!is_val<value_string>(val_input)) { throw raised_exception("strip() first argument must be a string"); @@ -715,11 +778,15 @@ const func_builtins & value_string_t::get_builtins() const { } }}, {"title", [](const func_args & args) -> value { + args.ensure_kwargs(); + args.ensure_count(1, 1); args.ensure_vals<value_string>(); jinja::string str = args.get_pos(0)->as_string().titlecase(); return mk_val<value_string>(str); }}, {"capitalize", [](const func_args & args) -> value { + args.ensure_kwargs(); + args.ensure_count(1, 1); args.ensure_vals<value_string>(); jinja::string str = args.get_pos(0)->as_string().capitalize(); return mk_val<value_string>(str); @@ -1021,8 +1088,8 @@ const func_builtins & value_bool_t::get_builtins() const { return builtins; } -[[noreturn]] static value array_unique_not_implemented(const func_args &) { - throw not_implemented_exception("Array unique builtin not implemented"); +[[noreturn]] static value array_sum_not_implemented(const func_args &) { + throw not_implemented_exception("Array sum builtin not implemented"); } const func_builtins & value_array_t::get_builtins() const { @@ -1087,11 +1154,13 @@ const func_builtins & value_array_t::get_builtins() const { auto arr = slice(val->as_array(), start, stop, step); return is_val<value_tuple>(val) ? mk_val<value_tuple>(std::move(arr)) : mk_val<value_array>(std::move(arr)); }}, - {"selectattr", selectattr<false>}, - {"select", selectattr<false>}, - {"rejectattr", selectattr<true>}, - {"reject", selectattr<true>}, + {"selectattr", select_or_reject<false, true>}, + {"select", select_or_reject<false, false>}, + {"rejectattr", select_or_reject<true, true>}, + {"reject", select_or_reject<true, false>}, + {"sum", array_sum_not_implemented}, {"join", [](const func_args & args) -> value { + args.ensure_kwargs({"d", "attribute"}); args.ensure_count(1, 3); if (!is_val<value_array>(args.get_pos(0))) { throw raised_exception("join() first argument must be an array"); @@ -1129,13 +1198,28 @@ const func_builtins & value_array_t::get_builtins() const { {"tojson", tojson}, {"map", [](const func_args & args) -> value { args.ensure_count(2); - if (!is_val<value_array>(args.get_pos(0))) { + value val = args.get_pos(0); + if (!is_val<value_array>(val)) { throw raised_exception("map: first argument must be an array"); } if (!is_val<value_kwarg>(args.get_args().at(1))) { - throw not_implemented_exception("map: filter-mapping not implemented"); + value filter = args.get_pos(1); + if (!is_val<value_string>(filter)) { + throw raised_exception("map: filter name must be a string"); + } + auto out = mk_val<value_array>(); + func_args filter_args(args.ctx); + const auto & all_args = args.get_args(); + for (size_t i = 2; i < all_args.size(); ++i) { + filter_args.push_back(all_args[i]); + } + const std::string filter_id = filter->as_string().str(); + auto arr = val->as_array(); + for (const auto & item : arr) { + out->push_back(apply_filter_by_name(args.ctx, filter_id, item, filter_args)); + } + return is_val<value_tuple>(val) ? mk_val<value_tuple>(out->as_array()) : out; } - value val = args.get_pos(0); value attribute = args.get_kwarg_or_pos("attribute", 1); value default_val = args.get_kwarg("default", mk_val<value_undefined>()); auto out = mk_val<value_array>(); @@ -1144,7 +1228,7 @@ const func_builtins & value_array_t::get_builtins() const { value attr_val = get_attribute(item, attribute, default_val); out->push_back(attr_val); } - return is_val<value_tuple>(val) ? mk_val<value_tuple>(std::move(out->as_array())) : out; + return is_val<value_tuple>(val) ? mk_val<value_tuple>(out->as_array()) : out; }}, {"append", [](const func_args & args) -> value { args.ensure_count(2); @@ -1250,7 +1334,36 @@ const func_builtins & value_array_t::get_builtins() const { } return result; }}, - {"unique", array_unique_not_implemented}, + {"unique", [](const func_args & args) -> value { + args.ensure_count(1, 3); + args.ensure_vals<value_array>(); + value val = args.get_pos(0); + value val_case = args.get_kwarg_or_pos("case_sensitive", 1); + value attribute = args.get_kwarg_or_pos("attribute", 2); + // FIXME: unique is currently always case sensitive + //const bool case_sensitive = val_case->as_bool(); // undefined == false + value undef = mk_val<value_undefined>(); + std::vector<value> result; + std::vector<value> seen; + for (const auto & item : val->as_array()) { + value key = item; + if (!attribute->is_undefined()) { + key = get_attribute(item, attribute, undef); + } + bool dup = false; + for (const auto & s : seen) { + if (value_compare(s, key, value_compare_op::eq)) { + dup = true; + break; + } + } + if (!dup) { + seen.push_back(key); + result.push_back(item); + } + } + return mk_val<value_array>(std::move(result)); + }}, }; return builtins; } @@ -1292,6 +1405,15 @@ const func_builtins & value_object_t::get_builtins() const { } return result; }}, + {"list", [](const func_args & args) -> value { + args.ensure_vals<value_object>(); + const auto & obj = args.get_pos(0)->as_ordered_object(); + auto result = mk_val<value_array>(); + for (const auto & pair : obj) { + result->push_back(pair.first); + } + return result; + }}, {"values", [](const func_args & args) -> value { args.ensure_vals<value_object>(); const auto & obj = args.get_pos(0)->as_ordered_object(); @@ -1379,14 +1501,18 @@ const func_builtins & value_none_t::get_builtins() const { const func_builtins & value_undefined_t::get_builtins() const { static const func_builtins builtins = { {"default", default_value}, - {"capitalize", empty_value_fn<value_string>}, + {"capitalize", empty_value_no_args_fn<value_string>}, {"first", empty_value_fn<value_undefined>}, {"items", empty_value_fn<value_array>}, - {"join", empty_value_fn<value_string>}, + {"join", [](const func_args & args) -> value { + args.ensure_kwargs({"d", "attribute"}); + args.ensure_count(1, 3); + return empty_value_fn<value_string>(args); + }}, {"last", empty_value_fn<value_undefined>}, {"length", empty_value_fn<value_int>}, {"list", empty_value_fn<value_array>}, - {"lower", empty_value_fn<value_string>}, + {"lower", empty_value_no_args_fn<value_string>}, {"map", empty_value_fn<value_array>}, {"max", empty_value_fn<value_undefined>}, {"min", empty_value_fn<value_undefined>}, @@ -1399,12 +1525,16 @@ const func_builtins & value_undefined_t::get_builtins() const { {"selectattr", empty_value_fn<value_array>}, {"sort", empty_value_fn<value_array>}, {"string", empty_value_fn<value_string>}, - {"strip", empty_value_fn<value_string>}, + {"strip", [](const func_args & args) -> value { + args.ensure_kwargs({"chars"}); + args.ensure_count(1, 2); + return empty_value_fn<value_string>(args); + }}, {"sum", empty_value_fn<value_int>}, - {"title", empty_value_fn<value_string>}, + {"title", empty_value_no_args_fn<value_string>}, {"truncate", empty_value_fn<value_string>}, {"unique", empty_value_fn<value_array>}, - {"upper", empty_value_fn<value_string>}, + {"upper", empty_value_no_args_fn<value_string>}, {"wordcount", empty_value_fn<value_int>}, }; return builtins; @@ -1414,7 +1544,8 @@ const func_builtins & value_undefined_t::get_builtins() const { ////////////////////////////////// -static value from_json(const common_json & j, bool mark_input) { +// the runtime walks values with recursion, a deeper input overflows the stack +static value from_json(const common_json & j, bool mark_input, int depth = 0) { if (j.is_null()) { return mk_val<value_none>(); } else if (j.is_boolean()) { @@ -1429,16 +1560,18 @@ static value from_json(const common_json & j, bool mark_input) { str->mark_input(); } return str; + } else if ((j.is_array() || j.is_object()) && depth >= JINJA_RECURSIVE_LIMIT) { + throw std::invalid_argument("JSON is nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); } else if (j.is_array()) { auto arr = mk_val<value_array>(); for (const auto & item : j) { - arr->push_back(from_json(item, mark_input)); + arr->push_back(from_json(item, mark_input, depth + 1)); } return arr; } else if (j.is_object()) { auto obj = mk_val<value_object>(); for (auto it = j.begin(); it != j.end(); ++it) { - obj->insert(it.key(), from_json(it.value(), mark_input)); + obj->insert(it.key(), from_json(it.value(), mark_input, depth + 1)); } return obj; } else { @@ -1522,10 +1655,10 @@ void global_from_json(context & ctx, const common_json & json_obj, bool mark_inp } } -// a float as Python writes it (repr, json.dumps): the shortest digits that read back as the same value -static std::string float_to_json(double val) { +// a float as Python's repr() and str() write it: the shortest digits that read back as the same value +static std::string float_repr(double val) { if (!std::isfinite(val)) { - return std::isnan(val) ? "nan" : val < 0 ? "-inf" : "inf"; // as before (json.dumps writes NaN and Infinity, str() writes nan and inf) + return std::isnan(val) ? "nan" : val < 0 ? "-inf" : "inf"; } const double mag = std::fabs(val); @@ -1551,6 +1684,7 @@ static std::string float_to_json(double val) { if (prec == 16 || reads_back(d)) { digits = d; } else if (is_pow2 && d.back() != '9') { + // a last digit 9 is not bumped (it would carry): no power of 2, from 2^-1074 to 2^1023, needs it d.back()++; if (reads_back(d)) { digits = d; @@ -1581,6 +1715,17 @@ static std::string float_to_json(double val) { return out; } +// a float as json.dumps writes it: nan and inf as NaN and Infinity, which are not valid JSON +static std::string float_json(double val) { + if (std::isnan(val)) { + return "NaN"; + } + if (std::isinf(val)) { + return val < 0 ? "-Infinity" : "Infinity"; + } + return float_repr(val); +} + // recursively convert value to JSON string // TODO: avoid circular references static void value_to_json_internal(std::ostringstream & oss, const value & val, int curr_lvl, int indent, const std::string_view item_sep, const std::string_view key_sep) { @@ -1598,7 +1743,7 @@ static void value_to_json_internal(std::ostringstream & oss, const value & val, } else if (is_val<value_int>(val)) { oss << val->as_int(); } else if (is_val<value_float>(val)) { - oss << float_to_json(val->as_float()); + oss << float_json(val->as_float()); } else if (is_val<value_string>(val)) { oss << "\""; for (char c : val->as_string().str()) { @@ -1621,6 +1766,8 @@ static void value_to_json_internal(std::ostringstream & oss, const value & val, } } oss << "\""; + } else if ((is_val<value_array>(val) || is_val<value_object>(val)) && curr_lvl >= JINJA_RECURSIVE_LIMIT) { + throw std::runtime_error("value is nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); } else if (is_val<value_array>(val)) { const auto & arr = val->as_array(); oss << "["; @@ -1645,7 +1792,8 @@ static void value_to_json_internal(std::ostringstream & oss, const value & val, size_t i = 0; for (const auto & pair : obj) { oss << indent_str() << (indent > 0 ? std::string(indent, ' ') : ""); - value_to_json_internal(oss, mk_val<value_string>(pair.first->as_string().str()), curr_lvl + 1, indent, item_sep, key_sep); + const std::string key = is_val<value_float>(pair.first) ? float_json(pair.first->as_float()) : pair.first->as_string().str(); + value_to_json_internal(oss, mk_val<value_string>(key), curr_lvl + 1, indent, item_sep, key_sep); oss << key_sep; value_to_json_internal(oss, pair.second, curr_lvl + 1, indent, item_sep, key_sep); if (i < obj.size() - 1) { @@ -1685,17 +1833,20 @@ std::string value_to_string_repr(const value & val) { } // stats utility -void value_t::stats_t::mark_used(value & val, bool deep) { +void value_t::stats_t::mark_used(value & val, bool deep, int depth) { val->stats.used = true; + if (deep && (is_val<value_array>(val) || is_val<value_object>(val)) && depth >= JINJA_RECURSIVE_LIMIT) { + throw std::runtime_error("value is nested more than " + std::to_string(JINJA_RECURSIVE_LIMIT) + " levels deep"); + } if (deep) { if (is_val<value_array>(val)) { for (auto & item : val->val_arr) { - mark_used(item, deep); + mark_used(item, deep, depth + 1); } } else if (is_val<value_object>(val)) { for (auto & pair : val->val_obj) { - mark_used(pair.first, deep); - mark_used(pair.second, deep); + mark_used(pair.first, deep, depth + 1); + mark_used(pair.second, deep, depth + 1); } } } diff --git a/common/jinja/value.h b/common/jinja/value.h index 142943dfd79f..8fdff884edee 100644 --- a/common/jinja/value.h +++ b/common/jinja/value.h @@ -7,6 +7,7 @@ #include <cmath> #include <cstdint> #include <functional> +#include <initializer_list> #include <map> #include <memory> #include <set> @@ -119,7 +120,7 @@ struct value_t { // ops can be builtin calls or operators: "array_access", "object_access" std::set<std::string> ops; // utility to recursively mark value and its children as used - static void mark_used(value & val, bool deep = false); + static void mark_used(value & val, bool deep = false, int depth = 0); } stats; value_t() = default; @@ -176,6 +177,8 @@ struct value_t { // const func_builtins & global_builtins(); +value try_builtin_func(context & ctx, const std::string & name, value & input, bool undef_on_missing = false); +value apply_filter_by_name(context & ctx, std::string filter_id, value input, const func_args & args); std::string value_to_json(const value & val, int indent = -1, const std::string_view item_sep = ", ", const std::string_view key_sep = ": "); @@ -658,6 +661,7 @@ struct func_args { size_t count() const { return args.size(); } void push_back(const value & val); void push_front(const value & val); + void ensure_kwargs(std::initializer_list<const char *> names = {}) const; void ensure_count(size_t min, size_t max = 999) const { size_t n = args.size(); if (n < min || n > max) { diff --git a/common/json-schema-to-grammar.cpp b/common/json-schema-to-grammar.cpp index 3349ae4fe0cc..6f3ecc992113 100644 --- a/common/json-schema-to-grammar.cpp +++ b/common/json-schema-to-grammar.cpp @@ -272,15 +272,12 @@ static bool is_reserved_name(const std::string & name) { return RESERVED_NAMES.find(name) != RESERVED_NAMES.end(); } -static std::regex INVALID_RULE_CHARS_RE("[^a-zA-Z0-9-]+"); static std::regex GRAMMAR_LITERAL_ESCAPE_RE("[\r\n\"\\\\]"); static std::regex GRAMMAR_RANGE_LITERAL_ESCAPE_RE("[\r\n\"\\]\\-\\\\]"); static std::unordered_map<char, std::string> GRAMMAR_LITERAL_ESCAPES = { {'\r', "\\r"}, {'\n', "\\n"}, {'"', "\\\""}, {'-', "\\-"}, {']', "\\]"}, {'\\', "\\\\"} }; -static const int MAX_PATTERN_DEPTH = 100; - static std::unordered_set<char> NON_LITERAL_SET = {'|', '.', '(', ')', '[', ']', '{', '}', '*', '+', '?', '^', '$'}; static std::unordered_set<char> ESCAPED_IN_REGEXPS_BUT_NOT_IN_LITERALS = {'^', '$', '.', '[', ']', '(', ')', '|', '{', '}', '*', '+', '?'}; @@ -312,6 +309,22 @@ static std::string format_literal(const std::string & literal) { std::string gbnf_format_literal(const std::string & literal) { return format_literal(literal); } +// same as std::regex_replace with [^a-zA-Z0-9-]+ -> "-", no std::regex: libstdc++ recurses per char +std::string gbnf_format_rule_name(const std::string & name) { + std::string out; + bool in_invalid = false; + for (char c : name) { + if ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9') || c == '-') { + out += c; + in_invalid = false; + } else if (!in_invalid) { + out += '-'; + in_invalid = true; + } + } + return out; +} + static size_t gbnf_escape_length(const std::string & pattern, size_t pos) { if (pos + 1 >= pattern.length() || pattern[pos] != '\\') { return 0; @@ -347,6 +360,17 @@ class common_chat_schema_converter { std::unordered_set<std::string> _refs_being_resolved; std::vector<std::string> _errors; std::vector<std::string> _warnings; + int _depth = 0; + + struct depth_guard { + int & depth; + depth_guard(int & depth) : depth(depth) { + if (++depth > COMMON_RECURSIVE_LIMIT) { + throw std::invalid_argument("JSON schema is nested more than " + std::to_string(COMMON_RECURSIVE_LIMIT) + " levels deep"); + } + } + ~depth_guard() { depth--; } + }; template <typename T> static const T & as(const common_chat_schema & node) { @@ -354,7 +378,7 @@ class common_chat_schema_converter { } std::string _add_rule(const std::string & name, const std::string & rule) { - std::string esc_name = regex_replace(name, INVALID_RULE_CHARS_RE, "-"); + std::string esc_name = gbnf_format_rule_name(name); if (_rules.find(esc_name) == _rules.end() || _rules[esc_name] == rule) { _rules[esc_name] = rule; return esc_name; @@ -482,7 +506,7 @@ class common_chat_schema_converter { } } paren_depth++; - if (paren_depth > MAX_PATTERN_DEPTH) { + if (paren_depth > COMMON_RECURSIVE_LIMIT) { throw unsupported_pattern("pattern nesting too deep"); } seq.emplace_back("(" + to_rule(transform()) + ")", false); @@ -644,7 +668,11 @@ class common_chat_schema_converter { std::string char_rule = _add_primitive("char", PRIMITIVE_RULES.at("char")); std::ostringstream out; out << "[\"] ( "; - std::function<void(size_t)> visit = [&](size_t idx) { + // one level per char of the longest name + std::function<void(size_t, int)> visit = [&](size_t idx, int depth) { + if (depth >= COMMON_RECURSIVE_LIMIT) { + throw std::invalid_argument("JSON schema property name is longer than " + std::to_string(COMMON_RECURSIVE_LIMIT) + " chars"); + } const auto & node = trie.nodes[idx]; std::string rejects; auto first = true; @@ -659,7 +687,7 @@ class common_chat_schema_converter { out << "[" << c << "]"; if (!trie.nodes[child].children.empty()) { out << " ("; - visit(child); + visit(child, depth + 1); out << ")"; } else { out << " " << char_rule << "+"; @@ -669,7 +697,7 @@ class common_chat_schema_converter { out << " | [^\"" << rejects << "] " << char_rule << "*"; } }; - visit(0); + visit(0, 0); out << " )"; if (trie.nodes[0].pattern < 0) { @@ -682,8 +710,7 @@ class common_chat_schema_converter { std::string _resolve_ref(const common_chat_schema_ref & schema) { auto it = schema.ref.find('#'); std::string ref_fragment = it != std::string::npos ? schema.ref.substr(it + 1) : schema.ref; - static const std::regex nonalphanumeric_regex(R"([^a-zA-Z0-9-]+)"); - std::string ref_name = "ref" + std::regex_replace(ref_fragment, nonalphanumeric_regex, "-"); + std::string ref_name = "ref" + gbnf_format_rule_name(ref_fragment); if (_rules.find(ref_name) == _rules.end() && _refs_being_resolved.find(schema.ref) == _refs_being_resolved.end()) { if (!schema.target) { _errors.push_back("Unresolved $ref " + schema.ref); @@ -833,10 +860,13 @@ class common_chat_schema_converter { std::unordered_set<std::string> required; std::vector<std::pair<std::string, const common_chat_schema *>> properties; std::map<std::string, size_t> enum_values; - std::function<void(const common_chat_schema &, bool)> add_component = [&](const common_chat_schema & comp, bool is_required) { + std::function<void(const common_chat_schema &, bool, int)> add_component = [&](const common_chat_schema & comp, bool is_required, int depth) { + if (depth >= COMMON_RECURSIVE_LIMIT) { + throw std::invalid_argument("JSON schema is nested more than " + std::to_string(COMMON_RECURSIVE_LIMIT) + " levels deep"); + } if (comp.kind() == common_chat_schema::KIND_REF) { if (const auto * target = as<common_chat_schema_ref>(comp).target) { - add_component(*target, is_required); + add_component(*target, is_required, depth + 1); } } else if (comp.kind() == common_chat_schema::KIND_OBJECT) { for (const auto & prop : as<common_chat_schema_object>(comp).properties) { @@ -854,10 +884,10 @@ class common_chat_schema_converter { for (const auto & child : schema.children) { if (child->kind() == common_chat_schema::KIND_ANY_OF) { for (const auto & alt : as<common_chat_schema_any_of>(*child).children) { - add_component(*alt, false); + add_component(*alt, false, 0); } } else { - add_component(*child, true); + add_component(*child, true, 0); } } if (!enum_values.empty()) { @@ -875,6 +905,8 @@ class common_chat_schema_converter { } std::string visit(const common_chat_schema & schema, const std::string & name) { + // the $ref targets are visited too, a $ref chain is not bounded by the builder + depth_guard guard(_depth); std::string rule_name = is_reserved_name(name) ? name + "-" : name.empty() ? "root" : name; std::string sub_name = name + (name.empty() ? "" : "-"); diff --git a/common/json-schema-to-grammar.h b/common/json-schema-to-grammar.h index b928c250bbef..b948743997ff 100644 --- a/common/json-schema-to-grammar.h +++ b/common/json-schema-to-grammar.h @@ -19,5 +19,6 @@ struct common_grammar_options { }; std::string gbnf_format_literal(const std::string & literal); +std::string gbnf_format_rule_name(const std::string & name); std::string build_grammar(const std::function<void(const common_grammar_builder &)> & cb, const common_grammar_options & options = {}); diff --git a/common/json-schema.cpp b/common/json-schema.cpp index 6898840e7d1f..eb57a524a605 100644 --- a/common/json-schema.cpp +++ b/common/json-schema.cpp @@ -9,6 +9,18 @@ #include <utility> #include <vector> +namespace { +struct depth_guard { + int & depth; + depth_guard(int & depth) : depth(depth) { + if (++depth > COMMON_RECURSIVE_LIMIT) { + throw std::invalid_argument("JSON schema is nested more than " + std::to_string(COMMON_RECURSIVE_LIMIT) + " levels deep"); + } + } + ~depth_guard() { depth--; } +}; +} // namespace + class common_chat_schema_builder { const common_json & root_; common_chat_schema_document & doc_; @@ -224,7 +236,14 @@ class common_chat_schema_builder { return node; } + int depth_ = 0; + common_chat_schema_ptr build_node(const common_json & schema, const std::string & path) { + depth_guard guard(depth_); + return build_node_impl(schema, path); + } + + common_chat_schema_ptr build_node_impl(const common_json & schema, const std::string & path) { if (!schema.is_object()) { fail(path, "schema must be an object"); } @@ -365,7 +384,9 @@ static common_chat_schema::value_type json_type(const common_json & value) { return common_chat_schema::TYPE_OBJECT; } -static common_chat_schema::type_set value_types_impl(const common_chat_schema & s, std::unordered_set<const common_chat_schema *> & visited) { +// depth counts the $ref, anyOf and allOf hops, a $ref chain is not bounded by the builder +static common_chat_schema::type_set value_types_impl(const common_chat_schema & s, std::unordered_set<const common_chat_schema *> & visited, int & depth) { + depth_guard guard(depth); switch (s.kind()) { case common_chat_schema::KIND_ANY: return common_chat_schema::type_set::all(); @@ -399,21 +420,21 @@ static common_chat_schema::type_set value_types_impl(const common_chat_schema & // a cycle contributes no type, to be safe return {}; } - auto types = value_types_impl(*target, visited); + auto types = value_types_impl(*target, visited, depth); visited.erase(target); return types; } case common_chat_schema::KIND_ANY_OF: { common_chat_schema::type_set types; for (const auto & child : static_cast<const common_chat_schema_any_of &>(s).children) { - types |= value_types_impl(*child, visited); + types |= value_types_impl(*child, visited, depth); } return types; } case common_chat_schema::KIND_ALL_OF: { auto types = common_chat_schema::type_set::all(); for (const auto & child : static_cast<const common_chat_schema_all_of &>(s).children) { - types &= value_types_impl(*child, visited); + types &= value_types_impl(*child, visited, depth); } return types; } @@ -423,10 +444,12 @@ static common_chat_schema::type_set value_types_impl(const common_chat_schema & common_chat_schema::type_set common_chat_schema::value_types() const { std::unordered_set<const common_chat_schema *> visited; - return value_types_impl(*this, visited); + int depth = 0; + return value_types_impl(*this, visited, depth); } -static bool may_be_string_impl(const common_chat_schema & s, std::unordered_set<const common_chat_schema *> & visited) { +static bool may_be_string_impl(const common_chat_schema & s, std::unordered_set<const common_chat_schema *> & visited, int & depth) { + depth_guard guard(depth); switch (s.kind()) { case common_chat_schema::KIND_STRING: return true; @@ -445,13 +468,13 @@ static bool may_be_string_impl(const common_chat_schema & s, std::unordered_set< if (!target || !visited.insert(target).second) { return false; } - bool result = may_be_string_impl(*target, visited); + bool result = may_be_string_impl(*target, visited, depth); visited.erase(target); return result; } case common_chat_schema::KIND_ANY_OF: for (const auto & child : static_cast<const common_chat_schema_any_of &>(s).children) { - if (may_be_string_impl(*child, visited)) { + if (may_be_string_impl(*child, visited, depth)) { return true; } } @@ -463,7 +486,7 @@ static bool may_be_string_impl(const common_chat_schema & s, std::unordered_set< if (child->kind() == common_chat_schema::KIND_ANY) { continue; } - if (!may_be_string_impl(*child, visited)) { + if (!may_be_string_impl(*child, visited, depth)) { return false; } any_string = true; @@ -477,7 +500,8 @@ static bool may_be_string_impl(const common_chat_schema & s, std::unordered_set< bool common_chat_schema::may_be_string() const { std::unordered_set<const common_chat_schema *> visited; - return may_be_string_impl(*this, visited); + int depth = 0; + return may_be_string_impl(*this, visited, depth); } const char * common_chat_schema::kind_name(node_kind kind) { diff --git a/common/ngram-cache.cpp b/common/ngram-cache.cpp index dce54b364749..419a0ebc9833 100644 --- a/common/ngram-cache.cpp +++ b/common/ngram-cache.cpp @@ -68,7 +68,7 @@ static llama_token try_draft(common_ngram_cache & nc_static, const common_ngram if (part_static_it == nc_static.end()) { return LLAMA_TOKEN_NULL; } - const common_ngram_cache_part part_static = part_static_it->second; + const common_ngram_cache_part & part_static = part_static_it->second; int max_count_static = 0; int sum_count_static = 0; @@ -96,7 +96,7 @@ static llama_token try_draft(common_ngram_cache & nc_static, const common_ngram // Try to draft a token from primary cache (context/dynamic), validate with static cache: static llama_token try_draft( - common_ngram_cache & nc_primary, const std::vector<common_ngram> & ngrams_primary, common_ngram_cache_part & part_static, + common_ngram_cache & nc_primary, const std::vector<common_ngram> & ngrams_primary, const common_ngram_cache_part & part_static, const int * min_sample_size, const int * min_percent) { llama_token drafted_token = LLAMA_TOKEN_NULL; @@ -108,7 +108,7 @@ static llama_token try_draft( if (part_primary_it == nc_primary.end()) { continue; } - const common_ngram_cache_part part_primary = part_primary_it->second; + const common_ngram_cache_part & part_primary = part_primary_it->second; int max_count_primary = 0; int max_count_static = 0; @@ -118,7 +118,7 @@ static llama_token try_draft( for (std::pair<llama_token, int> token_count_primary : part_primary) { const llama_token token = token_count_primary.first; - common_ngram_cache_part::iterator token_count_static_it = part_static.find(token); + common_ngram_cache_part::const_iterator token_count_static_it = part_static.find(token); const int32_t count_primary = token_count_primary.second; const int32_t count_static = token_count_static_it != part_static.end() ? 100*token_count_static_it->second : 1; @@ -162,11 +162,9 @@ void common_ngram_cache_draft( for (int j = ngram_start_static; j < ngram_start_static + LLAMA_NGRAM_STATIC; ++j) { ngram_static.tokens[j-ngram_start_static] = get_token(inp, draft, j); } - common_ngram_cache::iterator part_static_it = nc_static.find(ngram_static); - common_ngram_cache_part part_static; - if (part_static_it != nc_static.end()) { - part_static = part_static_it->second; - } + static const common_ngram_cache_part part_static_empty; + common_ngram_cache::const_iterator part_static_it = nc_static.find(ngram_static); + const common_ngram_cache_part & part_static = part_static_it != nc_static.end() ? part_static_it->second : part_static_empty; // cd = context + dynamic std::vector<common_ngram> ngrams_cd; diff --git a/common/parsers/deepseek.cpp b/common/parsers/deepseek.cpp index 7ee38ce6df74..dac180715a52 100644 --- a/common/parsers/deepseek.cpp +++ b/common/parsers/deepseek.cpp @@ -1,4 +1,5 @@ #include "parsers.h" +#include "log.h" // The DeepSeek V4 reference implementation renders consecutive tool results into a single // user block, ordered by the tool call order of the preceding assistant message (matched @@ -75,13 +76,30 @@ common_chat_params common_chat_params_init_deepseek_v3_2(const common_chat_templ // non-thinking generation prompt ends with a bare </think> instead of an empty // <think></think> pair. const bool is_v4 = tmpl.source().find("function_calls") == std::string::npos; + // V4.1: DSML tag names carry a leading space, e.g. <｜DSML｜ calls> + const bool is_v41 = is_v4 && tmpl.source().find("｜DSML｜ calls>") != std::string::npos; std::optional<json> adjusted_messages; if (is_v4) { adjusted_messages = deepseek_v4_sort_tool_results(inputs.messages); } - auto has_tools = inputs.tools.is_array() && !inputs.tools.empty(); + // V4.1 can declare tools on a system message instead of top-level "tools": parse calls to those too. + json tools = inputs.tools; + if (is_v41 && !(tools.is_array() && !tools.empty()) && inputs.messages.is_array()) { + for (const auto & msg : inputs.messages) { + if (msg.value("role", "") == "system" && msg.contains("tools") && msg.at("tools").is_array()) { + if (!tools.is_array()) { + tools = json::array(); + } + for (const auto & tool : msg.at("tools")) { + tools.push_back(tool); + } + } + } + } + + auto has_tools = tools.is_array() && !tools.empty(); auto has_response_format = !inputs.json_schema.is_null() && inputs.json_schema.is_object(); auto extract_reasoning = inputs.reasoning_format != COMMON_REASONING_FORMAT_NONE; auto include_grammar = has_response_format || (has_tools && inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_NONE); @@ -90,17 +108,39 @@ common_chat_params common_chat_params_init_deepseek_v3_2(const common_chat_templ if (is_v4 && has_response_format) { additional_context = json{ { "response_format", inputs.json_schema } }; } + // V4.1 raises on anything but low/high/max or 1-100: map minimal -> low, xhigh -> max, medium -> default + if (is_v41 && inputs.extra_context.is_object() && inputs.extra_context.contains("reasoning_effort") && + inputs.extra_context.at("reasoning_effort").is_string()) { + const std::string effort = inputs.extra_context.at("reasoning_effort").get<std::string>(); + json mapped; + if (effort == "minimal") { + mapped = "low"; + } else if (effort == "xhigh") { + mapped = "max"; + } else if (effort == "medium") { + mapped = nullptr; + } + if (effort == "minimal" || effort == "xhigh" || effort == "medium") { + LOG_DBG("%s: DeepSeek V4.1 reasoning_effort '%s' -> %s\n", __func__, effort.c_str(), + mapped.is_null() ? "unset (template default)" : mapped.get<std::string>().c_str()); + if (!additional_context.has_value()) { + additional_context = json::object(); + } + (*additional_context)["reasoning_effort"] = mapped; + } + } const std::string DSML = "｜DSML｜"; const std::string THINK_START = "<think>"; const std::string THINK_END = "</think>"; - const std::string TC_BLOCK = is_v4 ? "tool_calls" : "function_calls"; - const std::string FC_START = "<" + DSML + TC_BLOCK + ">"; - const std::string FC_END = "</" + DSML + TC_BLOCK + ">"; - const std::string INVOKE_START = "<" + DSML + "invoke"; - const std::string INVOKE_END = "</" + DSML + "invoke>"; - const std::string PARAM_START = "<" + DSML + "parameter"; - const std::string PARAM_END = "</" + DSML + "parameter>"; + const std::string TAG_SP = is_v41 ? " " : ""; + const std::string TC_BLOCK = is_v41 ? "calls" : is_v4 ? "tool_calls" : "function_calls"; + const std::string FC_START = "<" + DSML + TAG_SP + TC_BLOCK + ">"; + const std::string FC_END = "</" + DSML + TAG_SP + TC_BLOCK + ">"; + const std::string INVOKE_START = "<" + DSML + TAG_SP + "invoke"; + const std::string INVOKE_END = "</" + DSML + TAG_SP + "invoke>"; + const std::string PARAM_START = "<" + DSML + TAG_SP + "parameter"; + const std::string PARAM_END = "</" + DSML + TAG_SP + "parameter>"; const std::string GEN_PROMPT = "<｜Assistant｜>"; const std::string TC_SEPARATOR = "\n\n"; @@ -152,7 +192,7 @@ common_chat_params common_chat_params_init_deepseek_v3_2(const common_chat_templ // build tool call section first since we might need it in reasoning auto tool_choice = p.choice(); if (has_tool_calls) { - foreach_function(inputs.tools, [&](size_t tool_index, const json & tool) { + foreach_function(tools, [&](size_t tool_index, const json & tool) { const auto & function = tool.at("function"); std::string name = function.at("name"); @@ -223,7 +263,10 @@ common_chat_params common_chat_params_init_deepseek_v3_2(const common_chat_templ } if (extract_reasoning && inputs.enable_thinking) { - reasoning = p.optional(THINK_START + p.reasoning(p.until(THINK_END)) + THINK_END); + // V4.1 renders a continuation without reasoning as "<｜Assistant｜></think>" even in thinking mode, + // so consume the bare THINK_END too or it leaks into the content + reasoning = is_v41 ? p.optional((THINK_START + p.reasoning(p.until(THINK_END)) + THINK_END) | p.literal(THINK_END)) + : p.optional(THINK_START + p.reasoning(p.until(THINK_END)) + THINK_END); reasoning_with_tc = THINK_START + p.reasoning(p.until_one_of({ TC_SEPARATOR + FC_START, FC_START, THINK_END })) + p.space() + obligatory_tool_calls; diff --git a/common/parsers/harmony-xml.cpp b/common/parsers/harmony-xml.cpp new file mode 100644 index 000000000000..bf05fac5d680 --- /dev/null +++ b/common/parsers/harmony-xml.cpp @@ -0,0 +1,207 @@ +#include "parsers.h" + +// Harmony with XML tool calls: <|start|>assistant to=NAME<|channel|>analysis <|constrain|>xml<|message|><rfl:parameter name="KEY">\nVALUE\n</rfl:parameter> +common_chat_params common_chat_params_init_harmony_xml(const common_chat_template & tmpl, + const autoparser::generation_params & inputs) { + common_chat_params data; + + data.prompt = common_chat_template_direct_apply_impl(tmpl, inputs); + data.generation_prompt = common_chat_template_generation_prompt_impl(tmpl, inputs); + data.message_delimiters = { + { COMMON_CHAT_ROLE_ASSISTANT, "<|start|>assistant" }, + { COMMON_CHAT_ROLE_USER, "<|start|>user" }, + { COMMON_CHAT_ROLE_SYSTEM, "<|start|>developer" }, + { COMMON_CHAT_ROLE_SYSTEM, "<|start|>system" }, + }; + + data.format = COMMON_CHAT_FORMAT_PEG_NATIVE; + data.supports_thinking = true; + + data.thinking_start_tag = "<|channel|>analysis<|message|>"; + data.thinking_end_tags = {"<|end|>"}; + + // EOG text must reach the parser: an XML call has no closing tag of its own + static const std::vector<std::string> EOG = { + "<|call|>", "<|return|>", "<|endoftext|>", "<|im_end|>", "<|fim_pad|>", "<|repo_name|>", "<|file_sep|>", + }; + + data.preserved_tokens = { + "<|channel|>", "<|constrain|>", "<|message|>", "<|start|>", "<|end|>", + }; + data.preserved_tokens.insert(data.preserved_tokens.end(), EOG.begin(), EOG.end()); + + if (inputs.has_continuation()) { + const auto & msg = inputs.continue_msg; + + data.generation_prompt = "<|start|>assistant<|channel|>analysis<|message|>" + msg.reasoning_content; + if (inputs.continue_final_message == COMMON_CHAT_CONTINUATION_CONTENT) { + data.generation_prompt += "<|end|><|start|>assistant<|channel|>final<|message|>" + msg.render_content(); + } + + data.prompt.append(data.generation_prompt); + } + + auto has_tools = inputs.tools.is_array() && !inputs.tools.empty(); + auto has_response_format = !inputs.json_schema.is_null() && inputs.json_schema.is_object(); + auto include_grammar = has_response_format || (has_tools && inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_NONE); + auto extract_reasoning = inputs.reasoning_format != COMMON_REASONING_FORMAT_NONE; + + static const std::string PARAM_OPEN = "<rfl:parameter name=\""; + static const std::string PARAM_CLOSE = "\n</rfl:parameter>"; + + data.parser = build_chat_peg_parser([&](common_chat_peg_builder & p) { + auto start = p.rule("start", p.literal("<|start|>assistant")); + + auto eog = p.choice(); + for (const auto & tok : EOG) { + eog |= p.literal(tok); + } + auto with_eog = [&](std::vector<std::string> delims) { + delims.insert(delims.end(), EOG.begin(), EOG.end()); + return delims; + }; + + auto analysis_open = p.literal("<|channel|>analysis<|message|>"); + auto analysis_body = p.until_one_of(with_eog({ "<|end|>", "<|constrain|><|start|>assistant", "<|start|>assistant" })); + auto analysis_close = p.optional(p.literal("<|end|>") | p.literal("<|constrain|>") | eog); + if (extract_reasoning) { + p.rule("analysis", analysis_open + p.reasoning(analysis_body) + analysis_close); + } else { + p.rule("analysis", p.atomic(p.content(analysis_open)) + p.content(analysis_body + analysis_close)); + } + auto analysis = p.ref("analysis"); + + auto final_msg = p.rule("final", + p.literal("<|channel|>final<|message|>") + + p.content(p.until_one_of(with_eog({ "<|end|>" }))) + + p.optional(p.literal("<|end|>") | eog)); + + if (has_response_format) { + auto constrain_type = p.chars("[A-Za-z0-9_-]", 1, -1); + auto constraint = p.optional(p.space() + p.optional(p.literal("<|constrain|>")) + constrain_type); + auto response_format = p.rule("response-format", + p.literal("<|channel|>final") + constraint + p.literal("<|message|>") + + p.content(p.schema(p.json(), "response-format-schema", inputs.json_schema)) + + p.optional(p.literal("<|end|>") | eog)); + + return start + p.zero_or_more(analysis + start) + response_format; + } + + if (has_tools && inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_NONE) { + // tolerate a missing closing tag + std::vector<std::string> value_ends = with_eog({ PARAM_OPEN, "<|end|>" }); + std::vector<std::string> string_ends = { PARAM_CLOSE }; + auto next_open = p.choice(); + for (const auto & e : value_ends) { + string_ends.push_back("\n" + e); + next_open |= p.literal(e); + } + auto arg_close = p.tool_arg_close(p.gbnf( + p.literal(PARAM_CLOSE) | (p.literal("\n") + p.peek(p.optional(p.literal("\n")) + next_open)), + gbnf_format_literal("\n") + " " + gbnf_format_literal(PARAM_CLOSE.substr(1)) + "?")); + auto arg_string = p.rule("rfl-arg-string", + p.ac(p.tool_arg_string_value(p.until_one_of(string_ends)) + arg_close, PARAM_CLOSE)); + auto arg_sep = p.optional(p.literal("\n")); + + std::string call_close_gbnf = gbnf_format_literal("<|end|>"); + for (const auto & tok : EOG) { + call_close_gbnf += " | " + gbnf_format_literal(tok); + } + auto call_close = p.gbnf(p.literal("<|end|>") | eog | p.peek(p.literal("<|start|>assistant")), + "(" + call_close_gbnf + ")?"); + + auto tool_choice = p.choice(); + foreach_function(inputs.tools, [&](size_t tool_index, const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + + std::vector<common_peg_parser> arg_rules; + foreach_parameter(function, [&](size_t param_index, const common_chat_schema_property & param, const common_chat_schema_document_ptr & doc) { + auto rule_name = "tool-" + std::to_string(tool_index) + "-arg-" + std::to_string(param_index); + auto arg_open = p.tool_arg_open(p.literal(PARAM_OPEN) + p.tool_arg_name(p.literal(param.name)) + p.literal("\">\n")); + + auto types = param.schema->value_types(); + auto arg_value = p.eps(); + if (!types.has(common_chat_schema::TYPE_STRING) && + (types.has(common_chat_schema::TYPE_OBJECT) || types.has(common_chat_schema::TYPE_ARRAY))) { + // the schema grammar fixes the key order, and the model writes keys in its own order + arg_value = p.tool_arg_json_value(p.json()) + arg_close; + } else if (!types.has(common_chat_schema::TYPE_STRING)) { + arg_value = p.tool_arg_json_value(p.schema(p.json(), rule_name + "-schema", doc, *param.schema)) + arg_close; + } else if (types.is_only(common_chat_schema::TYPE_STRING)) { + arg_value = arg_string; + } else { + // grammar keeps only the string rule; the parser tries JSON first to type the value + auto json_value = p.choice(); + if (types.has(common_chat_schema::TYPE_OBJECT)) { + json_value |= p.json_object(); + } + if (types.has(common_chat_schema::TYPE_ARRAY)) { + json_value |= p.json_array(); + } + if (types.has(common_chat_schema::TYPE_NUMBER) || types.has(common_chat_schema::TYPE_INTEGER)) { + json_value |= p.json_number(); + } + if (types.has(common_chat_schema::TYPE_BOOLEAN)) { + json_value |= p.json_bool(); + } + if (types.has(common_chat_schema::TYPE_NULL)) { + json_value |= p.json_null(); + } + arg_value = p.gbnf(p.atomic(p.tool_arg_json_value(json_value) + arg_close) | arg_string, "rfl-arg-string"); + } + + arg_rules.push_back(p.rule(rule_name, p.tool_arg(arg_open + arg_value))); + }); + + if (arg_rules.empty()) { + auto any_name = p.chars("[^\"\\n<]", 1, -1); + arg_rules.push_back(p.rule("tool-" + std::to_string(tool_index) + "-arg-any", + p.tool_arg(p.tool_arg_open(p.literal(PARAM_OPEN) + p.tool_arg_name(any_name) + p.literal("\">\n")) + arg_string))); + } + + auto args = p.zero_or_more(p.choice(arg_rules) + arg_sep); + + auto call = p.tool( + p.tool_open(p.literal(" to=") + p.tool_name(p.literal(name)) + + p.literal("<|channel|>analysis <|constrain|>xml<|message|>")) + + p.tool_args(args) + + p.tool_close(call_close)); + + tool_choice |= p.rule("tool-" + std::to_string(tool_index), call); + }); + + auto tool_calls = inputs.parallel_tool_calls + ? tool_choice + p.zero_or_more(start + tool_choice) + : tool_choice; + auto tool_call = p.trigger_rule("tool-call", tool_calls); + + if (inputs.tool_choice == COMMON_CHAT_TOOL_CHOICE_REQUIRED) { + return start + p.zero_or_more(analysis + start) + tool_call; + } + + return start + p.zero_or_more(analysis + start) + (tool_call | final_msg | p.content(p.rest())); + } + + auto unsolicited = p.rule("unsolicited", p.atomic(p.literal(" to=") + p.rest())); + + // output without a channel header is returned as content instead of failing the request + return start + p.zero_or_more(analysis + start) + (final_msg | unsolicited | p.content(p.rest())); + }); + + if (include_grammar) { + data.grammar_lazy = !(has_response_format || (has_tools && inputs.tool_choice == COMMON_CHAT_TOOL_CHOICE_REQUIRED)); + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + data.parser.build_grammar(builder, data.grammar_lazy); + }); + + if (data.grammar_lazy) { + data.grammar_triggers = { + { COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, "^\\s+to$" }, + { COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, "<\\|start\\|>assistant(\\s+to)" }, + }; + } + } + + return data; +} diff --git a/common/parsers/muse-spark.cpp b/common/parsers/muse-spark.cpp new file mode 100644 index 000000000000..577090aa5cc9 --- /dev/null +++ b/common/parsers/muse-spark.cpp @@ -0,0 +1,146 @@ +#include "parsers.h" + +// An assistant turn is rendered as one or more messages, each +// "<|start|>assistant to=<recipient><|message|>{content}{END}" where END is +// <|eom|> (more messages follow) or <|eot|> (end of turn): +// - chain-of-thought: to=self, terminated by <|eom|> +// - user facing aside: to=commentary, terminated by <|eom|> +// - final answer: to=user, terminated by <|eot|> +// A commentary message carries content the user sees while the assistant keeps +// working, typically before or between tool calls. +// The generation prompt is just "<|start|>assistant"; the model emits its own +// " to=...<|message|>". +common_chat_params common_chat_params_init_muse_spark(const common_chat_template & tmpl, + const autoparser::generation_params & inputs) { + common_chat_params data; + + data.prompt = common_chat_template_direct_apply_impl(tmpl, inputs); + data.generation_prompt = "<|start|>assistant"; + data.format = COMMON_CHAT_FORMAT_PEG_NATIVE; + data.supports_thinking = true; + + data.preserved_tokens = { + "<|start|>", "<|message|>", "<|eom|>", "<|eot|>", + // ATEM tool-call markup emitted on " to=<tool>" turns. + "<atem:function_calls>", "<atem:invoke", "<atem:parameter", "</atem:parameter>", + "</atem:invoke>", "</atem:function_calls>", + }; + + data.message_delimiters = { + { COMMON_CHAT_ROLE_ASSISTANT, "<|start|>assistant" }, + { COMMON_CHAT_ROLE_USER, "<|start|>user" }, + { COMMON_CHAT_ROLE_SYSTEM, "<|start|>system" }, + { COMMON_CHAT_ROLE_TOOL, "<|start|>tool" }, + }; + + if (inputs.has_continuation()) { + const auto & msg = inputs.continue_msg; + + data.generation_prompt = "<|start|>assistant to=self<|message|>" + msg.reasoning_content; + if (inputs.continue_final_message == COMMON_CHAT_CONTINUATION_CONTENT) { + data.generation_prompt += "<|eom|><|start|>assistant to=user<|message|>" + msg.render_content(); + } + + data.prompt.append(data.generation_prompt); + } + + auto extract_reasoning = inputs.reasoning_format != COMMON_REASONING_FORMAT_NONE; + + auto has_tools = inputs.tools.is_array() && !inputs.tools.empty(); + // Constrained grammar whenever tools are offered. + auto include_grammar = has_tools && inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_NONE; + + data.parser = build_chat_peg_parser([&](common_chat_peg_builder & p) { + auto start = p.rule("start", p.literal("<|start|>assistant")); + + if (!extract_reasoning && !include_grammar) { + return start + p.content(p.rest()); + } + + if (extract_reasoning) { + p.rule("analysis", p.literal(" to=self<|message|>") + p.reasoning(p.until("<|eom|>")) + p.literal("<|eom|>")); + } else { + p.rule("analysis", p.literal(" to=self<|message|>") + p.content(p.until("<|eom|>")) + p.literal("<|eom|>")); + } + auto analysis = p.ref("analysis"); + + // Commentary is user facing content emitted mid turn, so it reads as + // content and always ends on <|eom|>. + auto preamble = p.rule("preamble", p.literal(" to=commentary<|message|>") + + p.content(p.until("<|eom|>")) + p.literal("<|eom|>")); + + auto aside = p.rule("aside", analysis | preamble); + + auto recipient = p.optional(p.literal(" to=user")); + auto final_msg = p.rule("final", recipient + p.literal("<|message|>") + + p.content(p.until_one_of({ "<|eot|>", "<|eom|>" }))); + + if (has_tools && inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_NONE) { + auto string_value = p.ac( + p.tool_arg_string_value(p.until("</atem:parameter>")) + p.tool_arg_close(p.literal("</atem:parameter>")), + "</atem:parameter>"); + + auto tool_choice = p.choice(); + foreach_function(inputs.tools, [&](size_t tool_index, const json & tool) { + const auto & function = tool.at("function"); + const std::string name = function.at("name"); + + std::vector<common_peg_parser> arg_rules; + foreach_parameter(function, [&](size_t param_index, const common_chat_schema_property & prop, const common_chat_schema_document_ptr & doc) { + auto value_parser = p.eps(); + if (prop.schema->may_be_string()) { + value_parser = string_value; + } else { + value_parser = p.tool_arg_json_value( + p.schema(p.json(), "tool-" + std::to_string(tool_index) + "-arg-" + std::to_string(param_index) + "-schema", doc, *prop.schema)) + + p.tool_arg_close(p.literal("</atem:parameter>")); + } + + arg_rules.push_back(p.tool_arg( + p.tool_arg_open(p.literal("<atem:parameter name=\"") + p.tool_arg_name(p.literal(prop.name)) + p.literal("\">")) + + value_parser)); + }); + + auto args = p.eps(); + if (!arg_rules.empty()) { + args = p.zero_or_more(p.choice(arg_rules) + p.space()); + } + + auto tool_parser = p.tool( + p.tool_open(p.literal(" to=") + p.until("<|message|>") + + p.literal("<|message|><atem:function_calls>") + p.space() + + p.literal("<atem:invoke name=\"") + p.tool_name(p.literal(name)) + p.literal("\">") + p.space()) + << p.tool_args(args) + << p.tool_close(p.literal("</atem:invoke>") + p.space() + p.literal("</atem:function_calls>"))); + + tool_choice |= p.rule("tool-" + std::to_string(tool_index), tool_parser); + }); + + auto tool_calls = inputs.parallel_tool_calls + ? p.trigger_rule("tool-call", tool_choice + p.zero_or_more(p.literal("<|eom|>") + start + tool_choice)) + : p.trigger_rule("tool-call", tool_choice); + + + if (inputs.tool_choice == COMMON_CHAT_TOOL_CHOICE_REQUIRED) { + return p.zero_or_more(start + aside) + start + tool_calls; + } + auto trailing_calls = p.optional(p.literal("<|eom|>") + start + tool_calls); + return p.zero_or_more(start + aside) + start + (tool_calls | (final_msg + trailing_calls)); + } + + return p.zero_or_more(start + aside) + start + final_msg; + }); + + if (include_grammar) { + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + data.parser.build_grammar(builder, data.grammar_lazy); + }); + data.grammar_triggers = { + { COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, + "<\\|start\\|>assistant( to=(?!self<\\|message\\|>)(?!commentary<\\|message\\|>)(?!user<\\|message\\|>)[^<]*?<\\|message\\|>)" }, + }; + } + + return data; +} diff --git a/common/parsers/parsers.h b/common/parsers/parsers.h index 8f0a97ce3446..532a44f014fe 100644 --- a/common/parsers/parsers.h +++ b/common/parsers/parsers.h @@ -59,6 +59,8 @@ common_chat_params common_chat_params_init_gigachat_v3(const common_chat_templat common_chat_params common_chat_params_init_gpt_oss(const common_chat_template & tmpl, const autoparser::generation_params & inputs); +common_chat_params common_chat_params_init_harmony_xml(const common_chat_template & tmpl, const autoparser::generation_params & inputs); + common_chat_params common_chat_params_init_k2_horizon(const common_chat_template & tmpl, const autoparser::generation_params & inputs); common_chat_params common_chat_params_init_kimi_k2(const common_chat_template & tmpl, const autoparser::generation_params & inputs); @@ -79,6 +81,7 @@ common_chat_params common_chat_params_init_minimax_m3(const common_chat_template common_chat_params common_chat_params_init_ministral_3(const common_chat_template & tmpl, const autoparser::generation_params & inputs); common_chat_params common_chat_params_init_muse_glimmer(const common_chat_template & tmpl, const autoparser::generation_params & inputs); +common_chat_params common_chat_params_init_muse_spark(const common_chat_template & tmpl, const autoparser::generation_params & inputs); common_chat_params common_chat_params_init_qwen3_coder(const common_chat_template & tmpl, const autoparser::generation_params & inputs); diff --git a/common/parsers/qwen3-coder.cpp b/common/parsers/qwen3-coder.cpp index abed169742d8..a68a6835e94b 100644 --- a/common/parsers/qwen3-coder.cpp +++ b/common/parsers/qwen3-coder.cpp @@ -74,15 +74,24 @@ common_chat_params common_chat_params_init_qwen3_coder(const common_chat_templat data.parser = build_chat_peg_parser([&](common_chat_peg_builder & p) { auto generation_prompt = p.literal(GEN_PREFIX); + // The template strips the newline before </think>, so leave it out of the reasoning + auto think_body = p.until_one_of({ "\n</think>", "</think>", "<tool_call>" }); + auto think_close = p.literal("\n</think>") | p.literal("</think>") | p.peek(p.literal("<tool_call>")); + + auto reasoning_extracted = p.optional("<think>" + p.space() + p.reasoning(think_body) + think_close); + auto reasoning_skipped = p.optional("<think>" + p.space() + think_body + think_close); + auto reasoning = p.eps(); if (supports_reasoning && extract_reasoning) { - reasoning = p.optional("<think>" + p.space() + - p.reasoning(p.until_one_of({ "</think>", "<tool_call>" })) + - (p.literal("</think>") | p.peek(p.literal("<tool_call>")))); + reasoning = reasoning_extracted; } // Response format parser if (has_response_format) { + // The answer must be bare JSON, so the think block is consumed even when it is not extracted + if (supports_reasoning && !extract_reasoning) { + reasoning = reasoning_skipped; + } return generation_prompt + (reasoning << p.content(p.schema(p.json(), "response-format", inputs.json_schema))); } @@ -166,8 +175,15 @@ common_chat_params common_chat_params_init_qwen3_coder(const common_chat_templat auto calls = inputs.parallel_tool_calls ? tool_call_first + p.zero_or_more(tool_call) : tool_call_first; auto tool_calls = p.trigger_rule("tool-call-root", p.repeat(calls, min_calls, 1)); + // The templates separate content from the tool calls with one or two newlines, + // stop the content before them + std::vector<std::string> content_ends; + for (const auto & start : tool_call_starts) { + content_ends.insert(content_ends.end(), { "\n\n" + start, "\n" + start, start }); + } + return generation_prompt + - (reasoning << p.content(p.until_one_of(tool_call_starts)) << tool_calls); + (reasoning << p.content(p.until_one_of(content_ends)) << tool_calls); } // Content only parser diff --git a/common/parsers/sources.cmake b/common/parsers/sources.cmake index 152397074d22..2174f4519a64 100644 --- a/common/parsers/sources.cmake +++ b/common/parsers/sources.cmake @@ -9,6 +9,7 @@ set(LLAMA_CHAT_PARSERS_SOURCES ${CMAKE_CURRENT_LIST_DIR}/gemma4.cpp ${CMAKE_CURRENT_LIST_DIR}/gigachat-v3.cpp ${CMAKE_CURRENT_LIST_DIR}/gpt-oss.cpp + ${CMAKE_CURRENT_LIST_DIR}/harmony-xml.cpp ${CMAKE_CURRENT_LIST_DIR}/k2-horizon.cpp ${CMAKE_CURRENT_LIST_DIR}/kimi-k2.cpp ${CMAKE_CURRENT_LIST_DIR}/kimi-k3.cpp @@ -19,6 +20,7 @@ set(LLAMA_CHAT_PARSERS_SOURCES ${CMAKE_CURRENT_LIST_DIR}/minimax-m3.cpp ${CMAKE_CURRENT_LIST_DIR}/ministral3.cpp ${CMAKE_CURRENT_LIST_DIR}/muse-glimmer.cpp + ${CMAKE_CURRENT_LIST_DIR}/muse-spark.cpp ${CMAKE_CURRENT_LIST_DIR}/qwen3-coder.cpp ${CMAKE_CURRENT_LIST_DIR}/translate-gemma.cpp ) diff --git a/common/peg-parser.cpp b/common/peg-parser.cpp index 8033f7e81530..e2ccb77bb14f 100644 --- a/common/peg-parser.cpp +++ b/common/peg-parser.cpp @@ -10,10 +10,12 @@ #include <initializer_list> #include <map> #include <memory> -#include <regex> #include <set> #include <stdexcept> +// The parser can run with a lower limit than COMMON_RECURSIVE_LIMIT +static constexpr int RULE_RECURSIVE_LIMIT = 64; + // Trick to catch missing branches template <typename T> inline constexpr bool is_always_false_v = false; @@ -186,13 +188,17 @@ std::string common_peg_ast_node::sanitized_text() const { } void common_peg_ast_arena::visit(common_peg_ast_id id, const common_peg_ast_visitor & visitor) const { - if (id == COMMON_PEG_INVALID_AST_ID) { - return; - } - const auto & node = get(id); - visitor(node); - for (const auto & child : node.children) { - visit(child, visitor); + // no recursion: the AST is several nodes deep per level of the input + std::vector<common_peg_ast_id> stack = { id }; + while (!stack.empty()) { + const auto cur = stack.back(); + stack.pop_back(); + if (cur == COMMON_PEG_INVALID_AST_ID) { + continue; + } + const auto & node = get(cur); + visitor(node); + stack.insert(stack.end(), node.children.rbegin(), node.children.rend()); } } @@ -715,8 +721,9 @@ struct parser_executor { return common_peg_parse_result(COMMON_PEG_PARSE_RESULT_SUCCESS, start_pos, pos, {}, std::move(invalid_utf8)); } - if (match == common_trie::PARTIAL_MATCH) { - // Found a partial match extending to end of input, return everything before it + if (match == common_trie::PARTIAL_MATCH && !ctx.is_complete()) { + // Found a partial match extending to end of input, return everything before it. + // On a complete input the delimiter can no longer form, so the bytes belong to the text return common_peg_parse_result(COMMON_PEG_PARSE_RESULT_SUCCESS, start_pos, pos, {}, std::move(invalid_utf8)); } @@ -736,8 +743,15 @@ struct parser_executor { } common_peg_parse_result operator()(const common_peg_rule_parser & p) { + // only rules recurse, a recursive rule is entered once per input level + if (ctx.rule_depth[p.child] >= RULE_RECURSIVE_LIMIT) { + throw common_peg_recursion_error("input is nested more than " + std::to_string(RULE_RECURSIVE_LIMIT) + " levels deep"); + } + // Parse the child + ctx.rule_depth[p.child]++; auto result = arena.parse(p.child, ctx, start_pos); + ctx.rule_depth[p.child]--; if (!result.fail()) { std::string_view text; @@ -819,6 +833,10 @@ common_peg_parse_result common_peg_arena::parse(common_peg_parse_context & ctx, if (root_ == COMMON_PEG_INVALID_PARSER_ID) { throw std::runtime_error("No root parser set"); } + + // Initialize rule depth for all parsers + ctx.rule_depth.assign(parsers_.size(), 0); + return parse(root_, ctx, start); } @@ -1069,11 +1087,6 @@ common_peg_parser operator|(const std::string & str, const common_peg_parser & p return operator|(str.c_str(), p); } -static std::string rule_name(const std::string & name) { - static const std::regex invalid_rule_chars_re("[^a-zA-Z0-9-]+"); - return std::regex_replace(name, invalid_rule_chars_re, "-"); -} - common_peg_parser_builder::common_peg_parser_builder() {} common_peg_parser common_peg_parser_builder::sequence(const std::vector<common_peg_parser_id> & parsers) { @@ -1155,14 +1168,14 @@ common_peg_parser common_peg_parser_builder::schema(const common_peg_parser & p, } common_peg_parser common_peg_parser_builder::rule(const std::string & name, const common_peg_parser & p, bool trigger) { - auto clean_name = rule_name(name); + auto clean_name = gbnf_format_rule_name(name); auto rule_id = arena_.add_parser(common_peg_rule_parser{clean_name, p.id(), trigger}); arena_.add_rule(clean_name, rule_id); return ref(clean_name); } common_peg_parser common_peg_parser_builder::rule(const std::string & name, const std::function<common_peg_parser()> & builder_fn, bool trigger) { - auto clean_name = rule_name(name); + auto clean_name = gbnf_format_rule_name(name); if (arena_.has_rule(clean_name)) { return ref(clean_name); } diff --git a/common/peg-parser.h b/common/peg-parser.h index 9255d6eb975f..46df99875d35 100644 --- a/common/peg-parser.h +++ b/common/peg-parser.h @@ -6,6 +6,7 @@ #include <memory> #include <set> +#include <stdexcept> #include <unordered_map> #include <string> #include <string_view> @@ -161,9 +162,10 @@ struct common_peg_parse_result { }; enum common_peg_parse_flags { - COMMON_PEG_PARSE_FLAG_NONE = 0, - COMMON_PEG_PARSE_FLAG_LENIENT = 1 << 0, - COMMON_PEG_PARSE_FLAG_DEBUG = 1 << 1, + COMMON_PEG_PARSE_FLAG_NONE = 0, + COMMON_PEG_PARSE_FLAG_LENIENT = 1 << 0, + COMMON_PEG_PARSE_FLAG_DEBUG = 1 << 1, + COMMON_PEG_PARSE_FLAG_COMPLETE = 1 << 2, }; inline common_peg_parse_flags operator|(common_peg_parse_flags a, common_peg_parse_flags b) { @@ -182,6 +184,10 @@ inline common_peg_parse_flags operator~(common_peg_parse_flags a) { return static_cast<common_peg_parse_flags>(~int(a)); } +struct common_peg_recursion_error : std::invalid_argument { + using std::invalid_argument::invalid_argument; +}; + struct common_peg_parse_context { std::string input; // [h, e, l, l, o, _, w, o, r, l, d] std::vector<llama_token> tokens; // [id, -1, -1, -1, -1, id, -1, -1, -1, -1, -1] @@ -189,6 +195,7 @@ struct common_peg_parse_context { common_peg_ast_arena ast; int parse_depth; + std::vector<int> rule_depth; // index: rule child id common_peg_parse_context(common_peg_parse_flags flags = COMMON_PEG_PARSE_FLAG_NONE) : flags(flags), parse_depth(0) {} @@ -203,6 +210,7 @@ struct common_peg_parse_context { bool is_lenient() const { return flags & COMMON_PEG_PARSE_FLAG_LENIENT; } bool is_debug() const { return flags & COMMON_PEG_PARSE_FLAG_DEBUG; } + bool is_complete() const { return flags & COMMON_PEG_PARSE_FLAG_COMPLETE; } }; class common_peg_arena; diff --git a/common/preset.cpp b/common/preset.cpp index 14d51809d363..31a8bd5131e4 100644 --- a/common/preset.cpp +++ b/common/preset.cpp @@ -171,12 +171,12 @@ static std::map<std::string, std::map<std::string, std::string>> parse_ini_from_ std::map<std::string, std::map<std::string, std::string>> parsed; if (!std::filesystem::exists(path)) { - throw std::runtime_error("preset file does not exist: " + fs_path_to_utf8(path)); + throw std::runtime_error("preset file does not exist: " + path.string()); } std::ifstream file(path); if (!file.good()) { - throw std::runtime_error("failed to open server preset file: " + fs_path_to_utf8(path)); + throw std::runtime_error("failed to open server preset file: " + path.string()); } std::string contents((std::istreambuf_iterator<char>(file)), std::istreambuf_iterator<char>()); @@ -225,7 +225,7 @@ static std::map<std::string, std::map<std::string, std::string>> parse_ini_from_ common_peg_parse_context ctx(contents); const auto result = parser.parse(ctx); if (!result.success()) { - throw std::runtime_error("failed to parse server config file: " + fs_path_to_utf8(path)); + throw std::runtime_error("failed to parse server config file: " + path.string()); } std::string current_section = COMMON_PRESET_DEFAULT_NAME; @@ -323,7 +323,7 @@ common_presets common_preset_context::load_from_ini(const std::filesystem::path } LOG_DBG("accepted option: %s = %s\n", key.c_str(), preset.options[opt].c_str()); } else if (ignore_unknown_keys) { - LOG_WRN("ignoring option '%s' from %s: not supported by this program\n", key.c_str(), fs_path_to_utf8(path).c_str()); + LOG_WRN("ignoring option '%s' from %s: not supported by this program\n", key.c_str(), path.string().c_str()); } else { throw std::runtime_error(string_format( "option '%s' not recognized in preset '%s'", @@ -401,7 +401,7 @@ common_presets common_preset_context::load_from_models_dir(const std::string & m if (!entry.is_regular_file(ec)) { continue; } - const std::string fname = fs_path_to_utf8(entry.path().filename()); + const std::string fname = entry.path().filename().string(); if (!string_ends_with(fname, ".gguf")) { continue; } @@ -422,9 +422,9 @@ common_presets common_preset_context::load_from_models_dir(const std::string & m if (!path.empty()) { models.push_back({ /* name */ name, - /* path */ fs_path_to_utf8(path), - /* path_mmproj */ fs_path_to_utf8(mmproj_file), // can be empty - /* path_draft */ fs_path_to_utf8(draft_file) // can be empty + /* path */ path.string(), + /* path_mmproj */ mmproj_file.string(), // can be empty + /* path_draft */ draft_file.string() // can be empty }); } }; @@ -432,13 +432,13 @@ common_presets common_preset_context::load_from_models_dir(const std::string & m for (const auto & entry : std::filesystem::directory_iterator(dir)) { std::error_code ec; if (entry.is_directory(ec)) { - scan_subdir(entry.path(), fs_path_to_utf8(entry.path().filename())); + scan_subdir(entry.path(), entry.path().filename().string()); continue; } if (!entry.is_regular_file(ec)) { continue; } - const std::string fname = fs_path_to_utf8(entry.path().filename()); + const std::string fname = entry.path().filename().string(); if (!string_ends_with(fname, ".gguf")) { continue; } @@ -450,7 +450,7 @@ common_presets common_preset_context::load_from_models_dir(const std::string & m string_replace_all(name, ".gguf", ""); models.push_back({ /* name */ name, - /* path */ fs_path_to_utf8(entry.path()), + /* path */ entry.path().string(), /* path_mmproj */ "", /* path_draft */ "" }); diff --git a/common/reasoning-budget.cpp b/common/reasoning-budget.cpp index 4884299f3011..81b7c3e56cdb 100644 --- a/common/reasoning-budget.cpp +++ b/common/reasoning-budget.cpp @@ -136,7 +136,8 @@ static void common_reasoning_budget_accept(struct llama_sampler * smpl, llama_to // track the end sequence within forced_tokens so it is also reported on DONE const int32_t match = ctx->end_matcher.advance(token); ctx->force_pos++; - if (ctx->force_pos >= ctx->forced_tokens.size()) { + // an end tag that is already in the prompt (e.g. "<think></think>") also ends forcing + if (match >= 0 || ctx->force_pos >= ctx->forced_tokens.size()) { ctx->state = REASONING_BUDGET_DONE; ctx->end_match = match; COM_TRC("%s", "forced sequence complete, done\n"); diff --git a/common/speculative.cpp b/common/speculative.cpp index 50647dbb20aa..4305ac6acb41 100644 --- a/common/speculative.cpp +++ b/common/speculative.cpp @@ -16,8 +16,10 @@ #include <cassert> #include <cmath> #include <cstring> +#include <fstream> #include <iomanip> #include <map> +#include <random> #include <cinttypes> #define SPC_DBG(fmt, ...) LOG_DBG("spec %12.*s: " fmt, 12, __func__, __VA_ARGS__) @@ -999,10 +1001,20 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { int32_t block_size = 0; llama_token mask_token_id = 0; + bool is_lilicorr = false; + int32_t lilicorr_top_k = 0; + size_t lilicorr_rows = 0; + std::vector<float> lilicorr_embd; + std::vector<llama_pos> lilicorr_pos; + bool is_dflash2 = false; bool is_mrope = false; int32_t selector_top_k = 0; + // DFlash2 probabilistic drafting: one generator per sequence and the seed it was last seeded with (-1: reseed) + std::vector<std::mt19937> dflash2_rng; + std::vector<int64_t> dflash2_seed; + // draft-dspark: the draft carries a Markov head and uses an anchor-first block layout const bool is_dspark; @@ -1053,6 +1065,18 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { selector_top_k = llama_model_dflash_selector_top_k(model_dft); is_dflash2 = selector_top_k > 0; + dflash2_rng.resize(n_seq); + dflash2_seed.assign(n_seq, -1); + char lilicorr_meta[32] = {}; + lilicorr_top_k = llama_model_meta_val_str(model_dft, "lilicorr.candidate_topk", lilicorr_meta, sizeof(lilicorr_meta)) >= 0 + ? std::atoi(lilicorr_meta) : 0; + is_lilicorr = lilicorr_top_k > 0; + if (is_lilicorr) { + lilicorr_rows = (size_t) block_size + 1; + const size_t lilicorr_slots = (size_t) n_seq * lilicorr_rows; + lilicorr_embd.resize(lilicorr_slots * (size_t) n_embd_dec); + lilicorr_pos.assign(lilicorr_slots, -1); + } mask_token_id = llama_vocab_mask(llama_model_get_vocab(model_dft)); if (is_dspark && this->params.p_min > 0.0f) { @@ -1098,7 +1122,7 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { // offload draft sampling to the backend backend_chains.assign(n_seq, nullptr); - if (this->params.backend_sampling && !is_dflash2) { + if (this->params.backend_sampling && !is_dflash2 && !is_lilicorr) { for (llama_seq_id seq_id = 0; seq_id < (llama_seq_id) n_seq; ++seq_id) { llama_sampler * chain = llama_sampler_chain_init(llama_sampler_chain_default_params()); llama_sampler_chain_add(chain, llama_sampler_init_top_k(10)); @@ -1118,7 +1142,7 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { } // DFlash2 reads its selector lattice from h_nextn and never consumes raw logits. - llama_set_embeddings_nextn(ctx_dft, true, /*masked*/ !is_dflash2); + llama_set_embeddings_nextn(ctx_dft, true, /*masked*/ !is_dflash2 && !is_lilicorr); llama_set_causal_attn(ctx_dft, causal_attn); // DFlash needs non-causal attention unless the model says otherwise } @@ -1141,6 +1165,9 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { return; } + // reseed per request rather than per round, or two identical requests differ + dflash2_seed[seq_id] = -1; + const int32_t N = (int32_t) prompt.size(); if (N <= 0) { return; @@ -1233,6 +1260,24 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { __func__, rc, (int) n_chunk, (int) offset); return false; } + if (is_lilicorr) { + // Ordinary DFlash can write to the KV cache, but LiliCorr needs to store embeddings across sequences. + const float * projected = llama_get_embeddings_nextn(ctx_dft); + if (projected) { + const size_t seq_offset = (size_t) seq_id * lilicorr_rows; + const llama_pos pos_min = std::max(0, batch_inject.tokens.back().pos[0] - block_size); + for (int32_t i = 0; i < n_chunk; ++i) { + const llama_pos pos = batch_inject.tokens[i].pos[0]; + if (pos < pos_min) { + continue; + } + const size_t slot = seq_offset + (size_t) pos % lilicorr_rows; + std::memcpy(lilicorr_embd.data() + slot * (size_t) n_embd_dec, + projected + (size_t) i * n_embd_dec, (size_t) n_embd_dec * sizeof(float)); + lilicorr_pos[slot] = pos; + } + } + } } } @@ -1260,12 +1305,17 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { const int32_t n = (int32_t) dp.pos0; const int32_t n_draft = params.n_max; - - const int32_t n_block_tokens = n_draft + (is_dspark && sample_from_anchor ? 0 : 1); + const int32_t n_block_tokens = is_lilicorr ? block_size : n_draft + (is_dspark && sample_from_anchor ? 0 : 1); i_block_beg[seq_id] = batch.size(); n_block [seq_id] = n_block_tokens; for (int32_t i = 0; i < n_block_tokens; ++i) { - batch.add(i == 0 ? dp.id_last : mask_token_id, n + i, seq_id, !is_dflash2); + const int32_t idx = batch.add(i == 0 ? dp.id_last : mask_token_id, n + i, seq_id, !is_dflash2 && !is_lilicorr); + if (is_lilicorr) { + // For LiliCorr drafting batch, set state embeddings for use in the associated transformer head. + const llama_pos pos = dp.pos0 - 1; + const size_t slot = (size_t) seq_id * lilicorr_rows + (size_t) pos % lilicorr_rows; + batch.set_embd_state(idx, { lilicorr_embd.data() + slot * (size_t) n_embd_dec, 1, (size_t) n_embd_dec }); + } } } @@ -1293,32 +1343,81 @@ struct common_speculative_impl_draft_dflash : public common_speculative_impl { auto & result = *dp.result; - if (is_dflash2) { + if (is_dflash2 || is_lilicorr) { + // Both DFlash and LiliCorr greedily walk the candidate lattice. const float * lattice = llama_get_embeddings_nextn(ctx_dft); GGML_ASSERT(lattice && "DFlash2 selector produced no lattice"); + // DFlash2 can instead sample each step and hand q to the verifier for rejection sampling + const bool sample = is_dflash2 && params.probabilistic && dp.result_q; + + // greedy keeps temperature 1, sampling uses the target's + const float temp = sample ? dp.temp : 1.0f; + + if (sample && dflash2_seed[seq_id] != dp.seed) { + dflash2_seed[seq_id] = dp.seed; + // the default seed means random; mixed so it differs from the target's, as in spec_retune + dflash2_rng[seq_id].seed(dp.seed == LLAMA_DEFAULT_SEED ? std::random_device{}() : dp.seed ^ 0x85ebca6bu); + } + + std::vector<float> probs; + std::vector<int32_t> sorted_idx; + int32_t predecessor = 0; - for (int32_t i = 1; i < n_block_tokens; ++i) { + for (int32_t i = 1; i < (is_dflash2 ? n_block_tokens : params.n_max + 1); ++i) { const float * row = lattice + (size_t) (beg + i) * n_embd_dec; - const float * scores = row + selector_top_k + (size_t) predecessor * selector_top_k; + const int32_t top_k = is_dflash2 ? selector_top_k : lilicorr_top_k; + const float * scores = row + top_k + (size_t) predecessor * top_k; predecessor = (int32_t) std::distance(scores, - std::max_element(scores, scores + selector_top_k)); - if (params.p_min > 0.0f) { - // softmax(scores) at the argmax, i.e. 1 / sum(exp(s_k - s_max)) + std::max_element(scores, scores + top_k)); + if (params.p_min > 0.0f || sample) { + // softmax(scores / temp) at the argmax, i.e. 1 / sum(exp((s_k - s_max) / temp)) + probs.resize(top_k); float sum = 0.0f; - for (int32_t k = 0; k < selector_top_k; ++k) { - sum += std::exp(scores[k] - scores[predecessor]); + for (int32_t k = 0; k < top_k; ++k) { + probs[k] = std::exp((scores[k] - scores[predecessor]) / temp); + sum += probs[k]; } if (1.0f / sum < params.p_min) { break; } + for (int32_t k = 0; k < top_k; ++k) { + probs[k] /= sum; + } + } + if (sample) { + // ggml_top_k leaves candidates unordered, so walk them by token id to keep a seed's draft stable + sorted_idx.resize(top_k); + for (int32_t k = 0; k < top_k; ++k) { + sorted_idx[k] = k; + } + std::sort(sorted_idx.begin(), sorted_idx.end(), [row](int32_t a, int32_t b) { return row[a] < row[b]; }); + + // a round-off overshoot keeps the argmax, which has q > 0 + double u = std::uniform_real_distribution<double>(0.0, 1.0)(dflash2_rng[seq_id]); + for (const int32_t k : sorted_idx) { + u -= probs[k]; + if (u < 0.0) { + predecessor = k; + break; + } + } + + auto & q = dp.result_q->emplace_back(); + q.reserve(top_k); + for (int32_t k = 0; k < top_k; ++k) { + q.push_back({ (llama_token) row[k], scores[k], probs[k] }); + } } result.push_back((llama_token) row[predecessor]); } if (result.size() < (size_t) params.n_min) { result.clear(); + if (sample) { + dp.result_q->clear(); + } } continue; } @@ -2111,9 +2210,6 @@ struct common_speculative_impl_ngram_cache : public common_speculative_impl { uint16_t n_draft; - bool save_dynamic; - bool save_static; - struct seq_info { size_t cache_size = 0; // number of tokens in n-gram cache @@ -2127,54 +2223,72 @@ struct common_speculative_impl_ngram_cache : public common_speculative_impl { common_speculative_impl_ngram_cache( const common_params_speculative & params, uint32_t n_seq, - uint16_t n_draft, - const std::string & path_static, - const std::string & path_dynamic, - bool save_dynamic, - bool save_static) + uint16_t n_draft) : common_speculative_impl(COMMON_SPECULATIVE_TYPE_NGRAM_CACHE, n_seq, n_draft) , params(params.ngram_cache) , n_draft(n_draft) - , save_dynamic(save_dynamic) - , save_static(save_static) { + const auto & ngram = params.ngram_cache; + SPC_TRC("%s", "adding speculative implementation 'ngram-cache'\n"); SPC_TRC("- n_draft=%d, cache_static=%s, cache_dynamic=%s\n", n_draft, - path_static.empty() ? "none" : path_static.c_str(), - path_dynamic.empty() ? "none" : path_dynamic.c_str()); + ngram.lookup_cache_static.empty() ? "none" : ngram.lookup_cache_static.c_str(), + ngram.lookup_cache_dynamic.empty() ? "none" : ngram.lookup_cache_dynamic.c_str()); sinfos.resize(n_seq); - if (!path_static.empty()) { + if (!ngram.lookup_cache_static.empty()) { try { - auto ngram_cache_static = common_ngram_cache_load(path_static); + auto ngram_cache_static = common_ngram_cache_load(ngram.lookup_cache_static); for (auto & sinfo : sinfos) { sinfo.ngram_cache_static = ngram_cache_static; } - } catch (...) { - SPC_ERR("failed to open static lookup cache: %s", path_static.c_str()); + } catch (const std::ifstream::failure &) { + SPC_ERR("failed to open static lookup cache: %s\n", ngram.lookup_cache_static.c_str()); GGML_ABORT("Couldn't read static lookup cache"); } } - if (!path_dynamic.empty()) { + if (!ngram.lookup_cache_dynamic.empty()) { try { - auto ngram_cache_dynamic = common_ngram_cache_load(path_dynamic); + auto ngram_cache_dynamic = common_ngram_cache_load(ngram.lookup_cache_dynamic); for (auto & sinfo : sinfos) { sinfo.ngram_cache_dynamic = ngram_cache_dynamic; } - } catch (...) { - SPC_ERR("failed to open dynamic lookup cache: %s", path_dynamic.c_str()); - GGML_ABORT("Couldn't read dynamic lookup cache"); + } catch (const std::ifstream::failure &) { + std::error_code ec; + const bool exists = std::filesystem::exists(ngram.lookup_cache_dynamic, ec); + if (!exists && !ec) { + // missing file is created on destruction + SPC_WRN("dynamic lookup cache file does not exist: %s, starting with empty cache\n", + ngram.lookup_cache_dynamic.c_str()); + } else { + SPC_ERR("failed to open dynamic lookup cache: %s\n", ngram.lookup_cache_dynamic.c_str()); + GGML_ABORT("Couldn't read dynamic lookup cache"); + } } } } - void begin(llama_seq_id /*seq_id*/, const llama_tokens & /*prompt*/) override { - // noop + ~common_speculative_impl_ngram_cache() override { + if (params.lookup_cache_dynamic.empty() || sinfos.empty()) { + return; + } + + auto & dynamic_cache = sinfos.front().ngram_cache_dynamic; + for (auto & sinfo : sinfos) { + common_ngram_cache_merge(dynamic_cache, sinfo.ngram_cache_context); + } + + SPC_INF("saving dynamic lookup cache at %s\n", params.lookup_cache_dynamic.c_str()); + common_ngram_cache_save(dynamic_cache, params.lookup_cache_dynamic); + } + + void begin(llama_seq_id seq_id, const llama_tokens & /*prompt*/) override { + sinfos[seq_id].cache_size = 0; } void draft_one( @@ -2185,22 +2299,6 @@ struct common_speculative_impl_ngram_cache : public common_speculative_impl { const auto & prompt = *dparams.prompt; - if (sinfo.cache_size < prompt.size() + 1) { - llama_tokens tokens_new; - tokens_new.reserve(prompt.size() + 1 - sinfo.cache_size); - for (size_t j = sinfo.cache_size; j < prompt.size(); ++j) { - tokens_new.push_back(prompt[j]); - } - tokens_new.push_back(dparams.id_last); // add the last token - - // Update context ngram cache with new dparams.prompt: - common_ngram_cache_update( - sinfo.ngram_cache_context, - LLAMA_NGRAM_MIN, LLAMA_NGRAM_MAX, - tokens_new, tokens_new.size(), false); - sinfo.cache_size = prompt.size() + 1; - } - llama_tokens inp; inp.reserve(prompt.size() + 1); for (size_t j = 0; j < prompt.size(); ++j) { @@ -2208,6 +2306,16 @@ struct common_speculative_impl_ngram_cache : public common_speculative_impl { } inp.push_back(dparams.id_last); + if (sinfo.cache_size < inp.size()) { + // Update context ngram cache with the full history so n-grams + // ending at the new tokens have their preceding context + common_ngram_cache_update( + sinfo.ngram_cache_context, + LLAMA_NGRAM_MIN, LLAMA_NGRAM_MAX, + inp, inp.size() - sinfo.cache_size, false); + sinfo.cache_size = inp.size(); + } + result.push_back(dparams.id_last); common_ngram_cache_draft( @@ -2268,20 +2376,12 @@ static common_ngram_map get_common_ngram_map( return common_ngram_map(size_key, size_value, key_only, min_hits); } -static common_speculative_impl_ngram_cache create_state_ngram_cache( +static std::unique_ptr<common_speculative_impl_ngram_cache> create_state_ngram_cache( const common_speculative_config & config, - uint32_t n_seq, - const std::string & path_static, - const std::string & path_dynamic) { + uint32_t n_seq) { uint16_t n_draft = 8; // TODO get from config? - // TODO bool param in common/common.h to set save_static/save_dynamic? - bool save_static = false; - bool save_dynamic = false; - - common_speculative_impl_ngram_cache state(config.params, n_seq, n_draft, path_static, path_dynamic, save_static, save_dynamic); - - return state; + return std::make_unique<common_speculative_impl_ngram_cache>(config.params, n_seq, n_draft); } std::string common_speculative_type_name_str(const std::vector<common_speculative_type> & types) { @@ -2781,11 +2881,7 @@ common_speculative * common_speculative_init(common_params_speculative & params, break; } case COMMON_SPECULATIVE_TYPE_NGRAM_CACHE: { - auto state = create_state_ngram_cache( - config, n_seq, - params.ngram_cache.lookup_cache_static, - params.ngram_cache.lookup_cache_dynamic); - impls.push_back(std::make_unique<common_speculative_impl_ngram_cache>(state)); + impls.push_back(create_state_ngram_cache(config, n_seq)); break; } default: diff --git a/common/speculative.h b/common/speculative.h index a59846829683..4262327cbbc2 100644 --- a/common/speculative.h +++ b/common/speculative.h @@ -73,7 +73,7 @@ struct common_speculative_draft_params { // the generated draft from the last _draft() call llama_tokens * result; - // candidate distribution per drafted token; set it to make draft-simple and draft-mtp sample + // candidate distribution per drafted token; set it to make draft-simple, draft-mtp and draft-dflash (DFlash2 only) sample std::vector<std::vector<llama_token_data>> * result_q = nullptr; // the target's temp and seed, read only when the drafter samples probabilistically diff --git a/common/win-app.manifest b/common/win-app.manifest new file mode 100644 index 000000000000..540f6ed81540 --- /dev/null +++ b/common/win-app.manifest @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8" standalone="yes"?> +<assembly xmlns="urn:schemas-microsoft-com:asm.v1" manifestVersion="1.0"> + <application xmlns="urn:schemas-microsoft-com:asm.v3"> + <windowsSettings> + <activeCodePage xmlns="http://schemas.microsoft.com/SMI/2019/WindowsSettings">UTF-8</activeCodePage> + <longPathAware xmlns="http://schemas.microsoft.com/SMI/2016/WindowsSettings">true</longPathAware> + </windowsSettings> + </application> +</assembly> diff --git a/conversion/__init__.py b/conversion/__init__.py index 7f32a87f062a..6a34da41fe4a 100644 --- a/conversion/__init__.py +++ b/conversion/__init__.py @@ -17,13 +17,16 @@ TEXT_MODEL_MAP: dict[str, str] = { + "NEOChatModel": "sensenova_u1", "AfmoeForCausalLM": "afmoe", "LagunaForCausalLM": "laguna", + "FlintForCausalLM": "flint", "ApertusForCausalLM": "llama", "ArceeForCausalLM": "llama", "ArcticForCausalLM": "arctic", "AudioFlamingo3ForConditionalGeneration": "qwen", "BaiChuanForCausalLM": "baichuan", + "BeamForCausalLM": "beam", "BaichuanForCausalLM": "baichuan", "BailingMoeForCausalLM": "bailingmoe", "BailingMoeV2ForCausalLM": "bailingmoe", @@ -43,6 +46,7 @@ "ChatGLMForConditionalGeneration": "chatglm", "ChatGLMModel": "chatglm", "ClefModel": "clef", + "CloverMoeModelLM": "clover", "CodeShellForCausalLM": "codeshell", "CogVLMForCausalLM": "cogvlm", "Cohere2MoeForCausalLM": "command_r", @@ -59,6 +63,7 @@ "DeepseekV32ForCausalLM": "deepseek", "DFlashDraftModel": "qwen", "DFlash2DraftModel": "qwen", + "LiLiCorrDraftModel": "nemotron", "Qwen3DSparkModel": "qwen", "DSparkDraftModel": "qwen", "DSparkSpeculator": "qwen", @@ -66,6 +71,7 @@ "LingDSparkModel": "qwen", "DeepseekV4ForCausalLM": "deepseek", "DeepseekV4DSparkModel": "deepseek", + "DeepseekV41ForCausalLM": "deepseek41", "DistilBertForMaskedLM": "bert", "DistilBertForSequenceClassification": "bert", "DistilBertModel": "bert", @@ -144,6 +150,7 @@ "JinaBertModel": "bert", "JinaEmbeddingsV5Model": "bert", "K2HorizonForCausalLM": "k2_horizon", + "Kolibri1ForCausalLM": "kolibri1", "KORMoForCausalLM": "qwen", "KimiK25ForConditionalGeneration": "deepseek", "KimiK3ForConditionalGeneration": "kimi_k3", @@ -166,6 +173,11 @@ "D1OmniModel": "lfm2", "Lfm2Model": "lfm2", "Lfm2MoeForCausalLM": "lfm2", + "Lfm3D1Model": "lfm3", + "Lfm3ForCausalLM": "lfm3", + "Lfm3OmniForConditionalGeneration": "lfm3", + "Lfm3VlForConditionalGeneration": "lfm3", + "LimiteForCausalLM": "limite", "Llama4ForCausalLM": "llama", "Llama4ForConditionalGeneration": "llama", "LlamaBidirectionalModel": "llama", @@ -191,13 +203,19 @@ "MiniCPMForCausalLM": "minicpm", "MiniCPMV4_6ForConditionalGeneration": "minicpm", "MiniCPMV4_7ForConditionalGeneration": "minicpm", + "MiniCPMOCRForSequenceClassification": "qwen", + "MiniCPMOcrForConditionalGeneration": "minicpm", "MiniMaxText01ForCausalLM": "minimax", "MiniMaxM1ForCausalLM": "minimax", "MiniMaxM2ForCausalLM": "minimax", "MiniMaxM3SparseForCausalLM": "minimax", "MiniMaxM3SparseForConditionalGeneration": "minimax", "Ministral3ForCausalLM": "mistral3", + "Ministral3Model": "mistral3", "Mistral3ForConditionalGeneration": "mistral3", + "Mistral3Model": "mistral3", + "MistralLarge4ForConditionalGeneration": "mistral4", + "VoxtralRealtimeForConditionalGeneration": "mistral3", "MistralForCausalLM": "llama", "MixtralForCausalLM": "llama", "ModernBertDecisionModel": "bert", @@ -219,8 +237,10 @@ "OlmoeForCausalLM": "olmo", "MuseGlimmerAssistantModel": "muse_glimmer", "MuseGlimmerForConditionalGeneration": "muse_glimmer", + "MuseSparkForConditionalGeneration": "muse_spark", "OpenELMForCausalLM": "openelm", "OpenJevModel": "qwen", + "H2OLightningModel": "h2o_lightning", "OrionForCausalLM": "orion", "PLMForCausalLM": "plm", "PLaMo2ForCausalLM": "plamo", @@ -275,6 +295,7 @@ "SeedOssForCausalLM": "olmo", "SmallThinkerForCausalLM": "smallthinker", "SmolLM3ForCausalLM": "llama", + "SopranoTextModel": "soprano", "Spark2_5ForCausalLM": "spark2_5", "SolarOpenForCausalLM": "glm", "StableLMEpochForCausalLM": "stablelm", @@ -314,6 +335,7 @@ "VllmD3Model": "vllm_d3", "DeepseekOCR2ForCausalLM": "deepseek", "DeepseekOCRForCausalLM": "deepseek", + "DeepseekV41ForCausalLM": "deepseek41", "DeepseekV4ForCausalLM": "deepseek", "Dots3NoteForCausalLM": "dots3", "Dots3NoteForConditionalGeneration": "dots3", @@ -343,6 +365,9 @@ "Lfm2AudioForConditionalGeneration": "lfm2", "D1OmniModel": "lfm2", "Lfm2VlForConditionalGeneration": "lfm2", + "Lfm3AudioForConditionalGeneration": "lfm3", + "Lfm3OmniForConditionalGeneration": "lfm3", + "Lfm3VlForConditionalGeneration": "lfm3", "LightOnOCRForConditionalGeneration": "lighton_ocr", "Llama4ForConditionalGeneration": "llama4", "LlavaForConditionalGeneration": "llava", @@ -351,11 +376,17 @@ "MiniMaxM3SparseForConditionalGeneration": "minimax", "MiniCPMV4_6ForConditionalGeneration": "minicpm", "MiniCPMV4_7ForConditionalGeneration": "minicpm", + "MiniCPMOCRForSequenceClassification": "qwen3vl", + "MiniCPMOcrForConditionalGeneration": "minicpm", "Mistral3ForConditionalGeneration": "llava", + "Mistral3Model": "llava", + "NemotronH_Omni_Reasoning_V3": "nemotron", "NemotronH_Nano_VL_V2": "nemotron", "MuseGlimmerForConditionalGeneration": "muse_glimmer", + "MuseSparkForConditionalGeneration": "muse_spark", "PaddleOCRVisionModel": "ernie", "Phi4ForCausalLMV": "phi", + "NEOVisionModel": "sensenova_u1", "Qwen2AudioForConditionalGeneration": "ultravox", "Qwen2VLForConditionalGeneration": "qwenvl", "Qwen2VLModel": "qwenvl", @@ -364,10 +395,12 @@ "Qwen3ASRForConditionalGeneration": "qwen3vl", "Qwen3OmniMoeForConditionalGeneration": "qwen3vl", "PocketTTSModel": "pockettts", + "SopranoModel": "soprano", "Qwen3TTSForConditionalGeneration": "qwen3tts", "Qwen3VLForConditionalGeneration": "qwen3vl", "Qwen3VLMoeForConditionalGeneration": "qwen3vl", "OpenJevModel": "qwen3vl", + "H2OLightningModel": "h2o_lightning", "Qwen3_5ForConditionalGeneration": "qwen3vl", "Qwen3_5MoeForConditionalGeneration": "qwen3vl", "Qwen4ExpForConditionalGeneration": "qwen4exp", @@ -379,6 +412,7 @@ "UltravoxModel": "ultravox", "UnlimitedOCRForCausalLM": "deepseek", "VoxtralForConditionalGeneration": "ultravox", + "VoxtralRealtimeForConditionalGeneration": "ultravox", "YoutuVLForConditionalGeneration": "youtuvl", } diff --git a/conversion/base.py b/conversion/base.py index efb7ea72e2cd..6347d7fd32a5 100644 --- a/conversion/base.py +++ b/conversion/base.py @@ -10,11 +10,13 @@ import os import re import sys +import tempfile from enum import IntEnum from pathlib import Path from hashlib import sha256 from typing import TYPE_CHECKING, Any, Callable, ContextManager, Iterable, Iterator, Literal, Sequence, TypeVar, cast from itertools import chain +from math import prod from transformers import AutoConfig import numpy as np @@ -154,6 +156,7 @@ def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, self.fuse_gate_up_exps = fuse_gate_up_exps self._gate_exp_buffer: dict[int, Tensor] = {} self._up_exp_buffer: dict[int, Tensor] = {} + self._unfusable_gate_up_layers: set[int] = set() self.fuse_qkv = fuse_qkv self._q_buffer: dict[int, Tensor] = {} self._k_buffer: dict[int, Tensor] = {} @@ -174,7 +177,9 @@ def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, self._nvfp4_layer_algo: dict[str, str | None] = {} # per-layer quant_algo, keyed by HF module path self._prec_a4: dict[str, bool] = {} # gguf tensor name -> can use 4-bit (A4) activations self._fp8_as_q8 = fp8_as_q8 + self._preserve_fp8 = ftype == gguf.LlamaFileType.GUESSED and not fp8_as_q8 self._fp8_dequantized: set[str] = set() + self._fp8_e4m3_preserved: set[str] = set() # Apply heuristics to figure out typical tensor encoding based on first tensor's dtype # NOTE: can't use field "torch_dtype" in config.json, because some finetunes lie. @@ -325,7 +330,7 @@ def _write_scales_tensor(self, scale_name: str, scales: list[float]): def dequant_model(self): # If all quantized tensors were already handled (e.g. pure NVFP4), skip - if self._is_nvfp4 and not any(k.endswith((".weight_scale", ".weight_scale_inv")) for k in self.model_tensors): + if self._is_nvfp4 and not any(k.endswith((".weight_scale", ".weight_scale_inv", ".input_scale", ".activation_scale", "_activation_scale", ".k_scale", ".v_scale")) for k in self.model_tensors): return tensors_to_remove: list[str] = [] @@ -349,6 +354,12 @@ def dequant_bitnet(weight: Tensor, scale: Tensor) -> Tensor: def dequant_simple(weight: Tensor, scale: Tensor, block_size: Sequence[int] | None = None) -> Tensor: scale = scale.float() + # ModelOpt block scales are pre-shaped for broadcasting, e.g. [out/128, 1, in/128, 1] + if block_size is None and scale.ndim == 2 * weight.ndim and all(n == 1 for n in scale.shape[1::2]): + assert all(w % n == 0 for w, n in zip(weight.shape, scale.shape[0::2])) + block_size = [w // n for w, n in zip(weight.shape, scale.shape[0::2])] + scale = scale.reshape(tuple(scale.shape[0::2])) + if block_size is not None: dim_offset = scale.ndim - len(block_size) for i, size in enumerate(block_size): @@ -439,7 +450,7 @@ def dequant_packed(w: Tensor, scale: Tensor, shape_tensor: Tensor, zero_point: T return (unpacked * scale.unsqueeze(-1).float()).reshape(shape) - def dequant_fp8() -> None: + def dequant_fp8(fp8_configs: list[dict[str, Any]] | None = None) -> None: for name in self.model_tensors.keys(): if name.endswith(".weight_scale"): weight_name = name.removesuffix("_scale") @@ -448,14 +459,29 @@ def dequant_fp8() -> None: continue w = self.model_tensors[weight_name] s = self.model_tensors[name] + block_size = None is_fp8_weight = False - if self._fp8_as_q8: - is_fp8_weight = w().dtype in (torch.float8_e4m3fn, torch.float8_e5m2) - self.model_tensors[weight_name] = lambda w=w, s=s: dequant_simple(w(), s(), None) + if self._fp8_as_q8 or fp8_configs is not None: + weight = w() + is_fp8_weight = weight.dtype in (torch.float8_e4m3fn, torch.float8_e5m2) + if fp8_configs is not None: + if not is_fp8_weight: + raise ValueError(f"Expected remaining weight {weight_name!r} to be FP8, got {weight.dtype}") + scale = s() + is_channel_scale = scale.ndim >= 1 and scale.ndim <= weight.ndim and scale.shape[0] == weight.shape[0] and all(size == 1 for size in scale.shape[1:]) + if prod(scale.shape) != 1 and not is_channel_scale: + block_configs = [c for c in fp8_configs if c.get("strategy") == "block"] + if not block_configs or any(not c.get("block_structure") or c.get("group_size") is not None for c in block_configs): + raise ValueError(f"FP8 weight {weight_name!r} with scale shape {list(scale.shape)} requires a block layout") + block_sizes = {tuple(c["block_structure"]) for c in block_configs} + if len(block_sizes) != 1: + raise ValueError(f"FP8 weight {weight_name!r} has ambiguous block layouts") + block_size = next(iter(block_sizes)) + self.model_tensors[weight_name] = lambda w=w, s=s, bs=block_size: dequant_simple(w(), s(), bs) tensors_to_remove.append(name) - if is_fp8_weight: + if self._fp8_as_q8 and is_fp8_weight: self._fp8_dequantized.add(weight_name) - if name.endswith((".input_scale", ".k_scale", ".v_scale")): + if name.endswith((".input_scale", ".activation_scale", "_activation_scale", ".k_scale", ".v_scale")): tensors_to_remove.append(name) if quant_method == "bitnet": @@ -520,29 +546,37 @@ def dequant_fp8() -> None: nvfp4_compressed_tensors = self._is_nvfp4_compressed_tensors(quant_method, quant_format, groups) if nvfp4_compressed_tensors: - dequant_fp8() + fp8_configs = [ + g["weights"] for g in groups.values() + if isinstance(g, dict) and g.get("format") == "float-quantized" + and g.get("weights", {}).get("type") == "float" + and g.get("weights", {}).get("num_bits") == 8 + ] + dequant_fp8(fp8_configs) elif len(groups) > 1: raise NotImplementedError("Can't handle multiple config groups for compressed-tensors yet") elif quant_format == "float-quantized" or quant_format == "int-quantized" or quant_format == "naive-quantized": weight_config = tuple(groups.values())[0]["weights"] block_size = weight_config.get("block_structure", None) strategy = weight_config.get("strategy") - assert strategy == "channel" or strategy == "block" - assert weight_config.get("group_size") is None # didn't find a model using this yet is_fp8 = ( quant_format == "float-quantized" and weight_config.get("type") == "float" and weight_config.get("num_bits") == 8 ) + assert strategy in ("channel", "block") or (is_fp8 and strategy == "tensor") + assert weight_config.get("group_size") is None # didn't find a model using this yet for name in self.model_tensors.keys(): if name.endswith(".weight_scale"): weight_name = name.removesuffix("_scale") w = self.model_tensors[weight_name] s = self.model_tensors[name] - self.model_tensors[weight_name] = lambda w=w, s=s: dequant_simple(w(), s(), block_size) + self.model_tensors[weight_name] = lambda w=w, s=s, bs=block_size: dequant_simple(w(), s(), bs) tensors_to_remove.append(name) if self._fp8_as_q8 and is_fp8: self._fp8_dequantized.add(weight_name) + if is_fp8 and name.endswith((".input_scale", ".activation_scale", "_activation_scale", ".k_scale", ".v_scale")): + tensors_to_remove.append(name) elif quant_format == "pack-quantized": weight_config = tuple(groups.values())[0]["weights"] assert weight_config.get("strategy") == "group" @@ -568,7 +602,7 @@ def dequant_fp8() -> None: tensors_to_remove.append(base_name + "_zero_point") else: raise NotImplementedError(f"Quant format {quant_format!r} for method {quant_method!r} is not yet supported") - elif quant_method == "modelopt": + elif quant_method in ("modelopt", "modelopt_mixed"): dequant_fp8() elif quant_method is not None: raise NotImplementedError(f"Quant method is not yet supported: {quant_method!r}") @@ -580,6 +614,148 @@ def dequant_fp8() -> None: for name, value in new_tensors.items(): self.model_tensors[name] = value + def _map_fp8_weight_names(self, name: str) -> tuple[str, ...]: + new_name = self.tensor_map.get_name(name, try_suffixes=(".weight",)) + return (new_name,) if new_name is not None else () + + def _prepare_fp8_e4m3_tensors(self): + if not self._preserve_fp8: + return + + scale_tensors: dict[str, list[tuple[int, float]] | np.ndarray] = {} + input_scale_tensors: dict[str, list[tuple[int, float]] | np.ndarray] = {} + consumed: list[str] = [] + candidates: dict[str, tuple[str, Tensor, tuple[str, ...], torch.Size]] = {} + weight_dtypes: dict[str, torch.dtype] = {} + scaled_weights: set[str] = set() + expert_pattern = re.compile(r"(\.[^.]*experts)\.(\d+)\.") + scale_types = { + gguf.MODEL_TENSOR.ATTN_Q, gguf.MODEL_TENSOR.ATTN_K, gguf.MODEL_TENSOR.ATTN_V, + gguf.MODEL_TENSOR.ATTN_OUT, gguf.MODEL_TENSOR.ATTN_QKV, gguf.MODEL_TENSOR.ATTN_GATE, + gguf.MODEL_TENSOR.FFN_GATE, gguf.MODEL_TENSOR.FFN_UP, gguf.MODEL_TENSOR.FFN_DOWN, + gguf.MODEL_TENSOR.FFN_GATE_SHEXP, gguf.MODEL_TENSOR.FFN_UP_SHEXP, gguf.MODEL_TENSOR.FFN_DOWN_SHEXP, + gguf.MODEL_TENSOR.FFN_GATE_EXP, gguf.MODEL_TENSOR.FFN_UP_EXP, gguf.MODEL_TENSOR.FFN_DOWN_EXP, + gguf.MODEL_TENSOR.SSM_IN, gguf.MODEL_TENSOR.SSM_OUT, gguf.MODEL_TENSOR.SSM_ALPHA, gguf.MODEL_TENSOR.SSM_BETA, + gguf.MODEL_TENSOR.NEXTN_EH_PROJ, gguf.MODEL_TENSOR.NEXTN_SHARED_HEAD_HEAD, gguf.MODEL_TENSOR.OUTPUT, + } + + for scale_name in list(self.model_tensors.keys()): + weight_name = None + if scale_name.endswith(".weight_scale"): + weight_name = scale_name.removesuffix("_scale") + elif scale_name.endswith("_scale_inv"): + weight_name = scale_name.removesuffix("_scale_inv") + elif scale_name.endswith(".qscale_weight"): + weight_name = scale_name.removesuffix("qscale_weight") + "weight" + + if weight_name is None or weight_name not in self.model_tensors: + continue + + scaled_weights.add(weight_name) + weight = self.model_tensors[weight_name]() + weight_dtypes[weight_name] = weight.dtype + if weight.dtype != torch.float8_e4m3fn or weight.ndim < 2: + continue + + scale = self.model_tensors[scale_name]() + if prod(scale.shape) != 1: + continue + + merged_name = expert_pattern.sub(r"\1.", weight_name) + new_names = self._map_fp8_weight_names(merged_name) + if not new_names: + continue + if any((mapped := self.tensor_map.get_type_and_name(new_name, try_suffixes=(".weight",))) is None or mapped[0] not in scale_types for new_name in new_names): + continue + bid = next((int(part) for part in new_names[0].split(".") if part.isdecimal()), None) + self._fp8_e4m3_preserved.add(weight_name) + if any(new_name.endswith("_norm.weight") or self.tensor_force_quant(weight_name, new_name, bid, weight.ndim) != gguf.GGMLQuantizationType.F8_E4M3 for new_name in new_names): + self._fp8_e4m3_preserved.discard(weight_name) + continue + candidates[weight_name] = (scale_name, scale, new_names, weight.shape) + + expert_groups: dict[str, list[str]] = {} + for name in self.model_tensors: + if (match := expert_pattern.search(name)) and name.endswith(".weight"): + expert_groups.setdefault(name[:match.end(1)], []).append(name) + for names in expert_groups.values(): + for name in names: + if name not in weight_dtypes: + weight_dtypes[name] = self.model_tensors[name]().dtype + dtypes = {weight_dtypes[name] for name in names} + if torch.float8_e4m3fn not in dtypes: + continue + if dtypes == {torch.float8_e4m3fn} and not any(name in scaled_weights for name in names): + continue + # The converter merges expert projections together. + if not all(name in candidates for name in names): + for name in names: + candidates.pop(name, None) + self._fp8_e4m3_preserved.discard(name) + if name not in scaled_weights: + gen = self.model_tensors[name] + self.model_tensors[name] = lambda gen=gen: gen().float() + + for weight_name, (scale_name, scale, new_names, shape) in candidates.items(): + scale = LazyTorchTensor.to_eager(scale).float().flatten() + + weight_prefix = weight_name.removesuffix(".weight") + # Transformers fine-grained FP8 uses activation_scale while ModelOpt uses input_scale. + # Ref: https://github.com/vllm-project/vllm/blob/main/vllm/model_executor/models/mistral3.py#L357-L361 + input_scale_name = next((name for name in ( + weight_prefix + ".input_scale", + weight_prefix + ".activation_scale", + weight_prefix + "_activation_scale", + weight_prefix + ".qscale_act", + ) if name in self.model_tensors), None) + input_scale = None + if input_scale_name is not None: + input_scale = self.model_tensors[input_scale_name]() + if prod(input_scale.shape) != 1: + raise ValueError(f"FP8 input scale {input_scale_name!r} must be a scalar") + input_scale = LazyTorchTensor.to_eager(input_scale).float().flatten() + consumed.append(input_scale_name) + + consumed.append(scale_name) + + expert_match = expert_pattern.search(weight_name) + if expert_match: + expert_id = int(expert_match.group(2)) + for new_name in new_names: + target_name = new_name.replace(".weight", ".scale") + entries = scale_tensors.setdefault(target_name, []) + assert isinstance(entries, list) + cast(list[tuple[int, float]], entries).append((expert_id, float(scale[0]))) + if input_scale is not None: + target_name = new_name.replace(".weight", ".input_scale") + entries = input_scale_tensors.setdefault(target_name, []) + assert isinstance(entries, list) + cast(list[tuple[int, float]], entries).append((expert_id, float(input_scale[0]))) + else: + for new_name in new_names: + mapped = self.tensor_map.get_type_and_name(new_name, try_suffixes=(".weight",)) if len(shape) == 3 else None + is_packed_expert = mapped is not None and mapped[0] in ( + gguf.MODEL_TENSOR.FFN_GATE_EXP, gguf.MODEL_TENSOR.FFN_UP_EXP, gguf.MODEL_TENSOR.FFN_DOWN_EXP, + ) + # Packed expert weights need one scale value per expert. + n_scales = shape[0] if is_packed_expert else 1 + scale_tensors[new_name.replace(".weight", ".scale")] = np.repeat(scale.numpy(), n_scales) + if input_scale is not None: + input_scale_tensors[new_name.replace(".weight", ".input_scale")] = np.repeat(input_scale.numpy(), n_scales) + + for name in consumed: + self.model_tensors.pop(name, None) + + for name, values in chain(scale_tensors.items(), input_scale_tensors.items()): + if isinstance(values, list): + values.sort(key=lambda item: item[0]) + scale = np.array([item[1] for item in values], dtype=np.float32) + else: + scale = values.astype(np.float32) + if not np.allclose(scale, 1.0, atol=1e-6): + logger.info(f" + {name} (FP8 scale, shape [{scale.size}])") + self.gguf_writer.add_tensor(name, scale) + @classmethod def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: name, gen = item @@ -624,6 +800,26 @@ def map_tensor_name(self, name: str, try_suffixes: Sequence[str] = (".weight", " raise ValueError(f"Can not map tensor {name!r}") return new_name + def prepare_gate_up_fusion(self) -> None: + self._unfusable_gate_up_layers.clear() + if not self.fuse_gate_up_exps or self._fp8_as_q8: + return + + for name, gen in self.model_tensors.items(): + merged_name = re.sub(r"(\.experts)\.\d+\.", r"\1.", name) + mapped = self.tensor_map.get_type_and_name(merged_name, try_suffixes=(".weight",)) + if mapped is None: + continue + tensor_type, new_name = mapped + if tensor_type not in (gguf.MODEL_TENSOR.FFN_GATE_EXP, gguf.MODEL_TENSOR.FFN_UP_EXP, gguf.MODEL_TENSOR.FFN_GATE_UP_EXP) or not new_name.endswith(".weight"): + continue + if gen().dtype == torch.float8_e4m3fn: + bid = next(int(part) for part in new_name.split(".") if part.isdecimal()) + self._unfusable_gate_up_layers.add(bid) + + for bid in sorted(self._unfusable_gate_up_layers): + logger.warning(f"Skipping --fuse-gate-up-exps for layer {bid}: fusion of preserved FP8 expert projections is not supported") + def prepare_qkv_fusion(self) -> None: self._fusable_qkv_weight_layers.clear() self._fusable_qkv_bias_layers.clear() @@ -637,6 +833,7 @@ def prepare_qkv_fusion(self) -> None: } weights: dict[int, set[gguf.MODEL_TENSOR]] = {} biases: dict[int, set[gguf.MODEL_TENSOR]] = {} + fp8_layers: set[int] = set() for name in self.model_tensors: mapped = self.tensor_map.get_type_and_name(name, try_suffixes=(".weight", ".bias")) @@ -651,12 +848,19 @@ def prepare_qkv_fusion(self) -> None: continue if new_name.endswith(".weight"): weights.setdefault(bid, set()).add(tensor_type) + if not self._fp8_as_q8 and self.model_tensors[name]().dtype == torch.float8_e4m3fn: + fp8_layers.add(bid) elif new_name.endswith(".bias"): biases.setdefault(bid, set()).add(tensor_type) for bid, weight_types in weights.items(): bias_types = biases.get(bid, set()) if weight_types == qkv_types and (not bias_types or bias_types == qkv_types): + # NVFP4 weights use separate reordering and repacking hooks and are exported before this fusion pass. + # Separate FP8 scales cannot be represented by one fused QKV scale. + if bid in fp8_layers: + logger.warning(f"Skipping --fuse-qkv for layer {bid}: fusion of preserved FP8 projections is not supported") + continue self._fusable_qkv_weight_layers.add(bid) if bias_types: self._fusable_qkv_bias_layers.add(bid) @@ -845,7 +1049,8 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter new_name = self.map_tensor_name(name) # Handle gate/up expert tensor fusion if enabled - if self.fuse_gate_up_exps and bid is not None: + # Preserved FP8 gate/up scales must stay with their separate projections. + if self.fuse_gate_up_exps and bid is not None and bid not in self._unfusable_gate_up_layers: if self.match_model_tensor_name(new_name, gguf.MODEL_TENSOR.FFN_GATE_EXP, bid): self._gate_exp_buffer[bid] = data_torch elif self.match_model_tensor_name(new_name, gguf.MODEL_TENSOR.FFN_UP_EXP, bid): @@ -902,8 +1107,46 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter return [(new_name, data_torch)] + def _tensor_requires_f32(self, new_name: str, bid: int | None, n_dims: int) -> bool: + # Conditions should closely match those in llama_model_quantize_internal in llama.cpp. + return n_dims <= 1 or new_name.endswith("_norm.weight") or ( + any( + self.match_model_tensor_name(new_name, key, bid) + for key in ( + gguf.MODEL_TENSOR.FFN_GATE_INP, + gguf.MODEL_TENSOR.FFN_GATE_INP_SHEXP, + gguf.MODEL_TENSOR.POS_EMBD, + gguf.MODEL_TENSOR.TOKEN_TYPES, + gguf.MODEL_TENSOR.SSM_CONV1D, + gguf.MODEL_TENSOR.SHORTCONV_CONV, + gguf.MODEL_TENSOR.TIME_MIX_FIRST, + gguf.MODEL_TENSOR.TIME_MIX_W1, + gguf.MODEL_TENSOR.TIME_MIX_W2, + gguf.MODEL_TENSOR.TIME_MIX_DECAY_W1, + gguf.MODEL_TENSOR.TIME_MIX_DECAY_W2, + gguf.MODEL_TENSOR.TIME_MIX_LERP_FUSED, + gguf.MODEL_TENSOR.POSNET_NORM1, + gguf.MODEL_TENSOR.POSNET_NORM2, + gguf.MODEL_TENSOR.V_ENC_EMBD_POS, + gguf.MODEL_TENSOR.A_ENC_EMBD_POS, + gguf.MODEL_TENSOR.ALTUP_CORRECT_COEF, + gguf.MODEL_TENSOR.ALTUP_PREDICT_COEF, + # Kimi KDA conv weights should be F32 + gguf.MODEL_TENSOR.SSM_CONV1D_Q, + gguf.MODEL_TENSOR.SSM_CONV1D_K, + gguf.MODEL_TENSOR.SSM_CONV1D_V, + # DSA indexer weights should be F32 + gguf.MODEL_TENSOR.INDEXER_PROJ, + ) + ) + or new_name[-7:] not in (".weight", ".lora_a", ".lora_b") + ) + def tensor_force_quant(self, name: str, new_name: str, bid: int | None, n_dims: int) -> gguf.GGMLQuantizationType | bool: - del new_name, bid # unused + if name in self._fp8_e4m3_preserved and n_dims >= 2: + if self._tensor_requires_f32(new_name, bid, n_dims): + return gguf.GGMLQuantizationType.F32 + return gguf.GGMLQuantizationType.F8_E4M3 # Force FP8-original tensors to Q8_0 when requested; Q8_0 is faster than F16/BF16. if self._fp8_as_q8 and name in self._fp8_dequantized and n_dims >= 2: return gguf.GGMLQuantizationType.Q8_0 @@ -1034,7 +1277,7 @@ def _generate_nvfp4_tensors(self): expert_scales: dict[tuple[int, str], list[tuple[int, float]]] = {} expert_input_scales: dict[tuple[int, str], list[tuple[int, float]]] = {} expert_shapes: dict[tuple[int, str], list[int]] = {} - n_experts = self.find_hparam(["num_local_experts", "num_experts"], optional=True) or 0 + n_experts = self.find_hparam(["num_local_experts", "num_experts", "n_routed_experts"], optional=True) or 0 consumed: list[str] = [] for name in self.model_tensors.keys(): @@ -1045,14 +1288,17 @@ def _generate_nvfp4_tensors(self): input_scale_name = name.replace(".weight", ".input_scale") if scale_name not in self.model_tensors: continue - # Force eager materialization of lazy tensors - weight = LazyTorchTensor.to_eager(self.model_tensors[name]()) - scale = LazyTorchTensor.to_eager(self.model_tensors[scale_name]()) + weight = self.model_tensors[name]() + scale = self.model_tensors[scale_name]() - # Skip non-NVFP4 tensors(e.g. 1D scale, or float8 weight) - if scale.ndim < 2 or weight.dtype in (torch.float8_e4m3fn, torch.float8_e5m2): + # Leave FP8 weights and their scales for _prepare_fp8_e4m3_tensors. + if weight.dtype in (torch.float8_e4m3fn, torch.float8_e5m2) or scale.ndim < 2: continue + if weight.ndim != 2 or scale.shape[0] != weight.shape[0] or scale.shape[1] * 8 != weight.shape[1]: + raise ValueError(f"NVFP4 weight {name!r} has incompatible shapes: weight {list(weight.shape)}, scale {list(scale.shape)}") + weight = LazyTorchTensor.to_eager(weight) + scale = LazyTorchTensor.to_eager(scale) scale2 = LazyTorchTensor.to_eager(self.model_tensors.get(scale2_name, lambda: torch.tensor(1.0))()) input_scale = LazyTorchTensor.to_eager(self.model_tensors.get(input_scale_name, lambda: torch.tensor(1.0))()) @@ -1208,8 +1454,10 @@ def load(): self.model_tensors[input_scale_name] = inverse_scale(self.model_tensors.pop(name)) self._generate_nvfp4_tensors() + self._prepare_fp8_e4m3_tensors() self.dequant_model() + self.prepare_gate_up_fusion() self.prepare_qkv_fusion() # Handle empty tensor_map for models with block_count=0 (like MobileNetV5) @@ -1223,10 +1471,21 @@ def load(): if name.endswith((".attention.masked_bias", ".attention.bias", ".rotary_emb.inv_freq")): continue + # FP8 transforms must only reorder values; norms and vectors use numeric F32 transforms. + preserve_fp8_e4m3 = self._preserve_fp8 and data_torch.dtype == torch.float8_e4m3fn and data_torch.ndim >= 2 and not name.endswith(("norm.weight", "norm_f.weight")) + if preserve_fp8_e4m3: + for new_name in self._map_fp8_weight_names(name): + mapped_bid = next((int(part) for part in new_name.split(".") if part.isdecimal()), None) + if self._tensor_requires_f32(new_name, mapped_bid, data_torch.ndim): + preserve_fp8_e4m3 = False + break + if preserve_fp8_e4m3: + self._fp8_e4m3_preserved.add(name) + old_dtype = data_torch.dtype # convert any unsupported data types to float32 - if data_torch.dtype not in (torch.float16, torch.float32): + if data_torch.dtype not in (torch.float16, torch.float32) and name not in self._fp8_e4m3_preserved: data_torch = data_torch.to(torch.float32) # use the first number-like part of the tensor name as the block id @@ -1237,51 +1496,14 @@ def load(): break for new_name, data_torch in (self.modify_tensors(data_torch, name, bid)): - # TODO: why do we squeeze here? - # data = data_torch.squeeze().numpy() - data = data_torch.numpy() - - n_dims = len(data.shape) + n_dims = len(data_torch.shape) data_qtype: gguf.GGMLQuantizationType | bool = self.tensor_force_quant(name, new_name, bid, n_dims) # Most of the codebase that takes in 1D tensors or norms only handles F32 tensors if n_dims <= 1 or new_name.endswith("_norm.weight"): data_qtype = gguf.GGMLQuantizationType.F32 - # Conditions should closely match those in llama_model_quantize_internal in llama.cpp - # Some tensor types are always in float32 - if data_qtype is False and ( - any( - self.match_model_tensor_name(new_name, key, bid) - for key in ( - gguf.MODEL_TENSOR.FFN_GATE_INP, - gguf.MODEL_TENSOR.FFN_GATE_INP_SHEXP, - gguf.MODEL_TENSOR.POS_EMBD, - gguf.MODEL_TENSOR.TOKEN_TYPES, - gguf.MODEL_TENSOR.SSM_CONV1D, - gguf.MODEL_TENSOR.SHORTCONV_CONV, - gguf.MODEL_TENSOR.TIME_MIX_FIRST, - gguf.MODEL_TENSOR.TIME_MIX_W1, - gguf.MODEL_TENSOR.TIME_MIX_W2, - gguf.MODEL_TENSOR.TIME_MIX_DECAY_W1, - gguf.MODEL_TENSOR.TIME_MIX_DECAY_W2, - gguf.MODEL_TENSOR.TIME_MIX_LERP_FUSED, - gguf.MODEL_TENSOR.POSNET_NORM1, - gguf.MODEL_TENSOR.POSNET_NORM2, - gguf.MODEL_TENSOR.V_ENC_EMBD_POS, - gguf.MODEL_TENSOR.A_ENC_EMBD_POS, - gguf.MODEL_TENSOR.ALTUP_CORRECT_COEF, - gguf.MODEL_TENSOR.ALTUP_PREDICT_COEF, - # Kimi KDA conv weights should be F32 - gguf.MODEL_TENSOR.SSM_CONV1D_Q, - gguf.MODEL_TENSOR.SSM_CONV1D_K, - gguf.MODEL_TENSOR.SSM_CONV1D_V, - # DSA indexer weights should be F32 - gguf.MODEL_TENSOR.INDEXER_PROJ, - ) - ) - or new_name[-7:] not in (".weight", ".lora_a", ".lora_b") - ): + if data_qtype is False and self._tensor_requires_f32(new_name, bid, n_dims): data_qtype = gguf.GGMLQuantizationType.F32 if data_qtype is False and any( @@ -1319,16 +1541,22 @@ def load(): else: raise ValueError(f"Unknown file type: {self.ftype.name}") + if data_torch.dtype == torch.float8_e4m3fn: + data = data_torch.view(torch.uint8).numpy() if data_qtype == gguf.GGMLQuantizationType.F8_E4M3 else data_torch.float().numpy() + else: + data = data_torch.numpy() + # a chunked tensor quantizes as one chunk at a time, while it is written quantize = data.quantize if isinstance(data, gguf.LazyChunkedTensor) else ( lambda qtype, d=data: gguf.quants.quantize(d, qtype)) - try: - data = quantize(data_qtype) - except gguf.QuantError as e: - logger.warning("%s, %s", e, "falling back to F16") - data_qtype = gguf.GGMLQuantizationType.F16 - data = quantize(data_qtype) + if not (data_qtype == gguf.GGMLQuantizationType.F8_E4M3 and data.dtype == np.uint8): + try: + data = quantize(data_qtype) + except gguf.QuantError as e: + logger.warning("%s, %s", e, "falling back to F16") + data_qtype = gguf.GGMLQuantizationType.F16 + data = quantize(data_qtype) shape = gguf.quant_shape_from_byte_shape(data.shape, data_qtype) if data.dtype == np.uint8 else data.shape @@ -1369,6 +1597,8 @@ def prepare_metadata(self, vocab_only: bool): self.ftype = gguf.LlamaFileType.MOSTLY_NVFP4 elif self._is_mxfp4: self.ftype = gguf.LlamaFileType.MOSTLY_MXFP4_MOE + elif self._fp8_e4m3_preserved: + self.ftype = gguf.LlamaFileType.MOSTLY_F8_E4M3 # Generate parameter weight class (useful for leader boards) if not yet determined if self.metadata.size_label is None and total_params > 0: @@ -1625,7 +1855,7 @@ def set_gguf_parameters(self): self.gguf_writer.add_head_count_kv(n_head_kv) logger.info(f"gguf: key-value head count = {n_head_kv}") - if self.hparams.get("is_causal") is False: + if self.hparams.get("is_causal") is False or self.hparams.get("use_bidirectional_attention") is True: self.gguf_writer.add_causal_attention(False) logger.info("gguf: causal attention = False") @@ -1700,7 +1930,7 @@ def set_gguf_parameters(self): self.gguf_writer.add_expert_group_used_count(n_group_used) logger.info(f"gguf: expert groups used count = {n_group_used}") - if (score_func := self.find_hparam(["score_function", "scoring_func", "score_func", "moe_router_activation", "moe_router_activation_func", "expert_selection_fn", "router_score_func"], optional=True)) is not None: + if (score_func := self.find_hparam(["score_function", "scoring_func", "score_func", "moe_router_activation", "moe_router_activation_func", "expert_selection_fn", "router_score_func", "router_score_function"], optional=True)) is not None: if score_func == "sigmoid": self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) elif score_func == "softmax": @@ -1836,6 +2066,9 @@ def get_vocab_base_pre(self, tokenizer) -> str: if chkhsh == "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35": # ref: https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0 res = "minerva-7b" + if chkhsh == "6e4d72c6e5260b90606e26a0931fa15e4b42ec6e97719d12919f2b1f93478262": + # ref: https://huggingface.co/domyn/Domyn-Small-v1.0 + res = "domyn-small" if chkhsh == "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664": # ref: https://huggingface.co/tencent/Hunyuan-A13B-Instruct res = "hunyuan" @@ -1869,6 +2102,12 @@ def get_vocab_base_pre(self, tokenizer) -> str: if chkhsh == "66b8d4e19ab16c3bfd89bce5d785fb7e0155e8648708a1f42077cb9fe002c273": # ref: https://huggingface.co/alvarobartt/grok-2-tokenizer res = "grok-2" + if chkhsh == "f5c965e4198da6e7525072d87d1ecf4c51d981fd486c7c4ec728ef9cec7e03fc": + # ref: https://huggingface.co/meta-models/Muse-Spark-Open-816B-A42B + res = "gpt-4o" + if chkhsh == "6e040dfe72e4b85855588c53acf4909ac4e98e55bc3a33cd7db499180dc42a78": + # ref: https://huggingface.co/Aleph-Alpha/Kolibri-1 + res = "qwen2" if chkhsh == "b3d1dd861f1d4c5c0d2569ce36baf3f90fe8a102db3de50dd71ff860d91be3df": # ref: https://huggingface.co/aari1995/German_Semantic_V3 res = "jina-v2-de" @@ -1932,6 +2171,9 @@ def get_vocab_base_pre(self, tokenizer) -> str: if chkhsh == "52df12b4c8d4176e7481aab4b6e8454d1fd0a210a04a574f6d4e067d10e23c3e": # ref: https://huggingface.co/CohereLabs/North-Mini-Code-1.0 res = "cohere2moe" + if chkhsh == "d5420e601e979078c670bc503d9ac411c311fa76b76a76267c31e0d6ba816637": + # ref: https://huggingface.co/RecursiveSI/flint + res = "flint" if chkhsh == "e636dc30a262dcc0d8c323492e32ae2b70728f4df7dfe9737d9f920a282b8aea": # ref: https://huggingface.co/Qwen/Qwen1.5-7B res = "qwen2" @@ -2163,20 +2405,34 @@ def _set_vocab_whitespace(self) -> None: special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) special_vocab.add_to_gguf(self.gguf_writer) + def _is_hybriddna(self) -> bool: + tokenizer_config_file = self.dir_model / "tokenizer_config.json" + if not tokenizer_config_file.is_file(): + return False + with open(tokenizer_config_file, "r", encoding="utf-8") as f: + return json.load(f).get("tokenizer_class") == "HybridDNATokenizer" + def _set_vocab_hybriddna(self): from transformers import AutoTokenizer tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) - vocab_size = self.hparams.get("vocab_size", len(tokenizer.vocab)) # ty: ignore[unresolved-attribute] - assert max(tokenizer.vocab.values()) < vocab_size # ty: ignore[unresolved-attribute] + vocab = tokenizer.get_vocab() + vocab_size = self.hparams.get("vocab_size", len(vocab)) + assert max(vocab.values()) < vocab_size - reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in tokenizer.vocab.items()} # ty: ignore[unresolved-attribute] - # k-mers can share text with a base-vocab BPE token (e.g. CCCCCC) and get - # dropped by get_vocab(); a reserved marker suffix (U+E000) keeps each - # k-mer's own id (llama.cpp strips it on detokenization) - for kmer in tokenizer.kmers: # ty: ignore[unresolved-attribute] + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab.items()} + # k-mers can share text with a base-vocab BPE token (e.g. CCCCCC) and get dropped by get_vocab() + # a reserved marker suffix (U+E000) keeps each k-mer's own id (llama.cpp strips it on detokenization) + # tail="pad_n" (Carbon-14B) adds N-padded tail tokens ("CT" -> "CTNNNN") that get the same marker + # llama.cpp detects them to pad with N and strips the padding on detokenization, tail="char" is unsupported + tail = getattr(tokenizer, "tail", "pad_a") + if tokenizer.k != 6 or tail not in ("pad_a", "pad_n"): + raise NotImplementedError(f"HybridDNATokenizer with k={tokenizer.k}, tail={tail!r}") + for kmer in [*tokenizer.kmers, *getattr(tokenizer, "npad_tokens", [])]: reverse_vocab[tokenizer.dna_token_to_id[kmer]] = kmer + "\ue000" # ty: ignore[unresolved-attribute] - added_vocab = tokenizer.get_added_vocab() # ty: ignore[unresolved-attribute] - added_tokens_decoder = tokenizer.added_tokens_decoder # ty: ignore[unresolved-attribute] + # older HybridDNATokenizer versions (Carbon-500M/3B/8B) do not register the base tokenizer's added tokens (<|im_start|>, <think>, ...) as their own + # but they are still encoded as special tokens: take their types from the base tokenizer + base_tokenizer = getattr(tokenizer, "_base_tokenizer", tokenizer) + added_tokens_decoder = {**base_tokenizer.added_tokens_decoder, **tokenizer.added_tokens_decoder} # ty: ignore[unresolved-attribute] tokens: list[str] = [] toktypes: list[int] = [] @@ -2186,7 +2442,7 @@ def _set_vocab_hybriddna(self): toktypes.append(gguf.TokenType.UNUSED) else: token: str = reverse_vocab[i] - if token in added_vocab: + if i in added_tokens_decoder: if added_tokens_decoder[i].special or self.does_token_look_special(token): toktypes.append(gguf.TokenType.CONTROL) else: @@ -2198,10 +2454,19 @@ def _set_vocab_hybriddna(self): tokpre = self.get_vocab_base_pre(tokenizer) self.gguf_writer.add_tokenizer_model("hybriddna") self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_dna_auto_tags(getattr(tokenizer, "auto_dna_tags", False)) self.gguf_writer.add_token_list(tokens) self.gguf_writer.add_token_types(toktypes) special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + if not special_vocab.merges: + # Carbon-500M/3B/8B ship only tokenizer.py, no tokenizer.json + # take the merges and special token ids from the base BPE tokenizer, keeping the model's own chat template (if any) + with tempfile.TemporaryDirectory() as tmp: + base_tokenizer.save_pretrained(tmp) + base_special_vocab = gguf.SpecialVocab(Path(tmp), load_merges=True) + base_special_vocab.chat_template = special_vocab.chat_template + special_vocab = base_special_vocab special_vocab.add_to_gguf(self.gguf_writer) def _set_vocab_qwen(self): @@ -2636,7 +2901,13 @@ def _set_vocab_mistral(self): ) if vocab.tokenizer_type == MistralTokenizerType.tekken: - self.gguf_writer.add_tokenizer_pre("tekken") + with open(vocab.fname_tokenizer, encoding="utf-8") as f: + pattern = json.load(f)["config"]["pattern"] + # newer tekken.json split numbers into right-aligned groups of 3 digits instead of single digits + if "\\p{N}{1,3}(?=(?:\\p{N}{3})*(?!\\p{N}))" in pattern: + self.gguf_writer.add_tokenizer_pre("tekken-num3") + else: + self.gguf_writer.add_tokenizer_pre("tekken") self.gguf_writer.add_token_merges( vocab.extract_vocab_merges_from_model() ) @@ -3113,7 +3384,7 @@ def get_model_architecture(hparams: dict[str, Any], model_type: ModelType) -> st # Kimi-K3's text_config reports "KimiLinearForCausalLM", which is the older # Kimi-Linear-48B architecture and cannot load K3 (no attention residuals, # latent MoE, situ, ...). Route on the top-level architecture instead. - if model_type == ModelType.TEXT and arch in ("StepVLForConditionalGeneration", "Sarashina2VisionForCausalLM", "Exaone4_5_ForConditionalGeneration", "Step3p7ForConditionalGeneration", "KimiK3ForConditionalGeneration"): + if model_type == ModelType.TEXT and arch in ("NEOChatModel", "StepVLForConditionalGeneration", "Sarashina2VisionForCausalLM", "Exaone4_5_ForConditionalGeneration", "Step3p7ForConditionalGeneration", "KimiK3ForConditionalGeneration"): return arch # if "architectures" is found in the sub-config, use that instead diff --git a/conversion/beam.py b/conversion/beam.py new file mode 100644 index 000000000000..67d0cc93ca63 --- /dev/null +++ b/conversion/beam.py @@ -0,0 +1,135 @@ +from __future__ import annotations + +from typing import Callable, Iterable, TYPE_CHECKING + +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import ModelBase, TextModel, gguf, logger + + +@ModelBase.register("BeamForCausalLM") +class BeamModel(TextModel): + model_arch = gguf.MODEL_ARCH.BEAM + + # reference NoPE query-scale constants; not in config.json + NOPE_SCALE_POWER = 0.1 + NOPE_SCALE_LENGTH = 2048 + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + hp = self.hparams + rope = hp.get("rope_parameters") or {} + if rope.get("full_attention") is not None: + raise ValueError("Beam: expected NoPE full-attention layers (rope_parameters.full_attention = null)") + if "sliding_attention" in rope: + swa_rope = rope["sliding_attention"] or {} + else: + # flat rope_theta / rope_scaling, already normalized by TextModel + swa_rope = {k: v for k, v in self.rope_parameters.items() if k not in ("sliding_attention", "full_attention", "type")} + swa_rope.update(self.rope_parameters.get("sliding_attention") or {}) + if swa_rope.get("rope_type", "default") != "default": + raise ValueError(f"Beam: unsupported sliding-attention rope type {swa_rope.get('rope_type')!r}") + # full layers are NoPE, so mirror the sliding rope params for the base class + swa_rope = {k: v for k, v in swa_rope.items() if not (k == "rope_type" and v == "default")} + self.rope_parameters = {"sliding_attention": dict(swa_rope), "full_attention": dict(swa_rope)} + + layer_types = hp["layer_types"] + mlp_types = hp["mlp_layer_types"] + n_layer = hp["num_hidden_layers"] + if len(layer_types) != n_layer or len(mlp_types) != n_layer: + raise ValueError("Beam: layer_types / mlp_layer_types must have num_hidden_layers entries") + if any(t not in ("sliding_attention", "full_attention") for t in layer_types): + raise ValueError(f"Beam: unknown layer type in {layer_types}") + if "sliding_attention" not in layer_types: + raise ValueError("Beam: expected at least one sliding_attention layer") + n_dense = 0 + while n_dense < n_layer and mlp_types[n_dense] == "dense": + n_dense += 1 + if any(t != "sparse" for t in mlp_types[n_dense:]): + raise ValueError("Beam: llama.cpp supports dense MLP layers only as a leading block") + self._n_dense_lead = n_dense + if hp.get("attention_bias", False): + raise ValueError("Beam: attention_bias=True is not supported") + self._experts: dict[tuple[int, str], dict[int, Tensor]] = {} + + def set_vocab(self): + self._set_vocab_gpt2() + # otherwise EOT is guessed from a hash-ordered scan + from transformers import AutoTokenizer + tok = AutoTokenizer.from_pretrained(self.dir_model) + ret_id = tok.convert_tokens_to_ids("<|return|>") # ty: ignore[unresolved-attribute] + if isinstance(ret_id, int) and ret_id >= 0: + self.gguf_writer.add_eot_token_id(ret_id) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hp = self.hparams + + head_dim = hp["head_dim"] + self.gguf_writer.add_rope_dimension_count(head_dim) + + self.gguf_writer.add_sliding_window(hp["sliding_window"]) + self.gguf_writer.add_sliding_window_pattern([t == "sliding_attention" for t in hp["layer_types"]]) + + self.gguf_writer.add_attn_temperature_scale(self.NOPE_SCALE_POWER) + self.gguf_writer.add_attn_temperature_length(self.NOPE_SCALE_LENGTH) + + self.gguf_writer.add_leading_dense_block_count(self._n_dense_lead) + self.gguf_writer.add_expert_feed_forward_length(hp["moe_intermediate_size"]) + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + self.gguf_writer.add_expert_weights_norm(bool(hp.get("norm_topk_prob", True))) + # equivalent to the reference's post-aggregation scaling + self.gguf_writer.add_expert_weights_scale(float(hp["routed_scaling_factor"])) + + if (softcap := hp.get("final_logit_softcapping")) is not None: + self.gguf_writer.add_final_logit_softcapping(float(softcap)) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + if name.endswith(".self_attn.gate_bias"): + name = name.replace(".self_attn.gate_bias", ".self_attn.gate_proj.bias") + return super().filter_tensors((name, gen)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + hp = self.hparams + if name.endswith(".self_attn.gate_proj.bias"): + assert tuple(data_torch.shape) == (hp["num_attention_heads"],), f"{name}: one gate bias per head expected, got {tuple(data_torch.shape)}" + elif name.endswith(".self_attn.gate_proj.weight"): + assert tuple(data_torch.shape) == (hp["num_attention_heads"] * hp["head_dim"], hp["hidden_size"]), f"{name}: {tuple(data_torch.shape)}" + elif name.endswith(".mlp.gate.e_score_correction.bias"): + assert tuple(data_torch.shape) == (hp["num_experts"],), f"{name}: {tuple(data_torch.shape)}" + elif name.endswith((".self_attn.q_norm.weight", ".self_attn.k_norm.weight")): + assert tuple(data_torch.shape) == (hp["head_dim"],), f"{name}: per-head q/k norm expected, got {tuple(data_torch.shape)}" + elif bid is not None and bid < self._n_dense_lead and ".mlp.experts." in name: + raise ValueError(f"Beam: expert tensor {name} in a dense layer") + if ".mlp.experts." in name: + assert bid is not None + n_experts = self.hparams["num_experts"] + parts = name.split(".") + xid = int(parts[parts.index("experts") + 1]) + proj = parts[parts.index("experts") + 2] + if proj not in ("gate_proj", "up_proj", "down_proj"): + raise ValueError(f"Beam: unexpected expert tensor {name}") + bucket = self._experts.setdefault((bid, proj), {}) + if xid in bucket: + raise ValueError(f"Beam: duplicate expert tensor {name}") + bucket[xid] = data_torch + if len(bucket) < n_experts: + return + del self._experts[(bid, proj)] + data = torch.stack([bucket[e] for e in range(n_experts)], dim=0) + yield from super().modify_tensors(data, f"model.layers.{bid}.mlp.experts.{proj}.weight", bid) + return + + yield from super().modify_tensors(data_torch, name, bid) + + def prepare_tensors(self): + super().prepare_tensors() + if self._experts: + missing = sorted(f"layer {b} {p} ({len(v)} experts)" for (b, p), v in self._experts.items()) + raise ValueError(f"Beam: unprocessed experts: {missing}") + logger.info("Beam: all routed experts stacked") diff --git a/conversion/clover.py b/conversion/clover.py new file mode 100644 index 000000000000..d757b64ede6b --- /dev/null +++ b/conversion/clover.py @@ -0,0 +1,41 @@ +from __future__ import annotations + +from typing import Callable, Iterable, TYPE_CHECKING + +from .base import ModelBase, gguf +from .qwen import _LinearAttentionVReorderBase + +if TYPE_CHECKING: + from torch import Tensor + + +@ModelBase.register("CloverMoeModelLM") +@ModelBase.example("Diffuspace/Clover-35B-A3B-Preview") +class CloverMoeModel(_LinearAttentionVReorderBase): + model_arch = gguf.MODEL_ARCH.CLOVER_MOE + supports_mtp_export = False + + def __init__(self, *args, **kwargs): + self.no_mtp = True + super().__init__(*args, **kwargs) + + def set_vocab(self): + self._set_vocab_gpt2() + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_expert_shared_count(self.hparams.get("num_shared_experts", 1)) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, _ = item + if name.endswith((".conv_right_weight", ".bd_softmax_logit_scale", ".bd_softmax_history_bias", ".bd_softmax_history_c")): + return None + + return super().filter_tensors(item) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.endswith(".A_log") or (name.endswith("norm.weight") and not name.endswith("linear_attn.norm.weight")): + data_torch = data_torch.float() + + yield from super().modify_tensors(data_torch, name, bid) diff --git a/conversion/deepseek.py b/conversion/deepseek.py index 817eb76128b6..581111da594d 100644 --- a/conversion/deepseek.py +++ b/conversion/deepseek.py @@ -236,6 +236,12 @@ def prepare_tensors(self): class DeepseekV2Model(TextModel): model_arch = gguf.MODEL_ARCH.DEEPSEEK2 + def _map_fp8_weight_names(self, name: str) -> tuple[str, ...]: + # MLA projections do not have runtime weight-scale support. + if name.endswith((".q_a_proj.weight", ".q_b_proj.weight", ".kv_a_proj_with_mqa.weight", ".kv_b_proj.weight")): + return () + return super()._map_fp8_weight_names(name) + # TODO @ngxson : remove this when we support MTP for deepseek models skip_mtp = True @@ -243,7 +249,7 @@ class DeepseekV2Model(TextModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - hparams: dict = ModelBase.load_hparams(self.dir_model, is_mistral_format=False) + hparams: dict = ModelBase.load_hparams(self.dir_model, is_mistral_format=self.is_mistral_format) self.origin_hf_arch = hparams.get('architectures', [None])[0] # special handling for Deepseek OCR @@ -803,9 +809,6 @@ def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: self._dsv4_mxfp4_generated = True return () - def _format_dsv4_tensor_name(self, key: gguf.MODEL_TENSOR, bid: int | None, suffix: str = ".weight") -> str: - return self.format_tensor_name(key, bid, suffix) - def _map_dsv4_tensor_name(self, name: str, bid: int | None) -> tuple[gguf.MODEL_TENSOR, str]: root_map: dict[str, tuple[gguf.MODEL_TENSOR, str]] = { "embed.weight": (gguf.MODEL_TENSOR.TOKEN_EMBD, ".weight"), @@ -879,17 +882,17 @@ def _map_dsv4_tensor_name(self, name: str, bid: int | None) -> tuple[gguf.MODEL_ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: if re.match(r"layers\.\d+\.ffn\.experts\.\d+\.w[123]\.(weight|scale)$", name): - return [] + return # hash layers route text tokens via tid2eid and image tokens via bias_vl; gate.bias is unused if name.endswith(".ffn.gate.bias") and bid is not None and bid < self.hparams["num_hash_layers"]: - return [] + return tensor_key, suffix = self._map_dsv4_tensor_name(name, bid) if tensor_key == gguf.MODEL_TENSOR.FFN_GATE_TID2EID: - return [] + return - return [(self._format_dsv4_tensor_name(tensor_key, bid, suffix), data_torch)] + yield self.format_tensor_name(tensor_key, bid, suffix), data_torch def tensor_force_quant(self, name: str, new_name: str, bid: int | None, n_dims: int) -> gguf.GGMLQuantizationType | bool: del bid # unused diff --git a/conversion/deepseek41.py b/conversion/deepseek41.py new file mode 100644 index 000000000000..53980c1d041f --- /dev/null +++ b/conversion/deepseek41.py @@ -0,0 +1,464 @@ +from __future__ import annotations + +import json +import math +import re +from pathlib import Path +from typing import Any, Callable, Iterable, TYPE_CHECKING, cast + +import numpy as np +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import LazyTorchTensor, ModelBase, TextModel, gguf +from .deepseek import DeepseekV4FlashVisionModel, DeepseekV4Model + + +# Engram hash constants from inference/engram.py, stored in the GGUF: the token map needs the HF tokenizers +# normalizers and the multipliers numpy's PCG64 stream, neither of which the runtime has. + +def _is_prime(n: int) -> bool: + if n < 2 or n % 2 == 0: + return n == 2 + return all(n % d for d in range(3, math.isqrt(n) + 1, 2)) + + +def engram_primes(n_layers: int, max_ngram_size: int, n_heads: int, vocab_size: int) -> list[list[list[int]]]: + """EngramLayout.from_args: [layer][ngram order 2..max][head] bucket moduli, never reused across layers.""" + seen: set[int] = set() + out: list[list[list[int]]] = [] + for _ in range(n_layers): + per_ngram = [] + for _ in range(max_ngram_size - 1): + sizes, cur = [], vocab_size - 1 + for _ in range(n_heads): + cand = cur + 1 + while not _is_prime(cand) or cand in seen: + cand += 1 + cur = cand + seen.add(cur) + sizes.append(cur) + per_ngram.append(sizes) + out.append(per_ngram) + return out + + +def engram_multipliers(layer_ids: list[int], max_ngram_size: int, compressed_vocab_size: int) -> list[list[int]]: + """compute_hash_multipliers: odd, bounded so that token_id * multiplier cannot overflow int64.""" + bound = max(1, (np.iinfo(np.int64).max // compressed_vocab_size) // 2) + rows = [] + for layer_id in layer_ids: + rng = np.random.default_rng(10007 * layer_id) + values = rng.integers(low=0, high=bound, size=(max_ngram_size,), dtype=np.int64) + rows.append([int(v) * 2 + 1 for v in values]) + return rows + + +def engram_compressed_token_map(tokenizer_dir: Path) -> tuple[list[int], int]: + """build_compressed_token_map: token id -> compressed id (tokens that normalize alike collapse).""" + from tokenizers import Regex, normalizers + from transformers import AutoTokenizer + + tokenizer = AutoTokenizer.from_pretrained(tokenizer_dir) + sentinel = "\ue000" + normalizer = normalizers.Sequence([ + normalizers.NFKC(), + normalizers.NFD(), + normalizers.StripAccents(), + normalizers.Lowercase(), + normalizers.Replace(Regex(r"[ \t\r\n]+"), " "), + normalizers.Replace(Regex(r"^ $"), sentinel), + normalizers.Strip(), + normalizers.Replace(sentinel, " "), + ]) + backend = tokenizer.backend_tokenizer + key_to_new: dict[str, int] = {} + lookup = [0] * len(tokenizer) + for token_id in range(len(tokenizer)): + text = backend.decode([token_id], skip_special_tokens=False) + if "\ufffd" in text: + key = backend.id_to_token(token_id) + else: + normalized = normalizer.normalize_str(text) + key = normalized if normalized else text + lookup[token_id] = key_to_new.setdefault(key, len(key_to_new)) + return lookup, len(key_to_new) + + +class _StreamedBytes: + """Raw tensor bytes produced chunk by chunk at write time (an Engram table is ~200 GB in BF16).""" + def __init__(self, shape: tuple[int, ...], chunks: Callable[[], Iterable[np.ndarray]]): + self.shape = shape + self.dtype = np.dtype(np.uint8) + self.nbytes = int(np.prod(shape)) + self._chunks = chunks + + def tofile(self, fout) -> None: + written = 0 + for chunk in self._chunks(): + chunk = np.ascontiguousarray(chunk, dtype=np.uint8) + chunk.tofile(fout) + written += chunk.nbytes + if written != self.nbytes: + raise ValueError(f"streamed {written} bytes, expected {self.nbytes}") + + def byteswap(self, inplace: bool = False): + raise NotImplementedError("streamed tensors are written little-endian only") + + +def _e8m0_check(scale_u8: np.ndarray, name: str) -> None: + # e4m3 (|x| in [2^-9, 448]) * 2^(e - 127) is exact in BF16 for e in [3, 246] + if scale_u8.size and (int(scale_u8.min()) < 3 or int(scale_u8.max()) > 246): + raise ValueError(f"{name}: E8M0 scale exponents outside [3, 246], the dequantized values would not be exact") + + +@ModelBase.register("DeepseekV41ForCausalLM") +class DeepseekV41Model(DeepseekV4Model): + """DeepSeek-V4.1 text model, lossless: FP8 (e4m3, 32x32 ue8m0 blocks) linears dequantized to BF16 (F32 with + --outtype f32), routed experts copied bit-exact as MXFP4, Engram tables (e4m3 rows, one e8m0 scale per 32) as the + exact BF16 lookup (F32 with --outtype f32), router and Engram gate F32. DSpark (mtp.*) is not converted here + (--dspark, DeepseekV41DSparkModel); the vision tower goes to an mmproj (--mmproj, DeepseekV41VisionModel). + The Engram tables of all layers are written as one per_layer_token_embd (rows concatenated in layer order) with + the PLE keys of qwen4exp: absolute head offsets and bucket counts, so the runtime can read it lazily.""" + model_arch = gguf.MODEL_ARCH.DEEPSEEK41 + supports_mtp_export = False + + _ENGRAM_EMBED_RE = re.compile(r"layers\.(\d+)\.engram\.embed\.(weight|scale)$") + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + self.hparams.setdefault("num_hash_layers", 0) # no hash-routed layers in V4.1 + self._f32 = self.ftype == gguf.LlamaFileType.ALL_F32 + qc = self.hparams.get("quantization_config") or {} + self._fp8_block = tuple(qc.get("weight_block_size") or (32, 32)) + if qc.get("scale_fmt", "ue8m0") != "ue8m0": + raise ValueError(f"unsupported FP8 scale format {qc.get('scale_fmt')!r}") + if self.hparams.get("gate_temp", 1.0) != 1.0: + raise ValueError("gate_temp != 1 is not supported (the router logits would need dividing by it)") + + # V4.1 does not use the DeepSeek-V4 template; a template shipped with the model is still added by set_vocab + self.gguf_writer.remove_key(gguf.Keys.Tokenizer.CHAT_TEMPLATE) + + def index_tensors(self, remote_hf_model_id: str | None = None) -> dict[str, Callable[[], Tensor]]: + # num_hidden_layers lives in text_config, which is merged only after indexing; MTP stages are skipped anyway + return TextModel.index_tensors(self, remote_hf_model_id=remote_hf_model_id) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hp = self.hparams + w = self.gguf_writer + w.add_attention_kv_source_layers(hp["kv_source_layer_ids"]) + w.add_indexer_source_layers(hp["index_source_layer_ids"]) + if hp.get("candidate_source_layer_id", -1) >= 0: + w.add_indexer_candidate_source_layer(hp["candidate_source_layer_id"]) + w.add_indexer_candidate_top_k_blocks(hp["candidate_topk_blocks"]) + w.add_indexer_candidate_block_size(hp["candidate_block_size"]) + + # GGUF cannot hold empty arrays: the Engram keys are omitted when the model has no Engram layers + layer_ids = list(hp.get("engram_layer_ids") or []) + if layer_ids: + max_ngram, n_heads = hp["engram_max_ngram_size"], hp["engram_n_heads"] + primes = engram_primes(len(layer_ids), max_ngram, n_heads, hp["engram_vocab_size"]) + for li, layer_primes in enumerate(primes): + if sum(p for per in layer_primes for p in per) != hp["engram_num_embeddings"][li]: + raise ValueError(f"engram layer {layer_ids[li]}: prime sum != num_embeddings") + token_map, cvocab = engram_compressed_token_map(self.dir_model) + if cvocab != hp["engram_compressed_vocab_size"] or len(token_map) != hp["vocab_size"]: + raise ValueError(f"compressed token map ({len(token_map)} -> {cvocab}) does not match the config") + # absolute row offsets into the concatenated table + sizes = [p for layer in primes for per in layer for p in per] + offsets = [sum(sizes[:i]) for i in range(len(sizes))] + w.add_key_value(gguf.Keys.PerLayerEmbedding.LAYERS.format(arch=w.arch), layer_ids, + gguf.GGUFValueType.ARRAY, gguf.GGUFValueType.UINT32) + w.add_ple_ngram_size(max_ngram) + w.add_ple_heads_per_ngram(n_heads) + w.add_embedding_length_per_layer_input(hp["engram_head_dim"]) + w.add_ple_layer_multipliers([m for row in engram_multipliers(layer_ids, max_ngram, cvocab) for m in row]) + w.add_ple_head_offsets(offsets) + w.add_ple_head_vocab_sizes(sizes) + w.add_engram_pad_token_id(hp["engram_pad_token_id"]) + w.add_engram_token_map(token_map) + + def dequant_model(self): + bo, bi = self._fp8_block + + def dequant(weight: Tensor, scale: Tensor) -> Tensor: + out_f, in_f = weight.shape + s = self._e8m0_to_float(scale).repeat_interleave(bo, 0)[:out_f].repeat_interleave(bi, 1)[:, :in_f] + return weight.float() * s + + for name in [n for n in self.model_tensors if n.endswith(".scale") and not self._ENGRAM_EMBED_RE.match(n)]: + weight_name = name.removesuffix(".scale") + ".weight" + if weight_name not in self.model_tensors or self.model_tensors[weight_name]().dtype not in self._float8_dtypes(): + continue + w, s = self.model_tensors[weight_name], self.model_tensors.pop(name) + out_f, in_f = w().shape + if tuple(s().shape) != (-(-out_f // bo), -(-in_f // bi)): + raise ValueError(f"{weight_name}: scale shape {tuple(s().shape)} does not match {(bo, bi)} blocks") + _e8m0_check(LazyTorchTensor.to_eager(s()).view(torch.uint8).numpy(), name) + self.model_tensors[weight_name] = lambda w=w, s=s: dequant(w(), s()) + self._dsv4_fp8_dequantized.add(weight_name) + + def _tensor_part(self, name: str) -> Path: + index = self.dir_model / "model.safetensors.index.json" + if not index.is_file(): + return self.dir_model / "model.safetensors" + with open(index, "r", encoding="utf-8") as f: + return self.dir_model / json.load(f)["weight_map"][name] + + def _write_mxfp4_experts(self, bid: int, proj: str, key: gguf.MODEL_TENSOR, n_expert: int | None = None) -> None: + n_expert = self.hparams["n_routed_experts"] if n_expert is None else n_expert + names = [f"layers.{bid}.ffn.experts.{e}.{proj}" for e in range(n_expert)] + pairs = [(self.model_tensors.pop(n + ".weight"), self.model_tensors.pop(n + ".scale")) for n in names] + rows, packed_cols = pairs[0][0]().shape + + def chunks() -> Iterable[np.ndarray]: + for w, s in pairs: + yield self.repack_mxfp4_blocks(LazyTorchTensor.to_eager(w()), LazyTorchTensor.to_eager(s())) + data = cast(np.ndarray, _StreamedBytes((len(pairs), rows, packed_cols * 2 // 32 * 17), chunks)) + self.gguf_writer.add_tensor(self.format_tensor_name(key, bid), data, raw_dtype=gguf.GGMLQuantizationType.MXFP4) + + def _write_engram_tables(self, layer_ids: list[int]) -> None: + # official lookup e4m3 * 2^(e8m0 - 127), exact in BF16 + parts, dim = [], None + for bid in layer_ids: + wn, sn = f"layers.{bid}.engram.embed.weight", f"layers.{bid}.engram.embed.scale" + rows, d = self.model_tensors.pop(wn)().shape + if d % 32 != 0 or tuple(self.model_tensors.pop(sn)().shape) != (rows, d // 32) or d != (dim or d): + raise ValueError(f"{wn}: expected one e8m0 scale per 32 elements and the same width in every layer") + if rows != self.hparams["engram_num_embeddings"][len(parts)]: + raise ValueError(f"{wn}: {rows} rows, config says {self.hparams['engram_num_embeddings'][len(parts)]}") + dim = d + parts.append((wn, sn, rows, self._tensor_part(wn), self._tensor_part(sn))) + assert dim is not None + name = self.format_tensor_name(gguf.MODEL_TENSOR.PER_LAYER_TOKEN_EMBD) + n_rows = sum(p[2] for p in parts) + + def chunks() -> Iterable[np.ndarray]: + from safetensors import safe_open + for wn, sn, rows, wpart, spart in parts: + with safe_open(wpart, framework="pt") as fw, safe_open(spart, framework="pt") as fs: + ws, ss = fw.get_slice(wn), fs.get_slice(sn) + for r0 in range(0, rows, 1 << 18): + q = ws[r0:r0 + (1 << 18)].view(torch.uint8).reshape(-1, 32) + e = ss[r0:r0 + (1 << 18)].view(torch.uint8).reshape(-1, 1) + _e8m0_check(e.numpy(), sn) + v = (q.view(torch.float8_e4m3fn).float() * torch.exp2(e.float() - 127)).reshape(-1, dim) + yield (v if self._f32 else v.bfloat16()).view(torch.uint8).numpy() + qt = gguf.GGMLQuantizationType.F32 if self._f32 else gguf.GGMLQuantizationType.BF16 + data = cast(np.ndarray, _StreamedBytes((n_rows, dim * (4 if self._f32 else 2)), chunks)) + self.gguf_writer.add_tensor(name, data, raw_dtype=qt) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + if not self._dsv4_mxfp4_generated: + for bid in range(self.block_count): + self._write_mxfp4_experts(bid, "w1", gguf.MODEL_TENSOR.FFN_GATE_EXP) + self._write_mxfp4_experts(bid, "w2", gguf.MODEL_TENSOR.FFN_DOWN_EXP) + self._write_mxfp4_experts(bid, "w3", gguf.MODEL_TENSOR.FFN_UP_EXP) + if self.hparams.get("engram_layer_ids"): + self._write_engram_tables(list(self.hparams["engram_layer_ids"])) + self._dsv4_mxfp4_generated = True + return () + + _LAYER_MAP: dict[str, tuple[gguf.MODEL_TENSOR, str]] = { + "attn.indexer.wk.weight": (gguf.MODEL_TENSOR.INDEXER_ATTN_K, ".weight"), + "attn.indexer.k_norm.weight": (gguf.MODEL_TENSOR.INDEXER_K_NORM, ".weight"), + "engram.wkv.weight": (gguf.MODEL_TENSOR.ENGRAM_KV, ".weight"), + } + + def _map_dsv4_tensor_name(self, name: str, bid: int | None) -> tuple[gguf.MODEL_TENSOR, str]: + m = re.match(r"layers\.\d+\.(.+)$", name) + if m is not None and m.group(1) in self._LAYER_MAP: + return self._LAYER_MAP[m.group(1)] + return super()._map_dsv4_tensor_name(name, bid) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.endswith(".engram.k_weight"): + return # folded into engram_gate + if name.endswith(".engram.q_weight"): + # Engram gate weight = q_weight * k_weight (bf16 * bf16 is exact in f32) + k = self.model_tensors[name.removesuffix("q_weight") + "k_weight"] + yield self.format_tensor_name(gguf.MODEL_TENSOR.ENGRAM_GATE, bid), data_torch.float() * k().float() + return + yield from super().modify_tensors(data_torch, name, bid) + + def tensor_force_quant(self, name: str, new_name: str, bid: int | None, n_dims: int) -> gguf.GGMLQuantizationType | bool: + if new_name.endswith((".engram_gate.weight", ".ffn_gate_inp.weight")) or name in self._dsv4_f32_tensors: + return gguf.GGMLQuantizationType.F32 + if n_dims >= 2 and (name in self._dsv4_fp8_dequantized or name in self._dsv4_bf16_tensors): + return gguf.GGMLQuantizationType.F32 if self._f32 else gguf.GGMLQuantizationType.BF16 + return False + + +class DeepseekV41DSparkModel(DeepseekV41Model): + """DeepSeek-V4.1 DSpark speculative draft (mtp.0..2 of the checkpoint) as a DFLASH GGUF (`--dspark`). + + Layout = the V4 DSpark draft (conversion/deepseek.py DeepseekV4DSparkModel) with V4.1's differences flagged by + `dflash.hyper_connection.single_pass`: stages blk.0..2 (MXFP4 experts bit-exact, dense BF16), mtp.0.main_proj / + main_norm -> fc / enc.output_norm, mtp.2.norm -> output_norm, markov_head.embed / head -> markov_w1 / markov_w2, + confidence_head.proj -> conf_proj (F32), no hc_head. Token embeddings and the lm head are the target's (shared at + runtime through ctx_other). target_layers are the V4.1 ids as-is: the draft reads the attention input of those + layers, which is what llama_set_embeddings_layer_inp extracts. + """ + model_arch = gguf.MODEL_ARCH.DFLASH + mtp_only = True + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + hp = self.hparams + self._n_main = hp["num_hidden_layers"] + self._n_stage = hp["num_nextn_predict_layers"] + if self._n_stage <= 0 or "dspark_block_size" not in hp: + raise ValueError("DeepSeek-V4.1 DSpark export needs num_nextn_predict_layers > 0 and the dspark_* config") + # stages keep main-model block ids (mtp.M -> layers.n_main+M); format_tensor_name() maps them back + self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self._n_stage) + + def index_tensors(self, remote_hf_model_id: str | None = None) -> dict[str, Callable[[], Tensor]]: + hp = {**self.hparams, **self.hparams.get("text_config", {})} # text_config is merged only after indexing + type(self)._dsv4_main_layers = hp["num_hidden_layers"] + type(self)._dsv4_nextn_layers = hp.get("num_nextn_predict_layers", 0) + return TextModel.index_tensors(self, remote_hf_model_id=remote_hf_model_id) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + m = re.match(r"mtp\.(\d+)\.(.+)$", name) + if m is None: + return None # shared with the target at runtime + stage, rest = int(m.group(1)), m.group(2) + assert cls._dsv4_main_layers is not None + if stage >= cls._dsv4_nextn_layers: + raise ValueError(f"Unexpected DSpark stage {stage}") + if rest.startswith(("markov_head.", "confidence_head.")): + return f"dspark.{rest}", gen + return f"layers.{cls._dsv4_main_layers + stage}.{rest}", gen + + def format_tensor_name(self, key: gguf.MODEL_TENSOR, bid: int | None = None, suffix: str = ".weight") -> str: + if bid is not None and bid >= self._n_main: + bid -= self._n_main + return super().format_tensor_name(key, bid, suffix) + + def set_vocab(self): + super().set_vocab() + self.gguf_writer.add_mask_token_id(self.hparams["dspark_noise_token_id"]) + + def set_gguf_parameters(self): + hp = self.hparams + n = self._n_stage + w = self.gguf_writer + w.add_block_count(n) + w.add_context_length(hp["max_position_embeddings"]) + w.add_embedding_length(hp["hidden_size"]) + w.add_feed_forward_length(hp["moe_intermediate_size"]) + w.add_head_count(hp["num_attention_heads"]) + w.add_head_count_kv(1) + w.add_key_length(hp["head_dim"]) + w.add_value_length(hp["head_dim"]) + w.add_rope_dimension_count(hp["qk_rope_head_dim"]) + # compress-ratio-0 layers: plain rope at rope_theta, no YaRN + w.add_rope_freq_base(float(hp["rope_theta"])) + w.add_layer_norm_rms_eps(hp["rms_norm_eps"]) + w.add_q_lora_rank(hp["q_lora_rank"]) + w.add_sliding_window(hp["sliding_window"]) + w.add_expert_count(hp["dspark_n_routed_experts"]) + w.add_expert_used_count(hp["dspark_num_experts_per_tok"]) + w.add_expert_feed_forward_length(hp["moe_intermediate_size"]) + w.add_expert_shared_count(hp["n_shared_experts"]) + w.add_expert_weights_scale(hp["routed_scaling_factor"]) + w.add_expert_weights_norm(hp["norm_topk_prob"]) + w.add_expert_gating_func(gguf.ExpertGatingFuncType.SQRTSOFTPLUS) + w.add_swiglu_clamp_exp([hp["swiglu_limit"]] * n) + w.add_swiglu_clamp_shexp([hp["swiglu_limit"]] * n) + w.add_attention_output_group_count(hp["o_groups"]) + w.add_attention_output_lora_rank(hp["o_lora_rank"]) + w.add_attention_compress_ratios([0] * n) + w.add_hyper_connection_count(hp["hc_mult"]) + w.add_hyper_connection_sinkhorn_iterations(hp["hc_sinkhorn_iters"]) + w.add_hyper_connection_epsilon(hp["hc_eps"]) + w.add_hyper_connection_single_pass(True) + w.add_block_size(hp["dspark_block_size"]) + w.add_target_layers(hp["dspark_target_layer_ids"]) + w.add_sample_from_anchor(True) + w.add_has_confidence_head(True) + w.add_file_type(self.ftype) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + # no Engram tables in the draft + if not self._dsv4_mxfp4_generated: + n_expert = self.hparams["dspark_n_routed_experts"] + for bid in range(self._n_main, self._n_main + self._n_stage): + self._write_mxfp4_experts(bid, "w1", gguf.MODEL_TENSOR.FFN_GATE_EXP, n_expert) + self._write_mxfp4_experts(bid, "w2", gguf.MODEL_TENSOR.FFN_DOWN_EXP, n_expert) + self._write_mxfp4_experts(bid, "w3", gguf.MODEL_TENSOR.FFN_UP_EXP, n_expert) + self._dsv4_mxfp4_generated = True + return () + + _DSPARK_ROOT: dict[str, gguf.MODEL_TENSOR] = { + "main_proj.weight": gguf.MODEL_TENSOR.FC, + "main_norm.weight": gguf.MODEL_TENSOR.ENC_OUTPUT_NORM, + "norm.weight": gguf.MODEL_TENSOR.OUTPUT_NORM, + "dspark.markov_head.embed.weight": gguf.MODEL_TENSOR.DSPARK_MARKOV_W1, + "dspark.markov_head.head.weight": gguf.MODEL_TENSOR.DSPARK_MARKOV_W2, + "dspark.confidence_head.proj.weight": gguf.MODEL_TENSOR.DSPARK_CONF_PROJ, + } + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.endswith(".ffn.gate.bias_vl"): + return + if name in self._DSPARK_ROOT: + yield self.format_tensor_name(self._DSPARK_ROOT[name], None), data_torch + return + m = re.match(r"layers\.\d+\.(main_proj\.weight|main_norm\.weight|norm\.weight)$", name) + if m is not None: + yield self.format_tensor_name(self._DSPARK_ROOT[m.group(1)], None), data_torch + return + yield from super().modify_tensors(data_torch, name, bid) + + def tensor_force_quant(self, name: str, new_name: str, bid: int | None, n_dims: int) -> gguf.GGMLQuantizationType | bool: + if new_name == "conf_proj.weight": + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + +@ModelBase.register("DeepseekV41ForCausalLM") +@ModelBase.example("deepseek-ai/DeepSeek-V4.1-Flash-1017") +class DeepseekV41VisionModel(DeepseekV4FlashVisionModel): + """DeepSeek-V4.1 vision tower (projector deepseek41v): the V4-Flash-Vision ViT + 3x3 aligner, with the V4.1 token + block ([START] ([IMAGE]*w [NEWLINE])*h [END], no pads) and resize plan. ref: inference/vision.py, + inference/image_processor.py of deepseek-ai/DeepSeek-V4.1-Flash-1017. The checkpoint config is HF-style + (vision_config); image_start / image_end / image_newline are written like V4's sentinels, there is no image_pad.""" + + def get_vision_config(self) -> dict[str, Any] | None: + vc = self.global_config.get("vision_config") + if not vc or vc.get("num_hidden_layers", 0) == 0: + raise ValueError("DeepseekV41VisionModel requires vision_config.num_hidden_layers > 0") + return { + "num_hidden_layers": vc["num_hidden_layers"], + "hidden_size": vc["hidden_size"], + "num_attention_heads": vc["num_attention_heads"], + "intermediate_size": vc["intermediate_size"], + "patch_size": vc["patch_size"], + # dynamic resolution; only used for compat / warmup + "image_size": vc["patch_size"] * vc["downsample_ratio"] * 16, + "rope_theta": vc.get("rope_theta", 10000.0), + "downsample_ratio": vc["downsample_ratio"], + "min_pixels": vc["min_pixels"], + "max_image_tokens": vc["max_image_tokens"], + "max_wh_ratio": vc.get("max_wh_ratio"), + } + + def set_gguf_parameters(self): + assert self.hparams_vision is not None + super(DeepseekV4FlashVisionModel, self).set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.DEEPSEEK41V) + # pytorch default eps (vision.py), not the LLM rms_norm_eps (1e-20) + self.gguf_writer.add_vision_attention_layernorm_eps(1e-6) + self.gguf_writer.add_vision_use_silu(True) + self.gguf_writer.add_vision_projector_scale_factor(self.hparams_vision["downsample_ratio"]) + self.gguf_writer.add_vision_min_pixels(self.hparams_vision["min_pixels"]) + # hardcoded in clip.cpp (PROJECTOR_TYPE_DEEPSEEK41V); add GGUF keys if a later model differs + assert self.hparams_vision["max_image_tokens"] == 1024, self.hparams_vision["max_image_tokens"] + assert self.hparams_vision["max_wh_ratio"] is None, self.hparams_vision["max_wh_ratio"] + assert self.hparams_vision["rope_theta"] == 10000, self.hparams_vision["rope_theta"] diff --git a/conversion/flint.py b/conversion/flint.py new file mode 100644 index 000000000000..a69314a9bcc8 --- /dev/null +++ b/conversion/flint.py @@ -0,0 +1,38 @@ +from __future__ import annotations + +from .base import ModelBase, gguf +from .qwen import Qwen2MoeModel + + +@ModelBase.register("FlintForCausalLM") +@ModelBase.example("RecursiveSI/flint") +class FlintModel(Qwen2MoeModel): + model_arch = gguf.MODEL_ARCH.FLINT + + def set_gguf_parameters(self): + super().set_gguf_parameters() + dense = self.hparams["mlp_only_layers"] + if dense != list(range(len(dense))): + raise ValueError("Flint dense layers must precede the MoE layers") + self.gguf_writer.add_leading_dense_block_count(len(dense)) + self.gguf_writer.add_expert_shared_count( + self.hparams["shared_expert_intermediate_size"] // self.hparams["moe_intermediate_size"] + ) + self.gguf_writer.add_expert_weights_norm(self.hparams["norm_topk_prob"]) + self.gguf_writer.add_expert_weights_scale(1.0) + self.gguf_writer.add_sliding_window(self.hparams["sliding_window"]) + self.gguf_writer.add_sliding_window_pattern([ + kind == "sliding_attention" for kind in self.hparams["layer_types"] + ]) + self.gguf_writer.add_rope_pattern([ + i not in self.hparams["no_rope_layer_indices"] for i in range(self.block_count) + ]) + + def modify_tensors(self, data_torch, name, bid): + if name.endswith(".softmax_offset"): + name += ".weight" + if name.endswith(".gate.expert_bias"): + if not self.hparams["router_expert_bias"]: + return + name += ".bias" + yield from super().modify_tensors(data_torch, name, bid) diff --git a/conversion/gemma.py b/conversion/gemma.py index 924d8e784a17..ab2d90610d60 100644 --- a/conversion/gemma.py +++ b/conversion/gemma.py @@ -999,6 +999,8 @@ def set_gguf_parameters(self): assert self.hparams_vision is not None self.gguf_writer.add_clip_vision_projector_type(gguf.VisionProjectorType.GEMMA4V) self.gguf_writer.add_vision_attention_layernorm_eps(self.hparams_vision.get("layer_norm_eps", 1e-6)) + assert self.hparams_vision.get("hidden_activation", "gelu_pytorch_tanh") == "gelu_pytorch_tanh" + self.gguf_writer.add_vision_use_gelu(True) # audio params if self.has_audio_encoder: diff --git a/conversion/granite.py b/conversion/granite.py index 796d37cca269..4c6c5a0e4cc5 100644 --- a/conversion/granite.py +++ b/conversion/granite.py @@ -8,7 +8,7 @@ if TYPE_CHECKING: from torch import Tensor -from .base import MmprojModel, ModelBase, gguf, logger +from .base import MmprojModel, ModelBase, gguf, jinja_str_or_json, logger from .llama import LlamaModel from .mamba import Mamba2Model @@ -239,8 +239,21 @@ class GraniteSwitchModel(GraniteMoeModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - # the weightless switch reserves one cache slot: one fewer block than num_hidden_layers - self.block_count = self.block_count - 1 + # The weightless switch layer(s) are counted in num_hidden_layers but carry no tensors. + # The count is not fixed, nor is it present in hparams, so we derive it here based on tensor block names. + layer_ids = { + int(m.group(1)) + for name in self.model_tensors + if (m := re.match(r"(?:model\.)?layers\.(\d+)\.", name)) + } + if not layer_ids: + raise ValueError("graniteswitch: no 'model.layers.N' tensors found in checkpoint") + n_weight_layers = max(layer_ids) + 1 + logger.info( + "gguf: (graniteswitch) num_hidden_layers %s counts %d weightless switch layer(s); using %d blocks", + self.hparams["num_hidden_layers"], self.block_count - n_weight_layers, n_weight_layers, + ) + self.block_count = n_weight_layers self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self.block_count) self._n_adapters = int(self.hparams["num_adapters"]) @@ -271,10 +284,40 @@ def set_gguf_parameters(self): self.gguf_writer.add_adapter_lora_rank(self._max_lora_rank) self.gguf_writer.add_adapter_token_ids_activate(self.hparams["adapter_token_ids"]) self.gguf_writer.add_adapter_token_ids_substitute(self.hparams["adapter_substitute_token_ids"]) + if self._has_decision_adapter(): + self.gguf_writer.add_decision_type(gguf.DecisionType.GRANITE_SWITCH) router_gain = float(self.hparams.get("control_token_gain", 15.0)) self.gguf_writer.add_adapter_router_gain(router_gain) logger.info("gguf: (graniteswitch) num_adapters=%s max_lora_rank=%s n_slots=%s router_gain=%s", self._n_adapters, self._max_lora_rank, self._n_slots, router_gain) + def _has_decision_adapter(self) -> bool: + return "decision" in self.hparams.get("adapter_names", []) + + def set_vocab(self): + super().set_vocab() + if self._has_decision_adapter(): + systemone_template = self._systemone_template() + logger.info("System One Template: %s", systemone_template) + self.gguf_writer.add_chat_template([{"name": "systemone", "template": systemone_template}]) + + def _systemone_template(self) -> str: + # prompt of the decision aLoRA: a state turn, then a question turn that opens with the control token + # (it replaces the first token of "### DECISION"), the answer is the label token that comes next + description = jinja_str_or_json("o.description") + option = ( + "{% if type != 'noul' %}{{ o.label }}: {% if o.description %}" + description + "{% endif %}" + "{% elif o.key == 'true' %}A: {% if o.description %}" + description + "{% else %}The statement is true.{% endif %}" + "{% else %}B: {% if o.description %}" + description + "{% else %}The statement is false.{% endif %}{% endif %}" + ) + return ( + "<|start_of_role|>user<|end_of_role|>State:\n" + jinja_str_or_json("state") + "<|end_of_text|>\n" + "<|start_of_role|>user<|end_of_role|><|decision|> DECISION\nQuestion:\n" + jinja_str_or_json("instructions") + + "{% if type == 'score' %} Rate along the ordered levels below (lowest first).{% endif %}" + "{{ '\n\nOptions:\n' }}" + "{% for o in options %}" + option + "{{ '\n' }}{% endfor %}" + "{{ '\nReply with exactly one option label.<|end_of_text|>\n<|start_of_role|>assistant<|end_of_role|>' }}" + ) + def _lora_a(self, data: Tensor) -> Tensor: # on-disk A: [n_adapters, 1, max_rank, in] -> [n_adapters+1, max_rank, in] a = data.squeeze(1) diff --git a/conversion/h2o_lightning.py b/conversion/h2o_lightning.py new file mode 100644 index 000000000000..764da4b970dc --- /dev/null +++ b/conversion/h2o_lightning.py @@ -0,0 +1,96 @@ +from __future__ import annotations + +import json + +from pathlib import Path +from typing import Any + +from .base import ModelBase, gguf, logger +from .qwen import Qwen3_5TextModel +from .qwen3vl import Qwen3VLVisionModel + + +def _is_h2o_lightning_checkpoint(dir_model: Path) -> bool: + return (dir_model / "h2o_lightning_shim.py").is_file() and (dir_model / "serve_config.json").is_file() + + +@ModelBase.register_hparams_loader(_is_h2o_lightning_checkpoint) +def _load_h2o_lightning_hparams(dir_model: Path) -> dict[str, Any]: + logger.info("gguf: detected H2O-Lightning checkpoint") + hparams = ModelBase.load_hparams(dir_model, False, guess=False) + hparams["architectures"] = ["H2OLightningModel"] + return hparams + + +@ModelBase.register("H2OLightningModel") +@ModelBase.example("h2oai/h2o-lightning-4b") +class H2OLightningModel(Qwen3_5TextModel): + model_arch = gguf.MODEL_ARCH.QWEN35 + + # prompt and calibration follow serve_config.json and h2o_lightning_shim.py of the model repo + # the state budget is hard-coded in server-decision.cpp + _MAX_STATE_TOKENS = 32000 + _DEFAULT_INSTRUCTIONS = "Answer the question below." + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + with open(self.dir_model / "serve_config.json", "r", encoding="utf-8") as f: + self._serve_config = json.load(f) + prompt = self._serve_config["prompt"] + expected = { + "state_compact": (prompt.get("state_compact", True), True), + "max_state_tokens": (prompt.get("max_state_tokens"), self._MAX_STATE_TOKENS), + "layout": (prompt.get("layout", "plain"), "plain"), + "chat_template": (prompt.get("chat_template", True), True), + "enable_thinking": (prompt.get("enable_thinking", False), False), + } + for name, (got, want) in expected.items(): + if got != want: + raise ValueError(f"serve_config.json: {name} is {got!r}, the h2o-lightning decision type expects {want!r}") + + def get_vocab_base_pre(self, tokenizer) -> str: + # transformers loads this checkpoint as Qwen2Tokenizer: the model was trained and is served with the Qwen2 split + pre = super().get_vocab_base_pre(tokenizer) + if pre != "qwen35": + raise ValueError(f"expected the Qwen3.5 tokenizer, got pre-tokenizer {pre!r}") + return "qwen2" + + def set_vocab(self): + super().set_vocab() + self.gguf_writer.add_chat_template([{"name": "systemone", "template": self._systemone_template()}]) + + def _systemone_template(self) -> str: + # the server gives the template texts rendered as the shim renders them, it only lays them out + prompt = self._serve_config["prompt"] + nl = "{{ '\\n' }}" + description = ( + "{% if type == 'noul' %}" + "{% if o.description %}{{ o.description }}{% elif o.key == 'true' %}the statement holds{% else %}it does not{% endif %}" + "{% elif o.description is none %}{{ o.key }}{% else %}{{ o.description }}{% endif %}" + ) + user = ( + "{% set user %}record: {{ state }}" + nl + + "question: {{ instructions if instructions else '" + self._DEFAULT_INSTRUCTIONS + "' }}" + nl + + "options:{% for o in options %}" + nl + "{{ o.label | trim }}) {{ o.key }}: " + description + "{% endfor %}{% endset %}" + ) + return ( + "<|im_start|>system" + nl + prompt["system"].strip() + "<|im_end|>" + nl + + "<|im_start|>user" + nl + "{% for image in images %}{{ image }}{% endfor %}" + user + "{{ user | trim }}<|im_end|>" + nl + + "<|im_start|>assistant" + nl + "<think>{{ '\\n\\n' }}</think>{{ '\\n\\n' }}" + prompt["prefill"] + ) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_decision_type(gguf.DecisionType.H2O_LIGHTNING) + # the answer follows "Answer:", so the token of a label has a leading space + cfg = self._serve_config + self.gguf_writer.add_decision_labels([" " + label for label in cfg["labels"][:cfg.get("max_options", len(cfg["labels"]))]]) + for name in ("choice", "noul", "score"): + self.gguf_writer.add_decision_temperature(name, self._serve_config["temperature"][name]) + # a request with images has this temperature for all question types + self.gguf_writer.add_decision_temperature("image", self._serve_config["image"]["temperature"]) + + +@ModelBase.register("H2OLightningModel") +class H2OLightningVisionModel(Qwen3VLVisionModel): + pass diff --git a/conversion/kolibri1.py b/conversion/kolibri1.py new file mode 100644 index 000000000000..845501f4ef38 --- /dev/null +++ b/conversion/kolibri1.py @@ -0,0 +1,23 @@ +from __future__ import annotations + +from .afmoe import AfmoeModel +from .base import ModelBase, gguf + + +@ModelBase.register("Kolibri1ForCausalLM") +@ModelBase.example("Aleph-Alpha/Kolibri-1") +class Kolibri1Model(AfmoeModel): + model_arch = gguf.MODEL_ARCH.KOLIBRI1 + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + # AfmoeModel reads these keys, this config stores the same values under other names + self.hparams["num_shared_experts"] = 1 + self.hparams["route_norm"] = self.hparams["norm_topk_prob"] + self.hparams["intermediate_size"] = self.hparams["moe_intermediate_size"] + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_expert_shared_feed_forward_length(self.hparams["shared_expert_intermediate_size"]) + self.gguf_writer.add_sliding_window_pattern([t == "sliding_attention" for t in self.hparams["layer_types"]]) + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) diff --git a/conversion/lfm2.py b/conversion/lfm2.py index 113c911168d9..61b7a0b2b9f0 100644 --- a/conversion/lfm2.py +++ b/conversion/lfm2.py @@ -15,25 +15,30 @@ from .gemma import ConformerAudioModel +def lfm2_feed_forward_length(hparams: dict[str, Any]) -> int: + ff_dim = hparams.get("block_ff_dim", hparams.get("intermediate_size")) + assert ff_dim is not None + auto_adjust_ff_dim = hparams["block_auto_adjust_ff_dim"] + ffn_dim_multiplier = hparams["block_ffn_dim_multiplier"] + multiple_of = hparams["block_multiple_of"] + + if auto_adjust_ff_dim: + ff_dim = int(2 * ff_dim / 3) + # custom dim factor multiplier + if ffn_dim_multiplier is not None: + ff_dim = int(ffn_dim_multiplier * ff_dim) + ff_dim = multiple_of * ((ff_dim + multiple_of - 1) // multiple_of) + + return ff_dim + + @ModelBase.register("Lfm2ForCausalLM", "LFM2ForCausalLM") @ModelBase.example("LiquidAI/LFM2-1.2B", "LiquidAI/LFM2.5-350M") class LFM2Model(TextModel): model_arch = gguf.MODEL_ARCH.LFM2 def _add_feed_forward_length(self): - ff_dim = self.find_hparam(["block_ff_dim", "intermediate_size"]) - auto_adjust_ff_dim = self.hparams["block_auto_adjust_ff_dim"] - ffn_dim_multiplier = self.hparams["block_ffn_dim_multiplier"] - multiple_of = self.hparams["block_multiple_of"] - - if auto_adjust_ff_dim: - ff_dim = int(2 * ff_dim / 3) - # custom dim factor multiplier - if ffn_dim_multiplier is not None: - ff_dim = int(ffn_dim_multiplier * ff_dim) - ff_dim = multiple_of * ((ff_dim + multiple_of - 1) // multiple_of) - - self.gguf_writer.add_feed_forward_length(ff_dim) + self.gguf_writer.add_feed_forward_length(lfm2_feed_forward_length(self.hparams)) def set_gguf_parameters(self): # set num_key_value_heads only for attention layers @@ -72,7 +77,9 @@ def _is_d1_checkpoint(dir_model: Path) -> bool: if not (dir_model / "config.json").is_file(): return False with open(dir_model / "config.json", encoding="utf-8") as f: - return json.load(f).get("auto_map", {}).get("AutoModel", "").endswith(".D1Model") + config = json.load(f) + # d1 on LFM3 is converted by conversion/lfm3.py + return config.get("auto_map", {}).get("AutoModel", "").endswith(".D1Model") and not config.get("model_type", "").startswith("lfm3") @ModelBase.register_hparams_loader(_is_d1_checkpoint) @@ -374,6 +381,16 @@ def set_gguf_parameters(self): if resize_algo is None: raise ValueError(f"unsupported resample: {resample}") self.gguf_writer.add_vision_image_resize_algo(resize_algo) + # tiling params from processor_config.json (do_image_splitting=False -> single tile, i.e. no tiling) + preproc = self.preprocessor_config + if preproc.get("do_image_splitting", True): + self.gguf_writer.add_vision_preproc_min_tiles(preproc.get("min_tiles", 2)) + self.gguf_writer.add_vision_preproc_max_tiles(preproc.get("max_tiles", 10)) + else: + self.gguf_writer.add_vision_preproc_min_tiles(1) + self.gguf_writer.add_vision_preproc_max_tiles(1) + self.gguf_writer.add_vision_preproc_tile_size(preproc.get("tile_size", 512)) + self.gguf_writer.add_vision_preproc_max_pixels_tolerance(preproc.get("max_pixels_tolerance", 2.0)) @classmethod def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: diff --git a/conversion/lfm3.py b/conversion/lfm3.py new file mode 100644 index 000000000000..a0287d4bbfe0 --- /dev/null +++ b/conversion/lfm3.py @@ -0,0 +1,629 @@ +from __future__ import annotations + +import json +import math + +from pathlib import Path +from typing import Any, Callable, Iterable, TYPE_CHECKING + +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import MmprojModel, ModelBase, TextModel, gguf, logger +from .lfm2 import D1Model, lfm2_feed_forward_length + + +@ModelBase.register("Lfm3ForCausalLM", "Lfm3VlForConditionalGeneration", "Lfm3OmniForConditionalGeneration") +@ModelBase.example("LiquidAI/LFM3-1.7B", "LiquidAI/LFM3-1.7B-Base") +class LFM3Model(TextModel): + model_arch = gguf.MODEL_ARCH.LFM3 + + # LFM3-Audio/Omni: encoder, projector and audio-output heads live next to the text model + _media_prefixes = ("encoder.", "mlp.", "codebook_embedding.", "depth_embeddings.", "depth_linear.", "depthformer.", + "mask_embedding", "model.codebook_embedding.", "model.depth_decoder.") + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + + if name.startswith(cls._media_prefixes): + return None + + name = name.removeprefix("lfm.") + + return super().filter_tensors((name, gen)) + + # LFM3-Audio live ASR prompt of the model card, the audio follows in the assistant turn + _asr_template = ( + "{{- bos_token -}}" + "{{- '<|im_start|>system\\nPerform live ASR.<|im_end|>\\n' -}}" + "{%- if add_generation_prompt -%}{{- '<|im_start|>assistant\\n' -}}{%- endif -%}" + ) + + # TTS prompt of the model card: a language code is looked up, anything else is taken as the language name + _tts_langs = { + "ar": "Arabic", "da": "Danish", "de": "German", "el": "Greek", "en": "American English", "en-us": "American English", + "en-gb": "British English", "fi": "Finnish", "fr": "French", "he": "Hebrew", "it": "Italian", "ja": "Japanese", + "ko": "Korean", "nl": "Dutch", "pl": "Polish", "pt": "Portuguese", "es": "Spanish", "sv": "Swedish", "tr": "Turkish", + "zh": "Chinese", + } + + # "language" and "voice" are optional, the text to speak is the first message + def _tts_template(self, think: bool) -> str: + return ( + "{%- set names = " + json.dumps(self._tts_langs) + " -%}" + "{%- set code = (language | lower) if language is defined and language else 'en' -%}" + "{%- set lang = names[code] if code in names else language -%}" + "{%- set v = (voice | lower) if voice is defined and voice and (voice | lower) in ['female', 'male'] else 'female' -%}" + "{{- bos_token -}}" + "{{- '<|im_start|>system\\nPerform TTS in ' + lang + ' using a ' + v + ' voice.<|im_end|>\\n' -}}" + "{{- '<|im_start|>user\\n' + messages[0]['content'] + '<|im_end|>\\n' -}}" + "{{- '<|im_start|>assistant\\n" + ("<think></think>" if think else "") + "<|audio_start|>' -}}" + ) + + def set_vocab(self): + super().set_vocab() + # hparams hold the merged text config, the checkpoint's own model_type is in config.json + with open(self.dir_model / "config.json", encoding="utf-8") as f: + model_type = json.load(f).get("model_type") + is_audio = model_type == "lfm3_audio" + is_omni = model_type == "lfm3_omni" + templates = [] + if is_audio: + templates.append({"name": "asr", "template": self._asr_template}) + if is_audio or is_omni: + # LFM3-Omni opens every assistant turn with an empty think block + templates.append({"name": "tts", "template": self._tts_template(think=is_omni)}) + if templates: + self.gguf_writer.add_chat_template(templates) + + def set_gguf_parameters(self): + layer_types = self.hparams["layer_types"] + n_kv_heads = self.hparams["num_key_value_heads"] + + # set num_key_value_heads only for attention layers + self.hparams["num_key_value_heads"] = [ + n_kv_heads if lt != "conv" else 0 + for lt in layer_types + ] + + super().set_gguf_parameters() + + self.gguf_writer.add_rope_dimension_count(self.hparams["head_dim"]) + + self.gguf_writer.add_sliding_window_pattern([lt == "sliding_attention" for lt in layer_types]) + self.gguf_writer.add_sliding_window(self.hparams["sliding_window"]) + + self.gguf_writer.add_shortconv_l_cache(self.hparams["conv_L_cache"]) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + # Partial RoPE is represented by masking trailing frequency pairs. + # rope_parameters is keyed by layer type; only full_attention layers use partial RoPE. + rope_parameters = self.hparams["rope_parameters"]["full_attention"] + partial = rope_parameters.get("partial_rotary_factor", 1.0) + head_dim = self.hparams["head_dim"] + rope_angles = int(partial * head_dim) // 2 + n_pairs = head_dim // 2 + assert 0 < rope_angles <= n_pairs + values = [1.0] * rope_angles + [1e30] * (n_pairs - rope_angles) + rope_freqs = torch.tensor(values, dtype=torch.float32) + yield (self.format_tensor_name(gguf.MODEL_TENSOR.ROPE_FREQS), rope_freqs) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # conv op requires 2d tensor + if "conv.conv" in name: + data_torch = data_torch.squeeze(1) + + yield from super().modify_tensors(data_torch, name, bid) + + +# d1 on LFM3-VL / LFM3-Omni: the stock weights, the d1 prompt read at its last token +_D1_TYPES = {"lfm3_vl": gguf.DecisionType.LFM3_D1, "lfm3_omni": gguf.DecisionType.LFM3_D1_OMNI} + + +def _is_lfm3_d1_checkpoint(dir_model: Path) -> bool: + if not (dir_model / "config.json").is_file(): + return False + with open(dir_model / "config.json", encoding="utf-8") as f: + config = json.load(f) + return config.get("architectures") == ["D1Model"] and config.get("model_type") in _D1_TYPES + + +@ModelBase.register_hparams_loader(_is_lfm3_d1_checkpoint) +def _load_lfm3_d1_hparams(dir_model: Path) -> dict[str, Any]: + logger.info("gguf: detected LFM3 d1 checkpoint") + hparams = ModelBase.load_hparams(dir_model, False, guess=False) + hparams["d1_family"] = hparams["model_type"] + # the mmproj is the base model's, the text model writes the decision + hparams["architectures"] = ["Lfm3VlForConditionalGeneration" if hparams["model_type"] == "lfm3_vl" else "Lfm3OmniForConditionalGeneration"] + hparams["text_config"]["architectures"] = ["Lfm3D1Model"] + return hparams + + +@ModelBase.register("Lfm3D1Model") +@ModelBase.example("LiquidAI/d1-2B", "LiquidAI/d1-omni-2B") +class LFM3D1Model(LFM3Model): + model_arch = gguf.MODEL_ARCH.LFM3 + + # how the checkpoint serves, hard-coded in the server: assert the checkpoint records the same + _served = {"d1_codes": 2, "d1_attention": "set"} + + def set_vocab(self): + # the vocab without the speech task templates of LFM3-Audio/Omni, d1 only decides + TextModel.set_vocab(self) + # the d1 prompt of LFM2, the LFM3 template writes an empty thought before the answer + self.gguf_writer.add_chat_template([{"name": "systemone", "template": D1Model._systemone_template() + "<think></think>"}]) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + + for key, value in self._served.items(): + if self.hparams.get(key) != value: + raise ValueError(f"unsupported d1 checkpoint: {key} = {self.hparams.get(key)!r}, expected {value!r}") + + # a lone question reads the whole prompt both ways on the full attention layers + self.gguf_writer.add_causal_attention(False) + self.gguf_writer.add_decision_type(_D1_TYPES[self.hparams["d1_family"]]) + + # the option answers share one temperature + with open(self.dir_model / "calibration.json", encoding="utf-8") as f: + calibration = json.load(f) + if calibration.get("temperatures"): + raise ValueError("unsupported d1 calibration: per-bucket temperatures") + for name in ("noul", "choice", "score"): + self.gguf_writer.add_decision_temperature(name, calibration["default"]) + + +class LFM3VLVisionMixin(MmprojModel): + """LFM3-VL vision tower and projector, shared with LFM3-Omni.""" + + def _set_lfm3vl_gguf_parameters(self): + assert self.hparams_vision is not None + # clip.cpp hardcodes the GELU projector and its input norm eps + if (self.global_config["projector_hidden_act"] != "gelu" or not self.global_config["projector_bias"] + or self.global_config["projector_layer_norm_eps"] != 1e-6): + raise ValueError("unsupported projector_hidden_act / projector_bias / projector_layer_norm_eps") + # clip.cpp hardcodes the vision rope base, the RGB patchifier and the 3x3 spatial conv + if (self.hparams_vision["rope_parameters"]["rope_theta"] != 1e6 or self.hparams_vision["in_channels"] != 3 + or self.hparams_vision["conv_kernel_size"] != 3): + raise ValueError("unsupported vision rope_theta / in_channels / conv_kernel_size") + self.gguf_writer.add_clip_vision_projector_type(gguf.VisionProjectorType.LFM3VL) + self.gguf_writer.add_vision_head_count_kv(self.hparams_vision["num_key_value_heads"]) + self.gguf_writer.add_vision_spatial_merge_size(self.global_config["downsample_factor"]) + self.gguf_writer.add_vision_attention_layernorm_eps(self.hparams_vision["norm_eps"]) + self.gguf_writer.add_vision_use_silu(True) + size = self.preprocessor_config["size"] + self.gguf_writer.add_vision_min_pixels(size["shortest_edge"]) + self.gguf_writer.add_vision_max_pixels(size["longest_edge"]) + # PIL resample enum, the torchvision backend has no lanczos + resample = self.preprocessor_config["resample"] + resize_algo = {2: "bilinear", 3: "bicubic"}.get(resample) + if resize_algo is None: + raise ValueError(f"unsupported resample: {resample}") + self.gguf_writer.add_vision_image_resize_algo(resize_algo) + self._check_video_config() + + # mtmd_get_video_ts_style and the lfm3vl video frame sizing hardcode these, conversion fails on a mismatch + _video = {"fps": 2.0, "min_frames": 4, "temporal_patch_size": 2, "size": {"shortest_edge": 4096, "longest_edge": 25165824}} + _video_max_frames = 768 + + def _check_video_config(self): + import json + video = self.preprocessor_config.get("video_processor") + path = self.dir_model / "video_preprocessor_config.json" + if video is None and path.is_file(): + with open(path, encoding="utf-8") as f: + video = json.load(f) + if video is None: + return + for k, v in {**self._video, "max_frames": self._video_max_frames}.items(): + if video.get(k) != v: + raise ValueError(f"unsupported video {k}={video.get(k)!r}, expected {v!r}") + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if "patch_embd" in new_name: + return gguf.GGMLQuantizationType.F16 + if "conv2d_spatial" in new_name: + # CUDA CONV_2D_DW requires an f32 kernel; the tensor is tiny + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def _lfm3vl_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name == "model.vision_tower.patchifier.weight": + # qwen2vl-style layout [channel, temporal, ph, pw], one conv kernel per temporal slice + assert self.hparams_vision is not None + t = self.hparams_vision["temporal_patch_size"] + p = self.hparams_vision["patch_size"] + n_embd = data_torch.shape[0] + w = data_torch.view(n_embd, 3, t, p, p) + yield ("v.patch_embd.weight", w[:, :, 0].contiguous()) + if t == 2: + yield ("v.patch_embd.weight.1", w[:, :, 1].contiguous()) + else: + assert t == 1, f"unsupported vision_temporal_patch_size {t}" + return + if name == "model.vision_tower.embedding_norm.weight": + yield ("v.embedding_norm.weight", data_torch) + return + if "conv.in_proj.weight" in name: + yield (f"v.blk.{bid}.conv2d_in_proj.weight", data_torch) + return + if "conv.spatial_conv.weight" in name: + yield (f"v.blk.{bid}.conv2d_spatial.weight", data_torch) + return + if "conv.out_proj.weight" in name: + yield (f"v.blk.{bid}.conv2d_out_proj.weight", data_torch) + return + + # projector: input LayerNorm -> linear_1 -> GELU -> linear_2 + if name.startswith("model.multi_modal_projector."): + layer, suffix = name.removeprefix("model.multi_modal_projector.").split(".") + yield ({"layer_norm": "mm.input_norm", "linear_1": "mm.0", "linear_2": "mm.2"}[layer] + "." + suffix, data_torch) + return + + yield (self.map_tensor_name(name), data_torch) + + +@ModelBase.register("Lfm3VlForConditionalGeneration") +@ModelBase.example("LiquidAI/LFM3-VL-2B") +class LFM3VLMmprojModel(LFM3VLVisionMixin): + has_vision_encoder = True + has_audio_encoder = False + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + assert self.hparams_vision is not None + # dynamic resolution, image_size is only set for MmprojModel compatibility + self.hparams_vision["image_size"] = 512 + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._set_lfm3vl_gguf_parameters() + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith(("model.vision_tower.", "model.multi_modal_projector.")): + yield from self._lfm3vl_tensors(data_torch, name, bid) + + +def _is_lfm3_audio_checkpoint(dir_model: Path) -> bool: + if not (dir_model / "config.json").is_file(): + return False + with open(dir_model / "config.json", encoding="utf-8") as f: + config = json.load(f) + return config.get("model_type") == "lfm3_audio" and "lfm" in config + + +# read the release config.json as is: a transformers that knows lfm3_audio rewrites it into another layout +@ModelBase.register_hparams_loader(_is_lfm3_audio_checkpoint) +def _load_lfm3_audio_hparams(dir_model: Path) -> dict[str, Any]: + with open(dir_model / "config.json", encoding="utf-8") as f: + config = json.load(f) + config["text_config"] = config["lfm"] + return config + + +@ModelBase.register("Lfm3AudioForConditionalGeneration") +@ModelBase.example("LiquidAI/LFM3-Audio-2B") +class LFM3AudioMmprojModel(MmprojModel): + has_vision_encoder = False + has_audio_encoder = True + + # the downsampler has the LFM2-Audio pre-encoder layout: conv, dw conv, pw conv, dw conv, pw conv + _downsample_idx = {"conv_in": 0, "conv_mid": 2, "lin_mid": 3, "conv_end": 5, "lin_end": 6} + + # audio output: MaskGIT depthformer (a.gen.code.*) and the codec decoder (a.gen.wav.*) + _depth_layer_map = { + "operator_norm": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_NORM, + "self_attn.q_proj": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_Q, + "self_attn.q_norm": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_Q_NORM, + "self_attn.k_proj": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_K, + "self_attn.k_norm": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_K_NORM, + "self_attn.v_proj": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_V, + "self_attn.o_proj": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_OUT, + "self_attn.gate_proj": gguf.MODEL_TENSOR.A_GEN_CODE_ATTN_GATE, + "ffn_norm": gguf.MODEL_TENSOR.A_GEN_CODE_FFN_NORM, + "feed_forward.w1": gguf.MODEL_TENSOR.A_GEN_CODE_FFN_GATE, + "feed_forward.w3": gguf.MODEL_TENSOR.A_GEN_CODE_FFN_UP, + "feed_forward.w2": gguf.MODEL_TENSOR.A_GEN_CODE_FFN_DOWN, + } + _codec_layer_map = { + "operator_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_NORM, + "post_operator_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_POST_NORM, + "self_attn.q_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_Q, + "self_attn.q_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_Q_NORM, + "self_attn.k_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_K, + "self_attn.k_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_K_NORM, + "self_attn.v_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_V, + "self_attn.o_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_OUT, + "self_attn.gate_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_GATE, + "conv.in_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_CONV_PW1, + "conv.conv": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_CONV_DW, + "conv.out_proj": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_CONV_PW2, + "ffn_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_FFN_NORM, + "post_ffn_norm": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_FFN_POST_NORM, + "feed_forward.w1": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_FFN_GATE, + "feed_forward.w3": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_FFN_UP, + "feed_forward.w2": gguf.MODEL_TENSOR.A_GEN_WAV_TFM_FFN_DOWN, + } + # the codec graph in clip.cpp hardcodes the liquid-codec FSQ front end and decoder shape, conversion fails on a mismatch + _codec = { + "model_type": "liquid_codec", "fsq_levels": [8, 7, 6, 6], "n_q": 12, "quantizer_dim": 256, + "encoder_dim": 512, "stft_n_fft": 1280, "stft_hop_length": 320, "stft_win_length": 1280, "stft_frame_stack": 6, + "decoder_window": 30, "sampling_rate": 24000, + } + # the lfm3a pipeline in mtmd-helper-gen.cpp hardcodes these + _generation = {"codebooks": 12, "maskgit_schedule": [4, 4, 4], "interleaved_n_text": 6, "interleaved_n_audio": 12} + + # speech-code sampling of the model card, generation_config.json overrides it + _audio_sampling = { + "audio_temperature": 1.0, "audio_top_k": 128, "audio_repetition_penalty": 1.1, "audio_repetition_window": 4096, + } + + # mtmd_audio_preprocessor_lfm3a hardcodes this front end, conversion fails on a mismatch + _feature_extractor = { + "sampling_rate": 16000, "feature_size": 128, "n_fft": 400, "win_length": 400, "hop_length": 160, + "log_floor": -12.0, "normalization_offset": 4.0, "normalization_divisor": 4.0, "encoder_stride": 8, + } + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + # audio output is exported when the checkpoint ships the codec + self._audio_output = (self.dir_model / "audio_tokenizer").is_dir() + gen = self.get_generation_config() + self._n_codebooks: int = gen["codebooks"] + self._audio_vocab: int = gen["audio_vocab_size"] + self._depth_embd: dict[int, Tensor] = {} + self._depth_norm: dict[int, Tensor] = {} + + def get_audio_config(self) -> dict[str, Any] | None: + enc = self.global_config["encoder"] + cfg = dict(enc["lfm"]) + cfg["num_mel_bins"] = enc["dim_in"] + cfg["sliding_window"] = enc["sliding_window"] + return cfg + + def get_generation_config(self) -> dict[str, Any]: + c = self.global_config + steps = c["maskgit_steps"] + return { + "codebooks": c["codebooks"], "audio_vocab_size": c["audio_vocab_size"], + "maskgit_schedule": [c["codebooks"] // steps] * steps, + "interleaved_n_text": c["interleaved_n_text"], "interleaved_n_audio": c["interleaved_n_audio"], + } + + def get_depth_config(self) -> dict[str, Any]: + return self.global_config["depthformer"] + + def set_gguf_parameters(self): + assert self.hparams_audio is not None + fe = self.preprocessor_config["feature_extractor"] + if fe["feature_extractor_type"] not in ("Lfm3AudioFeatureExtractor", "Lfm3OmniFeatureExtractor"): + raise ValueError(f"unsupported feature_extractor_type {fe['feature_extractor_type']!r}") + for k, v in self._feature_extractor.items(): + if fe[k] != v: + raise ValueError(f"unsupported feature_extractor.{k}={fe[k]!r}, expected {v!r}") + + # clip.cpp hardcodes the encoder rope base + if self.hparams_audio["rope_parameters"]["rope_theta"] != 1e6: + raise ValueError("unsupported audio encoder rope_theta") + + self.hparams_audio["intermediate_size"] = lfm2_feed_forward_length(self.hparams_audio) + super().set_gguf_parameters() + self.gguf_writer.add_clip_audio_projector_type(gguf.VisionProjectorType.LFM3A) + self.gguf_writer.add_audio_head_count_kv(self.hparams_audio["num_key_value_heads"]) + self.gguf_writer.add_audio_attention_layernorm_eps(self.hparams_audio["norm_eps"]) + self.gguf_writer.add_audio_num_mel_bins(self.hparams_audio["num_mel_bins"]) + self.gguf_writer.add_audio_window_size(self.hparams_audio["sliding_window"]) + + if not self._audio_output: + return + + # audio generation: depthformer hparams, the codec ones are constant and live in clip.cpp + gen = self.get_generation_config() + for k, v in self._generation.items(): + if gen[k] != v: + raise ValueError(f"unsupported {k}={gen[k]!r}, expected {v!r}") + depth = self.get_depth_config() + if depth.get("is_causal", False) or depth["use_sandwich_norm"] or set(depth["layer_types"]) != {"full_attention"}: + raise ValueError("unsupported depthformer, expected a bidirectional all-attention stack") + if depth["rope_parameters"]["full_attention"]["rope_theta"] != 1e6: + raise ValueError("unsupported depthformer rope_theta") + self.gguf_writer.add_clip_has_gen_audio_encoder(True) + self.gguf_writer.add_clip_gen_audio_projector_type(gguf.VisionProjectorType.LFM3A_GEN) + self.gguf_writer.add_gen_audio_projection_dim(self.n_embd_text) + self.gguf_writer.add_gen_audio_embedding_length(depth["hidden_size"]) + self.gguf_writer.add_gen_audio_feed_forward_length(depth["intermediate_size"]) + self.gguf_writer.add_gen_audio_block_count(depth["num_hidden_layers"]) + self.gguf_writer.add_gen_audio_head_count(depth["num_attention_heads"]) + self.gguf_writer.add_gen_audio_head_count_kv(depth["num_key_value_heads"]) + self.gguf_writer.add_gen_audio_attention_layernorm_eps(depth["norm_eps"]) + + # sampling defaults of the speech codes, next to the text ones that become general.sampling.* + gen = gguf.Metadata.load_generation_config(self.dir_model) + for key, add in (("audio_temperature", self.gguf_writer.add_gen_audio_sampling_temp), + ("audio_top_k", self.gguf_writer.add_gen_audio_sampling_top_k), + ("audio_repetition_penalty", self.gguf_writer.add_gen_audio_sampling_penalty_repeat), + ("audio_repetition_window", self.gguf_writer.add_gen_audio_sampling_penalty_last_n)): + value = gen.get(key, self._audio_sampling.get(key)) + if value is not None: + add(value) + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if new_name.startswith("a.conv1d.") or "conv_dw" in new_name or new_name.startswith("a.gen.wav.quant."): + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + if self._audio_output: + yield from self._codec_tensors() + + def _codec_tensors(self) -> Iterable[tuple[str, Tensor]]: + import json + from safetensors.torch import load_file + + T = gguf.MODEL_TENSOR + codec_dir = self.dir_model / "audio_tokenizer" + with open(codec_dir / "config.json", encoding="utf-8") as f: + cfg = json.load(f) + for k, v in self._codec.items(): + if cfg.get(k) != v: + raise ValueError(f"unsupported audio_tokenizer {k}={cfg.get(k)!r}, expected {v!r}") + if math.prod(cfg["fsq_levels"]) != self._audio_vocab - 1: + raise ValueError(f"audio_vocab_size {self._audio_vocab} does not match the codec, expected codebook size + 1") + + state_dict = load_file(codec_dir / "model.safetensors") + + # FSQ code table: index -> the len(levels) quantized values, see FiniteScalarQuantization._indices_to_codes + levels = torch.tensor(cfg["fsq_levels"], dtype=torch.int64) + basis = torch.cumprod(torch.cat([torch.ones(1, dtype=torch.int64), levels[:-1]]), dim=0) + half = levels // 2 + idx = torch.arange(int(levels.prod()), dtype=torch.int64)[:, None] + codes = ((idx // basis) % levels - half) / half + yield (self.format_tensor_name(T.A_GEN_WAV_QUANT_FIRST_CB), codes.to(torch.float32)) + + # one projection over the concatenated code vectors of all codebooks, under quantizer.fsq. in newer exports + quantizer = "quantizer.fsq." if "quantizer.fsq.project_out.weight" in state_dict else "quantizer." + for suffix in ("weight", "bias"): + yield (self.format_tensor_name(T.A_GEN_WAV_QUANT_FIRST_OUT, suffix=f".{suffix}"), state_dict[f"{quantizer}project_out.{suffix}"]) + yield (self.format_tensor_name(T.A_GEN_WAV_TFM_IN_PROJ, suffix=f".{suffix}"), state_dict[f"from_quantizer.{suffix}"]) + yield (self.format_tensor_name(T.A_GEN_WAV_TFM_OUT_PROJ, suffix=f".{suffix}"), state_dict[f"decoder.lin.{suffix}"]) + yield (self.format_tensor_name(T.A_GEN_WAV_TFM_OUTPUT_NORM), state_dict["decoder.lfm.embedding_norm.weight"]) + + for name, data_torch in state_dict.items(): + if not name.startswith("decoder.lfm.layers."): + continue + bid_str, key = name.removeprefix("decoder.lfm.layers.").rsplit(".weight", 1)[0].split(".", 1) + if key == "conv.conv": + data_torch = data_torch.squeeze(1) + yield (self.format_tensor_name(self._codec_layer_map[key], int(bid_str)), data_torch) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith("a.gen.wav."): + yield (name, data_torch) + return + + if name.startswith(("depthformer.", "depth_", "codebook_embedding.", "mask_embedding")): + if self._audio_output: + yield from self._depthformer_tensor(data_torch, name, bid) + return + + if not name.startswith(("encoder.", "mlp.")): + return + + if name.startswith("encoder.downsample."): + layer, suffix = name.removeprefix("encoder.downsample.").split(".") + if layer == "lin_out": + if suffix == "weight": + data_torch = data_torch.squeeze(-1) + yield (self.format_tensor_name(gguf.MODEL_TENSOR.A_ENC_OUT, suffix=f".{suffix}"), data_torch) + return + if suffix == "bias": + data_torch = data_torch[:, None, None] + yield (self.format_tensor_name(gguf.MODEL_TENSOR.A_ENC_CONV1D, self._downsample_idx[layer], f".{suffix}"), data_torch) + return + + # conv op requires 2d tensor + if name.endswith("conv.conv.weight"): + data_torch = data_torch.squeeze(1) + + yield (self.map_tensor_name(name), data_torch) + + def _depthformer_tensor(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + T = gguf.MODEL_TENSOR + + if name.startswith("depthformer.model.layers."): + key = name.removeprefix("depthformer.model.layers.").split(".", 1)[1].rsplit(".weight", 1)[0] + yield (self.format_tensor_name(self._depth_layer_map[key], bid), data_torch) + return + if name == "depthformer.model.embedding_norm.weight": + yield (self.format_tensor_name(T.A_GEN_CODE_OUTPUT_NORM), data_torch) + return + if name.startswith("depth_linear."): + yield (self.format_tensor_name(T.A_GEN_CODE_PROJ_IN, suffix="." + name.rsplit(".", 1)[1]), data_torch) + return + if name == "mask_embedding": + yield (self.format_tensor_name(T.A_GEN_CODE_MASK_EMBD, suffix=""), data_torch) + return + if name == "codebook_embedding.weight": + assert data_torch.shape[0] == self._n_codebooks * self._audio_vocab + yield (self.format_tensor_name(T.A_GEN_CODE_OUT_EMBD), data_torch) + return + + # per-codebook heads: the embedding table is tied to to_logits, merge the 12 tables into one tensor + assert name.startswith("depth_embeddings.") + idx = int(name.split(".")[1]) + key = name.split(".", 2)[2] + if key == "embedding.weight": + self._depth_embd[idx] = data_torch + if len(self._depth_embd) == self._n_codebooks: + yield (self.format_tensor_name(T.A_GEN_CODE_EMBD), torch.stack([self._depth_embd[i] for i in range(self._n_codebooks)], dim=0)) + elif key == "embedding_norm.weight": + self._depth_norm[idx] = data_torch + if len(self._depth_norm) == self._n_codebooks: + yield (self.format_tensor_name(T.A_GEN_CODE_HEAD_NORM), torch.stack([self._depth_norm[i] for i in range(self._n_codebooks)], dim=0)) + elif key == "to_logits.weight": + if not torch.equal(data_torch, self._depth_embd[idx]): + raise ValueError(f"depth_embeddings.{idx} is not tied") + else: + raise ValueError(f"unexpected tensor {name}") + + +@ModelBase.register("Lfm3OmniForConditionalGeneration") +@ModelBase.example("LiquidAI/LFM3-Omni-2B") +class LFM3OmniMmprojModel(LFM3VLVisionMixin, LFM3AudioMmprojModel): + has_vision_encoder = True + has_audio_encoder = True + + _audio_sampling = {"audio_temperature": 0.4, "audio_repetition_penalty": 1.2, "audio_repetition_window": 64} + _video_max_frames = 384 + + # the audio side is the LFM3-Audio model under the HF-native names + _audio_renames = ( + ("model.audio_encoder.lfm.", "encoder.lfm.lfm."), + ("model.audio_encoder.", "encoder."), + ("model.audio_projector.layer_norm.", "mlp.model.0."), + ("model.audio_projector.linear_1.", "mlp.model.1."), + ("model.audio_projector.linear_2.", "mlp.model.3."), + ("model.depth_decoder.model.", "depthformer.model."), + ("model.depth_decoder.", ""), + ("model.codebook_embedding.", "codebook_embedding."), + ) + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + assert self.hparams_vision is not None + # dynamic resolution, image_size is only set for MmprojModel compatibility + self.hparams_vision["image_size"] = 512 + + def get_audio_config(self) -> dict[str, Any] | None: + enc = self.global_config["audio_encoder_config"] + cfg = dict(enc["text_config"]) + cfg["num_mel_bins"] = enc["num_mel_bins"] + cfg["sliding_window"] = enc["sliding_window"] + return cfg + + def get_generation_config(self) -> dict[str, Any]: + c = self.global_config + return { + "codebooks": c["num_codebooks"], "audio_vocab_size": c["codebook_size"], "maskgit_schedule": c["maskgit_schedule"], + "interleaved_n_text": c["interleaved_n_text"], "interleaved_n_audio": c["interleaved_n_audio"], + } + + def get_depth_config(self) -> dict[str, Any]: + return self.global_config["depth_config"] + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._set_lfm3vl_gguf_parameters() + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith(("model.vision_tower.", "model.multi_modal_projector.")): + yield from self._lfm3vl_tensors(data_torch, name, bid) + return + for old, new in self._audio_renames: + if name.startswith(old): + yield from super().modify_tensors(data_torch, new + name.removeprefix(old), bid) + return + yield from super().modify_tensors(data_torch, name, bid) diff --git a/conversion/limite.py b/conversion/limite.py new file mode 100644 index 000000000000..7d413302b8c4 --- /dev/null +++ b/conversion/limite.py @@ -0,0 +1,184 @@ +from __future__ import annotations + +from typing import Iterable, TYPE_CHECKING + +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import ModelBase, TextModel, gguf + + +@ModelBase.register("LimiteForCausalLM") +@ModelBase.example("paradigma-inc/limite-1b-violetto") +class LimiteModel(TextModel): + model_arch = gguf.MODEL_ARCH.LIMITE + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + hp = self.hparams + + expected = { + "pos_mode": "rope", + "qk_norm": "rms_pre_rope", + "rope_style": "interleaved_pairs_odd_lane_sign_flip", + "rope_per_layer": False, + "rms_norm_has_weight": False, + "rms_norm_eps_mode": "torch_finfo_default", + "mlp_type": "swiglu", + "attn_gate_applied": "per_head_before_o_proj", + "ve_head_slice": "first_num_key_value_heads", + "ve_applied_before_qk_norm": True, + "global_nope": True, + "global_window": -1, + "mudd_r_site": "resid", + "tie_word_embeddings": True, + "final_softcap": 0.0, + } + for key, value in expected.items(): + if hp.get(key) != value: + raise NotImplementedError(f"Limite: unsupported {key}={hp.get(key)!r}, expected {value!r}") + if hp["softcap_logits"]["kind"] != "sigmoid": + raise NotImplementedError(f"Limite: unsupported softcap_logits kind {hp['softcap_logits']['kind']!r}") + + self.n_head = hp["num_attention_heads"] + self.n_head_kv = hp["num_key_value_heads"] + self.head_dim = hp["head_dim"] + self.n_pairs = hp["rope_n_pairs"] + + self.mudd_taps: dict[int, list[int]] = {} + if hp.get("mudd"): + if not hp.get("mudd_mlp"): + raise NotImplementedError("Limite: mudd without mudd_mlp is not supported") + self.mudd_taps = {int(il): [int(t) for t in taps] for il, taps in hp["mudd_tap_idx"].items()} + assert all(len(taps) == hp["mudd_taps"] for taps in self.mudd_taps.values()) + + def set_vocab(self): + self._set_vocab_gpt2() + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hp = self.hparams + + self.gguf_writer.add_key_length(self.head_dim) + self.gguf_writer.add_value_length(self.head_dim) + + # torch rms_norm with eps=None uses the fp32 epsilon, even for bf16 inputs + self.gguf_writer.add_layer_norm_rms_eps(torch.finfo(torch.float32).eps) + self.gguf_writer.add_attention_scale(hp["attention_softmax_scale"]) + self.gguf_writer.add_xsa_eps(hp["xsa_normalize_eps"] if hp.get("xsa") else 0.0) + + # HF freq_i = base^(-i/(n_pairs-1)), ggml uses freq_base^(-i/n_pairs) + self.gguf_writer.add_rope_dimension_count(2 * self.n_pairs) + self.gguf_writer.add_rope_freq_base(hp["rope_base_local"] ** (self.n_pairs / (self.n_pairs - 1))) + + # HF keeps keys k >= q - window, so a window of W spans W + 1 tokens + global_layers = set(hp["global_layers"]) + self.gguf_writer.add_sliding_window(hp["sliding_window"] + 1) + self.gguf_writer.add_sliding_window_pattern([il not in global_layers for il in range(self.block_count)]) + + cap = hp["softcap_logits"] + self.gguf_writer.add_final_logit_sigmoid_capping(cap["a"], cap["b"], cap["c"]) + + if self.mudd_taps: + n_taps = hp["mudd_taps"] + tap_indices = [-1] * (self.block_count * n_taps) + for il, taps in self.mudd_taps.items(): + tap_indices[il * n_taps:(il + 1) * n_taps] = taps + self.gguf_writer.add_mudd_feed_forward_length(hp["mudd_inter"]) + self.gguf_writer.add_mudd_tap_count(n_taps) + self.gguf_writer.add_mudd_tap_indices(tap_indices) + + def tensor_force_quant(self, name, new_name, bid, n_dims): + # tiny mixing weights, kept at full precision as in the reference + # the mudd tensors come from a global source tensor, so take the block id from the new name + if new_name.startswith("blk."): + bid = int(new_name.split(".")[1]) + for key in (gguf.MODEL_TENSOR.ATTN_GATE, gguf.MODEL_TENSOR.ATTN_VE_GATE, gguf.MODEL_TENSOR.MUDD_DOWN, gguf.MODEL_TENSOR.MUDD_UP): + if self.match_model_tensor_name(new_name, key, bid): + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def _swap_rope_pairs(self, w: Tensor, n_head: int) -> Tensor: + # HF rotates each pair by -theta; swapping the pair lanes gives the ggml +theta rotation. + # q and k are both swapped, so the attention scores do not change. + idx = torch.arange(self.head_dim) + idx[:2 * self.n_pairs] = idx[:2 * self.n_pairs].view(-1, 2).flip(-1).reshape(-1) + w = w.reshape(n_head, self.head_dim, -1) + return w[:, idx, :].reshape(n_head * self.head_dim, -1) + + def _pad_cols(self, w: Tensor) -> Tensor: + # gates read only the first channels of the input, pad them to n_embd + return torch.nn.functional.pad(w, (0, self.hparams["hidden_size"] - w.shape[-1])) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + hp = self.hparams + T = gguf.MODEL_TENSOR + + def load(n: str) -> Tensor: + return self.model_tensors[n]().float() + + if name == "model.value_embeds.weight": + ve = data_torch.reshape(data_torch.shape[0], -1, hp["ve_dim"])[:, :self.n_head_kv] + ve = torch.nn.functional.pad(ve, (0, self.head_dim - hp["ve_dim"])) + yield self.format_tensor_name(T.VALUE_EMBD), ve.reshape(ve.shape[0], -1) * hp["ve_gate_scale"] + return + + if name == "model.mudd.dense1": + for il in self.mudd_taps: + yield self.format_tensor_name(T.MUDD_DOWN, il), data_torch + return + if name == "model.mudd.dense2": + # rows [0, n) mix the attention input, rows [n, 2n) mix the residual + dense2_mlp = load("model.mudd.dense2_mlp") + bias = load("model.mudd.bias") + bias_mlp = load("model.mudd.bias_mlp") + for il, taps in self.mudd_taps.items(): + n = len(taps) + w = torch.cat([data_torch[il, :n], dense2_mlp[il, :n]], 0) + b = torch.cat([bias[il, :n], bias_mlp[il, :n]], 0) + yield self.format_tensor_name(T.MUDD_UP, il), w + yield self.format_tensor_name(T.MUDD_UP, il, ".bias"), b + return + if name.startswith("model.mudd."): + return + + if bid is None: + yield from super().modify_tensors(data_torch, name, bid) + return + + prefix = f"model.layers.{bid}." + name = name.removeprefix(prefix) + + if name in ("self_attn.q_proj.weight", "self_attn.k_proj.weight", "self_attn.v_proj.weight"): + data_torch = data_torch * load(prefix + "self_attn.qkv_scale") + if name == "self_attn.q_proj.weight": + data_torch = self._swap_rope_pairs(data_torch, self.n_head) + elif name == "self_attn.k_proj.weight": + data_torch = self._swap_rope_pairs(data_torch, self.n_head_kv) + elif name == "self_attn.o_proj.weight": + data_torch = data_torch * load(prefix + "self_attn.o_scale") * load(prefix + "post_lambda_attn") * hp["attn_gate_scale"] + elif name == "mlp.down_proj.weight": + data_torch = data_torch * load(prefix + "post_lambda_mlp") + elif name == "self_attn.attn_gate": + yield self.format_tensor_name(T.ATTN_GATE, bid), self._pad_cols(data_torch) + return + elif name == "self_attn.ve_gate": + yield self.format_tensor_name(T.ATTN_VE_GATE, bid), self._pad_cols(data_torch[:self.n_head_kv]) + return + elif name == "self_attn.xsa_alpha": + if hp.get("xsa") and bid in hp["xsa_layers"]: + yield self.format_tensor_name(T.ATTN_XSA_ALPHA, bid), torch.tanh(data_torch) + return + elif name == "resid_lambda_attn": + yield self.format_tensor_name(T.ATTN_RESID_SCALE, bid), data_torch.reshape(1) + return + elif name == "resid_lambda_mlp": + yield self.format_tensor_name(T.FFN_RESID_SCALE, bid), data_torch.reshape(1) + return + elif name in ("self_attn.qkv_scale", "self_attn.o_scale", "post_lambda_attn", "post_lambda_mlp"): + # folded into the projections above + return + + yield from super().modify_tensors(data_torch, prefix + name, bid) diff --git a/conversion/llama.py b/conversion/llama.py index 41d8c2309281..b04f54d41912 100644 --- a/conversion/llama.py +++ b/conversion/llama.py @@ -129,8 +129,9 @@ def set_vocab(self): tokenizer_config_json = json.load(f) if (add_prefix_space := tokenizer_config_json.get("add_prefix_space")) is not None: self.gguf_writer.add_add_space_prefix(add_prefix_space) - if tokenizer_config_json.get("tokenizer_class") == "HybridDNATokenizer": - return self._set_vocab_hybriddna() + + if self._is_hybriddna(): + return self._set_vocab_hybriddna() try: self._set_vocab_sentencepiece() diff --git a/conversion/llava.py b/conversion/llava.py index 98a004f98693..e193f0b95da4 100644 --- a/conversion/llava.py +++ b/conversion/llava.py @@ -2,7 +2,7 @@ import json -from typing import Iterable, TYPE_CHECKING +from typing import Callable, Iterable, TYPE_CHECKING if TYPE_CHECKING: from torch import Tensor @@ -128,3 +128,24 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter yield from super().modify_tensors(img_break_embd, name, bid) return # skip other tensors + + +@ModelBase.register("Mistral3Model") +@ModelBase.example("nvidia/Nemotron-3.5-Embed-1B-BF16") +class Mistral3EmbeddingVisionModel(LlavaVisionModel): + def __init__(self, dir_model, *args, **kwargs): + hparams = ModelBase.load_hparams(dir_model, is_mistral_format=False) + text_config = hparams.get("text_config", hparams) + if text_config.get("is_causal") is not False: + raise NotImplementedError("Expected a Nemotron Embed model for Mistral3Model, but is_causal is not False") + super().__init__(dir_model, *args, **kwargs) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + if item[0].endswith("embed_tokens.weight"): + return ModelBase.filter_tensors(item) + return super().filter_tensors(item) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_vision_preproc_image_size(self.preprocessor_config["size"]["longest_edge"]) diff --git a/conversion/mellum.py b/conversion/mellum.py index 1e50f92aeafd..9dc2192f3778 100644 --- a/conversion/mellum.py +++ b/conversion/mellum.py @@ -1,6 +1,6 @@ from __future__ import annotations -from typing import Iterable, TYPE_CHECKING +from typing import Callable, Iterable, TYPE_CHECKING import torch @@ -14,6 +14,54 @@ @ModelBase.example("JetBrains/Mellum2-12B-A2.5B-Base") class MellumModel(TextModel): model_arch = gguf.MODEL_ARCH.MELLUM + supports_mtp_export = True + + _n_main_layers: int | None = None + + _experts: list[dict[str, Tensor]] | None = None + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + # number of exported MTP blocks, appended after the trunk layers + self.n_nextn = 0 if self.no_mtp else (self.find_hparam(["num_nextn_predict_layers", "num_mtp_layers"], optional=True) or 0) + if self.mtp_only and self.n_nextn == 0: + raise ValueError("--mtp requested, but the checkpoint has no MTP layers (num_nextn_predict_layers is 0)") + if self.n_nextn > 0: + if any(t != "sparse" for t in self.hparams.get("mtp_mlp_layer_types") or []): + raise ValueError("Mellum MTP layers with dense MLP are not supported") + self.block_count += self.n_nextn + self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self.block_count) + + def index_tensors(self, remote_hf_model_id: str | None = None): + type(self)._n_main_layers = self.hparams["num_hidden_layers"] + return super().index_tensors(remote_hf_model_id=remote_hf_model_id) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + if (titem := super().filter_tensors(item)) is None: + return None + name, gen = titem + + if name.startswith("mtp."): + if cls.no_mtp: + return None + assert cls._n_main_layers is not None + # mtp.layers.{i}.* -> model.layers.{n_main + i}.*, mtp.{fc,norm,...} -> nextn names of the first MTP block + remapper = { + "fc": "eh_proj", + "pre_fc_norm_embedding": "enorm", + "pre_fc_norm_hidden": "hnorm", + "norm": "shared_head.norm", + } + parts = name.split(".", 3) + if len(parts) == 4 and parts[1] == "layers" and parts[2].isdecimal(): + name = f"model.layers.{cls._n_main_layers + int(parts[2])}.{parts[3]}" + elif len(parts) == 3 and parts[1] in remapper: + name = f"model.layers.{cls._n_main_layers}.{remapper[parts[1]]}.{parts[2]}" + elif cls.mtp_only and name not in ("model.embed_tokens.weight", "model.norm.weight", "lm_head.weight"): + return None + + return name, gen def set_gguf_parameters(self): super().set_gguf_parameters() @@ -26,10 +74,31 @@ def set_gguf_parameters(self): if (use_sliding_window is True or use_sliding_window is None) and sliding_window is not None: self.gguf_writer.add_sliding_window(sliding_window) logger.info(f"gguf: sliding window = {sliding_window}") - self.gguf_writer.add_sliding_window_pattern([t == "sliding_attention" for t in self.hparams["layer_types"]]) - logger.info(f"gguf: sliding window pattern length = {len(self.hparams['layer_types'])}") - - _experts: list[dict[str, Tensor]] | None = None + layer_types = list(self.hparams["layer_types"]) + # MTP blocks default to sliding window attention, as in transformers + if self.n_nextn > 0: + layer_types += self.hparams.get("mtp_layer_types") or ["sliding_attention"] * self.n_nextn + self.gguf_writer.add_sliding_window_pattern([t == "sliding_attention" for t in layer_types]) + logger.info(f"gguf: sliding window pattern length = {len(layer_types)}") + + if (norm_topk_prob := self.hparams.get("norm_topk_prob")) is not None: + self.gguf_writer.add_expert_weights_norm(norm_topk_prob) + + if self.n_nextn > 0: + self.gguf_writer.add_nextn_predict_layers(self.n_nextn) + + def prepare_metadata(self, vocab_only: bool): + from_dir = self.fname_out.is_dir() + super().prepare_metadata(vocab_only=vocab_only) + + if not self.mtp_only or not from_dir: + return + + output_type: str = self.ftype.name.partition("_")[2] + fname_default: str = gguf.naming_convention( + self.metadata.name, self.metadata.basename, self.metadata.finetune, + self.metadata.version, size_label=None, output_type=output_type, model_type=None) + self.fname_out = self.fname_out.parent / f"mtp-{fname_default}.gguf" def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: if name.find("experts") != -1: diff --git a/conversion/minicpm.py b/conversion/minicpm.py index 937ac033a914..d8fceb0c08e0 100644 --- a/conversion/minicpm.py +++ b/conversion/minicpm.py @@ -272,3 +272,18 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter yield self.format_tensor_name(gguf.MODEL_TENSOR.V_TOK_EMBD_SEP, suffix=""), data_torch[ids] return yield from super().modify_tensors(data_torch, name, bid) + + +# MiniCPM-OCR 1.0: the 4.6 stack with model_type minicpm_ocr. + +@ModelBase.register("MiniCPMOcrForConditionalGeneration") +@ModelBase.example("openbmb/MiniCPM-OCR-1.0") +class MiniCPMOCR1_0TextModel(MiniCPMV4_6TextModel): + model_arch = gguf.MODEL_ARCH.QWEN35 + no_mtp = True + + +@ModelBase.register("MiniCPMOcrForConditionalGeneration") +@ModelBase.example("openbmb/MiniCPM-OCR-1.0") +class MiniCPMOCR1_0VisionModel(MiniCPMV4_6VisionModel): + projector_type = gguf.VisionProjectorType.MINICPM_OCR_1_0 diff --git a/conversion/mistral3.py b/conversion/mistral3.py index fee039b353c4..6c771b26f3ba 100644 --- a/conversion/mistral3.py +++ b/conversion/mistral3.py @@ -5,7 +5,7 @@ if TYPE_CHECKING: from torch import Tensor -from .base import ModelBase, TextModel, gguf +from .base import ModelBase, TextModel, get_model_architecture, gguf from .deepseek import DeepseekV2Model from .llama import LlamaModel @@ -13,9 +13,11 @@ @ModelBase.register( "Mistral3ForConditionalGeneration", + "Mistral3Model", "Ministral3ForCausalLM", + "Ministral3Model", ) -@ModelBase.example("mistralai/Mistral-Small-3.1-24B-Instruct-2503", "hf-tiny-v2/tiny-random-Ministral3ForCausalLM") +@ModelBase.example("mistralai/Mistral-Small-3.1-24B-Instruct-2503", "hf-tiny-v2/tiny-random-Ministral3ForCausalLM", "nvidia/Nemotron-3-Embed-1B-BF16", "nvidia/Nemotron-3.5-Embed-1B-BF16") class Mistral3Model(TextModel): class Ministral3Model(LlamaModel): model_arch = gguf.MODEL_ARCH.MISTRAL3 @@ -29,6 +31,23 @@ def set_gguf_parameters(self): self.gguf_writer.add_rope_scaling_yarn_log_mul(rope_params["mscale_all_dim"]) self.gguf_writer.add_attn_temperature_scale(rope_params["llama_4_scaling_beta"]) + class Mistral3EmbedNemotronModel(Ministral3Model): + model_arch = gguf.MODEL_ARCH.MISTRAL3 + + def set_vocab(self): + super().set_vocab() + self.gguf_writer.add_add_bos_token(False) + self.gguf_writer.add_add_eos_token(False) + + def get_vocab_base_pre(self, tokenizer) -> str: + if self.origin_hf_arch == "Mistral3Model": + return "nemotron-3.5-embed" + return super().get_vocab_base_pre(tokenizer) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._try_set_pooling_type() + class Mistral4Model(DeepseekV2Model): model_arch = gguf.MODEL_ARCH.MISTRAL4 skip_mtp = False # model contains no MTP layers, so no need to skip @@ -42,12 +61,20 @@ def modify_tensors(self, data_torch, name, bid): model_arch = gguf.MODEL_ARCH.MISTRAL3 # unused impl: TextModel - def __init__(self, *args, **kwargs): - super().__init__(*args, **kwargs) + def __init__(self, dir_model, *args, **kwargs): + hparams = ModelBase.load_hparams(dir_model, is_mistral_format=False) + hf_arch = get_model_architecture(hparams, self.model_type) + if hf_arch in ("Ministral3Model", "Mistral3Model"): + text_config = hparams.get("text_config", hparams) + if text_config.get("is_causal") is not False: + raise NotImplementedError(f"Expected a Nemotron Embed model for {hf_arch}, but is_causal is not False") + super().__init__(dir_model, *args, **kwargs) if self.hparams.get("model_type") == "mistral4": - self.impl = Mistral3Model.Mistral4Model(*args, **kwargs) + self.impl = Mistral3Model.Mistral4Model(dir_model, *args, **kwargs) + elif self.hf_arch in ("Ministral3Model", "Mistral3Model"): + self.impl = Mistral3Model.Mistral3EmbedNemotronModel(dir_model, *args, **kwargs) else: - self.impl = Mistral3Model.Ministral3Model(*args, **kwargs) + self.impl = Mistral3Model.Ministral3Model(dir_model, *args, **kwargs) def set_vocab(self): self.impl.set_vocab() @@ -66,3 +93,13 @@ def write_vocab(self): def write(self): self.impl.write() + + +@ModelBase.register("VoxtralRealtimeForConditionalGeneration") +@ModelBase.example("mistralai/Voxtral-Mini-4B-Realtime-2602") +class VoxtralRealtimeModel(LlamaModel): + model_arch = gguf.MODEL_ARCH.MISTRAL3 + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_realtime_delay_tokens(self.hparams["default_num_delay_tokens"]) diff --git a/conversion/mistral4.py b/conversion/mistral4.py new file mode 100644 index 000000000000..dea6b3ecb9b2 --- /dev/null +++ b/conversion/mistral4.py @@ -0,0 +1,217 @@ +from __future__ import annotations + +from typing import Callable, Iterable, TYPE_CHECKING + +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import ModelBase, gguf + +from .mistral import MistralModel, MistralMoeModel + + +@ModelBase.register("MistralLarge4ForConditionalGeneration") +class MistralLarge4Model(MistralMoeModel): + model_arch = gguf.MODEL_ARCH.MISTRAL_LARGE4 + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + n_layer = self.hparams["num_hidden_layers"] + dsa = self.hparams["dsa"] + + def expand(pattern: str) -> list[str]: + values = pattern.split(",") + return [values[i % len(values)] for i in range(n_layer)] + + self.layer_has_rope = [v == "rope" for v in expand(self.hparams.get("nope") or "rope")] + self.layer_indexer_full = [v == "full" for v in expand(dsa.get("sharing") or "full")] + + kv_sharing = self.hparams.get("kv_sharing") or {} + if "source_layers_str" in kv_sharing: + self.layer_kv_source = [int(v) for v in kv_sharing["source_layers_str"].split(",")] + else: + assert not kv_sharing, f"unsupported kv_sharing config: {kv_sharing}" + self.layer_kv_source = list(range(n_layer)) + assert len(self.layer_kv_source) == n_layer + + # note: the rope dim of the indexer must match the main attention + assert dsa.get("rope_head_dim", -1) in (-1, self.hparams["qk_rope_head_dim"]) + assert dsa.get("match_nope", False), "indexer must follow the NoPE pattern of the main attention" + assert dsa.get("ssmax_scaling", False), "indexer without SSMax is not supported" + assert self.hparams.get("q_lora_rank") is None + assert not self.hparams["yarn"].get("apply_scale", True), "only YaRN without magnitude scaling is supported" + + def dequant_model(self): + quant_config = self.hparams.get("quantization") + if quant_config is not None: + assert quant_config["qformat_weight"] == "fp8_e4m3" + assert quant_config.get("qscheme_weight") == "BLOCK" + self.hparams["quantization_config"] = { + "quant_method": "fp8", + "weight_block_size": [quant_config["block_size_out"], quant_config["block_size_in"]], + } + return super().dequant_model() + + def set_gguf_parameters(self): + # skip the MistralMoeModel overrides, they apply the deepseek2 YaRN scaling + super(MistralMoeModel, self).set_gguf_parameters() + MistralModel.set_mistral_config(self.gguf_writer, self.hparams) + + dsa = self.hparams["dsa"] + self.gguf_writer.add_indexer_head_count(dsa["n_heads"]) + self.gguf_writer.add_indexer_key_length(dsa["head_dim"]) + self.gguf_writer.add_indexer_top_k(dsa["topk"]) + self.gguf_writer.add_indexer_types(self.layer_indexer_full) + self.gguf_writer.add_layer_norm_eps(dsa.get("norm_eps", 1e-6)) + + self.gguf_writer.add_rope_pattern(self.layer_has_rope) + self.gguf_writer.add_kv_source_map(self.layer_kv_source) + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SOFTMAX) + self.gguf_writer.add_final_logit_softcapping(self.hparams["softmax_tanh_gating"]) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + + # exported separately with --dspark + if name.startswith("mtp_"): + return None + + # experts need HF names for the merging logic in DeepseekV2Model + # note: bare "layers.N.experts" comes from the NVFP4 quantized_layers config + if ".experts." in name or name.endswith(".experts"): + name = "model." + name.replace(".experts", ".mlp.experts") + name = name.replace(".w1.", ".gate_proj.").replace(".w2.", ".down_proj.").replace(".w3.", ".up_proj.") + + # skip the MistralMoeModel renaming, the qscale names are needed for block FP8 dequant + return super(MistralMoeModel, cls).filter_tensors((name, gen)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name == "lerope.alpha": + # LeRoPE scales inv_freq by exp(alpha), ggml divides theta by the freq factors + yield (self.format_tensor_name(gguf.MODEL_TENSOR.ROPE_FREQS), torch.exp(-data_torch.float())) + return + + if bid is not None and name.endswith((".ssmax_scaling.s", ".ssmax_scaling.b")): + tensor = gguf.MODEL_TENSOR.INDEXER_SSMAX if ".indexer." in name else gguf.MODEL_TENSOR.ATTN_SSMAX + suffix = ".weight" if name.endswith(".s") else ".bias" + yield (self.format_tensor_name(tensor, bid, suffix), data_torch.float()) + return + + if bid is not None and ".indexer.q_input_norm." in name: + suffix = ".weight" if name.endswith(".weight") else ".bias" + yield (self.format_tensor_name(gguf.MODEL_TENSOR.INDEXER_Q_NORM, bid, suffix), data_torch) + return + + if bid is not None and ".indexer." in name: + name = "model." + name.replace(".attention.", ".self_attn.") + + # NoPE layers have a larger non-rotary head, so wkv_b is split per layer + if bid is not None and name.endswith(".wkv_b.weight"): + n_head = self.hparams["num_attention_heads"] + v_head_dim = self.hparams["v_head_dim"] + qk_nope_head_dim = self.hparams["qk_nope_head_dim"] + if not self.layer_has_rope[bid]: + qk_nope_head_dim += self.hparams["qk_rope_head_dim"] + + assert data_torch.shape[0] == n_head * (qk_nope_head_dim + v_head_dim) + + kv_b = data_torch.view(n_head, qk_nope_head_dim + v_head_dim, data_torch.shape[-1]) + k_b, v_b = torch.split(kv_b, [qk_nope_head_dim, v_head_dim], dim=1) + k_b = k_b.transpose(1, 2) + + yield (self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_K_B, bid), k_b) + yield (self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_V_B, bid), v_b) + return + + yield from super().modify_tensors(data_torch, name, bid) + + +class MistralLarge4DSparkModel(MistralLarge4Model): + """Mistral Large 4 DSpark draft (mtp_dspark.*) as a DFLASH GGUF, export with --dspark""" + model_arch = gguf.MODEL_ARCH.DFLASH + + _DSPARK_ROOT: dict[str, gguf.MODEL_TENSOR] = { + "backbone.target_projection.weight": gguf.MODEL_TENSOR.FC, + "backbone.target_norm.weight": gguf.MODEL_TENSOR.ENC_OUTPUT_NORM, + "backbone.final_norm.weight": gguf.MODEL_TENSOR.OUTPUT_NORM, + "backbone.mask_embedding": gguf.MODEL_TENSOR.DSPARK_MASK_EMBD, + "autoregressive_head.embedding.weight": gguf.MODEL_TENSOR.DSPARK_MARKOV_W1, + "autoregressive_head.output.weight": gguf.MODEL_TENSOR.DSPARK_MARKOV_W2, + "autoregressive_head.joint_proj.weight": gguf.MODEL_TENSOR.DSPARK_JOINT_PROJ, + "autoregressive_head.joint_proj.bias": gguf.MODEL_TENSOR.DSPARK_JOINT_PROJ, + } + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + mtp = self.hparams.get("mtp") or {} + dspark = mtp.get("dspark") + if dspark is None: + raise ValueError("Mistral Large 4 DSpark export needs the mtp.dspark config") + assert dspark.get("head_type") == "rnn", f"unsupported DSpark head type: {dspark.get('head_type')}" + assert dspark.get("draft_input") == "position_specific", f"unsupported DSpark draft input: {dspark.get('draft_input')}" + + windows = {int(v) for v in (mtp.get("ragged_attention") or "").split(",") if v.strip()} + assert len(windows) == 1, f"DSpark draft layers must share one sliding window, got {mtp.get('ragged_attention')}" + + self._n_stage = int(mtp["n_layers"]) + self._depth = int(mtp["depth"]) + self._window = windows.pop() + self._target_layers = [int(v) for v in mtp["target_activation_layers"].split(",")] + + self.layer_has_rope = [True] * self._n_stage + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + if not name.startswith("mtp_dspark."): + return None + name = name.removeprefix("mtp_dspark.") + if name.startswith("backbone.layers."): + return name.removeprefix("backbone."), gen + return f"dspark.{name}", gen + + def set_vocab(self): + super().set_vocab() + # block uses mask_embd, mask token id is not used + self.gguf_writer.add_mask_token_id(0) + + def set_gguf_parameters(self): + hp = self.hparams + w = self.gguf_writer + w.add_block_count(self._n_stage) + w.add_context_length(hp["max_position_embeddings"]) + w.add_embedding_length(hp["hidden_size"]) + w.add_feed_forward_length(hp["intermediate_size"]) + w.add_head_count(hp["num_attention_heads"]) + w.add_head_count_kv(1) + w.add_key_length(hp["kv_lora_rank"] + hp["qk_rope_head_dim"]) + w.add_value_length(hp["kv_lora_rank"]) + w.add_key_length_mla(hp["qk_nope_head_dim"] + hp["qk_rope_head_dim"]) + w.add_value_length_mla(hp["v_head_dim"]) + w.add_kv_lora_rank(hp["kv_lora_rank"]) + w.add_rope_dimension_count(hp["qk_rope_head_dim"]) + w.add_rope_freq_base(float(hp["rope_theta"])) + w.add_layer_norm_rms_eps(hp["rms_norm_eps"]) + MistralModel.set_mistral_config(w, hp) + w.add_sliding_window(self._window) + w.add_final_logit_softcapping(hp["softmax_tanh_gating"]) + w.add_block_size(self._depth) + # draft reads layer output = input of next layer + w.add_target_layers([layer + 1 for layer in self._target_layers]) + w.add_sample_from_anchor(True) + w.add_has_confidence_head(False) + w.add_file_type(self.ftype) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith("dspark."): + key = name.removeprefix("dspark.") + if key not in self._DSPARK_ROOT: + raise ValueError(f"Unexpected DSpark tensor {name!r}") + suffix = ".bias" if key.endswith(".bias") else ".weight" + yield (self.format_tensor_name(self._DSPARK_ROOT[key], None, suffix), data_torch) + return + + yield from super().modify_tensors(data_torch, name, bid) diff --git a/conversion/muse_glimmer.py b/conversion/muse_glimmer.py index c86b33227366..9b63d3dba64a 100644 --- a/conversion/muse_glimmer.py +++ b/conversion/muse_glimmer.py @@ -94,7 +94,7 @@ def set_gguf_parameters(self): assert self.hparams_vision is not None c = self.hparams_vision # enriched vision_config from get_vision_config() - self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.MUSE_GLIMMER) + self.gguf_writer.add_clip_vision_projector_type(gguf.VisionProjectorType.MUSE_GLIMMER) self.gguf_writer.add_vision_attention_layernorm_eps(float(c["layer_norm_eps"])) self.gguf_writer.add_vision_spatial_merge_size(int(c["merge_size"])) diff --git a/conversion/muse_spark.py b/conversion/muse_spark.py new file mode 100644 index 000000000000..150f22f95940 --- /dev/null +++ b/conversion/muse_spark.py @@ -0,0 +1,221 @@ +from __future__ import annotations + +from typing import Any, Iterable, TYPE_CHECKING + +import torch + +if TYPE_CHECKING: + from torch import Tensor + +from .base import ModelBase, MmprojModel, TextModel, gguf +from .muse_glimmer import MuseGlimmerVisionModel + + +# The reference clamps the squared stream coefficient with this floor. +RESIDUAL_GATE_EPS = 1e-3 + +# Block norms hold a delta around one; the output norm holds an absolute gain. +OFFSET_NORM_SUFFIXES = ( + "input_layernorm.weight", + "pre_feedforward_layernorm.weight", + "post_feedforward_layernorm.weight", + "pre_expert_norm.weight", + "post_expert_norm.weight", +) + + +def _unpermute_for_rope(tensor: "Tensor", n_heads: int) -> "Tensor": + """Invert transformers' `_permute_for_rope`: HF stores Q/K in rotate_half layout, + llama.cpp consumes the interleaved (NORM) layout. Vision Q/K carry a bias too.""" + if tensor.ndim == 1: + dim1, = tensor.shape + return tensor.view(n_heads, 2, dim1 // n_heads // 2).transpose(1, 2).reshape(dim1) + dim1, dim2 = tensor.shape + return tensor.view(n_heads, 2, dim1 // n_heads // 2, dim2).transpose(1, 2).reshape(dim1, dim2) + + +@ModelBase.register("MuseSparkForConditionalGeneration") +@ModelBase.example("meta-models/Muse-Spark-Open-816B-A42B") +class MuseSparkModel(TextModel): + model_arch = gguf.MODEL_ARCH.MUSE_SPARK + + def set_vocab(self): + self._set_vocab_gpt2() + + from transformers import AutoTokenizer + tok = AutoTokenizer.from_pretrained(self.dir_model) + eot_id = tok.convert_tokens_to_ids("<|eot|>") # ty: ignore[unresolved-attribute] + if isinstance(eot_id, int) and eot_id >= 0: + self.gguf_writer.add_eot_token_id(eot_id) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hparams = self.hparams + + # MetaP resolves to two scalars + # The output multiplier lands here and the attention scale rides on the synthesized QK-norm weights + self.gguf_writer.add_logit_scale(hparams["output_multiplier"]) + self.gguf_writer.add_final_logit_softcapping(hparams["final_logit_softcapping"]) + + self.gguf_writer.add_post_norm_eps(hparams["post_norm_eps"]) + + # Only the sliding layers carry rope, so the graph takes it from the pattern + sliding = [t == "sliding_attention" for t in hparams["layer_types"]] + theta = hparams["rope_parameters"]["rope_theta"] + assert sliding == [bool(t) for t in hparams["layer_rope_theta"]] + assert all(t in (0, theta) for t in hparams["layer_rope_theta"]) + assert all(t == "sparse" for t in hparams["mlp_layer_types"]) + + self.gguf_writer.add_sliding_window(hparams["sliding_window"]) + self.gguf_writer.add_rope_freq_base_swa(theta) + self.gguf_writer.add_sliding_window_pattern(sliding) + + # Experts live in a latent space narrower than the residual stream. + self.gguf_writer.add_moe_latent_size(hparams["moe_hidden_size"]) + self.gguf_writer.add_expert_feed_forward_length(hparams["moe_intermediate_size"]) + self.gguf_writer.add_expert_weights_scale(hparams["routed_scaling_factor"]) + self.gguf_writer.add_expert_weights_norm(True) + # the config carries no score function, the reference hardcodes sigmoid + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.endswith(OFFSET_NORM_SUFFIXES): + data_torch = data_torch + 1.0 + + if name.endswith(".self_attn.q_proj.weight"): + assert bid is not None + n_head = self.hparams["num_attention_heads"] + head_dim = self.hparams["head_dim"] + + yield self.map_tensor_name(name), _unpermute_for_rope(data_torch, n_head) + + # Synthesize QK-norm to carry the MetaP scale so the graph keeps the plain 1 / sqrt(head_dim) + ones = torch.ones(head_dim, dtype=torch.float32) + q_norm = ones * self.hparams["qk_scale_factor"] + yield self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_Q_NORM, bid), q_norm + yield self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_K_NORM, bid), ones + return + + if name.endswith(".self_attn.k_proj.weight"): + n_head_kv = self.hparams["num_key_value_heads"] + yield self.map_tensor_name(name), _unpermute_for_rope(data_torch, n_head_kv) + return + + # gate_up_proj fuses both projections over the output dim, gate first. + if name.endswith(".mlp.experts.gate_up_proj"): + assert bid is not None + n_ff = data_torch.shape[1] // 2 + yield self.format_tensor_name(gguf.MODEL_TENSOR.FFN_GATE_EXP, bid), data_torch[:, :n_ff, :] + yield self.format_tensor_name(gguf.MODEL_TENSOR.FFN_UP_EXP, bid), data_torch[:, n_ff:, :] + return + + if name.endswith(".mlp.experts.down_proj"): + assert bid is not None + yield self.format_tensor_name(gguf.MODEL_TENSOR.FFN_DOWN_EXP, bid), data_torch + return + + # The router scales its logits by the MetaP output multiplier before the sigmoid + # Fold it into the weight to keep a plain matmul + if name.endswith(".mlp.gate.weight"): + data_torch = data_torch.float() * self.hparams["output_multiplier"] + yield from super().modify_tensors(data_torch, name, bid) + return + + # Norm preserving residual gate: alpha scales the stream, beta the branch, with alpha^2 + beta^2 = 1 + # Both follow from the weight, so resolve them here + if name.endswith("_residual_gate.gate"): + assert bid is not None + attn = "post_attention" in name + + w = data_torch.float() / self.hparams["residual_gate_temperature"] + beta = torch.sigmoid(w) + alpha_sq = torch.sigmoid(-w) * (1.0 + beta) + alpha = torch.sqrt(torch.clamp(alpha_sq, min=RESIDUAL_GATE_EPS)) + + t_alpha = gguf.MODEL_TENSOR.ATTN_RESID_ALPHA if attn else gguf.MODEL_TENSOR.FFN_RESID_ALPHA + t_beta = gguf.MODEL_TENSOR.ATTN_RESID_BETA if attn else gguf.MODEL_TENSOR.FFN_RESID_BETA + yield self.format_tensor_name(t_alpha, bid), alpha + yield self.format_tensor_name(t_beta, bid), beta + return + + yield from super().modify_tensors(data_torch, name, bid) + + +@ModelBase.register("MuseSparkForConditionalGeneration") +@ModelBase.example("meta-models/Muse-Spark-Open-816B-A42B") +class MuseSparkVisionModel(MuseGlimmerVisionModel): + has_vision_encoder = True # same vision encoder as Muse Glimmer + has_audio_encoder = True + + def get_audio_config(self) -> dict[str, Any]: + c = self.global_config["audio_config"] + # the base class wants one width and one layer count: use the last stage width and the total number of conv blocks + return { + **c, + "hidden_size": c["hidden_sizes"][-1], + "intermediate_size": int(c["hidden_sizes"][-1] * c["mlp_ratio"]), + "num_attention_heads": 1, + "num_hidden_layers": sum(c["depths"]), + } + + def set_gguf_parameters(self): + super().set_gguf_parameters() + + assert self.hparams_audio + a = self.hparams_audio + + self.gguf_writer.add_clip_audio_projector_type(gguf.VisionProjectorType.MUSE_SPARK_AUDIO) + # the input is the raw waveform, one channel takes the place of the mel bins + self.gguf_writer.add_audio_num_mel_bins(1) + self.gguf_writer.add_audio_attention_layernorm_eps(float(a["rms_norm_eps"])) + self.gguf_writer.add_audio_conv_kernel_size(int(a["conv_kernel_size"])) + self.gguf_writer.add_audio_hidden_sizes([int(x) for x in a["hidden_sizes"]]) + self.gguf_writer.add_audio_patch_sizes([int(x) for x in a["patch_sizes"]]) + self.gguf_writer.add_audio_depths([int(x) for x in a["depths"]]) + + @classmethod + def filter_tensors(cls, item): + name, gen = item + if name.startswith("model.audio_tower."): + return MmprojModel.filter_tensors((name, gen)) + return super().filter_tensors((name, gen)) + + _AUDIO_HEAD = { + "model.audio_tower.norm": gguf.MODEL_TENSOR.A_PRE_NORM, + "model.audio_tower.proj": gguf.MODEL_TENSOR.A_MMPROJ_FC, + "model.audio_tower.post_proj_norm": gguf.MODEL_TENSOR.A_POST_NORM, + } + + def _audio_tensor(self, data_torch, name, suffix): + assert self.hparams_audio + + stem = name[: -len(suffix) - 1] + + if stem in self._AUDIO_HEAD: + return self.format_tensor_name(self._AUDIO_HEAD[stem], suffix="." + suffix), data_torch + + parts = stem.split(".") + stage = int(parts[3]) + + if parts[4] == "patch_embedder": + key = (gguf.MODEL_TENSOR.A_ENC_PATCH_PROJ if parts[5] == "proj" + else gguf.MODEL_TENSOR.A_ENC_PATCH_NORM) + return self.format_tensor_name(key, bid=stage, suffix="." + suffix), data_torch + + # conv blocks are numbered per stage upstream and flat here + depths = [int(d) for d in self.hparams_audio["depths"]] + bid = sum(depths[:stage]) + int(parts[5]) + tail = ".".join(parts[6:]) + key = { + "conv": gguf.MODEL_TENSOR.A_ENC_CONV1D, + "norm": gguf.MODEL_TENSOR.A_ENC_CONV1D_NORM, + "mlp.fc1": gguf.MODEL_TENSOR.A_ENC_FFN_UP, + "mlp.fc2": gguf.MODEL_TENSOR.A_ENC_FFN_DOWN, + }[tail] + return self.format_tensor_name(key, bid=bid, suffix="." + suffix), data_torch + + def modify_tensors(self, data_torch, name, bid): + if name.startswith("model.audio_tower."): + yield self._audio_tensor(data_torch, name, name.rpartition(".")[2]) + return + yield from super().modify_tensors(data_torch, name, bid) diff --git a/conversion/nemotron.py b/conversion/nemotron.py index f7eefcf8d0ea..371f5b616f64 100644 --- a/conversion/nemotron.py +++ b/conversion/nemotron.py @@ -1,16 +1,119 @@ from __future__ import annotations -from typing import Any, Callable, Iterable, TYPE_CHECKING +import re +from typing import Any, Callable, Iterable, Sequence, TYPE_CHECKING +import numpy as np import torch if TYPE_CHECKING: from pathlib import Path from torch import Tensor -from .base import MmprojModel, ModelBase, TextModel, gguf, logger +from .base import MmprojModel, ModelBase, ModelType, TextModel, get_model_architecture, gguf, logger from .granite import GraniteHybridModel +from .qwen import DFlashModel + + +@ModelBase.register("LiLiCorrDraftModel") +class LiLiCorrDraftModel(DFlashModel): + model_arch = gguf.MODEL_ARCH.DFLASH + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + prefix = "model.lilicorr." + if not any(name.startswith(prefix) for name in self.model_tensors): + raise ValueError("no lilicorr.* tensors found") + dflash_config = self.hparams["dflash_config"] + self.lilicorr_geometry = { + "hidden_size": int(dflash_config["lilicorr_hidden_size"]), + "candidate_topk": int(dflash_config["lilicorr_candidate_topk"]), + "num_heads": int(dflash_config["lilicorr_num_heads"]), + "num_layers": int(dflash_config["lilicorr_num_layers"]), + "factor_dim": int(dflash_config["lilicorr_factor_dim"]), + "mlp_hidden_size": self.model_tensors[prefix + "layers.0.mlp.up_proj.weight"]().shape[0], + } + self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self.block_count + self.lilicorr_geometry["num_layers"] + 1) + block = int(dflash_config.get("block_size", self.hparams.get("block_size", 16))) + topk = self.lilicorr_geometry["candidate_topk"] + heads = self.lilicorr_geometry["num_heads"] + nodes = (block - 1) * topk + relative = gguf.LazyBase.to_eager(self.model_tensors.pop(prefix + "relative_slot_bias")()).float().cpu().numpy() + same = gguf.LazyBase.to_eager(self.model_tensors.pop(prefix + "same_slot_bias")()).float().cpu().numpy() + bias = np.empty((heads, nodes, nodes), dtype=np.float32) + for q in range(nodes): + q_slot = q // topk + for k in range(nodes): + k_slot = k // topk + bias[:, q, k] = relative[:, q_slot - k_slot + block - 1] + if q_slot == k_slot: + bias[:, q, k] += same + self.model_tensors[prefix + "attention_bias.bias"] = lambda bias=bias: torch.from_numpy(bias) + for name in ("slot_embedding", "rank_embedding"): + gen = self.model_tensors.pop(prefix + name) + self.model_tensors[prefix + name + ".weight"] = lambda gen=gen: gen().reshape(-1, self.lilicorr_geometry["hidden_size"]) + for i in range(self.lilicorr_geometry["num_layers"]): + layer_prefix = prefix + f"layers.{i}.attn.in_proj" + for suffix in ("weight", "bias"): + self.model_tensors[layer_prefix + "." + suffix] = self.model_tensors.pop(layer_prefix + "_" + suffix) + dflash_config["selector_rank"] = 0 + dflash_config["selector_top_k"] = 0 + + def set_vocab(self): + if self.target_model_dir is None: + raise ValueError("LiLiCorr draft requires --target-model-dir") + from . import get_model_class + target_text_config = ModelBase.load_hparams(self.target_model_dir, False) + target_text_config = {**target_text_config, **target_text_config.get("text_config", {})} + target_arch = get_model_architecture(target_text_config, ModelType.TEXT) + target_cls = get_model_class(target_arch) + original_dir = self.dir_model + self.dir_model = self.target_model_dir + try: + if target_arch == "NemotronHForCausalLM": + self.is_moe = "num_experts_per_tok" in target_text_config + target_cls.set_vocab(self) # ty: ignore[unresolved-attribute] + finally: + self.dir_model = original_dir + self.gguf_writer.add_mask_token_id(self.hparams["dflash_config"]["mask_token_id"]) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + dflash_config = self.hparams["dflash_config"] + self.gguf_writer.add_lilicorr_hidden_size(int(self.lilicorr_geometry["hidden_size"])) + self.gguf_writer.add_lilicorr_candidate_topk(int(self.lilicorr_geometry["candidate_topk"])) + self.gguf_writer.add_lilicorr_num_heads(int(self.lilicorr_geometry["num_heads"])) + self.gguf_writer.add_lilicorr_num_layers(int(self.lilicorr_geometry["num_layers"])) + self.gguf_writer.add_lilicorr_factor_dim(int(self.lilicorr_geometry["factor_dim"])) + self.gguf_writer.add_lilicorr_mlp_hidden_size(int(self.lilicorr_geometry["mlp_hidden_size"])) + self.gguf_writer.add_lilicorr_vector_eps(float(dflash_config["lilicorr_vector_eps"])) + self.gguf_writer.add_lilicorr_logit_scale(float(dflash_config["lilicorr_logit_scale"])) + + def map_tensor_name(self, name: str, try_suffixes: Sequence[str] = (".weight", ".bias")) -> str: + if name.startswith("model.lilicorr.layers."): + parts = name.split(".", 4) + if not parts[4].startswith("attn.in_proj."): + parts[3] = str(self.block_count + int(parts[3])) + name = ".".join(parts) + elif name.startswith("model.lilicorr.feature_norm."): + feature_bid = self.block_count + self.lilicorr_geometry["num_layers"] + name = name.replace("model.lilicorr.feature_norm.", f"model.lilicorr.feature_mlp.{feature_bid}.norm.") + elif name.startswith("model.lilicorr.feature_mlp."): + feature_bid = self.block_count + self.lilicorr_geometry["num_layers"] + name = name.replace("model.lilicorr.feature_mlp.", f"model.lilicorr.feature_mlp.{feature_bid}.") + return super().map_tensor_name(name, try_suffixes) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith("model.lilicorr."): + yield self.map_tensor_name(name), data_torch + return + yield from super().modify_tensors(data_torch, name, bid) + + def tensor_force_quant(self, name: str, new_name: str, bid: int | None, n_dims: int) -> gguf.GGMLQuantizationType | bool: + if name.startswith("model.lilicorr."): + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) @ModelBase.register( @@ -152,15 +255,134 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter yield mapped_name, tensor +@ModelBase.register("NemotronH_Omni_Reasoning_V3") +class NemotronOmniVLModel(NemotronNanoV2VLModel): + _omni_tensor_prefixes = ( + "vision_model.embeddings.", + "vision_model.encoder.layer.", + "vision_projector.mlp1.", + ) + + def get_vision_config(self) -> dict[str, Any] | None: + vision_config = dict(self.global_config["vision_config"]) + vision_config["intermediate_size"] = int(vision_config["hidden_size"] * vision_config["mlp_ratio"]) + vision_config["image_size"] = 512 # warmup only; the full position table is resized at runtime + return vision_config + + def set_gguf_parameters(self): + preprocessor_config = self.preprocessor_config + + preprocessor_config["image_mean"] = preprocessor_config["norm_mean"] + preprocessor_config["image_std"] = preprocessor_config["norm_std"] + + MmprojModel.set_gguf_parameters(self) + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.NEMOTRON_OMNI) + self.gguf_writer.add_vision_attention_layernorm_eps(1e-6) + self.gguf_writer.add_vision_use_gelu(True) + downsample_ratio = self.global_config.get("downsample_ratio", 0.5) + self.gguf_writer.add_vision_projector_scale_factor(int(1.0 / downsample_ratio)) + patch_area = self.hparams["patch_size"] ** 2 + self.gguf_writer.add_vision_min_pixels(preprocessor_config["min_num_patches"] * patch_area) + self.gguf_writer.add_vision_max_pixels(preprocessor_config["max_num_patches"] * patch_area) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + + # Transformers can rename RADIO and projector tensors in Omni checkpoints. + # Accept both checkpoint layouts. + if name == "vision_model.summary_idxs": + # This buffer is only used by RadioModel.summary. The multimodal + # projector consumes RadioModel.features for both images and video. + return None + if name.startswith(cls._omni_tensor_prefixes): + return name, gen + + if "radio_model.model.patch_generator.video_embedder" in name or name.startswith("vision_projector.vision_final_layernorm."): + return MmprojModel.filter_tensors((name, gen)) + + return super().filter_tensors(item) + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if new_name in ("v.position_embd.weight", "v.class_embd"): + return gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith(self._omni_tensor_prefixes): + if name == "vision_model.embeddings.video_patch_projection.weight": + data_torch = data_torch.reshape( + self.hparams["hidden_size"], + 6, + self.hparams["patch_size"], + self.hparams["patch_size"], + ) + yield gguf.TENSOR_NAMES[gguf.MODEL_TENSOR.V_ENC_EMBD_PATCH] + ".weight.1", data_torch + return + + if name.startswith("vision_projector.mlp1."): + projector_mapping = { + "vision_projector.mlp1.norm.weight": "mlp1.0.weight", + "vision_projector.mlp1.linear1.weight": "mlp1.1.weight", + "vision_projector.mlp1.linear2.weight": "mlp1.3.weight", + } + name = projector_mapping[name] + elif name == "vision_model.embeddings.patch_projection.weight": + data_torch = data_torch.reshape( + self.hparams["hidden_size"], + 3, + self.hparams["patch_size"], + self.hparams["patch_size"], + ) + elif name == "vision_model.embeddings.position_embedding": + data_torch = data_torch.squeeze(0) + name += ".weight" + elif ".layer_scale" in name and name.endswith(".lambda1"): + name = name.removesuffix("lambda1") + "weight" + + yield from MmprojModel.modify_tensors(self, data_torch, name, bid) + return + + if "patch_generator.pos_embed" in name: + # Keep the full table for runtime interpolation. + yield from MmprojModel.modify_tensors(self, data_torch, name, bid) + return + + if "patch_generator.video_embedder" in name: + patch_size = self.hparams["patch_size"] + n_embd = self.hparams["hidden_size"] + temporal_patch_size = self.global_config["video_temporal_patch_size"] + if temporal_patch_size != 2: + raise ValueError("Current implementation only supports a temporal patch size of 2") + data_torch = data_torch.reshape(n_embd, temporal_patch_size * 3, patch_size, patch_size) + new_name = gguf.TENSOR_NAMES[gguf.MODEL_TENSOR.V_ENC_EMBD_PATCH] + ".weight.1" + yield new_name, data_torch + return + + yield from super().modify_tensors(data_torch, name, bid) + + @ModelBase.register("NemotronForCausalLM") @ModelBase.example("nvidia/Minitron-4B-Base") class NemotronModel(TextModel): model_arch = gguf.MODEL_ARCH.NEMOTRON def set_vocab(self): - self._set_vocab_sentencepiece() - self.gguf_writer.add_pad_token_id(0) - self.gguf_writer.add_unk_token_id(1) + if (self.dir_model / "tokenizer.model").exists(): + self._set_vocab_sentencepiece() + self.gguf_writer.add_pad_token_id(0) + self.gguf_writer.add_unk_token_id(1) + else: + # SPM-style BPE (Metaspace + byte fallback): mark <0xXX> tokens as BYTE so they decode to raw bytes + tokens, toktypes, tokpre = self.get_vocab_base() + toktypes = [gguf.TokenType.BYTE if re.fullmatch(r"<0x[0-9A-F]{2}>", tok) else typ for tok, typ in zip(tokens, toktypes)] + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + special_vocab.add_to_gguf(self.gguf_writer) def set_gguf_parameters(self): super().set_gguf_parameters() @@ -174,7 +396,10 @@ def set_gguf_parameters(self): rot_pct = self.rope_parameters["partial_rotary_factor"] n_embd = self.find_hparam(["hidden_size", "n_embd"]) n_head = self.find_hparam(["num_attention_heads", "n_head"]) - self.gguf_writer.add_rope_dimension_count(int(rot_pct * n_embd) // n_head) + # Use explicit head_dim when available; fallback keeps standard Nemotron working. + # Without this, models where n_head * head_dim != n_embd (e.g. 48 heads, head_dim=128) produce the wrong rope dimension count. + head_dim = self.hparams.get("head_dim") or n_embd // n_head + self.gguf_writer.add_rope_dimension_count(int(rot_pct * head_dim)) # * RopeScaling for Nemotron factor = self.hparams.get("factor") or self.rope_parameters.get("factor") @@ -208,6 +433,11 @@ class NemotronHModel(GraniteHybridModel): _ATTN_LAYER_TYPES = {"attention", "full_attention"} _MLP_LAYER_TYPES = {"moe"} + def _map_fp8_weight_names(self, name: str) -> tuple[str, ...]: + if ".mixer.experts." in name: + name = name.replace("backbone.", "model.").replace(".mixer.experts.", ".mlp.experts.") + return super()._map_fp8_weight_names(name) + def __init__(self, *args, **kwargs): # We have to determine the correct model architecture (MoE vs non-MoE) before # calling the parent __init__. This is because the parent constructor @@ -283,6 +513,8 @@ def get_attn_layers(self): @classmethod def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: name, gen = item + if name.startswith("language_model."): + name = name[len("language_model."):] if name.startswith("mtp."): # --no-mtp: drop the MTP head entirely if cls.no_mtp: @@ -432,6 +664,14 @@ def set_vocab(self): "mtp.layers.1.final_layernorm.weight": "model.layers.{bid}.shared_head.norm.weight", } + def _generate_nvfp4_tensors(self): + if self._mtp_bid is not None: + for name in list(self.model_tensors): + if name.startswith("mtp.layers.1.mixer"): + new_name = f"backbone.layers.{self._mtp_bid}.{name.split('.', 3)[3]}" + self.model_tensors[new_name] = self.model_tensors.pop(name) + super()._generate_nvfp4_tensors() + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: # mtp.layers.0: NextN input fusion + attention # mtp.layers.1: MoE + final head norm diff --git a/conversion/pockettts.py b/conversion/pockettts.py index 1c99e58cfc77..1b5c841110cf 100644 --- a/conversion/pockettts.py +++ b/conversion/pockettts.py @@ -5,6 +5,7 @@ from typing import Any, Iterable, TYPE_CHECKING import torch +import torch.nn.functional as F if TYPE_CHECKING: from torch import Tensor @@ -45,6 +46,102 @@ def _tensor_shapes(dir_model: Path) -> dict[str, tuple[int, ...]]: return {name: tuple(part[name].shape) for name in part.keys()} +def _has_voice_encoder(dir_model: Path) -> bool: + # without voice cloning, the mimi encoder weights are all zero + part_names = ModelBase.get_model_part_names(dir_model, "model", ".safetensors") + with gguf.utility.SafetensorsLocal(dir_model / part_names[0]) as part: + nonzero = {bool(part[name].mmap_bytes().any()) for name in part.keys() if name.startswith("mimi.encoder")} + if len(nonzero) != 1: + raise ValueError(f"{dir_model}: the mimi encoder is partly zeroed out") + return nonzero.pop() + + +def _load_safetensors(path: Path, prefixes: tuple[str, ...]) -> dict[str, Tensor]: + dtypes = {"F32": torch.float32, "BF16": torch.bfloat16, "I64": torch.int64} + with gguf.utility.SafetensorsLocal(path) as part: + return {name: torch.from_numpy(part[name].mmap_bytes()).view(dtypes[part[name].dtype]).reshape(part[name].shape) + for name in part.keys() if name.startswith(prefixes)} + + +def _rope_pairs(x: Tensor, n_head: int, rope_theta: float) -> Tensor: + # ggml NORM mode rope, x: [n_pos, n_embd] + n_pos, n_embd = x.shape + head_dim = n_embd // n_head + angle = torch.arange(n_pos, dtype=x.dtype)[:, None, None] * \ + torch.pow(rope_theta, -torch.arange(0, head_dim, 2, dtype=x.dtype) / head_dim) + x = x.view(n_pos, n_head, head_dim // 2, 2) + return torch.stack([x[..., 0] * angle.cos() - x[..., 1] * angle.sin(), + x[..., 0] * angle.sin() + x[..., 1] * angle.cos()], -1).reshape(n_pos, n_embd) + + +def _voice_prompt_embd(weights: dict[str, Tensor], kv: list[Tensor], n_head: int, rope_theta: float) -> tuple[Tensor, float]: + # the voice state only has K/V of each layer (kv[il] is [k/v, pos, n_embd]): layer 0 V gives each frame up to its scale, layer 1 V gives the scale + # returns the frames without bos_before_voice, and the max relative K/V error when the frames are prompted again + w = {name: t.double() for name, t in weights.items()} + kv = [t.double() for t in kv] + k0, v0, v1 = kv[0][0], kv[0][1], kv[1][1] + n_pos, n_embd = v0.shape + head_dim = n_embd // n_head + + def p(il: int, name: str) -> Tensor: + return w[f"flow_lm.transformer.layers.{il}.{name}"] + + def norm(x: Tensor, il: int, name: str) -> Tensor: + return F.layer_norm(x, (n_embd,), p(il, f"{name}.weight"), p(il, f"{name}.bias"), 1e-5) + + def heads(t: Tensor) -> Tensor: + return t.reshape(n_pos, n_head, head_dim).transpose(0, 1) + + def rows(t: Tensor) -> Tensor: + return t.transpose(0, 1).reshape(n_pos, n_embd) + + def attn(il: int, h: Tensor, k: Tensor, v: Tensor) -> Tensor: + q = _rope_pairs(h @ p(il, "self_attn.in_proj.weight").chunk(3)[0].T, n_head, rope_theta) + return rows(F.scaled_dot_product_attention(heads(q), heads(k), heads(v), is_causal=True)) @ p(il, "self_attn.out_proj.weight").T + + def ffn(il: int, x: Tensor) -> Tensor: + return F.gelu(norm(x, il, "norm2") @ p(il, "linear1.weight").T) @ p(il, "linear2.weight").T + + wv = p(0, "self_attn.in_proj.weight").chunk(3)[2] + h = torch.linalg.solve(wv, v0.T).T # norm1(x) + z = (h - p(0, "norm1.bias")) / p(0, "norm1.weight") # (x - mean(x)) / std(x) + + # fit z on [speaker_proj, 1] to get the latent direction back + proj = w["flow_lm.speaker_proj_weight"] + fit = torch.linalg.lstsq(torch.cat([proj, torch.ones(n_embd, 1, dtype=proj.dtype)], 1), z[1:].T).solution + frames = (proj @ fit[:-1]).T + + a0 = attn(0, h, k0, v0)[1:] + wv1 = p(1, "self_attn.in_proj.weight").chunk(3)[2] + + def err(scale: Tensor) -> Tensor: # per frame relative error of layer 1 V + x = scale[:, None] * frames + a0 + x = x + ffn(0, x) + return (norm(x, 1, "norm1") @ wv1.T - v1[1:]).norm(dim=1) / v1[1:].norm(dim=1) + + grid = torch.logspace(-3, 3, 49, dtype=torch.float64) + best = torch.stack([err(s.expand(n_pos - 1)) for s in grid]).argmin(0) + lo, hi = grid[(best - 1).clamp(min=0)], grid[(best + 1).clamp(max=len(grid) - 1)] + for _ in range(40): # golden section search, all frames at once + m1, m2 = hi - 0.618 * (hi - lo), lo + 0.618 * (hi - lo) + left = err(m1) < err(m2) + lo, hi = torch.where(left, lo, m1), torch.where(left, m2, hi) + frames = (lo + hi)[:, None] / 2 * frames + + # prompt the frames again and compare K/V with the shipped state + x = torch.cat([w["flow_lm.bos_before_voice"].reshape(1, n_embd), frames]) + drift = 0.0 + for il, (k_ref, v_ref) in enumerate(kv): + h = norm(x, il, "norm1") + _, wk, wv = p(il, "self_attn.in_proj.weight").chunk(3) + k, v = _rope_pairs(h @ wk.T, n_head, rope_theta), h @ wv.T + for a, b in ((k, k_ref), (v, v_ref)): + drift = max(drift, ((a - b).norm(dim=1) / b.norm(dim=1)).median().item()) + x = x + attn(il, h, k, v) + x = x + ffn(il, x) + return frames, drift + + @ModelBase.register_hparams_loader(lambda dir_model: "flow_lm.bos_emb" in _tensor_shapes(dir_model)) def _load_hparams(dir_model: Path) -> dict[str, Any]: logger.info("gguf: detected pocket-tts checkpoint, deriving hparams from tensor shapes") @@ -194,22 +291,27 @@ class PocketTTSMmprojModel(MmprojModel): (gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_Q, gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_K, gguf.MODEL_TENSOR.A_GEN_WAV_TFM_ATTN_V), ) + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + self.has_audio_encoder = _has_voice_encoder(self.dir_model) + def set_gguf_parameters(self): self.gguf_writer.add_file_type(self.ftype) assert self.hparams_audio is not None # voice-prompt encoder: mimi encoder + speaker_proj - self.gguf_writer.add_clip_has_audio_encoder(True) - # note: the 24kHz sample rate is hardcoded on the clip.cpp side, like the other audio models - self.gguf_writer.add_clip_audio_projector_type(gguf.VisionProjectorType.POCKETTTS_SPKENC) - self.gguf_writer.add_audio_projection_dim(self.n_embd_text) - self.gguf_writer.add_audio_block_count(self.hparams_audio["num_hidden_layers"]) - self.gguf_writer.add_audio_embedding_length(self.hparams_audio["hidden_size"]) - self.gguf_writer.add_audio_feed_forward_length(self.hparams_audio["intermediate_size"]) - self.gguf_writer.add_audio_head_count(self.hparams_audio["num_attention_heads"]) - self.gguf_writer.add_audio_attention_layernorm_eps(1e-5) - # mimi convolves the waveform directly, it is passed around as a 1-row "mel" - self.gguf_writer.add_audio_num_mel_bins(1) + if self.has_audio_encoder: + self.gguf_writer.add_clip_has_audio_encoder(True) + # note: the 24kHz sample rate is hardcoded on the clip.cpp side, like the other audio models + self.gguf_writer.add_clip_audio_projector_type(gguf.VisionProjectorType.POCKETTTS_SPKENC) + self.gguf_writer.add_audio_projection_dim(self.n_embd_text) + self.gguf_writer.add_audio_block_count(self.hparams_audio["num_hidden_layers"]) + self.gguf_writer.add_audio_embedding_length(self.hparams_audio["hidden_size"]) + self.gguf_writer.add_audio_feed_forward_length(self.hparams_audio["intermediate_size"]) + self.gguf_writer.add_audio_head_count(self.hparams_audio["num_attention_heads"]) + self.gguf_writer.add_audio_attention_layernorm_eps(1e-5) + # mimi convolves the waveform directly, it is passed around as a 1-row "mel" + self.gguf_writer.add_audio_num_mel_bins(1) # generation: flow-matching decoder + mimi decoder # the SEANet and flow net hparams are constant across the family, clip.cpp holds them @@ -229,12 +331,57 @@ def tensor_force_quant(self, name, new_name, bid, n_dims): # conv1d/conv1d_dw kernels must be F16, ggml_conv_1d(_dw) has no BF16 path if ".seanet." in new_name or new_name in ("a.downsample.conv.weight", "a.gen.wav.upsample.weight"): return gguf.GGMLQuantizationType.F16 + # voices are read on the host + if new_name.startswith("voice."): + return gguf.GGMLQuantizationType.F32 return False + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + # embeddings/<name>.safetensors hold the K/V state after the voice prompt (see get_state_for_audio_prompt() in the reference), turn it back into prompt embeddings + paths = sorted((self.dir_model / "embeddings").glob("*.safetensors")) + if not paths: + return + weights = _load_safetensors(self.dir_model / "model.safetensors", + ("flow_lm.transformer.layers.", "flow_lm.speaker_proj_weight", "flow_lm.bos_before_voice")) + n_layer = self.global_config["num_hidden_layers"] + for path in paths: + state = _load_safetensors(path, ("transformer.layers.",)) + kv = [] + for il in range(n_layer): + prefix = f"transformer.layers.{il}.self_attn/" + if any(prefix + k not in state for k in ("cache", "offset")): + break + n_pos = int(state[prefix + "offset"].item()) + # older packs have no pad entry + if prefix + "pad" in state and int(state[prefix + "pad"].item()) != 0: + break + kv.append(state[prefix + "cache"][:, 0, :n_pos].flatten(2)) # [k/v, pos, n_embd] + if len(kv) != n_layer or any(t.shape != kv[0].shape for t in kv) or kv[0].shape[1] < 2 or \ + kv[0].shape[2] != self.global_config["hidden_size"]: + logger.warning(f"voice {path.stem}: skipped, not an unpadded voice state of this backbone") + continue + embd, drift = _voice_prompt_embd(weights, kv, self.global_config["num_attention_heads"], + self.global_config["rope_theta"]) + # some packs ship a state made with other weights, the reference still uses it: keep up to 50% error, warn above 5% + if drift > 0.5: + logger.warning(f"voice {path.stem}: skipped, its state does not belong to these weights (error {drift:.1e})") + continue + log = logger.warning if drift > 0.05 else logger.info + log(f"voice {path.stem}: {embd.shape[0]} frames, prompting them again gives the shipped state within {drift:.1e}") + yield (f"voice.{path.stem}", embd.float()) + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # the block index of the mimi transformers is parsed here, not by the base class T = gguf.MODEL_TENSOR + if name.startswith("voice."): + yield (name, data_torch) + return + + if not self.has_audio_encoder and (name.startswith(("mimi.encoder", "mimi.downsample.")) + or name == "flow_lm.speaker_proj_weight"): + return # voice-prompt encoder + if name in ("flow_lm.bos_emb", "flow_lm.bos_before_voice", "flow_lm.conditioner.embed.weight"): return # folded into the backbone embedding table if name.startswith("flow_lm.transformer.") or name.startswith("flow_lm.out_norm."): diff --git a/conversion/pplx_decider.py b/conversion/pplx_decider.py index f9cfaf9d3de5..b71bd8a3ad23 100644 --- a/conversion/pplx_decider.py +++ b/conversion/pplx_decider.py @@ -3,7 +3,7 @@ import json from pathlib import Path -from typing import Any, Callable, Iterable, TYPE_CHECKING +from typing import Any, Iterable, TYPE_CHECKING import torch @@ -35,6 +35,7 @@ def _load_pplx_decider_hparams(dir_model: Path) -> dict[str, Any]: @ModelBase.register("PplxDeciderModel") @ModelBase.example("perplexity-ai/pplx-decider-v1-27b") +@ModelBase.example("FINAL-Bench/Darwin-27B-ZTC-v5") class PplxDeciderModel(Qwen3_5TextModel): model_arch = gguf.MODEL_ARCH.QWEN35 no_mtp = True # the checkpoint has no MTP head @@ -77,14 +78,6 @@ def set_gguf_parameters(self): for name in ("choice", "score", "noul"): self.gguf_writer.add_decision_temperature(name, self.hparams["decision"]["temperature"]) - @classmethod - def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: - name, gen = item - # the checkpoint is the bare backbone, its text tensors have no "model." prefix - if name.startswith("language_model."): - name = "model." + name - return super().filter_tensors((name, gen)) - def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: yield from super().generate_extra_tensors() from safetensors.torch import load_file @@ -92,7 +85,7 @@ def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: # the readout has one row per option label, store it as an LM head that is zero for the other tokens readout = load_file(self.dir_model / "readout.safetensors")["weight"] token_ids = self.hparams["decision"]["token_ids"] - n_vocab = self.hparams["text_config"]["vocab_size"] + n_vocab = self.hparams["vocab_size"] assert readout.shape[0] == len(token_ids) == len(set(token_ids)) lm_head = torch.zeros(n_vocab, readout.shape[1], dtype=readout.dtype) lm_head[token_ids] = readout diff --git a/conversion/qwen.py b/conversion/qwen.py index 43d2fb466ffe..e6456e5a54de 100644 --- a/conversion/qwen.py +++ b/conversion/qwen.py @@ -59,6 +59,10 @@ class Qwen2Model(TextModel): model_arch = gguf.MODEL_ARCH.QWEN2 def set_vocab(self): + # HuggingFaceBio/Carbon-14B: Qwen3 with the HybridDNATokenizer (Qwen3 BPE plus DNA 6-mers) + if self._is_hybriddna(): + self._set_vocab_hybriddna() + return try: self._set_vocab_sentencepiece() except FileNotFoundError: @@ -79,6 +83,15 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter class Qwen2MoeModel(TextModel): model_arch = gguf.MODEL_ARCH.QWEN2MOE + def _map_fp8_weight_names(self, name: str) -> tuple[str, ...]: + if name.removesuffix(".weight").endswith(".mlp.experts.gate_up_proj"): + bid = next(int(part) for part in self.map_tensor_name(name).split(".") if part.isdecimal()) + return ( + self.format_tensor_name(gguf.MODEL_TENSOR.FFN_GATE_EXP, bid), + self.format_tensor_name(gguf.MODEL_TENSOR.FFN_UP_EXP, bid), + ) + return super()._map_fp8_weight_names(name) + def set_gguf_parameters(self): super().set_gguf_parameters() if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: @@ -253,6 +266,11 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter yield from super().modify_tensors(data_torch, name, bid) return + # output embedding projection (voyage-4-nano) + if name == "linear.weight": + self.gguf_writer.add_embedding_length_out(data_torch.shape[0]) + name = "dense_2_out.weight" + yield from super().modify_tensors(data_torch, name, bid) @@ -373,6 +391,16 @@ def prepare_metadata(self, vocab_only: bool): class Qwen3NextModel(_QwenMtpMixin, Qwen2MoeModel): model_arch = gguf.MODEL_ARCH.QWEN3NEXT + def _map_fp8_weight_names(self, name: str) -> tuple[str, ...]: + if name.endswith(".linear_attn.in_proj_qkvz.weight"): + bid = next(int(part) for part in self.map_tensor_name(name).split(".") if part.isdecimal()) + # Both split projections keep the original per-tensor scales. + return ( + self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_QKV, bid), + self.format_tensor_name(gguf.MODEL_TENSOR.ATTN_GATE, bid), + ) + return super()._map_fp8_weight_names(name) + def set_gguf_parameters(self): super().set_gguf_parameters() self.gguf_writer.add_ssm_conv_kernel(self.hparams["linear_conv_kernel_dim"]) @@ -681,6 +709,52 @@ def set_gguf_parameters(self): self._try_set_pooling_type() +@ModelBase.register("MiniCPMOCRForSequenceClassification") +class MiniCPMOCRSeqClsModel(Qwen3_5TextModel): + # OCR consistency judge: Qwen3.5 VL trunk with a value head read at the last token + # the class scores are [inconsistent, consistent], the softmax temperature is 1 + model_arch = gguf.MODEL_ARCH.QWEN35 + no_mtp = True # the checkpoint has no MTP head + + CLASS_LABELS = ["inconsistent", "consistent"] + + def set_vocab(self): + super().set_vocab() + self.gguf_writer.add_chat_template([{"name": "systemone", "template": self._systemone_template()}]) + + def _systemone_template(self) -> str: + # the prompt of the training data, the two images are the original page and the one + # rendered from the OCR text; the task is fixed, there is nothing to fill in + # the trailing newlines are in an expression, so the template does not drop them + return ( + "<|im_start|>user\n{{ images[0] }}\nOCR文本：\n{{ state }}\n{{ images[1] }}\n" + "第一张图是原图，第二张图是上述 OCR 文本渲染得到的图片。\n" + "请判断该 OCR 文本及其对应渲染图是否与原图内容一致。\n" + "这是一个二分类任务：一致标为 1，不一致标为 0。" + "{{ '<|im_end|>\\n<|im_start|>assistant\\n<think>\\n\\n</think>\\n\\n' }}" + ) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + + # the config.json of the checkpoint keeps the one of the base model, it has no num_labels / id2label + if "score.weight" not in self.model_tensors: + raise ValueError("the checkpoint has no score.weight classification head") + + self.gguf_writer.add_pooling_type(gguf.PoolingType.LAST) + self.gguf_writer.add_embedding_length_out(len(self.CLASS_LABELS)) + self.gguf_writer.add_classifier_output_labels(self.CLASS_LABELS) + self.gguf_writer.add_decision_type(gguf.DecisionType.MINICPM_OCR_JEV) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name == "score.weight": + if data_torch.shape[0] != len(self.CLASS_LABELS): + raise ValueError(f"score.weight must have {len(self.CLASS_LABELS)} rows, got {data_torch.shape[0]}") + yield (gguf.TENSOR_NAMES[gguf.MODEL_TENSOR.CLS_OUT] + ".weight", data_torch) + return + yield from super().modify_tensors(data_torch, name, bid) + + def _is_openjev_checkpoint(dir_model: Path) -> bool: return (dir_model / "helper" / "shim.py").is_file() and (dir_model / "config.json").is_file() diff --git a/conversion/qwen3vl.py b/conversion/qwen3vl.py index 638bcbb246fe..9458366b1001 100644 --- a/conversion/qwen3vl.py +++ b/conversion/qwen3vl.py @@ -144,6 +144,16 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter yield from MmprojModel.modify_tensors(self, data_torch, name, bid) +@ModelBase.register("MiniCPMOCRForSequenceClassification") +class MiniCPMOCRSeqClsVisionModel(Qwen3VLVisionModel): + def set_gguf_parameters(self): + super().set_gguf_parameters() + # trained with the image budget of its processor, wider than the mtmd default of Qwen-VL + size = self.preprocessor_config["size"] + self.gguf_writer.add_vision_min_pixels(int(size["shortest_edge"])) + self.gguf_writer.add_vision_max_pixels(int(size["longest_edge"])) + + @ModelBase.register("Qwen3OmniMoeForConditionalGeneration") @ModelBase.example("Qwen/Qwen3-Omni-30B-A3B-Instruct") class Qwen3OmniMmprojModel(Qwen3VLVisionModel, Qwen25AudioModel): diff --git a/conversion/qwen4exp.py b/conversion/qwen4exp.py index 7ca26c2a3399..8a55d678d74a 100644 --- a/conversion/qwen4exp.py +++ b/conversion/qwen4exp.py @@ -41,6 +41,8 @@ def __init__(self, *args, **kwargs): self._ple_shards: dict[int, str] = {} self._ple_row_dim: int | None = None self._mtp_fc: dict[str, Tensor] = {} + # halves of the merged weights, keyed by (bid, merged tensor), see _merge_shared_input + self._merge_parts: dict[tuple[int, gguf.MODEL_TENSOR], dict[int, Tensor]] = {} @classmethod def filter_tensors(cls, item): @@ -131,44 +133,79 @@ def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iter # int64 hash constants must stay exact; 1-D tensors force F32, so use KV if name.endswith("ple_embedding.layer_multipliers"): self._ple_multipliers = [int(x) for x in data_torch.tolist()] - return [] + return if name.endswith("ple_embedding.ngram_heads_offsets"): self._ple_head_offsets = [int(x) for x in data_torch.tolist()] - return [] + return if name.endswith("ple_embedding.ngram_heads_vocab_sizes"): self._ple_head_vocab_sizes = [int(x) for x in data_torch.tolist()] - return [] + return if ".ngram_embedding.shard_" in name: - return self._place_ple_shard(data_torch, name) + yield from self._place_ple_shard(data_torch, name) + return # eh_proj([e ; h_s]) = fc_embedding(e) + fc_hidden(h_s) for every hc stream s if name.endswith((".nextn_fc_embedding.weight", ".nextn_fc_hidden.weight")): self._mtp_fc[name.rsplit(".", 2)[1]] = data_torch if len(self._mtp_fc) < 2: - return [] + return eh = torch.cat([self._mtp_fc.pop("nextn_fc_embedding"), self._mtp_fc.pop("nextn_fc_hidden")], dim=1) - return [(self.format_tensor_name(gguf.MODEL_TENSOR.NEXTN_EH_PROJ, bid, ".weight"), eh)] + yield (self.format_tensor_name(gguf.MODEL_TENSOR.NEXTN_EH_PROJ, bid, ".weight"), eh) + return # one projection feeds indexer q and k; split it, as minimax-m3 does if ".indexer.index_qk_proj.weight" in name: n_q = self.hparams["indexer_n_heads"] * self.hparams["indexer_head_dim"] - q = data_torch[:n_q] - k = data_torch[n_q:] - return [ - (self.format_tensor_name(gguf.MODEL_TENSOR.INDEXER_Q_PROJ, bid, ".weight"), q), - (self.format_tensor_name(gguf.MODEL_TENSOR.INDEXER_K_PROJ, bid, ".weight"), k), - ] + yield (self.format_tensor_name(gguf.MODEL_TENSOR.INDEXER_Q_PROJ, bid, ".weight"), data_torch[:n_q]) + yield (self.format_tensor_name(gguf.MODEL_TENSOR.INDEXER_K_PROJ, bid, ".weight"), data_torch[n_q:]) + return # Gemma zero-centred gammas the inherited norm.weight rule misses if name.endswith((".ple.norm_key.weight", ".ple.norm_query.weight", ".ple.norm_conv.weight", ".indexer.q_layernorm.weight", ".indexer.k_layernorm.weight")): - return [(self.map_tensor_name(name), data_torch + 1)] + yield (self.map_tensor_name(name), data_torch + 1) + return if name.endswith(".ple.conv1d.weight"): - return [(self.map_tensor_name(name), data_torch.squeeze())] + yield (self.map_tensor_name(name), data_torch.squeeze()) + return + + for new_name, data in super().modify_tensors(data_torch, name, bid): + yield from self._merge_shared_input(new_name, data, bid) + + # matmuls that read the same input, written as one weight [a | b] so the runtime does one matmul: + # (merged tensor, (a, b), linear-attention layers only) + _SHARED_INPUT_MERGES = ( + (gguf.MODEL_TENSOR.HC_ATTN_DOWN_INJECT, (gguf.MODEL_TENSOR.HC_ATTN_DOWN, gguf.MODEL_TENSOR.HC_ATTN_INJECT), False), + (gguf.MODEL_TENSOR.HC_FFN_DOWN_INJECT, (gguf.MODEL_TENSOR.HC_FFN_DOWN, gguf.MODEL_TENSOR.HC_FFN_INJECT), False), + (gguf.MODEL_TENSOR.ATTN_QKV_GATE, (gguf.MODEL_TENSOR.ATTN_QKV, gguf.MODEL_TENSOR.ATTN_GATE), True), + (gguf.MODEL_TENSOR.SSM_BETA_ALPHA_CAT, (gguf.MODEL_TENSOR.SSM_BETA, gguf.MODEL_TENSOR.SSM_ALPHA), True), + ) + + # caches one half of a merged weight until the other half arrives, then yields [a | b] + def _merge_shared_input(self, new_name: str, data: Tensor, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # a pre-quantized checkpoint carries per-tensor scales, which one merged weight cannot hold + if bid is None or self.hparams.get("quantization_config"): + yield (new_name, data) + return + + layer_types = self.hparams.get("layer_types") or [] + is_linear = bid < len(layer_types) and layer_types[bid] == "linear_attention" + + match = next(((merged, parts.index(part)) for merged, parts, linear_only in self._SHARED_INPUT_MERGES + for part in parts + if (is_linear or not linear_only) and self.match_model_tensor_name(new_name, part, bid)), None) + if match is None: + yield (new_name, data) + return - return super().modify_tensors(data_torch, name, bid) + merged, idx = match + halves = self._merge_parts.setdefault((bid, merged), {}) + halves[idx] = data + if len(halves) == 2: + del self._merge_parts[(bid, merged)] + yield (self.format_tensor_name(merged, bid), torch.cat([halves[0], halves[1]], dim=0)) # the shards concatenate into a tensor of well over 100 GB # use LazyChunkedTensor here, a single shard resident at a time @@ -214,6 +251,8 @@ def prepare_tensors(self): super().prepare_tensors() if self._mtp_fc: raise ValueError(f"MTP projection missing its other half: {sorted(self._mtp_fc)}") + if self._merge_parts: + raise ValueError(f"merged weights missing a half: {sorted((bid, t.name) for bid, t in self._merge_parts)}") n_parts = self.hparams.get("split_ngram_parts", 0) if self._ple_shards and len(self._ple_shards) != n_parts: raise ValueError( diff --git a/conversion/sensenova_u1.py b/conversion/sensenova_u1.py new file mode 100644 index 000000000000..bde5f9d9b388 --- /dev/null +++ b/conversion/sensenova_u1.py @@ -0,0 +1,114 @@ +from __future__ import annotations + +from pathlib import Path + +import torch + +from .base import MmprojModel, ModelBase, gguf +from .qwen import Qwen2Model + + +@ModelBase.example("sensenova/SenseNova-U1.5-8B-MoT") +@ModelBase.register("NEOChatModel") +class SenseNovaU1Model(Qwen2Model): + model_arch = gguf.MODEL_ARCH.SENSENOVA_U1 + + @classmethod + def filter_tensors(cls, item): + name, _ = item + if not name.startswith("language_model.") or "_mot_gen" in name: + return None + return super().filter_tensors(item) + + def set_gguf_parameters(self): + if int(self.hparams.get("num_experts") or 0) > 1: + raise ValueError("SenseNova U1 conversion currently supports the dense understanding branch") + if self.rope_parameters.get("rope_type", "default") not in ("default", None): + raise ValueError("SenseNova U1 scaled RoPE is not supported") + if self.hparams.get("attention_bias", False): + raise ValueError("SenseNova U1 attention bias is not supported") + if self.hparams.get("use_sliding_window", False): + raise ValueError("SenseNova U1 sliding attention is not supported") + super().set_gguf_parameters() + self.gguf_writer.add_rope_freq_base_spatial(self.hparams["rope_theta_hw"]) + + def get_tensors(self): + for name, gen in self.model_tensors.items(): + if name.endswith((".q_norm_hw.weight", ".k_norm_hw.weight")): + continue + data = gen() + if name.endswith((".q_norm.weight", ".k_norm.weight")): + spatial = self.model_tensors[name.replace("_norm.weight", "_norm_hw.weight")]() + # Keep one weight vector; the graph normalizes its two halves independently. + data = torch.cat((data, spatial), dim=0) + yield name, data + + +@ModelBase.register("NEOVisionModel") +@ModelBase.example("sensenova/SenseNova-U1.5-8B-MoT") +class SenseNovaU1VisionModel(MmprojModel): + def __init__(self, dir_model: Path, *args, **kwargs): + hparams = kwargs.pop("hparams", None) + if hparams is None: + hparams = ModelBase.load_hparams(dir_model, is_mistral_format=False) + else: + hparams = dict(hparams) + + vision_config = dict(hparams["vision_config"]) + # NEOVisionModel has no transformer blocks + # these defaults satisfy the generic mmproj metadata contract without replacing checkpoint values + vision_config.setdefault("image_size", 0) + vision_config.setdefault("intermediate_size", 0) + vision_config.setdefault("num_hidden_layers", 0) + vision_config.setdefault("num_attention_heads", 1) + hparams["vision_config"] = vision_config + super().__init__(dir_model, *args, hparams=hparams, **kwargs) + + self.preprocessor_config.setdefault("image_mean", [0.485, 0.456, 0.406]) + self.preprocessor_config.setdefault("image_std", [0.229, 0.224, 0.225]) + + @classmethod + def filter_tensors(cls, item): + name, gen = item + if not name.startswith("vision_model."): + return None + return super().filter_tensors((name, gen)) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type("sensenova_u1") + vision_config = self.hparams["vision_config"] + # These defaults match the known U1.5 checkpoint when older configs omit fields. + hidden_size = int(vision_config.get("hidden_size", 1024)) + min_pixels = int(vision_config.get("min_pixels", 65536)) + max_pixels = int(vision_config.get("max_pixels", 16777216)) + downsample_ratio = float(vision_config.get("downsample_ratio", 0.5)) + if downsample_ratio <= 0: + raise ValueError(f"SenseNova U1 downsample_ratio must be positive, got {downsample_ratio}") + merge_size = round(1.0 / downsample_ratio) + if abs((1.0 / downsample_ratio) - merge_size) > 1e-6: + raise ValueError(f"SenseNova U1 downsample_ratio must have an integer reciprocal, got {downsample_ratio}") + norm_eps = float(vision_config.get("layer_norm_eps", vision_config.get("rms_norm_eps", 1e-6))) + self.gguf_writer.add_vision_head_dim(hidden_size) + self.gguf_writer.add_vision_attention_layernorm_eps(norm_eps) + self.gguf_writer.add_vision_min_pixels(min_pixels) + self.gguf_writer.add_vision_max_pixels(max_pixels) + self.gguf_writer.add_vision_spatial_merge_size(merge_size) + + def modify_tensors(self, data_torch, name, bid): + tensor_names = { + "vision_model.embeddings.patch_embedding.weight": "v.patch_embd.weight", + "vision_model.embeddings.patch_embedding.bias": "v.patch_embd.bias", + "vision_model.embeddings.dense_embedding.weight": self.format_tensor_name(gguf.MODEL_TENSOR.V_MMPROJ, 0), + "vision_model.embeddings.dense_embedding.bias": self.format_tensor_name( + gguf.MODEL_TENSOR.V_MMPROJ, 0, suffix=".bias" + ), + } + if name not in tensor_names: + raise ValueError(f"Unexpected SenseNova U1 vision tensor: {name!r}") + return [(tensor_names[name], data_torch)] + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if new_name == self.format_tensor_name(gguf.MODEL_TENSOR.V_MMPROJ, 0): + return gguf.GGMLQuantizationType.F16 if self.ftype == gguf.LlamaFileType.MOSTLY_F16 else gguf.GGMLQuantizationType.F32 + return super().tensor_force_quant(name, new_name, bid, n_dims) diff --git a/conversion/soprano.py b/conversion/soprano.py new file mode 100644 index 000000000000..cf4c959c6ba0 --- /dev/null +++ b/conversion/soprano.py @@ -0,0 +1,116 @@ +from __future__ import annotations + +import json +from pathlib import Path +from typing import Any + +import torch + +from .base import ModelBase, MmprojModel, gguf, logger +from .qwen import Qwen3Model + + +def _is_soprano_checkpoint(dir_model: Path) -> bool: + if not (dir_model / "decoder.pth").is_file() or not (dir_model / "config.json").is_file(): + return False + with open(dir_model / "config.json", encoding="utf-8") as f: + config = json.load(f) + if config.get("model_type") != "qwen3" or config.get("bos_token_id") != 3 or config.get("eos_token_id") != 3: + return False + if not (dir_model / "tokenizer.json").is_file(): + return False + with open(dir_model / "tokenizer.json", encoding="utf-8") as f: + added = {t["id"]: t["content"] for t in json.load(f).get("added_tokens", [])} + return [added.get(i) for i in range(4)] == ["[UNK]", "[TEXT]", "[START]", "[STOP]"] + + +@ModelBase.register_hparams_loader(_is_soprano_checkpoint) +def _load_soprano_hparams(dir_model: Path) -> dict[str, Any]: + logger.info("gguf: detected Soprano checkpoint") + hparams = ModelBase.load_hparams(dir_model, False, guess=False) + # the text model stays Qwen3, the mmproj holds the decoder + hparams["text_config"] = {"architectures": ["SopranoTextModel"]} + hparams["architectures"] = ["SopranoModel"] + return hparams + + +@ModelBase.register("SopranoTextModel") +class SopranoTextModel(Qwen3Model): + model_arch = gguf.MODEL_ARCH.QWEN3 + + def get_vocab_base_pre(self, tokenizer) -> str: + return "soprano" + + def set_vocab(self): + super().set_vocab() + self.gguf_writer.add_unk_token_id(0) + + +@ModelBase.register("SopranoModel") +@ModelBase.example("ekwek/Soprano-80M", "ekwek/Soprano-1.1-80M") +class SopranoModel(MmprojModel): + has_vision_encoder = False + has_audio_encoder = False + + def _load_decoder(self) -> dict[str, torch.Tensor]: + state = torch.load(self.dir_model / "decoder.pth", map_location="cpu", mmap=True, weights_only=True) + return state.get("state_dict", state) + + def get_audio_config(self): + state = self._load_decoder() + n_embd, n_inp, _ = state["decoder.embed.weight"].shape + n_ff = state["decoder.convnext.0.pwconv1.weight"].shape[0] + n_layer = sum(1 for name in state if name.endswith(".pwconv1.weight")) + if n_inp != self.n_embd_text: + raise ValueError(f"Soprano decoder input dim {n_inp} does not match the backbone dim {self.n_embd_text}") + return {"num_hidden_layers": n_layer, "hidden_size": n_embd, "intermediate_size": n_ff} + + def set_gguf_parameters(self): + self.gguf_writer.add_file_type(self.ftype) + self.gguf_writer.add_clip_has_gen_audio_encoder(True) + self.gguf_writer.add_clip_gen_audio_projector_type(gguf.VisionProjectorType.SOPRANO) + self.gguf_writer.add_gen_audio_projection_dim(self.n_embd_text) + self.gguf_writer.add_gen_audio_embedding_length(self.hparams["hidden_size"]) + self.gguf_writer.add_gen_audio_feed_forward_length(self.hparams["intermediate_size"]) + self.gguf_writer.add_gen_audio_block_count(self.hparams["num_hidden_layers"]) + self.gguf_writer.add_gen_audio_head_count(1) + self.gguf_writer.add_gen_audio_attention_layernorm_eps(1e-6) + + def get_tensors(self): + yield from self._load_decoder().items() + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if "dwconv.weight" in new_name or (name == "decoder.embed.weight" and n_dims == 3): + return gguf.GGMLQuantizationType.F16 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def modify_tensors(self, data_torch, name, bid): + if name == "head.istft.window": + # the ISTFT in mtmd builds its own window + if not torch.equal(data_torch.float(), torch.hann_window(data_torch.shape[0])): + raise ValueError("Soprano requires a periodic Hann window") + return + if name == "decoder.embed.weight" and data_torch.shape[-1] == 1: + data_torch = data_torch.squeeze(-1) + + T = gguf.MODEL_TENSOR + if name.startswith("decoder.convnext."): + _, _, blk, key, *suffix = name.split(".") + block_map = { + "dwconv": T.A_GEN_WAV_UP_DWCONV, + "norm": T.A_GEN_WAV_UP_NORM, + "pwconv1": T.A_GEN_WAV_UP_PW1, + "pwconv2": T.A_GEN_WAV_UP_PW2, + "gamma": T.A_GEN_WAV_UP_GAMMA, + } + yield self.format_tensor_name(block_map[key], int(blk), suffix="".join("." + s for s in suffix)), data_torch + return + + tensor_map = { + "decoder.embed": T.A_GEN_WAV_INPUT, + "decoder.norm": T.A_GEN_WAV_NORM, + "decoder.final_layer_norm": T.A_GEN_WAV_OUTPUT_NORM, + "head.out": T.A_GEN_WAV_OUTPUT, + } + key, suffix = name.rsplit(".", 1) + yield self.format_tensor_name(tensor_map[key], suffix="." + suffix), data_torch diff --git a/conversion/ultravox.py b/conversion/ultravox.py index 62819e574d57..4a246daa1466 100644 --- a/conversion/ultravox.py +++ b/conversion/ultravox.py @@ -6,6 +6,7 @@ from torch import Tensor from .base import MmprojModel, ModelBase, TextModel, gguf +from .llama import LlamaModel @ModelBase.register("UltravoxModel") @@ -208,3 +209,47 @@ def tensor_force_quant(self, name, new_name, bid, n_dims): # Was trained in BF16, being safe, avoiding quantizing to FP16 return gguf.GGMLQuantizationType.F32 return super().tensor_force_quant(name, new_name, bid, n_dims) + + +@ModelBase.register("VoxtralRealtimeForConditionalGeneration") +@ModelBase.example("mistralai/Voxtral-Mini-4B-Realtime-2602") +class VoxtralRealtimeEncoderModel(MmprojModel): + has_vision_encoder = False + has_audio_encoder = True + + def set_gguf_parameters(self): + super().set_gguf_parameters() + assert self.hparams_audio is not None + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.VOXTRAL_RT) + self.gguf_writer.add_audio_num_mel_bins(self.hparams_audio["num_mel_bins"]) + self.gguf_writer.add_audio_head_dim(self.hparams_audio["head_dim"]) + self.gguf_writer.add_audio_attention_layernorm_eps(self.hparams_audio.get("rms_norm_eps", 1e-5)) + self.gguf_writer.add_audio_window_size(self.hparams_audio["sliding_window"]) + self.gguf_writer.add_audio_stack_factor(self.global_config["downsample_factor"]) + + def tensor_force_quant(self, name, new_name, bid, n_dims): + if ".conv" in name and ".weight" in name: + return gguf.GGMLQuantizationType.F16 + return super().tensor_force_quant(name, new_name, bid, n_dims) + + @classmethod + def filter_tensors(cls, item: tuple[str, Callable[[], Tensor]]) -> tuple[str, Callable[[], Tensor]] | None: + name, gen = item + + # prevent clash naming with vision tensors + if name.startswith("multi_modal_projector"): + name = "audio." + name + + return super().filter_tensors((name, gen)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if "conv1.bias" in name or "conv2.bias" in name: + data_torch = data_torch.unsqueeze(-1) + + # HF stores q/k in rotate-half layout, the encoder uses interleaved (normal) RoPE + if ".self_attn.q_proj." in name or ".self_attn.k_proj." in name: + assert self.hparams_audio is not None + n_head = self.hparams_audio["num_attention_heads"] + data_torch = LlamaModel.permute(data_torch, n_head, n_head) + + yield from super().modify_tensors(data_torch, name, bid) diff --git a/convert_hf_to_gguf.py b/convert_hf_to_gguf.py index e09616b190cf..b863bccc5a24 100755 --- a/convert_hf_to_gguf.py +++ b/convert_hf_to_gguf.py @@ -58,7 +58,7 @@ def parse_args() -> argparse.Namespace: ) parser.add_argument( "--outtype", type=str, choices=["f32", "f16", "bf16", "q8_0", "tq1_0", "tq2_0", "auto"], default="auto", - help="output format - use f32 for float32, f16 for float16, bf16 for bfloat16, q8_0 for Q8_0, tq1_0 or tq2_0 for ternary, and auto for the highest-fidelity 16-bit float type", + help="output format - use f32 for float32, f16 for float16, bf16 for bfloat16, q8_0 for Q8_0, tq1_0 or tq2_0 for ternary, and auto to preserve supported FP8 weights and otherwise select the highest-fidelity 16-bit float type", ) parser.add_argument( "--bigendian", action="store_true", @@ -127,7 +127,7 @@ def parse_args() -> argparse.Namespace: ) parser.add_argument( "--dspark", action="store_true", - help="Export only the DeepSeek-V4 DSpark draft tensors as a separate GGUF.", + help="Export only the DeepSeek-V4 or Mistral Large 4 DSpark draft tensors as a separate GGUF.", ) parser.add_argument( "--mistral-format", action="store_true", @@ -255,6 +255,9 @@ def main() -> None: assert hparams.get("vision_encoder") is not None, "This model does not support multimodal" from conversion.pixtral import PixtralModel model_class = PixtralModel + elif hparams.get("moe") is not None and hparams.get("dsa") is not None: + from conversion.mistral4 import MistralLarge4Model + model_class = MistralLarge4Model elif hparams.get("moe") is not None: from conversion.mistral import MistralMoeModel model_class = MistralMoeModel @@ -267,11 +270,21 @@ def main() -> None: sys.exit(1) if args.dspark: - if is_mistral_format or model_architecture != "DeepseekV4ForCausalLM": - logger.error("--dspark is only supported for DeepseekV4ForCausalLM") + if is_mistral_format or model_architecture == "MistralLarge4ForConditionalGeneration": + if model_class.__name__ != "MistralLarge4Model": + logger.error("--dspark is only supported for Mistral Large 4 among Mistral-format models") + sys.exit(1) + from conversion.mistral4 import MistralLarge4DSparkModel + model_class = MistralLarge4DSparkModel + elif model_architecture not in ("DeepseekV4ForCausalLM", "DeepseekV41ForCausalLM"): + logger.error("--dspark is only supported for DeepseekV4ForCausalLM, DeepseekV41ForCausalLM and Mistral Large 4") sys.exit(1) - from conversion.deepseek import DeepseekV4DSparkModel - model_class = DeepseekV4DSparkModel + elif model_architecture == "DeepseekV41ForCausalLM": + from conversion.deepseek41 import DeepseekV41DSparkModel + model_class = DeepseekV41DSparkModel + else: + from conversion.deepseek import DeepseekV4DSparkModel + model_class = DeepseekV4DSparkModel if args.mtp or args.no_mtp: if not model_class.supports_mtp_export: diff --git a/convert_hf_to_gguf_update.py b/convert_hf_to_gguf_update.py index 0afbcc7e93a3..37df033ef3d6 100755 --- a/convert_hf_to_gguf_update.py +++ b/convert_hf_to_gguf_update.py @@ -101,6 +101,7 @@ class TOKENIZER_TYPE(IntEnum): {"name": "command-r", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/CohereForAI/c4ai-command-r-v01", }, {"name": "tiny_aya", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/CohereLabs/tiny-aya-base", }, {"name": "cohere2moe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/CohereLabs/North-Mini-Code-1.0", }, + {"name": "flint", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/RecursiveSI/flint", }, {"name": "qwen2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/Qwen/Qwen1.5-7B", }, {"name": "olmo", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/allenai/OLMo-1.7-7B-hf", }, {"name": "dbrx", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/databricks/dbrx-base", }, @@ -177,6 +178,7 @@ class TOKENIZER_TYPE(IntEnum): {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/zai-org/GLM-4.5-Air", "chkhsh": "9ca2dd618e8afaf09731a7cf6e2105b373ba6a1821559f258b272fe83e6eb902"}, {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/zai-org/GLM-4.7-Flash", "chkhsh": "cdf5f35325780597efd76153d4d1c16778f766173908894c04afc20108536267"}, {"name": "minerva-7b", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0", "chkhsh": "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35"}, + {"name": "domyn-small", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/domyn/Domyn-Small-v1.0", "chkhsh": "6e4d72c6e5260b90606e26a0931fa15e4b42ec6e97719d12919f2b1f93478262"}, {"name": "hunyuan", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-A13B-Instruct", "chkhsh": "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664"}, {"name": "hunyuan-dense", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-4B-Instruct", "chkhsh": "bba3b3366b646dbdded5dbc42d59598b849371afc42f7beafa914afaa5b70aa6"}, {"name": "hy_v4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hy4-preview", "chkhsh": "e6ddf9c6686791c12d698d34c31ab9be1fea9af5a3d9a6909783ab382198ae1c"}, @@ -189,6 +191,10 @@ class TOKENIZER_TYPE(IntEnum): {"name": "qwen2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/Qwen/Qwen3-Embedding-0.6B", "chkhsh": "d4540891389ea895b53b399da6ac824becc30f2fba0e9ddbb98f92e55ca0e97c"}, {"name": "qwen35", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/openbmb/MiniCPM-V-4_6", "chkhsh": "1444df51289cfa8063b96f0e62b1125440111bc79a52003ea14b6eac7016fd5f"}, {"name": "grok-2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/alvarobartt/grok-2-tokenizer", "chkhsh": "66b8d4e19ab16c3bfd89bce5d785fb7e0155e8648708a1f42077cb9fe002c273"}, + # muse-spark uses the l4_202k tokenizer, whose pre-tokenizer regex is gpt-4o's + {"name": "gpt-4o", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/meta-models/Muse-Spark-Open-816B-A42B", "chkhsh": "f5c965e4198da6e7525072d87d1ecf4c51d981fd486c7c4ec728ef9cec7e03fc"}, + # kolibri1 uses a 128k vocabulary with the qwen2 pre-tokenizer regex + {"name": "qwen2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/Aleph-Alpha/Kolibri-1", "chkhsh": "6e040dfe72e4b85855588c53acf4909ac4e98e55bc3a33cd7db499180dc42a78"}, # jina-v2-de variants {"name": "jina-v2-de", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/aari1995/German_Semantic_V3", "chkhsh": "b3d1dd861f1d4c5c0d2569ce36baf3f90fe8a102db3de50dd71ff860d91be3df"}, {"name": "gpt-2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/evilfreelancer/ruGPT3XL", "chkhsh": "0fe1cf6eda062318a1af7270f3331a85c539a01778ff948e24388e949c5282f4"}, diff --git a/docs/backend/CANN.md b/docs/backend/CANN.md index b0dbc9262226..b48e5a60dd00 100755 --- a/docs/backend/CANN.md +++ b/docs/backend/CANN.md @@ -161,7 +161,7 @@ lspci -n | grep -Eo '19e5:d[0-9a-f]{3}' | cut -d: -f2 | FP16 | Support | Support | | Q8_0 | Support | Partial | | Q4_0 | Support | Partial | -| BF16 | Support | | +| BF16 | Support | No | > **310P note** > - `Q8_0`: data transform / buffer path is implemented, and `GET_ROWS` is supported, but quantized `MUL_MAT` / `MUL_MAT_ID` are not supported. @@ -274,7 +274,9 @@ cmake --build build --config release **Notes**: - - CANN backend only supports FP16/Q4_0/Q8_0 models currently. + - On 910B the CANN backend supports FP16, BF16 and Q4_0/Q8_0 models. On 310P, BF16 is not + supported and quantized `MUL_MAT` / `MUL_MAT_ID` are not implemented, so only FP16 models + are supported (see [DataType Supports](#datatype-supports)). 2. **Launch inference** @@ -355,3 +357,7 @@ Enable ACL graph execution during the prefill stage, default is false. This opti ### GGML_CANN_OPERATOR_FUSION Enable operator fusion during computation, default is false. This option fuses compatible operators (e.g., ADD + RMS_NORM) to reduce overhead and improve performance. + +### GGML_CANN_NO_PINNED + +Disable pinned (host-locked) host buffers. When it is set (any value), `aclrtMallocHost` is not called: the CANN host buffer type allocates regular CPU memory instead and the backend reports no `host_buffer` capability, so host-side staging uses pageable memory. Use it when pinned host allocation fails, or when the pinned memory is needed by other processes on the host. diff --git a/docs/backend/OPENCL.md b/docs/backend/OPENCL.md index 337b0c82a0f9..acaaedfbfc40 100644 --- a/docs/backend/OPENCL.md +++ b/docs/backend/OPENCL.md @@ -72,6 +72,8 @@ However, A6x GPUs in phones are likely not supported due to the outdated driver | MXFP4 | Support | | IQ4_NL | Support | +`MUL_MAT_ID` accepts an expert id of `-1` and writes zeros to that slot. `ADD_ID` adds no bias for `-1`, including in fused MoE operations. + ## Model Preparation Since common quantizations are supported now, it is recommanded to download GGUF models directly from Huggingface. diff --git a/docs/backend/SYCL.md b/docs/backend/SYCL.md index 81d293e4febe..fb800025d2d3 100644 --- a/docs/backend/SYCL.md +++ b/docs/backend/SYCL.md @@ -783,7 +783,8 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | GGML_SYCL | ON (mandatory) | Enable build with SYCL code path. | | GGML_SYCL_TARGET | INTEL *(default)* | Set the SYCL target device type. | | GGML_SYCL_DEVICE_ARCH | Optional | Set the SYCL device architecture. Setting the device architecture can improve the performance. See the table [--offload-arch](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/OffloadDesign.md#--offload-arch) for a list of valid architectures. | -| GGML_SYCL_F16 | OFF *(default)* \|ON *(optional)* | Enable FP16 build with SYCL code path. (1.) | +| GGML_SYCL_F16 | OFF *(default)* \|ON *(optional)* | Enable FP16 build with SYCL code path. [1.](#sycl-f16-footnote) | +| GGML_SYCL_SUPPORT_XMX | ON *(default)* \|OFF *(Optional)* | Build the code paths that use XMX (DPAS) instructions. Set OFF for AOT builds targeting iGPUs without XMX, which otherwise fail to compile. | | GGML_SYCL_GRAPH | ON *(default)* \|OFF *(Optional)* | Enable build with [SYCL Graph extension](https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_oneapi_graph.asciidoc). | | GGML_SYCL_DNN | ON *(default)* \|OFF *(Optional)* | Enable build with oneDNN. | | GGML_SYCL_HOST_MEM_FALLBACK | ON *(default)* \|OFF *(Optional)* | Allow host memory fallback when device memory is full during quantized weight reorder. Enables inference to continue at reduced speed (reading over PCIe) instead of failing. Requires Linux kernel 6.8+. | @@ -791,7 +792,7 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | CMAKE_C_COMPILER | `icx` *(Linux)*, `icx/cl` *(Windows)* | Set `icx` compiler for SYCL code path. | | CMAKE_CXX_COMPILER | `icpx` *(Linux)*, `icx` *(Windows)* | Set `icpx/icx` compiler for SYCL code path. | -1. FP32 or FP16 have different performance impact to LLM. Recommended to test them for better prompt processing performance on your models. You need to rebuild the code after change `GGML_SYCL_F16=OFF/ON`. +1. <a id="sycl-f16-footnote"></a>FP32 or FP16 have different performance impact to LLM. Recommended to test them for better prompt processing performance on your models. You need to rebuild the code after change `GGML_SYCL_F16=OFF/ON`. ### Runtime @@ -802,7 +803,8 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | GGML_SYCL_DEV2DEV_MEMCPY | 0 (default), 1, 2 | Choose the method of dev2dev memory copy.<br>Value: <br>* 0: SYCL API (default), only support dGPUs.<br>* 1: L0 API -- Better performance, only support dGPUs, found to lead to abnormal crash in some case. <br>* 2: Host Forward -- Most stable method for all cases (including iGPU + dGPU*N), but with lower performance (-2% to -5%).<br>SYCL & L0 API are easy to be impacted by Intel GPU driver issue. When you meet the garbled output or crash issues in multiple GPUs case, try with this debug flag to work around or check the issue.| | GGML_SYCL_ENABLE_FLASH_ATTN | 1 (default) or 0| Enable Flash-Attention. It can reduce memory usage. The performance impact depends on the LLM.| | GGML_SYCL_ENABLE_OPT | 0 or 1 (default)| Enable optimize features for Intel GPUs. (Recommended to 0 for Intel devices older than Gen 10) | -| GGML_SYCL_ENABLE_GRAPH | 0 (default) or 1 | Enable running computations through SYCL Graphs feature. Disabled by default because SYCL Graph is still on development, no better performance. | +| GGML_SYCL_ENABLE_GRAPH | 0 (default) or 1 | Enable running computations through SYCL Graphs feature. Disabled by default because SYCL Graph is still in development, performance depends on model and device. [1.](#sycl-graph-footnote) | +| GGML_SYCL_GRAPH_EVICTION_TIMEOUT | 10 (default) or positive integer | Seconds a cached SYCL graph can go unused before it is evicted. Checked on a sweep that runs every half of this timeout. | | GGML_SYCL_ENABLE_HOST_PINNED_MEM | 0 or 1 (default) | Enable host pinned memory to speed up copy data from host to device. When disable it, host memory will common malloc() on CPU. Disable it when use `--load-model mlock`.| | GGML_SYCL_HOST_PINNED_MEM_2G | 0 (default) or 1 | Limit the max memory allocation to be no more than 2GB when enable host pinned memory. USM allocations above 2 GiB take the relaxed/large-allocation path, which serializes H2D copies with compute and prevents copy/compute overlap. It will impact the startup time. Need more test. Depend on `GGML_SYCL_ENABLE_HOST_PINNED_MEM=1`.| | GGML_SYCL_UPLOAD_STAGING_SLOTS | 4 (default) or non-negative integer | Number of 8 MiB pinned host slots used to stage tensor uploads (model loading), so the host copy of one slot overlaps the transfer of the previous one. Set to 0 to use the old path: a malloc'd bounce buffer and a blocking copy per tensor. | @@ -811,6 +813,7 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | GGML_SYCL_ENABLE_DNN | 0 or 1 (default)| Enable running computations through oneDNN and always use oneMKL. | | GGML_SYCL_FA_ONEDNN | 1 (default) or 0 | Enable the oneDNN fused SDPA (flash-attention) path on supported GPUs. Set to 0 to always use the native SYCL flash-attention kernel. | | GGML_SYCL_FA_ONEDNN_MAX_KV | 0 (default, disabled) or positive integer | By default (0), all sequences are handled by the oneDNN fused SDPA path, regardless of KV length; a positive value caps that length, past which sequences fall back to the native kernel. If GPU driver watchdog resets (DEVICE_LOST) occur during long-context inference, set this near the context depth where they start, e.g. 24576. | +| GGML_SYCL_FA_DPAS | 1 (default) or 0 | Enable the XMX flash-attention kernel for a q4_0 or q8_0 KV cache (`-ctk q4_0 -ctv q4_0` or `-ctk q8_0 -ctv q8_0`) on Xe2 or newer GPUs (Arc B-series, Lunar Lake, Panther Lake, Wildcat Lake). It reads the quantized cache directly for decode and batches of up to 31 tokens, head sizes 64, 96, 128, 256 and 512, up to 32 query heads per KV head. Set to 0 to use the native SYCL flash-attention kernels. | | GGML_SYCL_ENABLE_VMM | 0 or 1 (default) | Enable the virtual-memory device pool. | | GGML_SYCL_ENABLE_MKL_FA | 1 (default) or 0 | Enable oneMKL GEMM flash attention for XMX-accelerated prompt processing with quantized KV cache. Automatically activates during prefill (prompt processing) when all conditions are met: (1) flash-attn enabled (`-fa` or `--flash-attn on`), (2) KV cache quantized (`--cache-type-k q8_0 --cache-type-v q8_0` or other `*_0/*_1` types), (3) batch size ≥ 1024 (`--batch-size 1024`), (4) prompt length ≥ 1024 tokens. Set to 0 to force the TILE kernel for A/B testing. Example minimum command: `llama-cli -m model.gguf -fa -ngl 99 --cache-type-k q8_0 --cache-type-v q8_0 --batch-size 1024 -p "your prompt"` | | GGML_SYCL_MKL_FA_DEBUG | 0 (default) or 1 | Enable per-call diagnostic logging for MKL flash attention: GEMM/softmax timings, interleaved-head detection, and buffer memory usage. | @@ -819,6 +822,9 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | GGML_SYCL_MKL_FA_DIAG | 0 (default) or 1 | Enable output fingerprinting for MKL flash attention. Dumps the first 64 float output values for the first 6 FA calls with n_kv ≥ 1024, labeled with kernel type (MKL/TILE/VEC) for cross-kernel comparison. | | GGML_SYCL_ENABLE_FUSION | 0 or 1 (default) | Enable fused-kernel dispatch in graph compute. Unsupported types and layouts fall back to the standalone op kernels. See `ggml_sycl_can_fuse()`. | | GGML_SYCL_ENABLE_ESIMD | 0 or 1 (default)| Enable ESIMD kernels when available. | +| GGML_SYCL_ENABLE_XMX_ESIMD | 0 or 1 (default) | Use the XMX (DPAS) multi-column mat-vec kernels for reordered Q2_K to Q6_K and Q8_0 weights on Xe2 GPUs. Speeds up speculative decoding and short prompt batches. | +| GGML_SYCL_XMX_MAX_COLS | non-negative integer, 80 (default) | Most activation columns (batch size) the `GGML_SYCL_ENABLE_XMX_ESIMD` kernels take; wider batches use the other mat-mul kernels. A larger value keeps XMX for bigger batches (as repeated launches), `0` never uses it. | +| GGML_SYCL_XMX_GLU_MAX_COLS | 0 to 16, 16 (default) | Most columns the fused gate and up XMX kernel takes; wider batches run gate and up as separate mat-vecs. 16 is the most the kernel is built for, larger values are clamped to 16 and `0` turns the fused kernel off. | | GGML_SYCL_XMX_GATHER_TYPES | decimal bitmask, all bits set (default) | Weight formats that may use the XMX dequant-GEMM paths, which dequantize weights straight into the XMX tiles. This speeds up prompt processing of MoE models on GPUs with XMX units (Arc A- and B-series, Arc Pro, Data Center GPU Max), for example pp512 of Qwen3-30B-A3B UD-IQ3_XXS by about 50% on an Arc Pro B60. Bits:<br>* 1: IQ4_NL, 2: IQ3_S, 4: IQ4_XS, 8: IQ3_XXS, 16: IQ2_XXS, 32: IQ2_XS, 64: IQ2_S, 128: IQ1_S, 256: IQ1_M<br>* 512: Q8_0, 1024: Q4_K, 2048: Q5_K, 4096: Q6_K (MoE `MUL_MAT_ID` only)<br>Add values to combine them, for example `3` for IQ4_NL and IQ3_S; `0` disables the paths. A set bit does not force the path: batches of more than 64 tokens per expert or row lengths that are not a multiple of 256 (32 for IQ4_NL and Q8_0) use the library GEMM. | | GGML_SYCL_XMX_GATHER_SHAPES | decimal bitmask, 255 (default) | XMX `joint_matrix` combinations the paths of `GGML_SYCL_XMX_GATHER_TYPES` may use; the operand type comes from `GGML_SYCL_DYNAMIC_PRECISION` and the best supported combination is picked automatically (logged as `fg_pick_combo`). Bits:<br>* Xe2, Xe3, Xe-HPC: 1: f16 8x16x16, 2: f16 16x16x16, 4: f16 32x64x16, 8: f16 32x64x32, 32: tf32 8x16x8, 64: bf16 8x16x16<br>* Xe-HPG (Arc A770, ARL-H): 16: f16 8x8x16, 128: bf16 8x8x16<br>Clear a bit to exclude a combination, or set a single bit to force one for testing. | | GGML_SYCL_DYNAMIC_PRECISION | `F16` (default with `GGML_SYCL_F16=ON`), `BF16`, `TF32` or `F32` (default otherwise) | Operand type of the XMX dequant-GEMM paths (`GGML_SYCL_XMX_GATHER_TYPES`); accumulation is always f32. `F16` is the fastest, but activations above 65504 overflow. `BF16` keeps the f32 range at a 7-bit mantissa, `TF32` keeps the range and the f16 mantissa but is about 30% slower and needs Xe2, Xe3 or Xe-HPC, and `F32` turns the XMX paths off. Ops that request a higher src1 precision ([TAG_GGML_PREC]) get it regardless of this setting. | @@ -831,6 +837,29 @@ User can use the device management in [docs/multi-gpu.md](https://github.com/ggm | UR_L0_ENABLE_RELAXED_ALLOCATION_LIMITS | 0 (default) or 1 | Allow SYCL/Unified Runtime Level Zero device allocations larger than 4 GiB. llama.cpp's direct Level Zero allocation path requests the relaxed maximum-size limit itself when GGML_SYCL_ENABLE_LEVEL_ZERO=1. | | GGML_SYCL_USM_SYSTEM | 0 (default) or 1 | Enable experimental support for [USM system allocations](https://github.khronos.org/SYCL_Reference/iface/usm_basic_concept.html#system-allocations) for large GPU buffers. This requires enough host memory for model weights and caches, an Intel Xe2+ GPU such as BMG or newer and supported on Linux only, with CONFIG_DRM_XE_GPUSVM enabled. | +1. <a id="sycl-graph-footnote"></a>SYCL Graph support (`GGML_SYCL_ENABLE_GRAPH=1`) is limited to single-GPU workloads and may also depend on the model architecture and kernels in use. + Performance depends on how often a recorded graph can be reused, which will vary by workload. + For this reason, it is recommended to measure performance both with and without graphs enabled on your workloads. + + To check whether graphs are supported for your workload, enable INFO logging (`-lv 4`) and look for `enabling SYCL graphs` or `disabling SYCL graphs`. + Support may differ between prefill and decode, so check the status for the phases that matter to you. + DEBUG logging (`-lv 5`) reports why graphs are disabled. + + Then benchmark with your preferred tool, such as `llama-bench`. + For graph activity details (including reuse), set `GGML_SYCL_DEBUG=1` and look for `[SYCL-GRAPH]` messages. + +### Flash-attention kernels + +Attention dispatches on shape and hardware. + +DPAS is the quantized path. q4_0 or q8_0 KV cache, decode and batches up to 31 tokens, Xe2 and newer only. It issues dpas straight on the quantized blocks and never materialises an f16 copy. vISA gets used here because joint_matrix has no s4 type. + +oneDNN does XMX through SDPA but converts KV to f16 first, so it ends up on prefill: 32+ tokens and 1K+ keys. MKL is the prompt processing equivalent through oneMKL GEMM, also f16. + +VEC/TILE are plain kernels with no XMX in them. They run when DPAS is off or the hardware doesn't support it. + +joint_matrix belongs to the matmul GEMMs. Attention doesn't use it. + ## Compile-time Flags Pass these via `CXXFLAGS` or add a one-off `#define` to enable a flag on the spot. diff --git a/docs/backend/snapdragon/README.md b/docs/backend/snapdragon/README.md index b8347a224aec..ea4e3f386deb 100644 --- a/docs/backend/snapdragon/README.md +++ b/docs/backend/snapdragon/README.md @@ -6,8 +6,8 @@ The cross-compilation toolchain images are provided by the [Qualcomm Snapdragon Toolchain registry](https://github.com/snapdragon-toolchain). These Docker images include the Android NDK, OpenCL SDK, Hexagon SDK, CMake, and the necessary cross-compilers: -* **Android toolchain**: `ghcr.io/snapdragon-toolchain/arm64-android:v0.7` -* **Linux toolchain**: `ghcr.io/snapdragon-toolchain/arm64-linux:v0.7` +* **Android toolchain**: `ghcr.io/snapdragon-toolchain/arm64-android:v0.8` +* **Linux toolchain**: `ghcr.io/snapdragon-toolchain/arm64-linux:v0.8` The unified build utility (`scripts/snapdragon/build.py`) automatically pulls and orchestrates these containers to perform target compilation. @@ -40,7 +40,7 @@ Alternatively, you can build llama.cpp manually by entering the cross-compilatio ```bash # Start the cross-compilation container manually: -~/src/llama.cpp$ docker run -it --rm -u $(id -u):$(id -g) --volume $(pwd):/workspace --platform linux/amd64 ghcr.io/snapdragon-toolchain/arm64-android:v0.7 +~/src/llama.cpp$ docker run -it --rm -u $(id -u):$(id -g) --volume $(pwd):/workspace --platform linux/amd64 ghcr.io/snapdragon-toolchain/arm64-android:v0.8 # Inside the container, build the project using presets: [d]/workspace> cp docs/backend/snapdragon/CMakeUserPresets.json . @@ -53,7 +53,7 @@ Preset CMake variables: GGML_HEXAGON="ON" GGML_OPENCL="ON" GGML_OPENMP="OFF" - HEXAGON_SDK_ROOT="/opt/hexagon/6.6.0.0" + HEXAGON_SDK_ROOT="/opt/hexagon/6.7.0.0" ... -- Including OpenCL backend -- Including Hexagon backend @@ -324,6 +324,9 @@ on 4 physical NPUs, or `--devices 'HTP0[0-1:0],HTP1[0-1:1]'` on 2 physical NPUs - `GGML_HEXAGON_NHVX=0` Controls the number of HVX hardware threads to use. The default is all (actual number varies depending on the hardware version). +- `GGML_HEXAGON_VTCM_SIZE=0` + Overrides the VTCM size used by each session. Accepts `K`, `M` and `G` suffixes; a plain number is in MB. The default (0) uses the size the hardware reports. Values above the hardware size will fail to start the session. + - `GGML_HEXAGON_HOSTBUF=1` (default: 0, disabled) Enables allocating host buffers for debugging. By default, host buffers are disabled. diff --git a/docs/backend/snapdragon/developer.md b/docs/backend/snapdragon/developer.md index 3608250dc729..363be41ba9fb 100644 --- a/docs/backend/snapdragon/developer.md +++ b/docs/backend/snapdragon/developer.md @@ -48,6 +48,157 @@ Alternatively, users can partition and split the model across multiple virtual s tensor-splitting, or row-splitting modes. For user-facing execution modes and examples, see the [Snapdragon user guide](README.md#multi-device-execution-modes). +## Tiled Weight Formats + +Weight tensors in the Hexagon backend are repacked from flat row-major GGML layouts into 2D tiles in memory. +Tiling groups 2D matrix blocks contiguously: +- Eliminates strided row reads when fetching 2D tiles into VTCM via DMA. +- Matches native HVX vector width (128 bytes) and HMX systolic array dimensions (32x32). +- Repacking happens on the host during model load (`set_tensor()`) or via runtime repacking (`rt-repack`). +Implementation: [`htp-repack.cpp`](../../../ggml/src/ggml-hexagon/htp-repack.cpp). + +### Tile Dimensions and Grid Layout + +Each tile represents a submatrix of `N_rows = 32` rows and `K_cols` columns: +- Standard types (`Q4_0`, `Q4_1`, `Q8_0`, `IQ4_NL`, `MXFP4`, and K-quants): `K_cols = 32` (`HTP_TENSOR_TILE_N_COLS = 32`). +- `Q2_0`: `K_cols = 64` (`HTP_TENSOR_TILE_K_Q2_0 = 64`). +- `Q1_0`: `K_cols = 128` (`HTP_TENSOR_TILE_K_Q1_0 = 128`). + +For a weight matrix of logical shape `[ne0, ne1]` (where `ne0 = K`, `ne1 = N`): +- `n_k_tiles = ne0 / K_cols` +- `n_col_tiles = (ne1 + 31) / 32` +- Tile index for column-tile `kt` and row-tile `ct`: `tile_idx = ct * n_k_tiles + kt` +- Byte offset in matrix buffer: `tile_offset = tile_idx * tile_size` + +### Block-32 Quantized Formats + +Block-32 formats use a tile size of 32 rows x 32 columns (`K_cols = 32`): + +- **Q4_0** (576 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q4_0`): + - **Quants** (bytes 0..511, 512 bytes): + Contains 32 rows x 32 columns of 4-bit quants. + Divided into 16 column pairs `cp = 0..15` covering columns `2*cp` and `2*cp + 1`. + For each column pair `cp`, 32 bytes are stored consecutively for rows `row = 0..31`: + `tile[cp * 32 + row]` holds `(quant[row][2*cp + 1] << 4) | quant[row][2*cp]`. + Low nibble holds the even column; high nibble holds the odd column. + - **Scales** (bytes 512..575, 64 bytes): + 32 FP16 values (`ggml_half`), storing scale `d` for each row `row = 0..31`. + +- **Q8_0** (1088 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q8_0`): + - **Quants** (bytes 0..1023, 1024 bytes): + Contains 32 rows x 32 columns of signed 8-bit quants (`int8_t`). + Divided into 16 column pairs `cp = 0..15` covering columns `col0 = 2*cp` and `col1 = 2*cp + 1`. + For each column pair `cp`, 64 bytes store interleaved column elements for each row `row = 0..31`: + `tile[cp * 64 + 2 * row + 0] = quant[row][col0]` + `tile[cp * 64 + 2 * row + 1] = quant[row][col1]` + - **Scales** (bytes 1024..1087, 64 bytes): + 32 FP16 values (`ggml_half`), storing scale `d` for each row `row = 0..31`. + +- **IQ4_NL** (576 bytes per tile, `HTP_TENSOR_TILE_SIZE_IQ4_NL`): + - **Quants** (bytes 0..511, 512 bytes): + Same nibble transposition and storage layout as `Q4_0`. + Contains 32 rows x 32 columns of non-linear 4-bit indices (values 0..15). + Divided into 16 column pairs `cp = 0..15`: + `tile[cp * 32 + row]` holds `(quant[row][2*cp + 1] << 4) | quant[row][2*cp]`. + - **Scales** (bytes 512..575, 64 bytes): + 32 FP16 values (`ggml_half`), storing scale `d` for each row `row = 0..31`. + - **Dequantization**: + In HVX/HMX kernels, each 4-bit index is looked up in the 16-entry non-linear table (`iq4_nl_to_fp16_lut`) to produce an FP16 value, then multiplied by the row scale `d`. + +- **MXFP4** (544 bytes per tile, `HTP_TENSOR_TILE_SIZE_MXFP4`): + - **Quants** (bytes 0..511, 512 bytes): + Same nibble transposition and storage layout as `Q4_0`. + Contains 32 rows x 32 columns of 4-bit OCP Microscaling FP4 (E2M1) values. + Divided into 16 column pairs `cp = 0..15`: + `tile[cp * 32 + row]` holds `(quant[row][2*cp + 1] << 4) | quant[row][2*cp]`. + - **Scales** (bytes 512..543, 32 bytes): + 32 unsigned 8-bit values (`uint8_t`), storing one 8-bit biased exponent (E8M0, bias 127) scale `e` per row `row = 0..31`. + - **Dequantization**: + Kernel converts E8M0 bias to IEEE FP16 bias via `vh = clamp(e - 112, 0, 30) << 10` to form a power-of-two FP16 scale. + Each 4-bit FP4 nibble is unpacked via `mxfp4_to_fp16_lut` and multiplied by this scale. + +- **Q4_1** (640 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q4_1`): + - **Quants** (bytes 0..511, 512 bytes): + Same 4-bit nibble transposition and storage layout as `Q4_0`. + - **Scales** (bytes 512..639, 128 bytes): + 32 pairs of FP16 values (`ggml_half`): `scale[2 * row + 0] = d` (scale) and `scale[2 * row + 1] = m` (min) for each row `row = 0..31`. + +### Q1_0 Format (1-Bit Quantization) + +`Q1_0` packs 128 columns per tile (`K_cols = 128`, `HTP_TENSOR_TILE_K_Q1_0 = 128`): + +- **Tile Layout** (576 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q1_0`): + - **Quants** (bytes 0..511, 512 bytes): + Contains 32 rows x 128 columns of 1-bit quants (-1 or +1). + Divided into 4 quarters (`quarter = 0..3`), where each quarter covers 32 columns in K. + Each quarter occupies 128 bytes (1 HVX vector) in `vrmpy` byte order. + Within a quarter, columns `kq = 0..31` map into 8 groups `g = kq / 4` (0..7) of 4 consecutive columns: + `byte_offset = quarter * 128 + 4 * row + (kq % 4)` + `bit = g` (0..7) + - **Scales** (bytes 512..575, 64 bytes): + 32 FP16 values (`ggml_half`), storing scale `d` for each row `row = 0..31`. + One scale per row applies to all 128 columns (all 4 quarters) of the tile. + +- **HMX Mapping (1-to-4 Tile Expansion)**: + - HMX hardware operates strictly on 32x32 FP16 tiles (`HTP_TENSOR_TILE_N_ROWS = 32`, `HTP_TENSOR_TILE_N_COLS = 32`). + - During kernel execution, HVX dequantization (`dequantize_tiled_weight_to_fp16_task_q1_0`) expands each 32x128 Q1_0 tile (576 bytes) into 4 contiguous 32x32 FP16 HMX tiles (4 x 2048 bytes = 8192 bytes total) in VTCM. + - HMX systolic array processes the 4 resulting 32x32 FP16 tiles over 4 compute steps along K. + +### Q2_0 Format (2-Bit Quantization) + +`Q2_0` packs 64 columns per tile (`K_cols = 64`, `HTP_TENSOR_TILE_K_Q2_0 = 64`): + +- **Tile Layout** (576 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q2_0`): + - **Quants** (bytes 0..511, 512 bytes): + Contains 32 rows x 64 columns of 2-bit quants (codes 0..3 representing signed values -1..2). + Divided into 16 column groups `group = 0..15` of 4 columns each. + Stored in `vrmpy` byte order across 4 HVX vectors (vec 0..3): + Vector `group >> 2` (0..3) holds `group & 3` at bit offset `2 * (group & 3)`. + Byte `4 * row + byte` holds row `row = 0..31` and column byte `0..3`. + Vec 0..1 holds the first 32 columns (half 0), vec 2..3 holds the next 32 columns (half 1). + - **Scales** (bytes 512..575, 64 bytes): + 32 FP16 values (`ggml_half`), storing scale `d` for each row `row = 0..31` (at offset `512 + 2 * row`). + One scale per row applies to all 64 columns of the tile. + +- **HMX Mapping (1-to-2 Tile Expansion)**: + - HMX hardware operates strictly on 32x32 FP16 tiles (`HTP_TENSOR_TILE_N_ROWS = 32`, `HTP_TENSOR_TILE_N_COLS = 32`). + - During kernel execution, HVX dequantization (`dequantize_tiled_weight_to_fp16_task_q2_0`) expands each 32x64 Q2_0 tile (576 bytes) into 2 contiguous 32x32 FP16 HMX tiles (2 x 2048 bytes = 4096 bytes total) in VTCM. + - HMX systolic array processes the 2 resulting 32x32 FP16 tiles over 2 compute steps along K. + +- **HVX Vector Dot-Product**: + - `tiled_vec_dot_q2_0_32x1` and `tiled_vec_dot_q2_0_32x2` unpack 2-bit quants using `unpack_q3_k_low2`, subtract 1, and accumulate against Q8_0 activation tiles using `Q6_Vw_vrmpyacc_VwVbVb`. + +### K-Quants Formats + +In GGML, K-quants pack 256 elements per super-block. +On Hexagon, each 256-element super-block splits along K into 8 tiles of 32 columns (`K_cols = 32`). + +Byte ordering: `Q2_K`, `Q3_K`, and `Q6_K` use `vrmpy` byte order within each 128B HVX vector: +`k = 0..31` is split into 8 groups `g = k/4` of 4 `k` each; byte `4*r + (k%4)` holds row `r`. + +- **Q2_K** (336 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q2_K`, lossless tiling with same size as `block_q2_K`): + - `bytes 0..255` (vec 0..1): unsigned 2-bit quants; vec `m` holds groups `4m..4m+3` at bit offsets 0, 2, 4, 6. + - `bytes 256..319`: raw `scales[]` bytes (`min << 4 | sc`): `[0..31]` for k 0..15, `[32..63]` for k 16..31. + - `bytes 320..335`: 8 FP16 in tile `j` (0..7) of super-block: `d` (`j < 4`) or `-dmin` (`j >= 4`) for rows `8*(j%4)..8*(j%4)+7`. + +- **Q3_K** (512 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q3_K`): + - `bytes 0..255` (vec 0..1): low 2 bits; vec `m` holds groups `4m..4m+3` at bit offsets 0, 2, 4, 6. + - `bytes 256..383` (vec 2): sign mask, bit `g` set when `hmask` is 0 (quant = `low2 - 4`). + - `bytes 384..511` (vec 3): FP16 scales `d * (scales[] - 32)`: `fp16[0..31]` for k 0..15, `fp16[32..63]` for k 16..31. + +- **Q4_K** (640 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q4_K`, same layout as Q4_1 tile; each 256-k super-block splits into 8 tiles of 32 k): + - `bytes 0..511` (vec 0..3): 4-bit quants; byte `32*cp + r` holds `k = 2*cp` (low nibble) and `2*cp + 1` (high nibble). + - `bytes 512..639` (vec 4): 32x2 FP16 per row: `(d * sc, -dmin * m)`. + +- **Q5_K** (768 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q5_K`): + - `bytes 0..639` (vec 0..4): Q4_K tile (low 4 bits + FP16 scale/min pairs). + - `bytes 640..767` (vec 5): 5th-bit plane; byte `l` holds the 8 high bits for lane `l` across vec `i = 0..3` (`bit 2i = lo, 2i+1 = hi`). + +- **Q6_K** (896 bytes per tile, `HTP_TENSOR_TILE_SIZE_Q6_K`): + - `bytes 0..511` (vec 0..3): low 4 bits; vec `i` holds group `2i` (low nibble) and `2i+1` (high nibble). + - `bytes 512..767` (vec 4..5): high 2 bits; vec `4+m` holds groups `4m..4m+3` at bit offsets 0, 2, 4, 6. + - `bytes 768..895` (vec 6): FP16 scales `d * scales[]`: `fp16[0..31]` for k 0..15, `fp16[32..63]` for k 16..31. + ## Op and Kernel Development Guidelines Writing high-performance operators for Hexagon requires following specific guidelines. @@ -134,6 +285,18 @@ Writing high-performance operators for Hexagon requires following specific guide - **Distinction**: `octx->src[N]` pointers *can* be NULL by design and must be checked when optional. Examples include attention masks, optional bias or weights in fused kernels, and frequency factors. +### `supports_op` Independence from Buffer and Repack State + +- `supports_op` (and op-specific checkers such as `supported_mul_mat()`, `supported_get_rows()`) runs during GGML graph scheduling **before** buffers are allocated and before tensor data is populated. +- **Never check buffer usage or repacking state in `supports_op`**: + - `t->buffer` may be NULL or uninitialized. + - `t->data` may be NULL. + - `buffer->usage` is unknown at scheduling time. + - `is_tiled` or `extra->flags & GGML_HEXAGON_TENSOR_TILED` is not set yet. +- Operator support decisions must depend strictly on static tensor properties: operand types (`t->type`), shapes (`t->ne`), strides (`t->nb`), and operation parameters. +- Repacking (converting weights to tiled layout) is an internal optimization applied during `set_tensor()` or rt-repack. Non-weight tensors or test harness tensors with the same type remain in flat layout. +- Therefore, any supported type (such as BF16, F16, quantized types) must be supported both when repacked into tiles and when stored flat in memory. + ### Multiline Macro Formatting - Keep trailing backslashes in multiline `#define` macros cleanly aligned to a consistent column. @@ -190,7 +353,7 @@ sessions. Common partitioning logic is factored into reusable inline helpers in [`htp-tensor.h`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h): -1. [`htp_tensor_mdev_rows_per_chunk`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L71): +1. [`htp_tensor_mdev_rows_per_chunk`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L104): Determines the minimum number of rows per chunk so that the chunk byte size is a multiple of 128 bytes: ``` @@ -201,7 +364,7 @@ Common partitioning logic is factored into reusable inline helpers in Returns `false` if the tensor cannot be safely row-partitioned (such as unaligned base pointer, permuted layout, or non-128-byte aligned outer strides). -2. [`htp_tensor_mdev_partition`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L98): +2. [`htp_tensor_mdev_partition`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L131): Calculates the per-device work range `struct htp_tensor_mdev_range { uint32_t start; uint32_t count; }` given `total_units`, `units_per_chunk`, `mdev_idx`, `mdev_count`, and the precomputed `mdev_count_div`. Handles chunk distribution across devices, assigns remainder units to the last device, and automatically triggers @@ -240,11 +403,11 @@ if (nrows == 0) { For flat element-wise operations that write directly to DDR: - Partition total linear elements N = ne0 * ne1 * ne2 * ne3 in 128-byte cache line chunks (`elems_per_line = (elem_size == 4) ? 32 : 64`). - Requires strict 1D contiguity: - [`htp_tensor_is_contiguous(dst, elem_size)`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L32) + [`htp_tensor_is_contiguous(dst, elem_size)`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L65) and 128-byte aligned destination pointer - [`htp_tensor_mdev_data_aligned(dst)`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L51). + [`htp_tensor_mdev_data_aligned(dst)`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L84). - If contiguous and aligned, pass `elems_per_line` to - [`htp_tensor_mdev_partition`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L98); + [`htp_tensor_mdev_partition`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h#L131); otherwise pass 0 to trigger Device 0 fallback. ### Single-Device Fallback (Device 0) @@ -312,7 +475,7 @@ Multi-device execution synchronizes worker sessions through atomic fence slots a (Output Slice 0) (Output Slice 1) | | Tensor Cache Flush Tensor Cache Flush - (htp_tensor_flush_all) (htp_tensor_flush_all) + (htp_dcache_flush_dirty_tensors) (htp_dcache_flush_dirty_tensors) | | Post-Op/Batch Barrier ---------------------- Post-Op/Batch Barrier (htp_mdev_group_barrier) (htp_mdev_group_barrier) @@ -350,8 +513,8 @@ Multi-device execution synchronizes worker sessions through atomic fence slots a ### Tensor Cache Flush and Pipeline Completion - In the kernel, ensure all pushed DMA operations have been popped in strict FIFO order to drain the queue. -- Use [`htp_tensor_flush_all()`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h) to flush specific dirty tensors back to DDR: - - [`htp_tensor_flush_all()`](../../../ggml/src/ggml-hexagon/htp/htp-tensor.h) flushes modified tensor address ranges, or the +- Use [`htp_dcache_flush_dirty_tensors()`](../../../ggml/src/ggml-hexagon/htp/htp-dcache.h) to flush specific dirty tensors back to DDR: + - [`htp_dcache_flush_dirty_tensors()`](../../../ggml/src/ggml-hexagon/htp/htp-dcache.h) flushes modified tensor address ranges, or the full D-cache when their total size exceeds the flush threshold, ensuring peer devices and the host CPU observe consistent data in DDR. - Never signal completion before all DMA transfers are drained and dirty tensor flushes have completed. diff --git a/docs/backend/snapdragon/linux.md b/docs/backend/snapdragon/linux.md index d4ecd9b1b167..20cc4817a465 100644 --- a/docs/backend/snapdragon/linux.md +++ b/docs/backend/snapdragon/linux.md @@ -3,7 +3,7 @@ The cross-compilation is performed using the Snapdragon Linux Docker toolchain image (see [github.com/snapdragon-toolchain](https://github.com/snapdragon-toolchain)): -* **Linux toolchain**: `ghcr.io/snapdragon-toolchain/arm64-linux:v0.7` +* **Linux toolchain**: `ghcr.io/snapdragon-toolchain/arm64-linux:v0.8` The unified build utility (`scripts/snapdragon/build.py`) automatically pulls and orchestrates this container to perform target compilation. You only need to @@ -29,7 +29,7 @@ Alternatively, you can build llama.cpp manually by entering the cross-compilatio ```bash # Start the cross-compilation container manually: -~/src/llama.cpp$ docker run -it --rm -u $(id -u):$(id -g) --volume $(pwd):/workspace --platform linux/amd64 ghcr.io/snapdragon-toolchain/arm64-linux:v0.7 +~/src/llama.cpp$ docker run -it --rm -u $(id -u):$(id -g) --volume $(pwd):/workspace --platform linux/amd64 ghcr.io/snapdragon-toolchain/arm64-linux:v0.8 # Inside the container, build the project using presets: [d]/workspace> cp docs/backend/snapdragon/CMakeUserPresets.json . diff --git a/docs/backend/snapdragon/windows.md b/docs/backend/snapdragon/windows.md index 886cfda3f653..8e768491a5d4 100644 --- a/docs/backend/snapdragon/windows.md +++ b/docs/backend/snapdragon/windows.md @@ -8,7 +8,7 @@ Native Windows 11 arm64 builds have the following tool dependencies: - UCRT and Driver Kit - LLVM core libraries and Clang compiler (winget) - CMake, Git, Python (winget) -- Hexagon SDK Community Edition 6.6 or later (see below) +- Hexagon SDK Community Edition 6.7 or later (see below) - OpenCL SDK 2.3 or later (see below) Note: The rest of the **Windows** build process assumes that you're running natively in Powershell. @@ -54,15 +54,15 @@ c:\Qualcomm\OpenCL_SDK\2.3.2 Either use the trimmed down version (optimized for CI) from - https://github.com/snapdragon-toolchain/hexagon-sdk/releases/download/v6.6.0.0/hexagon-sdk-v6.6.0.0-arm64-wos.tar.xz + https://github.com/snapdragon-toolchain/hexagon-sdk/releases/download/v6.7.0.0/hexagon-sdk-v6.7.0.0-arm64-wos.tar.xz Or download the complete official version from - https://softwarecenter.qualcomm.com/catalog/item/Hexagon_SDK?version=6.6.0.0 + https://softwarecenter.qualcomm.com/catalog/item/Hexagon_SDK?version=6.7.0.0 Unzip/untar the archive into ``` -c:\Qualcomm\Hexagon_SDK\6.6.0.0 +c:\Qualcomm\Hexagon_SDK\6.7.0.0 ``` ## Install the latest Adreno GPU driver @@ -150,8 +150,8 @@ The overall Hexagon backend build procedure for Windows on Snapdragon is the sam However, additional settings are required for generating and signing HTP Ops libraries. ``` > $env:OPENCL_SDK_ROOT="C:\Qualcomm\OpenCL_SDK\2.3.2" -> $env:HEXAGON_SDK_ROOT="C:\Qualcomm\Hexagon_SDK\6.6.0.0" -> $env:HEXAGON_TOOLS_ROOT="C:\Qualcomm\Hexagon_SDK\6.6.0.0\tools\HEXAGON_Tools\19.0.07" +> $env:HEXAGON_SDK_ROOT="C:\Qualcomm\Hexagon_SDK\6.7.0.0" +> $env:HEXAGON_TOOLS_ROOT="C:\Qualcomm\Hexagon_SDK\6.7.0.0\tools\HEXAGON_Tools\21.0.04" > $env:HEXAGON_HTP_CERT="c:\Users\MyUsers\Certs\ggml-htp-v1.pfx" > $env:WINDOWS_SDK_BIN="C:\Program Files (x86)\Windows Kits\10\bin\10.0.26100.0" diff --git a/docs/backend/zDNN.md b/docs/backend/zDNN.md index 7c6d0751074e..f8218973916e 100644 --- a/docs/backend/zDNN.md +++ b/docs/backend/zDNN.md @@ -2,6 +2,7 @@ > [!WARNING] > **Note:** zDNN is **not** the same as ZenDNN. +> > - **zDNN** (this page): IBM's Deep Neural Network acceleration library for IBM Z & LinuxONE Mainframes > - **ZenDNN**: AMD's deep learning library for AMD EPYC CPUs ([see ZenDNN documentation](ZenDNN.md)) @@ -46,6 +47,14 @@ The IBM zDNN backend has the following CMake options that control the behaviour | --------------------- | ------------- | -------------------------------------------------------------------------------------- | | `GGML_ZDNN_HIGH_PREC` | `0` | Set to `1` to requantize Q8_0 weights in smaller groups, for lower loss at lower speed | +## Performance Tunables + +| Flag Option | Default Value | Description | +| ----------------------- | ------------- | ------------------------------------------------------ | +| `--flash-attn` or `-fa` | `auto` | Set to `on` to run attention on the NNPA (Recommended) | + +Note: Set `-fa on` explicitly. Flash Attention fuses each layer's attention (the KQ matrix multiplication, softmax and KQV matrix multiplication) into one `FLASH_ATTN_EXT` operation, which zDNN runs on the NNPA instead of the CPU. The speedup grows with the context length. With `auto`, llama.cpp currently turns Flash Attention off, because the operation runs on a different device than the layer. zDNN runs it when the KV cache is F16 (the default), the model uses no attention sinks, ALiBi or logit softcapping, and there is one KV cache stream (one sequence, or `--kv-unified`). Otherwise it falls back to the CPU. + ## 1. Install zDNN Library Note: A minimum of libzdnn 1.1.2 is required for the IBM zDNN backend to link correctly. diff --git a/docs/build-s390x.md b/docs/build-s390x.md index 005dd2983459..e587e356fa41 100644 --- a/docs/build-s390x.md +++ b/docs/build-s390x.md @@ -249,7 +249,7 @@ IBM VXE/VXE2 SIMD acceleration depends on the BLAS implementation. It is strongl | MXFP4 | ✅ | ❓ | ❓ | | Q5_0 | ✅ | ❓ | ❓ | | Q5_1 | ✅ | ❓ | ❓ | -| Q8_0 | ✅ | ❓ | ❓ | +| Q8_0 | ✅ | ✅ | ❓ | | Q2_K | 🚫 | ❓ | ❓ | | Q3_K | ✅ | ❓ | ❓ | | Q4_K | ✅ | ❓ | ❓ | @@ -266,11 +266,11 @@ IBM VXE/VXE2 SIMD acceleration depends on the BLAS implementation. It is strongl | IQ1_M | 🚫 | ❓ | ❓ | | IQ4_NL | ✅ | ❓ | ❓ | | IQ4_XS | ✅ | ❓ | ❓ | -| FP32->FP16 | 🚫 | ❓ | ❓ | +| FP32->FP16 | ✅ | ❓ | ❓ | | FP16->FP32 | 🚫 | ❓ | ❓ | - ✅ - acceleration available - 🚫 - acceleration unavailable, will still run using scalar implementation - ❓ - acceleration unknown, please contribute if you can test it yourself -Last Updated by **Aaron Teo (aaron.teo1@ibm.com)** on Sep 8, 2026. +Last Updated by **Aaron Teo (aaron.teo1@ibm.com)** on Nov 3, 2026. diff --git a/docs/build.md b/docs/build.md index 7286ec58dede..4e3bfe651b39 100644 --- a/docs/build.md +++ b/docs/build.md @@ -481,7 +481,7 @@ cmake --build build --config Release Now you can load the model in conversation mode using `Vulkan` ```sh -build/bin/Release/llama-cli -m "[PATH TO MODEL]" -ngl 100 -c 16384 -t 10 -n -2 -cnv +build/bin/Release/llama-cli -m "[PATH TO MODEL]" -ngl 100 -c 16384 -t 10 -n -2 ``` **MSYS2** @@ -852,6 +852,36 @@ WebGPU allows cross-platform access to the GPU from supported browsers. We utili Follow the instructions [here](https://dawn.googlesource.com/dawn/+/refs/heads/main/src/emdawnwebgpu/) to download or build the emdawnwebgpu package (Note that it might be safer to build the emdawnwebgpu package locally, so that it stays in sync with the version of Dawn you have installed above). When building using CMake, the path to the emdawnwebgpu port file needs to be set with the flag `EMDAWNWEBGPU_DIR`. +## WASI + +Requires [wasi-sdk](https://github.com/WebAssembly/wasi-sdk) 34+ with `WASI_SDK_PATH` set. Only the libraries build (`llama-common` does not support WASI yet), so link your program against them: + +```bash +FLAGS="-msimd128 -D_WASI_EMULATED_SIGNAL -fwasm-exceptions -mllvm -wasm-use-legacy-eh=false" +cmake -B build-wasi -DCMAKE_TOOLCHAIN_FILE=$WASI_SDK_PATH/share/cmake/wasi-sdk-p2.cmake \ + -DCMAKE_C_FLAGS="$FLAGS" -DCMAKE_CXX_FLAGS="$FLAGS" -DCMAKE_HAVE_LIBC_PTHREAD=1 \ + -DBUILD_SHARED_LIBS=OFF -DGGML_NATIVE=OFF -DGGML_OPENMP=OFF -DLLAMA_BUILD_COMMON=OFF +cmake --build build-wasi --target llama + +$WASI_SDK_PATH/bin/clang++ --target=wasm32-wasip3 -O3 $FLAGS -I include -I ggml/include examples/simple/simple.cpp \ + build-wasi/src/libllama.a build-wasi/ggml/src/libggml*.a -lunwind -ldl -Wl,-z,stack-size=8388608 -o llama-simple.wasm +wasmtime run -W exceptions=y --dir models llama-simple.wasm -m models/model.gguf "Hello" +``` + +### wasi:webgpu + +The WebGPU backend can target [wasi:webgpu](https://github.com/WebAssembly/wasi-webgpu) via [wasi-webgpu-headers](https://github.com/wasi-gfx/wasi-webgpu-headers) (with its submodule) and Dawn's `dawn-headers` release. Point `Dawn_DIR` at a directory containing this `DawnConfig.cmake` next to both: + +```cmake +set(_wasi_webgpu "${CMAKE_CURRENT_LIST_DIR}/wasi-webgpu-headers") +add_library(dawn::webgpu_dawn INTERFACE IMPORTED) +set_target_properties(dawn::webgpu_dawn PROPERTIES + INTERFACE_SOURCES "${_wasi_webgpu}/webgpu.c;${_wasi_webgpu}/async_futures.c;${_wasi_webgpu}/imports.c;${_wasi_webgpu}/imports_component_type.o" + INTERFACE_INCLUDE_DIRECTORIES "${CMAKE_CURRENT_LIST_DIR}/dawn-headers/include/webgpu_upstream;${_wasi_webgpu}") +``` + +Then build as above, but with `wasi-sdk-p3.cmake` / `--target=wasm32-wasip3`, `-DGGML_WEBGPU=ON -DDawn_DIR=...` at configure, and `build-wasi/ggml/src/ggml-webgpu/libggml-webgpu.a` added at link. See `.github/workflows/build-wasi.yml` for a more complete example. + ## IBM Z & LinuxONE To read documentation for how to build on IBM Z & LinuxONE, [click here](./build-s390x.md) diff --git a/docs/ops.md b/docs/ops.md index 581db6495718..2885441c5a37 100644 --- a/docs/ops.md +++ b/docs/ops.md @@ -14,22 +14,22 @@ Legend: | Operation | BLAS | CANN | CPU | CUDA | ET | HTP | MTL | OpenCL | SYCL | Vulkan | WebGPU | ZenDNN | zDNN | |-----------|------|------|------|------|------|------|------|------|------|------|------|------|------| -| ABS | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| ABS | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | ACC | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | ADD1 | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | | ADD_ID | ❌ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | ARANGE | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| ARGMAX | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| ARGMAX | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | ARGSORT | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | -| CEIL | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| CEIL | ❌ | ❌ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | CLAMP | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | COL2IM_1D | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | CONCAT | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ | | CONT | ❌ | 🟡 | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ | -| CONV_1D_DW | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | +| CONV_1D_DW | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | | CONV_2D | ❌ | ❌ | 🟡 | ✅ | ❌ | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ | -| CONV_2D_DW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| CONV_2D_DW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | CONV_3D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | CONV_TRANSPOSE_2D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | @@ -38,96 +38,97 @@ Legend: | CPY | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | | CROSS_ENTROPY_LOSS | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | CROSS_ENTROPY_LOSS_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| CUMSUM | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| DIAG | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| CUMSUM | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| DIAG | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | DIAG_MASK_INF | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ | -| DIV | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| DIV | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | DSV4_HC_COMB | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | | DSV4_HC_POST | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | | DSV4_HC_PRE | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | -| DUP | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ | -| ELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| EXP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| EXPM1 | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| FILL | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| DUP | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ | +| ELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| EXP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| EXPM1 | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| FILL | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | FLASH_ATTN_EXT | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | -| FLOOR | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| GATED_DELTA_NET | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | 🟡 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| FLOOR | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| GATED_DELTA_NET | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | GATED_LINEAR_ATTN | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | GELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | -| GELU_ERF | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| GELU_ERF | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | GELU_QUICK | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | GET_ROWS | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ❌ | ❌ | | GET_ROWS_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | | GROUP_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | -| HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| HARDSWISH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| HARDSWISH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | IM2COL | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| IM2COL_3D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| L2_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | 🟡 | ❌ | ❌ | +| IM2COL_3D | ❌ | ❌ | ✅ | ✅ | ❌ | 🟡 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | +| L2_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ | | LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | 🟡 | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| LIGHTNING_INDEXER | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | +| LIGHTNING_INDEXER | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | ❌ | | LOG | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | | MEAN | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ | ❌ | -| MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | -| MUL_MAT_HADAMARD | ❌ | ❌ | ✅ | ❌ | ✅ | 🟡 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | +| MUL_MAT_HADAMARD | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | 🟡 | | MUL_MAT_ID | ❌ | 🟡 | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | 🟡 | ❌ | -| MUL_MAT_ID_W4A4 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | -| MUL_MAT_ID_W4A8 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | -| MUL_MAT_W4A4 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | -| MUL_MAT_W4A8 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | -| NEG | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| MUL_MAT_ID_W4A4 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | ❌ | +| MUL_MAT_ID_W4A8 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | ❌ | +| MUL_MAT_W4A4 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | ❌ | +| MUL_MAT_W4A8 | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | ❌ | +| NEG | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | 🟡 | ❌ | ❌ | | OPT_STEP_ADAMW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | OPT_STEP_SGD | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | OUT_PROD | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | | PAD | ❌ | 🟡 | ✅ | 🟡 | ❌ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | | PAD_REFLECT_1D | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | -| POOL_1D | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| POOL_2D | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| POOL_1D | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | +| POOL_2D | ❌ | 🟡 | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | +| REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | RELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | REPEAT | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ | | REPEAT_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| RMS_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| RMS_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | RMS_NORM_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | ROLL | ❌ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | ROPE | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | ROPE_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| ROUND | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| ROUND | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | RWKV_WKV6 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | | RWKV_WKV7 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | -| SCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| SET | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | +| SCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| SET | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ❌ | ❌ | | SET_ROWS | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | -| SGN | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| SGN | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | SIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | SILU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | SILU_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | | SIN | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| SOFTPLUS | ❌ | ❌ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| SOFTPLUS | ❌ | ❌ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | SOFT_MAX | ❌ | 🟡 | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | SOFT_MAX_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ | -| SOLVE_TRI | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | +| SOLVE_TRI | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ❌ | ❌ | | SQR | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | SQRT | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | SSM_CONV | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| SSM_SCAN | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ❌ | 🟡 | 🟡 | ✅ | ❌ | ❌ | -| STEP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| SSM_SCAN | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ❌ | ❌ | +| STEP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | SUM | ❌ | 🟡 | ✅ | 🟡 | ❌ | 🟡 | 🟡 | ❌ | 🟡 | 🟡 | 🟡 | ❌ | ❌ | | SUM_ROWS | ❌ | ✅ | ✅ | 🟡 | ❌ | 🟡 | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | -| SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| SWIGLU_CLAMP | ❌ | ❌ | ✅ | ❌ | ❌ | 🟡 | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | +| SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | +| SWIGLU_CLAMP | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | | SWIGLU_OAI | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | -| TANH | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| TANH | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | -| TOP_K | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ✅ | 🟡 | ✅ | ❌ | ❌ | -| TRI | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | -| TRUNC | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | +| TOP_K | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ | +| TOP_K_MASK | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| TRI | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | +| TRUNC | ❌ | ❌ | ✅ | 🟡 | 🟡 | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | UPSCALE | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ | | XIELU | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | diff --git a/docs/ops/Hexagon.csv b/docs/ops/Hexagon.csv index b93d02bd9a29..c9608b715dd7 100644 --- a/docs/ops/Hexagon.csv +++ b/docs/ops/Hexagon.csv @@ -35,8 +35,8 @@ "HTP0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","CEIL","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","HTP" +"HTP0","CEIL","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","HTP" "HTP0","ROUND","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" "HTP0","ROUND","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" "HTP0","TRUNC","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" @@ -77,8 +77,8 @@ "HTP0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","CEIL","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","HTP" +"HTP0","CEIL","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","HTP" "HTP0","ROUND","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" "HTP0","ROUND","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" "HTP0","TRUNC","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" @@ -115,12 +115,12 @@ "HTP0","EXPM1","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","HTP" "HTP0","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","HTP" "HTP0","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","HTP" -"HTP0","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","HTP" -"HTP0","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","HTP" +"HTP0","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","HTP" "HTP0","FLOOR","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","HTP" "HTP0","FLOOR","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","CEIL","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","HTP" +"HTP0","CEIL","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","HTP" "HTP0","ROUND","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","HTP" "HTP0","ROUND","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","HTP" "HTP0","TRUNC","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","HTP" @@ -157,16 +157,100 @@ "HTP0","EXPM1","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" "HTP0","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","HTP" "HTP0","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","HTP" -"HTP0","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","HTP" -"HTP0","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","HTP" +"HTP0","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","HTP" "HTP0","FLOOR","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","HTP" "HTP0","FLOOR","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","CEIL","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","HTP" +"HTP0","CEIL","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","HTP" "HTP0","ROUND","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","HTP" "HTP0","ROUND","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" "HTP0","TRUNC","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","HTP" "HTP0","TRUNC","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","ABS","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","ABS","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","SGN","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","SGN","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","NEG","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","NEG","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","STEP","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","STEP","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","TANH","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","TANH","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","ELU","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","ELU","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","RELU","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","RELU","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","SIGMOID","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","SIGMOID","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","GELU","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","GELU","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","GELU_QUICK","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","GELU_QUICK","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","SILU","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","SILU","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","HARDSWISH","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","HARDSWISH","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","HARDSIGMOID","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","HARDSIGMOID","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","EXP","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","EXP","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","EXPM1","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","EXPM1","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","SOFTPLUS","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","SOFTPLUS","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","GELU_ERF","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","GELU_ERF","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","FLOOR","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","FLOOR","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","CEIL","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","CEIL","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","ROUND","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","ROUND","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","TRUNC","type=bf16,ne_a=[128,2,2,2],v=0","support","0","no","HTP" +"HTP0","TRUNC","type=bf16,ne_a=[5,7,11,13],v=0","support","0","no","HTP" +"HTP0","ABS","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","ABS","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","SGN","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","SGN","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","NEG","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","NEG","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","STEP","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","STEP","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","TANH","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","TANH","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","ELU","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","ELU","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","RELU","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","RELU","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","SIGMOID","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","SIGMOID","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","GELU","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","GELU","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","GELU_QUICK","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","GELU_QUICK","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","SILU","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","SILU","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","HARDSWISH","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","HARDSWISH","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","HARDSIGMOID","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","HARDSIGMOID","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","EXP","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","EXP","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","EXPM1","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","EXPM1","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","SOFTPLUS","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","SOFTPLUS","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","GELU_ERF","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","GELU_ERF","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","FLOOR","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","FLOOR","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","CEIL","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","CEIL","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","ROUND","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","ROUND","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" +"HTP0","TRUNC","type=bf16,ne_a=[128,2,2,2],v=1","support","0","no","HTP" +"HTP0","TRUNC","type=bf16,ne_a=[5,7,11,13],v=1","support","0","no","HTP" "HTP0","DSV4_HC_COMB","n_tokens=1,n_iter=1,eps=0.000001","support","0","no","HTP" "HTP0","DSV4_HC_COMB","n_tokens=17,n_iter=4,eps=0.000001","support","0","no","HTP" "HTP0","DSV4_HC_COMB","n_tokens=257,n_iter=8,eps=0.000001","support","0","no","HTP" @@ -196,30 +280,30 @@ "HTP0","DSV4_HC_PRE","n_embd=128,n_hc=8,n_tokens=17,gated=1","support","0","no","HTP" "HTP0","DSV4_HC_PRE","n_embd=128,n_hc=65,n_tokens=17,gated=0","support","0","no","HTP" "HTP0","DSV4_HC_PRE","n_embd=128,n_hc=65,n_tokens=17,gated=1","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=1,n_tokens=1,identity=0","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=0","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=128,n_tokens=257,identity=0","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=0","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=1","support","0","no","HTP" -"HTP0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=1","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=1,n_tokens=1,identity=0,gated=0","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=0,gated=0","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=128,n_tokens=257,identity=0,gated=0","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=0,gated=0","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=1,gated=0","support","0","no","HTP" +"HTP0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=1,gated=0","support","0","no","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" @@ -232,24 +316,24 @@ "HTP0","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" "HTP0","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" "HTP0","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" -"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" -"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" -"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" +"HTP0","REGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" +"HTP0","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" +"HTP0","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" "HTP0","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" @@ -262,12 +346,12 @@ "HTP0","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" "HTP0","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" "HTP0","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" @@ -280,24 +364,24 @@ "HTP0","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" "HTP0","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" "HTP0","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","yes","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" -"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" +"HTP0","REGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" "HTP0","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" @@ -310,18 +394,78 @@ "HTP0","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" "HTP0","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" "HTP0","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,split","support","0","no","HTP" -"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,split","support","0","no","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" +"HTP0","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","yes","HTP" "HTP0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","yes","HTP" +"HTP0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" +"HTP0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" +"HTP0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" +"HTP0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" +"HTP0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" +"HTP0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" +"HTP0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","0","no","HTP" +"HTP0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","0","no","HTP" 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+"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=1,d2=3,v=0","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=1,d2=3,v=1","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=1,d2=3,v=0","support","1","yes","HTP" "HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=1,d2=3,v=1","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=0","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=1","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=0","support","0","no","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=0","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=1","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=0","support","1","yes","HTP" "HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=1,v=1","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=0","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=1","support","0","no","HTP" -"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=0","support","0","no","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=0","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=1","support","1","yes","HTP" +"HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=0","support","1","yes","HTP" "HTP0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=1","support","0","no","HTP" "HTP0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0,kernel_offset=0","support","0","no","HTP" "HTP0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1,kernel_offset=0","support","0","no","HTP" @@ -6996,6 +7185,15 @@ "HTP0","CONV_2D","ne_input=[19,17,16,3],ne_kernel=[3,3,16,33],type_kernel=f16,stride0=2,stride1=3,padding0=4,padding1=2,dilation0=2,dilation1=1,cwhn=0,kernel_offset=0","support","0","no","HTP" "HTP0","CONV_2D","ne_input=[13,11,16,3],ne_kernel=[1,1,16,33],type_kernel=f16,stride0=1,stride1=1,padding0=0,padding1=0,dilation0=1,dilation1=1,cwhn=0,kernel_offset=0","support","0","no","HTP" "HTP0","CONV_2D","ne_input=[19,17,8,2],ne_kernel=[3,3,8,17],type_kernel=f16,stride0=1,stride1=1,padding0=1,padding1=1,dilation0=1,dilation1=1,cwhn=0,kernel_offset=1","support","0","no","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[3,1,16,1],type_kernel=f32,stride=1,padding=0,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[7,1,16,1],type_kernel=f32,stride=1,padding=3,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[97,33,1,1],ne_kernel=[5,1,33,1],type_kernel=f32,stride=2,padding=2,dilation=2","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[3,1,16,1],type_kernel=f16,stride=1,padding=0,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[7,1,16,1],type_kernel=f16,stride=1,padding=3,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[97,33,1,1],ne_kernel=[5,1,33,1],type_kernel=f16,stride=2,padding=2,dilation=2","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[3,1,16,1],type_kernel=bf16,stride=1,padding=0,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[7,1,16,1],type_kernel=bf16,stride=1,padding=3,dilation=1","support","1","yes","HTP" +"HTP0","CONV_1D_DW","ne_input=[97,33,1,1],ne_kernel=[5,1,33,1],type_kernel=bf16,stride=2,padding=2,dilation=2","support","1","yes","HTP" "HTP0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],type_kernel=f32,stride=1,padding=0,dilation=1,cwhn=0","support","0","no","HTP" "HTP0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],type_kernel=f32,stride=1,padding=0,dilation=1,cwhn=1","support","0","no","HTP" "HTP0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],type_kernel=f32,stride=2,padding=1,dilation=1,cwhn=0","support","0","no","HTP" @@ -7474,14 +7672,14 @@ "HTP0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","0","no","HTP" "HTP0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","0","no","HTP" "HTP0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","no","HTP" -"HTP0","DUP","type=f32,ne=[10,10,20,1]","support","0","no","HTP" -"HTP0","DUP","type=f16,ne=[10,10,20,1]","support","0","no","HTP" -"HTP0","DUP","type=i32,ne=[10,10,20,1]","support","0","no","HTP" +"HTP0","DUP","type=f32,ne=[10,10,20,1]","support","1","yes","HTP" +"HTP0","DUP","type=f16,ne=[10,10,20,1]","support","1","yes","HTP" +"HTP0","DUP","type=i32,ne=[10,10,20,1]","support","1","yes","HTP" "HTP0","DUP","type=i16,ne=[10,10,20,1]","support","0","no","HTP" -"HTP0","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","no","HTP" -"HTP0","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","no","HTP" -"HTP0","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","no","HTP" -"HTP0","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","no","HTP" +"HTP0","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","yes","HTP" +"HTP0","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","yes","HTP" +"HTP0","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","yes","HTP" +"HTP0","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","yes","HTP" "HTP0","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","no","HTP" "HTP0","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","no","HTP" "HTP0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1,inplace=0","support","0","no","HTP" @@ -7989,13 +8187,15 @@ "HTP0","CPY","type_src=f16,type_dst=f16,ne_src=[256,4,1,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=1","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[256,4,1,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=1","support","1","yes","HTP" "HTP0","CPY","type_src=bf16,type_dst=bf16,ne_src=[256,4,1,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=1","support","0","no","HTP" -"HTP0","CPY","type_src=i32,type_dst=i32,ne_src=[256,4,1,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=1","support","0","no","HTP" -"HTP0","CPY","type_src=i32,type_dst=i32,ne_src=[256,1,4,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0","support","0","no","HTP" +"HTP0","CPY","type_src=i32,type_dst=i32,ne_src=[256,4,1,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=1","support","1","yes","HTP" +"HTP0","CPY","type_src=i32,type_dst=i32,ne_src=[256,1,4,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[256,1,4,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[2,2097121,1,1],permute_src=[1,0,2,3],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[2,2,524281,1],permute_src=[1,0,2,3],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[128,2,3,1],ne_dst=[128,2,3,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[128,4,3,1]","support","1","yes","HTP" "HTP0","CPY","type_src=f16,type_dst=f16,ne_src=[128,2,3,1],ne_dst=[128,2,3,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[128,4,3,1]","support","1","yes","HTP" +"HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[64,16,1,1],ne_dst=[1,64,16,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[32,64,16,1]","support","1","yes","HTP" +"HTP0","CPY","type_src=f16,type_dst=f16,ne_src=[64,16,1,1],ne_dst=[1,64,16,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[32,64,16,1]","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,7,32],ne_dst=[32,7,5,3],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,32,7],ne_dst=[3,5,7,32],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" "HTP0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,32,7],ne_dst=[32,7,5,3],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","HTP" @@ -8540,10 +8740,212 @@ "HTP0","SUB","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","HTP" "HTP0","MUL","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","HTP" "HTP0","DIV","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","HTP" +"HTP0","ADD","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" 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+"HTP0","DIV","type=bf16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","HTP" +"HTP0","ADD","type=f32,ne=[1,2,2,2],nr=[17,1,1,1],nf=1,perm1=0,src_overlap=0,weights=1","support","1","yes","HTP" +"HTP0","MUL","type=f32,ne=[1,2,2,2],nr=[17,1,1,1],nf=1,perm1=0,src_overlap=0,weights=1","support","1","yes","HTP" +"HTP0","ADD","type=f32,ne=[2,2,2,2],nr=[17,1,1,1],nf=1,perm1=0,src_overlap=0,weights=1","support","1","yes","HTP" +"HTP0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","ADD","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","SUB","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","MUL","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" +"HTP0","DIV","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","0","no","HTP" "HTP0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000,inplace=0","support","1","yes","HTP" "HTP0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","1","yes","HTP" "HTP0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=1","support","1","yes","HTP" "HTP0","SCALE","type=f32,ne=[100,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","1","yes","HTP" +"HTP0","SCALE","type=bf16,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","0","no","HTP" +"HTP0","SCALE","type=bf16,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=1","support","0","no","HTP" +"HTP0","SCALE","type=bf16,ne=[100,10,10,10],scale=0.500000,bias=0.000000,inplace=0","support","0","no","HTP" "HTP0","SILU_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","no","HTP" "HTP0","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000,noncontig_rows=0","support","1","yes","HTP" "HTP0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000,inplace=0","support","1","yes","HTP" @@ -8696,6 +9098,10 @@ "HTP0","NORM","type=f32,ne=[260,5,4,3],v=1,eps=10.000000,noncontig_rows=0","support","1","yes","HTP" "HTP0","RMS_NORM","type=f32,ne=[260,5,4,3],v=1,eps=10.000000,inplace=0","support","1","yes","HTP" "HTP0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001,inplace=1","support","1","yes","HTP" +"HTP0","NORM","type=f32,ne=[4,1,65536,1],v=0,eps=0.000001,noncontig_rows=0","support","1","yes","HTP" +"HTP0","RMS_NORM","type=f32,ne=[4,1,65536,1],v=0,eps=0.000001,inplace=0","support","1","yes","HTP" +"HTP0","RMS_NORM","type=f32,ne=[4,1,1,65536],v=0,eps=0.000001,inplace=0","support","1","yes","HTP" +"HTP0","L2_NORM","type=f32,ne=[4,1,65536,1],eps=0.000000,v=0,noncontig_rows=0","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[3,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[6,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[3,1024,4,1],ne_b=[3,1024,1,1]","support","1","yes","HTP" @@ -8726,6 +9132,21 @@ "HTP0","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[67,2048,1,1],ne_b=[4,2048,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[67,2048,4,1],ne_b=[4,2048,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,1024,1,1],ne_b=[7,1024,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[14,1024,1,1],ne_b=[7,1024,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,1024,4,1],ne_b=[7,1024,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,1024,1,1],ne_b=[7,1024,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,1024,4,1],ne_b=[7,1024,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,1536,1,1],ne_b=[7,1536,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[14,1536,1,1],ne_b=[7,1536,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,1536,4,1],ne_b=[7,1536,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,1536,1,1],ne_b=[7,1536,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,1536,4,1],ne_b=[7,1536,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,2048,1,1],ne_b=[7,2048,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[14,2048,1,1],ne_b=[7,2048,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[7,2048,4,1],ne_b=[7,2048,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,2048,1,1],ne_b=[7,2048,1,1]","support","1","yes","HTP" +"HTP0","SSM_CONV","type=f32,ne_a=[70,2048,4,1],ne_b=[7,2048,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[9,1024,1,1],ne_b=[9,1024,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[18,1024,1,1],ne_b=[9,1024,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[9,1024,4,1],ne_b=[9,1024,1,1]","support","1","yes","HTP" @@ -8742,6 +9163,8 @@ "HTP0","SSM_CONV","type=f32,ne_a=[72,2048,1,1],ne_b=[9,2048,1,1]","support","1","yes","HTP" "HTP0","SSM_CONV","type=f32,ne_a=[72,2048,4,1],ne_b=[9,2048,1,1]","support","1","yes","HTP" "HTP0","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","0","no","HTP" +"HTP0","SSM_SCAN","type=f32,d_state=96,head_dim=64,n_head=128,n_group=8,n_seq_tokens=1,n_seqs=1,xbc_overlap=0,K=1,weak_decay=0","support","0","no","HTP" +"HTP0","SSM_SCAN","type=f32,d_state=96,head_dim=64,n_head=16,n_group=8,n_seq_tokens=300,n_seqs=2,xbc_overlap=0,K=1,weak_decay=1","support","0","no","HTP" "HTP0","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","0","no","HTP" "HTP0","SSM_SCAN","type=f32,d_state=256,head_dim=64,n_head=8,n_group=2,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","0","no","HTP" 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+"HTP0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" +"HTP0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=1","support","1","yes","HTP" "HTP0","LEAKY_RELU","type=f16,ne_a=[10,5,4,3],negative_slope=0.100000","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne=[10,2,2,2]","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne=[10,2,2,2]","support","0","no","HTP" +"HTP0","CEIL","type=f16,ne=[10,2,2,2]","support","1","yes","HTP" "HTP0","ROUND","type=f16,ne=[10,2,2,2]","support","0","no","HTP" "HTP0","TRUNC","type=f16,ne=[10,2,2,2]","support","0","no","HTP" "HTP0","SQR","type=f16,ne=[7,1,5,3]","support","1","yes","HTP" @@ -12903,14 +14518,14 @@ "HTP0","SIN","type=f16,ne=[1024,1024,1,1]","support","0","no","HTP" "HTP0","COS","type=f16,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","COS","type=f16,ne=[1024,1024,1,1]","support","0","no","HTP" -"HTP0","CLAMP","type=f16,ne=[7,1,5,3],min=-0.500000,max=0.500000","support","1","yes","HTP" -"HTP0","CLAMP","type=f16,ne=[1024,1024,1,1],min=-0.500000,max=0.500000","support","1","yes","HTP" +"HTP0","CLAMP","type=f16,ne=[7,1,5,3],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" +"HTP0","CLAMP","type=f16,ne=[1024,1024,1,1],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" "HTP0","LEAKY_RELU","type=f16,ne_a=[7,1,5,3],negative_slope=0.100000","support","0","no","HTP" "HTP0","LEAKY_RELU","type=f16,ne_a=[1024,1024,1,1],negative_slope=0.100000","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","FLOOR","type=f16,ne=[1024,1024,1,1]","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne=[7,1,5,3]","support","0","no","HTP" -"HTP0","CEIL","type=f16,ne=[1024,1024,1,1]","support","0","no","HTP" +"HTP0","CEIL","type=f16,ne=[7,1,5,3]","support","1","yes","HTP" +"HTP0","CEIL","type=f16,ne=[1024,1024,1,1]","support","1","yes","HTP" "HTP0","ROUND","type=f16,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","ROUND","type=f16,ne=[1024,1024,1,1]","support","0","no","HTP" "HTP0","TRUNC","type=f16,ne=[7,1,5,3]","support","0","no","HTP" @@ -12920,10 +14535,11 @@ "HTP0","LOG","type=f32,ne=[10,5,4,3]","support","1","yes","HTP" "HTP0","SIN","type=f32,ne=[10,2,2,2]","support","0","no","HTP" "HTP0","COS","type=f32,ne=[10,2,2,2]","support","0","no","HTP" -"HTP0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","yes","HTP" +"HTP0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" +"HTP0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=1","support","1","yes","HTP" "HTP0","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","yes","HTP" "HTP0","FLOOR","type=f32,ne=[10,2,2,2]","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne=[10,2,2,2]","support","0","no","HTP" +"HTP0","CEIL","type=f32,ne=[10,2,2,2]","support","1","yes","HTP" "HTP0","ROUND","type=f32,ne=[10,2,2,2]","support","0","no","HTP" "HTP0","TRUNC","type=f32,ne=[10,2,2,2]","support","0","no","HTP" "HTP0","SQR","type=f32,ne=[7,1,5,3]","support","1","yes","HTP" @@ -12936,14 +14552,14 @@ "HTP0","SIN","type=f32,ne=[1024,1024,1,1]","support","0","no","HTP" "HTP0","COS","type=f32,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","COS","type=f32,ne=[1024,1024,1,1]","support","0","no","HTP" -"HTP0","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000","support","1","yes","HTP" -"HTP0","CLAMP","type=f32,ne=[1024,1024,1,1],min=-0.500000,max=0.500000","support","1","yes","HTP" +"HTP0","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" +"HTP0","CLAMP","type=f32,ne=[1024,1024,1,1],min=-0.500000,max=0.500000,v=0","support","1","yes","HTP" "HTP0","LEAKY_RELU","type=f32,ne_a=[7,1,5,3],negative_slope=0.100000","support","1","yes","HTP" "HTP0","LEAKY_RELU","type=f32,ne_a=[1024,1024,1,1],negative_slope=0.100000","support","1","yes","HTP" "HTP0","FLOOR","type=f32,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","FLOOR","type=f32,ne=[1024,1024,1,1]","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne=[7,1,5,3]","support","0","no","HTP" -"HTP0","CEIL","type=f32,ne=[1024,1024,1,1]","support","0","no","HTP" +"HTP0","CEIL","type=f32,ne=[7,1,5,3]","support","1","yes","HTP" +"HTP0","CEIL","type=f32,ne=[1024,1024,1,1]","support","1","yes","HTP" "HTP0","ROUND","type=f32,ne=[7,1,5,3]","support","0","no","HTP" "HTP0","ROUND","type=f32,ne=[1024,1024,1,1]","support","0","no","HTP" "HTP0","TRUNC","type=f32,ne=[7,1,5,3]","support","0","no","HTP" @@ -14279,6 +15895,12 @@ "HTP0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=1,v=12","support","0","no","HTP" "HTP0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=2,v=12","support","0","no","HTP" "HTP0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=3,v=12","support","0","no","HTP" +"HTP0","CONCAT","type=f32,ne_a=[98304,8,1,1],ne_b_d=288,dim=0,v=0","support","1","yes","HTP" +"HTP0","CONCAT","type=f32,ne_a=[20000,3,2,1],ne_b_d=333,dim=0,v=1","support","1","yes","HTP" +"HTP0","CONCAT","type=q8_0,ne_a=[8192,2,1,1],ne_b_d=4096,dim=0,v=0","support","0","no","HTP" +"HTP0","CONCAT","type=f32,ne_a=[98304,8,1,1],ne_b_d=2,dim=1,v=0","support","1","yes","HTP" +"HTP0","CONCAT","type=f32,ne_a=[20000,3,2,1],ne_b_d=1,dim=1,v=1","support","1","yes","HTP" +"HTP0","CONCAT","type=q8_0,ne_a=[8192,2,1,1],ne_b_d=1,dim=1,v=0","support","0","no","HTP" "HTP0","ARGSORT","type=f32,ne=[3,1,1,1],order=0","support","1","yes","HTP" "HTP0","ARGSORT","type=f32,ne=[4,1,1,1],order=0","support","1","yes","HTP" "HTP0","ARGSORT","type=f32,ne=[7,1,1,1],order=0","support","1","yes","HTP" @@ -14736,6 +16358,8 @@ "HTP0","TOP_K","type=f32,ne=[8192,2,1,1],k=2051,ties=0","support","1","yes","HTP" "HTP0","TOP_K","type=f32,ne=[33024,1,1,1],k=2051,ties=0","support","1","yes","HTP" "HTP0","TOP_K","type=f32,ne=[33024,4,1,1],k=2051,ties=0","support","1","yes","HTP" +"HTP0","TOP_K","type=f32,ne=[500,40000,1,1],k=16,ties=0","support","1","yes","HTP" +"HTP0","TOP_K","type=f32,ne=[1100,33000,1,1],k=16,ties=0","support","1","yes","HTP" "HTP0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","0","no","HTP" "HTP0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","0","no","HTP" "HTP0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=nearest","support","0","no","HTP" @@ -14776,6 +16400,10 @@ "HTP0","SUM","type=f32,ne=[33,1024,1,1]","support","1","yes","HTP" "HTP0","SUM","type=f32,ne=[33,256,1,1]","support","1","yes","HTP" "HTP0","SUM","type=f32,ne=[33,256,1,1],permute=[1,0,2,3]","support","0","no","HTP" +"HTP0","SUM","type=f32,ne=[10,5,4,3],permute=[1,0,2,3]","support","0","no","HTP" +"HTP0","SUM","type=f32,ne=[11,5,6,3],permute=[2,0,1,3]","support","0","no","HTP" +"HTP0","SUM","type=f32,ne=[11,5,6,3],slice=1","support","0","no","HTP" +"HTP0","SUM","type=f32,ne=[11,5,6,3],permute=[1,0,2,3],slice=1","support","0","no","HTP" "HTP0","SUM_ROWS","type=f32,ne=[10,5,4,3],permute=0,slice=0","support","1","yes","HTP" "HTP0","SUM_ROWS","type=f32,ne=[11,5,6,3],permute=1,slice=0","support","0","no","HTP" "HTP0","SUM_ROWS","type=f32,ne=[11,5,6,3],permute=0,slice=1","support","0","no","HTP" @@ -14810,6 +16438,9 @@ "HTP0","PAD","type=f32,ne_a=[100,1,1,1],pad_0=100,pad_1=0,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[100,1,1,1],pad_0=0,pad_1=100,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[100,100,1,1],pad_0=50,pad_1=50,circular=0","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[4,70000,1,1],pad_0=1,pad_1=1,circular=0","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[4,70000,1,1],pad_0=1,pad_1=1,circular=1","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[4,2,300,300],lp0=1,rp0=1,lp1=0,rp1=0,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=0","support","1","yes","HTP" "HTP0","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","0","no","HTP" "HTP0","PAD_REFLECT_1D","type=f32,ne_a=[3000,384,4,1],pad_0=10,pad_1=9","support","0","no","HTP" "HTP0","ROLL","shift0=3,shift1=-2,shift3=1,shift4=-1,permute=0","support","1","yes","HTP" @@ -14835,8 +16466,10 @@ "HTP0","CUMSUM","type=f32,ne=[20481,4,1,1]","support","1","yes","HTP" "HTP0","XIELU","type=f32,ne=[10,5,4,3]","support","0","no","HTP" "HTP0","XIELU","type=f16,ne=[10,5,4,3]","support","0","no","HTP" +"HTP0","XIELU","type=bf16,ne=[10,5,4,3]","support","0","no","HTP" "HTP0","XIELU","type=f32,ne=[512,16,1,1]","support","0","no","HTP" "HTP0","XIELU","type=f16,ne=[512,16,1,1]","support","0","no","HTP" +"HTP0","XIELU","type=bf16,ne=[512,16,1,1]","support","0","no","HTP" "HTP0","TRI","type=f32,ne=[10,10,4,3],tri_type=3","support","1","yes","HTP" "HTP0","TRI","type=f32,ne=[10,10,4,3],tri_type=2","support","1","yes","HTP" "HTP0","TRI","type=f32,ne=[10,10,4,3],tri_type=1","support","1","yes","HTP" @@ -14845,6 +16478,9 @@ "HTP0","FILL","type=f32,ne=[303,207,11,3],c=2.000000","support","1","yes","HTP" "HTP0","FILL","type=f32,ne=[800,600,4,4],c=-152.000000","support","1","yes","HTP" "HTP0","FILL","type=f32,ne=[2048,512,2,2],c=3.500000","support","1","yes","HTP" +"HTP0","FILL","type=f16,ne=[303,207,11,3],c=2.000000","support","1","yes","HTP" +"HTP0","FILL","type=f16,ne=[800,600,4,4],c=-152.000000","support","1","yes","HTP" +"HTP0","FILL","type=f16,ne=[2048,512,2,2],c=3.500000","support","1","yes","HTP" "HTP0","DIAG","type=f32,ne=[10,1,4,3]","support","1","yes","HTP" "HTP0","DIAG","type=f32,ne=[79,1,19,13]","support","1","yes","HTP" "HTP0","DIAG","type=f32,ne=[256,1,8,16]","support","1","yes","HTP" @@ -14874,16 +16510,22 @@ "HTP0","SOLVE_TRI","type=f32,ne_lhs=[64,64,4,4],ne_rhs=[384,64,4,4]","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=0,circular=0","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=0,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=1","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=0,circular=1","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=0,circular=1","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=1,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=1,circular=0","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=1,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=1,circular=1","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=1,circular=1","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=1,circular=1","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=2,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=2,circular=0","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=2,circular=0","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=2,circular=1","support","1","yes","HTP" "HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=2,circular=1","support","1","yes","HTP" +"HTP0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=2,circular=1","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -14944,30 +16586,30 @@ "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,1],kv=113,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,1],kv=113,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" @@ -15096,22 +16738,22 @@ "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,1],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=113,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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+"HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[4,3],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,1],kv=113,nb=1,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,1],kv=113,nb=3,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=40,hsv=40,nh=4,nr23=[1,1],kv=113,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" @@ -15128,22 +16770,22 @@ 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=bf16,type_V=bf16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15398,12 +17040,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15416,12 +17058,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15434,12 +17076,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15452,12 +17094,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15469,36 +17111,36 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=bf16,type_V=bf16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15506,12 +17148,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15524,12 +17166,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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-"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15542,12 +17184,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -15560,12 +17202,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16118,12 +17760,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=113,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16136,12 +17778,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16154,12 +17796,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16172,12 +17814,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16189,36 +17831,36 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16244,12 +17886,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16262,12 +17904,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -16280,12 +17922,12 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -20122,6 +21764,9 @@ "HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=72,hsv=64,nh=4,nr23=[1,1],kv=256,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=72,nh=4,nr23=[1,1],kv=256,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=17,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=1.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=113,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=1.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=128,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=128,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" "HTP0","FLASH_ATTN_EXT","hsk=72,hsv=72,nh=4,nr23=[1,1],kv=96,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" @@ -20138,16 +21783,18 @@ "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,1],kv=113,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,2],kv=1025,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=30.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,2],kv=1025,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=30.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,1],kv=1025,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[16,1],kv=16384,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=113,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=1024,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=24,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=24,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,2],kv=4096,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=768","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,2],kv=4096,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=768","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[16,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=512","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[16,2],kv=4096,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=768","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[16,2],kv=4096,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=768","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2304","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" @@ -20161,10 +21808,28 @@ "HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2048","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=8192,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" -"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=1,nr23=[12,2],kv=8192,nb=67,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","0","no","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=1,nr23=[12,2],kv=8192,nb=67,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=8192,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2048","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=8,nr23=[4,1],kv=512,nb=8,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","HTP" @@ -20183,12 +21848,27 @@ "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=0,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,2,1,3],kv_view=0,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=0,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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"HTP0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[8,1],kv=4096,nb=4,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=8,nr23=[4,1],kv=4096,nb=8,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[2,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" "HTP0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=4,nr23=[2,1],kv=1024,nb=4,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","HTP" 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+"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","1","yes","HTP" +"HTP0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=bf16,type_V=bf16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","0","no","HTP" "HTP0","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","HTP" "HTP0","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","HTP" "HTP0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","HTP" @@ -20223,14 +21903,48 @@ "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=64,n_seqs=1,v_repeat=1,permuted=0,kda=1,K=1","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=33,n_seqs=1,v_repeat=1,permuted=0,kda=1,K=1","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=100,n_seqs=1,v_repeat=1,permuted=0,kda=1,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=65,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=65,n_seqs=3,v_repeat=4,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=64,n_seqs=1,v_repeat=4,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=257,n_seqs=1,v_repeat=3,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=512,n_seqs=1,v_repeat=2,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=513,n_seqs=1,v_repeat=3,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=513,n_seqs=2,v_repeat=2,permuted=1,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=2048,n_seqs=1,v_repeat=2,permuted=0,kda=0,K=1","support","1","yes","HTP" +"HTP0","GATED_DELTA_NET","type=f32,head_count=16,head_size=128,n_seq_tokens=2047,n_seqs=2,v_repeat=3,permuted=0,kda=0,K=1","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=16,n_seq_tokens=2,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=2","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=32,n_seq_tokens=4,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=4","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=0,kda=0,K=4","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=8,head_size=128,n_seq_tokens=4,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=4","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=0,kda=1,K=4","support","1","yes","HTP" "HTP0","GATED_DELTA_NET","type=f32,head_count=8,head_size=32,n_seq_tokens=4,n_seqs=2,v_repeat=2,permuted=0,kda=1,K=4","support","1","yes","HTP" -"HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=32,n_seq_tokens=8,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=3","support","1","yes","HTP" -"HTP0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=16,n_seqs=2,v_repeat=1,permuted=0,kda=0,K=4","support","1","yes","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=iq4_nl","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=iq4_nl","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=iq4_nl","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=f32","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=f16","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=bf16","support","0","no","HTP" @@ -20285,6 +21999,33 @@ "HTP0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=q4_1","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=q4_0","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=iq4_nl","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=iq4_nl","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=iq4_nl","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=f32","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=f16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=bf16","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q8_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q5_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q5_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q4_1","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q4_0","support","0","no","HTP" +"HTP0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=iq4_nl","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=f32","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=f16","support","0","no","HTP" "HTP0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=bf16","support","0","no","HTP" diff --git a/docs/ops/OpenCL.csv b/docs/ops/OpenCL.csv index 997d8a420637..db66c5655b46 100644 --- a/docs/ops/OpenCL.csv +++ b/docs/ops/OpenCL.csv @@ -1,16 +1,16 @@ "backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" -"OpenCL","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" -"OpenCL","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" -"OpenCL","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" +"OpenCL","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" "OpenCL","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" @@ -21,38 +21,38 @@ "OpenCL","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" "OpenCL","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" "OpenCL","EXPM1","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","EXPM1","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" "OpenCL","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","CEIL","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","CEIL","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","ROUND","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ROUND","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","FLOOR","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","FLOOR","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" -"OpenCL","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" -"OpenCL","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" +"OpenCL","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" "OpenCL","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" @@ -63,38 +63,38 @@ "OpenCL","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" "OpenCL","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" "OpenCL","EXPM1","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","EXPM1","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","CEIL","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","CEIL","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","ROUND","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","ROUND","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","NEG","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","STEP","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","STEP","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","FLOOR","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","FLOOR","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","NEG","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","STEP","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","STEP","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","TANH","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" "OpenCL","TANH","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" -"OpenCL","ELU","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ELU","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","ELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","RELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" "OpenCL","RELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","SIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" @@ -105,38 +105,38 @@ "OpenCL","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","SILU","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" "OpenCL","SILU","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" -"OpenCL","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","EXP","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","EXP","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","EXPM1","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","EXPM1","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" +"OpenCL","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","EXP","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","EXP","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","EXPM1","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","EXPM1","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" "OpenCL","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" "OpenCL","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" -"OpenCL","FLOOR","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","CEIL","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","CEIL","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","ROUND","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","ROUND","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f32,ne_a=[128,2,2,2],v=0","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f32,ne_a=[5,7,11,13],v=0","support","0","no","OpenCL" -"OpenCL","ABS","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","ABS","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","SGN","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","SGN","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","NEG","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","NEG","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","STEP","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","STEP","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","FLOOR","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","FLOOR","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f32,ne_a=[128,2,2,2],v=0","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f32,ne_a=[5,7,11,13],v=0","support","1","yes","OpenCL" +"OpenCL","ABS","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","ABS","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","SGN","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","SGN","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","NEG","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","NEG","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","STEP","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","STEP","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","TANH","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" "OpenCL","TANH","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" -"OpenCL","ELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","ELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","ELU","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","ELU","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","RELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","RELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" "OpenCL","SIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" @@ -147,26 +147,173 @@ "OpenCL","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" "OpenCL","SILU","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" "OpenCL","SILU","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","EXP","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","EXPM1","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","EXPM1","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" -"OpenCL","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=1","support","0","no","OpenCL" +"OpenCL","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","EXP","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","EXPM1","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","EXPM1","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","OpenCL" +"OpenCL","SOFTPLUS","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","OpenCL" "OpenCL","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","no","OpenCL" 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"OpenCL","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=0,alpha=1.702000,limit=2.000000","support","1","yes","OpenCL" @@ -295,110 +502,275 @@ "OpenCL","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=1,alpha=0.500000,limit=7.000000","support","1","yes","OpenCL" "OpenCL","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=1,alpha=1.702000,limit=2.000000","support","1","yes","OpenCL" "OpenCL","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=1,alpha=1.702000,limit=7.000000","support","1","yes","OpenCL" -"OpenCL","GET_ROWS","type=f32,n=76800,m=5,r=4,be1=1,be2=2,v=0","support","1","yes","OpenCL" -"OpenCL","GET_ROWS","type=f32,n=256,m=80000,r=70000,be1=2,be2=1,v=0","support","1","yes","OpenCL" -"OpenCL","GET_ROWS","type=f32,n=256,m=5,r=4,be1=700,be2=100,v=0","support","1","yes","OpenCL" -"OpenCL","GET_ROWS","type=q4_0,n=76800,m=5,r=4,be1=1,be2=2,v=0","support","0","no","OpenCL" -"OpenCL","GET_ROWS","type=q4_0,n=256,m=80000,r=70000,be1=2,be2=1,v=0","support","0","no","OpenCL" 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"OpenCL","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=q1_0,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=q1_0,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=q2_0,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=q2_0,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=mxfp4,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=mxfp4,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=nvfp4,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" +"OpenCL","GET_ROWS_BACK","type=nvfp4,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=q2_K,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" 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"OpenCL","GET_ROWS_BACK","type=iq2_xs,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" @@ -447,309 +829,733 @@ "OpenCL","GET_ROWS_BACK","type=iq4_xs,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=0","support","0","no","OpenCL" "OpenCL","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=1","support","0","no","OpenCL" -"OpenCL","SET_ROWS","type=f32,type_idx=i64,ne=[1,8,1,3],nr23=[1,1],r=2,v=0","support","1","yes","OpenCL" -"OpenCL","SET_ROWS","type=f32,type_idx=i32,ne=[1,8,1,3],nr23=[1,1],r=2,v=0","support","1","yes","OpenCL" -"OpenCL","SET_ROWS","type=q8_0,type_idx=i32,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","no","OpenCL" -"OpenCL","SET_ROWS","type=f32,type_idx=i64,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","yes","OpenCL" -"OpenCL","SET_ROWS","type=f32,type_idx=i64,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","yes","OpenCL" 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"OpenCL","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","yes","OpenCL" "OpenCL","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","yes","OpenCL" +"OpenCL","REPEAT","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","no","OpenCL" "OpenCL","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","no","OpenCL" "OpenCL","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","no","OpenCL" +"OpenCL","REPEAT","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","no","OpenCL" "OpenCL","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","0","no","OpenCL" "OpenCL","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","0","no","OpenCL" "OpenCL","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","0","no","OpenCL" @@ -5000,7 +7707,7 @@ "OpenCL","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","no","OpenCL" "OpenCL","DUP","type=f32,ne=[10,10,20,1]","support","1","yes","OpenCL" "OpenCL","DUP","type=f16,ne=[10,10,20,1]","support","1","yes","OpenCL" -"OpenCL","DUP","type=i32,ne=[10,10,20,1]","support","0","no","OpenCL" +"OpenCL","DUP","type=i32,ne=[10,10,20,1]","support","1","yes","OpenCL" "OpenCL","DUP","type=i16,ne=[10,10,20,1]","support","0","no","OpenCL" "OpenCL","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","yes","OpenCL" "OpenCL","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","yes","OpenCL" @@ -5008,740 +7715,1519 @@ "OpenCL","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","yes","OpenCL" "OpenCL","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","no","OpenCL" "OpenCL","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","no","OpenCL" -"OpenCL","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","0","no","OpenCL" -"OpenCL","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","0","no","OpenCL" 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-"OpenCL","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","SUB","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","MUL","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","OpenCL" -"OpenCL","DIV","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","OpenCL" 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+"OpenCL","SQRT","type=f32,ne=[1024,1024,1,1]","support","1","yes","OpenCL" "OpenCL","LOG","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" +"OpenCL","LOG","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" "OpenCL","SIN","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" +"OpenCL","SIN","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" "OpenCL","COS","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" -"OpenCL","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000","support","1","yes","OpenCL" +"OpenCL","COS","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" +"OpenCL","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000,v=0","support","1","yes","OpenCL" +"OpenCL","CLAMP","type=f32,ne=[1024,1024,1,1],min=-0.500000,max=0.500000,v=0","support","1","yes","OpenCL" "OpenCL","LEAKY_RELU","type=f32,ne_a=[7,1,5,3],negative_slope=0.100000","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" -"OpenCL","FLOOR","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" -"OpenCL","CEIL","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" -"OpenCL","CEIL","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" -"OpenCL","ROUND","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" -"OpenCL","ROUND","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f32,ne=[7,1,5,3]","support","0","no","OpenCL" -"OpenCL","TRUNC","type=f32,ne=[1024,1024,1,1]","support","0","no","OpenCL" +"OpenCL","LEAKY_RELU","type=f32,ne_a=[1024,1024,1,1],negative_slope=0.100000","support","0","no","OpenCL" +"OpenCL","FLOOR","type=f32,ne=[7,1,5,3]","support","1","yes","OpenCL" +"OpenCL","FLOOR","type=f32,ne=[1024,1024,1,1]","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f32,ne=[7,1,5,3]","support","1","yes","OpenCL" +"OpenCL","CEIL","type=f32,ne=[1024,1024,1,1]","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f32,ne=[7,1,5,3]","support","1","yes","OpenCL" +"OpenCL","ROUND","type=f32,ne=[1024,1024,1,1]","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f32,ne=[7,1,5,3]","support","1","yes","OpenCL" +"OpenCL","TRUNC","type=f32,ne=[1024,1024,1,1]","support","1","yes","OpenCL" "OpenCL","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","1","yes","OpenCL" "OpenCL","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","1","yes","OpenCL" "OpenCL","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","0","no","OpenCL" @@ -8917,6 +15097,13 @@ "OpenCL","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,sinks=0,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" "OpenCL","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,sinks=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000,inplace=0","support","1","yes","OpenCL" "OpenCL","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,sinks=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[200001,2,3,1],mask=1,sinks=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[200001,2,3,1],mask=1,sinks=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[200000,1,1,1],mask=0,sinks=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[200000,4,1,1],mask=0,sinks=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[4,1,1,1],mask=0,sinks=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[4,1023,1,1],mask=0,sinks=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" +"OpenCL","SOFT_MAX","type=f32,ne=[643251,3,1,1],mask=0,sinks=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000,inplace=0","support","1","yes","OpenCL" "OpenCL","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","0","no","OpenCL" "OpenCL","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","0","no","OpenCL" "OpenCL","SOFT_MAX_BACK","type=f32,ne=[16,16,2,3],scale=1.000000,max_bias=0.000000","support","0","no","OpenCL" @@ -8965,490 +15152,1106 @@ "OpenCL","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","no","OpenCL" "OpenCL","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","no","OpenCL" "OpenCL","SOFT_MAX_BACK","type=f32,ne=[1024,1024,2,3],scale=0.100000,max_bias=8.000000","support","0","no","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,16,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,16,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,16,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[128,16,2,1],n_dims=128,mode=40,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" -"OpenCL","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1,inplace=0","support","1","yes","OpenCL" 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"OpenCL","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" -"OpenCL","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","no","OpenCL" +"OpenCL","CONCAT","type=f16,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" +"OpenCL","CONCAT","type=bf16,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" +"OpenCL","CONCAT","type=i8,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" +"OpenCL","CONCAT","type=i16,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" +"OpenCL","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" +"OpenCL","CONCAT","type=i64,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","yes","OpenCL" "OpenCL","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","yes","OpenCL" -"OpenCL","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","no","OpenCL" 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"OpenCL","ARGSORT","type=f32,ne=[1024,2,1,3],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[1025,2,1,3],order=0","support","0","no","OpenCL" +"OpenCL","ARGSORT","type=f32,ne=[1025,256,1,1],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[2047,2,1,3],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[2048,2,1,3],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[2049,2,1,3],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[2,8,8192,1],order=0","support","1","yes","OpenCL" +"OpenCL","ARGSORT","type=f32,ne=[2048,512,1,1],order=0","support","0","no","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[3,1,1,1],order=0","support","1","yes","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[4,1,1,1],order=0","support","1","yes","OpenCL" "OpenCL","ARGSORT","type=f32,ne=[7,1,1,1],order=0","support","1","yes","OpenCL" @@ -9539,9215 +16344,6174 @@ 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"SYCL0","TRUNC","type=f32,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" "SYCL0","TRUNC","type=f32,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","ABS","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","ABS","type=bf16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","SGN","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","SGN","type=bf16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","NEG","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","NEG","type=bf16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","STEP","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","STEP","type=bf16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","TANH","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","TANH","type=bf16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","ELU","type=bf16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" 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+"SYCL0","GELU_QUICK","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","SILU","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","SILU","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","HARDSWISH","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","HARDSWISH","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","HARDSIGMOID","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","HARDSIGMOID","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","EXP","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","EXP","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","EXPM1","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","EXPM1","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","SOFTPLUS","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","SOFTPLUS","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","GELU_ERF","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","GELU_ERF","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","FLOOR","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","FLOOR","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","CEIL","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","CEIL","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","ROUND","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","ROUND","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" +"SYCL0","TRUNC","type=bf16,ne_a=[128,2,2,2],v=1","support","1","yes","SYCL" +"SYCL0","TRUNC","type=bf16,ne_a=[5,7,11,13],v=1","support","1","yes","SYCL" "SYCL0","DSV4_HC_COMB","n_tokens=1,n_iter=1,eps=0.000001","support","1","yes","SYCL" "SYCL0","DSV4_HC_COMB","n_tokens=17,n_iter=4,eps=0.000001","support","1","yes","SYCL" "SYCL0","DSV4_HC_COMB","n_tokens=257,n_iter=8,eps=0.000001","support","1","yes","SYCL" @@ -196,12 +280,12 @@ "SYCL0","DSV4_HC_PRE","n_embd=128,n_hc=8,n_tokens=17,gated=1","support","1","yes","SYCL" "SYCL0","DSV4_HC_PRE","n_embd=128,n_hc=65,n_tokens=17,gated=0","support","1","yes","SYCL" "SYCL0","DSV4_HC_PRE","n_embd=128,n_hc=65,n_tokens=17,gated=1","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=1,n_tokens=1,identity=0","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=0","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=128,n_tokens=257,identity=0","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=0","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=1","support","1","yes","SYCL" -"SYCL0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=1","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=1,n_tokens=1,identity=0,gated=0","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=0,gated=0","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=128,n_tokens=257,identity=0,gated=0","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=0,gated=0","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=31,n_tokens=17,identity=1,gated=0","support","1","yes","SYCL" +"SYCL0","DSV4_HC_POST","n_embd=4096,n_tokens=21,identity=1,gated=0","support","1","yes","SYCL" "SYCL0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" "SYCL0","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" "SYCL0","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" @@ -322,6 +406,66 @@ "SYCL0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" "SYCL0","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" "SYCL0","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=0,split","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=0,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=0,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=0,split","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=0,split","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" +"SYCL0","REGLU","type=bf16,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU","type=bf16,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" +"SYCL0","SWIGLU","type=bf16,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU_ERF","type=bf16,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=1,swapped=0","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=1,swapped=1","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[128,2,2,2],v=1,split","support","1","yes","SYCL" +"SYCL0","GEGLU_QUICK","type=bf16,ne_a=[5,7,11,13],v=1,split","support","1","yes","SYCL" "SYCL0","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=0,alpha=0.500000,limit=2.000000","support","1","yes","SYCL" "SYCL0","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=0,alpha=0.500000,limit=7.000000","support","1","yes","SYCL" "SYCL0","SWIGLU_OAI","type=f32,ne_a=[128,2,2,2],v=0,alpha=1.702000,limit=2.000000","support","1","yes","SYCL" @@ -1429,6 +1573,10 @@ "SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[4096,2,1,1],k0=32,k1=1,s0=32,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[4096,2,1,1],k0=64,k1=1,s0=64,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[4160,2,1,1],k0=32,k1=1,s0=32,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[4160,2,1,1],k0=64,k1=1,s0=64,s1=1,p0=0,p1=0","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","yes","SYCL" @@ -1493,6 +1641,10 @@ "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","SYCL" "SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[4096,2,1,1],k0=32,k1=1,s0=32,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[4096,2,1,1],k0=64,k1=1,s0=64,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[4160,2,1,1],k0=32,k1=1,s0=32,s1=1,p0=0,p1=0","support","1","yes","SYCL" +"SYCL0","POOL_2D","pool_type=max,type_input=f32,ne_input=[4160,2,1,1],k0=64,k1=1,s0=64,s1=1,p0=0,p1=0","support","1","yes","SYCL" "SYCL0","POOL_1D","pool_type=avg,type_input=f32,ne_input=[10,3,2,1],k0=1,s0=1,p0=0","support","1","yes","SYCL" "SYCL0","POOL_1D","pool_type=avg,type_input=f32,ne_input=[11,1,3,2],k0=1,s0=1,p0=0","support","1","yes","SYCL" "SYCL0","POOL_1D","pool_type=avg,type_input=f32,ne_input=[128,2,1,3],k0=1,s0=1,p0=0","support","1","yes","SYCL" @@ -1801,6 +1953,16 @@ "SYCL0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[2,2,1536,729],ne_kernel=[2,2,1536,4096],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" "SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[128,128,1,2],ne_kernel=[32,33,1,2],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" "SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[128,128,2,1],ne_kernel=[33,34,2,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[64,64,320,1],ne_kernel=[1,1,320,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[16,16,1280,2],ne_kernel=[1,1,1280,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[8,8,2560,1],ne_kernel=[1,1,2560,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[32,32,192,1],ne_kernel=[2,2,192,1],s0=2,s1=2,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[64,512,1,1],ne_kernel=[2,512,1,1],s0=2,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[64,64,320,1],ne_kernel=[1,1,320,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[16,16,1280,2],ne_kernel=[1,1,1280,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[8,8,2560,1],ne_kernel=[1,1,2560,1],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[32,32,192,1],ne_kernel=[2,2,192,1],s0=2,s1=2,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","yes","SYCL" +"SYCL0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[64,512,1,1],ne_kernel=[2,512,1,1],s0=2,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","SYCL" "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,10,9],ne_kernel=[3,3,3,1],IC=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,v=0","support","1","yes","SYCL" "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,10,9],ne_kernel=[3,3,3,1],IC=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,v=0","support","1","yes","SYCL" "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,10,9],ne_kernel=[3,3,3,1],IC=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,v=0","support","1","yes","SYCL" @@ -3852,3149 +4014,3159 @@ "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=1","support","1","yes","SYCL" "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=0","support","1","yes","SYCL" "SYCL0","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=3,s1=3,s2=3,p0=3,p1=3,p2=3,d0=3,d1=3,d2=3,v=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f16,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0","support","1","yes","SYCL" -"SYCL0","CONV_2D","ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],type_kernel=f32,stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=1","support","1","yes","SYCL" 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+"SYCL0","CONV_1D_DW","ne_input=[64,16,1,1],ne_kernel=[7,1,16,1],type_kernel=bf16,stride=1,padding=3,dilation=1","support","1","yes","SYCL" +"SYCL0","CONV_1D_DW","ne_input=[97,33,1,1],ne_kernel=[5,1,33,1],type_kernel=bf16,stride=2,padding=2,dilation=2","support","1","yes","SYCL" "SYCL0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],type_kernel=f32,stride=1,padding=0,dilation=1,cwhn=0","support","1","yes","SYCL" "SYCL0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],type_kernel=f32,stride=1,padding=0,dilation=1,cwhn=1","support","1","yes","SYCL" "SYCL0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],type_kernel=f32,stride=2,padding=1,dilation=1,cwhn=0","support","1","yes","SYCL" @@ -7003,264 +7175,282 @@ "SYCL0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],type_kernel=f16,stride=1,padding=0,dilation=1,cwhn=1","support","1","yes","SYCL" "SYCL0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],type_kernel=f16,stride=2,padding=1,dilation=1,cwhn=0","support","1","yes","SYCL" "SYCL0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],type_kernel=f16,stride=2,padding=1,dilation=1,cwhn=1","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" 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-"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","1","yes","SYCL" -"SYCL0","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","1","yes","SYCL" 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+"SYCL0","CONV_3D","N=1,IC=1,ID=2,IH=2,IW=2,OC=1,KD=1,KH=0,KW=1,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16,kernel_offset=0","support","1","yes","SYCL" +"SYCL0","CONV_3D","N=1,IC=1,ID=2,IH=2,IW=2,OC=1,KD=0,KH=1,KW=1,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16,kernel_offset=0","support","1","yes","SYCL" "SYCL0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","yes","SYCL" "SYCL0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","yes","SYCL" "SYCL0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","yes","SYCL" @@ -7977,6 +8167,8 @@ "SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[2,2,524281,1],permute_src=[1,0,2,3],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","SYCL" "SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[128,2,3,1],ne_dst=[128,2,3,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[128,4,3,1]","support","1","yes","SYCL" "SYCL0","CPY","type_src=f16,type_dst=f16,ne_src=[128,2,3,1],ne_dst=[128,2,3,1],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[128,4,3,1]","support","1","yes","SYCL" +"SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[64,16,1,1],ne_dst=[1,64,16,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[32,64,16,1]","support","1","yes","SYCL" +"SYCL0","CPY","type_src=f16,type_dst=f16,ne_src=[64,16,1,1],ne_dst=[1,64,16,1],permute_src=[1,2,0,3],permute_dst=[0,0,0,0],_src_transpose=0,dst_alloc=[32,64,16,1]","support","1","yes","SYCL" "SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,7,32],ne_dst=[32,7,5,3],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","SYCL" "SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,32,7],ne_dst=[3,5,7,32],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","SYCL" "SYCL0","CPY","type_src=f32,type_dst=f32,ne_src=[3,5,32,7],ne_dst=[32,7,5,3],permute_src=[0,0,0,0],permute_dst=[0,0,0,0],_src_transpose=0","support","1","yes","SYCL" @@ -8333,6 +8525,10 @@ "SYCL0","SUB","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","MUL","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","DIV","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=f16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=f16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=f16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=f16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" @@ -8513,10 +8709,213 @@ "SYCL0","SUB","type=f32,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","MUL","type=f32,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" "SYCL0","DIV","type=f32,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=f32,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,6],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","1","yes","SYCL" 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+"SYCL0","DIV","type=bf16,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[128,1,8,1],nr=[1,4,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","ADD","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","SUB","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","MUL","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" +"SYCL0","DIV","type=bf16,ne=[5120,1,1,1],nr=[1,32,1,1],nf=1,perm1=0,src_overlap=0,type_b=f32","support","1","yes","SYCL" "SYCL0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000,inplace=0","support","1","yes","SYCL" "SYCL0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","1","yes","SYCL" "SYCL0","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=1","support","1","yes","SYCL" "SYCL0","SCALE","type=f32,ne=[100,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","1","yes","SYCL" +"SYCL0","SCALE","type=bf16,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=0","support","1","yes","SYCL" +"SYCL0","SCALE","type=bf16,ne=[10,10,10,10],scale=2.000000,bias=1.000000,inplace=1","support","1","yes","SYCL" +"SYCL0","SCALE","type=bf16,ne=[100,10,10,10],scale=0.500000,bias=0.000000,inplace=0","support","1","yes","SYCL" "SYCL0","SILU_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","no","SYCL" "SYCL0","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000,noncontig_rows=0","support","1","yes","SYCL" "SYCL0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000,inplace=0","support","1","yes","SYCL" @@ -8669,6 +9068,10 @@ "SYCL0","NORM","type=f32,ne=[260,5,4,3],v=1,eps=10.000000,noncontig_rows=0","support","1","yes","SYCL" "SYCL0","RMS_NORM","type=f32,ne=[260,5,4,3],v=1,eps=10.000000,inplace=0","support","1","yes","SYCL" "SYCL0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001,inplace=1","support","1","yes","SYCL" +"SYCL0","NORM","type=f32,ne=[4,1,65536,1],v=0,eps=0.000001,noncontig_rows=0","support","1","yes","SYCL" +"SYCL0","RMS_NORM","type=f32,ne=[4,1,65536,1],v=0,eps=0.000001,inplace=0","support","1","yes","SYCL" +"SYCL0","RMS_NORM","type=f32,ne=[4,1,1,65536],v=0,eps=0.000001,inplace=0","support","1","yes","SYCL" +"SYCL0","L2_NORM","type=f32,ne=[4,1,65536,1],eps=0.000000,v=0,noncontig_rows=0","support","1","yes","SYCL" "SYCL0","SSM_CONV","type=f32,ne_a=[3,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","SYCL" "SYCL0","SSM_CONV","type=f32,ne_a=[6,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","SYCL" "SYCL0","SSM_CONV","type=f32,ne_a=[3,1024,4,1],ne_b=[3,1024,1,1]","support","1","yes","SYCL" @@ -8715,6 +9118,8 @@ "SYCL0","SSM_CONV","type=f32,ne_a=[72,2048,1,1],ne_b=[9,2048,1,1]","support","1","yes","SYCL" "SYCL0","SSM_CONV","type=f32,ne_a=[72,2048,4,1],ne_b=[9,2048,1,1]","support","1","yes","SYCL" "SYCL0","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","0","no","SYCL" +"SYCL0","SSM_SCAN","type=f32,d_state=96,head_dim=64,n_head=128,n_group=8,n_seq_tokens=1,n_seqs=1,xbc_overlap=0,K=1,weak_decay=0","support","0","no","SYCL" +"SYCL0","SSM_SCAN","type=f32,d_state=96,head_dim=64,n_head=16,n_group=8,n_seq_tokens=300,n_seqs=2,xbc_overlap=0,K=1,weak_decay=1","support","0","no","SYCL" "SYCL0","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","1","yes","SYCL" "SYCL0","SSM_SCAN","type=f32,d_state=256,head_dim=64,n_head=8,n_group=2,n_seq_tokens=32,n_seqs=4,xbc_overlap=0,K=1,weak_decay=0","support","1","yes","SYCL" "SYCL0","SSM_SCAN","type=f32,d_state=128,head_dim=128,n_head=4,n_group=4,n_seq_tokens=16,n_seqs=2,xbc_overlap=1,K=1,weak_decay=0","support","1","yes","SYCL" @@ -8740,2640 +9145,3876 @@ "SYCL0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","SYCL" "SYCL0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","SYCL" "SYCL0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=128,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=64,n=1,k=64,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=256,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=512,n=1,k=512,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=128,n=32,k=128,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=128,n=4,k=128,bs=[2,3],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=256,n=512,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=32,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f32,m=1024,n=1,k=1024,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=64,n=1,k=64,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=128,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=256,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=512,n=1,k=512,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=128,n=32,k=128,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=128,n=4,k=128,bs=[2,3],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT_HADAMARD","type_a=f32,type_b=f16,m=256,n=512,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q1_0,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q2_0,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=8,k=4096,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=4,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=4,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=4,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=4,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=4,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=mxfp4,type_b=f16,m=16,n=8,k=256,bs=[1536,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=4,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=4,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f32,m=16,n=8,k=256,bs=[1536,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=4,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","0","no","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=4,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" -"SYCL0","MUL_MAT","type_a=nvfp4,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],k_v=0,o=1,src_overlap=0","support","1","yes","SYCL" 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-"SYCL0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=1","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f16,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","FLOOR","type=f16,ne=[10,2,2,2]","support","1","yes","SYCL" "SYCL0","CEIL","type=f16,ne=[10,2,2,2]","support","1","yes","SYCL" @@ -12846,8 +14488,8 @@ "SYCL0","SIN","type=f16,ne=[1024,1024,1,1]","support","1","yes","SYCL" "SYCL0","COS","type=f16,ne=[7,1,5,3]","support","1","yes","SYCL" "SYCL0","COS","type=f16,ne=[1024,1024,1,1]","support","1","yes","SYCL" -"SYCL0","CLAMP","type=f16,ne=[7,1,5,3],min=-0.500000,max=0.500000","support","1","yes","SYCL" -"SYCL0","CLAMP","type=f16,ne=[1024,1024,1,1],min=-0.500000,max=0.500000","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f16,ne=[7,1,5,3],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f16,ne=[1024,1024,1,1],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f16,ne_a=[7,1,5,3],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f16,ne_a=[1024,1024,1,1],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","FLOOR","type=f16,ne=[7,1,5,3]","support","1","yes","SYCL" @@ -12863,7 +14505,8 @@ "SYCL0","LOG","type=f32,ne=[10,5,4,3]","support","1","yes","SYCL" "SYCL0","SIN","type=f32,ne=[10,2,2,2]","support","1","yes","SYCL" "SYCL0","COS","type=f32,ne=[10,2,2,2]","support","1","yes","SYCL" -"SYCL0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000,v=1","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","FLOOR","type=f32,ne=[10,2,2,2]","support","1","yes","SYCL" "SYCL0","CEIL","type=f32,ne=[10,2,2,2]","support","1","yes","SYCL" @@ -12879,8 +14522,8 @@ "SYCL0","SIN","type=f32,ne=[1024,1024,1,1]","support","1","yes","SYCL" "SYCL0","COS","type=f32,ne=[7,1,5,3]","support","1","yes","SYCL" "SYCL0","COS","type=f32,ne=[1024,1024,1,1]","support","1","yes","SYCL" -"SYCL0","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000","support","1","yes","SYCL" -"SYCL0","CLAMP","type=f32,ne=[1024,1024,1,1],min=-0.500000,max=0.500000","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f32,ne=[7,1,5,3],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" +"SYCL0","CLAMP","type=f32,ne=[1024,1024,1,1],min=-0.500000,max=0.500000,v=0","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f32,ne_a=[7,1,5,3],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","LEAKY_RELU","type=f32,ne_a=[1024,1024,1,1],negative_slope=0.100000","support","1","yes","SYCL" "SYCL0","FLOOR","type=f32,ne=[7,1,5,3]","support","1","yes","SYCL" @@ -14222,6 +15865,12 @@ "SYCL0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=1,v=12","support","1","yes","SYCL" "SYCL0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=2,v=12","support","1","yes","SYCL" "SYCL0","CONCAT","type=q8_0,ne_a=[128,12,13,14],ne_b_d=7,dim=3,v=12","support","1","yes","SYCL" +"SYCL0","CONCAT","type=f32,ne_a=[98304,8,1,1],ne_b_d=288,dim=0,v=0","support","1","yes","SYCL" +"SYCL0","CONCAT","type=f32,ne_a=[20000,3,2,1],ne_b_d=333,dim=0,v=1","support","1","yes","SYCL" +"SYCL0","CONCAT","type=q8_0,ne_a=[8192,2,1,1],ne_b_d=4096,dim=0,v=0","support","1","yes","SYCL" +"SYCL0","CONCAT","type=f32,ne_a=[98304,8,1,1],ne_b_d=2,dim=1,v=0","support","1","yes","SYCL" +"SYCL0","CONCAT","type=f32,ne_a=[20000,3,2,1],ne_b_d=1,dim=1,v=1","support","1","yes","SYCL" +"SYCL0","CONCAT","type=q8_0,ne_a=[8192,2,1,1],ne_b_d=1,dim=1,v=0","support","1","yes","SYCL" "SYCL0","ARGSORT","type=f32,ne=[3,1,1,1],order=0","support","1","yes","SYCL" "SYCL0","ARGSORT","type=f32,ne=[4,1,1,1],order=0","support","1","yes","SYCL" "SYCL0","ARGSORT","type=f32,ne=[7,1,1,1],order=0","support","1","yes","SYCL" @@ -14679,6 +16328,8 @@ "SYCL0","TOP_K","type=f32,ne=[8192,2,1,1],k=2051,ties=0","support","1","yes","SYCL" "SYCL0","TOP_K","type=f32,ne=[33024,1,1,1],k=2051,ties=0","support","1","yes","SYCL" "SYCL0","TOP_K","type=f32,ne=[33024,4,1,1],k=2051,ties=0","support","1","yes","SYCL" +"SYCL0","TOP_K","type=f32,ne=[500,40000,1,1],k=16,ties=0","support","1","yes","SYCL" +"SYCL0","TOP_K","type=f32,ne=[1100,33000,1,1],k=16,ties=0","support","1","yes","SYCL" "SYCL0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","1","yes","SYCL" "SYCL0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","1","yes","SYCL" "SYCL0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=nearest","support","1","yes","SYCL" @@ -14753,6 +16404,9 @@ "SYCL0","PAD","type=f32,ne_a=[100,1,1,1],pad_0=100,pad_1=0,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[100,1,1,1],pad_0=0,pad_1=100,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[100,100,1,1],pad_0=50,pad_1=50,circular=0","support","1","yes","SYCL" +"SYCL0","PAD","type=f32,ne_a=[4,70000,1,1],pad_0=1,pad_1=1,circular=0","support","1","yes","SYCL" +"SYCL0","PAD","type=f32,ne_a=[4,70000,1,1],pad_0=1,pad_1=1,circular=1","support","0","no","SYCL" +"SYCL0","PAD","type=f32,ne_a=[4,2,300,300],lp0=1,rp0=1,lp1=0,rp1=0,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=0","support","1","yes","SYCL" "SYCL0","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","1","yes","SYCL" "SYCL0","PAD_REFLECT_1D","type=f32,ne_a=[3000,384,4,1],pad_0=10,pad_1=9","support","1","yes","SYCL" "SYCL0","ROLL","shift0=3,shift1=-2,shift3=1,shift4=-1,permute=0","support","1","yes","SYCL" @@ -14778,8 +16432,10 @@ "SYCL0","CUMSUM","type=f32,ne=[20481,4,1,1]","support","1","yes","SYCL" "SYCL0","XIELU","type=f32,ne=[10,5,4,3]","support","1","yes","SYCL" "SYCL0","XIELU","type=f16,ne=[10,5,4,3]","support","1","yes","SYCL" +"SYCL0","XIELU","type=bf16,ne=[10,5,4,3]","support","1","yes","SYCL" "SYCL0","XIELU","type=f32,ne=[512,16,1,1]","support","1","yes","SYCL" "SYCL0","XIELU","type=f16,ne=[512,16,1,1]","support","1","yes","SYCL" +"SYCL0","XIELU","type=bf16,ne=[512,16,1,1]","support","1","yes","SYCL" "SYCL0","TRI","type=f32,ne=[10,10,4,3],tri_type=3","support","1","yes","SYCL" "SYCL0","TRI","type=f32,ne=[10,10,4,3],tri_type=2","support","1","yes","SYCL" "SYCL0","TRI","type=f32,ne=[10,10,4,3],tri_type=1","support","1","yes","SYCL" @@ -14788,6 +16444,9 @@ "SYCL0","FILL","type=f32,ne=[303,207,11,3],c=2.000000","support","1","yes","SYCL" "SYCL0","FILL","type=f32,ne=[800,600,4,4],c=-152.000000","support","1","yes","SYCL" "SYCL0","FILL","type=f32,ne=[2048,512,2,2],c=3.500000","support","1","yes","SYCL" +"SYCL0","FILL","type=f16,ne=[303,207,11,3],c=2.000000","support","1","yes","SYCL" +"SYCL0","FILL","type=f16,ne=[800,600,4,4],c=-152.000000","support","1","yes","SYCL" +"SYCL0","FILL","type=f16,ne=[2048,512,2,2],c=3.500000","support","1","yes","SYCL" "SYCL0","DIAG","type=f32,ne=[10,1,4,3]","support","1","yes","SYCL" "SYCL0","DIAG","type=f32,ne=[79,1,19,13]","support","1","yes","SYCL" "SYCL0","DIAG","type=f32,ne=[256,1,8,16]","support","1","yes","SYCL" @@ -14817,16 +16476,22 @@ "SYCL0","SOLVE_TRI","type=f32,ne_lhs=[64,64,4,4],ne_rhs=[384,64,4,4]","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=0,circular=0","support","1","yes","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=0,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=0,circular=1","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=0,circular=1","support","0","no","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=0,circular=1","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=1,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=1,circular=0","support","1","yes","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=1,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=1,circular=1","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=1,circular=1","support","0","no","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=1,circular=1","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=2,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=2,circular=0","support","1","yes","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=2,circular=0","support","1","yes","SYCL" "SYCL0","PAD","type=f32,ne_a=[512,512,1,1],lp0=0,rp0=1,lp1=0,rp1=1,lp2=0,rp2=0,lp3=0,rp3=0,tfrm=2,circular=1","support","0","no","SYCL" "SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=1,rp0=2,lp1=3,rp1=4,lp2=5,rp2=6,lp3=7,rp3=8,tfrm=2,circular=1","support","0","no","SYCL" +"SYCL0","PAD","type=f32,ne_a=[11,22,33,44],lp0=0,rp0=2,lp1=0,rp1=4,lp2=0,rp2=6,lp3=0,rp3=8,tfrm=2,circular=1","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=8,nr23=[4,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" @@ -20065,6 +21730,9 @@ "SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=72,hsv=64,nh=4,nr23=[1,1],kv=256,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=72,nh=4,nr23=[1,1],kv=256,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=17,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=1.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=65,hsv=67,nh=4,nr23=[1,1],kv=113,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=1.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=128,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=128,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=72,hsv=72,nh=4,nr23=[1,1],kv=96,nb=2,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" @@ -20087,6 +21755,8 @@ "SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=113,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=1024,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=24,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=24,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=1,nr23=[8,2],kv=4096,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=768","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=1,nr23=[16,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=512","support","1","yes","SYCL" @@ -20108,6 +21778,24 @@ "SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=4096,nb=64,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=8192,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2048","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=32768,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2048","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=2,nr23=[12,1],kv=32768,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=2048","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[1,1],kv=8192,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[1,1],kv=8192,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=1,nr23=[8,1],kv=5003,nb=4,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=512","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=bf16,type_V=bf16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_0,type_V=q4_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q4_1,type_V=q4_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_0,type_V=q5_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q5_1,type_V=q5_1,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=iq4_nl,type_V=iq4_nl,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=f16,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=q4_0,permute=[0,2,1,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=q8_0,type_V=f32,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=96,nh=2,nr23=[8,2],kv=5003,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f32,type_V=q8_0,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=257","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=320,hsv=256,nh=1,nr23=[32,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","0","no","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=8,nr23=[4,1],kv=512,nb=8,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=1,n_kv_max=0","support","1","yes","SYCL" @@ -20132,6 +21820,10 @@ "SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=8,nr23=[4,1],kv=4096,nb=8,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[2,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" "SYCL0","FLASH_ATTN_EXT","hsk=512,hsv=512,nh=4,nr23=[2,1],kv=1024,nb=4,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=16,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=8,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","1","yes","SYCL" +"SYCL0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3],kv_view=1,v_is_view_of_k=0,n_kv_max=0,q_range=20","support","1","yes","SYCL" "SYCL0","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","1","yes","SYCL" "SYCL0","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","1","yes","SYCL" "SYCL0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","1","yes","SYCL" @@ -20174,6 +21866,33 @@ "SYCL0","GATED_DELTA_NET","type=f32,head_count=8,head_size=32,n_seq_tokens=4,n_seqs=2,v_repeat=2,permuted=0,kda=1,K=4","support","1","yes","SYCL" "SYCL0","GATED_DELTA_NET","type=f32,head_count=4,head_size=32,n_seq_tokens=8,n_seqs=1,v_repeat=1,permuted=0,kda=0,K=3","support","1","yes","SYCL" "SYCL0","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=16,n_seqs=2,v_repeat=1,permuted=0,kda=0,K=4","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=1,nm=1,type_K=iq4_nl","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=4,type_K=iq4_nl","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=1,ns=4,nm=1,type_K=iq4_nl","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=f32","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=f16","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=1,ns=1,nm=1,type_K=bf16","support","1","yes","SYCL" @@ -20228,6 +21947,33 @@ "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=q4_1","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=q4_0","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=64,kv=256,nb=1,ns=4,nm=1,type_K=iq4_nl","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=1,nm=1,type_K=iq4_nl","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=4,type_K=iq4_nl","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=f32","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=f16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=bf16","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q8_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q5_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q5_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q4_1","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=q4_0","support","1","yes","SYCL" +"SYCL0","LIGHTNING_INDEXER","hsk=128,nh=4,kv=256,nb=512,ns=4,nm=1,type_K=iq4_nl","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=f32","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=f16","support","1","yes","SYCL" "SYCL0","LIGHTNING_INDEXER","hsk=128,nh=32,kv=256,nb=512,ns=1,nm=1,type_K=bf16","support","1","yes","SYCL" diff --git a/docs/speculative.md b/docs/speculative.md index a32842a256b0..d8f3bcb3922a 100644 --- a/docs/speculative.md +++ b/docs/speculative.md @@ -100,8 +100,9 @@ llama-server -m Qwen3-4B.gguf -md Qwen3-4B-DSpark.gguf \ `--spec-draft-n-max` is clamped to the draft model's trained block size. -`--spec-draft-conf-min P` truncates each drafted block at the first position whose predicted -acceptance (from the draft's confidence head, if present) falls below `P` (default 0 = disabled). +`--spec-draft-p-min P` truncates each drafted block at the first position whose predicted +acceptance (from the draft's confidence head) falls below `P` (default 0 = disabled). +Values above 0 require a draft with a confidence head. Currently only drafts with a Qwen3 backbone are supported; support for other backbones (e.g. Gemma4) is planned. diff --git a/examples/llama-eval/README.md b/examples/llama-eval/README.md index 3c5c35f78f6c..1f0b5a09a486 100644 --- a/examples/llama-eval/README.md +++ b/examples/llama-eval/README.md @@ -24,3 +24,267 @@ python3 llama-eval.py \ --dataset aime2025 --n_cases 240 \ --grader-type regex ``` + +### Authentication + +A server started with `--api-key` (or any OpenAI-compatible endpoint behind a +token) needs one here too. `--api-key` is sent as `Authorization: Bearer` on +every eval request; it falls back to `$LLAMA_API_KEY`, which keeps the secret +out of your shell history and off the process list. + +```bash +# One key for every server +python3 llama-eval.py --server http://localhost:8033 --api-key sk-... ... + +# From the environment +export LLAMA_API_KEY=sk-... +python3 llama-eval.py --server http://localhost:8033 ... + +# One key per server, in --server order +python3 llama-eval.py \ + --server http://server1:8033,http://server2:8033 \ + --api-key sk-one,sk-two --threads 16,16 ... +``` + +The LLM grader authenticates too. It reuses the key of the server it runs on, +so `--grader-type llm` without `--grader-server` needs nothing extra; a grader +on a separate endpoint takes `--grader-api-key`. + +Endpoints on an opencode host additionally get an `x-opencode-session` header, +generated fresh for every task. An agentic episode sends the same id on all of +its turns, so opencode sees one session per task instead of one per request; +other servers never see the header. + +## Agentic suite + +`--dataset agentic` is a different shape from the other code suites. It runs +**SACB** (Simple Agent Coding Benchmark), hosted at +[`ilintar/SACB`](https://huggingface.co/datasets/ilintar/SACB) -- 60 tasks over +three hand-written repositories, in Python and TypeScript. Rather than +answering one prompt, the model is given a small but real repository, a +deliberately narrow tool set, and a bug report, and drives its own multi-turn +conversation until it declares itself finished. It is then graded by running a +test suite it was never allowed to see. + +```bash +python3 llama-eval.py \ + --server http://localhost:8033 --model my-model \ + --dataset agentic --threads 1 --temperature 0 +``` + +### The tools + +| tool | purpose | +|---|---| +| `list_files` | enumerate the tree | +| `read_file` | read, with 1-based line numbers and optional line-range narrowing | +| `search` | regular-expression search across the repository | +| `edit_lines` | replace an inclusive line range | +| `edit_replace` | replace an exact snippet, which must be unique | +| `write_file` | write a whole file | +| `lint` | run the language's linter and type checker | +| `finish` | declare the change complete | + +Three constraints are deliberate: + +**There is no shell and no way to run the tests.** The only feedback channel is +`lint`. A syntax or type error can be driven out mechanically; a logic error has +to be reasoned about. A harness that lets an agent iterate against the test +suite measures something closer to search than to understanding. + +**There are two edit tools**, one line-addressed and one content-addressed. +Which one a model reaches for, and whether it keeps line numbers straight after +its own earlier edit, is itself a signal. + +**The tests never touch the working tree.** They are held outside it and copied +into a throwaway copy only after the agent has stopped, so they can be neither +read nor edited. Every tool path is resolved and confinement-checked against the +repository root, so a symlink planted inside the tree cannot reach outside it. + +### Scoring + +A task is **resolved** when every test that was failing now passes *and* nothing +that was already passing broke. Both sets are derived by running the tests twice +when the corpus is built -- once against the defective tree and once against the +reference fix -- never hand-written, so a task whose defect no test exercises is +rejected rather than shipped. + +Because many tasks contain several independent defects, the fraction of target +tests passed is reported alongside, which separates "fixed two of the three +faults" from "changed nothing". Process metrics are reported too: turns, tool +calls, rejected calls, edits, and the peak conversation size. + +### Dependencies + +Nothing here is installed unless you select this suite, and then only for the +language you actually run. `--agentic-lang python` provisions ruff and mypy; +`--agentic-lang typescript` provisions the TypeScript compiler and uses node's +own test runner. Neither touches the other, and no other suite touches either. + +### Useful flags + +| flag | meaning | +|---|---| +| `--agentic-lang` | restrict to one language, and provision only its toolchain | +| `--agentic-max-turns` | give up after this many assistant turns (default 50) | +| `--agentic-max-tokens` | cap generation per turn (default: no cap); bounds a model that falls into a repetition loop, but also cuts reasoning off mid-thought. Truncated turns are counted as `truncated_turns` | +| `--agentic-context-limit` | abandon an episode once its context exceeds this many tokens | +| `--agentic-transcripts DIR` | save each episode's full message history to `DIR/<task_id>.json`, plus a `DIR/<task_id>.html` showing every reasoning block, reply, tool call and tool result; the main report links to it | + + +## Code suites (HumanEval, ClassEval) + +`--dataset humaneval` runs the 164 OpenAI HumanEval problems; `--dataset +classeval` runs the 100 ClassEval class-generation tasks. Unlike the other +suites these are not graded by matching text: the model's reply is parsed for a +```` ```python ```` block, that code is combined with the task's own unit tests, +and the result is **executed**. + +ClassEval asks for a whole class rather than one function, so it is scored the +way upstream does - **class level** (every one of the task's tests passes, which +is what feeds pass@k) and **method level** (what fraction of all 2196 test +methods passed). The second number separates "generated nothing usable" from +"got most of the class right", and both are printed at the end of a run. + +Give it more room to generate than HumanEval - a class with ten methods does not +fit in a short budget: + +```bash +python3 llama-eval.py \ + --server http://localhost:8033 --model my-model \ + --dataset classeval --threads 8 --n_predict 4096 --temperature 0 +``` + +```bash +# pass@1, greedy +python3 llama-eval.py \ + --server http://localhost:8033 --model my-model \ + --dataset humaneval --threads 8 --n_predict 1024 --temperature 0 + +# pass@10 -- each extra multiple of 164 is another sample per problem +python3 llama-eval.py \ + --server http://localhost:8033 --model my-model \ + --dataset humaneval --n_cases 1640 --temperature 0.8 --top-p 0.95 +``` + +`--grader-type exec` is the default for code suites, so neither it nor +`--dataset-source` normally needs to be passed. + +### Execution sandbox - no Docker required + +Generated code is untrusted, but these suites need far less than a container to +run safely. **The package set is derived from the dataset's own imports at +startup**, not hardcoded and not taken from the upstream `requirements.txt` - +which for ClassEval lists `torch`, `openai` and `transformers` that its *tests* +never touch. So each suite installs exactly what it needs: + +| suite | third-party packages | +|---|---| +| HumanEval | **none** - every problem imports only stdlib (`typing, math, random, copy, string, collections, hashlib, re`) | +| ClassEval | 13: `beautifulsoup4, gensim, lxml, netifaces, nltk, numpy, openpyxl, pandas, pillow, pypdf2, python-docx, reportlab, scipy` | + +Two of ClassEval's are *declared* rather than derived, because no import +statement mentions them: `lxml` is selected by string +(`BeautifulSoup(html, 'lxml')`, ClassEval_44 - without it that task silently +drops from 23/23 to 7/23), and `scipy` is a hard gensim requirement. Note also +that `PyPDF2` must **not** be modernised to `pypdf`: ClassEval_69's test imports +`PdfFileReader`, a name pypdf removed. + +The venv is cached under `~/.cache/llama-eval/` (override with +`LLAMA_EVAL_CACHE`) and rebuilt only when the package set, interpreter version +or provisioning steps change; force one with `--rebuild-sandbox`. `uv` is used +when available, which makes even the ClassEval venv build in seconds. + +**Interpreter selection.** A suite can prefer a different Python than the one +running the tool, and declares it: ClassEval asks for 3.13, because gensim +publishes no wheel past cp313 and its generated C no longer compiles on 3.14 +(it still uses `PyLongObject.ob_digit`). That interpreter is found automatically, +including via `uv python`; `--sandbox-python` overrides it. + +3.14 is fully supported anyway. ClassEval uses exactly two gensim APIs +(`utils.decode_htmlentities`, `matutils.unitvec`), both pure Python upstream, so +on 3.14+ the suite drops gensim from the install set and provisions a small shim +instead. Both paths score **100/100**. + +**Offline provisioning.** A suite that would otherwise fetch data at test time +declares a provisioning step that runs once at venv build time, while the +network is still up. ClassEval uses this to pre-seed exactly three nltk corpora +(`punkt_tab`, `averaged_perceptron_tagger_eng`, `wordnet`, ~33 MB), so the tests +themselves run with no network at all. Those are the *current* names - the +dataset asks for `punkt` and `averaged_perceptron_tagger`, which nltk has since +renamed, and seeding the legacy names too is not harmless: with a network +available nltk considers them satisfied and re-fetches the modern ones anyway. +The corpora are written *inside* the venv, not `~/nltk_data`, because `$HOME` is +a tmpfs under the strongest isolation tier. + +Each candidate program runs in a throwaway directory as its own process group, +under the strongest isolation the host offers: + +| tier | requires | isolates | +|---|---|---| +| `bwrap` | bubblewrap installed | read-only root, tmpfs `/tmp` and `$HOME`, **no network** | +| `unshare` | `unshare --map-current-user` | **no network** | +| `unshare-root` | any `unshare -r` | no network, but **runs as uid 0** - see below | +| `rlimit` | always available | cpu/memory/file-size/process caps only | + +**Candidate code must not run as root**, which is why `unshare -r` is a +last-resort tier that prints a warning. Root bypasses file permission bits, so a +test asserting that writing to a `chmod 0444` file *fails* instead sees it +succeed - ClassEval_50 scores 14/16 under uid 0 and 16/16 under uid 1000, with +nothing in the output to suggest the sandbox caused it. Install bubblewrap. + +All tiers additionally cap CPU time, address space (4 GiB), file size and core +dumps, and kill the whole process group on timeout (`--exec-timeout`, default +15 s - raise it for ClassEval, whose tests do real work). Writes to the +throwaway working directory are allowed, which is all the file-handling tasks in +ClassEval need. + +Note that the weakest tier does not contain filesystem access. If you are +scoring output from a model you do not trust, check the tier printed at startup. + +### Reproducibility + +Several tasks draw their test inputs from the *global, unseeded* RNG, so a +verdict is not reproducible run to run - which adds noise exactly when you are +comparing two models or two quantisations. `--exec-seed` (default `0`) seeds the +RNG before each test; pass `--exec-seed -1` for the stock upstream behaviour. +This does not change what the model is asked to compute. + +It matters more than it sounds. HumanEval/38, /50 and /53 are affected, and +ClassEval_58 (duplicate mine placement) fails about 30% of the time on its own +*reference* solution - measured here at 21/30 passes unseeded versus **30/30 +seeded**. + +### Dataset fidelity + +The canonical dataset runs **unmodified on current Python** - all 164 reference +solutions pass on CPython 3.14 with no patches, so no forked or re-hosted copy +is needed. `--dataset-source` accepts a local `.jsonl` or a HuggingFace repo id +if you do want to point at a modified copy. + +HumanEval does contain a handful of long-standing defects where the *prompt* +contradicts the graded test (notably HumanEval/47, /116 and /148). Those +penalise a model that reads the docstring carefully, but correcting them makes +the benchmark marginally easier and the resulting scores no longer comparable +with published HumanEval numbers, so nothing is patched by default. + +ClassEval is different: the upstream data has defects that cap the achievable +score below 100% for reasons unrelated to the model, so `--dataset classeval` +defaults to a **patched fork**, +[`ilintar/ClassEval`](https://huggingface.co/datasets/ilintar/ClassEval). +Six edits over five tasks lift the reference solutions from 96/100 classes and +2182/2196 test methods to **100/100 and 2196/2196**. Three repair tests nothing +could pass: + +- **ClassEval_17** was a time bomb - a hard-coded 2024 date checked against + `datetime.now()`, unpassable since January 2024. +- **ClassEval_48** asserted `get_hostname('0.0.0.0') == 'LAPTOP-2CS86KUM'`, the + dataset author's own machine name. +- **ClassEval_31** compared floats with `assertEqual`, failing on a 4-ULP numpy + difference. + +The other three fix only the *reference* solutions (NumPy 2.0 removals in +ClassEval_51, a 30%-flaky mine generator in ClassEval_58) and cannot affect a +model's score. No `skeleton` was touched, so what the model is asked to write is +byte-identical to upstream. Pass `--dataset-source FudanSELab/ClassEval` for the +unpatched original. diff --git a/examples/llama-eval/agentic_eval.py b/examples/llama-eval/agentic_eval.py new file mode 100644 index 000000000000..96629088a703 --- /dev/null +++ b/examples/llama-eval/agentic_eval.py @@ -0,0 +1,918 @@ +#!/usr/bin/env python3 +"""Multi-turn agentic coding eval: tools over a real working tree. + +The existing code suites are single-shot -- one prompt, one reply, execute, +grade. This one is not. The model is given a small but real repository and a +deliberately narrow tool set, and has to find its way to the defect before it +can fix it. That shape is what puts a run in the tens-of-thousands-of-tokens +range without any artificial padding: the context grows because the model +chose to read things. + +Three deliberate constraints: + +* No shell, and no way to run the tests. The only feedback channel is `lint`. + A syntax or type error can be driven out mechanically; a logic error has to + be reasoned about. Suites that let an agent iterate against the test suite + measure something closer to search than to understanding. +* Two edit tools, one line-addressed and one content-addressed. Which one a + model reaches for, and whether it keeps line numbers straight after its own + earlier edit, is itself a signal. +* Tests never touch the working tree. They are held outside it and copied in + after the agent has stopped, so they can be neither read nor edited. + +Everything here is imported lazily by llama-eval.py, and every dependency it +needs is scoped to the language actually under test, so none of it is +installed for anyone running the other suites. +""" + +import html +import json +import os +import re +import shutil +import tempfile +from dataclasses import dataclass, field +from pathlib import Path +from typing import Any, Dict, List, Optional, Sequence, Tuple + +MAX_READ_LINES = 400 +MAX_TOOL_CHARS = 12000 +MAX_SEARCH_HITS = 60 + + +@dataclass +class LangSpec: + """Everything language-specific: how to lint, how to test, what to install. + + Kept as data so adding a language is a corpus concern rather than a harness + change, and so a run only ever provisions the toolchain for the language it + is actually evaluating. + """ + name: str + exts: Tuple[str, ...] + packages: Tuple[str, ...] = () + provision: Tuple[str, ...] = () + env: Dict[str, str] = field(default_factory=dict) + address_space_limit: Optional[int] = 4 * 1024 * 1024 * 1024 + + def source_files(self, root: Path) -> List[Path]: + return sorted(p for p in root.rglob("*") + if p.is_file() and p.suffix in self.exts) + + +PYTHON = LangSpec( + name="python", + exts=(".py",), + packages=("ruff==0.14.2", "mypy==1.18.2"), +) + +TYPESCRIPT = LangSpec( + name="typescript", + exts=(".ts",), + address_space_limit=16 * 1024 * 1024 * 1024, + provision=( + "import os, subprocess, shutil, sys\n" + "npm = shutil.which('npm')\n" + "if not npm: sys.exit('npm not found on PATH; needed for the typescript suite')\n" + "dest = os.path.join(os.environ['SANDBOX_VENV'], 'node')\n" + "os.makedirs(dest, exist_ok=True)\n" + "r = subprocess.run([npm, 'install', '--silent', '--no-audit', '--no-fund',\n" + " '--prefix', dest, 'typescript@5.9.3'],\n" + " capture_output=True, text=True)\n" + "sys.exit(0 if r.returncode == 0 else (r.stderr or r.stdout)[-2000:])\n", + ), +) + +LANGS: Dict[str, LangSpec] = {"python": PYTHON, "typescript": TYPESCRIPT} + + +class PathEscape(Exception): + """A tool was handed a path outside the repository.""" + + +class Workspace: + """A private, writable copy of one task's repository. + + Every tool path is resolved through here. Confinement is checked on the + fully-resolved path, so a symlink planted inside the tree cannot be used to + read or write outside it. + """ + + def __init__(self, root: Path): + self.root = root.resolve() + self.escape_attempts = 0 + + def resolve(self, rel: str) -> Path: + if rel is None or not str(rel).strip(): + raise PathEscape("no path given") + raw = Path(str(rel)) + base = raw if raw.is_absolute() else (self.root / raw) + candidate = base.resolve() + if candidate != self.root and self.root not in candidate.parents: + self.escape_attempts += 1 + raise PathEscape(f"path {rel!r} is outside the repository") + return candidate + + def rel(self, path: Path) -> str: + return str(path.relative_to(self.root)) + + def files(self) -> List[Path]: + return sorted(p for p in self.root.rglob("*") + if p.is_file() and "__pycache__" not in p.parts) + + def snapshot(self) -> Dict[str, str]: + out = {} + for p in self.files(): + try: + out[self.rel(p)] = p.read_text() + except (UnicodeDecodeError, OSError): + pass + return out + + +def _clip(text: str, limit: int = MAX_TOOL_CHARS) -> str: + if len(text) <= limit: + return text + return text[:limit] + f"\n... [truncated, {len(text) - limit} more characters]" + + +def _numbered(lines: Sequence[str], start: int) -> str: + width = len(str(start + len(lines) - 1)) + return "\n".join(f"{start + i:>{width}}\t{ln}" for i, ln in enumerate(lines)) + + +def tool_schemas() -> List[Dict[str, Any]]: + """OpenAI-format function schemas for the whole tool set.""" + def fn(name, desc, props, required=()): + return {"type": "function", "function": { + "name": name, "description": desc, + "parameters": {"type": "object", "properties": props, + "required": list(required)}}} + + return [ + fn("list_files", "List files in the repository.", + {"path": {"type": "string", + "description": "Directory relative to the repository root. " + "Omit for the whole tree."}}), + fn("read_file", + "Read a file. Output is prefixed with 1-based line numbers. Give " + "start_line/end_line to read only part of a large file.", + {"path": {"type": "string", "description": "File path relative to the repository root."}, + "start_line": {"type": "integer", "description": "First line to read, 1-based, inclusive."}, + "end_line": {"type": "integer", "description": "Last line to read, 1-based, inclusive."}}, + ["path"]), + fn("search", + "Search the repository with a regular expression. Returns matching " + "lines with their file and line number.", + {"pattern": {"type": "string", "description": "Python regular expression."}, + "path": {"type": "string", "description": "Limit the search to this subdirectory."}, + "glob": {"type": "string", "description": "Limit to files matching this glob, e.g. '*.py'."}}, + ["pattern"]), + fn("edit_lines", + "Replace an inclusive 1-based line range with new text. Line numbers " + "refer to the file as it is now, so re-read it after any edit that " + "changed the number of lines.", + {"path": {"type": "string", "description": "File path relative to the repository root."}, + "start_line": {"type": "integer", "description": "First line to replace, 1-based, inclusive."}, + "end_line": {"type": "integer", "description": "Last line to replace, 1-based, inclusive."}, + "new_text": {"type": "string", "description": "Replacement text. Use an empty string to delete the range."}}, + ["path", "start_line", "end_line", "new_text"]), + fn("edit_replace", + "Replace an exact snippet of text. The snippet must occur exactly " + "once in the file unless replace_all is set.", + {"path": {"type": "string", "description": "File path relative to the repository root."}, + "old_text": {"type": "string", "description": "Exact text to find, including indentation."}, + "new_text": {"type": "string", "description": "Replacement text."}, + "replace_all": {"type": "boolean", "description": "Replace every occurrence instead of requiring exactly one."}}, + ["path", "old_text", "new_text"]), + fn("write_file", + "Write a whole file, creating or overwriting it. Prefer the edit " + "tools for changes to existing files.", + {"path": {"type": "string", "description": "File path relative to the repository root."}, + "content": {"type": "string", "description": "Full new file contents."}}, + ["path", "content"]), + fn("lint", + "Run the language's linter and type checker over the repository and " + "return the diagnostics. This is the only feedback available; the " + "test suite cannot be run.", + {"path": {"type": "string", "description": "Limit to this file or directory."}}), + fn("finish", + "Declare the task complete and end the session. This is the only " + "way to end it; call this once the change is made.", + {"summary": {"type": "string", "description": "Brief description of the change made."}}), + ] + + +class ToolBox: + """Executes tool calls against one workspace. Returns plain text results. + + Failures are reported as ordinary text rather than raised, because how a + model recovers from a rejected edit is part of what is being measured. + """ + + def __init__(self, ws: Workspace, linter=None): + self.ws = ws + self.linter = linter + self.calls = 0 + self.errors = 0 + self.edits = 0 + self.finished = False + self.finish_summary: Optional[str] = None + self.per_tool: Dict[str, int] = {} + + def dispatch(self, name: str, args: Dict[str, Any]) -> str: + self.calls += 1 + self.per_tool[name] = self.per_tool.get(name, 0) + 1 + handler = getattr(self, f"_t_{name}", None) + if handler is None: + result = f"Error: unknown tool {name!r}." + else: + try: + result = handler(args) + except PathEscape as e: + result = f"Error: {e}" + except KeyError as e: + result = f"Error: missing required argument {e}." + except Exception as e: + result = f"Error: {type(e).__name__}: {e}" + if result.startswith("Error:"): + self.errors += 1 + return _clip(result) + + def _t_list_files(self, a): + base = self.ws.resolve(a.get("path") or ".") + if not base.exists(): + return f"Error: {a.get('path')!r} does not exist." + paths = [p for p in self.ws.files() if p == base or base in p.parents] + if not paths: + return "(no files)" + return "\n".join(f"{self.ws.rel(p)}\t{p.stat().st_size} bytes" for p in paths) + + def _t_read_file(self, a): + path = self.ws.resolve(a["path"]) + if not path.is_file(): + return f"Error: {a['path']!r} is not a file." + lines = path.read_text().splitlines() + start = max(1, int(a.get("start_line") or 1)) + end = int(a.get("end_line") or len(lines)) + end = min(end, len(lines)) + if start > len(lines): + return f"Error: {a['path']!r} has only {len(lines)} lines." + window = lines[start - 1:end] + note = "" + if len(window) > MAX_READ_LINES: + window = window[:MAX_READ_LINES] + note = (f"\n... [showing {MAX_READ_LINES} of {end - start + 1} requested " + f"lines; re-read with start_line/end_line for the rest]") + header = f"{a['path']} ({len(lines)} lines total)\n" + return header + _numbered(window, start) + note + + def _t_search(self, a): + try: + rx = re.compile(a["pattern"]) + except re.error as e: + return f"Error: bad regular expression: {e}" + base = self.ws.resolve(a.get("path") or ".") + glob = a.get("glob") + hits, scanned = [], 0 + for p in self.ws.files(): + if not (p == base or base in p.parents): + continue + if glob and not p.match(glob): + continue + try: + text = p.read_text() + except (UnicodeDecodeError, OSError): + continue + scanned += 1 + for i, line in enumerate(text.splitlines(), 1): + if rx.search(line): + hits.append(f"{self.ws.rel(p)}:{i}:{line.strip()[:200]}") + if len(hits) >= MAX_SEARCH_HITS: + return ("\n".join(hits) + + f"\n... [stopped at {MAX_SEARCH_HITS} matches; narrow the pattern]") + if not hits: + return f"No matches for {a['pattern']!r} in {scanned} file(s)." + return "\n".join(hits) + + def _t_edit_lines(self, a): + path = self.ws.resolve(a["path"]) + if not path.is_file(): + return f"Error: {a['path']!r} is not a file." + lines = path.read_text().splitlines() + start, end = int(a["start_line"]), int(a["end_line"]) + if start < 1 or start > len(lines): + return (f"Error: start_line {start} out of range; " + f"{a['path']!r} has {len(lines)} lines.") + if end < start or end > len(lines): + return (f"Error: end_line {end} out of range; must be between " + f"{start} and {len(lines)}.") + new = str(a["new_text"]).splitlines() + path.write_text("\n".join(lines[:start - 1] + new + lines[end:]) + "\n") + self.edits += 1 + delta = len(new) - (end - start + 1) + return (f"Replaced lines {start}-{end} of {a['path']} " + f"({end - start + 1} -> {len(new)} lines, {delta:+d}). " + f"Later line numbers have shifted." if delta else + f"Replaced lines {start}-{end} of {a['path']}.") + + def _t_edit_replace(self, a): + path = self.ws.resolve(a["path"]) + if not path.is_file(): + return f"Error: {a['path']!r} is not a file." + text = path.read_text() + old, new = str(a["old_text"]), str(a["new_text"]) + if not old: + return "Error: old_text must not be empty." + n = text.count(old) + if n == 0: + return (f"Error: old_text not found in {a['path']}. It must match " + f"exactly, including indentation.") + if n > 1 and not a.get("replace_all"): + return (f"Error: old_text occurs {n} times in {a['path']}. Include " + f"more surrounding context to make it unique, or set " + f"replace_all.") + path.write_text(text.replace(old, new)) + self.edits += 1 + return f"Replaced {n} occurrence(s) in {a['path']}." + + def _t_write_file(self, a): + path = self.ws.resolve(a["path"]) + path.parent.mkdir(parents=True, exist_ok=True) + existed = path.is_file() + path.write_text(str(a["content"])) + self.edits += 1 + return f"{'Overwrote' if existed else 'Created'} {a['path']}." + + def _t_lint(self, a): + if self.linter is None: + return "Error: no linter is configured for this task." + target = a.get("path") + if target: + self.ws.resolve(target) + return self.linter(target) + + def _t_finish(self, a): + self.finished = True + self.finish_summary = a.get("summary") + return "Task marked complete." + + +PY_TEST_RUNNER = r''' +import json, os, random, sys, unittest +sys.path.insert(0, os.getcwd()) +random.seed(0) + +class Collect(unittest.TestResult): + def __init__(self): + super().__init__() + self.outcomes = {} + def addSuccess(self, t): self.outcomes[t.id()] = "pass" + def addFailure(self, t, e): self.outcomes[t.id()] = "fail" + def addError(self, t, e): self.outcomes[t.id()] = "error" + def addSkip(self, t, r): self.outcomes[t.id()] = "skip" + def addExpectedFailure(self, t, e): self.outcomes[t.id()] = "pass" + def addUnexpectedSuccess(self, t): self.outcomes[t.id()] = "fail" + +def flatten(s): + for t in s: + if isinstance(t, unittest.TestSuite): + yield from flatten(t) + else: + yield t + +out = {"tests": {}} +try: + suite = unittest.TestLoader().discover(os.environ.get("TEST_DIR", "tests"), + top_level_dir=".") + res = Collect() + for t in flatten(suite): + tid = t.id() + try: + t.run(res) + except Exception: + pass + res.outcomes.setdefault(tid, "error") + out["tests"] = res.outcomes +except Exception as e: + out["error"] = f"{type(e).__name__}: {e}" + +print("###RESULT###") +print(json.dumps(out)) +''' + + +def _node_roots() -> List[Path]: + """Directories that must stay visible for node to start under bwrap.""" + node = shutil.which("node") + if not node: + return [] + real = Path(node).resolve() + return [Path(node).parent.parent, real.parent.parent] + + +class Runner: + """Runs the linter and the hidden tests for one language, in the sandbox.""" + + def __init__(self, sandbox, lang: LangSpec, timeout: float = 90.0): + self.sandbox = sandbox + self.lang = lang + self.timeout = timeout + + def _binds(self) -> List[Path]: + return _node_roots() if self.lang.name == "typescript" else [] + + def _env(self) -> Dict[str, str]: + if self.lang.name != "typescript": + return {} + node = shutil.which("node") + return {"PATH": f"{Path(node).parent}:/usr/bin:/bin"} if node else {} + + def lint(self, workdir: Path, target: Optional[str] = None) -> str: + if self.lang.name == "python": + return self._lint_python(workdir, target) + return self._lint_typescript(workdir, target) + + def _lint_python(self, workdir: Path, target: Optional[str]) -> str: + venv = self.sandbox.venv_dir + tgt = target or "." + chunks = [] + r = self.sandbox.run_argv( + [str(venv / "bin" / "ruff"), "check", "--no-cache", + "--output-format", "concise", tgt], + workdir, timeout=self.timeout) + text = (r.stdout or r.stderr).strip() + if text and "All checks passed" not in text: + chunks.append(text) + r = self.sandbox.run_argv( + [str(venv / "bin" / "mypy"), "--no-color-output", "--no-error-summary", + "--cache-dir", "/dev/null", "--ignore-missing-imports", tgt], + workdir, timeout=self.timeout) + text = (r.stdout or r.stderr).strip() + if text and not text.startswith("Success:"): + chunks.append(text) + return "\n".join(chunks) if chunks else "No problems found." + + def _lint_typescript(self, workdir: Path, target: Optional[str]) -> str: + tsc = self.sandbox.venv_dir / "node" / "node_modules" / "typescript" / "bin" / "tsc" + files = [str(p.relative_to(workdir)) for p in sorted(workdir.rglob("*.ts")) + if "node_modules" not in p.parts] + if target: + t = (workdir / target).resolve() + files = [f for f in files if (workdir / f).resolve() == t + or t in (workdir / f).resolve().parents] + if not files: + return "No TypeScript files to check." + r = self.sandbox.run_argv( + ["node", str(tsc), "--noEmit", "--strict", "--target", "es2022", + "--module", "esnext", "--moduleResolution", "bundler", + "--allowImportingTsExtensions", *files], + workdir, timeout=self.timeout, env=self._env(), ro_binds=self._binds()) + out = (r.stdout or "") + (r.stderr or "") + return out.strip() or "No problems found." + + def test(self, workdir: Path) -> Dict[str, Any]: + if self.lang.name == "python": + return self._test_python(workdir) + return self._test_typescript(workdir) + + def _test_python(self, workdir: Path) -> Dict[str, Any]: + runner = workdir / "__run_tests.py" + runner.write_text(PY_TEST_RUNNER) + r = self.sandbox.run_argv( + [str(self.sandbox.python), "-I", "-B", str(runner)], + workdir, timeout=self.timeout, env={"TEST_DIR": "tests"}) + return self._parse_json_result(r) + + def _parse_json_result(self, r) -> Dict[str, Any]: + if r.status == "timeout": + return {"tests": {}, "error": "timeout"} + marker = "###RESULT###" + if marker not in (r.stdout or ""): + return {"tests": {}, + "error": f"no result: {(r.stderr or r.stdout or '')[-400:]}"} + try: + return json.loads(r.stdout.split(marker, 1)[1].strip()) + except Exception as e: + return {"tests": {}, "error": f"unparseable result: {e}"} + + def _test_typescript(self, workdir: Path) -> Dict[str, Any]: + tests = sorted(p for p in (workdir / "tests").rglob("*.ts")) \ + if (workdir / "tests").is_dir() else [] + if not tests: + return {"tests": {}, "error": "no test files"} + r = self.sandbox.run_argv( + ["node", "--test", "--experimental-strip-types", + "--test-reporter=tap", + *[str(p.relative_to(workdir)) for p in tests]], + workdir, timeout=self.timeout, env=self._env(), ro_binds=self._binds()) + return self._parse_tap(r) + + @staticmethod + def _parse_tap(r) -> Dict[str, Any]: + if r.status == "timeout": + return {"tests": {}, "error": "timeout"} + text = (r.stdout or "") + "\n" + (r.stderr or "") + outcomes: Dict[str, str] = {} + for line in text.splitlines(): + m = re.match(r"\s*(not )?ok\s+\d+\s*-\s*(.+?)\s*$", line) + if not m: + continue + name = m.group(2).strip() + if name.endswith(" # SKIP") or " # SKIP" in name: + outcomes[name.split(" # ")[0]] = "skip" + continue + verdict = "fail" if m.group(1) else "pass" + if outcomes.get(name) != "fail": + outcomes[name] = verdict + if not outcomes: + return {"tests": {}, + "error": f"no TAP output: {text.strip()[-400:]}"} + return {"tests": outcomes} + + +SYSTEM_PROMPT = """You are an expert {lang} engineer working in an existing repository. + +Resolve the user's request by editing files with the tools provided. + +How this session works: +- You are working autonomously. There is no human watching; nobody will answer + questions, approve a plan, or read progress reports. +- Every reply you send must contain at least one tool call until the task is + done. A reply that contains only text does nothing: no work happens and the + turn is wasted. Do not stop to describe what you are about to do; do it. +- The session ends only when you call `finish`. Call it once the change is + made, and not before. Only the files as you leave them are evaluated. + +Important constraints: +- You cannot run the code, the tests, or any shell command. The only feedback + available is the `lint` tool, which reports syntax and type problems. +- The repository already has a test suite that will be run against your work + after you finish, but you cannot see it or run it. Do not create test files. +- Read enough of the code to understand it before editing. A change that only + makes the symptom go away will usually fail the tests. +- Make the smallest correct change. Do not reformat or refactor unrelated code. + +Keep calling tools until the change is complete, then call `finish`.""" + + +@dataclass +class AgenticTask: + task_id: str + lang: str + category: str + difficulty: int + instruction: str + files: Dict[str, str] + tests: Dict[str, str] + gold: Dict[str, str] = field(default_factory=dict) + fail_to_pass: List[str] = field(default_factory=list) + pass_to_pass: List[str] = field(default_factory=list) + + @classmethod + def from_record(cls, rec: Dict[str, Any]) -> "AgenticTask": + def as_map(v): + return v if isinstance(v, dict) else json.loads(v or "{}") + def as_list(v): + return v if isinstance(v, list) else json.loads(v or "[]") + return cls( + task_id=rec["task_id"], lang=rec["lang"], category=rec["category"], + difficulty=int(rec.get("difficulty", 3)), + instruction=rec["instruction"], + files=as_map(rec["files"]), tests=as_map(rec["tests"]), + gold=as_map(rec.get("gold")), + fail_to_pass=as_list(rec.get("fail_to_pass")), + pass_to_pass=as_list(rec.get("pass_to_pass")), + ) + + @property + def spec(self) -> LangSpec: + return LANGS[self.lang] + + +def materialise(files: Dict[str, str], dest: Path) -> Path: + """Write a file map out as a real directory tree.""" + dest.mkdir(parents=True, exist_ok=True) + for rel, content in files.items(): + p = dest / rel + p.parent.mkdir(parents=True, exist_ok=True) + p.write_text(content) + return dest + + +def repo_overview(files: Dict[str, str]) -> str: + """A compact tree, so a run is not lost merely to not finding the files.""" + lines = [] + for rel in sorted(files): + n = files[rel].count("\n") + 1 + lines.append(f" {rel} ({n} lines)") + return "\n".join(lines) + + +def user_prompt(task: AgenticTask) -> str: + return (f"Repository files:\n{repo_overview(task.files)}\n\n" + f"Task:\n{task.instruction}") + + +@dataclass +class EpisodeResult: + stop_reason: str = "unknown" + turns: int = 0 + tool_calls: int = 0 + tool_errors: int = 0 + edits: int = 0 + escape_attempts: int = 0 + finished: bool = False + bad_tool_json: int = 0 + nudges: int = 0 + prompt_tokens: int = 0 + completion_tokens: int = 0 + peak_context: int = 0 + truncated_turns: int = 0 + per_tool: Dict[str, int] = field(default_factory=dict) + error: Optional[str] = None + + +NUDGE = ("Your last reply contained no tool call, so nothing happened. There is " + "no human in this session to respond to text. If your change is " + "complete, call `finish`. Otherwise continue working by calling the " + "tools; do not reply with text alone.") + + +def run_episode(task: AgenticTask, toolbox: ToolBox, chat, + max_turns: int = 50, + context_limit: Optional[int] = None, + max_nudges: int = 3) -> Tuple[EpisodeResult, List[Dict]]: + """Drive one multi-turn tool-calling episode. + + `chat(messages, tools) -> response dict` is supplied by the caller so this + module stays free of any HTTP concerns. + """ + tools = tool_schemas() + messages: List[Dict[str, Any]] = [ + {"role": "system", "content": SYSTEM_PROMPT.format(lang=task.spec.name)}, + {"role": "user", "content": user_prompt(task)}, + ] + res = EpisodeResult() + + for turn in range(max_turns): + res.turns = turn + 1 + try: + reply = chat(messages, tools) + except Exception as e: + res.stop_reason, res.error = "request_failed", f"{type(e).__name__}: {e}" + break + + usage = reply.get("usage") or {} + pt = int(usage.get("prompt_tokens") or 0) + ct = int(usage.get("completion_tokens") or 0) + res.prompt_tokens += pt + res.completion_tokens += ct + res.peak_context = max(res.peak_context, pt + ct) + + choices = reply.get("choices") or [] + if not choices: + res.stop_reason, res.error = "no_choices", json.dumps(reply)[:300] + break + msg = choices[0].get("message") or {} + if choices[0].get("finish_reason") == "length": + res.truncated_turns += 1 + calls = msg.get("tool_calls") or [] + + reasoning = msg.get("reasoning_content") + messages.append({ + "role": "assistant", + "content": msg.get("content") or "", + **({"reasoning_content": reasoning} if reasoning else {}), + **({"tool_calls": calls} if calls else {}), + }) + + if not calls: + if toolbox.finished: + res.stop_reason = "finished" + break + if res.nudges >= max_nudges: + res.stop_reason = "no_tool_calls" + break + res.nudges += 1 + messages.append({"role": "user", "content": NUDGE}) + continue + + for call in calls: + fn = call.get("function") or {} + name = fn.get("name") or "" + raw = fn.get("arguments") + if isinstance(raw, dict): + args = raw + else: + try: + args = json.loads(raw or "{}") + except (json.JSONDecodeError, TypeError): + res.bad_tool_json += 1 + args = None + output = (toolbox.dispatch(name, args) if args is not None else + f"Error: arguments for {name!r} were not valid JSON.") + messages.append({"role": "tool", + "tool_call_id": call.get("id") or f"call_{res.tool_calls}", + "content": output}) + + if toolbox.finished: + res.stop_reason = "finished" + break + if context_limit and res.peak_context > context_limit: + res.stop_reason = "context_limit" + break + else: + res.stop_reason = "max_turns" + + res.tool_calls = toolbox.calls + res.tool_errors = toolbox.errors + res.edits = toolbox.edits + res.escape_attempts = toolbox.ws.escape_attempts + res.finished = toolbox.finished + res.per_tool = dict(toolbox.per_tool) + return res, messages + + +def run_tests_against(files: Dict[str, str], task: AgenticTask, runner: Runner, + workroot: Path, label: str) -> Dict[str, str]: + """Materialise a tree, drop the hidden tests in, and run them. + + The tests are only ever written into this throwaway copy, never into the + tree the agent worked in, so there is no window in which they could have + been read or edited. + """ + dest = workroot / f"grade-{label}" + shutil.rmtree(dest, ignore_errors=True) + materialise(files, dest) + materialise(task.tests, dest) + return runner.test(dest).get("tests", {}) + + +def score(task: AgenticTask, outcomes: Dict[str, str]) -> Dict[str, Any]: + """Resolved means every target test passes and nothing previously passing broke.""" + def passing(tid): + return outcomes.get(tid) == "pass" + + f2p_ok = [t for t in task.fail_to_pass if passing(t)] + p2p_ok = [t for t in task.pass_to_pass if passing(t)] + regressions = [t for t in task.pass_to_pass if not passing(t)] + resolved = (len(f2p_ok) == len(task.fail_to_pass) + and not regressions and bool(task.fail_to_pass)) + return { + "resolved": resolved, + "f2p_passed": len(f2p_ok), "f2p_total": len(task.fail_to_pass), + "p2p_passed": len(p2p_ok), "p2p_total": len(task.pass_to_pass), + "regressions": regressions[:10], + "n_regressions": len(regressions), + "partial": (len(f2p_ok) / len(task.fail_to_pass)) if task.fail_to_pass else 0.0, + } + + +def make_sandbox(lang_name: str, sandbox_cls, cache_root=None, base_python=None): + """A sandbox carrying only the toolchain for `lang_name`. + + Keyed per language rather than per suite: running the Python tasks must + never provision node, and vice versa. + """ + lang = LANGS[lang_name] + return sandbox_cls( + name=f"agentic-{lang_name}", + packages=list(lang.packages), + provision=list(lang.provision), + env=dict(lang.env), + address_space_limit=lang.address_space_limit, + cache_root=cache_root, + base_python=base_python, + ) + + +def run_task(task: AgenticTask, chat, sandbox, workroot: Optional[Path] = None, + max_turns: int = 50, context_limit: Optional[int] = None, + test_timeout: float = 90.0) -> Dict[str, Any]: + """One full attempt: fresh workspace, agent episode, then hidden tests.""" + root = Path(tempfile.mkdtemp(prefix=f"agentic-{task.task_id}-", + dir=str(workroot) if workroot else None)) + try: + ws_root = root / "repo" + materialise(task.files, ws_root) + ws = Workspace(ws_root) + runner = Runner(sandbox, task.spec, timeout=test_timeout) + toolbox = ToolBox(ws, linter=lambda t: runner.lint(ws_root, t)) + + episode, messages = run_episode(task, toolbox, chat, + max_turns=max_turns, + context_limit=context_limit) + final = ws.snapshot() + changed = sorted(k for k in final + if final[k] != task.files.get(k)) + \ + sorted(k for k in task.files if k not in final) + + outcomes = run_tests_against(final, task, runner, root, "final") + result = score(task, outcomes) + result.update({ + "task_id": task.task_id, "lang": task.lang, + "category": task.category, "difficulty": task.difficulty, + "changed_files": changed, + "episode": {k: v for k, v in vars(episode).items()}, + "messages": messages, + }) + return result + finally: + shutil.rmtree(root, ignore_errors=True) + + +TRANSCRIPT_CSS = """ +body { font-family: system-ui, sans-serif; margin: 0; padding: 16px; background: #fff; color: #222; max-width: 1100px; } +h1 { font-size: 16px; margin: 0 0 4px; } +.meta { font-size: 13px; color: #555; font-family: 'SF Mono', 'Menlo', 'Consolas', monospace; margin-bottom: 12px; white-space: pre-wrap; } +.msg { border: 1px solid #e1e4e8; border-left-width: 4px; margin: 8px 0; padding: 6px 10px; background: #fafbfc; } +.msg .role { font-size: 12px; font-weight: 600; color: #555; margin-bottom: 4px; } +.system { border-left-color: #888; } +.user { border-left-color: #0969da; } +.nudge { border-left-color: #9a6700; } +.assistant { border-left-color: #1a7f37; background: #fff; } +.tool { border-left-color: #8250df; } +.tool.err { border-left-color: #cf222e; } +pre { font-family: 'SF Mono', 'Menlo', 'Consolas', monospace; font-size: 12px; background: #fff; border: 1px solid #e1e4e8; padding: 6px 8px; margin: 4px 0; white-space: pre-wrap; word-wrap: break-word; } +.reasoning pre { color: #57606a; background: #f6f8fa; } +.call { font-size: 12px; font-weight: 600; color: #8250df; margin-top: 6px; } +details > summary { cursor: pointer; font-size: 12px; color: #555; } +.empty { font-size: 12px; color: #888; font-style: italic; } +""" + + +def _pre(text: str) -> str: + return f"<pre>{html.escape(text)}</pre>" + + +def _render_call(call: Dict[str, Any]) -> str: + fn = call.get("function") or {} + raw = fn.get("arguments") + try: + args = raw if isinstance(raw, dict) else json.loads(raw or "{}") + shown = json.dumps(args, indent=2, ensure_ascii=False) + except (json.JSONDecodeError, TypeError): + shown = f"(invalid JSON)\n{raw}" + return (f'<div class="call">→ {html.escape(fn.get("name") or "?")} ' + f'<span style="font-weight:400;color:#888">{html.escape(call.get("id") or "")}</span></div>' + + _pre(shown)) + + +def render_transcript_html(messages: List[Dict[str, Any]], title: str, + meta: str = "") -> str: + """One page per episode: every turn, with reasoning, tool calls and results.""" + names = {} + for m in messages: + for c in m.get("tool_calls") or []: + names[c.get("id")] = (c.get("function") or {}).get("name") or "?" + + parts = [] + turn = 0 + for m in messages: + role = m.get("role") or "?" + content = m.get("content") or "" + if role == "assistant": + turn += 1 + body = "" + if m.get("reasoning_content"): + body += ('<details class="reasoning" open><summary>reasoning ' + f'({len(m["reasoning_content"])} chars)</summary>' + + _pre(m["reasoning_content"]) + "</details>") + body += _pre(content) if content.strip() else "" + body += "".join(_render_call(c) for c in m.get("tool_calls") or []) + if not body: + body = '<div class="empty">(empty reply)</div>' + parts.append(f'<div class="msg assistant"><div class="role">assistant ' + f'· turn {turn}</div>{body}</div>') + elif role == "tool": + name = names.get(m.get("tool_call_id"), "?") + err = " err" if content.startswith("Error") else "" + parts.append(f'<div class="msg tool{err}"><div class="role">tool result ' + f'· {html.escape(name)}</div>{_pre(content)}</div>') + elif role == "system": + parts.append('<div class="msg system"><details><summary>system prompt' + f'</summary>{_pre(content)}</details></div>') + else: + cls = "nudge" if content == NUDGE else role + label = "user (nudge)" if content == NUDGE else role + parts.append(f'<div class="msg {html.escape(cls)}"><div class="role">' + f'{html.escape(label)}</div>{_pre(content)}</div>') + + return (f'<!DOCTYPE html>\n<html>\n<head>\n<meta charset="UTF-8">\n' + f'<title>{html.escape(title)}\n\n' + f'\n\n

{html.escape(title)}

\n' + f'
{html.escape(meta)}
\n' + + "\n".join(parts) + "\n\n\n") + + +def write_transcript(messages: List[Dict[str, Any]], dest: Path, title: str, + meta: str = "") -> Path: + """Write `.json` (the raw message history) and `.html`.""" + dest.parent.mkdir(parents=True, exist_ok=True) + json_path = dest.with_name(dest.name + ".json") + with open(json_path, "w") as f: + json.dump(messages, f, indent=2, ensure_ascii=False) + with open(dest.with_name(dest.name + ".html"), "w") as f: + f.write(render_transcript_html(messages, title, meta)) + return json_path diff --git a/examples/llama-eval/eval_sandbox.py b/examples/llama-eval/eval_sandbox.py new file mode 100644 index 000000000000..b13bc9d7101b --- /dev/null +++ b/examples/llama-eval/eval_sandbox.py @@ -0,0 +1,488 @@ +#!/usr/bin/env python3 +"""Lightweight sandboxed execution for code-generation evals (HumanEval, ClassEval). + +Replaces the usual Docker-per-suite setup with a cached venv plus whatever +process isolation the host can give us without root: + + tier 1 bubblewrap read-only root, tmpfs /tmp and $HOME, no network + tier 2 unshare -rn no network (home still visible) + tier 3 rlimits only last resort, still capped on cpu/memory/procs/files + +Every tier also applies rlimits and runs the candidate program in a throwaway +working directory as its own process group, so a runaway solution is killed +along with anything it spawned. +""" + +import json +import os +import re +import resource +import shutil +import signal +import subprocess +import sys +import tempfile +import time +import venv +from dataclasses import dataclass +from pathlib import Path +from typing import Dict, List, Optional, Sequence + +DEFAULT_CACHE_ROOT = Path( + os.environ.get("LLAMA_EVAL_CACHE", Path.home() / ".cache" / "llama-eval") +) + +LIMIT_AS_BYTES = 4 * 1024 * 1024 * 1024 +LIMIT_CPU_SECONDS_SLACK = 5 +LIMIT_NPROC = 256 +LIMIT_FSIZE_BYTES = 64 * 1024 * 1024 + + +@dataclass +class ExecResult: + passed: bool + status: str + stdout: str = "" + stderr: str = "" + returncode: Optional[int] = None + duration: float = 0.0 + + def summary(self, max_chars: int = 400) -> str: + """Short human-readable reason, for grader logs.""" + if self.passed: + return "ok" + if self.status == "timeout": + return "timeout" + tail = (self.stderr or self.stdout).strip() + if not tail: + return f"{self.status} (rc={self.returncode})" + lines = [ln for ln in tail.splitlines() if ln.strip()] + reason = lines[-1] if lines else tail + return reason[:max_chars] + + +def resolve_python(spec: Optional[str]) -> Optional[str]: + """Turn '3.13' or a path into a usable interpreter, or None if unavailable. + + Suites can need an older interpreter than the one running this tool, because + a dependency has no wheel (or no working source build) for the newest + CPython. Accepts an explicit path, a bare version, or an executable name. + """ + if not spec: + return None + + candidate = Path(spec).expanduser() + if candidate.exists() and candidate.is_file(): + return str(candidate) + + uv = shutil.which("uv") + if uv and re.fullmatch(r"\d+\.\d+(\.\d+)?", spec): + try: + r = subprocess.run([uv, "python", "find", spec], + capture_output=True, text=True, timeout=120) + path = r.stdout.strip() + if r.returncode == 0 and path and Path(path).exists(): + return path + except Exception: + pass + + return shutil.which(spec) or shutil.which(f"python{spec}") + + +def _detect_isolation(probe_python: Optional[str] = None, + ro_binds: Sequence[Path] = ()) -> str: + """Pick the strongest isolation tier this host supports, once. + + The probe must run the *same* interpreter the suite will, with the same + binds. Probing a bare sys.executable silently downgrades the tier whenever + this tool is itself run from a venv under $HOME -- which is the usual case, + since it needs `datasets`. bwrap tmpfs-mounts the home directory, the + interpreter disappears, the probe fails, and the sandbox falls back to a + tier that does not hide $HOME at all. Nothing about the results looks wrong + when that happens, so it has to be got right here. + """ + py = probe_python or sys.executable + probe = "import sys; sys.exit(0)" + + if shutil.which("bwrap"): + try: + r = subprocess.run( + _bwrap_argv(Path.cwd(), [py, "-I", "-c", probe], ro_binds=ro_binds), + capture_output=True, timeout=20, + ) + if r.returncode == 0: + return "bwrap" + except Exception: + pass + + if shutil.which("unshare"): + for tier, argv in ( + ("unshare", ["unshare", "--user", "--map-current-user", "--net"]), + ("unshare-root", ["unshare", "-rn"]), + ): + try: + r = subprocess.run( + [*argv, py, "-I", "-c", probe], + capture_output=True, timeout=20, + ) + if r.returncode == 0: + return tier + except Exception: + continue + + return "rlimit" + + +UNSHARE_ARGV = { + "unshare": ["unshare", "--user", "--map-current-user", "--net"], + "unshare-root": ["unshare", "-rn"], +} + + +def _under(path: Path, parent: str) -> bool: + return bool(parent) and (str(path) == parent + or str(path).startswith(parent.rstrip("/") + os.sep)) + + +def _bwrap_argv(workdir: Path, inner: Sequence[str], + ro_binds: Sequence[Path] = ()) -> List[str]: + home = os.path.expanduser("~") + argv = [ + "bwrap", + "--ro-bind", "/", "/", + "--dev", "/dev", + "--proc", "/proc", + "--tmpfs", "/tmp", + ] + if home and home != "/": + argv += ["--tmpfs", home] + for path in ro_binds: + if _under(path, home): + argv += ["--ro-bind", str(path), str(path)] + argv += [ + "--bind", str(workdir), str(workdir), + "--chdir", str(workdir), + "--unshare-all", + "--die-with-parent", + "--new-session", + "--", + ] + return argv + list(inner) + + +def _nproc_ceiling() -> int: + """A process cap that bounds a fork bomb without tripping on existing load. + + RLIMIT_NPROC is enforced per real UID across the whole system, not per + process tree, so it has to sit above whatever the user is already running. + """ + try: + current = len(os.listdir("/proc")) + except OSError: + current = 512 + return max(current * 2, 1024) + + +def _apply_rlimits(timeout: float, with_nproc: bool, + as_bytes: Optional[int] = LIMIT_AS_BYTES): + def _preexec(): + os.setsid() + cpu = int(timeout) + LIMIT_CPU_SECONDS_SLACK + limits = [ + (resource.RLIMIT_CPU, (cpu, cpu)), + (resource.RLIMIT_FSIZE, (LIMIT_FSIZE_BYTES, LIMIT_FSIZE_BYTES)), + (resource.RLIMIT_CORE, (0, 0)), + ] + if as_bytes: + limits.append((resource.RLIMIT_AS, (as_bytes, as_bytes))) + if with_nproc: + ceiling = _nproc_ceiling() + limits.append((resource.RLIMIT_NPROC, (ceiling, ceiling))) + for res, lim in limits: + try: + resource.setrlimit(res, lim) + except (ValueError, OSError): + pass + return _preexec + + +class Sandbox: + """A cached venv plus an isolated runner for untrusted candidate programs.""" + + def __init__( + self, + name: str, + packages: Optional[Sequence[str]] = None, + cache_root: Optional[Path] = None, + base_python: Optional[str] = None, + isolation: Optional[str] = None, + provision: Optional[Sequence[str]] = None, + env: Optional[Dict[str, str]] = None, + address_space_limit: Optional[int] = LIMIT_AS_BYTES, + ): + self.name = name + self.packages = sorted(set(packages or [])) + self.provision = list(provision or []) + self.env = dict(env or {}) + # None drops the RLIMIT_AS cap entirely -- see _apply_rlimits + self.address_space_limit = address_space_limit + self.cache_root = Path(cache_root or DEFAULT_CACHE_ROOT) + self.base_python = base_python or sys.executable + self.venv_dir = self.cache_root / f"{name}-venv" + self._python: Optional[Path] = None + self._isolation = isolation + self._base_prefix: List[Path] = [] + + @property + def python(self) -> Path: + if self._python is None: + raise RuntimeError("Sandbox.ensure() must be called first") + return self._python + + @property + def isolation(self) -> str: + if self._isolation is None: + if self._python: + py = str(self._python) + roots = [self.venv_dir, *(self._base_prefix or [])] + else: + py = sys.executable + roots = self._detect_base_prefix(Path(py)) + self._isolation = _detect_isolation(py, roots) + return self._isolation + + def _stamp_path(self) -> Path: + return self.venv_dir / ".llama-eval-stamp.json" + + def _stamp_matches(self) -> bool: + try: + stamp = json.loads(self._stamp_path().read_text()) + except Exception: + return False + return ( + stamp.get("packages") == self.packages + and stamp.get("py") == self._base_version() + and stamp.get("provision") == self.provision + ) + + def _resolved_env(self) -> Dict[str, str]: + return {k: v.replace("{venv}", str(self.venv_dir)) for k, v in self.env.items()} + + def _base_version(self) -> str: + r = subprocess.run( + [self.base_python, "-c", + "import sys;print('.'.join(map(str,sys.version_info[:3])))"], + capture_output=True, text=True, + ) + return r.stdout.strip() + + def ensure(self, force: bool = False, quiet: bool = False) -> Path: + """Create/refresh the venv. Idempotent and cheap when already valid.""" + py = self.venv_dir / "bin" / "python" + if force and self.venv_dir.exists(): + shutil.rmtree(self.venv_dir) + + if py.exists() and self._stamp_matches(): + self._python = py + self._base_prefix = self._detect_base_prefix(py) + return py + + if not quiet: + pkgs = ", ".join(self.packages) if self.packages else "stdlib only" + print(f"[sandbox] provisioning venv {self.venv_dir} ({pkgs})") + + self.cache_root.mkdir(parents=True, exist_ok=True) + if self.venv_dir.exists(): + shutil.rmtree(self.venv_dir) + + uv = shutil.which("uv") + if uv: + subprocess.run( + [uv, "venv", "--python", self.base_python, str(self.venv_dir)], + check=True, capture_output=True, + ) + elif Path(self.base_python).resolve() == Path(sys.executable).resolve(): + venv.EnvBuilder(with_pip=bool(self.packages), clear=True).create(self.venv_dir) + else: + subprocess.run( + [self.base_python, "-m", "venv", str(self.venv_dir)], + check=True, capture_output=True, + ) + + if self.packages: + if uv: + cmd = [uv, "pip", "install", "--python", str(py), *self.packages] + else: + cmd = [str(py), "-m", "pip", "install", "--quiet", + "--disable-pip-version-check", *self.packages] + r = subprocess.run(cmd, capture_output=True, text=True) + if r.returncode != 0: + raise RuntimeError( + f"failed to install {len(self.packages)} package(s) into " + f"{self.venv_dir}:\n{(r.stderr or r.stdout)[-3000:]}" + ) + + for i, snippet in enumerate(self.provision, 1): + if not quiet: + print(f"[sandbox] provisioning step {i}/{len(self.provision)}") + prov_env = dict(os.environ) + prov_env["SANDBOX_VENV"] = str(self.venv_dir) + prov_env.update(self._resolved_env()) + r = subprocess.run([str(py), "-c", snippet], env=prov_env, + capture_output=True, text=True, timeout=1800) + if r.returncode != 0: + raise RuntimeError( + f"provisioning step {i} failed:\n{(r.stderr or r.stdout)[-3000:]}" + ) + + self._stamp_path().write_text(json.dumps({ + "packages": self.packages, + "py": self._base_version(), + "provision": self.provision, + })) + self._python = py + self._base_prefix = self._detect_base_prefix(py) + if not quiet: + print(f"[sandbox] ready ({self.isolation} isolation)") + if self.isolation == "unshare-root": + print("Warning: this host's unshare cannot keep the caller's uid, so " + "candidate code runs as root inside the namespace. Tests that " + "assert a permission denial will not see one. Install " + "bubblewrap (bwrap) for correct results.") + return py + + @staticmethod + def _detect_base_prefix(py: Path) -> List[Path]: + """Every directory that must stay visible for the venv to start. + + A venv is only symlinks into its base interpreter, so the whole install + tree has to survive the tmpfs that hides $HOME -- and binding just the + resolved tree is not enough. Version-managed interpreters (uv, pyenv) + are commonly reached through an unversioned alias symlink + (cpython-3.13-... -> cpython-3.13.14-...), and startup resolves through + the alias path, so both spellings need to be mounted. Walk the chain + and keep every install root it passes through. + """ + roots: List[Path] = [] + + def add(path: Path): + if path.exists() and path not in roots: + roots.append(path) + + cur, hops = py, 0 + while hops < 16: + hops += 1 + add(cur.parent.parent) + if cur.is_symlink(): + target = Path(os.readlink(cur)) + cur = target if target.is_absolute() else (cur.parent / target) + else: + break + + try: + r = subprocess.run([str(py), "-c", "import sys; print(sys.base_prefix)"], + capture_output=True, text=True, timeout=60) + if r.returncode == 0 and r.stdout.strip(): + add(Path(r.stdout.strip())) + except Exception: + pass + + return [p for p in roots if str(p) not in ("/", "/usr", "/usr/local")] + + def _isolate(self, argv: Sequence[str], workdir: Path, + ro_binds: Sequence[Path] = ()) -> List[str]: + """Wrap a command in the strongest isolation tier this host supports.""" + if self.isolation == "bwrap": + return _bwrap_argv( + workdir, argv, + ro_binds=[self.venv_dir, *(self._base_prefix or []), *ro_binds], + ) + if self.isolation in UNSHARE_ARGV: + return [*UNSHARE_ARGV[self.isolation], *argv] + return list(argv) + + def _base_env(self, workdir: Path) -> Dict[str, str]: + env = { + "PATH": "/usr/bin:/bin", + "HOME": str(workdir), + "TMPDIR": str(workdir), + "LC_ALL": "C.UTF-8", + "PYTHONHASHSEED": "0", + "PYTHONDONTWRITEBYTECODE": "1", + "OPENBLAS_NUM_THREADS": "1", + "OMP_NUM_THREADS": "1", + } + env.update(self._resolved_env()) + return env + + def run_argv(self, argv: Sequence[str], workdir: Path, + timeout: float = 15.0, env: Optional[Dict[str, str]] = None, + ro_binds: Sequence[Path] = ()) -> ExecResult: + """Run an arbitrary command in `workdir`, which stays writable. + + Unlike run(), the caller owns the directory and it survives the call. + That is what a multi-step agent needs: its edits have to persist across + many tool invocations before anything is graded. Taking an argv rather + than a source string is what lets a suite drive a linter or a test + runner for a language other than Python. + """ + run_env = self._base_env(workdir) + if env: + run_env.update(env) + + started = time.monotonic() + try: + proc = subprocess.Popen( + self._isolate(argv, workdir, ro_binds), + cwd=str(workdir), + stdin=subprocess.DEVNULL, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + text=True, + errors="replace", + env=run_env, + preexec_fn=_apply_rlimits(timeout, + with_nproc=self.isolation == "rlimit", + as_bytes=self.address_space_limit), + ) + except Exception as e: + return ExecResult(False, "error", "", f"{type(e).__name__}: {e}") + + try: + out, err = proc.communicate(timeout=timeout) + except subprocess.TimeoutExpired: + _kill_tree(proc) + out, err = proc.communicate() + return ExecResult(False, "timeout", out or "", err or "", + None, time.monotonic() - started) + + duration = time.monotonic() - started + if proc.returncode == 0: + return ExecResult(True, "ok", out, err, 0, duration) + return ExecResult(False, "failed", out, err, proc.returncode, duration) + + def run(self, code: str, timeout: float = 15.0, + env: Optional[Dict[str, str]] = None) -> ExecResult: + """Run `code` to completion in the sandbox. Exit 0 == passed.""" + workdir = Path(tempfile.mkdtemp(prefix=f"{self.name}-", dir="/tmp")) + try: + prog = workdir / "candidate.py" + prog.write_text(code) + return self.run_argv([str(self.python), "-I", "-B", str(prog)], + workdir, timeout=timeout, env=env) + except Exception as e: + return ExecResult(False, "error", "", f"{type(e).__name__}: {e}") + finally: + shutil.rmtree(workdir, ignore_errors=True) + + +def _kill_tree(proc: subprocess.Popen): + """Kill the candidate and everything it spawned.""" + for sig in (signal.SIGKILL,): + try: + os.killpg(os.getpgid(proc.pid), sig) + except (ProcessLookupError, PermissionError): + try: + proc.kill() + except ProcessLookupError: + pass diff --git a/examples/llama-eval/llama-eval.py b/examples/llama-eval/llama-eval.py index 61bdbddd8b13..3ed68e3b530d 100755 --- a/examples/llama-eval/llama-eval.py +++ b/examples/llama-eval/llama-eval.py @@ -1,6 +1,7 @@ #!/usr/bin/env python3 import argparse +import ast import json import os import re @@ -8,23 +9,113 @@ import sys import threading import time +import uuid from abc import ABC, abstractmethod from concurrent.futures import ThreadPoolExecutor, as_completed from dataclasses import dataclass, asdict, field from pathlib import Path from queue import Queue from typing import Dict, List, Optional, Any, Tuple +from urllib.parse import urlparse import requests from tqdm import tqdm import random from math import sqrt +from eval_sandbox import Sandbox, resolve_python + @dataclass class ServerConfig: url: str threads: int name: str = "" + api_key: Optional[str] = None + + def is_opencode(self) -> bool: + """Whether this endpoint is an opencode gateway rather than a llama-server.""" + return "opencode" in (urlparse(self.url).hostname or "") + + def headers(self, session_id: Optional[str] = None) -> Dict[str, str]: + headers = auth_headers(self.api_key) + if session_id and self.is_opencode(): + headers["x-opencode-session"] = session_id + return headers + + +def auth_headers(api_key: Optional[str]) -> Dict[str, str]: + """Standard request headers, carrying a bearer token when one is configured.""" + headers = {"Content-Type": "application/json"} + if api_key: + headers["Authorization"] = f"Bearer {api_key}" + return headers + + +SERVER_ERROR = "server_error" + +RETRYABLE_HTTP = {408, 409, 425, 429} + + +class ServerError(Exception): + """A request that still failed, or came back empty, after every retry.""" + + +def null_reply_reason(result: Any) -> Optional[str]: + """Why a chat completion carries no usable reply, or None when it does.""" + if not isinstance(result, dict): + return "reply is not a JSON object" + choices = result.get("choices") + if not choices: + return "reply has no choices" + msg = choices[0].get("message") + if not msg: + return "reply has no message" + if not (msg.get("content") or msg.get("tool_calls") or msg.get("reasoning_content")): + return "reply is empty" + return None + + +def post_with_retry(url: str, headers: Dict[str, str], data: Dict[str, Any], + retries: int, retry_delay: float, + timeout: Optional[float] = None) -> Dict[str, Any]: + """POST a chat completion, resending on errors and null replies. + + The wait before each resend doubles, starting at `retry_delay` seconds. + Raises ServerError once `retries` resends have all failed. + """ + reason = "" + attempts = 0 + for attempt in range(retries + 1): + if attempt: + wait = retry_delay * 2 ** (attempt - 1) + print(f" [{url}] {reason}; retry {attempt}/{retries} in {wait:.0f}s", + file=sys.stderr) + time.sleep(wait) + attempts += 1 + try: + response = requests.post(url, headers=headers, json=data, timeout=timeout) + except requests.RequestException as e: + reason = f"{type(e).__name__}: {e}" + continue + if response.status_code >= 400: + reason = f"HTTP {response.status_code}: {response.text[:300]}" + if response.status_code < 500 and response.status_code not in RETRYABLE_HTTP: + break + continue + try: + result = response.json() + except ValueError: + reason = f"invalid JSON: {response.text[:300]}" + continue + reason = null_reply_reason(result) or "" + if not reason: + return result + raise ServerError(f"{reason} (after {attempts} attempt{'s' if attempts > 1 else ''})") + + +def new_session_id(task_id: str) -> str: + """A fresh session id for one task, unique across tasks, runs and resumes.""" + return f"{task_id}-{uuid.uuid4().hex}" def wilson_interval(correct: int, total: int, z: float = 1.96) -> Tuple[float, float]: """Wilson score confidence interval for a proportion.""" @@ -106,13 +197,118 @@ def wilson_interval(correct: int, total: int, z: float = 1.96) -> Tuple[float, f B) {B} C) {C} D) {D} +""", + "humaneval": """Complete the following Python function. + +```python +{question} +``` + +Reply with the complete function in a single ```python code block, including the \ +signature and any imports it needs. Do not include tests, example usage, or explanation. +""", + "classeval": """Complete the following Python class. + +```python +{question} +``` + +Reply with the complete class in a single ```python code block: keep the class name \ +and every method signature exactly as given, implement every method body, and include \ +any imports the class needs. Do not include tests, example usage, or explanation. """, } +# Suites graded by running the generated code instead of matching its text. +CODE_SUITES = {"humaneval", "classeval", "agentic"} + +AGENTIC_SUITES = {"agentic"} + +# Import name -> pip name, for the cases where they differ. Anything not listed is assumed to install under the name it imports as. +PIP_NAMES = { + "bs4": "beautifulsoup4", + "PIL": "pillow", + "docx": "python-docx", + "fitz": "pymupdf", + "sklearn": "scikit-learn", + "yaml": "PyYAML", + "cv2": "opencv-python-headless", + "PyPDF2": "pypdf2", + "Levenshtein": "levenshtein", + "dateutil": "python-dateutil", + "attr": "attrs", + "OpenSSL": "pyOpenSSL", + "serial": "pyserial", + "Crypto": "pycryptodome", +} + +DATASET_SOURCE: Optional[str] = None + +# Extra construction options for the agentic suite, set from the CLI. +AGENTIC_OPTS: Dict[str, Any] = {} + class BaseDataset(ABC): questions: List[Dict] + is_agentic: bool = False + + def prepare(self, base_python: Optional[str] = None, force: bool = False) -> None: + """Provision whatever the suite needs before any task runs. + + Single-shot suites are provisioned from required_packages() instead, so + this is a no-op for them. + """ + + def run(self, index: int, chat) -> Dict[str, Any]: + """Drive one episode to completion and return its scored result.""" + raise NotImplementedError( + f"{type(self).__name__} does not drive its own conversation") + + def required_packages(self) -> List[str]: + """Third-party pip packages the suite's tests need.""" + return [] + + def provision_steps(self) -> List[str]: + """Python snippets run once at venv build time, with network access.""" + return [] + + def preferred_python(self) -> Optional[str]: + """Interpreter the suite's dependencies need, if not the current one.""" + return None + + def configure_python(self, python: str): + """Told which interpreter the sandbox will use, before it is built. + + Lets a suite adapt its package set to what that version can actually + install. + """ + + def default_exec_timeout(self) -> float: + """Per-task wall-clock limit that suits this suite's workload.""" + return 15.0 + + def sandbox_env(self) -> Dict[str, str]: + """Extra env for every run; '{venv}' expands to the venv path.""" + return {} + + def extract(self, response: str, question: Dict) -> str: + """Pull the candidate code out of a chat reply.""" + return extract_code(response) + + def build_program(self, question: Dict, completion: str, + seed: Optional[int] = None) -> str: + """Assemble the program whose exit status decides pass/fail.""" + raise NotImplementedError + + def interpret(self, result: Any, question: Dict) -> Tuple[bool, Dict[str, Any]]: + """Turn an ExecResult into (passed, detail-for-the-log).""" + return result.passed, { + "status": result.status, + "reason": result.summary(), + "duration": round(result.duration, 3), + } + @abstractmethod def get_question(self, index: int) -> Dict: pass @@ -175,6 +371,13 @@ def __init__( self.total_time: float = 0.0 self._lock = threading.Lock() + @property + def loaded_dataset(self) -> BaseDataset: + """The dataset, once loaded. Raises rather than handing back None.""" + if self.dataset is None: + raise RuntimeError("dataset not loaded; call load_dataset() first") + return self.dataset + def load_dataset(self, seed: int = 1234): if self.dataset_type == "aime": self.dataset = AimeDataset() @@ -186,6 +389,12 @@ def load_dataset(self, seed: int = 1234): self.dataset = Gsm8kDataset() elif self.dataset_type == "gpqa": self.dataset = GpqaDataset(variant="diamond", seed=seed) + elif self.dataset_type == "humaneval": + self.dataset = HumanEvalDataset(source=DATASET_SOURCE) + elif self.dataset_type == "classeval": + self.dataset = ClassEvalDataset(source=DATASET_SOURCE) + elif self.dataset_type == "agentic": + self.dataset = AgenticDataset(source=DATASET_SOURCE, **AGENTIC_OPTS) else: raise ValueError(f"Unknown dataset type: {self.dataset_type}") @@ -263,31 +472,55 @@ def add_result( self.correct = sum(1 for c in self.task_states.get("cases", {}).values() if c.get("correct", False)) + def _display_pair(self, task_state: TaskState) -> Tuple[str, str]: + """The (expected, answer) columns, kept narrow for code suites. + + There the gold value is a whole JSON test harness and the answer is a + whole function, so show the task id and the failure cause instead. + """ + if self.dataset_type not in CODE_SUITES: + return ( + task_state.expected, + task_state.answer if task_state.answer else "N/A", + ) + try: + expected = json.loads(task_state.expected)["task_id"] + except (ValueError, KeyError, TypeError): + expected = self.dataset_type + reason = (task_state.grader_log or {}).get("reason", "") + if task_state.correct: + reason = "ok" + return expected, (reason[:28] or "N/A") + def print_progress(self, task_state: TaskState, total_tasks: int, n_correct: int = 0): - display_answer = task_state.answer if task_state.answer else "N/A" + display_expected, display_answer = self._display_pair(task_state) display_tokens = str(task_state.tokens) if task_state.tokens is not None else "N/A" display_tps = f"{task_state.tps_gen:.1f}" if task_state.tps_gen is not None else "N/A" display_t_gen = f"{task_state.t_gen_ms/1000:.1f}" if task_state.t_gen_ms is not None else "N/A" display_server = task_state.server_name if task_state.server_name else "N/A" success_ratio = n_correct / self.processed if self.processed > 0 else 0.0 - first_line = task_state.question_text.split('\n')[0] + first_line = next( + (ln for ln in task_state.question_text.split('\n') if ln.strip()), "" + ) truncated_question = first_line[:43] if len(first_line) > 43: truncated_question += "..." else: truncated_question = truncated_question.ljust(43) + "..." - print(f"{self.processed:3}/{total_tasks:3} {task_state.task_id:<20} {self.dataset_type.upper()} {truncated_question:<40} {task_state.expected:<10} {display_answer:<10} {display_tokens:<6} {display_tps:<6} {display_t_gen:<8} {'✓' if task_state.correct else '✗'} [{n_correct:3}/{self.processed:3}, {success_ratio:.3f}] {display_server}") + print(f"{self.processed:3}/{total_tasks:3} {task_state.task_id:<20} {self.dataset_type.upper()} {truncated_question:<40} {display_expected:<16} {display_answer:<28} {display_tokens:<6} {display_tps:<6} {display_t_gen:<8} {'✓' if task_state.correct else ('⚠' if task_state.status == SERVER_ERROR else '✗')} [{n_correct:3}/{self.processed:3}, {success_ratio:.3f}] {display_server}") + + def n_server_errors(self) -> int: + cases = self.task_states.get("cases", {}) + return sum(1 for c in cases.values() if c.get("status") == SERVER_ERROR) + + def print_server_errors(self): + n = self.n_server_errors() + if n: + print(f"Server errors: {n} (not counted in accuracy; run with --resume to retry them)") def print_summary(self): - if self.total == 0: - print(f"\n{'='*60}") - print(f"Results: 0/0 correct (0.0%)") - print(f"{'='*60}") - else: - ci_lower, ci_upper = self.accuracy_ci() - print(f"\n{'='*60}") - print(f"Results: {self.correct}/{self.total} correct ({self.correct/self.total*100:.1f}%) [{ci_lower*100:.1f}%, {ci_upper*100:.1f}%]") - print(f"{'='*60}") + print() + self.print_existing_summary() def dump(self): with self._lock: @@ -347,7 +580,8 @@ def dump_html(self, tasks_to_save: List[Tuple[int, str]], all_cases: Dict[str, A completed = {tid: c for tid, c in cases.items() if c.get("status") == "ok"} n_correct = sum(1 for c in completed.values() if c.get("correct", False)) n_incorrect = len(completed) - n_correct - n_pending = len(tasks_to_save) - len(completed) + n_server_errors = sum(1 for c in cases.values() if c.get("status") == SERVER_ERROR) + n_pending = len(tasks_to_save) - len(completed) - n_server_errors accuracy = n_correct / len(completed) * 100 if completed else 0.0 ci_lower, ci_upper = wilson_interval(n_correct, len(completed)) if completed else (0.0, 1.0) @@ -374,6 +608,9 @@ def dump_html(self, tasks_to_save: List[Tuple[int, str]], all_cases: Dict[str, A elif status == "pending": status_class = "pending" status_text = "–" + elif status == SERVER_ERROR: + status_class = "server-error" + status_text = "⚠" else: status_class = "error" status_text = "!" @@ -392,6 +629,11 @@ def dump_html(self, tasks_to_save: List[Tuple[int, str]], all_cases: Dict[str, A escaped_reasoning = self._escape_html(reasoning_content) grader_log_str = self._escape_html(json.dumps(grader_log, indent=2)) escaped_server = self._escape_html(server_name) + transcript = grader_log.get("transcript") if isinstance(grader_log, dict) else None + transcript_link = ( + f'Transcript ' + f'{self._escape_html(transcript[:-5])}.html
' + if transcript and transcript.endswith(".json") else "") answer_class = status_class if status == "ok" else "" rows.append(f""" @@ -407,6 +649,7 @@ def dump_html(self, tasks_to_save: List[Tuple[int, str]], all_cases: Dict[str, A
+ {transcript_link} Prompt
{escaped_prompt}
Response
{escaped_response}
{f'Reasoning
{escaped_reasoning}
' if escaped_reasoning else ''} @@ -483,6 +726,7 @@ def _stat(v, fmt=".1f", avg_fmt=None): .incorrect {{ color: #cf222e; }} .pending {{ color: #888; }} .error {{ color: #9a6700; }} + .server-error {{ color: #8250df; }} .details-row {{ display: none; }} .details-row.open {{ display: table-row; }} .details-content {{ padding: 8px 16px; background: #f6f8fa; font-size: 12px; }} @@ -511,6 +755,7 @@ def _stat(v, fmt=".1f", avg_fmt=None):
Accuracy
{accuracy:.1f}% [{ci_lower*100:.1f}%, {ci_upper*100:.1f}%]
Correct
{n_correct} / {len(completed)}
Pending
{n_pending}
+
Server errors
{n_server_errors}
Time
{self.total_time:.1f}s
Sampling
{sampling_str}
@@ -680,6 +925,7 @@ def print_existing_summary(self): print(f"{'='*60}") print(f"Results: {correct}/{total} correct ({correct/total*100:.1f}%) [{ci_lower*100:.1f}%, {ci_upper*100:.1f}%]") print(f"{'='*60}") + self.print_server_errors() def accuracy_ci(self) -> Tuple[float, float]: """Compute Wilson score confidence interval from completed cases.""" @@ -974,6 +1220,526 @@ def get_prompt(self, question: Dict) -> str: D=question["shuffled_answers"][3] ) +FENCE_RE = re.compile(r"```[ \t]*([A-Za-z0-9_+-]*)[ \t]*\n(.*?)(?:```|\Z)", re.DOTALL) + +RESULT_MARKER = "__LLAMA_EVAL__" + +GENSIM_SHIM = { + "__init__.py": ( + '"""Minimal stand-in for the two gensim entry points ClassEval uses."""\n' + "from . import utils, matutils # noqa: F401\n" + ), + "utils.py": ( + "import re, html\n" + "RE_ENTITY = re.compile(r'&(#?)([xX]?)(\\w{1,8});')\n" + "def decode_htmlentities(text):\n" + " return RE_ENTITY.sub(lambda m: html.unescape(m.group(0)), text)\n" + ), + "matutils.py": ( + "import numpy as np\n" + "def unitvec(vec, norm='l2', return_norm=False):\n" + " v = np.asarray(vec, dtype=float)\n" + " n = float(np.sum(np.abs(v))) if norm == 'l1' " + "else float(np.sqrt(np.sum(v ** 2)))\n" + " if n == 0.0:\n" + " return (v, 1.0) if return_norm else v\n" + " out = v / n\n" + " return (out, n) if return_norm else out\n" + ), +} + +UNITTEST_PROLOGUE = ''' +import unittest as _ut_pre +_ut_pre.main = lambda *a, **k: None +''' + +UNITTEST_RUNNER = f''' + +if True: + import json as _json, os as _os, unittest as _ut + _loader = _ut.TestLoader() + _suite = _ut.TestSuite() + for _c in [v for v in list(globals().values()) + if isinstance(v, type) and issubclass(v, _ut.TestCase) + and v is not _ut.TestCase]: + _suite.addTests(_loader.loadTestsFromTestCase(_c)) + with open(_os.devnull, "w") as _null: + _res = _ut.TextTestRunner(stream=_null, verbosity=0).run(_suite) + _bad = {{t.id() for t, _ in _res.failures}} | {{t.id() for t, _ in _res.errors}} + _total = _res.testsRun + print("{RESULT_MARKER}" + _json.dumps({{ + "total": _total, + "passed": _total - len(_bad), + "failed": sorted(_bad), + "first_error": (_res.failures + _res.errors)[0][1].strip().splitlines()[-1] + if (_res.failures or _res.errors) else None, + }})) +''' + + +def parse_test_report(stdout: str) -> Optional[Dict[str, Any]]: + """Read the JSON line emitted by UNITTEST_RUNNER, if the program got that far.""" + for line in reversed(stdout.splitlines()): + if line.startswith(RESULT_MARKER): + try: + return json.loads(line[len(RESULT_MARKER):]) + except ValueError: + return None + return None + + +def extract_code(response: str, entry_point: Optional[str] = None, + class_name: Optional[str] = None) -> str: + """Pull the candidate program out of a chat reply. + + Prefers a fenced block that actually defines the thing being asked for, + since models like to emit a usage example or a test in a second block. + """ + if not response: + return "" + + if class_name: + wanted = rf"^\s*class\s+{re.escape(class_name)}\s*[:\(]" + elif entry_point: + wanted = rf"^\s*(?:async\s+)?def\s+{re.escape(entry_point)}\s*\(" + else: + wanted = None + + blocks = [(lang.lower(), body) for lang, body in FENCE_RE.findall(response)] + if blocks: + py = [b for lang, b in blocks if lang in ("python", "py", "python3", "")] + candidates = py or [b for _, b in blocks] + if wanted: + defining = [b for b in candidates if re.search(wanted, b, re.M)] + if defining: + return defining[-1].strip("\n") + return candidates[0].strip("\n") + + return response.strip("\n") + + +def _import_preamble(prompt: str) -> str: + """The import lines from the original stub. + + A chat model often returns just the function and drops the imports that the + stub had above it; replaying them keeps that from being scored as a failure. + """ + lines = [] + for line in prompt.splitlines(): + stripped = line.strip() + if stripped.startswith(("import ", "from ")) and not line.startswith((" ", "\t")): + lines.append(stripped) + return "\n".join(lines) + + +def build_program(question: Dict, completion: str, seed: Optional[int] = 0) -> str: + """Assemble the full program that decides pass/fail for one problem.""" + entry_point = question["entry_point"] + code = completion + + if not re.search(rf"^\s*(?:async\s+)?def\s+{re.escape(entry_point)}\s*\(", code, re.M): + body = completion if completion.startswith((" ", "\t")) else \ + "\n".join(" " + ln for ln in completion.splitlines()) + code = question["prompt"] + "\n" + body + + prologue = f"import random; random.seed({seed})" if seed is not None else "" + + return "\n\n".join(part for part in [ + _import_preamble(question["prompt"]), + code, + question["test"], + prologue, + f"check({entry_point})", + ] if part) + + +def pass_at_k(n: int, c: int, k: int) -> float: + """Unbiased pass@k estimator from the Codex paper (arXiv:2107.03374). + + n samples drawn, c of them correct. Computed as 1 - C(n-c,k)/C(n,k) via a + product so it stays stable for large n. + """ + if n - c < k: + return 1.0 + prod = 1.0 + for i in range(n - c + 1, n + 1): + prod *= 1.0 - k / i + return 1.0 - prod + + +class HumanEvalDataset(BaseDataset): + """OpenAI HumanEval, 164 hand-written Python problems. + + Every problem in this suite imports only from the standard library, so the + execution venv needs no pip installs at all -- see `required_packages`. + """ + + HF_REPO = "openai/openai_humaneval" + + def __init__(self, source: Optional[str] = None, split: str = "test"): + self.source = source or self.HF_REPO + self.split = split + self.questions: List[Dict] = [] + self._load_dataset() + + def _load_dataset(self): + print(f"Loading HumanEval dataset (source: {self.source})...") + + local = Path(self.source) + if local.exists(): + rows = [json.loads(ln) for ln in local.read_text().splitlines() if ln.strip()] + else: + from datasets import load_dataset + rows = [dict(r) for r in load_dataset(self.source, split=self.split)] + + required = {"task_id", "prompt", "entry_point", "test"} + for row in rows: + missing = required - row.keys() + if missing: + raise ValueError( + f"{self.source}: record {row.get('task_id', '?')} is missing {sorted(missing)}" + ) + row["dataset_type"] = "humaneval" + self.questions.append(row) + + print(f"HumanEval dataset loaded: {len(self.questions)} problems") + + def required_packages(self) -> List[str]: + """Third-party pip packages this suite needs. Derived, not hardcoded.""" + return sorted(third_party_imports( + "\n".join(q["prompt"] + "\n" + q["test"] for q in self.questions) + )) + + def extract(self, response: str, question: Dict) -> str: + return extract_code(response, question.get("entry_point")) + + def build_program(self, question: Dict, completion: str, + seed: Optional[int] = None) -> str: + return build_program(question, completion, seed=seed) + + def get_question(self, index: int) -> Dict: + return self.questions[index] + + def get_question_text(self, question: Dict) -> str: + return question["prompt"] + + def get_answer(self, question: Dict) -> str: + return json.dumps({ + "task_id": question["task_id"], + "entry_point": question["entry_point"], + "prompt": question["prompt"], + "test": question["test"], + }) + + def get_prompt(self, question: Dict) -> str: + return TEMPLATE_REGISTRY["humaneval"].format( + question=self.get_question_text(question).rstrip(), + ) + + +class ClassEvalDataset(BaseDataset): + """ClassEval: 100 class-level Python generation tasks. + + A task is a whole class judged by several independent unittest classes, so + it is scored twice -- class level (every test passes) and method level + (what fraction of tests passed), matching the upstream protocol. + """ + + HF_REPO = "ilintar/ClassEval" + + def __init__(self, source: Optional[str] = None): + self.source = source or self.HF_REPO + self.questions: List[Dict] = [] + self._gensim_shim = False + self._load_dataset() + + def _load_dataset(self): + print(f"Loading ClassEval dataset (source: {self.source})...") + + local = Path(self.source) + if local.exists(): + text = local.read_text() + rows = (json.loads(text) if local.suffix == ".json" + else [json.loads(ln) for ln in text.splitlines() if ln.strip()]) + else: + from datasets import load_dataset + rows = [dict(r) for r in load_dataset(self.source, split="test")] + + required = {"task_id", "skeleton", "test", "class_name"} + for row in rows: + missing = required - row.keys() + if missing: + raise ValueError( + f"{self.source}: record {row.get('task_id', '?')} is missing {sorted(missing)}" + ) + row["dataset_type"] = "classeval" + row["n_tests"] = _count_test_methods(row["test"]) + self.questions.append(row) + + print(f"ClassEval dataset loaded: {len(self.questions)} classes, " + f"{sum(q['n_tests'] for q in self.questions)} test methods") + + EXTRA_PACKAGES = [ + "lxml", + "scipy", + ] + + def configure_python(self, python: str): + """gensim stops at cp313, so on 3.14+ swap it for a small local shim.""" + try: + r = subprocess.run( + [python, "-c", "import sys; print('%d.%d' % sys.version_info[:2])"], + capture_output=True, text=True, timeout=60, + ) + major, minor = (int(x) for x in r.stdout.strip().split(".")) + except Exception: + return + self._gensim_shim = (major, minor) >= (3, 14) + + def required_packages(self) -> List[str]: + blob = "\n\n".join( + "\n\n".join(_as_text(q.get(f)) for f in + ("skeleton", "test", "solution_code", "import_statement")) + for q in self.questions + ) + found = {PIP_NAMES.get(m, m) for m in third_party_imports(blob)} + found |= set(self.EXTRA_PACKAGES) + if self._gensim_shim: + found.discard("gensim") + return sorted(found) + + NLTK_CORPORA = ("punkt_tab", "averaged_perceptron_tagger_eng", "wordnet") + + def provision_steps(self) -> List[str]: + steps = [] + + if any("nltk" in _as_text(q.get("skeleton")) + _as_text(q.get("test")) + for q in self.questions): + steps.append( + "import os, nltk\n" + "target = os.path.join(os.environ['SANDBOX_VENV'], 'nltk_data')\n" + "os.makedirs(target, exist_ok=True)\n" + f"for corpus in {self.NLTK_CORPORA!r}:\n" + " nltk.download(corpus, download_dir=target, quiet=True)\n" + ) + + if self._gensim_shim: + steps.append( + "import os, sysconfig\n" + "pkg = os.path.join(sysconfig.get_paths()['purelib'], 'gensim')\n" + "os.makedirs(pkg, exist_ok=True)\n" + f"files = {GENSIM_SHIM!r}\n" + "for name, body in files.items():\n" + " open(os.path.join(pkg, name), 'w').write(body)\n" + "import gensim.utils, gensim.matutils\n" + ) + + return steps + + def sandbox_env(self) -> Dict[str, str]: + return {"NLTK_DATA": "{venv}/nltk_data"} + + def preferred_python(self) -> Optional[str]: + return "3.13" + + def default_exec_timeout(self) -> float: + return 30.0 + + def extract(self, response: str, question: Dict) -> str: + return extract_code(response, class_name=question.get("class_name")) + + def build_program(self, question: Dict, completion: str, + seed: Optional[int] = None) -> str: + prologue = f"import random; random.seed({seed})" if seed is not None else "" + return "\n\n".join(part for part in [ + _as_text(question.get("import_statement")), + UNITTEST_PROLOGUE, + completion, + question["test"], + prologue, + UNITTEST_RUNNER, + ] if part) + + def interpret(self, result: Any, question: Dict) -> Tuple[bool, Dict[str, Any]]: + expected = question.get("n_tests", 0) + + report = parse_test_report(result.stdout) + if report is None: + return False, { + "status": result.status if result.status != "ok" else "no-report", + "reason": result.summary(), + "tests_total": expected, + "tests_passed": 0, + "duration": round(result.duration, 3), + } + + total, passed = report.get("total", 0) or expected, report.get("passed", 0) + ok = total > 0 and passed == total + return ok, { + "status": "ok" if ok else "failed", + "reason": "ok" if ok else (report.get("first_error") + or f"{passed}/{total} tests passed")[:200], + "tests_total": total, + "tests_passed": passed, + "duration": round(result.duration, 3), + } + + def get_question(self, index: int) -> Dict: + return self.questions[index] + + def get_question_text(self, question: Dict) -> str: + return question["skeleton"] + + def get_answer(self, question: Dict) -> str: + return json.dumps({ + "task_id": question["task_id"], + "class_name": question["class_name"], + "import_statement": _as_text(question.get("import_statement")), + "test": question["test"], + "n_tests": question["n_tests"], + }) + + def get_prompt(self, question: Dict) -> str: + return TEMPLATE_REGISTRY["classeval"].format( + question=self.get_question_text(question).rstrip(), + ) + + +class AgenticDataset(BaseDataset): + """Multi-turn tool-driven repair tasks over a small real repository. + + The other code suites answer one prompt. Here the model is handed a tool + set and drives its own conversation, so the Processor delegates the whole + episode rather than making a single request. + + Everything language-specific is imported lazily and provisioned per + language, so selecting the Python tasks never installs a node toolchain -- + and running any other suite installs none of it. + """ + + HF_REPO = "ilintar/SACB" + is_agentic = True + ae: Any + + def __init__(self, source: Optional[str] = None, lang: Optional[str] = None, + max_turns: int = 50, context_limit: Optional[int] = None, + max_tokens: Optional[int] = None): + self.source = source or self.HF_REPO + self.lang_filter = lang + self.max_turns = max_turns + self.context_limit = context_limit + self.max_tokens = max_tokens + self._sandboxes: Dict[str, Any] = {} + self._load_dataset() + + def _load_dataset(self): + import agentic_eval as ae + self.ae = ae + + print(f"Loading agentic dataset (source: {self.source})...") + path = Path(self.source) + if path.exists(): + rows = [json.loads(line) for line in path.read_text().splitlines() + if line.strip()] + else: + from datasets import load_dataset + rows = [dict(r) for r in load_dataset(self.source, split="test")] + + if self.lang_filter: + rows = [r for r in rows if r.get("lang") == self.lang_filter] + if not rows: + raise ValueError( + f"no agentic tasks in {self.source}" + + (f" for language {self.lang_filter!r}" if self.lang_filter else "")) + + self.tasks = [ae.AgenticTask.from_record(r) for r in rows] + self.languages = sorted({t.lang for t in self.tasks}) + print(f"Agentic dataset loaded: {len(self.tasks)} tasks " + f"({', '.join(self.languages)})") + + def __len__(self) -> int: + return len(self.tasks) + + def get_question(self, index: int) -> Dict: + return {"index": index} + + def get_question_text(self, question: Dict) -> str: + task = self.tasks[question["index"]] + first = task.instruction.strip().splitlines()[0] + return f"[{task.task_id}] {first}" + + def get_answer(self, question: Dict) -> str: + task = self.tasks[question["index"]] + return json.dumps({"task_id": task.task_id, "index": question["index"]}) + + def get_prompt(self, question: Dict) -> str: + return self.ae.user_prompt(self.tasks[question["index"]]) + + def default_exec_timeout(self) -> float: + return 90.0 + + def required_packages(self) -> List[str]: + return [] + + def prepare(self, base_python: Optional[str] = None, force: bool = False): + """Provision one sandbox per language present in the selected tasks.""" + for lang in self.languages: + sandbox = self.ae.make_sandbox(lang, Sandbox, base_python=base_python) + sandbox.ensure(force=force) + self._sandboxes[lang] = sandbox + return self._sandboxes + + def run(self, index: int, chat) -> Dict[str, Any]: + task = self.tasks[index] + return self.ae.run_task( + task, chat, self._sandboxes[task.lang], + max_turns=self.max_turns, context_limit=self.context_limit, + test_timeout=self.default_exec_timeout()) + + +def _as_text(value: Any) -> str: + """Some dataset fields arrive as a list of lines rather than a blob.""" + if not value: + return "" + if isinstance(value, (list, tuple)): + return "\n".join(str(v) for v in value) + return str(value) + + +def _count_test_methods(test_code: str) -> int: + """How many `def test_*` a task's test suite defines.""" + try: + tree = ast.parse(test_code) + except SyntaxError: + return len(re.findall(r"^\s*def\s+test\w*\s*\(", test_code, re.M)) + return sum( + 1 + for node in ast.walk(tree) + if isinstance(node, (ast.FunctionDef, ast.AsyncFunctionDef)) + and node.name.startswith("test") + ) + + +def third_party_imports(source: str) -> set: + """Top-level modules imported by `source` that are not in the stdlib.""" + import ast + + mods = set() + for chunk in source.split("\n\n"): + try: + tree = ast.parse(chunk) + except SyntaxError: + continue + for node in ast.walk(tree): + if isinstance(node, ast.Import): + mods.update(a.name.split(".")[0] for a in node.names) + elif isinstance(node, ast.ImportFrom) and node.module and node.level == 0: + mods.add(node.module.split(".")[0]) + + stdlib = set(sys.stdlib_module_names) + return {m for m in mods if m and m not in stdlib} + + class Grader: def __init__( self, @@ -981,14 +1747,29 @@ def __init__( grader_script: Optional[str] = None, grader_model_name: Optional[str] = None, grader_server_url: str = "", - dataset_type: str = "aime" + grader_api_key: Optional[str] = None, + dataset_type: str = "aime", + sandbox: Optional[Sandbox] = None, + exec_timeout: float = 15.0, + exec_seed: Optional[int] = 0, + dataset: Optional[BaseDataset] = None, ): self.grader_type = grader_type self.grader_script = grader_script self.grader_model_name = grader_model_name self.grader_server_url = grader_server_url + self.grader_api_key = grader_api_key self.dataset_type = dataset_type + self.sandbox = sandbox + self.exec_timeout = exec_timeout + self.exec_seed = exec_seed + self.dataset = dataset self.pattern = self._get_pattern() + self._local = threading.local() + + @property + def last_exec(self) -> Dict[str, Any]: + return getattr(self._local, "exec_info", {}) def _get_pattern(self) -> Optional[str]: if self.grader_type == "regex": @@ -1077,7 +1858,7 @@ def _grade_llm(self, gold: str, pred: str, problem: str) -> Tuple[bool, Optional Please provide only the extracted answer, nothing else. If there is no clear answer that can be extracted from the response, reply with 'no answer'.""" url = f"{self.grader_server_url}/v1/chat/completions" - headers = {"Content-Type": "application/json"} + headers = auth_headers(self.grader_api_key) data = { "model": self.grader_model_name, "messages": [ @@ -1102,6 +1883,28 @@ def _truncate_response(self, response: str, max_lines: int = 6) -> str: lines = response.split('\n') return '\n'.join(lines[-max_lines:]) if len(lines) > max_lines else response + def _grade_exec(self, gold: str, pred: str) -> Tuple[bool, Optional[str]]: + """Grade by running the generated code against the suite's own tests. + + `gold` is the JSON harness produced by the dataset's get_answer(); the + dataset owns how the program is assembled and how its result is read. + """ + if self.sandbox is None or self.dataset is None: + raise ValueError("exec grader requires a sandbox and a dataset") + + question = json.loads(gold) + completion = self.dataset.extract(pred, question) + if not completion.strip(): + self._local.exec_info = {"status": "empty", "reason": "no code in reply"} + return False, None + + program = self.dataset.build_program(question, completion, seed=self.exec_seed) + result = self.sandbox.run(program, timeout=self.exec_timeout) + passed, detail = self.dataset.interpret(result, question) + + self._local.exec_info = detail + return passed, completion + def grade(self, gold: str, pred: str, problem: str = "") -> Tuple[bool, Optional[str]]: """Grade the response""" if self.grader_type == "regex": @@ -1110,6 +1913,8 @@ def grade(self, gold: str, pred: str, problem: str = "") -> Tuple[bool, Optional return self._grade_cli(gold, pred) elif self.grader_type == "llm": return self._grade_llm(gold, pred, problem) + elif self.grader_type == "exec": + return self._grade_exec(gold, pred) else: raise ValueError(f"Unknown grader type: {self.grader_type}") @@ -1119,18 +1924,24 @@ def __init__( server_configs: List[ServerConfig], grader: Grader, model_name: Optional[str] = None, - n_predict: int = -1 + n_predict: int = -1, + retries: int = 5, + retry_delay: float = 10.0, + transcript_dir: Optional[Path] = None, ): self.server_configs = server_configs self.grader = grader self.model_name = model_name self.n_predict = n_predict + self.retries = retries + self.retry_delay = retry_delay + self.transcript_dir = transcript_dir @staticmethod def _check_server(server_config: ServerConfig) -> List[str]: url = f"{server_config.url}/v1/models" try: - response = requests.get(url) + response = requests.get(url, headers=server_config.headers()) response.raise_for_status() models = [m["id"] for m in response.json().get("data", [])] return models @@ -1139,10 +1950,11 @@ def _check_server(server_config: ServerConfig) -> List[str]: sys.exit(1) def _make_request( - self, server_config: ServerConfig, eval_state: EvalState, prompt: str + self, server_config: ServerConfig, eval_state: EvalState, prompt: str, + session_id: Optional[str] = None ) -> Tuple[Dict[str, Any], int, Optional[float], Optional[float], str]: url = f"{server_config.url}/v1/chat/completions" - headers = {"Content-Type": "application/json"} + headers = server_config.headers(session_id) data = { "model": self.model_name if self.model_name else "llama", "messages": [{"role": "user", "content": prompt}], @@ -1156,10 +1968,10 @@ def _make_request( data["top_p"] = eval_state.sampling_config["top_p"] if eval_state.sampling_config.get("min_p") is not None: data["min_p"] = eval_state.sampling_config["min_p"] + if eval_state.sampling_config.get("reasoning_effort") is not None: + data["reasoning_effort"] = eval_state.sampling_config["reasoning_effort"] - response = requests.post(url, headers=headers, json=data) - response.raise_for_status() - result = response.json() + result = post_with_retry(url, headers, data, self.retries, self.retry_delay) tokens = result.get("usage", {}).get("completion_tokens", 0) timings = result.get("timings", {}) tps_gen = timings.get("predicted_per_second") if timings else None @@ -1187,8 +1999,14 @@ def _process_single_case( problem_idx=problem_idx, ) + session_id = new_session_id(task_id) + + if eval_state.loaded_dataset.is_agentic: + return self._process_agentic_case( + server_config, eval_state, i, task_id, task_state, session_id) + try: - response, tokens, tps_gen, t_gen_ms, finish_reason = self._make_request(server_config, eval_state, prompt) + response, tokens, tps_gen, t_gen_ms, finish_reason = self._make_request(server_config, eval_state, prompt, session_id) result = response["choices"][0]["message"]["content"] reasoning_content = response["choices"][0].get("message", {}).get("reasoning_content") task_state.response = result @@ -1208,15 +2026,20 @@ def _process_single_case( eval_state.dump() return task_state - result_truncated = self.grader._truncate_response(result, max_lines=10) - is_correct, answer = self.grader.grade(expected, result_truncated, prompt) + if self.grader.grader_type == "exec": + graded_text = result + else: + graded_text = self.grader._truncate_response(result, max_lines=10) + is_correct, answer = self.grader.grade(expected, graded_text, prompt) grader_log = { - "pred": result_truncated, + "pred": graded_text, "grader_type": self.grader.grader_type } if self.grader.grader_type == "regex" and self.grader.pattern: grader_log["pattern"] = self.grader.pattern + if self.grader.grader_type == "exec": + grader_log.update(self.grader.last_exec) task_state.correct = is_correct task_state.answer = answer @@ -1232,11 +2055,136 @@ def _process_single_case( eval_state.dump() + except ServerError as e: + task_state.status = SERVER_ERROR + task_state.grader_log = {"error": str(e)} + eval_state.add_result( + task_id, prompt, expected, None, None, task_state.grader_log, + False, SERVER_ERROR, None, None, None, None, server_config.name, + chunk_idx, problem_idx, + ) + eval_state.dump() except Exception as e: task_state.status = f"error: {str(e)}" return task_state + def _agentic_chat(self, server_config: ServerConfig, eval_state: EvalState, + session_id: Optional[str] = None): + """A chat callable for agentic_eval: messages + tools in, response out.""" + url = f"{server_config.url}/v1/chat/completions" + + def chat(messages, tools): + data = { + "model": self.model_name if self.model_name else "llama", + "messages": messages, + "tools": tools, + "tool_choice": "auto", + } + per_turn = getattr(eval_state.dataset, "max_tokens", None) + if self.n_predict and self.n_predict > 0: + data["max_tokens"] = self.n_predict + elif per_turn: + data["max_tokens"] = per_turn + for key in ("temperature", "top_k", "top_p", "min_p", "reasoning_effort"): + value = eval_state.sampling_config.get(key) + if value is not None: + data[key] = value + return post_with_retry(url, server_config.headers(session_id), data, + self.retries, self.retry_delay, timeout=1800) + + return chat + + def _process_agentic_case( + self, server_config: ServerConfig, eval_state: EvalState, i: int, + task_id: str, task_state: TaskState, session_id: Optional[str] = None + ) -> TaskState: + """Run one whole tool-driven episode and grade the tree it leaves behind.""" + try: + result = eval_state.loaded_dataset.run( + i, self._agentic_chat(server_config, eval_state, session_id)) + except Exception as e: + task_state.status = f"error: {type(e).__name__}: {e}" + eval_state.add_result( + task_id, task_state.prompt, task_state.expected, + task_state.status, None, + {"error": f"{type(e).__name__}: {e}", "resolved": False}, + False, task_state.status, 0, None, None, None, + server_config.name, task_state.chunk_idx, i, + ) + eval_state.dump() + return task_state + + episode = result.get("episode", {}) + messages = result.pop("messages", None) + if messages is not None and self.transcript_dir is not None: + self._save_transcript(eval_state, task_id, messages, result) + + if episode.get("stop_reason") in ("request_failed", "no_choices"): + task_state.status = SERVER_ERROR + task_state.grader_log = result + task_state.response = f"server error on turn {episode.get('turns')}: {episode.get('error')}" + eval_state.add_result( + task_id, task_state.prompt, task_state.expected, task_state.response, + None, result, False, SERVER_ERROR, + episode.get("completion_tokens", 0), None, None, None, + server_config.name, task_state.chunk_idx, i, + ) + eval_state.dump() + return task_state + + task_state.tokens = episode.get("completion_tokens", 0) + task_state.correct = bool(result["resolved"]) + task_state.answer = ", ".join(result.get("changed_files", [])) or None + task_state.grader_log = result + task_state.status = "ok" + task_state.response = ( + f"stop={episode.get('stop_reason')} turns={episode.get('turns')} " + f"calls={episode.get('tool_calls')} edits={episode.get('edits')} " + f"errors={episode.get('tool_errors')} nudges={episode.get('nudges')} truncated={episode.get('truncated_turns')} " + f"peak_ctx={episode.get('peak_context')}\n" + f"changed: {task_state.answer or '(nothing)'}" + ) + + eval_state.add_result( + task_id, task_state.prompt, task_state.expected, task_state.response, + task_state.answer, result, task_state.correct, "ok", + task_state.tokens, None, None, None, server_config.name, + task_state.chunk_idx, i, + ) + eval_state.dump() + return task_state + + def _save_transcript(self, eval_state: EvalState, task_id: str, + messages: List[Dict[str, Any]], result: Dict[str, Any]): + """Write the episode's messages as .json plus a readable .html.""" + assert self.transcript_dir is not None + ep = result.get("episode", {}) + verdict = "RESOLVED" if result.get("resolved") else "not resolved" + meta = ( + f"{verdict} f2p {result.get('f2p_passed')}/{result.get('f2p_total')} " + f"p2p {result.get('p2p_passed')}/{result.get('p2p_total')}\n" + f"stop={ep.get('stop_reason')} turns={ep.get('turns')} " + f"calls={ep.get('tool_calls')} edits={ep.get('edits')} " + f"errors={ep.get('tool_errors')} nudges={ep.get('nudges')} truncated={ep.get('truncated_turns')} " + f"prompt_tokens={ep.get('prompt_tokens')} " + f"completion_tokens={ep.get('completion_tokens')} " + f"peak_ctx={ep.get('peak_context')}\n" + f"changed: {', '.join(result.get('changed_files') or []) or '(nothing)'}" + + (f"\nerror: {ep.get('error')}" if ep.get("error") else "") + ) + title = f"{task_id} ({result.get('task_id')})" + dataset = eval_state.loaded_dataset + assert isinstance(dataset, AgenticDataset) + try: + path = dataset.ae.write_transcript( + messages, self.transcript_dir / task_id, title, meta) + except OSError as e: + print(f"Warning: could not write transcript for {task_id}: {e}") + return + base = Path(eval_state.output_file).resolve().parent + result["transcript"] = os.path.relpath(path.resolve(), base) + @staticmethod def _worker( server_config: ServerConfig, @@ -1275,7 +2223,7 @@ def evaluate(self, eval_state: EvalState, verbose: bool = False, resume: bool = print(f" {i+1}. {sc.name} — {sc.url} ({sc.threads} threads) [{models_str}]") print(f"Model: {self.model_name}") print(f"Grader: {self.grader.grader_type}") - print(f"Sampling: temp={eval_state.sampling_config.get('temperature', 'skip')}, top-k={eval_state.sampling_config.get('top_k', 'skip')}, top-p={eval_state.sampling_config.get('top_p', 'skip')}, min-p={eval_state.sampling_config.get('min_p', 'skip')}") + print(f"Sampling: temp={eval_state.sampling_config.get('temperature', 'skip')}, top-k={eval_state.sampling_config.get('top_k', 'skip')}, top-p={eval_state.sampling_config.get('top_p', 'skip')}, min-p={eval_state.sampling_config.get('min_p', 'skip')}, reasoning-effort={eval_state.sampling_config.get('reasoning_effort', 'skip')}") print() # Shared task queue: all workers compete for tasks @@ -1342,6 +2290,79 @@ def evaluate(self, eval_state: EvalState, verbose: bool = False, resume: bool = eval_state.print_summary() eval_state.dump() +def preflight_sandbox(sandbox: Sandbox): + """Catch host policies that would fail problems for non-model reasons. + + A FIPS-enforcing OpenSSL makes hashlib.md5() raise, which would sink + HumanEval/162 no matter what the model generated. + """ + probe = sandbox.run("import hashlib; hashlib.md5(b'x').hexdigest()", timeout=15) + if not probe.passed: + print(f"Warning: md5 is unavailable in the execution venv " + f"({probe.summary(120)}). Problems that hash with md5 will fail " + f"regardless of the model -- this is a host policy, not a model result.") + + +def print_pass_at_k(eval_state: "EvalState"): + """Report pass@k plus a breakdown of how the failures failed. + + Each chunk is one full pass over the suite, so running --n_cases at a + multiple of the dataset size gives n samples per problem for free. + """ + cases = eval_state.task_states.get("cases", {}) + if not cases: + return + + by_problem: Dict[int, List[bool]] = {} + reasons: Dict[str, int] = {} + for case in cases.values(): + by_problem.setdefault(case.get("problem_idx", 0), []).append( + bool(case.get("correct", False)) + ) + if not case.get("correct", False): + status = (case.get("grader_log") or {}).get("status", case.get("status", "?")) + reasons[status] = reasons.get(status, 0) + 1 + + n = min(len(v) for v in by_problem.values()) + n_problems = len(by_problem) + + print(f"\n{'=' * 60}") + print(f" {eval_state.dataset_type}: {n_problems} problems, {n} sample(s) each") + print(f"{'=' * 60}") + + for k in sorted({1, 5, 10, 100, n}): + if k > n: + continue + score = sum( + pass_at_k(len(v), sum(v), k) for v in by_problem.values() + ) / n_problems + print(f" pass@{k:<4d} {score:.4f}") + + if n == 1: + solved = sum(1 for v in by_problem.values() if v[0]) + lo, hi = wilson_interval(solved, n_problems) + print(f" {solved}/{n_problems} solved 95% CI [{lo:.4f}, {hi:.4f}]") + + t_total = t_passed = 0 + for case in cases.values(): + log = case.get("grader_log") or {} + if "tests_total" in log: + t_total += log["tests_total"] + else: + try: + t_total += json.loads(case.get("expected") or "{}").get("n_tests", 0) + except ValueError: + pass + t_passed += log.get("tests_passed", 0) + if t_total: + print(f"\n test methods passed {t_passed}/{t_total} ({t_passed / t_total:.4f})") + + if reasons: + print("\n failures by cause:") + for status, count in sorted(reasons.items(), key=lambda kv: -kv[1]): + print(f" {status:<12s} {count}") + + def main(): parser = argparse.ArgumentParser( description="Simplified evaluation tool for llama.cpp" @@ -1358,13 +2379,28 @@ def main(): default="", help="Comma-separated display names for servers (default: use URLs)" ) + parser.add_argument( + "--api-key", + type=str, + default=None, + help="Bearer token for the eval servers: one key for all of them, or a " + "comma-separated key per --server (default: $LLAMA_API_KEY, else none)" + ) parser.add_argument( "--dataset", type=str, default="aime", - choices=["aime", "aime2025", "aime2026", "gsm8k", "gpqa"], + choices=["aime", "aime2025", "aime2026", "gsm8k", "gpqa", "humaneval", + "classeval", "agentic"], help="Dataset type (default: aime)" ) + parser.add_argument( + "--dataset-source", + type=str, + default=None, + help="Override the dataset location: a local .jsonl path or a HuggingFace " + "repo id (e.g. a patched HumanEval). Default: the suite's canonical repo" + ) parser.add_argument( "--n_cases", type=int, @@ -1407,6 +2443,25 @@ def main(): default=None, help="Min P sampling (default: not passed)" ) + parser.add_argument( + "--retries", + type=int, + default=5, + help="Times to resend a request that errors or comes back empty before " + "recording the case as a server error (default: 5)" + ) + parser.add_argument( + "--retry-delay", + type=float, + default=10.0, + help="Seconds to wait before the first resend; doubles on each further one (default: 10)" + ) + parser.add_argument( + "--reasoning-effort", + type=str, + default=None, + help="Reasoning effort sent as reasoning_effort with every request, e.g. low/medium/high (default: not passed)" + ) parser.add_argument( "--threads", type=str, @@ -1433,9 +2488,37 @@ def main(): parser.add_argument( "--grader-type", type=str, - default="llm", - choices=["regex", "cli", "llm"], - help="Grader type: regex, cli, or llm (default: llm)" + default=None, + choices=["regex", "cli", "llm", "exec"], + help="Grader type: regex, cli, llm, or exec (default: exec for code suites, " + "llm otherwise). 'exec' runs the generated code against the suite tests " + "in a sandboxed venv" + ) + parser.add_argument( + "--exec-timeout", + type=float, + default=None, + help="Per-problem wall-clock limit for the exec grader, in seconds " + "(default: per-suite, 15s for humaneval, 30s for classeval)" + ) + parser.add_argument( + "--exec-seed", + type=int, + default=0, + help="Seed the global RNG before running each test, so suites whose tests " + "draw random inputs score reproducibly (default: 0). Use -1 to leave " + "the RNG unseeded, matching the stock upstream harness" + ) + parser.add_argument( + "--sandbox-python", + type=str, + default=None, + help="Base interpreter used to build the execution venv (default: this one)" + ) + parser.add_argument( + "--rebuild-sandbox", + action="store_true", + help="Discard and re-provision the cached execution venv" ) parser.add_argument( "--grader-script", @@ -1455,6 +2538,51 @@ def main(): default="", help="Model name for LLM grader (default: same as main model)" ) + parser.add_argument( + "--grader-api-key", + type=str, + default=None, + help="Bearer token for the LLM grader server (default: the first " + "--api-key when the grader runs on the main server, else none)" + ) + parser.add_argument( + "--agentic-lang", + type=str, + default=None, + choices=["python", "typescript"], + help="Restrict the agentic suite to one language. Only that language's " + "toolchain is then provisioned." + ) + parser.add_argument( + "--agentic-max-turns", + type=int, + default=50, + help="Maximum assistant turns per agentic episode (default: 50)" + ) + parser.add_argument( + "--agentic-max-tokens", + type=int, + default=None, + help="Cap on generated tokens per agentic turn (default: no cap). " + "Bounds a model that falls into a repetition loop, but also cuts " + "off long reasoning; truncated turns are counted in the results." + ) + parser.add_argument( + "--agentic-context-limit", + type=int, + default=None, + help="Abandon an agentic episode once its context exceeds this many " + "tokens (default: no limit)" + ) + parser.add_argument( + "--agentic-transcripts", + type=Path, + default=None, + metavar="DIR", + help="Save each agentic episode's full message history to " + "DIR/.json, with a readable DIR/.html showing " + "every reasoning block, reply, tool call and tool result" + ) parser.add_argument( "--resume", action="store_true", @@ -1463,6 +2591,23 @@ def main(): args = parser.parse_args() + global DATASET_SOURCE, AGENTIC_OPTS + DATASET_SOURCE = args.dataset_source + AGENTIC_OPTS = { + "lang": args.agentic_lang, + "max_turns": args.agentic_max_turns, + "context_limit": args.agentic_context_limit, + "max_tokens": args.agentic_max_tokens, + } + + if args.grader_type is None: + args.grader_type = "exec" if args.dataset in CODE_SUITES else "llm" + + if args.grader_type == "exec" and args.dataset not in CODE_SUITES: + print(f"Error: --grader-type exec is only meaningful for code suites " + f"({', '.join(sorted(CODE_SUITES))}), not '{args.dataset}'") + sys.exit(1) + # Parse server URLs and thread counts server_urls = [u.strip() for u in args.server.split(",") if u.strip()] thread_counts = [int(t.strip()) for t in args.threads.split(",") if t.strip()] @@ -1480,11 +2625,30 @@ def main(): else: server_names = server_urls # fallback to URLs + api_key_arg = args.api_key if args.api_key is not None else os.environ.get("LLAMA_API_KEY") + if api_key_arg: + api_keys = [k.strip() for k in api_key_arg.split(",")] + if len(api_keys) == 1: + api_keys = api_keys * len(server_urls) + elif len(api_keys) != len(server_urls): + print(f"Error: --api-key ({len(api_keys)} keys) must be a single key or " + f"match --server ({len(server_urls)} URLs)") + sys.exit(1) + else: + api_keys = [None] * len(server_urls) + server_configs = [ - ServerConfig(url=url, threads=threads, name=name) - for url, threads, name in zip(server_urls, thread_counts, server_names) + ServerConfig(url=url, threads=threads, name=name, api_key=key) + for url, threads, name, key in zip(server_urls, thread_counts, server_names, api_keys) ] + if args.grader_api_key is not None: + grader_api_key = args.grader_api_key + else: + grader_url = args.grader_server or server_configs[0].url + grader_api_key = next( + (s.api_key for s in server_configs if s.url == grader_url), None) + if args.dataset == "gpqa" and args.grader_type != "llm": print("Error: GPQA dataset requires --grader-type llm") parser.print_help() @@ -1529,6 +2693,7 @@ def main(): grader_script=args.grader_script, grader_model_name=grader_model_name, grader_server_url=grader_server_url, + grader_api_key=grader_api_key, dataset_type=eval_state.dataset_type ) resume = True @@ -1548,6 +2713,7 @@ def main(): grader_script=args.grader_script, grader_model_name=grader_model_name, grader_server_url=grader_server_url, + grader_api_key=grader_api_key, dataset_type=args.dataset ) @@ -1563,6 +2729,8 @@ def main(): sampling_config["top_p"] = args.top_p if args.min_p is not None: sampling_config["min_p"] = args.min_p + if args.reasoning_effort is not None: + sampling_config["reasoning_effort"] = args.reasoning_effort eval_state = EvalState( dataset_type=args.dataset, @@ -1577,14 +2745,53 @@ def main(): eval_state.print_all_tasks() + if args.grader_type == "exec": + dataset = eval_state.loaded_dataset + + if dataset.is_agentic: + dataset.prepare(base_python=args.sandbox_python, + force=args.rebuild_sandbox) + else: + base_python = args.sandbox_python + want = dataset.preferred_python() + if not base_python and want: + base_python = resolve_python(want) + if base_python: + print(f"[sandbox] using Python {want} for " + f"{eval_state.dataset_type} ({base_python})") + + dataset.configure_python(base_python or sys.executable) + + sandbox = Sandbox( + name=eval_state.dataset_type, + packages=dataset.required_packages(), + provision=dataset.provision_steps(), + env=dataset.sandbox_env(), + base_python=base_python, + ) + sandbox.ensure(force=args.rebuild_sandbox) + preflight_sandbox(sandbox) + grader.sandbox = sandbox + grader.dataset = dataset + grader.exec_timeout = (args.exec_timeout if args.exec_timeout is not None + else dataset.default_exec_timeout()) + grader.exec_seed = None if args.exec_seed < 0 else args.exec_seed + processor = Processor( server_configs=server_configs, grader=grader, model_name=args.model, - n_predict=args.n_predict + n_predict=args.n_predict, + retries=args.retries, + retry_delay=args.retry_delay, + transcript_dir=args.agentic_transcripts, ) processor.evaluate(eval_state, verbose=args.verbose, resume=resume) + + if args.grader_type == "exec": + print_pass_at_k(eval_state) + print(f"\nEval state dumped to {args.output}") if __name__ == "__main__": diff --git a/examples/llama-eval/llama-server-simulator.py b/examples/llama-eval/llama-server-simulator.py index e64ba89335d9..dbd46d67f476 100755 --- a/examples/llama-eval/llama-server-simulator.py +++ b/examples/llama-eval/llama-server-simulator.py @@ -13,8 +13,6 @@ from dataclasses import dataclass from pathlib import Path -import datasets - # Set cache directory for HuggingFace datasets cache_dir = Path.home() / ".cache" / "huggingface" / "datasets" cache_dir.mkdir(parents=True, exist_ok=True) @@ -76,6 +74,8 @@ def _get_question_text(self, question: Dict) -> str: return question.get("problem", question.get("question", "")) def _load_dataset(self): + import datasets + if self.dataset_type == "aime": print(f"Loading AIME dataset (split: {self.split})...") cache_path = Path.home() / ".cache" / "huggingface" / "datasets" / "AI-MO___aimo-validation-aime" / "default" / "0.0.0" @@ -164,6 +164,58 @@ def get_answer(self, question: Dict) -> str: return str(normalized) if normalized is not None else answer return str(answer) +class CodeDataset: + """Stand-in for a code model: replays canonical solutions as chat replies. + + Handles both code suites: HumanEval keys off the function stub, ClassEval + off the class skeleton. + """ + + DEFAULT_SOURCE = { + "humaneval": "openai/openai_humaneval", + "classeval": "FudanSELab/ClassEval", + } + + def __init__(self, dataset_type: str, source: Optional[str] = None): + self.dataset_type = dataset_type + self.source = source or self.DEFAULT_SOURCE[dataset_type] + self.questions: List[Dict] = [] + self._load_dataset() + + def _load_dataset(self): + print(f"Loading {self.dataset_type} dataset (source: {self.source})...") + local = Path(self.source) + if local.exists(): + text = local.read_text() + if local.suffix == ".json": + rows = json.loads(text) + else: + rows = [json.loads(ln) for ln in text.splitlines() if ln.strip()] + else: + import datasets + rows = [dict(r) for r in datasets.load_dataset(self.source, split="test")] + self.questions = rows + print(f"{self.dataset_type} dataset loaded: {len(self.questions)} questions") + + def _stub_field(self) -> str: + return "skeleton" if self.dataset_type == "classeval" else "prompt" + + def _get_question_text(self, question: Dict) -> str: + return question[self._stub_field()] + + def find_question(self, request_text: str) -> Optional[Dict]: + for question in self.questions: + stub = question[self._stub_field()].rstrip() + if stub and stub in request_text: + return question + return None + + def get_answer(self, question: Dict) -> str: + if self.dataset_type == "classeval": + return question["solution_code"] + return question["prompt"] + question["canonical_solution"] + + class Simulator: def __init__( self, @@ -171,12 +223,17 @@ def __init__( host: str = "localhost", success_rate: float = 0.8, dataset_split: str = "train", - dataset_type: str = "aime" + dataset_type: str = "aime", + dataset_source: Optional[str] = None ): self.port = port self.host = host self.success_rate = success_rate - self.dataset = AimeDataset(dataset_split, dataset_type) + self.dataset_type = dataset_type + if dataset_type in ("humaneval", "classeval"): + self.dataset = CodeDataset(dataset_type, dataset_source) + else: + self.dataset = AimeDataset(dataset_split, dataset_type) self.eval_state = EvalState( id=dataset_type, tasks=[dataset_type], @@ -196,6 +253,12 @@ def _generate_response( else: response_text = self._generate_wrong_answer(question) + if self.dataset_type in ("humaneval", "classeval"): + response_text = ( + f"Here is the implementation:\n\n```python\n{response_text}\n```\n\n" + "Let me know if you want it optimised further." + ) + comp_tokens = random.randint(10000, 60000) tps_gen = random.uniform(90.0, 110.0) t_gen_ms = comp_tokens / tps_gen * 1000 @@ -229,6 +292,12 @@ def _generate_response( def _generate_wrong_answer(self, question: Dict) -> str: expected_answer = self.dataset.get_answer(question) + if self.dataset_type == "classeval": + return re.sub(r"(\n\s+def [^\n]+:\n)", r"\1 return None\n", + question["skeleton"]) + if self.dataset_type == "humaneval": + return question["prompt"] + " return None\n" + if expected_answer.isdigit(): wrong_answer = str(int(expected_answer) + 1) else: @@ -335,7 +404,7 @@ def main(): "--dataset", type=str, default="aime", - choices=["aime", "aime2025"], + choices=["aime", "aime2025", "humaneval", "classeval"], help="Dataset type (default: aime)" ) parser.add_argument( @@ -344,6 +413,12 @@ def main(): default="train", help="AIME dataset split to use (default: train)" ) + parser.add_argument( + "--dataset-source", + type=str, + default=None, + help="Override the dataset location (local .jsonl path or HuggingFace repo id)" + ) args = parser.parse_args() @@ -353,7 +428,8 @@ def main(): host=args.host, success_rate=args.success_rate, dataset_split=args.dataset_split, - dataset_type=args.dataset + dataset_type=args.dataset, + dataset_source=args.dataset_source ) server = HTTPServer((args.host, args.port), RequestHandler) diff --git a/examples/realtime_client.py b/examples/realtime_client.py new file mode 100644 index 000000000000..3b806fab3d0e --- /dev/null +++ b/examples/realtime_client.py @@ -0,0 +1,211 @@ +#!/usr/bin/env python3 +"""Example client for the llama-server /v1/realtime websocket, with the openai SDK. + +Start a server with an audio model, e.g. LFM3-Audio: + + llama-server -hf LiquidAI/LFM3-Audio-2B-GGUF + +Spoken conversation, the audio of each wav file is one user turn. It is sent in chunks as it would come from a +microphone, the server prefills it as it arrives so the response starts right after the last chunk: + + python examples/realtime_client.py --instructions "Respond with interleaved text and audio." question.wav + +Output modalities: left out, the model picks; "text", "audio" or "text,audio" (interleaved) force the response. +Without --instructions, a forced mode comes with the system prompt of the LFM3-Audio or LFM3-Omni model card: + + python examples/realtime_client.py --output-modalities text,audio --out answer.wav question.wav + +Tool calls: --tools gives the conversation a demo tool, the client runs its calls and sends the results back: + + python examples/realtime_client.py --tools --text "Set the volume to 30." + +Text turns go in with --text, transcription sessions transcribe each file: + + python examples/realtime_client.py --text "What is the capital of France?" + python examples/realtime_client.py --type transcription --language en speech.wav + +Live transcription models (Voxtral Realtime, LFM3-Audio live ASR) transcribe while the audio is sent, a transcription +session opens with ?intent=transcription: + + python examples/realtime_client.py --type transcription speech.wav + +Requirements: pip install "openai[realtime]" numpy +""" + +import argparse +import asyncio +import base64 +import json +import time +import wave + +import numpy as np +from openai import AsyncOpenAI + + +# system prompts of the LiquidAI/LFM3-Audio-2B and LiquidAI/LFM3-Omni-2B model cards for a forced output mode +MODE_INSTRUCTIONS = { + "audio": {"text,audio": "Respond with interleaved text and audio."}, + "omni": {"text": "Respond in text.", "text,audio": "Respond in interleaved text and audio."}, +} +# and with tools: calls, or an answer in interleaved text and speech +TOOLS_INSTRUCTIONS = "Respond with function calls, and interleaved text and audio.\n\nList of tools:" + +# the demo tool of --tools +DEMO_TOOLS = [{ + "type": "function", + "name": "set_volume", + "description": "Set the device speaker volume.", + "parameters": { + "type": "object", + "properties": {"volume": {"type": "integer", "description": "Volume from 0 to 100."}}, + "required": ["volume"], + }, +}] + + +def run_tool(name, arguments): + if name == "set_volume": + return {"volume": json.loads(arguments)["volume"]} + return {"error": f"unknown tool {name}"} + + +def read_wav(path, rate): + # PCM16 wav -> mono int16 at the given rate + with wave.open(path, "rb") as f: + assert f.getsampwidth() == 2, "the example reads PCM16 wav files" + x = np.frombuffer(f.readframes(f.getnframes()), dtype=np.int16).astype(np.float32) + x = x.reshape(-1, f.getnchannels()).mean(axis=1) + sr = f.getframerate() + if sr != rate: + n = int(round(len(x) * rate / sr)) + x = np.interp(np.arange(n) * sr / rate, np.arange(len(x)), x) + return np.clip(x, -32768, 32767).astype(np.int16) + + +def write_wav(path, pcm, rate): + with wave.open(path, "wb") as f: + f.setnchannels(1) + f.setsampwidth(2) + f.setframerate(rate) + f.writeframes(pcm.tobytes()) + + +async def main(args): + # the SDK derives a wss:// URL from base_url, a plain http server needs ws:// + client = AsyncOpenAI(base_url=args.url, api_key=args.api_key, websocket_base_url=args.url.replace("http", "ws", 1)) + query = {"intent": "transcription"} if args.type == "transcription" else {} + async with client.realtime.connect(model=args.model, extra_query=query) as conn: + ev = await conn.recv() + if ev.type == "error": + print("error:", ev.error.message) + return + # the audio goes in at the rate of the model, PCM16 mono + session_info = ev.model_dump(warnings=False)["session"] + audio_fmt = session_info["audio"] + card = "omni" if "omni" in str(session_info.get("model", "")).lower() else "audio" + in_rate = audio_fmt["input"]["format"]["rate"] + out_rate = (audio_fmt.get("output") or {}).get("format", {}).get("rate", 24000) + + session = {"type": args.type} + if args.type == "realtime": + instructions = args.instructions + if instructions is None: + instructions = TOOLS_INSTRUCTIONS if args.tools else MODE_INSTRUCTIONS[card].get(args.output_modalities) + if args.tools: + session["tools"] = DEMO_TOOLS + if instructions is not None: + session["instructions"] = instructions + if args.output_modalities: + session["output_modalities"] = args.output_modalities.split(",") + elif args.language: + session["audio"] = {"input": {"transcription": {"language": args.language}}} + await conn.session.update(session=session) # ty: ignore[invalid-argument-type] + ev = await conn.recv() + if ev.type == "error": + print("error:", ev.error.message) + return + + turns = [("audio", path) for path in args.wav] + [("text", text) for text in args.text] + for i, (kind, src) in enumerate(turns): + t_last = 0.0 + + # the input is sent while the events are read: live transcription arrives while the audio is sent + async def send_turn(): + nonlocal t_last + if kind == "audio": + pcm = read_wav(src, in_rate) + step = in_rate * args.chunk_ms // 1000 + for j in range(0, len(pcm), step): + chunk = pcm[j:j + step] + await conn.input_audio_buffer.append(audio=base64.b64encode(chunk.tobytes()).decode()) + if args.realtime: + await asyncio.sleep(len(chunk) / in_rate) + if args.type == "transcription": + # "final" ends the input, models that transcribe with a delay then complete the last item + await conn.send({"type": "input_audio_buffer.commit", "final": i == len(args.wav) - 1}) # ty: ignore[invalid-argument-type] + else: + await conn.conversation.item.create(item={ + "type": "message", "role": "user", "content": [{"type": "input_text", "text": src}]}) + if args.type == "realtime": + # the audio not committed yet ends the user turn + await conn.response.create() + t_last = time.perf_counter() + + print(f"--- turn {i} ({kind}: {src})") + sender = asyncio.create_task(send_turn()) + t_first = None + audio = [] + async for ev in conn: + if ev.type == "response.output_text.delta" or ev.type == "conversation.item.input_audio_transcription.delta": + t_first = t_first or time.perf_counter() + print(ev.delta, end="", flush=True) + elif ev.type == "response.output_audio.delta": + t_first = t_first or time.perf_counter() + audio.append(np.frombuffer(base64.b64decode(ev.delta), dtype=np.int16)) + elif ev.type == "response.done": + # the calls of the response are run, their results go back and the model answers them + calls = [o for o in ev.model_dump()["response"]["output"] if o["type"] == "function_call"] + for call in calls: + result = json.dumps(run_tool(call["name"], call["arguments"])) + print(f"\n[call {call['name']}({call['arguments']}) -> {result}]", flush=True) + await conn.conversation.item.create(item={ + "type": "function_call_output", "call_id": call["call_id"], "output": result}) + if not calls: + break + await conn.response.create() + elif ev.type == "conversation.item.input_audio_transcription.completed": + break + elif ev.type == "error": + print("\nerror:", ev.error.message) + return + await sender + print() + if t_first is not None and t_first > t_last: + print(f"first output {1000 * (t_first - t_last):.0f} ms after the end of the input") + elif t_first is not None: + print(f"output started {1000 * (t_last - t_first):.0f} ms before the end of the input, " + f"done {1000 * (time.perf_counter() - t_last):.0f} ms after it") + if audio: + pcm_out = np.concatenate(audio) + path = f"{args.out.removesuffix('.wav')}_{i}.wav" if len(turns) > 1 else args.out + write_wav(path, pcm_out, out_rate) + print(f"audio: {len(pcm_out) / out_rate:.2f} s -> {path}") + + +if __name__ == "__main__": + p = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) + p.add_argument("wav", nargs="*", help="PCM16 wav files, one user turn each") + p.add_argument("--text", action="append", default=[], help="a user turn as text, after the audio turns, repeatable") + p.add_argument("--type", choices=["realtime", "transcription"], default="realtime", help="session type") + p.add_argument("--instructions", help="system prompt of the conversation") + p.add_argument("--tools", action="store_true", help="give the conversation a demo tool (set_volume), its calls are run") + p.add_argument("--output-modalities", choices=["text", "audio", "text,audio"], help="default: the model picks") + p.add_argument("--language", help="transcription language, e.g. en") + p.add_argument("--chunk-ms", type=int, default=100, help="audio chunk size") + p.add_argument("--realtime", action=argparse.BooleanOptionalAction, default=True, help="send the audio in real time") + p.add_argument("--out", default="response.wav", help="where the audio of the responses goes") + p.add_argument("--url", default="http://127.0.0.1:9931/v1") + p.add_argument("--api-key", default="none") + p.add_argument("--model", default="default", help="model name, used by the router") + asyncio.run(main(p.parse_args())) diff --git a/examples/sycl/build.sh b/examples/sycl/build.sh index bec96886b19d..dc9e44a8ea28 100755 --- a/examples/sycl/build.sh +++ b/examples/sycl/build.sh @@ -4,15 +4,18 @@ # SPDX-License-Identifier: MIT print_usage() { - echo "Usage: ./build.sh [fp32|fp16] [--help]" + echo "Usage: ./build.sh [fp32|fp16] [ssl|nossl] [--help]" echo "" echo "Options:" echo " fp32 Build with FP32 precision (default)" echo " fp16 Build with FP16 precision (faster for long-prompt inference)" + echo " ssl Build with OpenSSL (default)" + echo " nossl Build without OpenSSL" echo " --help Print this help message" } PRECISION=fp32 +SSL=ON for arg in "$@"; do case "$arg" in @@ -23,6 +26,12 @@ for arg in "$@"; do fp32|fp16) PRECISION="$arg" ;; + ssl) + SSL=ON + ;; + nossl) + SSL=OFF + ;; *) echo "Error: unknown option '$arg'" print_usage @@ -37,10 +46,13 @@ source /opt/intel/oneapi/setvars.sh if [ "$PRECISION" = "fp16" ]; then #for FP16 - cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DGGML_SYCL_F16=ON -DLLAMA_OPENSSL=ON # faster for long-prompt inference + echo "cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DGGML_SYCL_F16=ON -DLLAMA_OPENSSL=$SSL # faster for long-prompt inference +" + cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DGGML_SYCL_F16=ON -DLLAMA_OPENSSL="$SSL" # faster for long-prompt inference else #for FP32 - cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DLLAMA_OPENSSL=ON + echo "cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DLLAMA_OPENSSL=$SSL" + cmake .. -DGGML_SYCL=ON -DCMAKE_C_COMPILER=icx -DCMAKE_CXX_COMPILER=icpx -DLLAMA_OPENSSL="$SSL" fi #build example/main @@ -50,4 +62,5 @@ fi #cmake --build . --config Release --target llama-bench #build all binary +echo "cmake --build . --config Release -j$((($(nproc)+1)/2)) -v" cmake --build . --config Release -j$((($(nproc)+1)/2)) -v diff --git a/examples/sycl/win-build-sycl.bat b/examples/sycl/win-build-sycl.bat index 9a82edbefe62..4b3906a6371f 100644 --- a/examples/sycl/win-build-sycl.bat +++ b/examples/sycl/win-build-sycl.bat @@ -3,23 +3,62 @@ :: Copyright (C) 2024 Intel Corporation :: SPDX-License-Identifier: MIT -IF /I "%1"=="--help" ( - echo Usage: win-build-sycl.bat [fp32^|fp16] [--help] - echo. - echo Options: - echo fp32 Build with FP32 precision ^(default^) - echo fp16 Build with FP16 precision ^(faster for long-prompt inference^) - echo --help Print this help message - exit /B 0 -) +SET "PRECISION=fp32" +SET "SSL=ON" +SET "OPENSSL_OPTION=" -SET PRECISION=%1 -IF "%PRECISION%"=="" SET PRECISION=fp32 -IF /I NOT "%PRECISION%"=="fp32" IF /I NOT "%PRECISION%"=="fp16" ( - echo Error: invalid value '%PRECISION%'. Use 'fp32' or 'fp16'. - echo Usage: win-build-sycl.bat [fp32^|fp16] [--help] - exit /B 1 -) +:PARSE_ARGS +IF "%~1"=="" GOTO ARGS_DONE +IF /I "%~1"=="--help" GOTO HELP +IF /I "%~1"=="fp32" GOTO ARG_FP32 +IF /I "%~1"=="fp16" GOTO ARG_FP16 +IF /I "%~1"=="ssl" GOTO ARG_SSL +IF /I "%~1"=="nossl" GOTO ARG_NOSSL +GOTO INVALID_ARG + +:ARG_FP32 +SET "PRECISION=fp32" +GOTO NEXT_ARG + +:ARG_FP16 +SET "PRECISION=fp16" +GOTO NEXT_ARG + +:ARG_SSL +SET "SSL=ON" +SET "OPENSSL_OPTION=" +GOTO NEXT_ARG + +:ARG_NOSSL +SET "SSL=OFF" +SET "OPENSSL_OPTION=-DLLAMA_OPENSSL=OFF" +GOTO NEXT_ARG + +:NEXT_ARG +SHIFT +GOTO PARSE_ARGS + +:HELP +SET "ARG_ERROR=0" +GOTO PRINT_USAGE + +:INVALID_ARG +SET "ARG_ERROR=1" +echo Error: unknown option '%~1' + +:PRINT_USAGE +echo Usage: win-build-sycl.bat [fp32^|fp16] [ssl^|nossl] [--help] +echo. +echo Options: +echo fp32 Build with FP32 precision ^(default^) +echo fp16 Build with FP16 precision ^(faster for long-prompt inference^) +echo ssl Build with BoringSSL ^(default^) +echo nossl Build without BoringSSL +echo --help Print this help message +IF "%ARG_ERROR%"=="1" exit /B 1 +exit /B 0 + +:ARGS_DONE IF not exist build (mkdir build) cd build @@ -31,10 +70,10 @@ if %errorlevel% neq 0 goto ERROR IF /I "%PRECISION%"=="fp16" ( :: for FP16 :: faster for long-prompt inference - cmake -G "MinGW Makefiles" .. -DLLAMA_OPENSSL=OFF -DGGML_SYCL=ON -DCMAKE_CXX_COMPILER=icx -DBUILD_SHARED_LIBS=ON -DCMAKE_BUILD_TYPE=Release -DGGML_SYCL_F16=ON + cmake -G "MinGW Makefiles" .. -DLLAMA_BUILD_BORINGSSL=%SSL% %OPENSSL_OPTION% -DGGML_SYCL=ON -DCMAKE_CXX_COMPILER=icx -DBUILD_SHARED_LIBS=ON -DCMAKE_BUILD_TYPE=Release -DGGML_SYCL_F16=ON ) ELSE ( :: for FP32 - cmake -G "Ninja" .. -DLLAMA_OPENSSL=OFF -DGGML_SYCL=ON -DCMAKE_C_COMPILER=cl -DCMAKE_CXX_COMPILER=icx -DBUILD_SHARED_LIBS=ON -DCMAKE_BUILD_TYPE=Release + cmake -G "Ninja" .. -DLLAMA_BUILD_BORINGSSL=%SSL% %OPENSSL_OPTION% -DGGML_SYCL=ON -DCMAKE_C_COMPILER=cl -DCMAKE_CXX_COMPILER=icx -DBUILD_SHARED_LIBS=ON -DCMAKE_BUILD_TYPE=Release ) if %errorlevel% neq 0 goto ERROR diff --git a/ggml/CMakeLists.txt b/ggml/CMakeLists.txt index be04143cfb91..4e127a59b38a 100644 --- a/ggml/CMakeLists.txt +++ b/ggml/CMakeLists.txt @@ -4,7 +4,7 @@ project("ggml" C CXX ASM) ### GGML Version set(GGML_VERSION_MAJOR 0) -set(GGML_VERSION_MINOR 26) +set(GGML_VERSION_MINOR 28) set(GGML_VERSION_PATCH 0) set(GGML_VERSION_BASE "${GGML_VERSION_MAJOR}.${GGML_VERSION_MINOR}.${GGML_VERSION_PATCH}") @@ -252,6 +252,7 @@ option(GGML_OPENMP_FETCH "ggml: fetch LLVM OpenMP" option(GGML_RPC "ggml: use RPC" OFF) option(GGML_SYCL "ggml: use SYCL" OFF) option(GGML_SYCL_F16 "ggml: use 16 bit floats for sycl calculations" OFF) +option(GGML_SYCL_SUPPORT_XMX "ggml: build the XMX (DPAS) code paths in the SYCL backend" ON) option(GGML_SYCL_GRAPH "ggml: enable graphs in the SYCL backend" ON) option(GGML_SYCL_HOST_MEM_FALLBACK "ggml: allow host memory fallback in SYCL reorder (requires kernel 6.8+)" ON) option(GGML_SYCL_SUPPORT_LEVEL_ZERO_API "ggml: use Level Zero API in SYCL backend" ON) diff --git a/ggml/cmake/common.cmake b/ggml/cmake/common.cmake index f3610298ffb8..42b65a58051c 100644 --- a/ggml/cmake/common.cmake +++ b/ggml/cmake/common.cmake @@ -2,10 +2,16 @@ function(ggml_get_flags CCID CCVER) set(C_FLAGS "") set(CXX_FLAGS "") - if (CCID MATCHES "Clang") + if (CCID MATCHES "Clang" OR CCID MATCHES "IntelLLVM") set(C_FLAGS -Wunreachable-code-break -Wunreachable-code-return) set(CXX_FLAGS -Wunreachable-code-break -Wunreachable-code-return -Wmissing-prototypes -Wextra-semi) + if (CCID STREQUAL "IntelLLVM") + # for Intel DPC++ and LLVM SYCL, using debug does not disable optimization + list(APPEND C_FLAGS -Rno-debug-disables-optimization) + list(APPEND CXX_FLAGS -Rno-debug-disables-optimization) + endif() + if ( (CCID STREQUAL "Clang" AND CCVER VERSION_GREATER_EQUAL 3.8.0) OR (CCID STREQUAL "AppleClang" AND CCVER VERSION_GREATER_EQUAL 7.3.0) diff --git a/ggml/include/ggml-backend.h b/ggml/include/ggml-backend.h index 7a65d8121b1c..735ed2c2b017 100644 --- a/ggml/include/ggml-backend.h +++ b/ggml/include/ggml-backend.h @@ -70,7 +70,8 @@ extern "C" { GGML_API void ggml_backend_buffer_reset (ggml_backend_buffer_t buffer); // tensor copy between different backends - GGML_API void ggml_backend_tensor_copy(const struct ggml_tensor * src, struct ggml_tensor * dst); + GGML_API void ggml_backend_tensor_copy (const struct ggml_tensor * src, struct ggml_tensor * dst); + GGML_API void ggml_backend_tensor_copy_n(const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors); // // Backend (stream) @@ -95,6 +96,8 @@ extern "C" { GGML_API void ggml_backend_tensor_get (const struct ggml_tensor * tensor, void * data, size_t offset, size_t size); GGML_API void ggml_backend_tensor_set_2d( struct ggml_tensor * tensor, const void * data, size_t offset, size_t size, size_t n_copies, size_t stride_tensor, size_t stride_data); GGML_API void ggml_backend_tensor_get_2d(const struct ggml_tensor * tensor, void * data, size_t offset, size_t size, size_t n_copies, size_t stride_tensor, size_t stride_data); + GGML_API void ggml_backend_tensor_set_n ( struct ggml_tensor * const * tensors, const void * data, const size_t * offsets, const size_t * sizes, const size_t * data_offsets, size_t n_tensors); + GGML_API void ggml_backend_tensor_get_n (const struct ggml_tensor * const * tensors, void * data, const size_t * offsets, const size_t * sizes, const size_t * data_offsets, size_t n_tensors); GGML_API void ggml_backend_tensor_memset( struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size); GGML_API void ggml_backend_synchronize(ggml_backend_t backend); diff --git a/ggml/include/ggml-rpc.h b/ggml/include/ggml-rpc.h index 482bd3666d1c..ecf0a3a6dc25 100644 --- a/ggml/include/ggml-rpc.h +++ b/ggml/include/ggml-rpc.h @@ -8,10 +8,10 @@ extern "C" { #define RPC_PROTO_MAJOR_VERSION 8 #define RPC_PROTO_MINOR_VERSION 0 -#define RPC_PROTO_PATCH_VERSION 0 +#define RPC_PROTO_PATCH_VERSION 1 #ifdef __cplusplus -static_assert(GGML_OP_COUNT == 101, "GGML_OP_COUNT has changed - update RPC_PROTO_PATCH_VERSION"); +static_assert(GGML_OP_COUNT == 102, "GGML_OP_COUNT has changed - update RPC_PROTO_PATCH_VERSION"); #endif #define GGML_RPC_MAX_SERVERS 16 diff --git a/ggml/include/ggml.h b/ggml/include/ggml.h index b14ef1730dac..d9967a46b03e 100644 --- a/ggml/include/ggml.h +++ b/ggml/include/ggml.h @@ -381,6 +381,8 @@ extern "C" { GGML_API void ggml_fp32_to_bf16_row_ref(const float *, ggml_bf16_t *, int64_t); GGML_API void ggml_fp32_to_bf16_row(const float *, ggml_bf16_t *, int64_t); + typedef struct { uint8_t bits; } ggml_fp8_e4m3_t; + struct ggml_object; struct ggml_context; struct ggml_cgraph; @@ -430,6 +432,7 @@ extern "C" { GGML_TYPE_NVFP4 = 40, // NVFP4 (4 blocks, E4M3 scale) GGML_TYPE_Q1_0 = 41, GGML_TYPE_Q2_0 = 42, + GGML_TYPE_F8_E4M3 = 43, GGML_TYPE_Q4_0_ROCMFP4 = 100, // ROCmFP4 experimental UE4M3 scales + packed AMD FP4 blocks GGML_TYPE_Q4_0_ROCMFP4_FAST = 101, // ROCmFP4 single-scale speed layout GGML_TYPE_COUNT = 102, @@ -488,6 +491,7 @@ extern "C" { GGML_FTYPE_MOSTLY_NVFP4 = 26, // except 1d tensors GGML_FTYPE_MOSTLY_Q1_0 = 27, // except 1d tensors GGML_FTYPE_MOSTLY_Q2_0 = 28, // except 1d tensors + GGML_FTYPE_MOSTLY_F8_E4M3 = 29, // except 1d tensors GGML_FTYPE_MOSTLY_Q4_0_ROCMFP4 = 100, // except 1d tensors GGML_FTYPE_MOSTLY_Q4_0_ROCMFP4_LEAN = 101, // ROCmFP4 with Q5_K token embeddings GGML_FTYPE_MOSTLY_Q4_0_ROCMFP4_COHERENT = 102, // ROCmFP4 with Q6_K token embeddings @@ -594,6 +598,7 @@ extern "C" { GGML_OP_DSV4_HC_COMB, GGML_OP_DSV4_HC_PRE, GGML_OP_DSV4_HC_POST, + GGML_OP_TOP_K_MASK, GGML_OP_UNARY, @@ -935,6 +940,7 @@ extern "C" { enum ggml_type type); // dst[i0, i1, i2] = a[i0, i1, i2] + b[i0, ids[i1, i2]] + // an id of -1 adds nothing: dst[i0, i1, i2] = a[i0, i1, i2] GGML_API struct ggml_tensor * ggml_add_id( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1486,6 +1492,16 @@ extern "C" { enum ggml_prec prec, int idx); + // [TAG_GGML_PREC] + // get the accumulator / src[idx] precision set by the functions above + // return GGML_PREC_UNDEFINED when the op does not carry the requested precision + GGML_API enum ggml_prec ggml_prec_get_acc( + const struct ggml_tensor * a); + + GGML_API enum ggml_prec ggml_prec_get_src( + const struct ggml_tensor * a, + int idx); + // A: k columns, n rows => [ne03, ne02, n, k] // B: k columns, m rows (i.e. we transpose it internally) => [ne03 * x, ne02 * y, m, k] // result is n columns, m rows => [ne03 * x, ne02 * y, m, n] @@ -1507,6 +1523,7 @@ extern "C" { enum ggml_op_hint hint); // indirect matrix multiplication + // an id of -1 skips the slot and zeroes the matching row of the result // // [TAG_MUL_MAT_ID_DUPLICATE_ID] // note: this op has undefined behaviour if a given `a` is referenced more than once for a given `b` @@ -2509,6 +2526,24 @@ extern "C" { float max_bias, float logit_softcap); + // same as ggml_flash_attn_ext, but each q slice attends to its own list of K/V rows + // q: [n_embd_k, n_batch, n_head, ne3] + // k: [n_embd_k, n_rows, n_head_kv, 1 ] shared by all q slices + // v: [n_embd_v, n_rows, n_head_kv, 1 ] + // mask: [n_kv, n_batch, ne32, ne3] + // kv_rows: [n_kv, ne3] I32, mask column i of slice i3 uses row kv_rows[i, i3] of k and v + // negative rows are padding, their mask entries must be -inf + GGML_API struct ggml_tensor * ggml_flash_attn_ext_rows( + struct ggml_context * ctx, + struct ggml_tensor * q, + struct ggml_tensor * k, + struct ggml_tensor * v, + struct ggml_tensor * mask, + struct ggml_tensor * kv_rows, + float scale, + float max_bias, + float logit_softcap); + GGML_DEPRECATED(GGML_API void ggml_flash_attn_ext_set_prec( struct ggml_tensor * a, enum ggml_prec prec), @@ -2758,6 +2793,26 @@ extern "C" { struct ggml_tensor * post, struct ggml_tensor * comb); + // top-k sparse attention mask: keep the mask cells of the live picks and the extra cells, set the rest to -inf + // + // mask: [n_kv, m1, m2, m3] f16 or f32, broadcast to the rows of top_k + // top_k: [n_top, ne1, ne2, ne3] i32, picks of each row + // score: [n_pick, ne1, ne2, ne3] f32, can be NULL: a pick is live when its score is above -inf, else every pick is live + // blocks: [n_blk, n_pick] i32, can be NULL: the member cells of each pick, else a pick is a cell + // extra: [n_extra, ne1, ne2, ne3] i32, can be NULL: cells of each row kept without a pick + // res: [n_kv, ne1, ne2, ne3] same type as mask + // + // res[c, i] = mask[c, i % m] when c is a cell of a live pick of row i or an extra cell of row i, else -inf + // picks and cells out of range are skipped + // + GGML_API struct ggml_tensor * ggml_top_k_mask( + struct ggml_context * ctx, + struct ggml_tensor * mask, + struct ggml_tensor * top_k, + struct ggml_tensor * score, + struct ggml_tensor * blocks, + struct ggml_tensor * extra); + // custom operators typedef void (*ggml_custom1_op_t)(struct ggml_tensor * dst , const struct ggml_tensor * a, int ith, int nth, void * userdata); diff --git a/ggml/src/ggml-backend-impl.h b/ggml/src/ggml-backend-impl.h index dc7367dec4fe..545880b068c7 100644 --- a/ggml/src/ggml-backend-impl.h +++ b/ggml/src/ggml-backend-impl.h @@ -47,6 +47,9 @@ extern "C" { // Backend buffer // + // TODO: remove `set_tensor`, `get_tensor`, `set_tensor_2d`, `get_tensor_2d` and `cpy_tensor` from the buffer interface + // they are superseded by the `set_tensor_n`, `get_tensor_n`, `cpy_tensor_n` interface + // ref: https://github.com/ggml-org/llama.cpp/pull/30881#discussion_r4400299490 struct ggml_backend_buffer_i { // (optional) free the buffer void (*free_buffer) (ggml_backend_buffer_t buffer); @@ -68,6 +71,11 @@ extern "C" { void (*clear) (ggml_backend_buffer_t buffer, uint8_t value); // (optional) reset any internal state due to tensor initialization, such as tensor extras void (*reset) (ggml_backend_buffer_t buffer); + // (optional) batched tensor data copies + void (*set_tensor_n) (ggml_backend_buffer_t buffer, struct ggml_tensor * const * tensors, const void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors); + void (*get_tensor_n) (ggml_backend_buffer_t buffer, const struct ggml_tensor * const * tensors, void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors); + // (optional) batched tensor copies: returns true if all copies were performed, false if unsupported and no copies were performed + bool (*cpy_tensor_n) (ggml_backend_buffer_t buffer, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors); }; struct ggml_backend_buffer { diff --git a/ggml/src/ggml-backend-meta.cpp b/ggml/src/ggml-backend-meta.cpp index f97cf37bb31e..d7636d68ddf5 100644 --- a/ggml/src/ggml-backend-meta.cpp +++ b/ggml/src/ggml-backend-meta.cpp @@ -1055,7 +1055,8 @@ static struct ggml_backend_meta_split_state ggml_backend_meta_get_split_state( } break; case GGML_OP_DSV4_HC_COMB: case GGML_OP_DSV4_HC_PRE: - case GGML_OP_DSV4_HC_POST: { + case GGML_OP_DSV4_HC_POST: + case GGML_OP_TOP_K_MASK: { split_state = handle_generic(src_ss, /*scalar_only =*/ true); } break; case GGML_OP_UNARY: { @@ -1707,6 +1708,9 @@ static const ggml_backend_buffer_i ggml_backend_meta_buffer_iface = { /* .cpy_tensor = */ nullptr, /* .clear = */ ggml_backend_meta_buffer_clear, /* .reset = */ ggml_backend_meta_buffer_reset, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; bool ggml_backend_buffer_is_meta(ggml_backend_buffer_t buf) { diff --git a/ggml/src/ggml-backend.cpp b/ggml/src/ggml-backend.cpp index ffbcba3661cf..3520b434918d 100644 --- a/ggml/src/ggml-backend.cpp +++ b/ggml/src/ggml-backend.cpp @@ -402,6 +402,62 @@ size_t ggml_backend_get_max_size(ggml_backend_t backend) { return ggml_backend_buft_get_max_size(ggml_backend_get_default_buffer_type(backend)); } +template +static void ggml_backend_tensor_buft_groups(size_t n_tensors, cb_get_buffer && get_buffer, std::vector> & groups) { + std::unordered_map buft_idx; + groups.clear(); + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_buffer_t buf = get_buffer(i); + auto it = buft_idx.find(buf->buft); + if (it == buft_idx.end()) { + buft_idx[buf->buft] = groups.size(); + groups.emplace_back(); + } + groups[buft_idx[buf->buft]].push_back(i); + } +} + +static bool ggml_backend_tensor_batch_is_2d( + const struct ggml_tensor * const * tensors, + const size_t * offsets, + const size_t * sizes, + const size_t * data_offsets, + size_t n_tensors, + size_t * base_offset, + size_t * size, + size_t * stride_tensor, + size_t * stride_data) { + if (n_tensors <= 1) { + return false; + } + + const struct ggml_tensor * tensor = tensors[0]; + const size_t size0 = sizes[0]; + + if (size0 == 0 || offsets[1] < offsets[0] || data_offsets[1] < data_offsets[0]) { + return false; + } + + const size_t stride_tensor0 = offsets[1] - offsets[0]; + const size_t stride_data0 = data_offsets[1] - data_offsets[0]; + + for (size_t i = 1; i < n_tensors; i++) { + if (tensors[i] != tensor || sizes[i] != size0) { + return false; + } + if (offsets[i] != offsets[0] + i*stride_tensor0 || data_offsets[i] != data_offsets[0] + i*stride_data0) { + return false; + } + } + + *base_offset = offsets[0]; + *size = size0; + *stride_tensor = stride_tensor0; + *stride_data = stride_data0; + + return true; +} + void ggml_backend_tensor_set_async(ggml_backend_t backend, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { GGML_ASSERT(backend); GGML_ASSERT(tensor); @@ -546,6 +602,154 @@ void ggml_backend_tensor_get_2d(const struct ggml_tensor * tensor, void * data, buf->iface.get_tensor_2d(buf, tensor, data, offset, size, n_copies, stride_tensor, stride_data); } +void ggml_backend_tensor_set_n(struct ggml_tensor * const * tensors, const void * data, + const size_t * offsets, const size_t * sizes, const size_t * data_offsets, size_t n_tensors) { + if (n_tensors == 0) { + return; + } + + std::vector data_ptrs(n_tensors); + for (size_t i = 0; i < n_tensors; i++) { + data_ptrs[i] = (const char *) data + data_offsets[i]; + } + + ggml_backend_buffer_t buf = NULL; + bool same_buft = true; + + for (size_t i = 0; i < n_tensors; i++) { + GGML_ASSERT(tensors[i] != NULL); + ggml_backend_buffer_t tensor_buf = tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + GGML_ASSERT(tensor_buf != NULL && "tensor buffer not set"); + GGML_ASSERT(tensors[i]->data != NULL && "tensor not allocated"); + GGML_ASSERT(offsets[i] + sizes[i] <= ggml_nbytes(tensors[i]) && "tensor write out of bounds"); + + if (buf == NULL) { + buf = tensor_buf; + } else if (buf->buft != tensor_buf->buft) { + same_buft = false; + } + } + + if (same_buft && buf->iface.set_tensor_n != NULL) { + buf->iface.set_tensor_n(buf, tensors, data_ptrs.data(), offsets, sizes, n_tensors); + return; + } + + if (!same_buft) { + std::vector> groups; + ggml_backend_tensor_buft_groups(n_tensors, [&](size_t i) { + return tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + }, groups); + + for (size_t g = 0; g < groups.size(); g++) { + std::vector g_tensors; + std::vector g_offsets; + std::vector g_sizes; + std::vector g_data_offsets; + g_tensors.reserve(groups[g].size()); + g_offsets.reserve(groups[g].size()); + g_sizes.reserve(groups[g].size()); + g_data_offsets.reserve(groups[g].size()); + + for (size_t i : groups[g]) { + g_tensors.push_back(tensors[i]); + g_offsets.push_back(offsets[i]); + g_sizes.push_back(sizes[i]); + g_data_offsets.push_back(data_offsets[i]); + } + + ggml_backend_tensor_set_n(g_tensors.data(), data, g_offsets.data(), g_sizes.data(), g_data_offsets.data(), g_tensors.size()); + } + return; + } + + size_t base_offset = 0, size = 0, stride_tensor = 0, stride_data = 0; + if (ggml_backend_tensor_batch_is_2d(tensors, offsets, sizes, data_offsets, n_tensors, + &base_offset, &size, &stride_tensor, &stride_data)) { + ggml_backend_tensor_set_2d(tensors[0], data_ptrs[0], base_offset, size, + n_tensors, stride_tensor, stride_data); + return; + } + + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_tensor_set(tensors[i], data_ptrs[i], offsets[i], sizes[i]); + } +} + +void ggml_backend_tensor_get_n(const struct ggml_tensor * const * tensors, void * data, + const size_t * offsets, const size_t * sizes, const size_t * data_offsets, size_t n_tensors) { + if (n_tensors == 0) { + return; + } + + std::vector data_ptrs(n_tensors); + for (size_t i = 0; i < n_tensors; i++) { + data_ptrs[i] = (char *) data + data_offsets[i]; + } + + ggml_backend_buffer_t buf = NULL; + bool same_buft = true; + + for (size_t i = 0; i < n_tensors; i++) { + GGML_ASSERT(tensors[i] != NULL); + ggml_backend_buffer_t tensor_buf = tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + GGML_ASSERT(tensor_buf != NULL && "tensor buffer not set"); + GGML_ASSERT(tensors[i]->data != NULL && "tensor not allocated"); + GGML_ASSERT(offsets[i] + sizes[i] <= ggml_nbytes(tensors[i]) && "tensor read out of bounds"); + + if (buf == NULL) { + buf = tensor_buf; + } else if (buf->buft != tensor_buf->buft) { + same_buft = false; + } + } + + if (same_buft && buf->iface.get_tensor_n != NULL) { + buf->iface.get_tensor_n(buf, tensors, data_ptrs.data(), offsets, sizes, n_tensors); + return; + } + + if (!same_buft) { + std::vector> groups; + ggml_backend_tensor_buft_groups(n_tensors, [&](size_t i) { + return tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + }, groups); + + for (size_t g = 0; g < groups.size(); g++) { + std::vector g_tensors; + std::vector g_offsets; + std::vector g_sizes; + std::vector g_data_offsets; + g_tensors.reserve(groups[g].size()); + g_offsets.reserve(groups[g].size()); + g_sizes.reserve(groups[g].size()); + g_data_offsets.reserve(groups[g].size()); + + for (size_t i : groups[g]) { + g_tensors.push_back(tensors[i]); + g_offsets.push_back(offsets[i]); + g_sizes.push_back(sizes[i]); + g_data_offsets.push_back(data_offsets[i]); + } + + ggml_backend_tensor_get_n(g_tensors.data(), data, g_offsets.data(), g_sizes.data(), g_data_offsets.data(), g_tensors.size()); + } + return; + } + + size_t base_offset = 0, size = 0, stride_tensor = 0, stride_data = 0; + if (ggml_backend_tensor_batch_is_2d(tensors, offsets, sizes, data_offsets, n_tensors, + &base_offset, &size, &stride_tensor, &stride_data)) { + ggml_backend_tensor_get_2d(tensors[0], data_ptrs[0], base_offset, size, + n_tensors, stride_tensor, stride_data); + return; + } + + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_tensor_get(tensors[i], data_ptrs[i], offsets[i], sizes[i]); + } +} + void ggml_backend_tensor_memset(struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { GGML_ASSERT(tensor); ggml_backend_buffer_t buf = tensor->view_src ? tensor->view_src->buffer : tensor->buffer; @@ -648,6 +852,59 @@ void ggml_backend_tensor_copy(const struct ggml_tensor * src, struct ggml_tensor } } +void ggml_backend_tensor_copy_n(const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors) { + if (n_tensors == 0) { + return; + } + + for (size_t i = 0; i < n_tensors; ++i) { + GGML_ASSERT(ggml_are_same_layout(srcs[i], dsts[i]) && "cannot copy tensors with different layouts"); + } + + ggml_backend_buffer_t buf = dsts[0]->view_src ? dsts[0]->view_src->buffer : dsts[0]->buffer; + bool same_buft = true; + for (size_t i = 0; i < n_tensors; ++i) { + ggml_backend_buffer_t dst_buf = dsts[i]->view_src ? dsts[i]->view_src->buffer : dsts[i]->buffer; + if (dst_buf->buft != buf->buft) { + same_buft = false; + break; + } + } + + // if cpy_tensor_n returns false, it must not have performed any copies + if (same_buft && buf->iface.cpy_tensor_n != NULL) { + if (buf->iface.cpy_tensor_n(buf, srcs, dsts, n_tensors)) { + return; + } + } + + if (!same_buft) { + std::vector> groups; + ggml_backend_tensor_buft_groups(n_tensors, [&](size_t i) { + return dsts[i]->view_src ? dsts[i]->view_src->buffer : dsts[i]->buffer; + }, groups); + + for (size_t g = 0; g < groups.size(); g++) { + std::vector g_srcs; + std::vector g_dsts; + g_srcs.reserve(groups[g].size()); + g_dsts.reserve(groups[g].size()); + + for (size_t i : groups[g]) { + g_srcs.push_back(srcs[i]); + g_dsts.push_back(dsts[i]); + } + + ggml_backend_tensor_copy_n(g_srcs.data(), g_dsts.data(), g_srcs.size()); + } + return; + } + + for (size_t i = 0; i < n_tensors; ++i) { + ggml_backend_tensor_copy(srcs[i], dsts[i]); + } +} + void ggml_backend_tensor_copy_async(ggml_backend_t backend_src, ggml_backend_t backend_dst, const struct ggml_tensor * src, struct ggml_tensor * dst) { GGML_ASSERT(ggml_are_same_layout(src, dst) && "cannot copy tensors with different layouts"); @@ -853,6 +1110,9 @@ static const struct ggml_backend_buffer_i ggml_backend_multi_buffer_i = { /* .cpy_tensor = */ NULL, /* .clear = */ ggml_backend_multi_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; ggml_backend_buffer_t ggml_backend_multi_buffer_alloc_buffer(ggml_backend_buffer_t * buffers, size_t n_buffers) { @@ -2226,6 +2486,7 @@ bool ggml_op_alloc_size_may_expand(enum ggml_op op) { case GGML_OP_CUMSUM: case GGML_OP_ARGSORT: case GGML_OP_TOP_K: + case GGML_OP_ARGMAX: return true; default: return false; @@ -2531,6 +2792,9 @@ static const struct ggml_backend_buffer_i ggml_backend_cpu_buffer_i = { /* .cpy_tensor = */ ggml_backend_cpu_buffer_cpy_tensor, /* .clear = */ ggml_backend_cpu_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; static const struct ggml_backend_buffer_i ggml_backend_cpu_buffer_from_ptr_i = { @@ -2545,6 +2809,9 @@ static const struct ggml_backend_buffer_i ggml_backend_cpu_buffer_from_ptr_i = { /* .cpy_tensor = */ ggml_backend_cpu_buffer_cpy_tensor, /* .clear = */ ggml_backend_cpu_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; // CPU backend buffer type diff --git a/ggml/src/ggml-cann/ggml-cann.cpp b/ggml/src/ggml-cann/ggml-cann.cpp index 0bac41d033e7..3a78a1402758 100644 --- a/ggml/src/ggml-cann/ggml-cann.cpp +++ b/ggml/src/ggml-cann/ggml-cann.cpp @@ -920,7 +920,7 @@ static void * ggml_backend_cann_buffer_get_base(ggml_backend_buffer_t buffer) { * @param dst Pointer to the destination buffer where transformed data will be * stored. */ -static void ggml_backend_cann_transform_q4_0(ggml_tensor * tensor, const void * src, void * dst) { +static void ggml_backend_cann_transform_q4_0(const ggml_tensor * tensor, const void * src, void * dst) { int64_t n_elems = ggml_nelements(tensor); int64_t groups = n_elems / QK4_0; size_t quant_bytes = n_elems * sizeof(uint8_t) / 2; @@ -1014,7 +1014,7 @@ static void ggml_backend_cann_transform_back_q4_0(const ggml_tensor * tensor, vo * @param dst Pointer to the destination buffer where transformed data will be * stored. */ -static void ggml_backend_cann_transform_q8_0(ggml_tensor * tensor, const void * src, void * dst) { +static void ggml_backend_cann_transform_q8_0(const ggml_tensor * tensor, const void * src, void * dst) { int64_t n_elems = ggml_nelements(tensor); int64_t groups = n_elems / QK8_0; size_t quant_bytes = n_elems * sizeof(uint8_t); @@ -1075,7 +1075,7 @@ static void ggml_backend_cann_transform_back_q8_0(const ggml_tensor * tensor, co * @param dst Pointer to the destination buffer where transformed data will be * stored. */ -static void ggml_backend_cann_transform(ggml_tensor * tensor, const void * src, void * dst) { +static void ggml_backend_cann_transform(const ggml_tensor * tensor, const void * src, void * dst) { switch (tensor->type) { case GGML_TYPE_Q4_0: ggml_backend_cann_transform_q4_0(tensor, src, dst); @@ -1478,6 +1478,9 @@ static const ggml_backend_buffer_i ggml_backend_cann_buffer_interface = { /* .cpy_tensor = */ ggml_backend_cann_buffer_cpy_tensor, /* .clear = */ ggml_backend_cann_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; /** @@ -2455,9 +2458,10 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten #ifdef ASCEND_310P // Q4 && Q8 per group is not support on 310p device return false; -#endif +#else // only support contiguous for quantized types. return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); +#endif default: return false; } @@ -2472,9 +2476,10 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten #ifdef ASCEND_310P // Q4 && Q8 per group is not support on 310p device return false; -#endif +#else // only support contiguous for quantized types. return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); +#endif default: return false; } @@ -2641,7 +2646,7 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten #ifdef ASCEND_310P // Ger is not supported on 310p device return false; -#endif +#else switch (op->src[0]->type) { case GGML_TYPE_F16: case GGML_TYPE_F32: @@ -2649,6 +2654,7 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten default: return false; } +#endif } case GGML_OP_CONV_TRANSPOSE_1D: return true; @@ -2664,10 +2670,14 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten return true; case GGML_OP_FLASH_ATTN_EXT: { + // K/V row lists (ggml_flash_attn_ext_rows) are not supported + if (op->src[5] != nullptr) { + return false; + } #ifdef ASCEND_310P // FA not support on 310p device return false; -#endif +#else // derived from [ggml-cuda.cu] if (op->src[1]->type != GGML_TYPE_F16 || op->src[2]->type != GGML_TYPE_F16) { return false; @@ -2693,6 +2703,7 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, const ggml_ten return false; } return true; +#endif } case GGML_OP_SSM_CONV: // ggml_cann_ssm_conv() requires F32 src/dst and the time-major layout diff --git a/ggml/src/ggml-cpu/CMakeLists.txt b/ggml/src/ggml-cpu/CMakeLists.txt index d347757e1854..8327c52e6dae 100644 --- a/ggml/src/ggml-cpu/CMakeLists.txt +++ b/ggml/src/ggml-cpu/CMakeLists.txt @@ -650,9 +650,9 @@ function(ggml_add_cpu_backend_variant_impl tag_name) # Fetch KleidiAI sources: include(FetchContent) - set(KLEIDIAI_COMMIT_TAG "v1.31.0") + set(KLEIDIAI_COMMIT_TAG "v1.32.0") set(KLEIDIAI_DOWNLOAD_URL "https://github.com/ARM-software/kleidiai/releases/download/${KLEIDIAI_COMMIT_TAG}/kleidiai-${KLEIDIAI_COMMIT_TAG}-src.tar.gz") - set(KLEIDIAI_RELEASE_ARCHIVE_MD5 "930495f3aeb16b25dc18a2bde45924f4") + set(KLEIDIAI_RELEASE_ARCHIVE_MD5 "05f1953428ffe8e8c7f585dc6d508887") set(KLEIDIAI_FETCH_ARGS URL ${KLEIDIAI_DOWNLOAD_URL} diff --git a/ggml/src/ggml-cpu/amx/amx.cpp b/ggml/src/ggml-cpu/amx/amx.cpp index e90c2797ffdd..554a2066a75c 100644 --- a/ggml/src/ggml-cpu/amx/amx.cpp +++ b/ggml/src/ggml-cpu/amx/amx.cpp @@ -116,6 +116,9 @@ static ggml_backend_buffer_i ggml_backend_amx_buffer_interface = { /* .cpy_tensor = */ nullptr, /* .clear = */ ggml_backend_amx_buffer_clear, /* .reset = */ nullptr, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; static const char * ggml_backend_amx_buffer_type_get_name(ggml_backend_buffer_type_t buft) { diff --git a/ggml/src/ggml-cpu/arch/arm/quants.c b/ggml/src/ggml-cpu/arch/arm/quants.c index cfbbf66178cf..f16505b2c986 100644 --- a/ggml/src/ggml-cpu/arch/arm/quants.c +++ b/ggml/src/ggml-cpu/arch/arm/quants.c @@ -287,6 +287,9 @@ void ggml_vec_dot_q2_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vaddvq_f32(sumv); #else + UNUSED(nb); + UNUSED(x); + UNUSED(y); ggml_vec_dot_q2_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); return; #endif diff --git a/ggml/src/ggml-cpu/arch/arm/repack.cpp b/ggml/src/ggml-cpu/arch/arm/repack.cpp index ad0e5ccaf7b7..b60eff9d5307 100644 --- a/ggml/src/ggml-cpu/arch/arm/repack.cpp +++ b/ggml/src/ggml-cpu/arch/arm/repack.cpp @@ -535,6 +535,60 @@ void ggml_gemv_mxfp4_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const v UNUSED(ncols_interleaved); UNUSED(blocklen); +#if defined(__aarch64__) && defined(__ARM_FEATURE_SVE) + if (svcntb() * 8 == 256) { + const svbool_t pg16 = svptrue_pat_b8(SV_VL16); + const svbool_t pg4 = svptrue_pat_b32(SV_VL4); + const svbool_t pgb = svptrue_b8(); + const svbool_t pgw = svptrue_b32(); + const svbool_t pg_hi4 = svnot_b_z(pgw, pg4); + const svuint8_t m4b = svdup_n_u8(0x0f); + const svuint8_t values = svld1_u8(pg16, (const uint8_t *) kvalues_mxfp4); + + // Reorder Q8 four-byte groups as [0,2,4,6,1,3,5,7] + const svuint32_t q8_group_index = svsub_n_u32_m(pg_hi4, svindex_u32(0, 2), 7); + + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + float * res_ptr = s; + + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_mxfp4x4 * b_ptr = (const block_mxfp4x4 *) vx + (x * nb); + svfloat32_t sumf = svdup_n_f32(0.0f); + + for (int l = 0; l < nb; l++) { + const svint8_t q8 = svld1_s8(pgb, a_ptr[l].qs); + const svint8_t q8_even_odd = svreinterpret_s8_u32(svtbl_u32(svreinterpret_u32_s8(q8), q8_group_index)); + const svuint8_t qmx01 = svld1_u8(pgb, b_ptr[l].qs + 0); + const svuint8_t qmx_lo01 = svtbl_u8(values, svand_u8_x(pgb, qmx01, m4b)); + const svuint8_t qmx_hi01 = svtbl_u8(values, svlsr_n_u8_x(pgb, qmx01, 4)); + const svuint8_t qmx23 = svld1_u8(pgb, b_ptr[l].qs + 32); + const svuint8_t qmx_lo23 = svtbl_u8(values, svand_u8_x(pgb, qmx23, m4b)); + const svuint8_t qmx_hi23 = svtbl_u8(values, svlsr_n_u8_x(pgb, qmx23, 4)); + + svint32_t sumi = svdup_n_s32(0); + sumi = svdot_lane_s32(sumi, svreinterpret_s8_u8(qmx_lo01), q8_even_odd, 0); + sumi = svdot_lane_s32(sumi, svreinterpret_s8_u8(qmx_lo23), q8_even_odd, 1); + sumi = svdot_lane_s32(sumi, svreinterpret_s8_u8(qmx_hi01), q8_even_odd, 2); + sumi = svdot_lane_s32(sumi, svreinterpret_s8_u8(qmx_hi23), q8_even_odd, 3); + const svint32_t sumi_cols = svadd_s32_z(pg4, sumi, svext_s32(sumi, sumi, 4)); + + // Vector form of GGML_CPU_E8M0_TO_FP32_HALF + const svuint32_t e_u32 = svld1ub_u32(pg4, b_ptr[l].e); + const svbool_t e_is_denormal = svcmplt_n_u32(pg4, e_u32, 2); + const svuint32_t e_denormal_bits = svlsl_u32_x(pg4, svdup_n_u32(0x00200000), e_u32); + const svuint32_t e_normal_bits = svlsl_n_u32_x(pg4, svsub_n_u32_x(pg4, e_u32, 1), 23); + const svuint32_t e_bits = svsel_u32(e_is_denormal, e_denormal_bits, e_normal_bits); + const svfloat16_t d_f16 = svreinterpret_f16_u16(svdup_n_u16(a_ptr[l].d)); + const svfloat32_t d_f32 = svcvt_f32_f16_x(pg4, d_f16); + const svfloat32_t scale = svmul_f32_x(pg4, svreinterpret_f32_u32(e_bits), d_f32); + sumf = svmla_f32_m(pg4, sumf,svcvt_f32_s32_m(svdup_n_f32(0.0f), pg4, sumi_cols), scale); + } + svst1_f32(pg4, res_ptr + x * 4, sumf); + } + return; + } +#endif // defined(__aarch64__) && defined(__ARM_FEATURE_SVE) + #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) const int8x16_t kvalues = vld1q_s8(kvalues_mxfp4); const block_q8_0 * a_ptr = (const block_q8_0 *) vy; @@ -1791,6 +1845,71 @@ void ggml_gemv_q8_0_4x8_q8_0(int n, UNUSED(ncols_interleaved); UNUSED(blocklen); +#if defined(__aarch64__) && defined(__ARM_FEATURE_SVE) + // 256-bit SVE: 32 x int8 -> 8 x int32 + if (ggml_cpu_get_sve_cnt() == QK8_0) { + const block_q8_0x4 * GGML_RESTRICT b_ptr = (const block_q8_0x4 *) vx; + + const svbool_t pg = svptrue_b8(); + const svbool_t pg4w = svptrue_pat_b32(SV_VL4); + + // after svtbl + svcvt the scale lanes are [d0,d0,d1,d1,d2,d2,d3,d3]: lane pair j = row j + const svuint16_t d_idx = svreinterpret_u16_u32(svlsr_n_u32_x(pg, svindex_u32(0, 1), 1)); + + for (int c = 0; c < nc; c += ncols_interleaved) { + const block_q8_0 * GGML_RESTRICT a_ptr = (const block_q8_0 *) vy; + + svfloat32_t acc = svdup_n_f32(0.0f); + + for (int b = 0; b < nb; ++b) { + const int8_t * GGML_RESTRICT bq = (const int8_t *) b_ptr->qs; + + uint64_t a_chunk0; + uint64_t a_chunk1; + uint64_t a_chunk2; + uint64_t a_chunk3; + uint64_t b_d; + + memcpy(&a_chunk0, a_ptr->qs + 0, sizeof(a_chunk0)); + memcpy(&a_chunk1, a_ptr->qs + 8, sizeof(a_chunk1)); + memcpy(&a_chunk2, a_ptr->qs + 16, sizeof(a_chunk2)); + memcpy(&a_chunk3, a_ptr->qs + 24, sizeof(a_chunk3)); + memcpy(&b_d, b_ptr->d, sizeof(b_d)); + + const svint8_t aq0 = svreinterpret_s8_u64(svdup_n_u64(a_chunk0)); + const svint8_t aq1 = svreinterpret_s8_u64(svdup_n_u64(a_chunk1)); + const svint8_t aq2 = svreinterpret_s8_u64(svdup_n_u64(a_chunk2)); + const svint8_t aq3 = svreinterpret_s8_u64(svdup_n_u64(a_chunk3)); + + const svint8_t bq0 = svld1_s8(pg, bq + 0); + const svint8_t bq1 = svld1_s8(pg, bq + 32); + const svint8_t bq2 = svld1_s8(pg, bq + 64); + const svint8_t bq3 = svld1_s8(pg, bq + 96); + + const svint32_t iacc0 = svdot_s32(svdup_n_s32(0), bq0, aq0); + const svint32_t iacc1 = svdot_s32(svdup_n_s32(0), bq1, aq1); + const svint32_t iacc2 = svdot_s32(svdup_n_s32(0), bq2, aq2); + const svint32_t iacc3 = svdot_s32(svdup_n_s32(0), bq3, aq3); + + const svint32_t isum = svadd_s32_x(pg, svadd_s32_x(pg, iacc0, iacc1), svadd_s32_x(pg, iacc2, iacc3)); + + const svfloat16_t bd_h = svtbl_f16(svreinterpret_f16_u64(svdup_n_u64(b_d)), d_idx); + const svfloat32_t scale = svmul_n_f32_x(pg, svcvt_f32_f16_x(pg, bd_h), GGML_CPU_FP16_TO_FP32(a_ptr->d)); + + acc = svmla_f32_x(pg, acc, svcvt_f32_s32_x(pg, isum), scale); + + ++a_ptr; + ++b_ptr; + } + + svst1_f32(pg4w, s, svadd_f32_x(pg, svuzp1_f32(acc, acc), svuzp2_f32(acc, acc))); + s += ncols_interleaved; + } + + return; + } +#endif // defined(__aarch64__) && defined(__ARM_FEATURE_SVE) + #if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) const block_q8_0x4 * b_ptr = (const block_q8_0x4 *) vx; @@ -4874,6 +4993,7 @@ void ggml_gemm_q6_K_8x8_q8_K(int n, constexpr int ncols_interleaved = 8; constexpr int blocklen = 8; + constexpr int q8_k_blocklen = 4; assert(n % qk == 0); assert(nr % 4 == 0); @@ -4882,9 +5002,195 @@ void ggml_gemm_q6_K_8x8_q8_K(int n, UNUSED(nb); UNUSED(ncols_interleaved); UNUSED(blocklen); + UNUSED(q8_k_blocklen); + +#if defined(__aarch64__) && defined(__ARM_FEATURE_SVE) && defined(__ARM_FEATURE_MATMUL_INT8) + if (svcntb() * 8 == 256) { + const svbool_t pg8 = svptrue_b8(); + const svbool_t pg32 = svptrue_b32(); + + const svuint8_t low_nibble = svdup_n_u8(0x0f); + const svuint8_t high_lo2 = svdup_n_u8(0x03); + const svuint8_t high_hi2 = svdup_n_u8(0x30); + const svint8_t q6_bias = svdup_n_s8(32); + const svint32_t zero_s32 = svdup_n_s32(0); + + for (int y = 0; y < nr / q8_k_blocklen; ++y) { + const block_q8_Kx4 * GGML_RESTRICT q8_ptr = (const block_q8_Kx4 *) vy + y * nb; + + for (int x = 0; x < nc / ncols_interleaved; ++x) { + const block_q6_Kx8 * GGML_RESTRICT q6_ptr = (const block_q6_Kx8 *) vx + x * nb; + + // one accumlator per output row + svfloat32_t acc_f32_r0 = svdup_n_f32(0); + svfloat32_t acc_f32_r1 = svdup_n_f32(0); + svfloat32_t acc_f32_r2 = svdup_n_f32(0); + svfloat32_t acc_f32_r3 = svdup_n_f32(0); + + for (int b = 0; b < nb; ++b) { + svint32_t acc_c03_r01 = zero_s32; + svint32_t acc_c03_r23 = zero_s32; + svint32_t acc_c47_r01 = zero_s32; + svint32_t acc_c47_r23 = zero_s32; + + for (int half = 0; half < 2; ++half) { + const uint8_t * ql_base = q6_ptr[b].ql + half * 512; + const uint8_t * qh_base = q6_ptr[b].qh + half * 256; + + for (int sb = 0; sb < QK_K / 64; ++sb) { + const int8_t * q8_base_l = q8_ptr[b].qs + half * 512 + sb * 64; + const int8_t * q8_base_h = q8_ptr[b].qs + half * 512 + 256 + sb * 64; + + // load 16 bytes (8B of R0, 8B of R1) and repeat in upper half + // low lanes will multiply with 16 bytes of C0 and high lanes will multiply with 16 bytes of C1 + const svint8_t q8_l_r01_k0 = svld1rq_s8(pg8, q8_base_l + 0); + const svint8_t q8_l_r01_k1 = svld1rq_s8(pg8, q8_base_l + 32); + const svint8_t q8_l_r23_k0 = svld1rq_s8(pg8, q8_base_l + 16); + const svint8_t q8_l_r23_k1 = svld1rq_s8(pg8, q8_base_l + 48); + + const svint8_t q8_h_r01_k0 = svld1rq_s8(pg8, q8_base_h + 0); + const svint8_t q8_h_r01_k1 = svld1rq_s8(pg8, q8_base_h + 32); + const svint8_t q8_h_r23_k0 = svld1rq_s8(pg8, q8_base_h + 16); + const svint8_t q8_h_r23_k1 = svld1rq_s8(pg8, q8_base_h + 48); + + const int ql_off = sb * QK_K / 2; + const int qh_off = ql_off & 255; + + const int scale_idx_l = half * 8 + sb; + const int scale_idx_h = scale_idx_l + 4; + + const svint32_t scales_l_all = svld1sb_s32(pg32, q6_ptr[b].scales + scale_idx_l * 8); + const svint32_t scales_h_all = svld1sb_s32(pg32, q6_ptr[b].scales + scale_idx_h * 8); + + const svint32_t scales_l_c03 = svzip1_s32(scales_l_all, scales_l_all); + const svint32_t scales_h_c03 = svzip1_s32(scales_h_all, scales_h_all); + + { + svuint8_t q6_ql0_01 = svld1_u8(pg8, ql_base + ql_off); + svuint8_t q6_ql1_01 = svld1_u8(pg8, ql_base + ql_off + 64); + svuint8_t q6_qh0_01 = svld1_u8(pg8, qh_base + qh_off); + svuint8_t q6_qh1_01 = svld1_u8(pg8, qh_base + qh_off + 64); + + if (sb > 1) { + q6_qh0_01 = svlsr_n_u8_x(pg8, q6_qh0_01, 2); + q6_qh1_01 = svlsr_n_u8_x(pg8, q6_qh1_01, 2); + } + + const svuint8_t q6_qh0_01_hi = svand_u8_x(pg8, q6_qh0_01, high_hi2); + const svuint8_t q6_qh1_01_hi = svand_u8_x(pg8, q6_qh1_01, high_hi2); + + const svuint8_t q6_l0_01_bits = svorr_u8_x(pg8, svand_u8_x(pg8, q6_ql0_01, low_nibble), svlsl_n_u8_x(pg8, svand_u8_x(pg8, q6_qh0_01, high_lo2), 4)); + const svuint8_t q6_l1_01_bits = svorr_u8_x(pg8, svand_u8_x(pg8, q6_ql1_01, low_nibble), svlsl_n_u8_x(pg8, svand_u8_x(pg8, q6_qh1_01, high_lo2), 4)); + const svuint8_t q6_h0_01_bits = svorr_u8_x(pg8, svlsr_n_u8_x(pg8, q6_ql0_01, 4), q6_qh0_01_hi); + const svuint8_t q6_h1_01_bits = svorr_u8_x(pg8, svlsr_n_u8_x(pg8, q6_ql1_01, 4), q6_qh1_01_hi); + + const svint8_t q6_l0_01 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_l0_01_bits), q6_bias); + const svint8_t q6_l1_01 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_l1_01_bits), q6_bias); + const svint8_t q6_h0_01 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_h0_01_bits), q6_bias); + const svint8_t q6_h1_01 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_h1_01_bits), q6_bias); + + svint32_t dot_l_r01 = svmmla_s32(zero_s32, q6_l0_01, q8_l_r01_k0); + dot_l_r01 = svmmla_s32(dot_l_r01, q6_l1_01, q8_l_r01_k1); + + svint32_t dot_h_r01 = svmmla_s32(zero_s32, q6_h0_01, q8_h_r01_k0); + dot_h_r01 = svmmla_s32(dot_h_r01, q6_h1_01, q8_h_r01_k1); + + svint32_t dot_l_r23 = svmmla_s32(zero_s32, q6_l0_01, q8_l_r23_k0); + dot_l_r23 = svmmla_s32(dot_l_r23, q6_l1_01, q8_l_r23_k1); + + svint32_t dot_h_r23 = svmmla_s32(zero_s32, q6_h0_01, q8_h_r23_k0); + dot_h_r23 = svmmla_s32(dot_h_r23, q6_h1_01, q8_h_r23_k1); + + acc_c03_r01 = svmla_s32_x(pg32, acc_c03_r01, dot_l_r01, scales_l_c03); + acc_c03_r01 = svmla_s32_x(pg32, acc_c03_r01, dot_h_r01, scales_h_c03); + acc_c03_r23 = svmla_s32_x(pg32, acc_c03_r23, dot_l_r23, scales_l_c03); + acc_c03_r23 = svmla_s32_x(pg32, acc_c03_r23, dot_h_r23, scales_h_c03); + } + + const svint32_t scales_l_c47 = svzip2_s32(scales_l_all, scales_l_all); + const svint32_t scales_h_c47 = svzip2_s32(scales_h_all, scales_h_all); + + { + svuint8_t q6_ql0_23 = svld1_u8(pg8, ql_base + ql_off + 32); + svuint8_t q6_ql1_23 = svld1_u8(pg8, ql_base + ql_off + 96); + svuint8_t q6_qh0_23 = svld1_u8(pg8, qh_base + qh_off + 32); + svuint8_t q6_qh1_23 = svld1_u8(pg8, qh_base + qh_off + 96); + + if (sb > 1) { + q6_qh0_23 = svlsr_n_u8_x(pg8, q6_qh0_23, 2); + q6_qh1_23 = svlsr_n_u8_x(pg8, q6_qh1_23, 2); + } + + const svuint8_t q6_qh0_23_hi = svand_u8_x(pg8, q6_qh0_23, high_hi2); + const svuint8_t q6_qh1_23_hi = svand_u8_x(pg8, q6_qh1_23, high_hi2); + + const svuint8_t q6_l0_23_bits = svorr_u8_x(pg8, svand_u8_x(pg8, q6_ql0_23, low_nibble), svlsl_n_u8_x(pg8, svand_u8_x(pg8, q6_qh0_23, high_lo2), 4)); + const svuint8_t q6_l1_23_bits = svorr_u8_x(pg8, svand_u8_x(pg8, q6_ql1_23, low_nibble), svlsl_n_u8_x(pg8, svand_u8_x(pg8, q6_qh1_23, high_lo2), 4)); + const svuint8_t q6_h0_23_bits = svorr_u8_x(pg8, svlsr_n_u8_x(pg8, q6_ql0_23, 4), q6_qh0_23_hi); + const svuint8_t q6_h1_23_bits = svorr_u8_x(pg8, svlsr_n_u8_x(pg8, q6_ql1_23, 4), q6_qh1_23_hi); + + const svint8_t q6_l0_23 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_l0_23_bits), q6_bias); + const svint8_t q6_l1_23 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_l1_23_bits), q6_bias); + const svint8_t q6_h0_23 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_h0_23_bits), q6_bias); + const svint8_t q6_h1_23 = svsub_s8_x(pg8, svreinterpret_s8_u8(q6_h1_23_bits), q6_bias); + + svint32_t dot_l_r01 = svmmla_s32(zero_s32, q6_l0_23, q8_l_r01_k0); + dot_l_r01 = svmmla_s32(dot_l_r01, q6_l1_23, q8_l_r01_k1); + + svint32_t dot_h_r01 = svmmla_s32(zero_s32, q6_h0_23, q8_h_r01_k0); + dot_h_r01 = svmmla_s32(dot_h_r01, q6_h1_23, q8_h_r01_k1); + + svint32_t dot_l_r23 = svmmla_s32(zero_s32, q6_l0_23, q8_l_r23_k0); + dot_l_r23 = svmmla_s32(dot_l_r23, q6_l1_23, q8_l_r23_k1); + + svint32_t dot_h_r23 = svmmla_s32(zero_s32, q6_h0_23, q8_h_r23_k0); + dot_h_r23 = svmmla_s32(dot_h_r23, q6_h1_23, q8_h_r23_k1); + + acc_c47_r01 = svmla_s32_x(pg32, acc_c47_r01, dot_l_r01, scales_l_c47); + acc_c47_r01 = svmla_s32_x(pg32, acc_c47_r01, dot_h_r01, scales_h_c47); + acc_c47_r23 = svmla_s32_x(pg32, acc_c47_r23, dot_l_r23, scales_l_c47); + acc_c47_r23 = svmla_s32_x(pg32, acc_c47_r23, dot_h_r23, scales_h_c47); + } + } + } + + // acc_c03_r01 -> c0-r0,c0-r1,c1-r0,c1-r1,c2-r0,c2-r1,c3-r0,c3-r1 + // acc_c47_r01 -> c4-r0,c4-r1,c5-r0,c5-r1,c6-r0,c6-r1,c7-r0,c7-r1 + // svuzp1_s32 picks even lanes -> c0-r0,c1-r0,c2-r0,c3-r0,c4-r0,c5-r0,c6-r0,c7-r0 + // similarly svuzp2_s32 picks remaining values from odd lanes + const svint32_t dot_r0 = svuzp1_s32(acc_c03_r01, acc_c47_r01); + const svint32_t dot_r1 = svuzp2_s32(acc_c03_r01, acc_c47_r01); + const svint32_t dot_r2 = svuzp1_s32(acc_c03_r23, acc_c47_r23); + const svint32_t dot_r3 = svuzp2_s32(acc_c03_r23, acc_c47_r23); + + const svuint32_t q6_d_bits = svld1uh_u32(pg32, (const uint16_t *) q6_ptr[b].d); + const svfloat32_t q6_d_f32 = svcvt_f32_f16_x(pg32, svreinterpret_f16_u32(q6_d_bits)); + + const svfloat32_t scale_r0 = svmul_n_f32_x(pg32, q6_d_f32, q8_ptr[b].d[0]); + const svfloat32_t scale_r1 = svmul_n_f32_x(pg32, q6_d_f32, q8_ptr[b].d[1]); + const svfloat32_t scale_r2 = svmul_n_f32_x(pg32, q6_d_f32, q8_ptr[b].d[2]); + const svfloat32_t scale_r3 = svmul_n_f32_x(pg32, q6_d_f32, q8_ptr[b].d[3]); + + acc_f32_r0 = svmla_f32_x(pg32, acc_f32_r0, svcvt_f32_s32_x(pg32, dot_r0), scale_r0); + acc_f32_r1 = svmla_f32_x(pg32, acc_f32_r1, svcvt_f32_s32_x(pg32, dot_r1), scale_r1); + acc_f32_r2 = svmla_f32_x(pg32, acc_f32_r2, svcvt_f32_s32_x(pg32, dot_r2), scale_r2); + acc_f32_r3 = svmla_f32_x(pg32, acc_f32_r3, svcvt_f32_s32_x(pg32, dot_r3), scale_r3); + } + + const int row = y * q8_k_blocklen; + const int col = x * ncols_interleaved; + + svst1_f32(pg32, s + (row + 0) * bs + col, acc_f32_r0); + svst1_f32(pg32, s + (row + 1) * bs + col, acc_f32_r1); + svst1_f32(pg32, s + (row + 2) * bs + col, acc_f32_r2); + svst1_f32(pg32, s + (row + 3) * bs + col, acc_f32_r3); + } + } + return; + } +#endif // SVE compile-time end #if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8) - constexpr int q8_k_blocklen = 4; const uint8x16_t m4b = vdupq_n_u8(0x0f); const uint8x16_t mask_lo = vdupq_n_u8(0x03); const uint8x16_t mask_hi = vdupq_n_u8(0x30); diff --git a/ggml/src/ggml-cpu/arch/s390/quants.c b/ggml/src/ggml-cpu/arch/s390/quants.c index 52344828e39d..22b8b83109c9 100644 --- a/ggml/src/ggml-cpu/arch/s390/quants.c +++ b/ggml/src/ggml-cpu/arch/s390/quants.c @@ -310,7 +310,7 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_yl = vec_xl(0 , y[ib].qs); const int8x16_t v_yh = vec_xl(QK8_1/2, y[ib].qs); - const int32x4_t v_xy_ = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); + const int32x4_t v_xy_ = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xl, v_yl), v_xh, v_yh); const float32x4_t v_xy = vec_float(v_xy_); const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)); @@ -379,8 +379,8 @@ void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo const int8x16_t v_y1l = vec_xl(0, y1->qs); const int8x16_t v_y1h = vec_xl(QK8_0/2, y1->qs); - const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0l, v_y0l), v_x0h, v_y0h); - const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1l, v_y1l), v_x1h, v_y1h); + const int32x4_t v_xy0 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x0l, v_y0l), v_x0h, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x1l, v_y1l), v_x1h, v_y1h); const float32x4_t v_xy0f = vec_float(v_xy0); const float32x4_t v_xy1f = vec_float(v_xy1); @@ -407,7 +407,7 @@ void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo const int8x16_t v_yl = vec_xl(0, y0->qs); const int8x16_t v_yh = vec_xl(QK8_0/2, y0->qs); - const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); + const int32x4_t v_xy = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xl, v_yl), v_xh, v_yh); const float32x4_t v_xyf = vec_float(v_xy); const float32x4_t v_d = vec_splats(GGML_E8M0_TO_FP32_HALF(x0->e) * GGML_CPU_FP16_TO_FP32(y0->d)); @@ -502,8 +502,8 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_y1l = vec_xl(0, (const int8_t *)y1->qs); const int8x16_t v_y1h = vec_xl(QK8_0/2, (const int8_t *)y1->qs); - const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); - const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); + const int32x4_t v_xy0 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); const float32x4_t v_xy0f = vec_float(v_xy0); const float32x4_t v_xy1f = vec_float(v_xy1); @@ -548,7 +548,7 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_yl = vec_xl(0, (const int8_t *)y0->qs); const int8x16_t v_yh = vec_xl(QK8_0/2, (const int8_t *)y0->qs); - const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); + const int32x4_t v_xy = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); const float32x4_t v_xyf = vec_float(v_xy); const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); @@ -653,8 +653,8 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_y1l = vec_xl(0 , y1->qs); const int8x16_t v_y1h = vec_xl(QK8_1/2, y1->qs); - const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); - const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); + const int32x4_t v_xy0 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); const float32x4_t v_xy0f = vec_float(v_xy0); const float32x4_t v_xy1f = vec_float(v_xy1); @@ -701,7 +701,7 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_yl = vec_xl(0 , y0->qs); const int8x16_t v_yh = vec_xl(QK8_1/2, y0->qs); - const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); + const int32x4_t v_xy = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); const float32x4_t v_xyf = vec_float(v_xy); const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); @@ -751,7 +751,7 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi const int8x16_t v_yl = vec_xl(0 , y[ib].qs); const int8x16_t v_yh = vec_xl(QK8_0/2, y[ib].qs); - const int32x4_t v_xy_ = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); + const int32x4_t v_xy_ = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xl, v_yl), v_xh, v_yh); const float32x4_t v_xy = vec_float(v_xy_); const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)); @@ -855,10 +855,10 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi q3bytes[2] = vec_sub((int8x16_t)vec_and(vec_sr(q3b[0], 2), v_3m), (int8x16_t)q3h[2]); q3bytes[3] = vec_sub((int8x16_t)vec_and(vec_sr(q3b[1], 2), v_3m), (int8x16_t)q3h[3]); - isum0 = ggml_vec_dot(v_z, q3bytes[0], q8bytes[0]); - isum1 = ggml_vec_dot(v_z, q3bytes[1], q8bytes[1]); - isum2 = ggml_vec_dot(v_z, q3bytes[2], q8bytes[2]); - isum3 = ggml_vec_dot(v_z, q3bytes[3], q8bytes[3]); + isum0 = ggml_vec_dot_s32(v_z, q3bytes[0], q8bytes[0]); + isum1 = ggml_vec_dot_s32(v_z, q3bytes[1], q8bytes[1]); + isum2 = ggml_vec_dot_s32(v_z, q3bytes[2], q8bytes[2]); + isum3 = ggml_vec_dot_s32(v_z, q3bytes[3], q8bytes[3]); isum += (isum0[0] + isum0[1] + isum0[2] + isum0[3]) * scale[0]; isum += (isum1[0] + isum1[1] + isum1[2] + isum1[3]) * scale[1]; @@ -877,10 +877,10 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi q3bytes[2] = vec_sub((int8x16_t)vec_and(vec_sr(q3b[0], 6), v_3m), (int8x16_t)q3h[2]); q3bytes[3] = vec_sub((int8x16_t)vec_and(vec_sr(q3b[1], 6), v_3m), (int8x16_t)q3h[3]); - isum0 = ggml_vec_dot(v_z, q3bytes[0], q8bytes[4]); - isum1 = ggml_vec_dot(v_z, q3bytes[1], q8bytes[5]); - isum2 = ggml_vec_dot(v_z, q3bytes[2], q8bytes[6]); - isum3 = ggml_vec_dot(v_z, q3bytes[3], q8bytes[7]); + isum0 = ggml_vec_dot_s32(v_z, q3bytes[0], q8bytes[4]); + isum1 = ggml_vec_dot_s32(v_z, q3bytes[1], q8bytes[5]); + isum2 = ggml_vec_dot_s32(v_z, q3bytes[2], q8bytes[6]); + isum3 = ggml_vec_dot_s32(v_z, q3bytes[3], q8bytes[7]); isum += vec_hsum_i32x4(isum0) * scale[0]; isum += vec_hsum_i32x4(isum1) * scale[1]; @@ -981,7 +981,7 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi v_xl[0] = (int8x16_t)vec_and(v_x[0], v_lm); v_xl[1] = (int8x16_t)vec_and(v_x[1], v_lm); - const int32x4_t p1 = ggml_vec_dot(ggml_vec_dot(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); + const int32x4_t p1 = ggml_vec_dot_s32(ggml_vec_dot_s32(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); sumi1 += vec_hsum_i32x4(p1) * scales[2*j+0]; v_y[0] = vec_xl(0 , y0); @@ -991,7 +991,7 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi v_xl[0] = (int8x16_t)vec_sr(v_x[0], 4); v_xl[1] = (int8x16_t)vec_sr(v_x[1], 4); - const int32x4_t p2 = ggml_vec_dot(ggml_vec_dot(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); + const int32x4_t p2 = ggml_vec_dot_s32(ggml_vec_dot_s32(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); sumi2 += vec_hsum_i32x4(p2) * scales[2*j+1]; } @@ -1107,8 +1107,8 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi q5b[2] = (int8x16_t)vec_or(vec_sr(v_xl[0], 4), q5h[2]); q5b[3] = (int8x16_t)vec_or(vec_sr(v_xl[1], 4), q5h[3]); - int32x4_t sumi0 = ggml_vec_dot(ggml_vec_dot(v_z, q5b[0], v_y[0]), q5b[1], v_y[1]); - int32x4_t sumi1 = ggml_vec_dot(ggml_vec_dot(v_z, q5b[2], v_y[2]), q5b[3], v_y[3]); + int32x4_t sumi0 = ggml_vec_dot_s32(ggml_vec_dot_s32(v_z, q5b[0], v_y[0]), q5b[1], v_y[1]); + int32x4_t sumi1 = ggml_vec_dot_s32(ggml_vec_dot_s32(v_z, q5b[2], v_y[2]), q5b[3], v_y[3]); sumi += vec_hsum_i32x4(sumi0) * *scales++; sumi += vec_hsum_i32x4(sumi1) * *scales++; @@ -1217,10 +1217,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi q6b[2] = (int8x16_t)(vec_or(vec_and(v_xl[2], v_lm), q6h[2])); q6b[3] = (int8x16_t)(vec_or(vec_and(v_xl[3], v_lm), q6h[3])); - int32x4_t summs0 = ggml_vec_dot(v_z, q6b[0], v_y[0]); - int32x4_t summs1 = ggml_vec_dot(v_z, q6b[1], v_y[1]); - int32x4_t summs2 = ggml_vec_dot(v_z, q6b[2], v_y[2]); - int32x4_t summs3 = ggml_vec_dot(v_z, q6b[3], v_y[3]); + int32x4_t summs0 = ggml_vec_dot_s32(v_z, q6b[0], v_y[0]); + int32x4_t summs1 = ggml_vec_dot_s32(v_z, q6b[1], v_y[1]); + int32x4_t summs2 = ggml_vec_dot_s32(v_z, q6b[2], v_y[2]); + int32x4_t summs3 = ggml_vec_dot_s32(v_z, q6b[3], v_y[3]); isum += vec_hsum_i32x4(summs0) * scale[0] + vec_hsum_i32x4(summs1) * scale[1] + @@ -1251,10 +1251,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi q6b[2] = (int8x16_t)(vec_or(vec_sr(v_xl[2], 4), q6h[2])); q6b[3] = (int8x16_t)(vec_or(vec_sr(v_xl[3], 4), q6h[3])); - summs0 = ggml_vec_dot(v_z, q6b[0], v_y[0]); - summs1 = ggml_vec_dot(v_z, q6b[1], v_y[1]); - summs2 = ggml_vec_dot(v_z, q6b[2], v_y[2]); - summs3 = ggml_vec_dot(v_z, q6b[3], v_y[3]); + summs0 = ggml_vec_dot_s32(v_z, q6b[0], v_y[0]); + summs1 = ggml_vec_dot_s32(v_z, q6b[1], v_y[1]); + summs2 = ggml_vec_dot_s32(v_z, q6b[2], v_y[2]); + summs3 = ggml_vec_dot_s32(v_z, q6b[3], v_y[3]); isum += vec_hsum_i32x4(summs0) * scale[0] + vec_hsum_i32x4(summs1) * scale[1] + @@ -1367,8 +1367,8 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi // q2u2 = vec_mul(q2u2, q2s2); // q2u3 = vec_mul(q2u3, q2s3); -// const int32x4_t p1 = ggml_vec_dot(ggml_vec_dot(vec_splat_s32(0), q2u0, q8b0), q2u1, q8b1); -// const int32x4_t p2 = ggml_vec_dot(ggml_vec_dot(vec_splat_s32(0), q2u2, q8b2), q2u3, q8b3); +// const int32x4_t p1 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splat_s32(0), q2u0, q8b0), q2u1, q8b1); +// const int32x4_t p2 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splat_s32(0), q2u2, q8b2), q2u3, q8b3); // sumf1 += (p1[0] + p1[1] + p1[2] + p1[3]) * (0.5f + (aux32[1] >> 28)); // sumf2 += (p2[0] + p2[1] + p2[2] + p2[3]) * (0.5f + (aux32[3] >> 28)); @@ -1445,7 +1445,7 @@ void ggml_vec_dot_iq4_nl_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const v const int8x16_t v_yl = vec_xl(0 , y0->qs); const int8x16_t v_yh = vec_xl(QK8_0/2, y0->qs); - const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); + const int32x4_t v_xy = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_xl, v_yl), v_xh, v_yh); sumf += GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d) * vec_hsum_i32x4(v_xy); } @@ -1508,8 +1508,8 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v const int8x16_t v_y3 = vec_xl(48, q8); q8 += 64; - int32x4_t vsumi0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0l, v_y0), v_x0h, v_y1); - int32x4_t vsumi1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1l, v_y2), v_x1h, v_y3); + int32x4_t vsumi0 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x0l, v_y0), v_x0h, v_y1); + int32x4_t vsumi1 = ggml_vec_dot_s32(ggml_vec_dot_s32(vec_splats(0), v_x1l, v_y2), v_x1h, v_y3); int ls1 = ((x[ibl].scales_l[ib] & 0xF) | ((h << 4) & 0x30)) - 32; int ls2 = ((x[ibl].scales_l[ib] >> 4) | ((h << 2) & 0x30)) - 32; diff --git a/ggml/src/ggml-cpu/arch/s390/repack.cpp b/ggml/src/ggml-cpu/arch/s390/repack.cpp index abf3433adda2..c12fe215e80e 100644 --- a/ggml/src/ggml-cpu/arch/s390/repack.cpp +++ b/ggml/src/ggml-cpu/arch/s390/repack.cpp @@ -70,23 +70,6 @@ void ggml_quantize_mat_q8_0_4x4(const float * GGML_RESTRICT x, void * GGML_RESTR #endif } -#if defined(__VXE__) || defined(__VXE2__) -static inline int16x8_t vxe_dot_acc(const int8x16_t v_x, const int8x16_t v_y, const int16x8_t v_acc) { - return vec_meadd(v_x, v_y, vec_moadd(v_x, v_y, v_acc)); -} - -static inline int8x16_t vxe_splat_granule(const int8_t * qs) { - uint32_t g; - memcpy(&g, qs, sizeof(g)); - return (int8x16_t)vec_splats(g); -} - -static inline int32x4_t vxe_fold(const int16x8_t v_sumi) { - const int16x8_t v_ones = vec_splats((int16_t)1); - return vec_add(vec_mule(v_sumi, v_ones), vec_mulo(v_sumi, v_ones)); -} -#endif - void ggml_gemv_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { const int qk = QK8_0; const int nb = n / qk; @@ -131,21 +114,21 @@ void ggml_gemv_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo int16x8_t v_sumi = vec_splats((int16_t)0); - v_sumi = vxe_dot_acc(v_x0l, vxe_splat_granule(y_lo + 0), v_sumi); - v_sumi = vxe_dot_acc(v_x1l, vxe_splat_granule(y_lo + 4), v_sumi); - v_sumi = vxe_dot_acc(v_x2l, vxe_splat_granule(y_lo + 8), v_sumi); - v_sumi = vxe_dot_acc(v_x3l, vxe_splat_granule(y_lo + 12), v_sumi); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x0l, ggml_vec_xl_s8x4_splat(y_lo + 0)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x1l, ggml_vec_xl_s8x4_splat(y_lo + 4)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x2l, ggml_vec_xl_s8x4_splat(y_lo + 8)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x3l, ggml_vec_xl_s8x4_splat(y_lo + 12)); - v_sumi = vxe_dot_acc(v_x0h, vxe_splat_granule(y_hi + 0), v_sumi); - v_sumi = vxe_dot_acc(v_x1h, vxe_splat_granule(y_hi + 4), v_sumi); - v_sumi = vxe_dot_acc(v_x2h, vxe_splat_granule(y_hi + 8), v_sumi); - v_sumi = vxe_dot_acc(v_x3h, vxe_splat_granule(y_hi + 12), v_sumi); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x0h, ggml_vec_xl_s8x4_splat(y_hi + 0)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x1h, ggml_vec_xl_s8x4_splat(y_hi + 4)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x2h, ggml_vec_xl_s8x4_splat(y_hi + 8)); + v_sumi = ggml_vec_dot_s16(v_sumi, v_x3h, ggml_vec_xl_s8x4_splat(y_hi + 12)); const float32x4_t v_yd = vec_splats(GGML_CPU_FP16_TO_FP32(a_ptr[l].d)); - const float32x4_t v_xd = __lzs_f16cx4_load(b_ptr[l].d); + const float32x4_t v_xd = ggml_vec_xl_f16x4_finite(b_ptr[l].d); const float32x4_t v_d = vec_mul(v_yd, v_xd); - v_sumf = vec_madd(vec_float(vxe_fold(v_sumi)), v_d, v_sumf); + v_sumf = vec_madd(vec_float(vec_paddl_s16(v_sumi)), v_d, v_sumf); } vec_xst(v_sumf, 0, res_ptr + x * ncols_interleaved); @@ -192,24 +175,24 @@ void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo const int8_t * y_lo = a_ptr[l].qs + 16 * k; const int8_t * y_hi = y_lo + qk / 2 * 4; - v_sumi0 = vxe_dot_acc(v_xl, vxe_splat_granule(y_lo + 0), v_sumi0); - v_sumi1 = vxe_dot_acc(v_xl, vxe_splat_granule(y_lo + 4), v_sumi1); - v_sumi2 = vxe_dot_acc(v_xl, vxe_splat_granule(y_lo + 8), v_sumi2); - v_sumi3 = vxe_dot_acc(v_xl, vxe_splat_granule(y_lo + 12), v_sumi3); + v_sumi0 = ggml_vec_dot_s16(v_sumi0, v_xl, ggml_vec_xl_s8x4_splat(y_lo + 0)); + v_sumi1 = ggml_vec_dot_s16(v_sumi1, v_xl, ggml_vec_xl_s8x4_splat(y_lo + 4)); + v_sumi2 = ggml_vec_dot_s16(v_sumi2, v_xl, ggml_vec_xl_s8x4_splat(y_lo + 8)); + v_sumi3 = ggml_vec_dot_s16(v_sumi3, v_xl, ggml_vec_xl_s8x4_splat(y_lo + 12)); - v_sumi0 = vxe_dot_acc(v_xh, vxe_splat_granule(y_hi + 0), v_sumi0); - v_sumi1 = vxe_dot_acc(v_xh, vxe_splat_granule(y_hi + 4), v_sumi1); - v_sumi2 = vxe_dot_acc(v_xh, vxe_splat_granule(y_hi + 8), v_sumi2); - v_sumi3 = vxe_dot_acc(v_xh, vxe_splat_granule(y_hi + 12), v_sumi3); + v_sumi0 = ggml_vec_dot_s16(v_sumi0, v_xh, ggml_vec_xl_s8x4_splat(y_hi + 0)); + v_sumi1 = ggml_vec_dot_s16(v_sumi1, v_xh, ggml_vec_xl_s8x4_splat(y_hi + 4)); + v_sumi2 = ggml_vec_dot_s16(v_sumi2, v_xh, ggml_vec_xl_s8x4_splat(y_hi + 8)); + v_sumi3 = ggml_vec_dot_s16(v_sumi3, v_xh, ggml_vec_xl_s8x4_splat(y_hi + 12)); } const float32x4_t v_yd = __lzs_f16cx4_load(a_ptr[l].d); - const float32x4_t v_xd = __lzs_f16cx4_load(b_ptr[l].d); + const float32x4_t v_xd = ggml_vec_xl_f16x4_finite(b_ptr[l].d); - v_sumf[0] = vec_madd(vec_float(vxe_fold(v_sumi0)), vec_mul(v_xd, vec_splat(v_yd, 0)), v_sumf[0]); - v_sumf[1] = vec_madd(vec_float(vxe_fold(v_sumi1)), vec_mul(v_xd, vec_splat(v_yd, 1)), v_sumf[1]); - v_sumf[2] = vec_madd(vec_float(vxe_fold(v_sumi2)), vec_mul(v_xd, vec_splat(v_yd, 2)), v_sumf[2]); - v_sumf[3] = vec_madd(vec_float(vxe_fold(v_sumi3)), vec_mul(v_xd, vec_splat(v_yd, 3)), v_sumf[3]); + v_sumf[0] = vec_madd(vec_float(vec_paddl_s16(v_sumi0)), vec_mul(v_xd, vec_splat(v_yd, 0)), v_sumf[0]); + v_sumf[1] = vec_madd(vec_float(vec_paddl_s16(v_sumi1)), vec_mul(v_xd, vec_splat(v_yd, 1)), v_sumf[1]); + v_sumf[2] = vec_madd(vec_float(vec_paddl_s16(v_sumi2)), vec_mul(v_xd, vec_splat(v_yd, 2)), v_sumf[2]); + v_sumf[3] = vec_madd(vec_float(vec_paddl_s16(v_sumi3)), vec_mul(v_xd, vec_splat(v_yd, 3)), v_sumf[3]); } for (int m = 0; m < 4; m++) { diff --git a/ggml/src/ggml-cpu/common.h b/ggml/src/ggml-cpu/common.h index abbadc359c5a..2c62e6976fe4 100644 --- a/ggml/src/ggml-cpu/common.h +++ b/ggml/src/ggml-cpu/common.h @@ -43,6 +43,14 @@ static inline float f32_to_f32(float x) { return x; } +static inline float f8_e4m3_to_f32(ggml_fp8_e4m3_t x) { + return ggml_f8_e4m3_to_fp32(x.bits); +} + +static inline ggml_fp8_e4m3_t f32_to_f8_e4m3(float x) { + return { ggml_fp32_to_f8_e4m3(x) }; +} + // TODO - merge this into the traits table, after using row-based conversions template struct type_conversion_table; @@ -65,6 +73,12 @@ struct type_conversion_table { static constexpr ggml_bf16_t (*from_f32)(float) = f32_to_bf16; }; +template <> +struct type_conversion_table { + static constexpr float (*to_f32)(ggml_fp8_e4m3_t) = f8_e4m3_to_f32; + static constexpr ggml_fp8_e4m3_t (*from_f32)(float) = f32_to_f8_e4m3; +}; + template <> struct type_conversion_table { static constexpr float (*to_f32)(int32_t) = i32_to_f32; diff --git a/ggml/src/ggml-cpu/ggml-cpu-impl.h b/ggml/src/ggml-cpu/ggml-cpu-impl.h index 82345b2063bd..865847a7785f 100644 --- a/ggml/src/ggml-cpu/ggml-cpu-impl.h +++ b/ggml/src/ggml-cpu/ggml-cpu-impl.h @@ -30,7 +30,7 @@ struct ggml_compute_params { }; -#if defined(_MSC_VER) +#if defined(_MSC_VER) && !defined(__clang__) #define m512bh(p) p #define m512i(p) p @@ -443,6 +443,13 @@ inline static ggml_int8x16x4_t ggml_vec_xl_s8x4(const int8_t * ptr) { return res; } +// load 4 bytes and replicate them into all 4 word lanes +inline static int8x16_t ggml_vec_xl_s8x4_splat(const int8_t * ptr) { + uint32_t tmp; + memcpy(&tmp, ptr, sizeof(tmp)); + return (int8x16_t)vec_splats(tmp); +} + typedef struct ggml_int16x8x2_t { int16x8_t val[2]; } ggml_int16x8x2_t; @@ -456,31 +463,17 @@ inline static ggml_int16x8x2_t ggml_vec_xl_s16x2(const int16_t * ptr) { return res; } -/* - ! WARNING: Very slow. Use vec_perm if possible. Refer to iq4_xs - ! or iq4_nl for example implementation. -*/ -inline static int8x16_t ggml_vec_tbl(int8x16_t a, uint8x16_t b) { - int8x16_t res; - - res[ 0] = a[b[ 0]]; - res[ 1] = a[b[ 1]]; - res[ 2] = a[b[ 2]]; - res[ 3] = a[b[ 3]]; - res[ 4] = a[b[ 4]]; - res[ 5] = a[b[ 5]]; - res[ 6] = a[b[ 6]]; - res[ 7] = a[b[ 7]]; - res[ 8] = a[b[ 8]]; - res[ 9] = a[b[ 9]]; - res[10] = a[b[10]]; - res[11] = a[b[11]]; - res[12] = a[b[12]]; - res[13] = a[b[13]]; - res[14] = a[b[14]]; - res[15] = a[b[15]]; - - return res; +// faster fp16 -> fp32 conversion using vector intrinsics +// WARNING: fp16 inf converts into 65536.0f. use this only for finite values. +inline static float32x4_t ggml_vec_xl_f16x4_finite(const ggml_fp16_t * x) { + uint64_t tmp; + memcpy(&tmp, x, sizeof(tmp)); + + const uint64x2_t v_x = { tmp, tmp }; + const uint32x4_t v_xh = vec_unpackh((uint16x8_t)v_x); + const uint32x4_t v_bits = vec_sl(vec_and(v_xh, vec_splats((uint32_t)0x7FFF)), 13); + const float32x4_t v_abs = vec_mul((float32x4_t)v_bits, vec_splats(0x1.0p+112f)); + return (float32x4_t)vec_or((uint32x4_t)v_abs, vec_sl(vec_and(v_xh, vec_splats((uint32_t)0x8000)), 16)); } inline static int16x8_t vec_padd_s16(int16x8_t a, int16x8_t b) { @@ -492,6 +485,11 @@ inline static int16x8_t vec_padd_s16(int16x8_t a, int16x8_t b) { return v_abo + v_abe; } +inline static int32x4_t vec_paddl_s16(int16x8_t a) { + const int16x8_t v_ones = vec_splats((int16_t)1); + return vec_mule(a, v_ones) + vec_mulo(a, v_ones); +} + /** * @see https://github.com/ggml-org/llama.cpp/pull/14037 */ @@ -505,7 +503,11 @@ inline static int32_t vec_hsum_i32x4(int32x4_t v) { return v_temp[0] + v_temp[1]; } -inline static int32x4_t ggml_vec_dot(int32x4_t acc, int8x16_t a, int8x16_t b) { +inline static int16x8_t ggml_vec_dot_s16(int16x8_t acc, int8x16_t a, int8x16_t b) { + return vec_meadd(a, b, vec_moadd(a, b, acc)); +} + +inline static int32x4_t ggml_vec_dot_s32(int32x4_t acc, int8x16_t a, int8x16_t b) { const int16x8_t p = vec_mule(a, b) + vec_mulo(a, b); return acc + (vec_unpackh(p) + vec_unpackl(p)); } diff --git a/ggml/src/ggml-cpu/ggml-cpu.c b/ggml/src/ggml-cpu/ggml-cpu.c index f91bba4f78d2..de29160c3095 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.c +++ b/ggml/src/ggml-cpu/ggml-cpu.c @@ -86,6 +86,9 @@ float ggml_table_f32_e8m0_half[1 << 8]; // precomputed f32 table for ue4m3 (1 KB) (simd-mappings.h) float ggml_table_f32_ue4m3[1 << 8]; +// Signed FP8 needs its own table: UE4M3 ignores the sign, halves values for NVFP4, and maps NaN to zero. +float ggml_table_f32_f8_e4m3[1 << 8]; + #if defined(__ARM_ARCH) struct ggml_arm_arch_features_type { int sve_cnt; @@ -308,6 +311,12 @@ static const struct ggml_type_traits_cpu type_traits_cpu[GGML_TYPE_COUNT] = { .vec_dot_type = GGML_TYPE_Q8_0, .nrows = 1, }, + [GGML_TYPE_F8_E4M3] = { + .from_float = quantize_row_f8_e4m3, + .vec_dot = ggml_vec_dot_f8_e4m3_f32, + .vec_dot_type = GGML_TYPE_F32, + .nrows = 1, + }, [GGML_TYPE_Q2_K] = { .from_float = quantize_row_q2_K, .vec_dot = ggml_vec_dot_q2_K_q8_K, @@ -1664,7 +1673,12 @@ static void ggml_compute_forward_mul_mat_id( for (int id = 0; id < n_ids; ++id) { const int32_t i02 = *(const int32_t *) ((const char *) ids->data + iid1*ids->nb[1] + id*ids->nb[0]); - assert(i02 >= 0 && i02 < n_as); + assert(i02 == -1 || (i02 >= 0 && i02 < n_as)); + + if (i02 == -1) { + memset((char *) dst->data + id*nb1 + iid1*nb2, 0, ne0*sizeof(float)); + continue; + } MMID_MATRIX_ROW(i02, matrix_row_counts[i02]) = (struct mmid_row_mapping) {id, iid1}; matrix_row_counts[i02] += 1; @@ -2117,6 +2131,10 @@ static void ggml_compute_forward(struct ggml_compute_params * params, struct ggm { ggml_compute_forward_dsv4_hc_post(params, tensor); } break; + case GGML_OP_TOP_K_MASK: + { + ggml_compute_forward_top_k_mask(params, tensor); + } break; case GGML_OP_MAP_CUSTOM1: { ggml_compute_forward_map_custom1(params, tensor); @@ -2300,6 +2318,7 @@ static int ggml_get_n_tasks(struct ggml_tensor * node, int n_threads) { case GGML_OP_DSV4_HC_COMB: case GGML_OP_DSV4_HC_PRE: case GGML_OP_DSV4_HC_POST: + case GGML_OP_TOP_K_MASK: { n_tasks = n_threads; } break; @@ -2878,7 +2897,7 @@ struct ggml_cplan ggml_graph_plan( case GGML_OP_ADD_ID: case GGML_OP_ADD1: { - if (ggml_is_quantized(node->src[0]->type)) { + if (ggml_is_quantized(node->src[0]->type) || node->src[0]->type == GGML_TYPE_F8_E4M3) { cur = ggml_type_size(GGML_TYPE_F32) * node->src[0]->ne[0] * n_tasks; } } break; @@ -2926,7 +2945,7 @@ struct ggml_cplan ggml_graph_plan( } break; case GGML_OP_OUT_PROD: { - if (ggml_is_quantized(node->src[0]->type) || + if (ggml_is_quantized(node->src[0]->type) || node->src[0]->type == GGML_TYPE_F8_E4M3 || node->src[0]->type == GGML_TYPE_F16) { cur = ggml_type_size(GGML_TYPE_F32) * node->src[0]->ne[0] * n_tasks; } @@ -3910,6 +3929,7 @@ void ggml_cpu_init(void) { // initialize UE4M3 table (256 entries) for (int i = 0; i < (1 << 8); ++i) { ggml_table_f32_ue4m3[i] = ggml_ue4m3_to_fp32(i); + ggml_table_f32_f8_e4m3[i] = ggml_f8_e4m3_to_fp32(i); } const uint64_t t_end = ggml_time_us(); UNUSED(t_end); diff --git a/ggml/src/ggml-cpu/kleidiai/kernels.cpp b/ggml/src/ggml-cpu/kleidiai/kernels.cpp index 89e95968cd91..24aa2824493f 100644 --- a/ggml/src/ggml-cpu/kleidiai/kernels.cpp +++ b/ggml/src/ggml-cpu/kleidiai/kernels.cpp @@ -201,85 +201,117 @@ static struct kai_matmul_uker_config q4_k_matmul_config() { return config; } -template -static size_t q4_k_get_m_step() { - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - return api.get_step(&config).m; +static struct kai_matmul_uker_config default_matmul_config() { + return {}; } -template -static size_t q4_k_get_n_step() { - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - return api.get_step(&config).n; -} +template< + struct kai_matmul_uker_api (*GetApi)(void), + struct kai_matmul_uker_config (*GetConfig)(void), + size_t MR, size_t NR, size_t KR, size_t SR> +struct matmul_uker_adapter { + static size_t get_m_step() { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + return api.get_step(&config).m; + } -template -static size_t q4_k_get_constant() { - return Value; -} + static size_t get_n_step() { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + return api.get_step(&config).n; + } -template -static size_t q4_k_get_dst_offset(size_t m_idx, size_t n_idx, size_t dst_stride) { - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - const struct kai_matmul_uker_dst_dim_args index = { m_idx, n_idx }; - const struct kai_matmul_uker_dst_stride_args stride = { dst_stride }; - return api.get_dst_offset(&config, &index, &stride); -} + static size_t get_mr() { + if constexpr (MR == 0) { + return get_m_step(); + } + return MR; + } -template -static size_t q4_k_get_lhs_packed_offset(size_t m_idx, size_t k, size_t bl) { - GGML_ASSERT(bl == KLEIDIAI_Q4_K_BLOCK_LENGTH); + static size_t get_nr() { + if constexpr (NR == 0) { + return get_n_step(); + } + return NR; + } - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - const struct kai_matmul_uker_lhs_dim_args shape = { m_idx, k }; - const struct kai_matmul_uker_lhs_dim_args index = { m_idx, 0 }; - const struct kai_matmul_uker_lhs_stride_args stride = api.get_lhs_stride(&config, &shape); - return api.get_lhs_offset(&config, &index, &stride); -} + static size_t get_kr() { + return KR; + } -template -static size_t q4_k_get_rhs_packed_offset(size_t n_idx, size_t k, size_t bl) { - GGML_ASSERT(bl == KLEIDIAI_Q4_K_BLOCK_LENGTH); + static size_t get_sr() { + return SR; + } - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - const struct kai_matmul_uker_rhs_dim_args shape = { n_idx, k }; - const struct kai_matmul_uker_rhs_dim_args index = { n_idx, 0 }; - const struct kai_matmul_uker_rhs_stride_args stride = api.get_rhs_stride(&config, &shape); - return api.get_rhs_offset(&config, &index, &stride); -} + static size_t get_dst_offset(size_t m_idx, size_t n_idx, size_t dst_stride) { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + const struct kai_matmul_uker_dst_dim_args index = { m_idx, n_idx }; + const struct kai_matmul_uker_dst_stride_args stride = { dst_stride }; + return api.get_dst_offset(&config, &index, &stride); + } -template -static void q4_k_run_matmul( - size_t m, size_t n, size_t k, size_t bl, - const void * lhs_packed, const void * rhs_packed, - void * dst, size_t dst_stride_row, size_t dst_stride_col, - float clamp_min, float clamp_max) { - GGML_ASSERT(bl == KLEIDIAI_Q4_K_BLOCK_LENGTH); - GGML_ASSERT(dst_stride_col == sizeof(float)); - - const struct kai_matmul_uker_api api = GetApi(); - const struct kai_matmul_uker_config config = q4_k_matmul_config(); - const struct kai_matmul_uker_lhs_dim_args lhs_shape = { m, k }; - const struct kai_matmul_uker_rhs_dim_args rhs_shape = { n, k }; - - struct kai_matmul_uker_args args = {}; - args.flags = KAI_MATMUL_UKER_FLAGS_ARGS_CLAMP; - args.shape = { m, n, k }; - args.operand.lhs.ptr = lhs_packed; - args.operand.lhs.stride = api.get_lhs_stride(&config, &lhs_shape); - args.operand.rhs.ptr = rhs_packed; - args.operand.rhs.stride = api.get_rhs_stride(&config, &rhs_shape); - args.operand.dst.ptr = dst; - args.operand.dst.stride.m = dst_stride_row; - args.activation.clamp.min_ptr = &clamp_min; - args.activation.clamp.max_ptr = &clamp_max; - api.run(&config, &args); -} + static size_t get_lhs_packed_offset(size_t m_idx, size_t k, size_t bl) { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + GGML_ASSERT(bl == config.format.bl); + const struct kai_matmul_uker_lhs_dim_args shape = { m_idx, k }; + const struct kai_matmul_uker_lhs_dim_args index = { m_idx, 0 }; + const struct kai_matmul_uker_lhs_stride_args stride = api.get_lhs_stride(&config, &shape); + return api.get_lhs_offset(&config, &index, &stride); + } + + static size_t get_rhs_packed_offset(size_t n_idx, size_t k, size_t bl) { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + GGML_ASSERT(bl == config.format.bl); + const struct kai_matmul_uker_rhs_dim_args shape = { n_idx, k }; + const struct kai_matmul_uker_rhs_dim_args index = { n_idx, 0 }; + const struct kai_matmul_uker_rhs_stride_args stride = api.get_rhs_stride(&config, &shape); + return api.get_rhs_offset(&config, &index, &stride); + } + + static void run( + size_t m, size_t n, size_t k, size_t bl, + const void * lhs_packed, const void * rhs_packed, + void * dst, size_t dst_stride_row, size_t dst_stride_col, + float clamp_min, float clamp_max) { + const struct kai_matmul_uker_api api = GetApi(); + const struct kai_matmul_uker_config config = GetConfig(); + GGML_ASSERT(bl == config.format.bl); + GGML_ASSERT(dst_stride_col == sizeof(float)); + const struct kai_matmul_uker_lhs_dim_args lhs_shape = { m, k }; + const struct kai_matmul_uker_rhs_dim_args rhs_shape = { n, k }; + + struct kai_matmul_uker_args args = {}; + args.flags = KAI_MATMUL_UKER_FLAGS_ARGS_CLAMP; + args.shape = { m, n, k }; + args.operand.lhs.ptr = lhs_packed; + args.operand.lhs.stride = api.get_lhs_stride(&config, &lhs_shape); + args.operand.rhs.ptr = rhs_packed; + args.operand.rhs.stride = api.get_rhs_stride(&config, &rhs_shape); + args.operand.dst.ptr = dst; + args.operand.dst.stride.m = dst_stride_row; + args.activation.clamp.min_ptr = &clamp_min; + args.activation.clamp.max_ptr = &clamp_max; + api.run(&config, &args); + } +}; + +using q4_k_gemm_adapter = matmul_uker_adapter< + kai_matmul_clamp_f32_f16p4vsx2_qai4c32p16vsx4s1s0sf16_4vsx16vs_sme2_mopa, + q4_k_matmul_config, 0, 0, 4, 2>; +using q4_k_gemv_adapter = matmul_uker_adapter< + kai_matmul_clamp_f32_qsi8d32p1x4_qai4c32p16vsx4s1s0sf16_1x16vs_sme2_dot, + q4_k_matmul_config, 0, 0, 4, 2>; +// GEMM and GEMV share the RHS layout only at SVE256 (NR=8, KR=8, SR=1). +using sve_q8_gemm_adapter = matmul_uker_adapter< + kai_matmul_clamp_f32_qai8dxp4x8sf32_qsi8cxp4vsx8sf32bf32_16x4vs_sve_i8mm, + default_matmul_config, 4, 0, 8, 1>; +using sve_q8_gemv_adapter = matmul_uker_adapter< + kai_matmul_clamp_f32_qai8dxp1x8_qsi8cxp8x8_1x8_sve_dot, + default_matmul_config, 1, 8, 8, 1>; static struct kai_matmul_pack_lhs_uker_config q4_k_lhs_pack_config() { struct kai_matmul_pack_lhs_uker_config config = {}; @@ -628,7 +660,7 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .packed_size_ex = */ &rhs_ps_fn5, /* .pack_func_ex = */ &rhs_pack_fn12, }, - /* .required_cpu = */ CPU_FEATURE_SVE | CPU_FEATURE_I8MM | CPU_FEATURE_DOTPROD, + /* .required_cpu = */ CPU_FEATURE_SVE | CPU_FEATURE_SVEI8MM | CPU_FEATURE_DOTPROD, /* .lhs_type = */ GGML_TYPE_F32, /* .rhs_type = */ GGML_TYPE_Q4_0, /* .op_type = */ GGML_TYPE_F32, @@ -737,16 +769,16 @@ static ggml_kleidiai_kernels gemm_gemv_kernels_q4_k[] = { { /* SME2 GEMM */ { - /* .get_m_step = */ &q4_k_get_m_step, - /* .get_n_step = */ &q4_k_get_n_step, - /* .get_mr = */ &q4_k_get_m_step, - /* .get_nr = */ &q4_k_get_n_step, - /* .get_kr = */ &q4_k_get_constant<4>, - /* .get_sr = */ &q4_k_get_constant<2>, - /* .get_dst_offset = */ &q4_k_get_dst_offset, - /* .get_lhs_offset_ex = */ &q4_k_get_lhs_packed_offset, - /* .get_rhs_packed_offset_ex = */ &q4_k_get_rhs_packed_offset, - /* .run_kernel_ex = */ &q4_k_run_matmul, + /* .get_m_step = */ q4_k_gemm_adapter::get_m_step, + /* .get_n_step = */ q4_k_gemm_adapter::get_n_step, + /* .get_mr = */ q4_k_gemm_adapter::get_mr, + /* .get_nr = */ q4_k_gemm_adapter::get_nr, + /* .get_kr = */ q4_k_gemm_adapter::get_kr, + /* .get_sr = */ q4_k_gemm_adapter::get_sr, + /* .get_dst_offset = */ q4_k_gemm_adapter::get_dst_offset, + /* .get_lhs_offset_ex = */ q4_k_gemm_adapter::get_lhs_packed_offset, + /* .get_rhs_packed_offset_ex = */ q4_k_gemm_adapter::get_rhs_packed_offset, + /* .run_kernel_ex = */ q4_k_gemm_adapter::run, }, { /* .get_offset = */ kai_get_lhs_offset_lhs_pack_f16pmrx2_f32_neon, @@ -756,16 +788,16 @@ static ggml_kleidiai_kernels gemm_gemv_kernels_q4_k[] = { }, /* SME2 GEMV */ { - /* .get_m_step = */ &q4_k_get_m_step, - /* .get_n_step = */ &q4_k_get_n_step, - /* .get_mr = */ &q4_k_get_m_step, - /* .get_nr = */ &q4_k_get_n_step, - /* .get_kr = */ &q4_k_get_constant<4>, - /* .get_sr = */ &q4_k_get_constant<2>, - /* .get_dst_offset = */ &q4_k_get_dst_offset, - /* .get_lhs_offset_ex = */ &q4_k_get_lhs_packed_offset, - /* .get_rhs_packed_offset_ex = */ &q4_k_get_rhs_packed_offset, - /* .run_kernel_ex = */ &q4_k_run_matmul, + /* .get_m_step = */ q4_k_gemv_adapter::get_m_step, + /* .get_n_step = */ q4_k_gemv_adapter::get_n_step, + /* .get_mr = */ q4_k_gemv_adapter::get_mr, + /* .get_nr = */ q4_k_gemv_adapter::get_nr, + /* .get_kr = */ q4_k_gemv_adapter::get_kr, + /* .get_sr = */ q4_k_gemv_adapter::get_sr, + /* .get_dst_offset = */ q4_k_gemv_adapter::get_dst_offset, + /* .get_lhs_offset_ex = */ q4_k_gemv_adapter::get_lhs_packed_offset, + /* .get_rhs_packed_offset_ex = */ q4_k_gemv_adapter::get_rhs_packed_offset, + /* .run_kernel_ex = */ q4_k_gemv_adapter::run, }, { /* .get_offset = */ q4_k_lhs_get_offset, @@ -883,6 +915,54 @@ static ggml_kleidiai_kernels gemm_gemv_kernels_q8[] = { /* .rhs_type = */ GGML_TYPE_Q8_0, /* .op_type = */ GGML_TYPE_F32, }, + { + /* SVE I8MM GEMM */ + { + /* .get_m_step = */ sve_q8_gemm_adapter::get_m_step, + /* .get_n_step = */ sve_q8_gemm_adapter::get_n_step, + /* .get_mr = */ sve_q8_gemm_adapter::get_mr, + /* .get_nr = */ sve_q8_gemm_adapter::get_nr, + /* .get_kr = */ sve_q8_gemm_adapter::get_kr, + /* .get_sr = */ sve_q8_gemm_adapter::get_sr, + /* .get_dst_offset = */ sve_q8_gemm_adapter::get_dst_offset, + /* .get_lhs_offset_ex = */ sve_q8_gemm_adapter::get_lhs_packed_offset, + /* .get_rhs_packed_offset_ex = */ sve_q8_gemm_adapter::get_rhs_packed_offset, + /* .run_kernel_ex = */ sve_q8_gemm_adapter::run, + }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qai8dxp_f32, + /* .get_packed_offset_ex = */ &lhs_offs_fn5, + /* .packed_size_ex = */ &lhs_ps_fn5, + /* .pack_func_ex = */ &lhs_pack_float_fn9_no_bl, + }, + /* SVE DOT GEMV */ + { + /* .get_m_step = */ sve_q8_gemv_adapter::get_m_step, + /* .get_n_step = */ sve_q8_gemv_adapter::get_n_step, + /* .get_mr = */ sve_q8_gemv_adapter::get_mr, + /* .get_nr = */ sve_q8_gemv_adapter::get_nr, + /* .get_kr = */ sve_q8_gemv_adapter::get_kr, + /* .get_sr = */ sve_q8_gemv_adapter::get_sr, + /* .get_dst_offset = */ sve_q8_gemv_adapter::get_dst_offset, + /* .get_lhs_offset_ex = */ sve_q8_gemv_adapter::get_lhs_packed_offset, + /* .get_rhs_packed_offset_ex = */ sve_q8_gemv_adapter::get_rhs_packed_offset, + /* .run_kernel_ex = */ sve_q8_gemv_adapter::run, + }, + /* .gemv_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qai8dxp_f32, + /* .get_packed_offset_ex = */ &lhs_offs_fn5, + /* .packed_size_ex = */ &lhs_ps_fn5, + /* .pack_func_ex = */ &lhs_pack_float_fn9_no_bl, + }, + /* .rhs_info = */ { + /* .packed_size_ex = */ &rhs_ps_fn5, + /* .pack_func_ex = */ &rhs_pack_scale_fn12, + }, + /* .required_cpu = */ CPU_FEATURE_SVE | CPU_FEATURE_SVEI8MM | CPU_FEATURE_DOTPROD, + /* .lhs_type = */ GGML_TYPE_F32, + /* .rhs_type = */ GGML_TYPE_Q8_0, + /* .op_type = */ GGML_TYPE_F32, + }, { /* I8MM GEMM */ { diff --git a/ggml/src/ggml-cpu/kleidiai/kernels.h b/ggml/src/ggml-cpu/kleidiai/kernels.h index 308ea945182f..ac5d5d302e88 100644 --- a/ggml/src/ggml-cpu/kleidiai/kernels.h +++ b/ggml/src/ggml-cpu/kleidiai/kernels.h @@ -13,7 +13,8 @@ enum cpu_feature { CPU_FEATURE_SVE = 4, CPU_FEATURE_SME = 8, CPU_FEATURE_SME2 = 16, - CPU_FEATURE_FP16 = 32 + CPU_FEATURE_FP16 = 32, + CPU_FEATURE_SVEI8MM = 64 }; inline cpu_feature& operator|=(cpu_feature& lhs, cpu_feature rhs) { diff --git a/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp b/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp index dd9bcbf6347a..57a4a5662e89 100644 --- a/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp +++ b/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp @@ -319,8 +319,10 @@ static void init_kleidiai_context(void) { size_t detected_smcus = 0; + // The fixed-width SVE kernels require 32-byte vectors, including the Q8 shared RHS layout. ctx.features = (runtime_feat.has_dotprod ? CPU_FEATURE_DOTPROD : CPU_FEATURE_NONE) | (runtime_feat.has_i8mm ? CPU_FEATURE_I8MM : CPU_FEATURE_NONE) | + (runtime_feat.has_svei8mm ? CPU_FEATURE_SVEI8MM : CPU_FEATURE_NONE) | (runtime_feat.has_fp16 ? CPU_FEATURE_FP16 : CPU_FEATURE_NONE) | (runtime_feat.sve_cnt == QK8_0 ? CPU_FEATURE_SVE : CPU_FEATURE_NONE); @@ -1616,6 +1618,11 @@ class tensor_traits : public ggml::cpu::tensor_traits { const size_t kr = kernel->get_kr(); const size_t sr = kernel->get_sr(); const ggml_type rhs_type = kernels->rhs_type; + if (rhs_type == GGML_TYPE_Q8_0 && (kernels->required_cpu & CPU_FEATURE_SVE)) { + GGML_ASSERT(nr == kernels->gemv.get_nr()); + GGML_ASSERT(kr == kernels->gemv.get_kr()); + GGML_ASSERT(sr == kernels->gemv.get_sr()); + } const size_t block_len = rhs_type == GGML_TYPE_Q8_0 ? QK8_0 : rhs_type == GGML_TYPE_Q4_0 ? QK4_0 : rhs_type == GGML_TYPE_Q4_K ? GGML_KLEIDIAI_Q4_K_BL : diff --git a/ggml/src/ggml-cpu/ops.cpp b/ggml/src/ggml-cpu/ops.cpp index 9bc46c935f86..d8b8fe6d379c 100644 --- a/ggml/src/ggml-cpu/ops.cpp +++ b/ggml/src/ggml-cpu/ops.cpp @@ -537,26 +537,36 @@ void ggml_compute_forward_dup( switch (src0->type) { case GGML_TYPE_F16: { - /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F8_E4M3) ggml_compute_forward_dup_flt(params, dst); else ggml_compute_forward_dup_to_q(params, dst); } break; case GGML_TYPE_BF16: { - /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F8_E4M3) ggml_compute_forward_dup_flt(params, dst); else ggml_compute_forward_dup_to_q(params, dst); } break; case GGML_TYPE_F32: { - /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); - else if (dst->type == GGML_TYPE_I32) ggml_compute_forward_dup_flt(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F8_E4M3) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_I32) ggml_compute_forward_dup_flt(params, dst); else ggml_compute_forward_dup_to_q(params, dst); } break; + case GGML_TYPE_F8_E4M3: + { + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else GGML_ABORT("not implemented"); + } break; case GGML_TYPE_I32: { if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); @@ -605,8 +615,9 @@ static void ggml_compute_forward_add_q_f32( GGML_ASSERT(nb1 <= nb2); GGML_ASSERT(nb2 <= nb3); - GGML_ASSERT(ggml_is_quantized(src0->type)); + GGML_ASSERT(ggml_is_quantized(src0->type) || src0->type == GGML_TYPE_F8_E4M3); GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(ne00 % ggml_blck_size(type) == 0); // rows per thread const int dr = (nr + nth - 1)/nth; @@ -636,8 +647,6 @@ static void ggml_compute_forward_add_q_f32( float * src1_row = (float *)((char *) src1->data + (i11*nb11 + i12*nb12 + i13*nb13)); void * dst_row = (void *) ((char *) dst->data + ( i1*nb1 + i2*nb2 + i3*nb3)); - assert(ne00 % 32 == 0); - // unquantize row from src0 to temp buffer dequantize_row_q(src0_row, wdata, ne00); // add src1 @@ -673,6 +682,7 @@ void ggml_compute_forward_add( case GGML_TYPE_Q8_0: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -743,12 +753,17 @@ static void ggml_compute_forward_add_id_f32( // src1 indices const int i11 = *(int32_t *) ((char *) src2->data + i1*nb20 + i2*nb21); - GGML_ASSERT(i11 >= 0 && i11 < ne11); + GGML_ASSERT(i11 == -1 || (i11 >= 0 && i11 < ne11)); - ggml_vec_add_f32(ne0, - (float *) ((char *) dst->data + i3*nb3 + i2*nb2 + i1*nb1 ), - (float *) ((char *) src0->data + i3*nb03 + i2*nb02 + i1*nb01), - (float *) ((char *) src1->data + i11*nb11)); + float * dst_row = (float *) ((char *) dst->data + i3*nb3 + i2*nb2 + i1*nb1 ); + const float * src0_row = (float *) ((char *) src0->data + i3*nb03 + i2*nb02 + i1*nb01); + + if (i11 == -1) { + memcpy(dst_row, src0_row, ne0*sizeof(float)); + continue; + } + + ggml_vec_add_f32(ne0, dst_row, src0_row, (float *) ((char *) src1->data + i11*nb11)); } } @@ -950,7 +965,7 @@ static void ggml_compute_forward_add1_q_f32( GGML_ASSERT(nb1 <= nb2); GGML_ASSERT(nb2 <= nb3); - GGML_ASSERT(ggml_is_quantized(src0->type)); + GGML_ASSERT(ggml_is_quantized(src0->type) || src0->type == GGML_TYPE_F8_E4M3); GGML_ASSERT(dst->type == src0->type); GGML_ASSERT(src1->type == GGML_TYPE_F32); @@ -1125,6 +1140,7 @@ void ggml_compute_forward_add1( case GGML_TYPE_Q8_1: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -1256,6 +1272,7 @@ void ggml_compute_forward_acc( case GGML_TYPE_Q8_1: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q4_0_ROCMFP4: case GGML_TYPE_Q4_0_ROCMFP4_FAST: case GGML_TYPE_Q2_K: @@ -1294,24 +1311,37 @@ static void ggml_compute_forward_sum_f32( } assert(ggml_is_scalar(dst)); - assert(src0->nb[0] == sizeof(float)); GGML_TENSOR_LOCALS(int64_t, ne0, src0, ne) GGML_TENSOR_LOCALS(size_t, nb0, src0, nb) - ggml_float sum = 0; - ggml_float row_sum = 0; + ggml_float sum = 0; - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - for (int64_t i01 = 0; i01 < ne01; i01++) { - ggml_vec_sum_f32_ggf(ne00, - &row_sum, - (float *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03)); - sum += row_sum; + if (nb00 == sizeof(float)) { + ggml_float row_sum = 0; + for (int64_t i03 = 0; i03 < ne03; i03++) { + for (int64_t i02 = 0; i02 < ne02; i02++) { + for (int64_t i01 = 0; i01 < ne01; i01++) { + ggml_vec_sum_f32_ggf(ne00, + &row_sum, + (float *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03)); + sum += row_sum; + } + } + } + } else { + for (int64_t i03 = 0; i03 < ne03; i03++) { + for (int64_t i02 = 0; i02 < ne02; i02++) { + for (int64_t i01 = 0; i01 < ne01; i01++) { + const char * row = (const char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03; + for (int64_t i00 = 0; i00 < ne00; i00++) { + sum += (ggml_float) *(const float *) (row + i00*nb00); + } + } } } } + ((float *) dst->data)[0] = sum; } @@ -1898,213 +1928,87 @@ void ggml_compute_forward_repeat_back( } // ggml_compute_forward_concat -static void ggml_compute_forward_concat_any( - const ggml_compute_params * params, - ggml_tensor * dst) { - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - - const int ith = params->ith; - const int nth = params->nth; +// rows of dst copied together, so that a strided source is read along neighboring rows +static constexpr int64_t GGML_CONCAT_TILE = 32; - GGML_TENSOR_BINARY_OP_LOCALS - - const int32_t dim = ggml_get_op_params_i32(dst, 0); - - GGML_ASSERT(dim >= 0 && dim < 4); - GGML_ASSERT(ggml_is_contiguous_rows(src0)); - GGML_ASSERT(ggml_is_contiguous_rows(src1)); - - int64_t o[4] = {0, 0, 0, 0}; - - if (dim == 0) { - GGML_ASSERT(src0->ne[0] % ggml_blck_size(src0->type) == 0); - GGML_ASSERT(src1->ne[0] % ggml_blck_size(src1->type) == 0); - - o[dim] = src0->ne[dim]/ggml_blck_size(src0->type); - } else { - o[dim] = src0->ne[dim]; - } - - // Region 1: copy rows from src0 - for (int i3 = 0; i3 < ne03; i3++) { - for (int i2 = ith; i2 < ne02; i2 += nth) { - for (int i1 = 0; i1 < ne01; i1++) { - const char * x = (const char *) src0->data + i1*nb01 + i2*nb02 + i3*nb03; - char * y = ( char *) dst->data + i1*nb1 + i2*nb2 + i3*nb3; - memcpy(y, x, ggml_row_size(src0->type, ne00)); - } - } - } - - // Region 2: copy rows from src1, offset into dst by o[] - for (int i3 = 0; i3 < ne13; i3++) { - for (int i2 = ith; i2 < ne12; i2 += nth) { - for (int i1 = 0; i1 < ne11; i1++) { - const char * x = (const char *) src1->data + i1*nb11 + i2*nb12 + i3*nb13; - char * y = ( char *) dst->data + (i1 + o[1])*nb1 + (i2 + o[2])*nb2 + (i3 + o[3])*nb3 + o[0]*nb0; - memcpy(y, x, ggml_row_size(src1->type, ne10)); - } +// copy n_rows rows of n elements of es bytes from a source with element stride nb0, element by element +template +static void ggml_concat_copy_strided(char * y, size_t nby, const char * x, size_t nbx, size_t nb0, int64_t n, int64_t n_rows) { + for (int64_t i0 = 0; i0 < n; i0++) { + for (int64_t r = 0; r < n_rows; r++) { + memcpy(y + r*nby + i0*es, x + r*nbx + i0*nb0, es); } } } -static void ggml_compute_forward_concat_i8( - const ggml_compute_params * params, - ggml_tensor * dst) { - - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - - GGML_ASSERT(ggml_type_size(src0->type) == sizeof(int8_t)); +// copy n_rows rows of n elements of src into dst, rows are nbx bytes apart in src and nby bytes apart in dst +static void ggml_concat_copy_rows(char * y, size_t nby, const ggml_tensor * src, const char * x, size_t nbx, int64_t n, int64_t n_rows) { + const size_t es = ggml_type_size(src->type); - const int ith = params->ith; - const int nth = params->nth; - - GGML_TENSOR_BINARY_OP_LOCALS - - const int32_t dim = ggml_get_op_params_i32(dst, 0); - - GGML_ASSERT(dim >= 0 && dim < 4); - - int64_t o[4] = {0, 0, 0, 0}; - o[dim] = src0->ne[dim]; - - const int8_t * x; - - // TODO: smarter multi-theading - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = ith; i2 < ne2; i2 += nth) { - for (int i1 = 0; i1 < ne1; i1++) { - for (int i0 = 0; i0 < ne0; i0++) { - if (i0 < ne00 && i1 < ne01 && i2 < ne02 && i3 < ne03) { - x = (const int8_t *) ((const char *)src0->data + (i0 )*nb00 + (i1 )*nb01 + (i2 )*nb02 + (i3 )*nb03); - } else { - x = (const int8_t *) ((const char *)src1->data + (i0 - o[0])*nb10 + (i1 - o[1])*nb11 + (i2 - o[2])*nb12 + (i3 - o[3])*nb13); - } - - int8_t * y = (int8_t *)((char *)dst->data + i0*nb0 + i1*nb1 + i2*nb2 + i3*nb3); - - *y = *x; - } - } + if (src->nb[0] == es) { + const size_t row_size = ggml_row_size(src->type, n); + for (int64_t r = 0; r < n_rows; r++) { + memcpy(y + r*nby, x + r*nbx, row_size); } + return; } -} -static void ggml_compute_forward_concat_f16( - const ggml_compute_params * params, - ggml_tensor * dst) { - - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - - GGML_ASSERT(ggml_type_size(src0->type) == sizeof(ggml_fp16_t)); - - const int ith = params->ith; - const int nth = params->nth; - - GGML_TENSOR_BINARY_OP_LOCALS - - const int32_t dim = ggml_get_op_params_i32(dst, 0); - - GGML_ASSERT(dim >= 0 && dim < 4); - - int64_t o[4] = {0, 0, 0, 0}; - o[dim] = src0->ne[dim]; - - const ggml_fp16_t * x; - - // TODO: smarter multi-theading - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = ith; i2 < ne2; i2 += nth) { - for (int i1 = 0; i1 < ne1; i1++) { - for (int i0 = 0; i0 < ne0; i0++) { - if (i0 < ne00 && i1 < ne01 && i2 < ne02 && i3 < ne03) { - x = (const ggml_fp16_t *) ((const char *)src0->data + (i0 )*nb00 + (i1 )*nb01 + (i2 )*nb02 + (i3 )*nb03); - } else { - x = (const ggml_fp16_t *) ((const char *)src1->data + (i0 - o[0])*nb10 + (i1 - o[1])*nb11 + (i2 - o[2])*nb12 + (i3 - o[3])*nb13); - } - - ggml_fp16_t * y = (ggml_fp16_t *)((char *)dst->data + i0*nb0 + i1*nb1 + i2*nb2 + i3*nb3); - - *y = *x; - } - } - } + switch (es) { + case 1: ggml_concat_copy_strided<1>(y, nby, x, nbx, src->nb[0], n, n_rows); break; + case 2: ggml_concat_copy_strided<2>(y, nby, x, nbx, src->nb[0], n, n_rows); break; + case 4: ggml_concat_copy_strided<4>(y, nby, x, nbx, src->nb[0], n, n_rows); break; + case 8: ggml_concat_copy_strided<8>(y, nby, x, nbx, src->nb[0], n, n_rows); break; + default: GGML_ABORT("unsupported element size"); } } -static void ggml_compute_forward_concat_f32( +// each dst row comes from src0 or src1, or for dim 0 from the row of src0 followed by the row of src1 +void ggml_compute_forward_concat( const ggml_compute_params * params, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; - GGML_ASSERT(ggml_type_size(src0->type) == sizeof(float)); - - const int ith = params->ith; - const int nth = params->nth; - GGML_TENSOR_BINARY_OP_LOCALS const int32_t dim = ggml_get_op_params_i32(dst, 0); GGML_ASSERT(dim >= 0 && dim < 4); + GGML_ASSERT(nb0 == ggml_type_size(dst->type)); + GGML_ASSERT(!ggml_is_quantized(dst->type) || (nb00 == nb0 && nb10 == nb0)); + GGML_ASSERT(dim != 0 || (ne00 % ggml_blck_size(dst->type) == 0 && ne10 % ggml_blck_size(dst->type) == 0)); - int64_t o[4] = {0, 0, 0, 0}; - o[dim] = src0->ne[dim]; + const size_t y1 = dim == 0 ? ggml_row_size(dst->type, ne00) : 0; - const float * x; + const int64_t nr = ne1*ne2*ne3; + const int64_t dr = (nr + params->nth - 1)/params->nth; - // TODO: smarter multi-theading - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = ith; i2 < ne2; i2 += nth) { - for (int i1 = 0; i1 < ne1; i1++) { - for (int i0 = 0; i0 < ne0; i0++) { - if (i0 < ne00 && i1 < ne01 && i2 < ne02 && i3 < ne03) { - x = (const float *) ((const char *)src0->data + (i0 )*nb00 + (i1 )*nb01 + (i2 )*nb02 + (i3 )*nb03); - } else { - x = (const float *) ((const char *)src1->data + (i0 - o[0])*nb10 + (i1 - o[1])*nb11 + (i2 - o[2])*nb12 + (i3 - o[3])*nb13); - } + const int64_t ir0 = dr*params->ith; + const int64_t ir1 = MIN(ir0 + dr, nr); - float * y = (float *)((char *)dst->data + i0*nb0 + i1*nb1 + i2*nb2 + i3*nb3); + for (int64_t ir = ir0; ir < ir1; ) { + int64_t i[4] = { 0, ir % ne1, (ir/ne1) % ne2, ir/(ne1*ne2) }; - *y = *x; - } - } + // a tile of consecutive rows sharing i2, i3 and their source + int64_t nt = MIN(MIN(ir1 - ir, ne1 - i[1]), GGML_CONCAT_TILE); + if (dim == 1 && i[1] < ne01) { + nt = MIN(nt, ne01 - i[1]); } - } -} -void ggml_compute_forward_concat( - const ggml_compute_params * params, - ggml_tensor * dst) { + char * y = (char *) dst->data + i[1]*nb1 + i[2]*nb2 + i[3]*nb3; - const ggml_tensor * src0 = dst->src[0]; + if (dim == 0 || i[dim] < src0->ne[dim]) { + ggml_concat_copy_rows(y, nb1, src0, (const char *) src0->data + i[1]*nb01 + i[2]*nb02 + i[3]*nb03, nb01, ne00, nt); + } - switch (src0->type) { - case GGML_TYPE_F16: - case GGML_TYPE_BF16: - case GGML_TYPE_I16: - { - ggml_compute_forward_concat_f16(params, dst); - } break; - case GGML_TYPE_I8: - { - ggml_compute_forward_concat_i8(params, dst); - } break; - case GGML_TYPE_F32: - case GGML_TYPE_I32: - { - ggml_compute_forward_concat_f32(params, dst); - } break; - default: - { - ggml_compute_forward_concat_any(params, dst); - } + if (dim == 0 || i[dim] >= src0->ne[dim]) { + i[dim] -= src0->ne[dim]; // i[0] does not address rows + ggml_concat_copy_rows(y + y1, nb1, src1, (const char *) src1->data + i[1]*nb11 + i[2]*nb12 + i[3]*nb13, nb11, ne10, nt); + } + + ir += nt; } } @@ -3550,6 +3454,73 @@ static void ggml_compute_forward_swiglu_oai_f32( } } +static void ggml_compute_forward_swiglu_oai_f16( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + char * src0_d = (char *) src0->data; + char * src1_d = (char *) (src1 ? src1->data : src0->data); + const size_t src0_o = src0->nb[1]; + const size_t src1_o = src1 ? src1->nb[1] : src0->nb[1]; + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(ggml_is_contiguous_1(dst)); + + if (src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src0->type == src1->type); + } + + const int ith = params->ith; + const int nth = params->nth; + + const int nc = src1 ? src0->ne[0] : src0->ne[0] / 2; + const int nr = ggml_nrows(src0); + + GGML_ASSERT(dst->ne[0] == nc); + GGML_ASSERT(ggml_nrows(dst) == nr); + + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + + // rows per thread + const int dr = (nr + nth - 1)/nth; + + // row range for this thread + const int ir0 = dr*ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int i1 = ir0; i1 < ir1; i1++) { + ggml_fp16_t * src0_p = (ggml_fp16_t *) (src0_d + i1*src0_o); + ggml_fp16_t * src1_p = (ggml_fp16_t *) (src1_d + i1*src1_o); + ggml_fp16_t * dst_p = (ggml_fp16_t *) ((char *) dst->data + i1*(dst->nb[1])); + + if (!src1) { + src0_p += swapped ? nc : 0; + src1_p += swapped ? 0 : nc; + } + + for (int k = 0; k < nc; k++) { + const float x = std::min(GGML_CPU_FP16_TO_FP32(src0_p[k]), limit); + const float y = std::clamp(GGML_CPU_FP16_TO_FP32(src1_p[k]), -limit, limit); + const float out_glu = x / (1.f + expf(alpha * (-x))); + dst_p[k] = GGML_CPU_FP32_TO_FP16(out_glu * (y + 1.f)); + } + +#ifndef NDEBUG + for (int k = 0; k < nc; k++) { + const float x = GGML_CPU_FP16_TO_FP32(dst_p[k]); + GGML_UNUSED(x); + assert(!isnan(x)); + assert(!isinf(x)); + } +#endif // NDEBUG + } +} + static void ggml_compute_forward_swiglu_oai( const ggml_compute_params * params, ggml_tensor * dst) { @@ -3561,6 +3532,10 @@ static void ggml_compute_forward_swiglu_oai( { ggml_compute_forward_swiglu_oai_f32(params, dst); } break; + case GGML_TYPE_F16: + { + ggml_compute_forward_swiglu_oai_f16(params, dst); + } break; default: { GGML_ABORT("fatal error"); @@ -4843,6 +4818,7 @@ void ggml_compute_forward_out_prod( case GGML_TYPE_Q8_0: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -4885,8 +4861,8 @@ static void ggml_compute_forward_scale_f32( const ggml_tensor * src0 = dst->src[0]; - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(dst)); + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + GGML_ASSERT(ggml_is_contiguous_rows(dst)); GGML_ASSERT(ggml_are_same_shape(src0, dst)); float s; // scale factor @@ -4901,6 +4877,8 @@ static void ggml_compute_forward_scale_f32( const int nc = src0->ne[0]; const int nr = ggml_nrows(src0); + GGML_TENSOR_UNARY_OP_LOCALS + // rows per thread const int dr = (nr + nth - 1)/nth; @@ -4908,25 +4886,23 @@ static void ggml_compute_forward_scale_f32( const int ir0 = dr*ith; const int ir1 = MIN(ir0 + dr, nr); - const size_t nb01 = src0->nb[1]; + for (int i = ir0; i < ir1; i++) { + const int64_t i1 = i % ne01; + const int64_t i2 = (i / ne01) % ne02; + const int64_t i3 = i / (ne01*ne02); - const size_t nb1 = dst->nb[1]; + float * y = (float *) ((char *) dst->data + i1*nb1 + i2*nb2 + i3*nb3); + const float * x = (const float *) ((char *) src0->data + i1*nb01 + i2*nb02 + i3*nb03); - if (b == 0.0f) { - for (int i1 = ir0; i1 < ir1; i1++) { + if (b == 0.0f) { if (dst->data != src0->data) { // src0 is same shape as dst => same indices // TODO: add x parameter to ggml_vec_scale_f32 and remove this memcpy - memcpy((char *)dst->data + i1*nb1, (char *)src0->data + i1*nb01, nc * sizeof(float)); + memcpy(y, x, nc * sizeof(float)); } - ggml_vec_scale_f32(nc, (float *) ((char *) dst->data + i1*nb1), s); - } - } else { - for (int i1 = ir0; i1 < ir1; i1++) { - ggml_vec_mad1_f32(nc, - (float *) ((char *) dst->data + i1*nb1), - (float *) ((char *) src0->data + i1*nb1), - s, b); + ggml_vec_scale_f32(nc, y, s); + } else { + ggml_vec_mad1_f32(nc, y, x, s, b); } } } @@ -4937,8 +4913,8 @@ static void ggml_compute_forward_scale_bf16( const ggml_tensor * src0 = dst->src[0]; - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(dst)); + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + GGML_ASSERT(ggml_is_contiguous_rows(dst)); GGML_ASSERT(ggml_are_same_shape(src0, dst)); float s; // scale factor @@ -4953,6 +4929,8 @@ static void ggml_compute_forward_scale_bf16( const int nc = src0->ne[0]; const int nr = ggml_nrows(src0); + GGML_TENSOR_UNARY_OP_LOCALS + // rows per thread const int dr = (nr + nth - 1)/nth; @@ -4960,9 +4938,13 @@ static void ggml_compute_forward_scale_bf16( const int ir0 = dr*ith; const int ir1 = MIN(ir0 + dr, nr); - for (int i1 = ir0; i1 < ir1; i1++) { - const ggml_bf16_t * x = (const ggml_bf16_t *) ((const char *) src0->data + i1*src0->nb[1]); - ggml_bf16_t * y = (ggml_bf16_t *) ((char *) dst->data + i1*dst->nb[1]); + for (int i = ir0; i < ir1; i++) { + const int64_t i1 = i % ne01; + const int64_t i2 = (i / ne01) % ne02; + const int64_t i3 = i / (ne01*ne02); + + const ggml_bf16_t * x = (const ggml_bf16_t *) ((const char *) src0->data + i1*nb01 + i2*nb02 + i3*nb03); + ggml_bf16_t * y = (ggml_bf16_t *) ((char *) dst->data + i1*nb1 + i2*nb2 + i3*nb3); for (int k = 0; k < nc; k++) { y[k] = GGML_FP32_TO_BF16(s*GGML_BF16_TO_FP32(x[k]) + b); } @@ -5162,6 +5144,7 @@ void ggml_compute_forward_set( case GGML_TYPE_Q8_1: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q4_0_ROCMFP4: case GGML_TYPE_Q4_0_ROCMFP4_FAST: case GGML_TYPE_Q2_K: @@ -5389,6 +5372,7 @@ void ggml_compute_forward_get_rows( case GGML_TYPE_Q8_1: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q4_0_ROCMFP4: case GGML_TYPE_Q4_0_ROCMFP4_FAST: case GGML_TYPE_Q2_K: @@ -6151,6 +6135,7 @@ void ggml_compute_forward_clamp( case GGML_TYPE_Q8_1: case GGML_TYPE_MXFP4: case GGML_TYPE_NVFP4: + case GGML_TYPE_F8_E4M3: case GGML_TYPE_Q4_0_ROCMFP4: case GGML_TYPE_Q4_0_ROCMFP4_FAST: case GGML_TYPE_Q2_K: @@ -8452,40 +8437,47 @@ static void ggml_compute_forward_pad_f32( const int32_t lp3 = ggml_get_op_params_i32(dst, 6); const int32_t rp3 = ggml_get_op_params_i32(dst, 7); - // TODO: optimize + const int64_t nrows = ne1 * ne2 * ne3; + const bool src_row_contig = src0->nb[0] == sizeof(float); + + for (int64_t row = ith; row < nrows; row += nth) { + const int64_t i1 = row % ne1; + const int64_t i2 = (row / ne1) % ne2; + const int64_t i3 = row / (ne1 * ne2); + + float * dst_row = dst_ptr + row * ne0; + + if constexpr (circular_t) { + // circular padding wraps around on a torus + const int64_t src_i1 = ggml_wrap_around(i1 - lp1, ne01); + const int64_t src_i2 = ggml_wrap_around(i2 - lp2, ne02); + const int64_t src_i3 = ggml_wrap_around(i3 - lp3, ne03); - for (int64_t i2 = 0; i2 < ne2; ++i2) { - for (int64_t i1 = ith; i1 < ne1; i1 += nth) { for (int64_t i0 = 0; i0 < ne0; ++i0) { - for (int64_t i3 = 0; i3 < ne3; ++i3) { - // circular means wrap around on a torus, so x and y loop around - if constexpr (circular_t) { - const int64_t dst_idx = i3*(ne0*ne1*ne2) + i2*(ne0*ne1) + i1*ne0 + i0; - const int64_t src_i0 = ggml_wrap_around(i0 - lp0, ne00); - const int64_t src_i1 = ggml_wrap_around(i1 - lp1, ne01); - const int64_t src_i2 = ggml_wrap_around(i2 - lp2, ne02); - const int64_t src_i3 = ggml_wrap_around(i3 - lp3, ne03); - - const int64_t src_idx = - src_i3*nb03 + - src_i2*nb02 + - src_i1*nb01 + - src_i0*nb00; - - const float * src_ptr = (const float *)((char *) src0->data + src_idx); - dst_ptr[dst_idx] = *src_ptr; + const int64_t src_i0 = ggml_wrap_around(i0 - lp0, ne00); + dst_row[i0] = *(const float *)((const char *) src0->data + src_i3*nb03 + src_i2*nb02 + src_i1*nb01 + src_i0*nb00); + } + } else { + const bool interior = (i1 >= lp1 && i1 < ne1 - rp1) + && (i2 >= lp2 && i2 < ne2 - rp2) + && (i3 >= lp3 && i3 < ne3 - rp3); + if (!interior) { + memset(dst_row, 0, ne0 * sizeof(float)); + continue; + } + + const char * src_row = (const char *) src0->data + (i3 - lp3)*nb03 + (i2 - lp2)*nb02 + (i1 - lp1)*nb01; + + if (src_row_contig && lp0 >= 0 && rp0 >= 0) { + memset(dst_row, 0, lp0 * sizeof(float)); + memcpy(dst_row + lp0, src_row, ne00 * sizeof(float)); + memset(dst_row + lp0 + ne00, 0, rp0 * sizeof(float)); + } else { + for (int64_t i0 = 0; i0 < ne0; ++i0) { + if (i0 >= lp0 && i0 < ne0 - rp0) { + dst_row[i0] = *(const float *)(src_row + (i0 - lp0)*nb00); } else { - const int64_t dst_idx = i3*(ne0*ne1*ne2) + i2*(ne0*ne1) + i1*ne0 + i0; - if ((i0 >= lp0 && i0 < ne0 - rp0) \ - && (i1 >= lp1 && i1 < ne1 - rp1) \ - && (i2 >= lp2 && i2 < ne2 - rp2) \ - && (i3 >= lp3 && i3 < ne3 - rp3)) { - const int64_t src_idx = (i3 - lp3)*nb03 + (i2 - lp2)*nb02 + (i1 - lp1)*nb01 + (i0 - lp0)*nb00; - const float * src_ptr = (const float *)((char *) src0->data + src_idx); - dst_ptr[dst_idx] = *src_ptr; - } else { - dst_ptr[dst_idx] = 0; - } + dst_row[i0] = 0.0f; } } } @@ -8860,6 +8852,7 @@ static void ggml_compute_forward_flash_attn_ext_f16_one_chunk( const ggml_tensor * v = dst->src[2]; const ggml_tensor * mask = dst->src[3]; const ggml_tensor * sinks = dst->src[4]; + const ggml_tensor * kv_rows = dst->src[5]; GGML_TENSOR_LOCALS(int64_t, neq, q, ne) GGML_TENSOR_LOCALS(size_t, nbq, q, nb) @@ -8967,6 +8960,8 @@ static void ggml_compute_forward_flash_attn_ext_f16_one_chunk( const float * pq = (const float *) ((char *) q->data + (iq1*nbq1 + iq2*nbq2 + iq3*nbq3)); q_to_vec_dot(pq, Q_q, DK); + const int32_t * rows = kv_rows ? (const int32_t *) ((const char *) kv_rows->data + iq3*kv_rows->nb[1]) : nullptr; + // online softmax / attention // loop over n_kv and n_head_kv // ref: https://arxiv.org/pdf/2112.05682.pdf @@ -8977,9 +8972,14 @@ static void ggml_compute_forward_flash_attn_ext_f16_one_chunk( continue; } + const int64_t ik1 = rows ? rows[ic] : ic; + if (ik1 < 0) { + continue; + } + float s; // KQ value - const char * k_data = (const char *) k->data + ( ic*nbk1 + ik2*nbk2 + ik3*nbk3); + const char * k_data = (const char *) k->data + (ik1*nbk1 + ik2*nbk2 + ik3*nbk3); kq_vec_dot(DK, &s, 0, k_data, 0, Q_q, 0, 1); s = s*scale; // scale KQ value @@ -8995,7 +8995,7 @@ static void ggml_compute_forward_flash_attn_ext_f16_one_chunk( float ms = 1.0f; // upon new higher max val, scale VKQ and KQ sum with this value float vs = 1.0f; // post-softmax KQ value, expf(s - M) - const char * v_data = ((const char *) v->data + (ic*nbv1 + iv2*nbv2 + iv3*nbv3)); + const char * v_data = ((const char *) v->data + (ik1*nbv1 + iv2*nbv2 + iv3*nbv3)); if (v->type == GGML_TYPE_F16) { if (s > M) { @@ -9162,6 +9162,10 @@ static void ggml_compute_forward_flash_attn_ext_tiled( static constexpr int Q_TILE_SZ = ggml_fa_tile_config::Q; static constexpr int KV_TILE_SZ = ggml_fa_tile_config::KV; + // with kv_rows the loop runs over the mask columns and reads K/V rows through kv_rows + const ggml_tensor * kv_rows = dst->src[5]; + const int64_t n_kv_cols = kv_rows ? kv_rows->ne[0] : nek1; + int ir = ir0; while (ir < ir1) { // q indices for the start of this tile @@ -9169,6 +9173,10 @@ static void ggml_compute_forward_flash_attn_ext_tiled( const int iq2 = (ir - iq3*neq2*neq1)/neq1; const int iq1 = (ir - iq3*neq2*neq1 - iq2*neq1); + // padding rows are masked, read row 0 for them + const int32_t * rows = kv_rows ? (const int32_t *) ((const char *) kv_rows->data + iq3*kv_rows->nb[1]) : nullptr; + auto kv_row = [rows](int64_t i) -> int64_t { return rows ? std::max(rows[i], 0) : i; }; + // Number of valid rows in this tile: // - limited by tile size (Q_TILE_SZ) // - limited by chunk boundary (ir1 - ir) @@ -9228,8 +9236,8 @@ static void ggml_compute_forward_flash_attn_ext_tiled( memset(K_f32, 0, DK * KV_TILE_SZ * sizeof(float)); memset(V32, 0, KV_TILE_SZ * DV * sizeof(float)); - for (int64_t ic = 0; ic < nek1; ic += KV_TILE_SZ) { - const int kv_tile = (int)std::min((int64_t)KV_TILE_SZ, nek1 - ic); + for (int64_t ic = 0; ic < n_kv_cols; ic += KV_TILE_SZ) { + const int kv_tile = (int)std::min((int64_t)KV_TILE_SZ, n_kv_cols - ic); // skip the tile entirely if all the masks are -inf if (mask) { @@ -9256,7 +9264,7 @@ static void ggml_compute_forward_flash_attn_ext_tiled( // Pack K tile transposed: K_f32[dk][kv] so KV_TILE is contiguous (SIMD dim) // Zero-pad the last tile so the GEMM always operates on KV_TILE_SZ columns for (int tk = 0; tk < kv_tile; tk++) { - const char * k_data = (const char *)k->data + (ic + tk)*nbk1 + ik2*nbk2 + ik3*nbk3; + const char * k_data = (const char *)k->data + kv_row(ic + tk)*nbk1 + ik2*nbk2 + ik3*nbk3; if (kv_type == GGML_TYPE_F16) { const ggml_fp16_t * k_f16 = (const ggml_fp16_t *)k_data; for (int64_t dk = 0; dk < DK; dk++) { @@ -9321,7 +9329,7 @@ static void ggml_compute_forward_flash_attn_ext_tiled( // V accumulation: VKQ32 += softmax(KQ) * V // Pack V tile to contiguous F32, zero-padded for (int tk = 0; tk < kv_tile; tk++) { - const char * v_data = (const char *)v->data + (ic + tk)*nbv1 + iv2*nbv2 + iv3*nbv3; + const char * v_data = (const char *)v->data + kv_row(ic + tk)*nbv1 + iv2*nbv2 + iv3*nbv3; if (kv_type == GGML_TYPE_F16) { ggml_cpu_fp16_to_fp32((const ggml_fp16_t *)v_data, V32 + tk * DV, DV); } else { @@ -9493,8 +9501,12 @@ static void ggml_compute_forward_flash_attn_ext_f16( // When use_ref is set, force the vec-only reference implementation (no tiling, no KV-chunking) const bool use_ref = params->use_ref; + // with kv_rows the loops run over the mask columns, the split KV path does not support it + const ggml_tensor * kv_rows = dst->src[5]; + const int64_t n_kv_cols = kv_rows ? kv_rows->ne[0] : nek1; + const bool kv_is_f32_or_f16 = (k->type == GGML_TYPE_F32 || k->type == GGML_TYPE_F16); - const bool use_split_kv_path = !use_ref && (neq1 == 1 && neq3 == 1) && kv_is_f32_or_f16 && (k->type == v->type) && q->type == GGML_TYPE_F32 && nek1 >= 512; + const bool use_split_kv_path = !use_ref && !kv_rows && (neq1 == 1 && neq3 == 1) && kv_is_f32_or_f16 && (k->type == v->type) && q->type == GGML_TYPE_F32 && nek1 >= 512; if (use_split_kv_path) { const int64_t chunk_size = (nek1 + nth - 1) / nth; @@ -9573,7 +9585,7 @@ static void ggml_compute_forward_flash_attn_ext_f16( if (use_tiled) { ggml_compute_forward_flash_attn_ext_tiled(params, dst, ir0, ir1); } else { - ggml_compute_forward_flash_attn_ext_f16_one_chunk(params, dst, ir0, ir1, 0, nek1, nullptr, 0); + ggml_compute_forward_flash_attn_ext_f16_one_chunk(params, dst, ir0, ir1, 0, n_kv_cols, nullptr, 0); } current_chunk = ggml_threadpool_chunk_add(params->threadpool, 1); @@ -11663,6 +11675,92 @@ void ggml_compute_forward_dsv4_hc_post( } } +// ggml_compute_forward_top_k_mask + +void ggml_compute_forward_top_k_mask( + const ggml_compute_params * params, + ggml_tensor * dst) { + const ggml_tensor * mask = dst->src[0]; + const ggml_tensor * top_k = dst->src[1]; + const ggml_tensor * score = dst->src[2]; + const ggml_tensor * blocks = dst->src[3]; + const ggml_tensor * extra = dst->src[4]; + + GGML_ASSERT(dst->type == mask->type); + GGML_ASSERT(dst->nb[0] == ggml_type_size(dst->type)); + + const int64_t n_kv = mask->ne[0]; + const int64_t ne1 = dst->ne[1]; + const int64_t ne2 = dst->ne[2]; + const int64_t n_rows = ggml_nrows(dst); + const int64_t n_top = top_k->ne[0]; + const int64_t n_blk = blocks ? blocks->ne[0] : 1; + const int64_t n_pick = blocks ? blocks->ne[1] : score ? score->ne[0] : n_kv; + const int64_t n_extra = extra ? extra->ne[0] : 0; + + const size_t ts = ggml_type_size(dst->type); + + const int ith = params->ith; + const int nth = params->nth; + + for (int64_t ir = ith; ir < n_rows; ir += nth) { + const int64_t i1 = ir % ne1; + const int64_t i2 = (ir / ne1) % ne2; + const int64_t i3 = ir / (ne1*ne2); + + const char * mask_row = (const char *) mask->data + + (i1 % mask->ne[1])*mask->nb[1] + (i2 % mask->ne[2])*mask->nb[2] + (i3 % mask->ne[3])*mask->nb[3]; + char * dst_row = (char *) dst->data + i1*dst->nb[1] + i2*dst->nb[2] + i3*dst->nb[3]; + + if (dst->type == GGML_TYPE_F16) { + const ggml_fp16_t ninf = GGML_CPU_FP32_TO_FP16(-INFINITY); + for (int64_t c = 0; c < n_kv; ++c) { + ((ggml_fp16_t *) dst_row)[c] = ninf; + } + } else { + for (int64_t c = 0; c < n_kv; ++c) { + ((float *) dst_row)[c] = -INFINITY; + } + } + + auto keep = [&](int32_t c) { + if (c >= 0 && c < n_kv) { + memcpy(dst_row + c*ts, mask_row + c*ts, ts); + } + }; + + const char * top_k_row = (const char *) top_k->data + i1*top_k->nb[1] + i2*top_k->nb[2] + i3*top_k->nb[3]; + + for (int64_t j = 0; j < n_top; ++j) { + const int32_t p = *(const int32_t *) (top_k_row + j*top_k->nb[0]); + if (p < 0 || p >= n_pick) { + continue; + } + if (score) { + const float s = *(const float *) ((const char *) score->data + + p*score->nb[0] + i1*score->nb[1] + i2*score->nb[2] + i3*score->nb[3]); + if (!(s > -INFINITY)) { + continue; + } + } + if (!blocks) { + keep(p); + continue; + } + for (int64_t k = 0; k < n_blk; ++k) { + keep(*(const int32_t *) ((const char *) blocks->data + k*blocks->nb[0] + p*blocks->nb[1])); + } + } + + if (extra) { + const char * extra_row = (const char *) extra->data + i1*extra->nb[1] + i2*extra->nb[2] + i3*extra->nb[3]; + for (int64_t j = 0; j < n_extra; ++j) { + keep(*(const int32_t *) (extra_row + j*extra->nb[0])); + } + } + } +} + // ggml_compute_forward_rwkv_wkv7 static void ggml_compute_forward_rwkv_wkv7_f32( diff --git a/ggml/src/ggml-cpu/ops.h b/ggml/src/ggml-cpu/ops.h index 2728b08b6c97..00a2ea7dc2de 100644 --- a/ggml/src/ggml-cpu/ops.h +++ b/ggml/src/ggml-cpu/ops.h @@ -108,6 +108,7 @@ void ggml_compute_forward_lightning_indexer(const struct ggml_compute_params * p void ggml_compute_forward_dsv4_hc_comb(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_dsv4_hc_pre(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_dsv4_hc_post(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_top_k_mask(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom1(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom2(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom3(const struct ggml_compute_params * params, struct ggml_tensor * dst); diff --git a/ggml/src/ggml-cpu/quants.c b/ggml/src/ggml-cpu/quants.c index 8ce16c03f930..8e2d5b35fffc 100644 --- a/ggml/src/ggml-cpu/quants.c +++ b/ggml/src/ggml-cpu/quants.c @@ -3,6 +3,7 @@ #include "ggml-cpu-impl.h" #include "simd-mappings.h" +#include "vec.h" #include "ggml-quants.h" #include "quants.h" @@ -70,6 +71,10 @@ void rocmfp4_quantize_row_q4_0_fast(const float * GGML_RESTRICT x, void * GGML_R rocmfp4_quantize_row_q4_0_fast_ref(x, (block_rocmfp4_fast *) y, k); } +void quantize_row_f8_e4m3(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k) { + quantize_row_f8_e4m3_ref(x, y, k); +} + // // 2-6 bit quantization in super-blocks // @@ -435,6 +440,49 @@ void rocmfp4_vec_dot_q4_0_fast_q8_0(int n, float * GGML_RESTRICT s, size_t bs, c *s = sumf; } +void ggml_vec_dot_f8_e4m3_f32(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + + const ggml_fp8_e4m3_t * GGML_RESTRICT x = vx; + const float * GGML_RESTRICT y = vy; + + float sumf = 0.0f; + int pos = 0; +#if defined(GGML_SIMD) && !defined(__ARM_FEATURE_SVE) && !defined(__riscv_v_intrinsic) + GGML_F32_VEC sum[GGML_F32_ARR] = { GGML_F32_VEC_ZERO }; + const int np = n - n % GGML_F32_STEP; + for (; pos < np; pos += GGML_F32_STEP) { + for (int j = 0; j < GGML_F32_ARR; ++j) { + const int offset = pos + j*GGML_F32_EPR; + GGML_F32_VEC ax; +#if defined(__AVX512F__) && defined(__AVX512BW__) + const __m128i codes = _mm_loadu_si128((const __m128i *) (x + offset)); + ax = _mm512_i32gather_ps(_mm512_cvtepu8_epi32(codes), ggml_table_f32_f8_e4m3, sizeof(float)); +#elif defined(__AVX2__) && !defined(__AVX512F__) + const __m128i codes = _mm_loadl_epi64((const __m128i *) (x + offset)); + ax = _mm256_i32gather_ps(ggml_table_f32_f8_e4m3, _mm256_cvtepu8_epi32(codes), sizeof(float)); +#else + float values[GGML_F32_EPR]; + for (int k = 0; k < GGML_F32_EPR; ++k) { + values[k] = ggml_table_f32_f8_e4m3[x[offset + k].bits]; + } + ax = GGML_F32_VEC_LOAD(values); +#endif + sum[j] = GGML_F32_VEC_FMA(sum[j], ax, GGML_F32_VEC_LOAD(y + offset)); + } + } + GGML_F32_VEC_REDUCE(sumf, sum); +#endif + for (; pos < n; ++pos) { + sumf += ggml_table_f32_f8_e4m3[x[pos].bits] * y[pos]; + } + *s = sumf; +} + void ggml_vec_dot_q5_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { const int qk = QK8_0; const int nb = n / qk; diff --git a/ggml/src/ggml-cpu/quants.h b/ggml/src/ggml-cpu/quants.h index c89f9f69b8ab..f60ebd95656f 100644 --- a/ggml/src/ggml-cpu/quants.h +++ b/ggml/src/ggml-cpu/quants.h @@ -23,6 +23,7 @@ void quantize_row_q8_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, in void quantize_row_mxfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_nvfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); +void quantize_row_f8_e4m3(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); // CPU from_float wrappers; defined in ggml-cpu/quants.c over the _ref quantizers in ggml-quants.c. GGML_API void rocmfp4_quantize_row_q4_0 (const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); @@ -44,6 +45,7 @@ void quantize_row_iq4_xs (const float * GGML_RESTRICT x, void * GGML_RESTRICT y, // Dot product void ggml_vec_dot_q1_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q2_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); +void ggml_vec_dot_f8_e4m3_f32(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); diff --git a/ggml/src/ggml-cpu/repack.cpp b/ggml/src/ggml-cpu/repack.cpp index 2632ae3a063c..9282ca299b60 100644 --- a/ggml/src/ggml-cpu/repack.cpp +++ b/ggml/src/ggml-cpu/repack.cpp @@ -4855,7 +4855,12 @@ template data + iid1 * ids->nb[1] + id * ids->nb[0]); - GGML_ASSERT(i02 >= 0 && i02 < n_as); + GGML_ASSERT(i02 == -1 || (i02 >= 0 && i02 < n_as)); + + if (i02 == -1) { + memset((char *) dst->data + id*nb1 + iid1*nb2, 0, ne0*sizeof(float)); + continue; + } MMID_MATRIX_ROW(i02, matrix_row_counts[i02]) = { id, iid1 }; matrix_row_counts[i02] += 1; diff --git a/ggml/src/ggml-cpu/simd-mappings.h b/ggml/src/ggml-cpu/simd-mappings.h index ebb54a4ab8b6..7b86e8ad9a79 100644 --- a/ggml/src/ggml-cpu/simd-mappings.h +++ b/ggml/src/ggml-cpu/simd-mappings.h @@ -42,6 +42,7 @@ extern "C" { #define GGML_CPU_COMPUTE_FP32_TO_FP16(x) neon_compute_fp32_to_fp16(x) #define GGML_CPU_FP16_TO_FP32(x) GGML_CPU_COMPUTE_FP16_TO_FP32(x) + #define GGML_CPU_FP32_TO_FP16(x) GGML_CPU_COMPUTE_FP32_TO_FP16(x) static inline float neon_compute_fp16_to_fp32(ggml_fp16_t h) { __fp16 tmp; @@ -126,6 +127,8 @@ extern float ggml_table_f32_e8m0_half[1 << 8]; // defined in ggml-cpu.c, initialized in ggml_cpu_init() extern float ggml_table_f32_ue4m3[1 << 8]; +extern float ggml_table_f32_f8_e4m3[1 << 8]; + // Use lookup table for E8M0 on x86 (faster than bit manipulation) #if defined(__AVX__) || defined(__AVX2__) || defined(__AVX512F__) #define GGML_CPU_E8M0_TO_FP32_HALF(x) ggml_table_f32_e8m0_half[(uint8_t)(x)] @@ -150,9 +153,15 @@ extern float ggml_table_f32_ue4m3[1 << 8]; #define GGML_CPU_FP32_TO_FP16(x) GGML_CPU_COMPUTE_FP32_TO_FP16(x) #endif -// On ARM NEON, it's quicker to directly convert x -> x instead of calling into ggml_lookup_fp16_to_fp32, -// so we define GGML_CPU_FP16_TO_FP32 and GGML_CPU_FP32_TO_FP16 elsewhere for NEON. -// This is also true for POWER9. +// a branch that defines a GGML_CPU_COMPUTE_* macro must also select it, or the fallback takes over silently +#if defined(GGML_CPU_COMPUTE_FP16_TO_FP32) && !defined(GGML_CPU_FP16_TO_FP32) && !defined(__F16C__) // see: https://github.com/ggml-org/llama.cpp/issues/30342 +#error "a branch defined GGML_CPU_COMPUTE_FP16_TO_FP32 without selecting it as GGML_CPU_FP16_TO_FP32" +#endif +#if defined(GGML_CPU_COMPUTE_FP32_TO_FP16) && !defined(GGML_CPU_FP32_TO_FP16) +#error "a branch defined GGML_CPU_COMPUTE_FP32_TO_FP16 without selecting it as GGML_CPU_FP32_TO_FP16" +#endif + +// fall back to the lookup table / the portable software conversion for whichever direction no branch selected #if !defined(GGML_CPU_FP16_TO_FP32) inline static float ggml_lookup_fp16_to_fp32(ggml_fp16_t f) { uint16_t s; diff --git a/ggml/src/ggml-cpu/spacemit/ime.cpp b/ggml/src/ggml-cpu/spacemit/ime.cpp index 81e86b9dd666..5f114f587a49 100644 --- a/ggml/src/ggml-cpu/spacemit/ime.cpp +++ b/ggml/src/ggml-cpu/spacemit/ime.cpp @@ -682,7 +682,12 @@ template class tensor_ const int32_t i02 = *(const int32_t *) ((const char *) ids->data + iid1 * ids->nb[1] + id * ids->nb[0]); - GGML_ASSERT(i02 >= 0 && i02 < n_as); + GGML_ASSERT(i02 == -1 || (i02 >= 0 && i02 < n_as)); + + if (i02 == -1) { + memset((char *) dst->data + id * nb1 + iid1 * nb2, 0, ne0 * sizeof(float)); + continue; + } MMID_MATRIX_ROW(i02, matrix_row_counts[i02]) = { id, iid1 }; matrix_row_counts[i02] += 1; @@ -1041,6 +1046,10 @@ class tensor_traits_common : public tensor_traits_base { return true; } case GGML_OP_FLASH_ATTN_EXT: + // K/V row lists are handled by the generic CPU path + if (op->src[5] != nullptr) { + return false; + } forward_flash_attn_ext_f16(params, op); return true; case GGML_OP_CONT: @@ -1484,6 +1493,9 @@ static const ggml_backend_buffer_i ggml_backend_riscv64_spacemit_buffer_i = { /* .cpy_tensor = */ nullptr, /* .clear = */ ggml_backend_riscv64_spacemit_buffer_clear, /* .reset = */ nullptr, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; static const char * ggml_backend_cpu_riscv64_spacemit_buffer_type_get_name(ggml_backend_buffer_type_t buft) { diff --git a/ggml/src/ggml-cpu/tiled/tiled-kernel.cpp b/ggml/src/ggml-cpu/tiled/tiled-kernel.cpp index bffa737c7cd4..5819ac07ca31 100644 --- a/ggml/src/ggml-cpu/tiled/tiled-kernel.cpp +++ b/ggml/src/ggml-cpu/tiled/tiled-kernel.cpp @@ -244,16 +244,6 @@ static void tiled_run_microtile_avx2(const tiled_tile_src0 & src0, const tiled_t const int bs_stride = (nkr == 1) ? TILED_TILE_ROWS : TILED_MICRO; const int bs_off = seff * TILED_MICRO; - // Horizontal sum helper: converts 8x32-bit int lane inside a YMM register to scalar int32 - auto hsum256_epi32 = [](const __m256i v) -> int32_t { - __m128i low = _mm256_castsi256_si128(v); - __m128i high = _mm256_extracti128_si256(v, 1); - __m128i sum128 = _mm_add_epi32(low, high); - sum128 = _mm_add_epi32(sum128, _mm_shuffle_epi32(sum128, _MM_SHUFFLE(2, 3, 0, 1))); - sum128 = _mm_add_epi32(sum128, _mm_shuffle_epi32(sum128, _MM_SHUFFLE(1, 0, 3, 2))); - return _mm_cvtsi128_si32(sum128); - }; - for (int i = 0; i < TILED_MICRO; i++) { const int ar = i0 + i; const int d_off = seff * TILED_MICRO + ar; @@ -362,15 +352,20 @@ static void tiled_run_microtile_avx2(const tiled_tile_src0 & src0, const tiled_t } } - // OPTIMIZATION 2: Vectorized Epilogue with FMA3 gating - // Reduce accumulators into a 256-bit vector across 8 columns - alignas(32) int32_t s1_vals[GROUP]; - #pragma GCC unroll 8 - for (int t = 0; t < GROUP; t++) { - s1_vals[t] = hsum256_epi32(acc[t]); - } - __m256i s1_vec = _mm256_load_si256((const __m256i *) s1_vals); + // Reduce the eight accumulators to column sums in acc[0]..acc[7] order, with additions modulo 2^32. + const __m256i ab = _mm256_hadd_epi32(acc[0], acc[1]); + const __m256i cd = _mm256_hadd_epi32(acc[2], acc[3]); + const __m256i ef = _mm256_hadd_epi32(acc[4], acc[5]); + const __m256i gh = _mm256_hadd_epi32(acc[6], acc[7]); + + // Each 128-bit half now holds four column sums over input lanes 0..3 or 4..7. + const __m256i abcd = _mm256_hadd_epi32(ab, cd); + const __m256i efgh = _mm256_hadd_epi32(ef, gh); + const __m256i lo = _mm256_permute2x128_si256(abcd, efgh, 0x20); + const __m256i hi = _mm256_permute2x128_si256(abcd, efgh, 0x31); + __m256i s1_vec = _mm256_add_epi32(lo, hi); + // OPTIMIZATION 2: Vectorized Epilogue with FMA3 gating if constexpr (BIAS != 0 && ACTBIAS) { // act-bias correction: raw = desired + 128*sum_s scales[s]*w_bsum[s]; corr precomputed in repack_src0 s1_vec = _mm256_sub_epi32(s1_vec, _mm256_set1_epi32(mins_row[0])); diff --git a/ggml/src/ggml-cpu/unary-ops.cpp b/ggml/src/ggml-cpu/unary-ops.cpp index 1d8344436f02..f5d57d6f941a 100644 --- a/ggml/src/ggml-cpu/unary-ops.cpp +++ b/ggml/src/ggml-cpu/unary-ops.cpp @@ -78,7 +78,7 @@ static inline float op_expm1(float x) { } static inline float op_softplus(float x) { - return (x > 20.0f) ? x : logf(1.0f + expf(x)); + return (x > 20.0f) ? x : log1pf(expf(x)); } static inline float op_floor(float x) { diff --git a/ggml/src/ggml-cpu/vec.cpp b/ggml/src/ggml-cpu/vec.cpp index 3918a6f4d9d2..8f0bf4999cfb 100644 --- a/ggml/src/ggml-cpu/vec.cpp +++ b/ggml/src/ggml-cpu/vec.cpp @@ -401,6 +401,10 @@ void ggml_vec_silu_f32(const int n, float * y, const float * x) { for (; i + 3 < n; i += 4) { vst1q_f32(y + i, ggml_v_silu(vld1q_f32(x + i))); } +#elif defined(__VXE__) || defined(__VXE2__) + for (; i + 3 < n; i += 4) { + vec_xst(ggml_v_silu(vec_xl(0, x + i)), 0, y + i); + } #elif defined(__riscv_v_intrinsic) for (int vl; i < n; i += vl) { vl = __riscv_vsetvl_e32m2(n - i); @@ -438,6 +442,10 @@ void ggml_vec_swiglu_f32(const int n, float * y, const float * x, const float * for (; i + 3 < n; i += 4) { vst1q_f32(y + i, vmulq_f32(ggml_v_silu(vld1q_f32(x + i)), vld1q_f32(g + i))); } +#elif defined(__VXE__) || defined(__VXE2__) + for (; i + 3 < n; i += 4) { + vec_xst(vec_mul(ggml_v_silu(vec_xl(0, x + i)), vec_xl(0, g + i)), 0, y + i); + } #elif defined(__riscv_v_intrinsic) for (int vl; i < n; i += vl) { vl = __riscv_vsetvl_e32m2(n - i); @@ -452,6 +460,92 @@ void ggml_vec_swiglu_f32(const int n, float * y, const float * x, const float * } } +#ifndef GGML_GELU_QUICK_FP16 +// computed in f32 without the fp16 table, which loses precision on f32 input +void ggml_vec_gelu_quick_f32(const int n, float * y, const float * x) { + int i = 0; +#if defined(__AVX512F__) && defined(__AVX512DQ__) + for (; i + 15 < n; i += 16) { + _mm512_storeu_ps(y + i, ggml_v_gelu_quick(_mm512_loadu_ps(x + i))); + } +#elif defined(__AVX2__) && defined(__FMA__) + for (; i + 7 < n; i += 8) { + _mm256_storeu_ps(y + i, ggml_v_gelu_quick(_mm256_loadu_ps(x + i))); + } +#elif defined(__SSE2__) + for (; i + 3 < n; i += 4) { + _mm_storeu_ps(y + i, ggml_v_gelu_quick(_mm_loadu_ps(x + i))); + } +#elif defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + const int vlen = svcntw(); + for (; i < n; i += vlen) { + const svbool_t pg = svwhilelt_b32_s32(i, n); + svst1_f32(pg, y + i, ggml_v_gelu_quick(pg, svld1_f32(pg, x + i))); + } +#elif defined(__ARM_NEON) && defined(__aarch64__) + for (; i + 3 < n; i += 4) { + vst1q_f32(y + i, ggml_v_gelu_quick(vld1q_f32(x + i))); + } +#elif defined(__VXE__) || defined(__VXE2__) + for (; i + 3 < n; i += 4) { + vec_xst(ggml_v_gelu_quick(vec_xl(0, x + i)), 0, y + i); + } +#elif defined(__riscv_v_intrinsic) + for (int vl; i < n; i += vl) { + vl = __riscv_vsetvl_e32m2(n - i); + vfloat32m2_t vx = __riscv_vle32_v_f32m2(&x[i], vl); + vfloat32m2_t vy = ggml_v_gelu_quick_m2(vx, vl); + __riscv_vse32_v_f32m2(&y[i], vy, vl); + } +#endif + for (; i < n; ++i) { + y[i] = ggml_gelu_quick_f32(x[i]); + } +} + +void ggml_vec_geglu_quick_f32(const int n, float * y, const float * x, const float * g) { + int i = 0; +#if defined(__AVX512F__) && defined(__AVX512DQ__) + for (; i + 15 < n; i += 16) { + _mm512_storeu_ps(y + i, _mm512_mul_ps(ggml_v_gelu_quick(_mm512_loadu_ps(x + i)), _mm512_loadu_ps(g + i))); + } +#elif defined(__AVX2__) && defined(__FMA__) + for (; i + 7 < n; i += 8) { + _mm256_storeu_ps(y + i, _mm256_mul_ps(ggml_v_gelu_quick(_mm256_loadu_ps(x + i)), _mm256_loadu_ps(g + i))); + } +#elif defined(__SSE2__) + for (; i + 3 < n; i += 4) { + _mm_storeu_ps(y + i, _mm_mul_ps(ggml_v_gelu_quick(_mm_loadu_ps(x + i)), _mm_loadu_ps(g + i))); + } +#elif defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + const int vlen = svcntw(); + for (; i < n; i += vlen) { + const svbool_t pg = svwhilelt_b32_s32(i, n); + svst1_f32(pg, y + i, svmul_f32_x(pg, ggml_v_gelu_quick(pg, svld1_f32(pg, x + i)), svld1_f32(pg, g + i))); + } +#elif defined(__ARM_NEON) && defined(__aarch64__) + for (; i + 3 < n; i += 4) { + vst1q_f32(y + i, vmulq_f32(ggml_v_gelu_quick(vld1q_f32(x + i)), vld1q_f32(g + i))); + } +#elif defined(__VXE__) || defined(__VXE2__) + for (; i + 3 < n; i += 4) { + vec_xst(vec_mul(ggml_v_gelu_quick(vec_xl(0, x + i)), vec_xl(0, g + i)), 0, y + i); + } +#elif defined(__riscv_v_intrinsic) + for (int vl; i < n; i += vl) { + vl = __riscv_vsetvl_e32m2(n - i); + vfloat32m2_t vx = __riscv_vle32_v_f32m2(&x[i], vl); + vfloat32m2_t vg = __riscv_vle32_v_f32m2(&g[i], vl); + vfloat32m2_t vy = __riscv_vfmul_vv_f32m2(ggml_v_gelu_quick_m2(vx, vl), vg, vl); + __riscv_vse32_v_f32m2(&y[i], vy, vl); + } +#endif + for (; i < n; ++i) { + y[i] = ggml_gelu_quick_f32(x[i]) * g[i]; + } +} +#endif + ggml_float ggml_vec_cvar_f32(const int n, float * y, const float * x, const float mean) { int i = 0; ggml_float sum = 0; @@ -581,6 +675,12 @@ ggml_float ggml_vec_soft_max_f32(const int n, float * y, const float * x, float vst1q_f32(y + i, val); sum += (ggml_float)vaddvq_f32(val); } +#elif defined(__VXE__) || defined(__VXE2__) + for (; i + 3 < n; i += 4) { + float32x4_t v_val = ggml_v_expf(vec_sub(vec_xl(0, x + i), vec_splats(max))); + vec_xst(v_val, 0, y + i); + sum += (ggml_float)vec_hsum_f32x4(v_val); + } #elif defined(__riscv_v_intrinsic) vfloat64m1_t vsum = __riscv_vfmv_v_f_f64m1(0, 1); for (int avl; i < n; i += avl) { diff --git a/ggml/src/ggml-cpu/vec.h b/ggml/src/ggml-cpu/vec.h index 59fa88f2c9c5..f24fa00f2b0d 100644 --- a/ggml/src/ggml-cpu/vec.h +++ b/ggml/src/ggml-cpu/vec.h @@ -44,7 +44,6 @@ inline static ggml_float ggml_sve_sum_f32x2(svfloat32_t sum_lo, svfloat32_t sum_ #endif #define GGML_GELU_FP16 -#define GGML_GELU_QUICK_FP16 #define GGML_SOFT_MAX_UNROLL 4 #define GGML_VEC_DOT_UNROLL 2 @@ -1054,11 +1053,7 @@ inline static void ggml_vec_gelu_quick_f32(const int n, float * y, const float * } } #else -inline static void ggml_vec_gelu_quick_f32(const int n, float * y, const float * x) { - for (int i = 0; i < n; ++i) { - y[i] = ggml_gelu_quick_f32(x[i]); - } -} +void ggml_vec_gelu_quick_f32(const int n, float * y, const float * x); #endif // Sigmoid Linear Unit (SiLU) function @@ -1143,6 +1138,13 @@ inline static svfloat32_t ggml_v_silu(svbool_t pg, svfloat32_t x) { return svdiv_f32_x(pg, x, one_plus_exp_neg_x); } +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static svfloat32_t ggml_v_gelu_quick(svbool_t pg, svfloat32_t x) { + const svfloat32_t one = svdup_n_f32_x(pg, 1.0f); + const svfloat32_t exp_cx = ggml_v_expf(pg, svmul_n_f32_x(pg, x, GELU_QUICK_COEF)); + return svdiv_f32_x(pg, x, svadd_f32_x(pg, one, exp_cx)); +} + #elif defined(__ARM_NEON) && defined(__aarch64__) // adapted from arm limited optimized routine @@ -1182,6 +1184,13 @@ inline static float32x4_t ggml_v_silu(float32x4_t x) { return vdivq_f32(x, one_plus_exp_neg_x); } +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static float32x4_t ggml_v_gelu_quick(float32x4_t x) { + const float32x4_t one = vdupq_n_f32(1.0f); + const float32x4_t exp_cx = ggml_v_expf(vmulq_n_f32(x, GELU_QUICK_COEF)); + return vdivq_f32(x, vaddq_f32(one, exp_cx)); +} + #elif defined(__AVX512F__) && defined(__AVX512DQ__) // adapted from arm limited optimized routine @@ -1225,6 +1234,13 @@ inline static __m512 ggml_v_silu(__m512 x) { return _mm512_div_ps(x, one_plus_exp_neg_x); } +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static __m512 ggml_v_gelu_quick(__m512 x) { + const __m512 one = _mm512_set1_ps(1); + const __m512 exp_cx = ggml_v_expf(_mm512_mul_ps(x, _mm512_set1_ps(GELU_QUICK_COEF))); + return _mm512_div_ps(x, _mm512_add_ps(one, exp_cx)); +} + #elif defined(__AVX2__) && defined(__FMA__) // adapted from arm limited optimized routine @@ -1280,6 +1296,13 @@ inline static __m256 ggml_v_silu(__m256 x) { return _mm256_div_ps(x, one_plus_exp_neg_x); } +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static __m256 ggml_v_gelu_quick(__m256 x) { + const __m256 one = _mm256_set1_ps(1); + const __m256 exp_cx = ggml_v_expf(_mm256_mul_ps(x, _mm256_set1_ps(GELU_QUICK_COEF))); + return _mm256_div_ps(x, _mm256_add_ps(one, exp_cx)); +} + #elif defined(__SSE2__) // __AVX2__ / __ARM_NEON #if defined(__FMA__) @@ -1334,6 +1357,60 @@ inline static __m128 ggml_v_silu(__m128 x) { return _mm_div_ps(x, one_plus_exp_neg_x); } +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static __m128 ggml_v_gelu_quick(__m128 x) { + const __m128 one = _mm_set1_ps(1); + const __m128 exp_cx = ggml_v_expf(_mm_mul_ps(x, _mm_set1_ps(GELU_QUICK_COEF))); + return _mm_div_ps(x, _mm_add_ps(one, exp_cx)); +} + +#elif defined(__VXE__) || defined(__VXE2__) + +// adapted from arm limited optimized routine +// the maximum error is 1.45358 plus 0.5 ulps +// numbers above 88.38 will flush to infinity +// numbers beneath -103.97 will flush to zero +inline static float32x4_t ggml_v_expf(float32x4_t v_x) { + const float32x4_t v_r = vec_splats(0x1.8p23f); + const float32x4_t v_z = vec_madd(v_x, vec_splats(0x1.715476p+0f), v_r); + const float32x4_t v_n = vec_sub(v_z, v_r); + const float32x4_t v_b = vec_nmsub(v_n, vec_splats(0x1.7f7d1cp-20f), + vec_nmsub(v_n, vec_splats(0x1.62e4p-1f), v_x)); + const uint32x4_t v_e = vec_sl((uint32x4_t)v_z, 23); + const float32x4_t v_k = (float32x4_t)vec_add(v_e, (uint32x4_t)vec_splats(1.0f)); + const uint32x4_t v_c = (uint32x4_t)vec_cmpgt(vec_abs(v_n), vec_splats(126.0f)); + const float32x4_t v_u = vec_mul(v_b, v_b); + const float32x4_t v_j = vec_madd( + vec_madd(vec_madd(vec_splats(0x1.0e4020p-7f), v_b, vec_splats(0x1.573e2ep-5f)), v_u, + vec_madd(vec_splats(0x1.555e66p-3f), v_b, vec_splats(0x1.fffdb6p-2f))), + v_u, vec_mul(vec_splats(0x1.ffffecp-1f), v_b)); + if (vec_all_eq(v_c, vec_splats(UINT32_C(0)))) { + return vec_madd(v_j, v_k, v_k); + } + const uint32x4_t v_d = vec_and((uint32x4_t)vec_cmple(v_n, vec_splats(0.0f)), vec_splats(UINT32_C(0x82000000))); + const float32x4_t v_s1 = (float32x4_t)vec_add(v_d, vec_splats(UINT32_C(0x7f000000))); + const float32x4_t v_s2 = (float32x4_t)vec_sub(v_e, v_d); + return vec_sel(vec_sel(vec_madd(v_k, v_j, v_k), vec_mul(vec_madd(v_s2, v_j, v_s2), v_s1), v_c), + vec_mul(v_s1, v_s1), (uint32x4_t)vec_cmpgt(vec_abs(v_n), vec_splats(192.0f))); +} + +// computes silu x/(1+exp(-x)) in single precision vector +inline static float32x4_t ggml_v_silu(float32x4_t v_x) { + const float32x4_t v_one = vec_splats(1.0f); + const float32x4_t v_zero = vec_splats(0.0f); + const float32x4_t v_neg_x = vec_sub(v_zero, v_x); + const float32x4_t v_exp_neg_x = ggml_v_expf(v_neg_x); + const float32x4_t v_one_plus_exp_neg_x = vec_add(v_one, v_exp_neg_x); + return vec_div(v_x, v_one_plus_exp_neg_x); +} + +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static float32x4_t ggml_v_gelu_quick(float32x4_t x) { + const float32x4_t one = vec_splats(1.0f); + const float32x4_t exp_cx = ggml_v_expf(vec_mul(x, vec_splats(GELU_QUICK_COEF))); + return vec_div(x, vec_add(one, exp_cx)); +} + #elif defined(__riscv_v_intrinsic) // adapted from arm limited optimized routine @@ -1386,7 +1463,13 @@ inline static vfloat32m2_t ggml_v_silu_m2(vfloat32m2_t x, int vl) { return __riscv_vfdiv_vv_f32m2(x, one_plus_exp_neg_x, vl); } -#endif // __ARM_NEON / __AVX2__ / __SSE2__ / __riscv_v_intrinsic +// gelu_quick(x) = x / (1 + exp(-1.702 x)); x stays the numerator so it cannot overflow +inline static vfloat32m2_t ggml_v_gelu_quick_m2(vfloat32m2_t x, int vl) { + const vfloat32m2_t exp_cx = ggml_v_expf_m2(__riscv_vfmul_vf_f32m2(x, GELU_QUICK_COEF, vl), vl); + return __riscv_vfdiv_vv_f32m2(x, __riscv_vfadd_vf_f32m2(exp_cx, 1.0f, vl), vl); +} + +#endif // __ARM_NEON / __AVX2__ / __SSE2__ / __VXE__ / __riscv_v_intrinsic inline static void ggml_vec_silu_f16(const int n, ggml_fp16_t * y, const ggml_fp16_t * x) { for (int i = 0; i < n; ++i) { @@ -1531,11 +1614,7 @@ inline static void ggml_vec_geglu_quick_f32(const int n, float * y, const float } } #else -inline static void ggml_vec_geglu_quick_f32(const int n, float * y, const float * x, const float * g) { - for (int i = 0; i < n; ++i) { - y[i] = ggml_gelu_quick_f32(x[i]) * g[i]; - } -} +void ggml_vec_geglu_quick_f32(const int n, float * y, const float * x, const float * g); #endif inline static void ggml_vec_geglu_quick_f16(const int n, ggml_fp16_t * y, const ggml_fp16_t * x, const ggml_fp16_t * g) { diff --git a/ggml/src/ggml-cuda/common.cuh b/ggml/src/ggml-cuda/common.cuh index 66aa2183f34e..4d7f945673ac 100644 --- a/ggml/src/ggml-cuda/common.cuh +++ b/ggml/src/ggml-cuda/common.cuh @@ -82,6 +82,7 @@ #define GGML_CUDA_CC_RDNA2 (GGML_CUDA_CC_OFFSET_AMD + 0x1030) // RX 6000, minimum for dp4a #define GGML_CUDA_CC_RDNA3 (GGML_CUDA_CC_OFFSET_AMD + 0x1100) // RX 7000, minimum for WMMA #define GGML_CUDA_CC_RDNA3_5 (GGML_CUDA_CC_OFFSET_AMD + 0x1150) // AI 370, AI Max 395 laptops. +#define GGML_CUDA_CC_RDNA4_M (GGML_CUDA_CC_OFFSET_AMD + 0x1170) // gfx117X #define GGML_CUDA_CC_RDNA4 (GGML_CUDA_CC_OFFSET_AMD + 0x1200) // RX 9000 #define GGML_CUDA_CC_IS_AMD(cc) (cc >= GGML_CUDA_CC_OFFSET_AMD) @@ -89,8 +90,9 @@ #define GGML_CUDA_CC_IS_RDNA1(cc) (cc >= GGML_CUDA_CC_RDNA1 && cc < GGML_CUDA_CC_RDNA2) #define GGML_CUDA_CC_IS_RDNA2(cc) (cc >= GGML_CUDA_CC_RDNA2 && cc < GGML_CUDA_CC_RDNA3) #define GGML_CUDA_CC_IS_RDNA3_0(cc) (cc >= GGML_CUDA_CC_RDNA3 && cc < GGML_CUDA_CC_RDNA3_5) -#define GGML_CUDA_CC_IS_RDNA3_5(cc) (cc >= GGML_CUDA_CC_RDNA3_5 && cc < GGML_CUDA_CC_RDNA4) +#define GGML_CUDA_CC_IS_RDNA3_5(cc) (cc >= GGML_CUDA_CC_RDNA3_5 && cc < GGML_CUDA_CC_RDNA4_M) #define GGML_CUDA_CC_IS_RDNA3(cc) (GGML_CUDA_CC_IS_RDNA3_0(cc) || GGML_CUDA_CC_IS_RDNA3_5(cc)) +#define GGML_CUDA_CC_IS_RDNA4_M(cc) (cc >= GGML_CUDA_CC_RDNA4_M && cc < GGML_CUDA_CC_RDNA4) #define GGML_CUDA_CC_IS_RDNA4(cc) (cc >= GGML_CUDA_CC_RDNA4) #define GGML_CUDA_CC_IS_GCN_APU(cc) ((cc) == GGML_CUDA_CC_GFX909 || (cc) == GGML_CUDA_CC_GFX90C) #define GGML_CUDA_CC_IS_GCN(cc) ((cc > GGML_CUDA_CC_OFFSET_AMD && cc < GGML_CUDA_CC_CDNA1) || GGML_CUDA_CC_IS_GCN_APU(cc)) @@ -277,9 +279,17 @@ static const char * cu_get_error_str(CUresult err) { #define AMD_MFMA_AVAILABLE #endif // defined(GGML_USE_HIP) && defined(CDNA) && !defined(GGML_HIP_NO_MMQ_MFMA) -#if defined(GGML_USE_HIP) && (defined(RDNA4) || defined(RDNA3)) +#if defined(GGML_USE_HIP) && (defined(RDNA4) || defined(RDNA4_M)) +#define AMD_WMMA_128B_AVAILABLE +#endif // defined(GGML_USE_HIP) && (defined(RDNA4) || defined(RDNA4_M)) + +#if defined(GGML_USE_HIP) && defined(RDNA3) +#define AMD_WMMA_256B_AVAILABLE +#endif // defined(GGML_USE_HIP) && defined(RDNA3) + +#if defined(AMD_WMMA_128B_AVAILABLE) || defined(AMD_WMMA_256B_AVAILABLE) #define AMD_WMMA_AVAILABLE -#endif // defined(GGML_USE_HIP) && defined(RDNA4) +#endif // defined(AMD_WMMA_128B_AVAILABLE) || defined(AMD_WMMA_256B_AVAILABLE) // The Volta instructions are in principle available on Turing or newer but they are effectively unusable: #if !defined(GGML_USE_HIP) && __CUDA_ARCH__ == GGML_CUDA_CC_VOLTA @@ -326,7 +336,7 @@ static bool fast_fp16_hardware_available(const int cc) { // To be used for feature selection of external libraries, e.g. cuBLAS. static bool fp16_mma_hardware_available(const int cc) { return (GGML_CUDA_CC_IS_NVIDIA(cc) && cc >= GGML_CUDA_CC_VOLTA) || - GGML_CUDA_CC_IS_CDNA(cc) || GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4(cc) || + GGML_CUDA_CC_IS_CDNA(cc) || GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc) || GGML_CUDA_CC_IS_RDNA4(cc) || (GGML_CUDA_CC_IS_MTHREADS(cc) && cc >= GGML_CUDA_CC_QY2); } @@ -355,7 +365,7 @@ static bool amd_mfma_available(const int cc) { } static bool amd_wmma_available(const int cc) { - return (GGML_CUDA_CC_IS_RDNA4(cc) || GGML_CUDA_CC_IS_RDNA3(cc)); + return GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc) || GGML_CUDA_CC_IS_RDNA4(cc); } static bool volta_mma_available(const int cc) { @@ -713,7 +723,7 @@ static __device__ __forceinline__ int ggml_cuda_dp4a(const int a, const int b, i #if defined(GGML_USE_HIP) #if defined(CDNA) || defined(RDNA2) || defined(__gfx906__) c = __builtin_amdgcn_sdot4(a, b, c, false); -#elif defined(RDNA3) || defined(RDNA4) +#elif defined(RDNA3) || defined(RDNA4_M) || defined(RDNA4) c = __builtin_amdgcn_sudot4( true, a, true, b, c, false); #elif defined(RDNA1) || defined(__gfx900__) int tmp1; @@ -758,9 +768,9 @@ static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const float2 v acc += v.y*u.y; } -#if defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4) || defined(__gfx906__) || defined(CDNA)) +#if defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4_M) || defined(RDNA4) || defined(__gfx906__) || defined(CDNA)) #define V_DOT2_F32_F16_AVAILABLE -#endif // defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4) || defined(__gfx906__) || defined(CDNA)) +#endif // defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4_M) || defined(RDNA4) || defined(__gfx906__) || defined(CDNA)) static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const half2 v, const half2 u) { #ifdef V_DOT2_F32_F16_AVAILABLE @@ -1320,15 +1330,12 @@ struct ggml_tensor_extra_gpu { struct ggml_cuda_graph { #ifdef USE_CUDA_GRAPH ~ggml_cuda_graph() { - if (instance != nullptr) { + for (cudaGraphExec_t instance : instances) { CUDA_CHECK(cudaGraphExecDestroy(instance)); } - if (graph != nullptr) { - CUDA_CHECK(cudaGraphDestroy(graph)); - } } - cudaGraph_t graph = nullptr; - cudaGraphExec_t instance = nullptr; + // the ggml graph is captured as a series of CUDA graphs, so the GPU can run one chunk while the next is enqueued + std::vector instances; size_t num_nodes = 0; std::vector nodes; bool disable_due_to_gpu_arch = false; @@ -1557,7 +1564,7 @@ struct ggml_backend_cuda_context { // Check if any CUDA graph has an instance for this context bool any_cuda_graph_has_instance() const { for (const auto & [key, graph] : cuda_graphs) { - if (graph && graph->instance != nullptr) { + if (graph && !graph->instances.empty()) { return true; } } @@ -1612,11 +1619,11 @@ struct ggml_backend_cuda_context { // pool std::unique_ptr pools[GGML_CUDA_MAX_DEVICES][GGML_CUDA_MAX_STREAMS]; - static std::unique_ptr new_pool_for_device(int device, int stream_no); + static std::unique_ptr new_pool_for_device(ggml_backend_cuda_context & ctx, int device, int stream_no); ggml_cuda_pool & pool(int device) { if (pools[device][curr_stream_no] == nullptr) { - pools[device][curr_stream_no] = new_pool_for_device(device, curr_stream_no); + pools[device][curr_stream_no] = new_pool_for_device(*this, device, curr_stream_no); } return *pools[device][curr_stream_no]; } diff --git a/ggml/src/ggml-cuda/conv2d.cu b/ggml/src/ggml-cuda/conv2d.cu index 9636db23713b..c5e1836fff72 100644 --- a/ggml/src/ggml-cuda/conv2d.cu +++ b/ggml/src/ggml-cuda/conv2d.cu @@ -180,7 +180,6 @@ static __global__ void conv2d_implicit_gemm_f16(const half * __restrict__ input, const int end = int(int64_t(tiles) * (split + 1) / split_k) * BK; for (int k0 = begin; k0 < end; k0 += BK) { if (k_total % 8 == 0 && uintptr_t(weight) % 16 == 0) { -#pragma unroll for (int i = tid; i < BM * BK / 8; i += nthreads) { const int row = i / (BK / 8), col = 8 * (i % (BK / 8)); const int4 v = m0 + row < oc && k0 + col < k_total ? @@ -189,7 +188,6 @@ static __global__ void conv2d_implicit_gemm_f16(const half * __restrict__ input, *(int4 *) &a_s[row][col / 2] = v; } } else { -#pragma unroll for (int i = tid; i < BM * BK / 2; i += nthreads) { const int row = i / (BK / 2), col = 2 * (i % (BK / 2)); half lo = __float2half(0.0f), hi = lo; @@ -202,7 +200,6 @@ static __global__ void conv2d_implicit_gemm_f16(const half * __restrict__ input, a_s[row][col / 2] = __halves2half2(lo, hi); } } -#pragma unroll for (int k = load_row; k < BK; k += nthreads / (BN / 2)) { const int ki = k0 + k; const int ci = ki / (kw * kh), ky = ki / kw % kh, kx = ki % kw; diff --git a/ggml/src/ggml-cuda/dsv4-hc.cu b/ggml/src/ggml-cuda/dsv4-hc.cu index ca1d2dc8a482..2d0b3cfeaed7 100644 --- a/ggml/src/ggml-cuda/dsv4-hc.cu +++ b/ggml/src/ggml-cuda/dsv4-hc.cu @@ -145,7 +145,8 @@ static __global__ void dsv4_hc_pre_f32( dst[i0*sd0 + it*sd1] = scale * sum; } -template +// gated: post = gate_scale_out*sigmoid(gate_scale_in*post), the fused SCALE -> SIGMOID -> SCALE chain of qwen4exp +template static __global__ void dsv4_hc_post_f32( const float * x, const float * residual, @@ -167,7 +168,9 @@ static __global__ void dsv4_hc_post_f32( int64_t sc2, int64_t sd0, int64_t sd1, - int64_t sd2) { + int64_t sd2, + float gate_scale_in, + float gate_scale_out) { ggml_cuda_pdl_lc(); const int64_t ir = (int64_t) blockIdx.x * blockDim.x + threadIdx.x; const int64_t nr = n_embd * hc * n_tokens; @@ -182,7 +185,12 @@ static __global__ void dsv4_hc_post_f32( const int64_t idst = (ir / n_embd) % hc; const int64_t it = ir / (n_embd * hc); - float sum = x[i0*sx0 + it*sx1] * post[idst*sp0 + it*sp1]; + float p = post[idst*sp0 + it*sp1]; + if constexpr (gated) { + p = gate_scale_out * (1.0f / (1.0f + expf(-(gate_scale_in * p)))); + } + + float sum = x[i0*sx0 + it*sx1] * p; if constexpr (has_comb) { for (int64_t isrc = 0; isrc < hc; ++isrc) { sum += residual[i0*sr0 + isrc*sr1 + it*sr2] * comb[idst*sc0 + isrc*sc1 + it*sc2]; @@ -272,12 +280,19 @@ void ggml_cuda_op_dsv4_hc_pre(ggml_backend_cuda_context & ctx, ggml_tensor * dst scale); } -void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { +void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst, + const ggml_tensor * gate_scale_in, const ggml_tensor * gate_scale_out) { const ggml_tensor * x = dst->src[0]; const ggml_tensor * residual = dst->src[1]; - const ggml_tensor * post = dst->src[2]; const ggml_tensor * comb = dst->src[3]; + // when fused, read the raw post weights from before the SCALE -> SIGMOID -> SCALE chain + const bool gated = gate_scale_in != nullptr; + const ggml_tensor * post = gated ? gate_scale_in->src[0] : dst->src[2]; + + const float gate_in = gated ? ggml_get_op_params_f32(gate_scale_in, 0) : 1.0f; + const float gate_out = gated ? ggml_get_op_params_f32(gate_scale_out, 0) : 1.0f; + GGML_ASSERT(x->type == GGML_TYPE_F32); GGML_ASSERT(residual->type == GGML_TYPE_F32); GGML_ASSERT(post->type == GGML_TYPE_F32); @@ -303,7 +318,8 @@ void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * ds const dim3 grid_dims((nr + block_size - 1) / block_size, 1, 1); const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(grid_dims, block_dims, 0, ctx.stream()); - auto kernel = comb ? dsv4_hc_post_f32 : dsv4_hc_post_f32; + auto kernel = comb ? (gated ? dsv4_hc_post_f32 : dsv4_hc_post_f32) + : (gated ? dsv4_hc_post_f32 : dsv4_hc_post_f32); ggml_cuda_kernel_launch(kernel, launch_params, (const float *) x->data, (const float *) residual->data, (const float *) post->data, comb ? (const float *) comb->data : nullptr, (float *) dst->data, @@ -312,5 +328,6 @@ void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * ds nbr0 / sizeof(float), nbr1 / sizeof(float), nbr2 / sizeof(float), nbp0 / sizeof(float), nbp1 / sizeof(float), nbc0 / sizeof(float), nbc1 / sizeof(float), nbc2 / sizeof(float), - nbd0 / sizeof(float), nbd1 / sizeof(float), nbd2 / sizeof(float)); + nbd0 / sizeof(float), nbd1 / sizeof(float), nbd2 / sizeof(float), + gate_in, gate_out); } diff --git a/ggml/src/ggml-cuda/dsv4-hc.cuh b/ggml/src/ggml-cuda/dsv4-hc.cuh index 2379aaefb41b..1885e76659d5 100644 --- a/ggml/src/ggml-cuda/dsv4-hc.cuh +++ b/ggml/src/ggml-cuda/dsv4-hc.cuh @@ -3,4 +3,6 @@ void ggml_cuda_op_dsv4_hc_comb(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_dsv4_hc_pre(ggml_backend_cuda_context & ctx, ggml_tensor * dst); -void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +// gate_scale_in/gate_scale_out: the SCALE nodes of a fused SCALE -> SIGMOID -> SCALE chain feeding src[2] +void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst, + const ggml_tensor * gate_scale_in = nullptr, const ggml_tensor * gate_scale_out = nullptr); diff --git a/ggml/src/ggml-cuda/fattn-common.cuh b/ggml/src/ggml-cuda/fattn-common.cuh index 41d948335ef5..beb877941c75 100644 --- a/ggml/src/ggml-cuda/fattn-common.cuh +++ b/ggml/src/ggml-cuda/fattn-common.cuh @@ -25,6 +25,7 @@ typedef void (* fattn_kernel_t)( const char * __restrict__ mask, const char * __restrict__ sinks, const int * __restrict__ KV_max, + const int * __restrict__ KV_rows, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -991,8 +992,13 @@ void launch_fattn( const bool V_is_K_view = V->view_src && (V->view_src == K || (V->view_src == K->view_src && V->view_offs == K->view_offs)); - const ggml_tensor * mask = dst->src[3]; - const ggml_tensor * sinks = dst->src[4]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + const ggml_tensor * kv_rows = dst->src[5]; + + // with kv_rows the kernel iterates over the mask columns and reads K/V rows through kv_rows + const int64_t n_kv_cols = kv_rows ? kv_rows->ne[0] : K->ne[1]; + GGML_ASSERT(!kv_rows || !use_sparse); ggml_tensor * KQV = dst; @@ -1113,8 +1119,8 @@ void launch_fattn( // Optional optimization where the mask is scanned to determine whether part of the calculation can be skipped. // Only worth the overhead if there is at lease one FATTN_KQ_STRIDE x FATTN_KQ_STRIDE square to be skipped or - // multiple sequences of possibly different lengths. - const bool scan_mask = !use_sparse && mask && K->ne[1] % FATTN_KQ_STRIDE == 0 && (Q->ne[1] >= 1024 || Q->ne[3] > 1); + // multiple sequences of possibly different lengths, or kv_rows lists that end with padding. + const bool scan_mask = !use_sparse && mask && n_kv_cols % FATTN_KQ_STRIDE == 0 && (Q->ne[1] >= 1024 || Q->ne[3] > 1 || kv_rows); if (scan_mask) { const int64_t s31 = mask->nb[1] / sizeof(half2); const int64_t s33 = mask->nb[3] / sizeof(half2); @@ -1123,7 +1129,7 @@ void launch_fattn( const dim3 block_dim_KV_max(FATTN_KQ_STRIDE/2, 1, 1); const int ne_KV_max = blocks_num_KV_max.x*blocks_num_KV_max.y; - const int iter_k = K->ne[1] / FATTN_KQ_STRIDE; + const int iter_k = n_kv_cols / FATTN_KQ_STRIDE; KV_max.alloc(ne_KV_max); ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(blocks_num_KV_max, block_dim_KV_max, 0, main_stream); @@ -1132,13 +1138,19 @@ void launch_fattn( CUDA_CHECK(cudaGetLastError()); } + // K/V are shared by all slices when read through kv_rows + if (kv_rows) { + nb13 = 0; + nb23 = 0; + } + const dim3 block_dim(warp_size, nwarps, 1); int max_blocks_per_sm = 1; // Max. number of active blocks limited by occupancy. CUDA_CHECK(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&max_blocks_per_sm, fattn_kernel, block_dim.x * block_dim.y * block_dim.z, nbytes_shared)); GGML_ASSERT(max_blocks_per_sm > 0); int parallel_blocks = max_blocks_per_sm; - const int64_t n_kv = use_sparse ? n_kv_max : K->ne[1]; + const int64_t n_kv = use_sparse ? n_kv_max : n_kv_cols; const int ntiles_KV = (n_kv + nbatch_fa - 1) / nbatch_fa; // Max. number of parallel blocks limited by KV cache length. dim3 blocks_num; @@ -1255,6 +1267,7 @@ void launch_fattn( mask ? ((const char *) mask->data) : nullptr, sinks ? ((const char *) sinks->data) : nullptr, KV_max.ptr, + kv_rows ? (const int *) kv_rows->data : nullptr, !stream_k && parallel_blocks > 1 ? dst_tmp.ptr : (float *) KQV->data, dst_tmp_meta.ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, Q->ne[0], ne01, Q->ne[2], Q->ne[3], Q->nb[1], Q->nb[2], Q->nb[3], diff --git a/ggml/src/ggml-cuda/fattn-mma-f16.cuh b/ggml/src/ggml-cuda/fattn-mma-f16.cuh index 296aa2b34964..96b596ea6fb5 100644 --- a/ggml/src/ggml-cuda/fattn-mma-f16.cuh +++ b/ggml/src/ggml-cuda/fattn-mma-f16.cuh @@ -420,6 +420,9 @@ static __device__ __forceinline__ void flash_attn_ext_f16_load_tile( // padded slots gather row 0, the -inf mask removes their contribution const int32_t index = i < i_sup ? indices[k_VKQ_0 + i] : 0; i_KV = index >= 0 ? index : 0; + } else if (indices) { + // K/V rows given per mask column, negative rows are padding + i_KV = max(indices[k_VKQ_0 + i], 0); } else { i_KV = k_VKQ_0 + i; } @@ -467,8 +470,11 @@ static __device__ __forceinline__ void flash_attn_ext_f16_load_tile( if constexpr (use_sparse) { const int32_t index = i < i_sup ? indices[k_VKQ_0 + i] : -1; src = index >= 0 ? KV + int64_t(index)*stride_KV + k*h2_per_chunk : zero; + } else if (!oob_check || i < i_sup) { + const int64_t i_KV = indices ? max(indices[k_VKQ_0 + i], 0) : k_VKQ_0 + i; + src = KV + i_KV*stride_KV + k*h2_per_chunk; } else { - src = !oob_check || i < i_sup ? KV + int64_t(k_VKQ_0 + i)*stride_KV + k*h2_per_chunk : zero; + src = zero; } ggml_cuda_memcpy_1<16>(swizzle(tile_KV, i*stride_tile + k*h2_per_chunk, i), src); } @@ -634,7 +640,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( cp_async_wait_all(); __syncthreads(); flash_attn_ext_f16_load_tile - (V_h2, tile_V, nbatch_V2, stride_V, k_VKQ_0, k_VKQ_sup, nullptr); + (V_h2, tile_V, nbatch_V2, stride_V, k_VKQ_0, k_VKQ_sup, indices); } else { // the sparse mask values are gathered per element, always load them synchronously constexpr bool use_cp_async = nstages == 1 && !use_sparse; @@ -991,7 +997,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( (mask_h, tile_mask, stride_mask, k_VKQ_0 + nbatch_fa, k_VKQ_sup, jt*ncols1, ne01, nullptr); } flash_attn_ext_f16_load_tile - (K_h2, tile_K, nbatch_K2, stride_K, k_VKQ_0 + nbatch_fa, k_VKQ_sup, nullptr); + (K_h2, tile_K, nbatch_K2, stride_K, k_VKQ_0 + nbatch_fa, k_VKQ_sup, indices); } } @@ -1255,7 +1261,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( T_B_KQ Q_B[(Q_in_reg ? DKQ/(2*T_B_KQ::J) : 1)]; #if defined(TURING_MMA_AVAILABLE) T_C_VKQ VKQ_C[cols_per_warp == 8 ? DV/T_C_VKQ::I : DV/(2*T_C_VKQ::J)]; -#elif defined(AMD_WMMA_AVAILABLE) && defined(RDNA3) +#elif defined(AMD_WMMA_256B_AVAILABLE) T_C_VKQ VKQ_C[DV % 32 != 0 ? DV/T_C_VKQ::J : DV/(2*T_C_VKQ::J)]; #elif defined(AMD_MFMA_AVAILABLE) T_C_VKQ VKQ_C[ DV/T_C_VKQ::J]; @@ -1343,7 +1349,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( (mask_h, tile_mask, stride_mask, kb0*nbatch_fa, k_VKQ_sup, jt*ncols1, ne01, nullptr); } flash_attn_ext_f16_load_tile - (K_h2, tile_K, nbatch_K2, stride_K, kb0*nbatch_fa, k_VKQ_sup, nullptr); + (K_h2, tile_K, nbatch_K2, stride_K, kb0*nbatch_fa, k_VKQ_sup, indices); } // kb0_start is always < kb0_stop so the last iter can be executed unconditionally. @@ -1802,6 +1808,7 @@ static __global__ void flash_attn_ext_f16( const char * mask_ptr, const char * sinks_ptr, const int * KV_max_ptr, + const int * KV_rows_ptr, float * dst_ptr, float2 * dst_meta_ptr, const float scale, @@ -1866,7 +1873,7 @@ static __global__ void flash_attn_ext_f16( #endif // defined(AMD_WMMA_AVAILABLE) #if defined(AMD_MFMA_AVAILABLE) - if (ncols1*ncols2 < 16 || (DKQ > 256 && ncols1*ncols2 < 32)) { + if (ncols1*ncols2 < 16 || (DKQ > 256 && ncols1*ncols2 < 32 && !use_sparse)) { NO_DEVICE_CODE; return; } @@ -1924,7 +1931,8 @@ static __global__ void flash_attn_ext_f16( const half2 * V_h2 = V_is_K_view ? K_h2 : (const half2 *) (V + nb23*sequence + nb22*z_KV); const float * sinks_f = sinks ? (const float *) sinks + zt_Q : nullptr; - const int32_t * indices = use_sparse ? sparse_indices + (int64_t(sequence % ne33)*iter_j + jt)*ne11 : nullptr; + const int32_t * indices = use_sparse ? sparse_indices + (int64_t(sequence % ne33)*iter_j + jt)*ne11 : + KV_rows_ptr ? KV_rows_ptr + int64_t(sequence)*ne11 : nullptr; const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, zt_Q, n_head_log2, m0, m1) : 1.0f; @@ -1973,7 +1981,8 @@ static __global__ void flash_attn_ext_f16( const half2 * V_h2 = V_is_K_view ? K_h2 : (const half2 *) (V + nb23*sequence + nb22*z_KV); const float * sinks_f = sinks ? (const float *) sinks + zt_Q : nullptr; - const int32_t * indices = use_sparse ? sparse_indices + (int64_t(sequence % ne33)*iter_j + jt)*ne11 : nullptr; + const int32_t * indices = use_sparse ? sparse_indices + (int64_t(sequence % ne33)*iter_j + jt)*ne11 : + KV_rows_ptr ? KV_rows_ptr + int64_t(sequence)*ne11 : nullptr; const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, zt_Q, n_head_log2, m0, m1) : 1.0f; @@ -1989,7 +1998,7 @@ static __global__ void flash_attn_ext_f16( (Q_f2, K_h2, V_h2, mask_h, indices, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, gqa_ratio, ne11, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, zt_gqa, kb0_start, kb0_stop); #else - GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, dst_ptr, dst_meta_ptr, scale, + GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, KV_rows_ptr, dst_ptr, dst_meta_ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, ne00, ne01, ne02, ne03, nb01, nb02, nb03, @@ -2054,7 +2063,7 @@ void ggml_cuda_flash_attn_ext_mma_f16_case(ggml_backend_cuda_context & ctx, ggml bool use_sparse = false; if (logit_softcap == 0.0f) { constexpr bool use_logit_softcap = false; -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_MUSA) if constexpr (ggml_cuda_flash_attn_ext_mma_f16_may_use_sparse(DKQ, DV, ncols1, ncols2)) { if (ggml_cuda_flash_attn_ext_mma_f16_shall_use_sparse(cc, dst, ncols1, ncols2)) { constexpr bool use_sparse_kernel = true; @@ -2077,7 +2086,7 @@ void ggml_cuda_flash_attn_ext_mma_f16_case(ggml_backend_cuda_context & ctx, ggml } } } else -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_MUSA) { constexpr bool use_sparse_kernel = false; fattn_kernel = flash_attn_ext_f16; diff --git a/ggml/src/ggml-cuda/fattn-tile.cuh b/ggml/src/ggml-cuda/fattn-tile.cuh index e9f012fdfa30..bc2b71a9ea10 100644 --- a/ggml/src/ggml-cuda/fattn-tile.cuh +++ b/ggml/src/ggml-cuda/fattn-tile.cuh @@ -810,6 +810,7 @@ static __global__ void flash_attn_tile( const char * mask_ptr, const char * sinks_ptr, const int * KV_max_ptr, + const int * KV_rows_ptr, float * dst_ptr, float2 * dst_meta_ptr, const float scale, @@ -834,6 +835,7 @@ static __global__ void flash_attn_tile( const int * GGML_CUDA_RESTRICT KV_max = KV_max_ptr; float * GGML_CUDA_RESTRICT dst = dst_ptr; float2 * GGML_CUDA_RESTRICT dst_meta = dst_meta_ptr; + GGML_UNUSED(KV_rows_ptr); // Skip unused kernel variants for faster compilation: @@ -968,7 +970,7 @@ static __global__ void flash_attn_tile( if (ncols2 == 1) { // Branch with out-of-bounds checks. int k_VKQ_0 = blockIdx.y*nbatch_fa; - while (k_VKQ_0 < k_VKQ_max - nbatch_fa) { + while (k_VKQ_0 <= k_VKQ_max - nbatch_fa) { constexpr bool oob_check = false; flash_attn_tile_iter (Q_tmp, K_h2, V_h2, maskh, ne01, logit_softcap, slope, KQ, KV_tmp, @@ -1145,7 +1147,7 @@ static __global__ void flash_attn_tile( } } #else - GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, dst_ptr, dst_meta_ptr, scale, + GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, KV_rows_ptr, dst_ptr, dst_meta_ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, ne00, ne01, ne02, ne03, nb01, nb02, nb03, diff --git a/ggml/src/ggml-cuda/fattn-vec.cuh b/ggml/src/ggml-cuda/fattn-vec.cuh index 57a285565913..9df15128f0ca 100644 --- a/ggml/src/ggml-cuda/fattn-vec.cuh +++ b/ggml/src/ggml-cuda/fattn-vec.cuh @@ -25,6 +25,7 @@ static __global__ void flash_attn_ext_vec( const char * mask_ptr, const char * sinks_ptr, const int * KV_max_ptr, + const int * KV_rows_ptr, float * dst_ptr, float2 * dst_meta_ptr, const float scale, @@ -50,6 +51,7 @@ static __global__ void flash_attn_ext_vec( const int * GGML_CUDA_RESTRICT KV_max = KV_max_ptr; float * GGML_CUDA_RESTRICT dst = dst_ptr; float2 * GGML_CUDA_RESTRICT dst_meta = dst_meta_ptr; + GGML_UNUSED(KV_rows_ptr); // Skip unused kernel variants for faster compilation: if (use_logit_softcap && !(D == 128 || D == 256)) { @@ -317,7 +319,7 @@ static __global__ void flash_attn_ext_vec( #endif // V_DOT2_F32_F16_AVAILABLE } - ggml_cuda_syncwarp(); + ggml_cuda_syncwarp(); // Needed for KQ synchronization. #pragma unroll for (int k0 = 0; k0 < WARP_SIZE; k0 += V_cols_per_iter) { @@ -374,6 +376,8 @@ static __global__ void flash_attn_ext_vec( } #endif // V_DOT2_F32_F16_AVAILABLE } + + ggml_cuda_syncwarp(); // Needed for KQ synchronization. } if (sinks && blockIdx.y == 0) { @@ -512,7 +516,7 @@ static __global__ void flash_attn_ext_vec( dst_meta[((sequence*int(ne01.z) + ic0 + tid)*ne02 + head)*gridDim.y + blockIdx.y] = make_float2(KQ_max[tid], KQ_sum[tid]); } #else - GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, dst_ptr, dst_meta_ptr, scale, + GGML_UNUSED_VARS(Q_ptr, K_ptr, V_ptr, mask_ptr, sinks_ptr, KV_max_ptr, KV_rows_ptr, dst_ptr, dst_meta_ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, ne00, ne01, ne02, ne03, nb01, nb02, nb03, diff --git a/ggml/src/ggml-cuda/fattn.cu b/ggml/src/ggml-cuda/fattn.cu index 5fa3e530840c..5d7ebf966378 100644 --- a/ggml/src/ggml-cuda/fattn.cu +++ b/ggml/src/ggml-cuda/fattn.cu @@ -5,7 +5,8 @@ #include "fattn-vec.cuh" #include "fattn.cuh" -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_MUSA) + // one list per group of ncols1 queries: a column is selected if any query of the group can see it template __launch_bounds__(256, 1) @@ -14,10 +15,20 @@ static __global__ void flash_attn_mask_to_sparse_indices( const int n_kv_max, const int64_t s31, const int64_t s33) { ggml_cuda_pdl_sync(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int values_per_lane = 8; + using lane_mask_t = std::conditional_t; + constexpr uint64_t ballot_mask = ~(lane_mask_t)0; + const auto popc = [](const lane_mask_t mask) { + if constexpr (warp_size == 64) { + return __popcll(mask); + } else { + return __popc(mask); + } + }; const int tid = threadIdx.x; - const int warp = tid / WARP_SIZE; - const int lane = tid % WARP_SIZE; + const int warp = tid / warp_size; + const int lane = tid % warp_size; const int sequence = blockIdx.y; const int group = blockIdx.x; @@ -27,7 +38,7 @@ static __global__ void flash_attn_mask_to_sparse_indices( const half * mask = mask_ptr + sequence*s33 + q0*s31; int32_t * indices = indices_ptr + (int64_t(sequence)*gridDim.x + group)*n_kv_max; - __shared__ int warp_offsets[256/WARP_SIZE]; + __shared__ int warp_offsets[256/warp_size]; __shared__ int row_count; __shared__ int chunk_count; @@ -37,11 +48,11 @@ static __global__ void flash_attn_mask_to_sparse_indices( __syncthreads(); for (int i0 = 0; i0 < ne30; i0 += blockDim.x*values_per_lane) { - uint32_t selected_warp[values_per_lane]; + lane_mask_t selected_warp[values_per_lane]; int warp_count = 0; #pragma unroll for (int item = 0; item < values_per_lane; ++item) { - const int i = i0 + (warp*values_per_lane + item)*WARP_SIZE + lane; + const int i = i0 + (warp*values_per_lane + item)*warp_size + lane; bool selected = false; if (i < ne30) { #pragma unroll @@ -49,8 +60,8 @@ static __global__ void flash_attn_mask_to_sparse_indices( selected |= (!oob || q < q1 - q0) && isfinite(__half2float(mask[q*s31 + i])); } } - selected_warp[item] = __ballot_sync(0xFFFFFFFF, selected); - warp_count += __popc(selected_warp[item]); + selected_warp[item] = (lane_mask_t)__ballot_sync(ballot_mask, (int) selected); + warp_count += popc(selected_warp[item]); } if (lane == 0) { @@ -61,7 +72,7 @@ static __global__ void flash_attn_mask_to_sparse_indices( if (tid == 0) { int offset = 0; #pragma unroll - for (int iw = 0; iw < 256/WARP_SIZE; ++iw) { + for (int iw = 0; iw < 256/warp_size; ++iw) { const int count = warp_offsets[iw]; warp_offsets[iw] = offset; offset += count; @@ -70,16 +81,16 @@ static __global__ void flash_attn_mask_to_sparse_indices( } __syncthreads(); - const uint32_t lane_mask = lane == 0 ? 0 : (1u << lane) - 1; + const lane_mask_t lane_mask = lane == 0 ? 0 : ((lane_mask_t)1 << lane) - 1; int warp_item_offset = 0; #pragma unroll for (int item = 0; item < values_per_lane; ++item) { - const int i = i0 + (warp*values_per_lane + item)*WARP_SIZE + lane; - const int dst = row_count + warp_offsets[warp] + warp_item_offset + __popc(selected_warp[item] & lane_mask); - if ((selected_warp[item] & (uint32_t(1) << lane)) && dst < n_kv_max) { + const int i = i0 + (warp*values_per_lane + item)*warp_size + lane; + const int dst = row_count + warp_offsets[warp] + warp_item_offset + popc(selected_warp[item] & lane_mask); + if ((selected_warp[item] & ((lane_mask_t)1 << lane)) && dst < n_kv_max) { indices[dst] = i; } - warp_item_offset += __popc(selected_warp[item]); + warp_item_offset += popc(selected_warp[item]); } __syncthreads(); @@ -101,13 +112,13 @@ static __global__ void flash_attn_mask_to_sparse_indices( // the dependent grid reads indices, signal once the row is complete ggml_cuda_pdl_lc(); } -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_MUSA) void ggml_cuda_flash_attn_ext_compact_mask( const ggml_tensor * mask, int32_t * indices, int32_t * counts, int32_t n_queries, int32_t ncols1, int32_t n_kv_max, cudaStream_t stream) { -#if defined(GGML_USE_HIP) || defined(GGML_USE_MUSA) +#ifdef GGML_USE_MUSA GGML_UNUSED_VARS(mask, indices, counts, n_queries, ncols1, n_kv_max, stream); - GGML_ABORT("sparse flash attention is only supported on NVIDIA CUDA"); + GGML_ABORT("sparse flash attention is not supported on MUSA"); #else const int64_t s31 = mask->nb[1] / sizeof(half); const int64_t s33 = mask->nb[3] / sizeof(half); @@ -122,16 +133,17 @@ void ggml_cuda_flash_attn_ext_compact_mask( ggml_cuda_kernel_launch(kernel, launch_params, (const half *) mask->data, indices, counts, int(mask->ne[0]), n_queries, n_kv_max, s31, s33); CUDA_CHECK(cudaGetLastError()); -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_MUSA) } bool ggml_cuda_flash_attn_ext_mma_f16_shall_use_sparse(const int cc, const ggml_tensor * dst, const int ncols1, const int ncols2) { -#if defined(GGML_USE_HIP) || defined(GGML_USE_MUSA) +#ifdef GGML_USE_MUSA GGML_UNUSED_VARS(cc, dst, ncols1, ncols2); return false; #else const ggml_tensor * Q = dst->src[0]; const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; const ggml_tensor * mask = dst->src[3]; float max_bias = 0.0f; @@ -139,16 +151,21 @@ bool ggml_cuda_flash_attn_ext_mma_f16_shall_use_sparse(const int cc, const ggml_ memcpy(&max_bias, (const float *) dst->op_params + 1, sizeof(float)); memcpy(&logit_softcap, (const float *) dst->op_params + 2, sizeof(float)); + // On CDNA only the DKQ=576 kernel variant with ncols2=16 is compiled with sparse support. + if (amd_mfma_available(cc) && !ggml_cuda_flash_attn_ext_mma_f16_may_use_sparse(int(Q->ne[0]), int(V->ne[0]), 1, 16)) { + return false; + } + const int32_t n_kv_max = ggml_get_op_params_i32(dst, 4); // the dense kernel handles up to 64/ncols2 queries per K/V pass, the single-query gather has to beat that const int64_t n_gather = (ncols1 == 1 ? std::min(Q->ne[1], 64/ncols2) : ncols1) * (int64_t) n_kv_max; - return GGML_CUDA_CC_IS_NVIDIA(cc) && turing_mma_available(cc) && + return ((GGML_CUDA_CC_IS_NVIDIA(cc) && turing_mma_available(cc)) || amd_mfma_available(cc)) && dst->src[5] == nullptr && mask != nullptr && n_kv_max > 0 && max_bias == 0.0f && logit_softcap == 0.0f && mask->ne[0] == K->ne[1] && mask->ne[1] >= Q->ne[1] && mask->ne[2] == 1 && - K->ne[1] >= std::max(4096, 2*n_gather); -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) + K->ne[1] >= std::max(4096, GGML_CUDA_CC_IS_NVIDIA(cc) ? 2*n_gather : 2LL*n_kv_max); +#endif // !defined(GGML_USE_MUSA) } template @@ -156,7 +173,7 @@ static void ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1(ggml_backend_cuda_con const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; const ggml_tensor * Q = dst->src[0]; -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_MUSA) if constexpr (ggml_cuda_flash_attn_ext_mma_f16_may_use_sparse(DKQ, DV, 1, ncols2)) { // a sparse variant at the full tile width gathers the union of its queries once, prefer it for large batches constexpr bool has_wide_sparse = ggml_cuda_flash_attn_ext_mma_f16_may_use_sparse(DKQ, DV, 64/ncols2, ncols2); @@ -165,7 +182,7 @@ static void ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1(ggml_backend_cuda_con return; } } -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_MUSA) if constexpr (ncols2 <= 8) { if (turing_mma_available(cc) && Q->ne[1] <= 8/ncols2) { @@ -199,12 +216,15 @@ static void ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2(ggml_backend_cuda_con const ggml_tensor * V = dst->src[2]; const ggml_tensor * mask = dst->src[3]; + // with kv_rows the kernel iterates over the mask columns + const int64_t n_kv = dst->src[5] ? dst->src[5]->ne[0] : K->ne[1]; + float max_bias = 0.0f; memcpy(&max_bias, (const float *) KQV->op_params + 1, sizeof(float)); // Edge cases like no mask, ALiBi, unpadded K/V, or misaligned addresses for large data transfers // are put into the template specialization without GQA optimizations. - bool use_gqa_opt = mask && max_bias == 0.0f && K->ne[1] % FATTN_KQ_STRIDE == 0; + bool use_gqa_opt = mask && max_bias == 0.0f && n_kv % FATTN_KQ_STRIDE == 0; for (const ggml_tensor * t : {Q, K, V, mask}) { if (t == nullptr || ggml_is_quantized(t->type)) { continue; @@ -365,7 +385,9 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg GGML_ASSERT(Q->ne[2] % K->ne[2] == 0); const int gqa_ratio = Q->ne[2] / K->ne[2]; - if (gqa_ratio == 20 && GGML_CUDA_CC_IS_NVIDIA(cc)) { // GLM 4.7 Flash + if (amd_mfma_available(cc) && ggml_cuda_flash_attn_ext_mma_f16_shall_use_sparse(cc, dst, 1, 16)) { + ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst); + } else if (gqa_ratio == 20 && GGML_CUDA_CC_IS_NVIDIA(cc)) { // GLM 4.7 Flash if (cc >= GGML_CUDA_CC_DGX_SPARK) { if (Q->ne[1] <= 8) { ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst); @@ -417,9 +439,7 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg #define FATTN_VEC_CASE(D, type_K_case, type_V_case) \ if constexpr (GGML_CUDA_FA_##type_K_case##_##type_V_case) { \ - const bool type_K_okay = type_K == GGML_TYPE_##type_K_case || (type_K == GGML_TYPE_F32 && GGML_TYPE_##type_K_case == GGML_TYPE_F16); \ - const bool type_V_okay = type_V == GGML_TYPE_##type_V_case || (type_V == GGML_TYPE_F32 && GGML_TYPE_##type_V_case == GGML_TYPE_F16); \ - if (head_size == (D) && type_K_okay && type_V_okay) { \ + if (head_size == (D) && type_K == GGML_TYPE_##type_K_case && type_V == GGML_TYPE_##type_V_case) { \ return ggml_cuda_flash_attn_ext_vec_case; \ } \ } \ @@ -432,7 +452,9 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg typedef void (* fattn_vec_case_t)(ggml_backend_cuda_context & ctx, ggml_tensor * dst); // Vector kernel for the given head size and K/V types, nullptr if its template instance was not compiled: -static fattn_vec_case_t ggml_cuda_get_fattn_vec_case(const int64_t head_size, const ggml_type type_K, const ggml_type type_V) { +static fattn_vec_case_t ggml_cuda_get_fattn_vec_case(const int64_t head_size, const ggml_type type_K_in, const ggml_type type_V_in) { + const ggml_type type_K = type_K_in == GGML_TYPE_F32 ? GGML_TYPE_F16 : type_K_in; + const ggml_type type_V = type_V_in == GGML_TYPE_F32 ? GGML_TYPE_F16 : type_V_in; FATTN_VEC_CASES_ALL_D(F16, F16) FATTN_VEC_CASES_ALL_D(Q4_0, F16) FATTN_VEC_CASES_ALL_D(Q4_1, F16) @@ -548,6 +570,10 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const const ggml_tensor * K = dst->src[1]; const ggml_tensor * V = dst->src[2]; const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * kv_rows = dst->src[5]; + + // with kv_rows the kernel iterates over the mask columns + const int64_t n_kv = kv_rows ? kv_rows->ne[0] : K->ne[1]; const int gqa_ratio = Q->ne[2] / K->ne[2]; GGML_ASSERT(Q->ne[2] % K->ne[2] == 0); @@ -557,7 +583,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const // The effective batch size for the kernel can be increased by gqa_ratio. // The kernel versions without this optimization are also used for ALiBi, if there is no mask, or if the KV cache is not padded, - bool gqa_opt_applies = gqa_ratio >= 2 && mask && max_bias == 0.0f && K->ne[1] % FATTN_KQ_STRIDE == 0; + bool gqa_opt_applies = gqa_ratio >= 2 && mask && max_bias == 0.0f && n_kv % FATTN_KQ_STRIDE == 0; for (const ggml_tensor * t : {Q, K, V, mask}) { if (t == nullptr || ggml_is_quantized(t->type)) { continue; @@ -629,6 +655,12 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const return BEST_FATTN_KERNEL_NONE; } + // only the MMA kernel reads K/V through kv_rows + if (kv_rows) { + return GGML_CUDA_CC_IS_NVIDIA(cc) && turing_mma_available(cc) && mask && Q->ne[0] != 40 && Q->ne[0] != 72 ? + BEST_FATTN_KERNEL_MMA_F16 : BEST_FATTN_KERNEL_NONE; + } + // For small batch sizes the vector kernel may be preferable over the kernels optimized for large batch sizes: // 192 satisfies % 64 == 0 but has no vec instance (DKQ != DV); force it onto the MMA path. const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % 64 == 0 && Q->ne[0] != 192 && K->ne[1] % FATTN_KQ_STRIDE == 0; @@ -679,6 +711,11 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const return BEST_FATTN_KERNEL_MMA_F16; } + // On CDNA, the sparse MMA kernel is used for DKQ=576 regardless of the head size heuristics. + if (amd_mfma_available(cc) && ggml_cuda_flash_attn_ext_mma_f16_shall_use_sparse(cc, dst, 1, 16)) { + return BEST_FATTN_KERNEL_MMA_F16; + } + // AMD MFMA needs a certain minimum batch size to outscale the tile kernel for large head sizes. if (amd_mfma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72) { if ((Q->ne[0] <= 64 && Q->ne[1] * gqa_ratio_eff > 8)) { diff --git a/ggml/src/ggml-cuda/gated-delta-net-mma.cu b/ggml/src/ggml-cuda/gated-delta-net-mma.cu index 8a9e926deb98..0684adc1ad3d 100644 --- a/ggml/src/ggml-cuda/gated-delta-net-mma.cu +++ b/ggml/src/ggml-cuda/gated-delta-net-mma.cu @@ -4,7 +4,7 @@ #include #include -namespace { +namespace ggml_cuda_gated_delta_net_mma { constexpr int D = 128; using bf16 = nv_bfloat16; @@ -417,6 +417,7 @@ static gdn_path select_gdn_mma_path(int device, const ggml_cuda_gdn_mma_args & a #endif // GGML_USE_HIP } } // namespace +using namespace ggml_cuda_gated_delta_net_mma; bool ggml_cuda_gdn_mma_launch(int device, const ggml_cuda_gdn_mma_args & a, cudaStream_t stream) { if (!a.state_out) { diff --git a/ggml/src/ggml-cuda/ggml-cuda.cu b/ggml/src/ggml-cuda/ggml-cuda.cu index 52ef97ff3a1d..929353e00ec9 100644 --- a/ggml/src/ggml-cuda/ggml-cuda.cu +++ b/ggml/src/ggml-cuda/ggml-cuda.cu @@ -74,6 +74,7 @@ #include "ggml-cuda/cumsum.cuh" #include "ggml-cuda/fill.cuh" #include "ggml-cuda/lightning-indexer.cuh" +#include "ggml-cuda/top-k-mask.cuh" #include "ggml.h" #include @@ -218,52 +219,36 @@ static cudaError_t ggml_cuda_device_malloc(void ** ptr, size_t size, int device) } #if defined(GGML_USE_HIP) -static int ggml_cuda_parse_id(char devName[]) { +static int ggml_cuda_parse_id(const char * devName) { // A list of possible Target IDs can be found under the rocclr/clr repo in device.cpp // these values are not stable so this is susceptible to breakage // https://github.com/ROCm/clr/blob/amd-staging/rocclr/device/device.cpp - int archMajor = 0x0; - int archMinor = 0x0; - int archNum = GGML_CUDA_CC_OFFSET_AMD; - int archLen = strlen(devName); - char archName[archLen + 1]; + // Extract the base architecture model ("gfx908:sramecc+:xnack-" -> "908") + std::string archName = devName; + archName.erase(0, 3); + archName = archName.substr(0, archName.find(':')); - // strip leading 'gfx' while copying into our buffer - if (archLen > 3) { - strcpy(archName, &devName[3]); - archLen -= 3; - } + const auto hex = [](const std::string & s) { return (int) strtoul(s.c_str(), nullptr, 16); }; - // trim trailing :xnack- or :sramecc- statuses - archLen = strcspn(archName, ":"); - archName[archLen] = '\0'; + int cc = 0; // tease out the version information - if (archLen > 8) { + if (archName.size() > 8) { // versions labeled generic use '-' as delimiter - // strip the trailing "-generic" then iterate through what remains - if ((strstr(archName, "-generic"))) { - archName[archLen - 8] = '\0'; - char * pch; - if ((pch = strtok(archName, "-"))) { - archMajor = (int)strtoul(pch, 0, 16); - if ((pch = strtok(NULL, "-"))) { - archMinor = 0x10 * (int)strtoul(pch, 0, 16); - } + if (archName.compare(archName.size() - 8, 8, "-generic") == 0) { + archName.resize(archName.size() - 8); + const size_t sep = archName.find('-'); + cc = 0x100 * hex(archName.substr(0, sep)); + if (sep != std::string::npos) { + cc += 0x10 * hex(archName.substr(sep + 1)); } } - } else if (archLen >= 3) { - // last two digits should be the minor * 0x10 + stepping - archMinor = (int)strtoul(&archName[archLen - 2], 0, 16); - archName[archLen - 2] = '\0'; - - // only the major version remains - archMajor = (int)strtoul(archName, 0, 16); + } else if (archName.size() >= 3) { + // ordinary IDs are the version in hex + cc = hex(archName); } - archNum += archMajor * 0x100; - archNum += archMinor; - return archNum; + return GGML_CUDA_CC_OFFSET_AMD + cc; } #endif // defined(GGML_USE_HIP) @@ -529,6 +514,7 @@ const ggml_cuda_device_info & ggml_cuda_info() { struct ggml_cuda_pool_leg : public ggml_cuda_pool { static const int MAX_BUFFERS = 256; + ggml_backend_cuda_context & ctx; int device; struct ggml_cuda_buffer { void * ptr = nullptr; @@ -538,7 +524,8 @@ struct ggml_cuda_pool_leg : public ggml_cuda_pool { ggml_cuda_buffer buffer_pool[MAX_BUFFERS] = {}; size_t pool_size = 0; - explicit ggml_cuda_pool_leg(int device) : + ggml_cuda_pool_leg(ggml_backend_cuda_context & ctx, int device) : + ctx(ctx), device(device) { } @@ -560,6 +547,20 @@ struct ggml_cuda_pool_leg : public ggml_cuda_pool { } } + // captured CUDA graphs can still use freed buffers, so they must be captured again + void invalidate_cuda_graphs() { +#ifdef USE_CUDA_GRAPH + int n_captured = 0; + for (const auto & [key, graph] : ctx.cuda_graphs) { + n_captured += graph->instances.size(); + } + if (n_captured > 0) { + GGML_LOG_DEBUG(GGML_CUDA_NAME " pool[%d]: memory freed, %d captured CUDA graphs must be captured again\n", device, n_captured); + } + ctx.cuda_graphs.clear(); +#endif // USE_CUDA_GRAPH + } + void * alloc(size_t size, size_t * actual_size) override { #ifdef DEBUG_CUDA_MALLOC int nnz = 0; @@ -610,6 +611,7 @@ struct ggml_cuda_pool_leg : public ggml_cuda_pool { device, look_ahead_size/1024.0/1024.0, cached_bytes/1024.0/1024.0); CUDA_CHECK(cudaDeviceSynchronize()); clear_pool(); + invalidate_cuda_graphs(); err = ggml_cuda_device_malloc(&ptr, look_ahead_size, device); if (err == cudaSuccess) { GGML_LOG_DEBUG(GGML_CUDA_NAME " pool[%d]: retry succeeded\n", device); @@ -638,6 +640,7 @@ struct ggml_cuda_pool_leg : public ggml_cuda_pool { ggml_cuda_set_device(device); CUDA_CHECK(cudaFree(ptr)); pool_size -= size; + invalidate_cuda_graphs(); } }; @@ -792,14 +795,15 @@ struct ggml_cuda_pool_vmm : public ggml_cuda_pool { }; #endif // defined(GGML_USE_VMM) -std::unique_ptr ggml_backend_cuda_context::new_pool_for_device(int device, - [[maybe_unused]] int stream_no) { +std::unique_ptr ggml_backend_cuda_context::new_pool_for_device(ggml_backend_cuda_context & ctx, + int device, + [[maybe_unused]] int stream_no) { #if defined(GGML_USE_VMM) if (ggml_cuda_info().devices[device].vmm) { return std::unique_ptr(new ggml_cuda_pool_vmm(device)); } #endif // defined(GGML_USE_VMM) - return std::unique_ptr(new ggml_cuda_pool_leg(device)); + return std::unique_ptr(new ggml_cuda_pool_leg(ctx, device)); } // destroying a cuBLAS handle while a graph is being captured in a different thread can result in a CUDA error @@ -969,6 +973,46 @@ static void ggml_backend_cuda_buffer_get_tensor_2d(ggml_backend_buffer_t buffer, CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); } +static void ggml_backend_cuda_buffer_set_tensor_n(ggml_backend_buffer_t buffer, struct ggml_tensor * const * tensors, const void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_backend_cuda_buffer_context * ctx = (ggml_backend_cuda_buffer_context *)buffer->context; + + ggml_cuda_set_device(ctx->device); + + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + CUDA_CHECK(cudaMemcpyAsync( + (char *) tensors[i]->data + offsets[i], + data[i], + sizes[i], + cudaMemcpyHostToDevice, + cudaStreamPerThread)); + } + + CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); +} + +static void ggml_backend_cuda_buffer_get_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * tensors, void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_backend_cuda_buffer_context * ctx = (ggml_backend_cuda_buffer_context *)buffer->context; + + ggml_cuda_set_device(ctx->device); + + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + CUDA_CHECK(cudaMemcpyAsync( + data[i], + (const char *) tensors[i]->data + offsets[i], + sizes[i], + cudaMemcpyDeviceToHost, + cudaStreamPerThread)); + } + + CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); +} + static bool ggml_backend_cuda_buffer_cpy_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * src, ggml_tensor * dst) { if (ggml_backend_buffer_is_cuda(src->buffer)) { ggml_backend_cuda_buffer_context * src_ctx = (ggml_backend_cuda_buffer_context *)src->buffer->context; @@ -994,6 +1038,54 @@ static bool ggml_backend_cuda_buffer_cpy_tensor(ggml_backend_buffer_t buffer, co GGML_UNUSED(buffer); } +static bool ggml_backend_cuda_buffer_cpy_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors) { + ggml_backend_cuda_buffer_context * dst_ctx = (ggml_backend_cuda_buffer_context *)buffer->context; + + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_buffer_t src_buf = srcs[i]->view_src ? srcs[i]->view_src->buffer : srcs[i]->buffer; + if (!ggml_backend_buffer_is_cuda(src_buf)) { + return false; + } + } + +#ifdef GGML_CUDA_NO_PEER_COPY + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_buffer_t src_buf = srcs[i]->view_src ? srcs[i]->view_src->buffer : srcs[i]->buffer; + ggml_backend_buffer_t dst_buf = dsts[i]->view_src ? dsts[i]->view_src->buffer : dsts[i]->buffer; + ggml_backend_cuda_buffer_context * src_ctx = (ggml_backend_cuda_buffer_context *)src_buf->context; + ggml_backend_cuda_buffer_context * dst_ctx_i = (ggml_backend_cuda_buffer_context *)dst_buf->context; + const int src_physical = ggml_cuda_get_physical_device(src_ctx->device); + const int dst_physical = ggml_cuda_get_physical_device(dst_ctx_i->device); + if (src_physical != dst_physical) { + return false; + } + } +#endif + + ggml_cuda_set_device(dst_ctx->device); + + for (size_t i = 0; i < n_tensors; i++) { + ggml_backend_buffer_t src_buf = srcs[i]->view_src ? srcs[i]->view_src->buffer : srcs[i]->buffer; + ggml_backend_buffer_t dst_buf = dsts[i]->view_src ? dsts[i]->view_src->buffer : dsts[i]->buffer; + ggml_backend_cuda_buffer_context * src_ctx = (ggml_backend_cuda_buffer_context *)src_buf->context; + ggml_backend_cuda_buffer_context * dst_ctx_i = (ggml_backend_cuda_buffer_context *)dst_buf->context; + const int src_physical = ggml_cuda_get_physical_device(src_ctx->device); + const int dst_physical = ggml_cuda_get_physical_device(dst_ctx_i->device); + if (src_physical == dst_physical) { + CUDA_CHECK(cudaMemcpyAsync(dsts[i]->data, srcs[i]->data, ggml_nbytes(srcs[i]), cudaMemcpyDeviceToDevice, cudaStreamPerThread)); + } else { +#ifdef GGML_CUDA_NO_PEER_COPY + GGML_ABORT("peer copy not supported"); +#else + CUDA_CHECK(cudaMemcpyPeerAsync(dsts[i]->data, dst_physical, srcs[i]->data, src_physical, ggml_nbytes(srcs[i]), cudaStreamPerThread)); +#endif + } + } + + CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); + return true; +} + static void ggml_backend_cuda_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { ggml_backend_cuda_buffer_context * ctx = (ggml_backend_cuda_buffer_context *)buffer->context; @@ -1014,6 +1106,9 @@ static const ggml_backend_buffer_i ggml_backend_cuda_buffer_interface = { /* .cpy_tensor = */ ggml_backend_cuda_buffer_cpy_tensor, /* .clear = */ ggml_backend_cuda_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ ggml_backend_cuda_buffer_set_tensor_n, + /* .get_tensor_n = */ ggml_backend_cuda_buffer_get_tensor_n, + /* .cpy_tensor_n = */ ggml_backend_cuda_buffer_cpy_tensor_n, }; // cuda buffer type @@ -1465,6 +1560,12 @@ static ggml_backend_buffer_t ggml_backend_cuda_host_buffer_type_alloc_buffer(ggm return buffer; } +static size_t ggml_backend_cuda_host_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) { + GGML_UNUSED(buft); + // very large pinned allocations can fail (e.g. on Windows) and fall back to pageable memory, smaller ones succeed + return 4ull*1024*1024*1024; +} + ggml_backend_buffer_type_t ggml_backend_cuda_host_buffer_type() { static struct ggml_backend_buffer_type ggml_backend_cuda_buffer_type_host = { /* .iface = */ { @@ -1472,7 +1573,7 @@ ggml_backend_buffer_type_t ggml_backend_cuda_host_buffer_type() { /* .alloc_buffer = */ ggml_backend_cuda_host_buffer_type_alloc_buffer, /* .alloc_buffer_n = */ NULL, /* .get_alignment = */ ggml_backend_cpu_buffer_type()->iface.get_alignment, - /* .get_max_size = */ NULL, // defaults to SIZE_MAX + /* .get_max_size = */ ggml_backend_cuda_host_buffer_type_get_max_size, /* .get_alloc_size = */ ggml_backend_cpu_buffer_type()->iface.get_alloc_size, /* .get_alloc_size_n = */ NULL, /* .is_host = */ ggml_backend_cpu_buffer_type()->iface.is_host, @@ -1672,7 +1773,7 @@ static void ggml_cuda_mul_mat_cublas_impl(ggml_backend_cuda_context & ctx, const if (compute_type == GGML_TYPE_F16) { prefer_f32_output = cc == GGML_CUDA_CC_VOLTA || GGML_CUDA_CC_IS_RDNA4(cc) || GGML_CUDA_CC_IS_CDNA(cc); } else if (compute_type == GGML_TYPE_BF16) { - prefer_f32_output = !GGML_CUDA_CC_IS_RDNA3(cc) && !GGML_CUDA_CC_IS_CDNA(cc); + prefer_f32_output = !GGML_CUDA_CC_IS_RDNA3(cc) && !GGML_CUDA_CC_IS_RDNA4_M(cc) && !GGML_CUDA_CC_IS_CDNA(cc); } if (prefer_f32_output) { @@ -2078,6 +2179,67 @@ static bool ggml_cuda_match_shared_expert(const ggml_cgraph * graph, int routed_ return true; } +// Buffer- and batch-size independent, so graph_optimize produces the same graph topology for every ubatch size (see #29986). +static bool ggml_cuda_mul_mat_q_fusion_matches(const ggml_tensor * up, const ggml_tensor * gate, const ggml_tensor * glu, const int device) { + const ggml_tensor * x_up = up->src[0]; + const ggml_tensor * y = up->src[1]; + + if ((up->op != GGML_OP_MUL_MAT && up->op != GGML_OP_MUL_MAT_ID) || !ggml_cuda_mmq_fusion_supported(x_up->type) || y->type != GGML_TYPE_F32) { + return false; + } + + // The fused kernel is only compiled for weights whose rows fill whole tiles (no fallback). + if (ggml_cuda_mmq_needs_fallback(x_up->ne[1], ggml_cuda_info().devices[device].cc)) { + return false; + } + + if (!ggml_cuda_should_fuse_mul_mat(up, gate, glu)) { + return false; + } + + // The fused write-back applies SWIGLU_OAI with the default alpha and limit of ggml_cuda_op_swiglu_oai_single. + if (ggml_get_glu_op(glu) == GGML_GLU_OP_SWIGLU_OAI && (ggml_get_op_params_f32(glu, 2) != 1.702f || ggml_get_op_params_f32(glu, 3) != 7.0f)) { + return false; + } + + // NVIDIA only: the fused write-back relies on the MMA accumulator layout. + return turing_mma_available(ggml_cuda_info().devices[device].cc); +} + +static bool ggml_cuda_should_fuse_mul_mat_q(const ggml_tensor * up, const ggml_tensor * gate, const ggml_tensor * glu) { + // A hinted matmul can be fused, but its unfused path may be faster (e.g. FWHT for GGML_HINT_SRC0_IS_HADAMARD). + if (ggml_get_op_params_i32(up, 1) != GGML_HINT_NONE || ggml_get_op_params_i32(gate, 1) != GGML_HINT_NONE) { + return false; + } + + // The padding of a compute-buffer weight that is a view cannot be cleared, see ggml_cuda_mul_mat. + const auto bad_padding_clear = [](const ggml_tensor * x) { + return ggml_backend_buffer_get_usage(x->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE && + ggml_nbytes(x) != ggml_backend_buffer_get_alloc_size(x->buffer, x) && x->view_src; + }; + const int device = ggml_cuda_get_device(); + if (!ggml_cuda_mul_mat_q_fusion_matches(up, gate, glu, device) || bad_padding_clear(up->src[0]) || bad_padding_clear(gate->src[0])) { + return false; + } + + // The batch size checks are done here, not in ggml_cuda_mul_mat_q_fusion_matches. + const ggml_tensor * x_up = up->src[0]; + const ggml_tensor * y = up->src[1]; + const int cc = ggml_cuda_info().devices[device].cc; + + // For MUL_MAT_ID: same kernel choice as ggml_cuda_mul_mat_id, with the nominal tiles of all experts (the per-expert token counts are only known on the GPU). + const bool is_id = up->op == GGML_OP_MUL_MAT_ID; + const int64_t ncols = is_id ? y->ne[2] : y->ne[1]; + const int64_t nchannels = is_id ? x_up->ne[2] : y->ne[2]*y->ne[3]; + const bool use_mmvq = is_id ? ncols <= get_mmvq_mmid_max_batch(x_up->type, cc) : ggml_cuda_should_use_mmvq(x_up->type, cc, ncols); + if (use_mmvq || !ggml_cuda_should_use_mmq(x_up->type, cc, ncols, /*n_experts =*/ is_id ? x_up->ne[2] : 0)) { + return false; + } + + // The fused kernel needs one block per tile (no stream-k split), so only fuse if the tiling is efficient. + return ggml_cuda_mmq_fusion_is_efficient(x_up->type, x_up->ne[1], ncols, nchannels, device); +} + static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_TENSOR_BINARY_OP_LOCALS @@ -2147,6 +2309,8 @@ static bool ggml_cuda_mul_mat_id_needs_sync(const ggml_tensor * dst, const int c const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; + const int warp_size = ggml_cuda_info().devices[ggml_cuda_get_device()].warp_size; + if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { return true; } @@ -2165,7 +2329,7 @@ static bool ggml_cuda_mul_mat_id_needs_sync(const ggml_tensor * dst, const int c return false; } - if (ggml_cuda_should_use_mmf(src0->type, cc, WARP_SIZE, src0->ne, src0->nb, src1->ne[2], /*mul_mat_id=*/true)) { + if (ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src0->nb, src1->ne[2], /*mul_mat_id=*/true)) { return false; } @@ -2183,6 +2347,7 @@ static void ggml_cuda_mul_mat_id(ggml_backend_cuda_context & ctx, ggml_tensor * GGML_TENSOR_BINARY_OP_LOCALS const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + const int warp_size = ggml_cuda_info().devices[ggml_cuda_get_device()].warp_size; // [TAG_MUL_MAT_ID_CUDA_GRAPHS] if (src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32) { @@ -2207,7 +2372,7 @@ static void ggml_cuda_mul_mat_id(ggml_backend_cuda_context & ctx, ggml_tensor * return; } - if (ggml_cuda_should_use_mmf(src0->type, cc, WARP_SIZE, src0->ne, src0->nb, src1->ne[2], /*mul_mat_id=*/true)) { + if (ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src0->nb, src1->ne[2], /*mul_mat_id=*/true)) { ggml_cuda_mul_mat_f(ctx, src0, src1, ids, dst); return; } @@ -2681,6 +2846,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_OP_LIGHTNING_INDEXER: ggml_cuda_lightning_indexer(ctx, dst); break; + case GGML_OP_TOP_K_MASK: + ggml_cuda_op_top_k_mask(ctx, dst); + break; default: return false; } @@ -2910,16 +3078,14 @@ static bool ggml_cuda_graph_update_required(ggml_backend_cuda_context * cuda_ctx return res; } -static void ggml_cuda_graph_update_executable(ggml_backend_cuda_context * cuda_ctx, const void * graph_key) { - ggml_cuda_graph * graph = cuda_ctx->cuda_graph(graph_key); - +static void ggml_cuda_graph_update_executable(cudaGraphExec_t & instance, cudaGraph_t cuda_graph) { #if CUDART_VERSION >= 12000 cudaGraphExecUpdateResultInfo result_info; - cudaError_t stat = cudaGraphExecUpdate(graph->instance, graph->graph, &result_info); + cudaError_t stat = cudaGraphExecUpdate(instance, cuda_graph, &result_info); #else cudaGraphNode_t errorNode; cudaGraphExecUpdateResult result_info; - cudaError_t stat = cudaGraphExecUpdate(graph->instance, graph->graph, &errorNode, &result_info); + cudaError_t stat = cudaGraphExecUpdate(instance, cuda_graph, &errorNode, &result_info); #endif // CUDART_VERSION >= 12000 if (stat == cudaErrorGraphExecUpdateFailure) { @@ -2930,13 +3096,39 @@ static void ggml_cuda_graph_update_executable(ggml_backend_cuda_context * cuda_c // The pre-existing graph exec cannot be updated due to violated constraints // so instead clear error and re-instantiate (void)cudaGetLastError(); - CUDA_CHECK(cudaGraphExecDestroy(graph->instance)); - graph->instance = nullptr; - CUDA_CHECK(cudaGraphInstantiate(&graph->instance, graph->graph, NULL, NULL, 0)); + CUDA_CHECK(cudaGraphExecDestroy(instance)); + instance = nullptr; + CUDA_CHECK(cudaGraphInstantiate(&instance, cuda_graph, nullptr, nullptr, 0)); } else { GGML_ASSERT(stat == cudaSuccess); } } + +// number of ggml nodes per CUDA graph chunk, 0 captures the whole ggml graph as one CUDA graph +static int ggml_cuda_graph_chunk_size() { + static const int chunk_size = [] { + const char * env = getenv("GGML_CUDA_GRAPH_CHUNK_SIZE"); + return env != nullptr ? atoi(env) : 512; + }(); + return chunk_size; +} + +// end the capture of chunk `idx`, update or create its executable and launch it +static void ggml_cuda_graph_launch_chunk(ggml_backend_cuda_context * cuda_ctx, ggml_cuda_graph * graph, size_t idx) { + cudaGraph_t cuda_graph = nullptr; + CUDA_CHECK(cudaStreamEndCapture(cuda_ctx->stream(), &cuda_graph)); + + if (idx < graph->instances.size()) { + ggml_cuda_graph_update_executable(graph->instances[idx], cuda_graph); + } else { + GGML_ASSERT(idx == graph->instances.size()); + graph->instances.emplace_back(nullptr); + CUDA_CHECK(cudaGraphInstantiate(&graph->instances[idx], cuda_graph, nullptr, nullptr, 0)); + } + CUDA_CHECK(cudaGraphDestroy(cuda_graph)); + + CUDA_CHECK(cudaGraphLaunch(graph->instances[idx], cuda_ctx->stream())); +} #endif // USE_CUDA_GRAPH static bool ggml_cuda_should_fuse_rope_set_rows(const ggml_tensor * rope, @@ -2964,9 +3156,10 @@ static bool ggml_cuda_should_fuse_rope_set_rows(const ggml_tensor * rope, return false; } - // Only norm/neox shaders have the fusion code + // Only norm/neox/multi shaders have the fusion code const int mode = ((const int32_t *) rope->op_params)[2]; - if (mode != GGML_ROPE_TYPE_NORMAL && mode != GGML_ROPE_TYPE_NEOX) { + if (mode != GGML_ROPE_TYPE_NORMAL && mode != GGML_ROPE_TYPE_NEOX && + mode != GGML_ROPE_TYPE_MROPE && mode != GGML_ROPE_TYPE_IMROPE) { return false; } @@ -3162,6 +3355,65 @@ static int ggml_cuda_try_ssm_scan_cache_fusion( return skip; } +// expert group selection from build_moe_ffn (n_expert_groups > 1) +// src0/src1 index into this table, -1 is the (biased) probs, -2 is not checked +static const struct { + ggml_op op; + int src0; + int src1; +} topk_moe_group_pattern[] = { + { GGML_OP_RESHAPE, -1, -2 }, // 0: [n_exp_per_group, n_expert_groups, n_tokens] + { GGML_OP_RESHAPE, 0, -2 }, // 1: [1, n_exp_per_group, n_expert_groups, n_tokens] + { GGML_OP_ARGSORT, 0, -2 }, // 2 + { GGML_OP_VIEW, 2, -2 }, // 3: top-2 per group + { GGML_OP_GET_ROWS, 1, 3 }, // 4 + { GGML_OP_RESHAPE, 4, -2 }, // 5 + { GGML_OP_SUM_ROWS, 5, -2 }, // 6: group scores + { GGML_OP_RESHAPE, 6, -2 }, // 7 + { GGML_OP_ARGSORT, 7, -2 }, // 8 + { GGML_OP_VIEW, 8, -2 }, // 9: top n_group_used groups + { GGML_OP_GET_ROWS, 0, 9 }, // 10 + { GGML_OP_FILL, 0, -2 }, // 11 + { GGML_OP_SET_ROWS, 10, 9 }, // 12: unused groups -> -inf + { GGML_OP_RESHAPE, 12, -2 }, // 13: [n_expert, n_tokens] +}; + +static bool ggml_cuda_topk_moe_group_fusion(const struct ggml_cgraph * cgraph, int node_idx, const ggml_tensor * selection, ggml_cuda_topk_moe_args & args) { +#if defined(GGML_USE_HIP) && HIP_VERSION < 60300000 + GGML_UNUSED_VARS(cgraph, node_idx, selection, args); + return false; +#else + const int n_ops = (int) std::size(topk_moe_group_pattern); + if (node_idx + n_ops > cgraph->n_nodes) { + return false; + } + + ggml_tensor ** nodes = cgraph->nodes + node_idx; + auto src_ok = [&](const ggml_tensor * src, int idx) { + return idx == -2 || src == (idx == -1 ? selection : nodes[idx]); + }; + + for (int i = 0; i < n_ops; i++) { + const auto & p = topk_moe_group_pattern[i]; + if (nodes[i]->op != p.op || !src_ok(nodes[i]->src[0], p.src0) || !src_ok(nodes[i]->src[1], p.src1)) { + return false; + } + } + + const int n_groups = nodes[0]->ne[1]; + const int n_group_used = nodes[9]->ne[0]; + + if (nodes[3]->ne[0] != 2 || nodes[12]->src[2] != nodes[11] || ggml_get_op_params_f32(nodes[11], 0) != -INFINITY || + n_groups > WARP_SIZE) { + return false; + } + + args.n_groups = n_groups; + args.n_group_used = n_group_used; + return true; +#endif // defined(GGML_USE_HIP) && HIP_VERSION < 60300000 +} + static bool ggml_cuda_topk_moe_fusion(const struct ggml_cgraph * cgraph, int node_idx, ggml_cuda_topk_moe_args & args) { args.sigmoid = false; args.sqrt_softplus = false; @@ -3169,6 +3421,8 @@ static bool ggml_cuda_topk_moe_fusion(const struct ggml_cgraph * cgraph, int nod args.delayed_softmax = false; args.prob_bias = false; args.norm = false; + args.n_groups = 0; + args.n_group_used = 0; const int n_nodes = cgraph->n_nodes; ggml_tensor ** nodes = cgraph->nodes; @@ -3211,18 +3465,20 @@ static bool ggml_cuda_topk_moe_fusion(const struct ggml_cgraph * cgraph, int nod } // src of bias add is the unreshaped probs (-2 instead of -1) - if (nodes[node_idx]->op == GGML_OP_ADD && nodes[node_idx]->src[0] == nodes[node_idx - 2]) { + const ggml_tensor * selection = nodes[node_idx - 2]; + if (nodes[node_idx]->op == GGML_OP_ADD && nodes[node_idx]->src[0] == selection) { args.prob_bias = true; + selection = nodes[node_idx]; node_idx++; } - // RESHAPE/ADD -> ARGSORT - if (node_idx >= n_nodes || nodes[node_idx]->op != GGML_OP_ARGSORT) { - return false; + + if (ggml_cuda_topk_moe_group_fusion(cgraph, node_idx, selection, args)) { + node_idx += (int) std::size(topk_moe_group_pattern); + selection = nodes[node_idx - 1]; } - if (args.prob_bias && nodes[node_idx]->src[0] != nodes[node_idx - 1]) { - return false; - } else if (!args.prob_bias && nodes[node_idx]->src[0] != nodes[node_idx - 2]) { + // RESHAPE/ADD/group mask -> ARGSORT + if (node_idx >= n_nodes || nodes[node_idx]->op != GGML_OP_ARGSORT || nodes[node_idx]->src[0] != selection) { return false; } @@ -3233,6 +3489,11 @@ static bool ggml_cuda_topk_moe_fusion(const struct ggml_cgraph * cgraph, int nod nodes[node_idx]->src[0] != nodes[node_idx - 1]) { return false; } + + // kept groups must hold all used experts + if (args.n_groups > 0 && nodes[node_idx]->ne[0] > args.n_group_used * (probs_reshaped->ne[1] / args.n_groups)) { + return false; + } node_idx++; if (node_idx >= n_nodes || nodes[node_idx]->op != GGML_OP_GET_ROWS) { @@ -3615,6 +3876,26 @@ static bool ggml_cuda_can_fuse(const struct ggml_cgraph * cgraph, } } + // scale_out*sigmoid(scale_in*post) as the hc_post weights (qwen4exp hc_combine) + std::initializer_list hc_post_gate_ops = { GGML_OP_SCALE, GGML_OP_UNARY, GGML_OP_SCALE, GGML_OP_DSV4_HC_POST }; + + if (is_equal(hc_post_gate_ops, ops) && ggml_can_fuse_subgraph(cgraph, node_idx, ops, { node_idx + 3 })) { + const ggml_tensor * scale_in = cgraph->nodes[node_idx]; + const ggml_tensor * sigmoid = cgraph->nodes[node_idx + 1]; + const ggml_tensor * scale_out = cgraph->nodes[node_idx + 2]; + + // the chain must feed hc_post->src[2]; a bias on either scale is not handled + if (ggml_check_edges(cgraph, node_idx, {{1, 0, 0}, {2, 0, 1}, {3, 2, 2}}) && + ggml_get_unary_op(sigmoid) == GGML_UNARY_OP_SIGMOID && + ggml_get_op_params_f32(scale_in, 1) == 0.0f && ggml_get_op_params_f32(scale_out, 1) == 0.0f && + scale_in->src[0]->type == GGML_TYPE_F32 && scale_out->type == GGML_TYPE_F32 && + ggml_are_same_shape(scale_in->src[0], scale_out)) { + int out_nodes[] = { node_idx + 3 }; + return ggml_cuda_check_fusion_memory_ranges(cgraph, node_idx, (int)ops.size(), out_nodes, 1); + } + return false; + } + if (!ggml_can_fuse(cgraph, node_idx, ops)) { return false; } @@ -3777,6 +4058,11 @@ static bool ggml_cuda_can_fuse(const struct ggml_cgraph * cgraph, return false; } + // TODO: make the fused softcap kernel stride aware, it reads src and writes dst as dense + if (!ggml_is_contiguous(scale->src[0]) || !ggml_is_contiguous(scale2)) { + return false; + } + if (ggml_get_unary_op(tanh) != GGML_UNARY_OP_TANH) { return false; } @@ -3887,17 +4173,18 @@ static int ggml_cuda_try_fuse(ggml_backend_cuda_context * cuda_ctx, ggml_cgraph } else { ops.insert(ops.end(), { GGML_OP_SOFT_MAX }); } - const int i_probs = i + (int) ops.size() - 1; // last node of the gating activation - + ops.push_back(GGML_OP_RESHAPE); if (args.prob_bias) { - bias = cgraph->nodes[i_probs + 2]->src[1]; - ops.insert(ops.end(), { GGML_OP_RESHAPE, GGML_OP_ADD, GGML_OP_ARGSORT, GGML_OP_VIEW, - GGML_OP_GET_ROWS }); - out_nodes[0] = i_probs + 4; - } else { - ops.insert(ops.end(), { GGML_OP_RESHAPE, GGML_OP_ARGSORT, GGML_OP_VIEW, GGML_OP_GET_ROWS }); - out_nodes[0] = i_probs + 3; + ops.push_back(GGML_OP_ADD); + bias = cgraph->nodes[i + ops.size() - 1]->src[1]; + } + if (args.n_groups > 0) { + for (const auto & p : topk_moe_group_pattern) { + ops.push_back(p.op); + } } + ops.insert(ops.end(), { GGML_OP_ARGSORT, GGML_OP_VIEW, GGML_OP_GET_ROWS }); + out_nodes[0] = i + ops.size() - 2; ids = cgraph->nodes[out_nodes[0]]; if (args.norm) { @@ -4373,6 +4660,18 @@ static int ggml_cuda_try_fuse(ggml_backend_cuda_context * cuda_ctx, ggml_cgraph fused_node_count = 3; break; } + + if (ggml_cuda_should_fuse_mul_mat_q(up, gate, glu)) { + ggml_cuda_mm_fusion_args_host fusion_data{}; + fusion_data.gate = gate->src[0]; + fusion_data.glu_op = ggml_get_glu_op(glu); + fusion_data.glu_limit = ggml_get_op_params_f32(glu, 3); + + ggml_cuda_mul_mat_q(*cuda_ctx, src0, src1, ids, glu, &fusion_data); + fused_mul_mat_vec = true; + fused_node_count = 3; + break; + } } } @@ -4579,6 +4878,11 @@ static int ggml_cuda_try_fuse(ggml_backend_cuda_context * cuda_ctx, ggml_cgraph return 1; } + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_SCALE, GGML_OP_UNARY, GGML_OP_SCALE, GGML_OP_DSV4_HC_POST }, { GGML_UNARY_OP_SIGMOID })) { + ggml_cuda_op_dsv4_hc_post(*cuda_ctx, cgraph->nodes[i + 3], node, cgraph->nodes[i + 2]); + return 3; + } + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_SCALE, GGML_OP_UNARY, GGML_OP_SCALE }, { GGML_UNARY_OP_TANH })) { ggml_cuda_op_softcap(*cuda_ctx, cgraph->nodes[i + 2], node); return 2; @@ -4598,6 +4902,13 @@ static void ggml_cuda_graph_evaluate_and_capture(ggml_backend_cuda_context * cud ggml_cuda_concurrent_event * concurrent_event = nullptr; bool should_launch_concurrent_events = false; +#ifdef USE_CUDA_GRAPH + ggml_cuda_graph * graph = use_cuda_graph ? cuda_ctx->cuda_graph(graph_key) : nullptr; + const int chunk_size = ggml_cuda_graph_chunk_size(); + int chunk_end = chunk_size; + size_t n_chunks = 0; +#endif // USE_CUDA_GRAPH + const auto try_launch_concurrent_event = [&](const ggml_tensor * node) { if (stream_ctx.concurrent_events.find(node) != stream_ctx.concurrent_events.end()) { concurrent_event = &stream_ctx.concurrent_events[node]; @@ -4697,6 +5008,15 @@ static void ggml_cuda_graph_evaluate_and_capture(ggml_backend_cuda_context * cud for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; +#ifdef USE_CUDA_GRAPH + // fused nodes are skipped together, so a cut never splits a fusion + // a concurrent region must join before its capture can end + if (use_cuda_graph && chunk_size > 0 && i >= chunk_end && !is_concurrent_event_active) { + ggml_cuda_graph_launch_chunk(cuda_ctx, graph, n_chunks++); + CUDA_CHECK(cudaStreamBeginCapture(cuda_ctx->stream(), cudaStreamCaptureModeRelaxed)); + chunk_end = i + chunk_size; + } +#endif // USE_CUDA_GRAPH if (is_concurrent_event_active) { GGML_ASSERT(concurrent_event); @@ -4822,14 +5142,14 @@ static void ggml_cuda_graph_evaluate_and_capture(ggml_backend_cuda_context * cud } #ifdef USE_CUDA_GRAPH - ggml_cuda_graph * graph = cuda_ctx->cuda_graph(graph_key); if (use_cuda_graph && cuda_graph_update_required) { // End CUDA graph capture - if (graph->graph != nullptr) { - CUDA_CHECK(cudaGraphDestroy(graph->graph)); - graph->graph = nullptr; - } + ggml_cuda_graph_launch_chunk(cuda_ctx, graph, n_chunks++); - CUDA_CHECK(cudaStreamEndCapture(cuda_ctx->stream(), &graph->graph)); + // drop the chunks left over from a longer graph + for (size_t i = n_chunks; i < graph->instances.size(); ++i) { + CUDA_CHECK(cudaGraphExecDestroy(graph->instances[i])); + } + graph->instances.resize(n_chunks); graph_evaluated_or_captured = true; // CUDA graph has been captured std::lock_guard lock(ggml_cuda_lock); @@ -4841,16 +5161,11 @@ static void ggml_cuda_graph_evaluate_and_capture(ggml_backend_cuda_context * cud } } - if (use_cuda_graph) { - ggml_cuda_graph * graph = cuda_ctx->cuda_graph(graph_key); - if (graph->instance == nullptr) { // Create executable graph from captured graph. - CUDA_CHECK(cudaGraphInstantiate(&graph->instance, graph->graph, NULL, NULL, 0)); - } - if (cuda_graph_update_required) { // Update graph executable - ggml_cuda_graph_update_executable(cuda_ctx, graph_key); + if (use_cuda_graph && !cuda_graph_update_required) { + // the chunks were launched during capture, otherwise launch them here + for (cudaGraphExec_t instance : graph->instances) { + CUDA_CHECK(cudaGraphLaunch(instance, cuda_ctx->stream())); } - // Launch graph - CUDA_CHECK(cudaGraphLaunch(graph->instance, cuda_ctx->stream())); #else GGML_UNUSED(graph_key); graph_evaluated_or_captured = true; @@ -4862,7 +5177,7 @@ static void ggml_cuda_graph_evaluate_and_capture(ggml_backend_cuda_context * cud static bool ggml_cuda_graph_set_enabled(ggml_backend_cuda_context * cuda_ctx, const void * graph_key) { ggml_cuda_graph * graph = cuda_ctx->cuda_graph(graph_key); - if (graph->graph == nullptr) { + if (graph->instances.empty()) { if (ggml_cuda_info().devices[cuda_ctx->device].cc < GGML_CUDA_CC_VOLTA) { if (!graph->disable_due_to_gpu_arch && ggml_cuda_graph_debug_enabled()) { GGML_LOG_DEBUG("%s: disabling CUDA graphs due to GPU architecture\n", __func__); @@ -4916,7 +5231,7 @@ static enum ggml_status ggml_backend_cuda_graph_compute(ggml_backend_t backend, } } else { use_cuda_graph = true; - cuda_graph_update_required = graph->instance == nullptr; + cuda_graph_update_required = graph->instances.empty(); } } } @@ -5006,6 +5321,19 @@ static void ggml_backend_cuda_graph_optimize(ggml_backend_t backend, ggml_cgraph } } for (int i = 0; i < cgraph->n_nodes; ++i) { + // Keep the inputs of the fused gate/up/GLU MMQ kernel alive until the GLU so that they cannot alias its output (under op offload the weights are buffer copies). + if (i + 2 < cgraph->n_nodes && cgraph->nodes[i + 2]->op == GGML_OP_GLU) { + ggml_tensor * glu = cgraph->nodes[i + 2]; + ggml_tensor * gate = glu->src[0]; + ggml_tensor * up = glu->src[1]; + const bool ok = (gate == cgraph->nodes[i] && up == cgraph->nodes[i + 1]) || (gate == cgraph->nodes[i + 1] && up == cgraph->nodes[i]); + if (ok && ggml_cuda_mul_mat_q_fusion_matches(up, gate, glu, cuda_ctx->device)) { + add_alloc_deps(i, i + 2); + i += 2; + continue; + } + } + ggml_cuda_moe_weighted_reduction_match match; if (ggml_cuda_match_moe_weighted_reduction(cgraph, i, match)) { params->add_alloc_dep(params->user_data, const_cast(match.experts), match.dst); @@ -5818,6 +6146,9 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g (ggml_get_glu_op(op) == GGML_GLU_OP_SWIGLU_OAI || ggml_get_glu_op(op) == GGML_GLU_OP_SWIGLU_CLAMP)) { return false; } + if (op->src[0]->type == GGML_TYPE_F16 && ggml_get_glu_op(op) == GGML_GLU_OP_SWIGLU_OAI) { + return false; + } return ggml_is_contiguous_1(op->src[0]); default: return false; @@ -6094,7 +6425,8 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_OP_LOG: return true; case GGML_OP_SCALE: - return (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_BF16) && op->type == op->src[0]->type; + return (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_BF16) && op->type == op->src[0]->type && + ggml_is_contiguous_rows(op->src[0]); case GGML_OP_CLAMP: return ggml_is_contiguous_rows(op->src[0]); case GGML_OP_ADD: @@ -6172,7 +6504,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g //return ggml_is_contiguous_rows(op->src[0]) && ggml_is_contiguous_rows(op->src[1]); return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); case GGML_OP_SUM: - return ggml_is_contiguous_rows(op->src[0]); + return ggml_is_contiguously_allocated(op->src[0]); case GGML_OP_TOP_K: return op->src[0]->ne[0] <= INT_MAX; case GGML_OP_ARGSORT: @@ -6231,6 +6563,8 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g return true; case GGML_OP_LIGHTNING_INDEXER: return ggml_cuda_lightning_indexer_supported(dev_ctx->device, op); + case GGML_OP_TOP_K_MASK: + return op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32; default: return false; diff --git a/ggml/src/ggml-cuda/mma.cuh b/ggml/src/ggml-cuda/mma.cuh index 1cec98b06ef9..524db9d8512b 100644 --- a/ggml/src/ggml-cuda/mma.cuh +++ b/ggml/src/ggml-cuda/mma.cuh @@ -76,11 +76,11 @@ namespace ggml_cuda_mma { // For the A/C matrices this means I major == row major, J major == column major. // For the B matrix this means I major == column major, J major == row major. // MIRRORED == Each data value is held exactly once per thread subgroup. - DATA_LAYOUT_I_MAJOR = 0, // Always used for Turing, Ampere, Ada Lovelace, consumer Blackwell, matrix A&B for RDNA4 and CDNA. - DATA_LAYOUT_J_MAJOR = 10, // Matrix C for CDNA and RDNA4, int and float matrix C for RDNA3. + DATA_LAYOUT_I_MAJOR = 0, // Always used for Turing, Ampere, Ada Lovelace, consumer Blackwell, matrix A&B for WMMA128 and CDNA. + DATA_LAYOUT_J_MAJOR = 10, // Matrix C for CDNA and WMMA128, int and float matrix C for WMMA256. DATA_LAYOUT_I_MAJOR_MIRRORED = 20, // Volta, matrix A&B for RDNA3. DATA_LAYOUT_J_MAJOR_MIRRORED = 30, - DATA_LAYOUT_I_MAJOR_SCRAMBLED = 40, // Scrambled matrix C for faster transposition (RDNA4/CDNA), convert to float to unscramble. + DATA_LAYOUT_I_MAJOR_SCRAMBLED = 40, // Scrambled matrix C for faster transposition (WMMA128/CDNA), convert to float to unscramble. }; // Implemented mma combinations are: // - (I_MAJOR, I_MAJOR) -> I_MAJOR @@ -88,11 +88,11 @@ namespace ggml_cuda_mma { // - (I_MAJOR, J_MAJOR_MIRRORED) -> I_MAJOR static constexpr __device__ data_layout get_input_data_layout() { -#if defined(RDNA3) || defined(VOLTA_MMA_AVAILABLE) +#if defined(AMD_WMMA_256B_AVAILABLE) || defined(VOLTA_MMA_AVAILABLE) return DATA_LAYOUT_I_MAJOR_MIRRORED; #else return DATA_LAYOUT_I_MAJOR; -#endif // defined(RDNA3) || defined(VOLTA_MMA_AVAILABLE) +#endif // defined(AMD_WMMA_256B_AVAILABLE) || defined(VOLTA_MMA_AVAILABLE) } template @@ -201,7 +201,7 @@ namespace ggml_cuda_mma { static __device__ __forceinline__ int get_j(const int l) { if constexpr (I == 16 && J == 16) { -#if defined(RDNA3) +#if defined(AMD_WMMA_256B_AVAILABLE) if constexpr (std::is_same_v || std::is_same_v) { // matrix C return 2 * l + (threadIdx.x / 16); @@ -210,11 +210,11 @@ namespace ggml_cuda_mma { return l; } #else - // matrix C is the transposed matrix A&B on RDNA4 + // matrix C is the transposed matrix A&B on WMMA128 return ne * (threadIdx.x / 16) + l; -#endif // defined(RDNA3) +#endif // defined(AMD_WMMA_256B_AVAILABLE) } else if constexpr (I == 16 && J == 8) { - // mmq input for RDNA4 + // mmq input for WMMA128 return ne * (threadIdx.x / 16) + l; } else if constexpr (I == 16 && J == 4) { return ne * (threadIdx.x / 16) + l; @@ -573,7 +573,7 @@ namespace ggml_cuda_mma { static constexpr int I = I_; static constexpr int J = J_; static constexpr data_layout dl = DATA_LAYOUT_I_MAJOR_MIRRORED; -#if defined(RDNA3) +#if defined(AMD_WMMA_256B_AVAILABLE) static constexpr int ne = tile::ne; half2 x[ne] = {{0.0f, 0.0f}}; @@ -616,7 +616,7 @@ namespace ggml_cuda_mma { return -1; } } -#endif // defined(RDNA3) +#endif // defined(AMD_WMMA_256B_AVAILABLE) }; template @@ -694,7 +694,7 @@ namespace ggml_cuda_mma { }; static __device__ __forceinline__ tile<16, 16, half2, DATA_LAYOUT_I_MAJOR> unscramble(const tile<16, 16, half2, DATA_LAYOUT_I_MAJOR_SCRAMBLED> & t) { -#if defined(AMD_MFMA_AVAILABLE) || (defined(AMD_WMMA_AVAILABLE) && defined(RDNA4)) +#if defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_128B_AVAILABLE) tile<16, 16, half2, DATA_LAYOUT_I_MAJOR> ret; #pragma unroll for (int l0 = 0; l0 < t.ne/2; ++l0) { @@ -705,7 +705,7 @@ namespace ggml_cuda_mma { #else NO_DEVICE_CODE; GGML_UNUSED(t); -#endif // defined(AMD_MFMA_AVAILABLE) || (defined(AMD_WMMA_AVAILABLE) && defined(RDNA4)) +#endif // defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_128B_AVAILABLE) } #if defined(TURING_MMA_AVAILABLE) @@ -726,7 +726,7 @@ namespace ggml_cuda_mma { return ret; } -#elif defined(AMD_WMMA_AVAILABLE) && defined(RDNA3) +#elif defined(AMD_WMMA_256B_AVAILABLE) static __device__ __forceinline__ tile<16, 8, half2, DATA_LAYOUT_I_MAJOR_MIRRORED> get_half2( const tile<16, 16, float, DATA_LAYOUT_I_MAJOR> & tile_float) { tile<16, 8, half2, DATA_LAYOUT_I_MAJOR_MIRRORED> ret; @@ -1171,7 +1171,7 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[3])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #elif defined(AMD_WMMA_AVAILABLE) -#if defined(RDNA4) +#if defined(AMD_WMMA_128B_AVAILABLE) using halfx8_t = __attribute__((ext_vector_type(8))) _Float16; halfx8_t& acc_frag = reinterpret_cast(D.x[0]); const halfx8_t& a_frag = reinterpret_cast(A.x[0]); @@ -1180,7 +1180,7 @@ namespace ggml_cuda_mma { #else GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // defined(RDNA4) +#endif // defined(AMD_WMMA_128B_AVAILABLE) #elif defined(AMD_MFMA_AVAILABLE) // MFMA: FP16 input, FP32 accumulate, convert back to half2. using halfx4_t = __attribute__((ext_vector_type(4))) _Float16; @@ -1218,7 +1218,7 @@ namespace ggml_cuda_mma { static __device__ __forceinline__ void mma( tile<16, 16, half2, DATA_LAYOUT_I_MAJOR_SCRAMBLED> & D, const tile<32, 8, half2, DATA_LAYOUT_I_MAJOR> & A, const tile<16, 8, half2, DATA_LAYOUT_I_MAJOR> & B) { -#if defined(AMD_MFMA_AVAILABLE) || (defined(AMD_WMMA_AVAILABLE) && defined(RDNA4)) +#if defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_128B_AVAILABLE) tile<16, 8, half2> * D16 = (tile<16, 8, half2> *) &D; const tile<16, 8, half2> * A16 = (const tile<16, 8, half2> *) &A; mma(D16[0], A16[0], B); @@ -1226,7 +1226,7 @@ namespace ggml_cuda_mma { #else GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) && defined(RDNA4) +#endif // defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_128B_AVAILABLE) } template @@ -1373,14 +1373,14 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[3])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #elif defined(AMD_WMMA_AVAILABLE) -#if defined(RDNA4) +#if defined(AMD_WMMA_128B_AVAILABLE) using halfx8_t = __attribute__((ext_vector_type(8))) _Float16; using floatx8_t = __attribute__((ext_vector_type(8))) float; floatx8_t& acc_frag = reinterpret_cast(D.x[0]); const halfx8_t& a_frag = reinterpret_cast(A.x[0]); const halfx8_t& b_frag = reinterpret_cast(B.x[0]); acc_frag = __builtin_amdgcn_wmma_f32_16x16x16_f16_w32_gfx12(a_frag, b_frag, acc_frag); -#elif defined(RDNA3) +#elif defined(AMD_WMMA_256B_AVAILABLE) using halfx16_t = __attribute__((ext_vector_type(16))) _Float16; using floatx8_t = __attribute__((ext_vector_type(8))) float; floatx8_t& acc_frag = reinterpret_cast(D.x[0]); @@ -1390,7 +1390,7 @@ namespace ggml_cuda_mma { #else GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // RDNA4 +#endif // AMD_WMMA_128B_AVAILABLE #elif defined(AMD_MFMA_AVAILABLE) using halfx4_t = __attribute__((ext_vector_type(4))) _Float16; using floatx4_t = __attribute__((ext_vector_type(4))) float; @@ -1408,15 +1408,15 @@ namespace ggml_cuda_mma { static __device__ __forceinline__ void mma( tile<16, 16, float, dl_d> & D, const tile<16, 8, nv_bfloat162, dl_ab> & A, const tile<16, 8, nv_bfloat162, dl_ab> & B) { #if defined(AMD_WMMA_AVAILABLE) -#if defined(RDNA4) - using bf16x8_t = __attribute__((ext_vector_type(8))) __bf16; +#if defined(AMD_WMMA_128B_AVAILABLE) + using bf16x8_t = __attribute__((ext_vector_type(8))) short; using floatx8_t = __attribute__((ext_vector_type(8))) float; floatx8_t& acc_frag = reinterpret_cast(D.x[0]); const bf16x8_t& a_frag = reinterpret_cast(A.x[0]); const bf16x8_t& b_frag = reinterpret_cast(B.x[0]); acc_frag = __builtin_amdgcn_wmma_f32_16x16x16_bf16_w32_gfx12(a_frag, b_frag, acc_frag); -#elif defined(RDNA3) - using bf16x16_t = __attribute__((ext_vector_type(16))) __bf16; +#elif defined(AMD_WMMA_256B_AVAILABLE) + using bf16x16_t = __attribute__((ext_vector_type(16))) short; using floatx8_t = __attribute__((ext_vector_type(8))) float; floatx8_t& acc_frag = reinterpret_cast(D.x[0]); const bf16x16_t& a_frag = reinterpret_cast(A.x[0]); @@ -1425,7 +1425,7 @@ namespace ggml_cuda_mma { #else GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // defined(RDNA4) +#endif // defined(AMD_WMMA_128B_AVAILABLE) #elif defined(AMD_MFMA_AVAILABLE) using floatx4_t = __attribute__((ext_vector_type(4))) float; floatx4_t& acc_frag = reinterpret_cast(D.x[0]); @@ -1467,19 +1467,19 @@ namespace ggml_cuda_mma { #elif defined(AMD_WMMA_AVAILABLE) using int32x8_t = __attribute__((__vector_size__(8 * sizeof(int)))) int; int32x8_t * acc = (int32x8_t *) D.x; -#if defined(RDNA4) +#if defined(AMD_WMMA_128B_AVAILABLE) using int32x2_t = __attribute__((__vector_size__(2 * sizeof(int)))) int; int32x2_t * a_vec = (int32x2_t *) A.x; int32x2_t * b_vec = (int32x2_t *) B.x; acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32_gfx12(true, a_vec[0], true, b_vec[0], acc[0], true); acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32_gfx12(true, a_vec[1], true, b_vec[1], acc[0], true); -#elif defined(RDNA3) +#elif defined(AMD_WMMA_256B_AVAILABLE) using int32x4_t = __attribute__((__vector_size__(4 * sizeof(int)))) int; int32x4_t * a_vec = (int32x4_t *) A.x; int32x4_t * b_vec = (int32x4_t *) B.x; acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32(true, a_vec[0], true, b_vec[0], acc[0], true); acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32(true, a_vec[1], true, b_vec[1], acc[0], true); -#endif // RDNA4 +#endif // AMD_WMMA_128B_AVAILABLE #else GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; @@ -1556,7 +1556,7 @@ namespace ggml_cuda_mma { static __device__ __forceinline__ void mma( tile<16, 16, half2, DATA_LAYOUT_I_MAJOR> & D, const tile<32, 8, half2, DATA_LAYOUT_I_MAJOR_MIRRORED> & A, const tile<16, 8, half2, DATA_LAYOUT_I_MAJOR_MIRRORED> & B) { -#if defined(AMD_WMMA_AVAILABLE) && defined(RDNA3) +#if defined(AMD_WMMA_256B_AVAILABLE) using halfx16_t = __attribute__((ext_vector_type(16))) _Float16; halfx16_t * xD = (halfx16_t *) D.x; const halfx16_t * xA = (const halfx16_t *) A.x; @@ -1585,17 +1585,17 @@ namespace ggml_cuda_mma { #elif defined(AMD_WMMA_AVAILABLE) using int32x8_t = __attribute__((__vector_size__(8 * sizeof(int)))) int; int32x8_t * acc = (int32x8_t *) D.x; -#if defined(RDNA4) +#if defined(AMD_WMMA_128B_AVAILABLE) using int32x2_t = __attribute__((__vector_size__(2 * sizeof(int)))) int; int32x2_t * a_vec = (int32x2_t *) A.x; int32x2_t * b_vec = (int32x2_t *) B.x; acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32_gfx12(true, a_vec[0], true, b_vec[0], acc[0], false); -#elif defined(RDNA3) +#elif defined(AMD_WMMA_256B_AVAILABLE) using int32x4_t = __attribute__((__vector_size__(4 * sizeof(int)))) int; int32x4_t * a_vec = (int32x4_t *) A.x; int32x4_t * b_vec = (int32x4_t *) B.x; acc[0] = __builtin_amdgcn_wmma_i32_16x16x16_iu8_w32(true, a_vec[0], true, b_vec[0], acc[0], false); -#endif // RDNA4 +#endif // AMD_WMMA_128B_AVAILABLE #else GGML_UNUSED(D); GGML_UNUSED(A); diff --git a/ggml/src/ggml-cuda/mmq-load-tiles.cuh b/ggml/src/ggml-cuda/mmq-load-tiles.cuh index 0dd3a9edf18e..f8505d646956 100644 --- a/ggml/src/ggml-cuda/mmq-load-tiles.cuh +++ b/ggml/src/ggml-cuda/mmq-load-tiles.cuh @@ -5,7 +5,9 @@ #include "mmq.cuh" template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q1_0( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -69,6 +71,25 @@ template static __device__ __forceinline_ for (int j = 0; j < 2; ++j) { const int q = qxi[j]; +#if defined(GGML_USE_HIP) + const uint32_t q_bits = (uint16_t) q; + + // Expand each group of four Q1_0 bits into byte selectors for v_perm_b32. + const uint32_t q0_bits = q_bits >> 0; + const uint32_t q1_bits = q_bits >> 4; + const uint32_t q2_bits = q_bits >> 8; + const uint32_t q3_bits = q_bits >> 12; + + const uint32_t q0_indices = (q0_bits & 0x01) | ((q0_bits & 0x02) << 7) | ((q0_bits & 0x04) << 14) | ((q0_bits & 0x08) << 21); + const uint32_t q1_indices = (q1_bits & 0x01) | ((q1_bits & 0x02) << 7) | ((q1_bits & 0x04) << 14) | ((q1_bits & 0x08) << 21); + const uint32_t q2_indices = (q2_bits & 0x01) | ((q2_bits & 0x02) << 7) | ((q2_bits & 0x04) << 14) | ((q2_bits & 0x08) << 21); + const uint32_t q3_indices = (q3_bits & 0x01) | ((q3_bits & 0x02) << 7) | ((q3_bits & 0x04) << 14) | ((q3_bits & 0x08) << 21); + + const int v0 = ggml_hip_perm(0x000001FF, 0x000001FF, q0_indices); + const int v1 = ggml_hip_perm(0x000001FF, 0x000001FF, q1_indices); + const int v2 = ggml_hip_perm(0x000001FF, 0x000001FF, q2_indices); + const int v3 = ggml_hip_perm(0x000001FF, 0x000001FF, q3_indices); +#else // unpack crumbs into nibble indices const int n0 = __byte_perm(0x11100100, 0x11100100, q >> 0); // [0, 1, 4, 5] [ 8, 9, 12, 13] const int n1 = __byte_perm(0x11100100, 0x11100100, q >> 2); // [2, 3, 6, 7] [10, 11, 14, 15] @@ -82,6 +103,7 @@ template static __device__ __forceinline_ const int v1 = __byte_perm(s0, s1, 0x7632); const int v2 = __byte_perm(s2, s3, 0x5410); const int v3 = __byte_perm(s2, s3, 0x7632); +#endif // defined(GGML_USE_HIP) #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) x_qs[i*sram_stride + dst_offset + j*4+0] = v0; @@ -120,7 +142,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q2_0( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -166,8 +190,8 @@ template static __device__ __forceinline_ const uint32_t qx_indices = (q & 0x03) | ((q & 0x0C) << 6) | ((q & 0x30) << 12) | ((q & 0xC0) << 18); const uint32_t qy_bits = q >> 8; const uint32_t qy_indices = (qy_bits & 0x03) | ((qy_bits & 0x0C) << 6) | ((qy_bits & 0x30) << 12) | ((qy_bits & 0xC0) << 18); - const int qx = __builtin_amdgcn_perm(0x020100FF, 0x020100FF, qx_indices); - const int qy = __builtin_amdgcn_perm(0x020100FF, 0x020100FF, qy_indices); + const int qx = ggml_hip_perm(0x020100FF, 0x020100FF, qx_indices); + const int qy = ggml_hip_perm(0x020100FF, 0x020100FF, qy_indices); #else // unpack even and odd crumbs into byte values const int qe = __byte_perm(0x020100FF, 0x020100FF, q >> 0); @@ -209,7 +233,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q4_0( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -356,7 +382,9 @@ static __device__ __forceinline__ void ggml_cuda_mmq_store_tiles_q4_0_rdna35( #endif // defined(GGML_USE_HIP) && defined(RDNA3_5) template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q4_1( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -419,7 +447,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q5_0( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -499,7 +529,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q5_1( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -576,8 +608,8 @@ template static __device__ __forceinline_ } } -template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q8_0( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { +template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q8_0( + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -607,7 +639,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q8_0 * bxi = (const block_q8_0 *) x + kbx0 + i*stride + kbx; + const block_q8_0 * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride) + kbx; #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) x_qs[i*sram_stride + 0 + txi] = get_int_b2(bxi[0].qs, kqsx); @@ -630,7 +662,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q8_0 * bxi = (const block_q8_0 *) x + kbx0 + i*stride + kbxd; + const block_q8_0 * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride) + kbxd; #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) x_df[i*sram_stride + kbxd] = bxi->d; @@ -726,7 +758,9 @@ static __device__ __forceinline__ void ggml_cuda_mmq_store_tiles_q8_0_rdna35( // --------------------------------------------------------------------------------------------- template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q2_K( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -787,7 +821,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q3_K( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1187,11 +1223,13 @@ static __device__ __forceinline__ void ggml_cuda_mmq_store_tiles_q5_K_rdna35( } #endif -template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q4_K( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { +template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q4_K( + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { #if defined(RDNA3_5) - ggml_cuda_mmq_load_tiles_q4_K_rdna35(x, x_tile, kbx0, i_max, stride); - return; + if constexpr (!has_fusion) { + ggml_cuda_mmq_load_tiles_q4_K_rdna35(x, x_tile, kbx0, i_max, stride); + return; + } #endif constexpr int warp_size = ggml_cuda_get_physical_warp_size(); @@ -1221,7 +1259,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; + const block_q4_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int qs0 = get_int_b4(bxi->qs, txi); #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) @@ -1250,7 +1288,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; + const block_q4_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int * scales = (const int *) bxi->scales; const int ksc = threadIdx.x % 2; @@ -1278,7 +1316,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; + const block_q4_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); x_dm[i] = bxi->dm; } @@ -1291,7 +1329,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / (QI4_K/8); + const block_q4_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride) + (threadIdx.x % (MMQ_TILE_NE_K/8)) / (QI4_K/8); const int * scales = (const int *) bxi->scales; @@ -1303,11 +1341,13 @@ template static __device__ __forceinline_ #endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) } -template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q5_K( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { +template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q5_K( + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { #if defined(RDNA3_5) - ggml_cuda_mmq_load_tiles_q5_K_rdna35(x, x_tile, kbx0, i_max, stride); - return; + if constexpr (!has_fusion) { + ggml_cuda_mmq_load_tiles_q5_K_rdna35(x, x_tile, kbx0, i_max, stride); + return; + } #endif constexpr int warp_size = ggml_cuda_get_physical_warp_size(); @@ -1337,7 +1377,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + const block_q5_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int ky = QR5_K*txi; const int ql = get_int_b4(bxi->qs, txi); @@ -1378,7 +1418,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + const block_q5_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int * scales = (const int *) bxi->scales; const int ksc = threadIdx.x % 2; @@ -1406,7 +1446,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + const block_q5_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); x_dm[i] = bxi->dm; } @@ -1420,7 +1460,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + const block_q5_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int * scales = (const int *) bxi->scales; @@ -1432,8 +1472,8 @@ template static __device__ __forceinline_ #endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) } -template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q6_K( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { +template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_q6_K( + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1462,7 +1502,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride; + const block_q6_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int ql = get_int_b2(bxi->ql, txi); const int ql0 = (ql >> 0) & 0x0F0F0F0F; @@ -1492,7 +1532,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride; + const block_q6_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) x_df[i*sram_stride] = bxi->d; @@ -1510,7 +1550,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / 4; + const block_q6_K * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride) + (threadIdx.x % (MMQ_TILE_NE_K/8)) / 4; #if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) x_sc[i*sram_stride + threadIdx.x%4] = get_int_b2(bxi->scales, threadIdx.x % (MMQ_TILE_NE_K/8)); @@ -1523,7 +1563,9 @@ template static __device__ __forceinline_ // --------------------------------------------------------------------------------------------- template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq1_s( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1585,7 +1627,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq2_xxs( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1649,7 +1693,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq2_xs( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1714,7 +1760,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq2_s( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1782,7 +1830,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq3_xxs( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1846,7 +1896,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq3_s( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1914,8 +1966,8 @@ template static __device__ __forceinline_ } } -template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq4_xs( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { +template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq4_xs( + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -1942,7 +1994,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride; + const block_iq4_xs * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const int aux_q4 = get_int_b4(bxi->qs, kqsx); const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); @@ -1966,7 +2018,7 @@ template static __device__ __forceinline_ i = min(i, i_max); } - const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride; + const block_iq4_xs * bxi = ggml_cuda_mmq_x_row(x, x_gate, kbx0, i, stride); const float d = __half2float(bxi->d); @@ -1982,7 +2034,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_iq4_nl( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -2051,7 +2105,9 @@ template static __device__ __forceinline_ // --------------------------------------------------------------------------------------------- template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_mxfp4( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -2118,7 +2174,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_mxfp4_fp4( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q4) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q4); @@ -2160,7 +2218,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_nvfp4( - const char * __restrict__ x, int * __restrict__ x_tile, const int kb0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kb0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, prec_src1) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, prec_src1); @@ -2216,7 +2276,9 @@ template static __de } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_nvfp4_nvfp4( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q4) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q4); @@ -2257,7 +2319,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_rocmfp4( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); @@ -2326,7 +2390,9 @@ template static __device__ __forceinline_ } template static __device__ __forceinline__ void ggml_cuda_mmq_load_tiles_rocmfp4_fast( - const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + const char * __restrict__ x, const char * __restrict__ x_gate, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + GGML_UNUSED(x_gate); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, GGML_PREC_Q8) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, GGML_PREC_Q8); diff --git a/ggml/src/ggml-cuda/mmq.cu b/ggml/src/ggml-cuda/mmq.cu index bb696b4d6803..493c56fc7c9d 100644 --- a/ggml/src/ggml-cuda/mmq.cu +++ b/ggml/src/ggml-cuda/mmq.cu @@ -137,12 +137,54 @@ static ggml_prec ggml_cuda_mmq_get_prec_src1(const ggml_tensor * src0, const ggm return GGML_PREC_Q4; } +// Tile width in ne11 (dense) / ne12 (MoE) direction with the fewest tiles that fits into shared memory, 0 if there is none. +static int ggml_cuda_mmq_get_J_best( + const ggml_type type, const int64_t ncols, const bool fallback, const int cc, const size_t smpbo, const ggml_prec prec_src1, + int * nthreads_best = nullptr) { + int J_best = 0; + int ntiles_J_best = INT_MAX; + + for (int J = 8; J <= 128 && ntiles_J_best > 1; J += 8) { + const ggml_cuda_mmq_config config = ggml_cuda_mmq_get_config(type, J, fallback, cc, prec_src1); + if (config.type == GGML_TYPE_COUNT) { + continue; + } + + if (mmq_get_nbytes_shared(config, cc) > smpbo) { + continue; + } + + const int ntiles_x = (ncols + config.J - 1) / config.J; + + if (ntiles_x < ntiles_J_best) { + J_best = J; + if (nthreads_best) { + *nthreads_best = config.nthreads; + } + ntiles_J_best = ntiles_x; + } + } + return J_best; +} + void ggml_cuda_mul_mat_q( - ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { + ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst, + const ggml_cuda_mm_fusion_args_host * fusion) { GGML_ASSERT( src1->type == GGML_TYPE_F32); GGML_ASSERT( dst->type == GGML_TYPE_F32); GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); // Optional, used for batched GGML_MUL_MAT_ID. + // Fused gate/up/GLU: src0 is the up weight, dst the GLU output. + const ggml_tensor * gate = fusion ? fusion->gate : nullptr; + ggml_cuda_mm_fusion_args_device fusion_device = {}; + if (fusion) { + GGML_ASSERT(gate && !fusion->x_bias && !fusion->gate_bias && !fusion->x_scale && !fusion->gate_scale); + GGML_ASSERT(gate->type == src0->type && ggml_are_same_shape(gate, src0) && ggml_are_same_stride(gate, src0)); + fusion_device.gate = gate->data; + fusion_device.glu_op = fusion->glu_op; + fusion_device.glu_limit = fusion->glu_limit; + } + GGML_TENSOR_BINARY_OP_LOCALS; cudaStream_t stream = ctx.stream(); @@ -164,14 +206,16 @@ void ggml_cuda_mul_mat_q( const float * src1_d = (const float *) src1->data; float * dst_d = (float *) dst->data; - // If src0 is a temporary compute buffer, clear any potential padding. - if (ggml_backend_buffer_get_usage(src0->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE) { - const size_t size_data = ggml_nbytes(src0); - const size_t size_alloc = ggml_backend_buffer_get_alloc_size(src0->buffer, src0); - if (size_alloc > size_data) { - GGML_ASSERT(ggml_is_contiguously_allocated(src0)); - GGML_ASSERT(!src0->view_src); - CUDA_CHECK(cudaMemsetAsync((char *) src0->data + size_data, 0, size_alloc - size_data, stream)); + // If src0 (or the fused gate weight) is a temporary compute buffer, clear any potential padding. + for (const ggml_tensor * t : { src0, gate }) { + if (t && ggml_backend_buffer_get_usage(t->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE) { + const size_t size_data = ggml_nbytes(t); + const size_t size_alloc = ggml_backend_buffer_get_alloc_size(t->buffer, t); + if (size_alloc > size_data) { + GGML_ASSERT(ggml_is_contiguously_allocated(t)); + GGML_ASSERT(!t->view_src); + CUDA_CHECK(cudaMemsetAsync((char *) t->data + size_data, 0, size_alloc - size_data, stream)); + } } } @@ -186,7 +230,9 @@ void ggml_cuda_mul_mat_q( const bool fallback = ggml_cuda_mmq_needs_fallback(ne01, cc); - const ggml_prec prec_src1 = ggml_cuda_mmq_get_prec_src1(src0, dst, cc); + // With fusion dst is the GLU output, not a MUL_MAT; the fused types always quantize src1 to Q8_1. + // TODO support for Q4 precision if both tensors allow it + const ggml_prec prec_src1 = gate ? GGML_PREC_Q8 : ggml_cuda_mmq_get_prec_src1(src0, dst, cc); const bool use_native_fp4 = prec_src1 == GGML_PREC_Q4; const size_t y_block_size = use_native_fp4 ? sizeof(block_fp4_mmq) : sizeof(block_q8_1_mmq); @@ -202,34 +248,16 @@ void ggml_cuda_mul_mat_q( // Each expert only sees ne12*n_expert_used/ne02 tokens on average. // On RDNA3 and RDNA4 it is faster to pick the tile size against this value instead of ne12. - if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4(cc)) { + if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc) || GGML_CUDA_CC_IS_RDNA4(cc)) { ncols_opt = (ne12*n_expert_used + ne02 - 1) / ne02; } } - int ntiles_J_best = INT_MAX; - - for (int J = 8; J <= 128 && ntiles_J_best > 1; J += 8) { - const ggml_cuda_mmq_config config = ggml_cuda_mmq_get_config(src0->type, J, fallback, cc, prec_src1); - if (config.type == GGML_TYPE_COUNT) { - continue; - } - - if (mmq_get_nbytes_shared(config, cc) > smpbo) { - continue; - } - - const int ntiles_x = (ncols_opt + config.J - 1) / config.J; - - if (ntiles_x < ntiles_J_best) { - J_best = J; - nthreads_best = config.nthreads; - ntiles_J_best = ntiles_x; - } - } + J_best = ggml_cuda_mmq_get_J_best(src0->type, ncols_opt, fallback, cc, smpbo, prec_src1, &nthreads_best); #if defined(GGML_USE_HIP) if (GGML_CUDA_CC_IS_RDNA3_5(cc) && J_best > 0) { + const int ntiles_J_best = (ncols_opt + J_best - 1) / J_best; const int64_t ncols_max = ids ? ne12 : ne1; J_best = mmq_rdna35_select_J(src0->type, fallback, cc, smpbo, prec_src1, J_best, ntiles_J_best, ncols_max, ne01, ids != nullptr); @@ -283,7 +311,7 @@ void ggml_cuda_mul_mat_q( ne00, ne01, ne1, s01, ne11, s1, ne02, ne12, s02, s12, s2, ne03, ne13, s03, s13, s3, - ne1, J_best}; + ne1, J_best, fusion_device}; ggml_cuda_mul_mat_q_switch_type(ctx, args, stream, prec_src1); return; } @@ -362,7 +390,7 @@ void ggml_cuda_mul_mat_q( ne00, ne01, ne_get_rows, s01, ne_get_rows, s1, ne02, ne02, s02, s12, s2, ne03, ne13, s03, s13, s3, - ne12, J_best}; + ne12, J_best, fusion_device}; ggml_cuda_mul_mat_q_switch_type(ctx, args, stream, prec_src1); } @@ -463,7 +491,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11, int64_t } if (amd_wmma_available(cc)) { - if (GGML_CUDA_CC_IS_RDNA3(cc)) { + if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc)) { // High expert counts are almost always better on MMQ due to // the synchronization overhead in the cuBLAS/hipBLAS path: // https://github.com/ggml-org/llama.cpp/pull/18202 @@ -480,7 +508,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11, int64_t return ne11 <= (GGML_CUDA_CC_IS_RDNA3_0(cc) ? 128 : 256); case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ2_S: - return GGML_CUDA_CC_IS_RDNA3_5(cc) || ne11 <= 128; + return GGML_CUDA_CC_IS_RDNA3_5(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc) || ne11 <= 128; default: return true; } @@ -505,3 +533,22 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11, int64_t return (!GGML_CUDA_CC_IS_CDNA(cc)) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE; } + +bool ggml_cuda_mmq_fusion_is_efficient(const ggml_type type, const int64_t nrows_x, const int64_t ncols, const int64_t nchannels, const int device) { + const int cc = ggml_cuda_info().devices[device].cc; + const int nsm = ggml_cuda_info().devices[device].nsm; + const size_t smpbo = ggml_cuda_info().devices[device].smpbo; + + // Same tile width as ggml_cuda_mul_mat_q; the fused kernel has no fallback, quantizes src1 to Q8_1 and writes I/2 output rows per tile. + const bool fallback = false; + const int J_best = ggml_cuda_mmq_get_J_best(type, ncols, fallback, cc, smpbo, GGML_PREC_Q8); + if (J_best == 0) { + return false; + } + const int64_t nrows_tile = ggml_cuda_mmq_get_config(type, J_best, fallback, cc, GGML_PREC_Q8).I / 2; + const int64_t ntiles = (ncols + J_best - 1)/J_best * ((nrows_x + nrows_tile - 1)/nrows_tile) * nchannels; + // Same condition as launch_mul_mat_q uses to run the stream-k kernel with one block per tile. + const int64_t tiles_nwaves = (ntiles + nsm - 1) / nsm; + const int64_t tiles_efficiency_percent = 100 * ntiles / (nsm*tiles_nwaves); + return tiles_efficiency_percent >= 90; +} diff --git a/ggml/src/ggml-cuda/mmq.cuh b/ggml/src/ggml-cuda/mmq.cuh index 26bf182fe951..9cbf197d0fd8 100644 --- a/ggml/src/ggml-cuda/mmq.cuh +++ b/ggml/src/ggml-cuda/mmq.cuh @@ -1,6 +1,7 @@ #pragma once #include "common.cuh" +#include "unary.cuh" #include #include @@ -11,10 +12,12 @@ #define MMQ_ITER_K_FP4 512 #define MMQ_NWARPS 8 -typedef void (*ggml_cuda_mmq_load_tiles_t)(const char * __restrict__ x, int * x_tile, const int kbx0, const int i_max, const int stride); +typedef void (*ggml_cuda_mmq_load_tiles_t)(const char * __restrict__ x, const char * __restrict__ x_gate, int * x_tile, + const int kbx0, const int i_max, const int stride); typedef void (*ggml_cuda_mmq_vec_dot_t)(const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00); typedef void (*ggml_cuda_mmq_write_back_t)(const float * __restrict__ sum, const int32_t * __restrict__ get_rows_to_sorted, - float * __restrict__ dst, const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max); + float * __restrict__ dst, const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max, + const ggml_glu_op glu_op, const float glu_limit); enum mmq_q8_1_ds_layout { MMQ_Q8_1_DS_LAYOUT_D4, @@ -250,6 +253,9 @@ static __host__ ggml_cuda_mmq_config ggml_cuda_mmq_get_config(const ggml_type ty if (GGML_CUDA_CC_IS_RDNA4(cc)) { return ggml_cuda_mmq_get_config_rdna4(type, J, fallback); } + if (GGML_CUDA_CC_IS_RDNA4_M(cc)) { + return ggml_cuda_mmq_get_config_rdna3_5(type, J, fallback); + } if (GGML_CUDA_CC_IS_RDNA3_5(cc)) { return ggml_cuda_mmq_get_config_rdna35(type, J, fallback); } @@ -282,6 +288,8 @@ static constexpr __device__ ggml_cuda_mmq_config ggml_cuda_mmq_get_config(ggml_t return ggml_cuda_mmq_get_config_cdna(type, J, fallback); #elif defined(RDNA4) return ggml_cuda_mmq_get_config_rdna4(type, J, fallback); +#elif defined(RDNA4_M) + return ggml_cuda_mmq_get_config_rdna3_5(type, J, fallback); #elif defined(RDNA3_5) return ggml_cuda_mmq_get_config_rdna35(type, J, fallback); #elif defined(RDNA3) @@ -443,6 +451,28 @@ static __host__ int ggml_cuda_mmq_get_nbytes_shared_x(const ggml_cuda_mmq_config // ------------------------------------------------------------ +// Weight types with a fused gate/up/GLU path (see ggml_cuda_mmq_get_util_funcs). +static constexpr __host__ __device__ bool ggml_cuda_mmq_fusion_supported(const ggml_type type) { + return type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K || type == GGML_TYPE_Q6_K || type == GGML_TYPE_Q8_0 || type == GGML_TYPE_IQ4_XS; +} + +// Fused gate/up/GLU: the weight tile alternates chunks of this many up and gate rows, so rows r and r + 8 of an MMA tile (same thread) pair up. +static constexpr int GGML_CUDA_MMQ_FUSION_ROWS = 8; + +// Source of weight tile row i; with has_fusion the up or gate row that the interleaved tile holds there. +template +static __device__ __forceinline__ const block_t * ggml_cuda_mmq_x_row( + const char * __restrict__ x, const char * __restrict__ x_gate, const int kbx0, const int i, const int stride) { + if constexpr (has_fusion) { + constexpr int R = GGML_CUDA_MMQ_FUSION_ROWS; + const char * x_src = (i / R) % 2 == 0 ? x : x_gate; + return (const block_t *) x_src + kbx0 + ((i / (2*R))*R + i % R)*stride; + } else { + GGML_UNUSED(x_gate); + return (const block_t *) x + kbx0 + i*stride; + } +} + #include "mmq-load-tiles.cuh" #include "mmq-vec-dot.cuh" @@ -522,10 +552,14 @@ static __device__ __forceinline__ void ggml_cuda_mmq_vec_dot_q6_K_q8_1_mma_rdna3 template static __device__ __forceinline__ void ggml_cuda_mmq_write_back_dp4a( const float * __restrict__ sum, const int32_t * __restrict__ ids_dst, float * __restrict__ dst, - const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max) { + const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max, + const ggml_glu_op glu_op, const float glu_limit) { + GGML_UNUSED_VARS(glu_op, glu_limit); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, prec_src1) / warp_size; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, prec_src1); + static_assert(I % warp_size == 0, "DP4A MMQ tile height must be a multiple of the physical warp size"); const bool y_scale_used = y_scale != nullptr; @@ -559,16 +593,19 @@ template static __de } } -template +// has_fusion: accumulators l and l + ne/2 hold the up and gate values of one output element, the GLU of the two is written. +template static __device__ __forceinline__ void ggml_cuda_mmq_write_back_mma( const float * __restrict__ sum, const int * __restrict__ ids_dst, float * __restrict__ dst, - const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max) { + const float * __restrict__ y_scale, const int stride, const int i_max, const int j_max, + const ggml_glu_op glu_op, const float glu_limit) { #if defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) typedef tile<16, 16, int, DATA_LAYOUT_J_MAJOR> tile_C; #else typedef tile<16, 8, int> tile_C; #endif // defined(AMD_MFMA_AVAILABLE) || defined(AMD_WMMA_AVAILABLE) + static_assert(!has_fusion || tile_C::I == 2*GGML_CUDA_MMQ_FUSION_ROWS, "each C tile must hold one chunk of up rows and one of gate rows"); constexpr int rows_per_warp = ggml_cuda_mmq_get_rows_per_warp(type, J, fallback, prec_src1); constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. @@ -582,20 +619,23 @@ static __device__ __forceinline__ void ggml_cuda_mmq_write_back_mma( #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int l = 0; l < tile_C::ne; ++l) { + for (int l = 0; l < (has_fusion ? tile_C::ne/2 : tile_C::ne); ++l) { const int j = j0 + (threadIdx.y % ntx) * tile_C::J + tile_C::get_j(l); if (j > j_max) { continue; } - const int i = i0 + n*tile_C::I + tile_C::get_i(l); + const int i = (i0 + n*tile_C::I)/(has_fusion ? 2 : 1) + tile_C::get_i(l); if (fallback && i > i_max) { continue; } - if constexpr (type == GGML_TYPE_NVFP4) { + if constexpr (has_fusion) { + const int sum_index = (j0/tile_C::J + n)*tile_C::ne + l; + dst[ids_dst[j]*stride + i] = ggml_cuda_op_glu_single(glu_op, sum[sum_index + tile_C::ne/2], sum[sum_index], glu_limit); + } else if constexpr (type == GGML_TYPE_NVFP4) { if (y_scale_used) { dst[ids_dst[j]*stride + i] = y_scale[j] * sum[(j0/tile_C::J + n)*tile_C::ne + l]; } else { @@ -608,6 +648,8 @@ static __device__ __forceinline__ void ggml_cuda_mmq_write_back_mma( } } } + + GGML_UNUSED_VARS(y_scale_used, glu_op, glu_limit); } // ------------------------------------------------------------------------------------------------------------------------------------- @@ -624,8 +666,9 @@ struct ggml_cuda_mmq_util_funcs { vdr(vdr), load_tiles(load_tiles), vec_dot(vec_dot), write_back(write_back) {} }; -template +template static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_funcs() { + static_assert(!has_fusion || ggml_cuda_mmq_fusion_supported(type), "no fused loader for this type"); if (!ggml_cuda_mmq_get_config(type, J, fallback, prec_src1).use_mma_data_layout()) { switch (type) { case GGML_TYPE_Q1_0: @@ -667,7 +710,7 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func case GGML_TYPE_Q8_0: return ggml_cuda_mmq_util_funcs( VDR_Q8_0_Q8_1_MMQ, - ggml_cuda_mmq_load_tiles_q8_0, + ggml_cuda_mmq_load_tiles_q8_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_dp4a, ggml_cuda_mmq_write_back_dp4a); // --------------------------------------------------------------------------------------------- @@ -686,19 +729,19 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func case GGML_TYPE_Q4_K: return ggml_cuda_mmq_util_funcs( VDR_Q4_K_Q8_1_MMQ, - ggml_cuda_mmq_load_tiles_q4_K, + ggml_cuda_mmq_load_tiles_q4_K, ggml_cuda_mmq_vec_dot_q4_K_q8_1_dp4a, ggml_cuda_mmq_write_back_dp4a); case GGML_TYPE_Q5_K: return ggml_cuda_mmq_util_funcs( VDR_Q5_K_Q8_1_MMQ, - ggml_cuda_mmq_load_tiles_q5_K, + ggml_cuda_mmq_load_tiles_q5_K, ggml_cuda_mmq_vec_dot_q5_K_q8_1_dp4a, ggml_cuda_mmq_write_back_dp4a); case GGML_TYPE_Q6_K: return ggml_cuda_mmq_util_funcs( VDR_Q6_K_Q8_1_MMQ, - ggml_cuda_mmq_load_tiles_q6_K, + ggml_cuda_mmq_load_tiles_q6_K, ggml_cuda_mmq_vec_dot_q6_K_q8_1_dp4a, ggml_cuda_mmq_write_back_dp4a); // --------------------------------------------------------------------------------------------- @@ -741,7 +784,7 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func case GGML_TYPE_IQ4_XS: return ggml_cuda_mmq_util_funcs( VDR_IQ4_XS_Q8_1_MMQ, - ggml_cuda_mmq_load_tiles_iq4_xs, + ggml_cuda_mmq_load_tiles_iq4_xs, ggml_cuda_mmq_vec_dot_q8_0_q8_1_dp4a, ggml_cuda_mmq_write_back_dp4a); case GGML_TYPE_IQ4_NL: @@ -790,7 +833,7 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func -1, ggml_cuda_mmq_load_tiles_mxfp4_fp4, ggml_cuda_mmq_vec_dot_fp4_fp4_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); } break; case GGML_TYPE_NVFP4: @@ -799,7 +842,7 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func -1, ggml_cuda_mmq_load_tiles_nvfp4_nvfp4, ggml_cuda_mmq_vec_dot_fp4_fp4_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); } break; default: @@ -815,156 +858,156 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func -1, ggml_cuda_mmq_load_tiles_q1_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q2_0: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q2_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q4_0: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q4_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q4_1: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q4_1, ggml_cuda_mmq_vec_dot_q8_1_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q5_0: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q5_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q5_1: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q5_1, ggml_cuda_mmq_vec_dot_q8_1_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q8_0: return ggml_cuda_mmq_util_funcs( -1, - ggml_cuda_mmq_load_tiles_q8_0, + ggml_cuda_mmq_load_tiles_q8_0, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); // --------------------------------------------------------------------------------------------- case GGML_TYPE_Q2_K: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q2_K, ggml_cuda_mmq_vec_dot_q2_K_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q3_K: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_q3_K, ggml_cuda_mmq_vec_dot_q8_0_16_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q4_K: return ggml_cuda_mmq_util_funcs( -1, - ggml_cuda_mmq_load_tiles_q4_K, + ggml_cuda_mmq_load_tiles_q4_K, #if defined(RDNA3_5) ggml_cuda_mmq_vec_dot_q4_K_q8_1_mma_rdna35, #else ggml_cuda_mmq_vec_dot_q8_1_q8_1_mma, #endif - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q5_K: return ggml_cuda_mmq_util_funcs( -1, - ggml_cuda_mmq_load_tiles_q5_K, + ggml_cuda_mmq_load_tiles_q5_K, #if defined(RDNA3_5) ggml_cuda_mmq_vec_dot_q4_K_q8_1_mma_rdna35, #else ggml_cuda_mmq_vec_dot_q8_1_q8_1_mma, #endif - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q6_K: return ggml_cuda_mmq_util_funcs( -1, - ggml_cuda_mmq_load_tiles_q6_K, + ggml_cuda_mmq_load_tiles_q6_K, ggml_cuda_mmq_vec_dot_q6_K_q8_1_mma_rdna35, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); // --------------------------------------------------------------------------------------------- case GGML_TYPE_IQ1_S: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq1_s, ggml_cuda_mmq_vec_dot_q8_1_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ2_XXS: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq2_xxs, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ2_XS: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq2_xs, ggml_cuda_mmq_vec_dot_q8_0_16_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ2_S: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq2_s, ggml_cuda_mmq_vec_dot_q8_0_16_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ3_XXS: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq3_xxs, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ3_S: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq3_s, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ4_XS: return ggml_cuda_mmq_util_funcs( -1, - ggml_cuda_mmq_load_tiles_iq4_xs, + ggml_cuda_mmq_load_tiles_iq4_xs, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_IQ4_NL: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_iq4_nl, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); // --------------------------------------------------------------------------------------------- case GGML_TYPE_MXFP4: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_mxfp4, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_NVFP4: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_nvfp4, ggml_cuda_mmq_vec_dot_q8_0_16_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q4_0_ROCMFP4: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_rocmfp4, ggml_cuda_mmq_vec_dot_q8_0_16_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); case GGML_TYPE_Q4_0_ROCMFP4_FAST: return ggml_cuda_mmq_util_funcs( -1, ggml_cuda_mmq_load_tiles_rocmfp4_fast, ggml_cuda_mmq_vec_dot_q8_0_q8_1_mma, - ggml_cuda_mmq_write_back_mma); + ggml_cuda_mmq_write_back_mma); default: return ggml_cuda_mmq_util_funcs(1, nullptr, nullptr, nullptr); } @@ -972,22 +1015,22 @@ static constexpr __device__ ggml_cuda_mmq_util_funcs ggml_cuda_mmq_get_util_func template static constexpr __device__ int ggml_cuda_mmq_get_vdr() { - return ggml_cuda_mmq_get_util_funcs().vdr; + return ggml_cuda_mmq_get_util_funcs().vdr; } -template +template static constexpr __device__ ggml_cuda_mmq_load_tiles_t ggml_cuda_mmq_get_load_tiles() { - return ggml_cuda_mmq_get_util_funcs().load_tiles; + return ggml_cuda_mmq_get_util_funcs().load_tiles; } template static constexpr __device__ ggml_cuda_mmq_vec_dot_t ggml_cuda_mmq_get_vec_dot() { - return ggml_cuda_mmq_get_util_funcs().vec_dot; + return ggml_cuda_mmq_get_util_funcs().vec_dot; } -template +template static constexpr __device__ ggml_cuda_mmq_write_back_t ggml_cuda_mmq_get_write_back() { - return ggml_cuda_mmq_get_util_funcs().write_back; + return ggml_cuda_mmq_get_util_funcs().write_back; } // --------------------------------------------------------------------------------------------- @@ -1037,21 +1080,24 @@ static __device__ __forceinline__ void mmq_hip_tile_barrier() { } #endif -template +// has_fusion: x and x_gate are the up and gate weights. +template static __device__ __forceinline__ void mul_mat_q_process_tile( - const char * __restrict__ x, const int offset_x, const int * __restrict__ y, + const char * __restrict__ x, const char * __restrict__ x_gate, const int offset_x, const int * __restrict__ y, const int * __restrict__ ids_dst, float * __restrict__ dst, float * __restrict__ tmp_fixup, - const float * __restrict__ y_scale, + const float * __restrict__ y_scale, const ggml_glu_op glu_op, const float glu_limit, const int stride_row_x, const int ncols_y, const int stride_col_dst, const int tile_x_max_i, const int tile_y_max_j, const int kb0_start, const int kb0_stop) { + static_assert(!(fixup && has_fusion), "the fused gate/up path does not split K"); + static_assert(!(fallback && has_fusion), "the fused gate/up path needs nrows_x % 128 == 0"); constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr int nwarps = ggml_cuda_mmq_get_nthreads(type, J, fallback, prec_src1) / warp_size; constexpr int qk = ggml_cuda_type_traits::qk; constexpr int I = ggml_cuda_mmq_get_I(type, J, fallback, prec_src1); - constexpr ggml_cuda_mmq_load_tiles_t load_tiles = ggml_cuda_mmq_get_load_tiles(); + constexpr ggml_cuda_mmq_load_tiles_t load_tiles = ggml_cuda_mmq_get_load_tiles(); constexpr ggml_cuda_mmq_vec_dot_t vec_dot = ggml_cuda_mmq_get_vec_dot(); - constexpr ggml_cuda_mmq_write_back_t write_back = ggml_cuda_mmq_get_write_back(); + constexpr ggml_cuda_mmq_write_back_t write_back = ggml_cuda_mmq_get_write_back(); extern __shared__ int data_mul_mat_q[]; int * tile_y = data_mul_mat_q + J; @@ -1079,11 +1125,11 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( constexpr int sz = sizeof(block_q8_1_mmq) / sizeof(int); #if defined(RDNA3_5) - if constexpr (type == GGML_TYPE_Q4_K && (J == 64 || J == 128)) { + if constexpr (!has_fusion && type == GGML_TYPE_Q4_K && (J == 64 || J == 128)) { constexpr int qs_cache_size = I/nwarps; __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); + load_tiles(x, x_gate, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); __syncthreads(); for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { @@ -1126,12 +1172,12 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( } __syncthreads(); } - } else if constexpr (type == GGML_TYPE_Q5_K && (J == 64 || J == 128)) { + } else if constexpr (!has_fusion && type == GGML_TYPE_Q5_K && (J == 64 || J == 128)) { constexpr int qs_cache_size = I/nwarps; constexpr int qh_cache_size = I*(QI5_K/4)/(nwarps*warp_size); __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); + load_tiles(x, x_gate, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); __syncthreads(); for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { @@ -1176,12 +1222,12 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( } __syncthreads(); } - } else if constexpr (type == GGML_TYPE_Q4_0 && (J == 64 || J == 128)) { + } else if constexpr (!has_fusion && type == GGML_TYPE_Q4_0 && (J == 64 || J == 128)) { constexpr int qs_cache_size = I/nwarps; constexpr int d_cache_size = 4; __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); + load_tiles(x, x_gate, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); __syncthreads(); for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { @@ -1223,12 +1269,12 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( } __syncthreads(); } - } else if constexpr (type == GGML_TYPE_Q8_0 && J == 128) { + } else if constexpr (!has_fusion && type == GGML_TYPE_Q8_0 && J == 128) { constexpr int qs_cache_size = 2*(I/nwarps); constexpr int d_cache_size = 4; __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); + load_tiles(x, x_gate, tile_x, offset_x + kb0_start, tile_x_max_i, stride_row_x); __syncthreads(); for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { @@ -1285,7 +1331,7 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( // load_tiles overwrites tile_x, which other warps of this block may still be // reading in the previous iteration's vec_dot. __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); + load_tiles(x, x_gate, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); mmq_hip_tile_barrier(); } @@ -1322,36 +1368,38 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( #endif // defined(RDNA3_5) { for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { + load_tiles(x, x_gate, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); { - // load_tiles overwrites tile_x, which other warps of this block may still be - // reading in the previous iteration's vec_dot. - __syncthreads(); - load_tiles(x, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); - mmq_hip_tile_barrier(); - } - - const int yk = kb0 * qk / ne_block; - const int * by0 = y + ncols_y * yk * sz; - const int * by1 = y + ncols_y * (yk + 1) * sz; + const int * by0 = y + ncols_y * (kb0 * qk / ne_block) * sz; + #pragma unroll + for (int l0 = 0; l0 < J * MMQ_TILE_Y_K; l0 += nwarps * warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; - mmq_hip_tile_barrier(); -#pragma unroll - for (int l0 = 0; l0 < J*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { - const int l = l0 + threadIdx.y*warp_size + threadIdx.x; - tile_y[l] = by0[l]; + tile_y[l] = by0[l]; + } } + __syncthreads(); + vec_dot(tile_x, tile_y, sum, 0); + __syncthreads(); -#pragma unroll - for (int l0 = 0; l0 < J*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { - const int l = l0 + threadIdx.y*warp_size + threadIdx.x; - tile_y[l] = by1[l]; + + { + const int * by0 = y + ncols_y * ((kb0 * qk / ne_block) * sz + sz); + #pragma unroll + for (int l0 = 0; l0 < J * MMQ_TILE_Y_K; l0 += nwarps * warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; + + tile_y[l] = by0[l]; + } } + __syncthreads(); + vec_dot(tile_x, tile_y, sum, MMQ_TILE_NE_K); - mmq_hip_tile_barrier(); + __syncthreads(); } } #if defined(RDNA3_5) @@ -1359,29 +1407,35 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( #endif if (fixup) { - write_back(sum, ids_dst, tmp_fixup + blockIdx.x*(J*I), y_scale, I, I, J); + write_back(sum, ids_dst, tmp_fixup + blockIdx.x*(J*I), y_scale, I, I, J, glu_op, glu_limit); } else { - write_back(sum, ids_dst, dst, y_scale, stride_col_dst, tile_x_max_i, tile_y_max_j); + write_back(sum, ids_dst, dst, y_scale, stride_col_dst, tile_x_max_i, tile_y_max_j, glu_op, glu_limit); } } // The mul_mat_q kernel implements "stream-k" work partitioning as described in https://arxiv.org/abs/2301.03598 -template +template __launch_bounds__(ggml_cuda_mmq_get_nthreads(type, J, fallback, prec_src1), ggml_cuda_mmq_get_occupancy(type, J, fallback, prec_src1)) static __global__ void mul_mat_q( - const char * __restrict__ x, const int * __restrict__ y, const int32_t * __restrict__ ids_dst, + const char * __restrict__ x, const char * __restrict__ x_gate, const int * __restrict__ y, const int32_t * __restrict__ ids_dst, const int32_t * __restrict__ expert_bounds, float * __restrict__ dst, float * __restrict__ tmp_fixup, - const float * __restrict__ y_scale, + const float * __restrict__ y_scale, const ggml_glu_op glu_op, const float glu_limit, const uint3 blocks_per_ne00, const int nrows_x, const int ncols_dst, const int stride_row_x, const int ncols_y, const int stride_col_dst, const uint3 channel_ratio, const uint3 nchannels_y, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, const uint3 sample_ratio, const uint3 nsamples_y, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst, const uint3 ntx, const int32_t * __restrict__ block_expert, const int32_t * __restrict__ block_start, const int n_experts) { +#ifdef TURING_MMA_AVAILABLE + constexpr bool fusion_available = true; +#else + constexpr bool fusion_available = false; +#endif // TURING_MMA_AVAILABLE + // Skip unused template specializations for faster compilation: - if (ggml_cuda_mmq_get_config(type, J, fallback, prec_src1).type == GGML_TYPE_COUNT) { + if (ggml_cuda_mmq_get_config(type, J, fallback, prec_src1).type == GGML_TYPE_COUNT || (has_fusion && !fusion_available)) { NO_DEVICE_CODE; return; } @@ -1411,7 +1465,9 @@ static __global__ void mul_mat_q( } __syncthreads(); - if constexpr (!ggml_cuda_mmq_get_stream_k(type, J, fallback, prec_src1)) { + // The fused kernel always processes the whole K range of a tile. + if constexpr (has_fusion || !ggml_cuda_mmq_get_stream_k(type, J, fallback, prec_src1)) { + constexpr int I_dst = has_fusion ? I/2 : I; int wt, zt, jt, it; if (block_expert != nullptr) { it = blockIdx.x; @@ -1426,8 +1482,8 @@ static __global__ void mul_mat_q( const uint2 tmp2 = fast_div_modulo(blockIdx.z, nchannels_y); wt = tmp2.x; zt = tmp2.y; - jt = blockIdx.y; - it = blockIdx.x; + jt = blockIdx.x; + it = blockIdx.y; } // Defaults for regular matrix multiplication: @@ -1473,22 +1529,22 @@ static __global__ void mul_mat_q( } offset_y += (col_low + jt*J)*(sizeof(block_q8_1_mmq)/sizeof(int)); - offset_dst += it*I; + offset_dst += it*I_dst; const float * y_scale_tile = nullptr; if constexpr (type == GGML_TYPE_NVFP4) { offset_y_scale += col_low + jt*J; y_scale_tile = y_scale ? y_scale + offset_y_scale : nullptr; } - const int tile_x_max_i = nrows_x - it*I - 1; + const int tile_x_max_i = nrows_x - it*I_dst - 1; const int tile_y_max_j = col_diff - jt*J - 1; - const int offset_x = fastdiv(wt, sample_ratio)*stride_sample_x + fastdiv(zt, channel_ratio)*stride_channel_x + it*I*stride_row_x; + const int offset_x = fastdiv(wt, sample_ratio)*stride_sample_x + fastdiv(zt, channel_ratio)*stride_channel_x + it*I_dst*stride_row_x; constexpr bool fixup = false; - mul_mat_q_process_tile - (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, - stride_row_x, ncols_y, stride_col_dst, + mul_mat_q_process_tile + (x, x_gate, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, + glu_op, glu_limit, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, 0, blocks_per_ne00.z); return; } @@ -1580,9 +1636,9 @@ static __global__ void mul_mat_q( const int offset_x = fastdiv(wt, sample_ratio)*stride_sample_x + fastdiv(zt, channel_ratio)*stride_channel_x + it*I*stride_row_x; constexpr bool fixup = false; // All but (potentially) the last iterations write their data to dst rather than the fixup buffer. - mul_mat_q_process_tile - (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, - stride_row_x, ncols_y, stride_col_dst, + mul_mat_q_process_tile + (x, x_gate, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, + glu_op, glu_limit, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); kbc += blocks_per_ne00.z; @@ -1664,9 +1720,9 @@ static __global__ void mul_mat_q( const int offset_x = fastdiv(wt, sample_ratio)*stride_sample_x + fastdiv(zt, channel_ratio)*stride_channel_x + it*I*stride_row_x; constexpr bool fixup = true; // Last index writes its data to fixup buffer to avoid data races with other blocks. - mul_mat_q_process_tile - (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, - stride_row_x, ncols_y, stride_col_dst, + mul_mat_q_process_tile + (x, x_gate, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, y_scale_tile, + glu_op, glu_limit, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); } @@ -1816,6 +1872,7 @@ struct mmq_args { int64_t nsamples_x; int64_t nsamples_y; int64_t stride_sample_x; int64_t stride_sample_y; int64_t stride_sample_dst; int64_t ncols_max; int J_best; // Tile width in ne11(dense)/ne12(MoE) direction to use for optimal performance. + ggml_cuda_mm_fusion_args_device fusion = {}; // gate != nullptr selects the fused gate/up/GLU path }; #if defined(GGML_USE_HIP) @@ -1972,7 +2029,7 @@ static int mmq_rdna35_select_J( } #endif // GGML_USE_HIP -template +template static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { const int id = ggml_cuda_get_device(); const int cc = ggml_cuda_info().devices[id].cc; @@ -1986,13 +2043,17 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a const dim3 block_dims(warp_size, nwarps, 1); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + if constexpr (!has_fusion) { + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + } - const int nty = (args.nrows_x + config.I - 1) / config.I; + const int I_dst = has_fusion ? config.I/2 : config.I; // Rows of dst per tile, see mul_mat_q. + const int nty = (args.nrows_x + I_dst - 1) / I_dst; const int ntx = (args.ncols_max + config.J - 1) / config.J; const int ntzw = args.nchannels_y * args.nsamples_y; - const dim3 block_nums_xy_tiling(nty, ntx, ntzw); + // Column tiles innermost so that the concurrently running blocks share the same tile of x and read it from L2. + const dim3 block_nums_xy_tiling(ntx, nty, ntzw); GGML_ASSERT(args.nchannels_y % args.nchannels_x == 0); GGML_ASSERT(args.nsamples_y % args.nsamples_x == 0); @@ -2006,8 +2067,8 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a const uint3 channel_ratio_fd = init_fastdiv_values(channel_ratio); const uint3 sample_ratio_fd = init_fastdiv_values(sample_ratio); - if (!config.stream_k) { - const bool use_compact = args.expert_bounds != nullptr && GGML_CUDA_CC_IS_RDNA3_5(cc); + if (has_fusion || !config.stream_k) { + const bool use_compact = !has_fusion && args.expert_bounds != nullptr && GGML_CUDA_CC_IS_RDNA3_5(cc); const int32_t * block_expert_ptr = nullptr; const int32_t * block_start_ptr = nullptr; int n_experts = 0; @@ -2032,8 +2093,9 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a } } - mul_mat_q<<>> - (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.y_scale, + GGML_ASSERT(block_nums.y <= MMQ_MAX_GRIDDIM_Y); + mul_mat_q<<>> + (args.x, (const char *) args.fusion.gate, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.y_scale, args.fusion.glu_op, args.fusion.glu_limit, blocks_per_ne00_fd, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio_fd, nchannels_y_fd, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, sample_ratio_fd, nsamples_y_fd, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, @@ -2046,10 +2108,12 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a const int ntiles_dst = ntx * nty * ntzw; const int tiles_nwaves = (ntiles_dst + nsm - 1) / nsm; const int tiles_efficiency_percent = 100 * ntiles_dst / (nsm*tiles_nwaves); - const dim3 block_nums_stream_k(GGML_CUDA_CC_IS_NVIDIA(cc) && tiles_efficiency_percent >= 90 ? ntiles_dst : nsm, 1, 1); GGML_ASSERT(ntiles_dst * blocks_per_ne00_fd.z < (1 << 30)); // Assert that variable kbc will not overflow. + const int nwork = ntiles_dst * ((args.ncols_x + config.K_vram - 1) / config.K_vram); // Maximum number of CUDA blocks that can do useful work. + const dim3 block_nums_stream_k(GGML_CUDA_CC_IS_NVIDIA(cc) && tiles_efficiency_percent >= 90 ? ntiles_dst : std::min(nsm, nwork), 1, 1); + const bool fixup_needed = ntiles_dst % block_nums_stream_k.x != 0; ggml_cuda_pool & pool = ctx.pool(id); @@ -2061,8 +2125,8 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a const dim3 block_nums_fixup(block_nums_stream_k.x, config.I/warp_size, 1); const dim3 block_dims_fixup(block_dims.x, block_dims.y/2, block_dims.z); - mul_mat_q<<>> - (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.y_scale, + mul_mat_q<<>> + (args.x, (const char *) args.fusion.gate, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.y_scale, args.fusion.glu_op, args.fusion.glu_limit, blocks_per_ne00_fd, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio_fd, nchannels_y_fd, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, sample_ratio_fd, nsamples_y_fd, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, @@ -2079,56 +2143,56 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a ntx_fd); } -template +template void mul_mat_q_switch_J(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { switch (args.J_best) { case 8: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 16: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 24: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 32: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 40: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 48: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 56: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 64: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 72: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 80: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 88: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 96: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 104: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 112: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 120: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; case 128: - launch_mul_mat_q(ctx, args, stream); + launch_mul_mat_q(ctx, args, stream); break; default: fprintf(stderr, "J_best=%d\n", args.J_best); @@ -2136,15 +2200,27 @@ void mul_mat_q_switch_J(ggml_backend_cuda_context & ctx, const mmq_args & args, } } +template +static void mul_mat_q_switch_fusion(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { + if constexpr (!fallback && ggml_cuda_mmq_fusion_supported(type)) { + if (args.fusion.gate) { + mul_mat_q_switch_J(ctx, args, stream); + return; + } + } + GGML_ASSERT(!args.fusion.gate); + mul_mat_q_switch_J(ctx, args, stream); +} + template void mul_mat_q_case(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; if (ggml_cuda_mmq_needs_fallback(args.nrows_x, cc)) { constexpr bool fallback = true; - mul_mat_q_switch_J(ctx, args, stream); + mul_mat_q_switch_fusion(ctx, args, stream); } else { constexpr bool fallback = false; - mul_mat_q_switch_J(ctx, args, stream); + mul_mat_q_switch_fusion(ctx, args, stream); } } @@ -2188,6 +2264,9 @@ extern DECL_MMQ_CASE_W4A4(GGML_TYPE_NVFP4); // ------------------------------------------------------------------------------------------------------------------------- void ggml_cuda_mul_mat_q( - ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); + ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst, + const ggml_cuda_mm_fusion_args_host * fusion = nullptr); bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11, int64_t n_experts); + +bool ggml_cuda_mmq_fusion_is_efficient(ggml_type type, int64_t nrows_x, int64_t ncols, int64_t nchannels, int device); diff --git a/ggml/src/ggml-cuda/mmvf.cu b/ggml/src/ggml-cuda/mmvf.cu index 752d28c4f2e2..a62bf53e8472 100644 --- a/ggml/src/ggml-cuda/mmvf.cu +++ b/ggml/src/ggml-cuda/mmvf.cu @@ -844,7 +844,7 @@ bool ggml_cuda_should_use_mmvf(enum ggml_type type, int cc, int warp_size, const return ne11 <= MMVF_MAX_BATCH_SIZE; } if (fp16_mma_hardware_available(cc)) { - if (GGML_CUDA_CC_IS_RDNA3(cc)) { + if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc)) { return ne11 <= 3; } if (GGML_CUDA_CC_IS_RDNA4(cc)) { diff --git a/ggml/src/ggml-cuda/mmvq.cu b/ggml/src/ggml-cuda/mmvq.cu index 7719592478f3..fb75807668b7 100644 --- a/ggml/src/ggml-cuda/mmvq.cu +++ b/ggml/src/ggml-cuda/mmvq.cu @@ -117,7 +117,7 @@ static constexpr __device__ mmvq_parameter_table_id get_device_table_id() { return MMVQ_PARAMETERS_RDNA4; #elif defined(RDNA3_0) return MMVQ_PARAMETERS_RDNA3_0; -#elif defined(RDNA2) || defined(RDNA3_5) +#elif defined(RDNA2) || defined(RDNA3_5) || defined(RDNA4_M) return MMVQ_PARAMETERS_RDNA2; #elif defined(GCN) || defined(CDNA) return MMVQ_PARAMETERS_GCN; @@ -137,7 +137,7 @@ static __host__ mmvq_parameter_table_id get_device_table_id(int cc) { if (GGML_CUDA_CC_IS_RDNA3_0(cc)) { return MMVQ_PARAMETERS_RDNA3_0; } - if (GGML_CUDA_CC_IS_RDNA2(cc) || GGML_CUDA_CC_IS_RDNA3_5(cc)) { + if (GGML_CUDA_CC_IS_RDNA2(cc) || GGML_CUDA_CC_IS_RDNA3_5(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc)) { return MMVQ_PARAMETERS_RDNA2; } if (GGML_CUDA_CC_IS_GCN(cc) || GGML_CUDA_CC_IS_CDNA(cc)) { @@ -308,7 +308,7 @@ int get_mmvq_mmid_max_batch(ggml_type type, int cc) { if (GGML_CUDA_CC_IS_RDNA4(cc)) { return get_mmvq_mmid_max_batch_rdna4(type); } - if (GGML_CUDA_CC_IS_RDNA3(cc)) { + if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4_M(cc)) { return get_mmvq_mmid_max_batch_rdna3(type); } if (GGML_CUDA_CC_IS_RDNA1(cc) || GGML_CUDA_CC_IS_RDNA2(cc)) { @@ -441,7 +441,7 @@ template static constexpr __device__ int get_mmvq_mmid_max_batch_for_device() { #if defined(RDNA4) return get_mmvq_mmid_max_batch_rdna4(type); -#elif defined(RDNA3) +#elif defined(RDNA3) || defined(RDNA4_M) return get_mmvq_mmid_max_batch_rdna3(type); #elif defined(RDNA2) || defined(RDNA1) return get_mmvq_mmid_max_batch_rdna1_rdna2(type); @@ -477,10 +477,12 @@ static constexpr __host__ __device__ int calc_nwarps(ggml_type type, int ncols_d } else if (table_id == MMVQ_PARAMETERS_GCN) { switch (ncols_dst) { case 1: + return 2; case 2: case 3: + return type == GGML_TYPE_Q3_K ? 1 : 2; case 4: - return 2; + return type == GGML_TYPE_Q6_K? 1 : 2; case 5: case 6: case 7: @@ -585,11 +587,31 @@ static constexpr __host__ __device__ int calc_nwarps(ggml_type type, int ncols_d return 1; } -static constexpr __host__ __device__ int calc_rows_per_block(int ncols_dst, int table_id, bool small_k = false, int nwarps = 1) { +// Low bit types load few weight bytes per thread, a second row per block shares the q8_1 loads and adds memory parallelism. +static constexpr __host__ __device__ bool mmvq_two_rows_ncols1(ggml_type type) { + switch (type) { + case GGML_TYPE_Q1_0: + case GGML_TYPE_Q2_K: + case GGML_TYPE_Q3_K: + case GGML_TYPE_IQ1_S: + case GGML_TYPE_IQ1_M: + return true; + default: + return false; + } +} + +static constexpr __host__ __device__ int calc_rows_per_block(ggml_type type, int ncols_dst, int table_id, bool small_k = false, int nwarps = 1) { if (table_id == MMVQ_PARAMETERS_GENERIC || table_id == MMVQ_PARAMETERS_GCN || table_id == MMVQ_PARAMETERS_TURING || table_id == MMVQ_PARAMETERS_GB10) { switch (ncols_dst) { case 1: - return small_k ? nwarps : 1; + if (small_k) { + return nwarps; + } + if (table_id == MMVQ_PARAMETERS_GB10) { + return type == GGML_TYPE_IQ2_S || type == GGML_TYPE_IQ3_S ? 2 : 1; + } + return table_id == MMVQ_PARAMETERS_GENERIC && mmvq_two_rows_ncols1(type) ? 2 : 1; case 2: case 3: case 4: @@ -624,7 +646,7 @@ static __global__ void mul_mat_vec_q( constexpr int vdr = get_vdr_mmvq(type); constexpr mmvq_parameter_table_id table_id = get_device_table_id(); constexpr int nwarps = calc_nwarps(type, ncols_dst, table_id, small_k, halve_iters); - constexpr int rows_per_cuda_block = calc_rows_per_block(ncols_dst, table_id, small_k, nwarps); + constexpr int rows_per_cuda_block = calc_rows_per_block(type, ncols_dst, table_id, small_k, nwarps); constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr vec_dot_q_cuda_t vec_dot_q_cuda = get_vec_dot_q_cuda(type); @@ -736,7 +758,8 @@ static __global__ void mul_mat_vec_q( #if __CUDA_ARCH__ == GGML_CUDA_CC_DGX_SPARK // start the next iterations' weight loads early if constexpr (mmvq_should_prefetch(type)) { - constexpr int pf_dist = 2; // loop iterations, not blocks + // loop iterations, not blocks; q3_K and q6_K keep the distance in blocks they had with vdr 1 + constexpr int pf_dist = type == GGML_TYPE_Q3_K || type == GGML_TYPE_Q6_K ? 1 : 2; const int kbx_pf = kbx + pf_dist*blocks_per_iter; if (kbx_pf < blocks_per_row_x) { #pragma unroll @@ -1032,7 +1055,7 @@ static std::pair calc_launch_params( const int ncols_dst, const int nrows_x, const int nchannels_dst, const int nsamples_or_ntokens, const int warp_size, const mmvq_parameter_table_id table_id, const bool small_k = false, const bool halve_iters = false) { const int nwarps = calc_nwarps(type, ncols_dst, table_id, small_k, halve_iters); - const int rpb = calc_rows_per_block(ncols_dst, table_id, small_k, nwarps); + const int rpb = calc_rows_per_block(type, ncols_dst, table_id, small_k, nwarps); const int64_t nblocks = (nrows_x + rpb - 1) / rpb; const dim3 block_nums(nblocks, nchannels_dst, nsamples_or_ntokens); const dim3 block_dims(warp_size, nwarps, 1); diff --git a/ggml/src/ggml-cuda/norm.cu b/ggml/src/ggml-cuda/norm.cu index d804b933bbb5..3f0ea6f2a474 100644 --- a/ggml/src/ggml-cuda/norm.cu +++ b/ggml/src/ggml-cuda/norm.cu @@ -81,7 +81,7 @@ static __global__ void group_norm_f32(const float * x, float * dst, const int gr } } -template +template static __global__ void rms_norm_f32(const float * x, float * dst, const int ncols, @@ -142,31 +142,82 @@ static __global__ void rms_norm_f32(const float * x, addc = add + add_sample * add_stride_sample + add_channel * add_stride_channel + add_row * add_stride_row; } - float tmp = 0.0f; // partial sum for thread in warp - - for (int col = tid; col < ncols; col += block_size) { - const float xi = xc[col]; - tmp += xi * xi; - } - - // sum up partial sums - tmp = block_reduce(tmp, s_sum); + if constexpr (do_vec) { + const int ncols4 = ncols / 4; + const float4 * x4 = (const float4 *) xc; + const float4 * mul4 = (const float4 *) mulc; + const float4 * add4 = (const float4 *) addc; + float4 * dst4 = (float4 *) dstc; + + float4 xs[vpt]; + float tmp = 0.0f; + +#pragma unroll + for (int k = 0; k < vpt; k++) { + const int i = tid + k*block_size; + if (i < ncols4) { + xs[k] = x4[i]; + tmp += xs[k].x*xs[k].x + xs[k].y*xs[k].y + xs[k].z*xs[k].z + xs[k].w*xs[k].w; + } + } + tmp = block_reduce(tmp, s_sum); + const float scale = rsqrtf(tmp / ncols + eps); + +#pragma unroll + for (int k = 0; k < vpt; k++) { + const int i = tid + k*block_size; + if (i < ncols4) { + float4 r = make_float4(scale*xs[k].x, scale*xs[k].y, scale*xs[k].z, scale*xs[k].w); + if constexpr (do_multiply) { + const float4 m = mul4[i]; + r.x *= m.x; + r.y *= m.y; + r.z *= m.z; + r.w *= m.w; + } + if constexpr (do_add) { + const float4 a = add4[i]; + r.x += a.x; + r.y += a.y; + r.z += a.z; + r.w += a.w; + } + if constexpr (do_scale) { + r.x *= scale_out; + r.y *= scale_out; + r.z *= scale_out; + r.w *= scale_out; + } + dst4[i] = r; + } + } + } else { + float tmp = 0.0f; // partial sum for thread in warp - const float mean = tmp / ncols; - const float scale = rsqrtf(mean + eps); + for (int col = tid; col < ncols; col += block_size) { + const float xi = xc[col]; + tmp += xi * xi; + } - for (int col = tid; col < ncols; col += block_size) { - if constexpr (do_multiply && do_add) { - const int mul_col = fastmodulo(col, mul_ncols_packed); - const int add_col = fastmodulo(col, add_ncols_packed); - dstc[col] = scale * xc[col] * mulc[mul_col] + addc[add_col]; - } else if constexpr (do_multiply) { - const int mul_col = fastmodulo(col, mul_ncols_packed); - dstc[col] = scale * xc[col] * mulc[mul_col]; - } else if constexpr (do_scale) { - dstc[col] = scale_out * (scale * xc[col]); - } else { - dstc[col] = scale * xc[col]; + // sum up partial sums + tmp = block_reduce(tmp, s_sum); + + const float mean = tmp / ncols; + const float scale = rsqrtf(mean + eps); + + for (int col = tid; col < ncols; col += block_size) { + if constexpr (do_multiply && do_add) { + const int mul_col = fastmodulo(col, mul_ncols_packed); + const int add_col = fastmodulo(col, add_ncols_packed); + dstc[col] = scale * xc[col] * mulc[mul_col] + addc[add_col]; + } else if constexpr (do_multiply) { + const int mul_col = fastmodulo(col, mul_ncols_packed); + dstc[col] = scale * xc[col] * mulc[mul_col]; + } else if constexpr (do_scale) { + dstc[col] = scale_out * (scale * xc[col]); + } else { + dstc[col] = scale * xc[col]; + } } } @@ -332,34 +383,89 @@ static void group_norm_f32_cuda( } } +#define RMS_NORM_LAUNCH(BLOCK_SIZE, VPT, VEC) \ + do { \ + const dim3 block_dims(BLOCK_SIZE, 1, 1); \ + const ggml_cuda_kernel_launch_params launch_params{ blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float) : 0, stream }; \ + ggml_cuda_kernel_launch(rms_norm_f32, launch_params, \ + x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, \ + mul, mul_stride_row, mul_stride_channel, mul_stride_sample, \ + mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, \ + add, add_stride_row, add_stride_channel, add_stride_sample, \ + add_ncols_packed, add_nrows_packed, add_nchannels_packed, add_nsamples_packed, scale_out); \ + } while (0) + +template +static void rms_norm_f32_dispatch( + const dim3 blocks_num, + const ggml_tensor * x_t, float * dst, const int ncols, const int nchannels, const int nsamples, + const int64_t stride_row, const int64_t stride_channel, const int64_t stride_sample, const float eps, + const ggml_tensor * mul_t, const int64_t mul_stride_row, const int64_t mul_stride_channel, const int64_t mul_stride_sample, + const uint3 mul_ncols_packed, const uint3 mul_nrows_packed, const uint3 mul_nchannels_packed, const uint3 mul_nsamples_packed, + const ggml_tensor * add_t, const int64_t add_stride_row, const int64_t add_stride_channel, const int64_t add_stride_sample, + const uint3 add_ncols_packed, const uint3 add_nrows_packed, const uint3 add_nchannels_packed, const uint3 add_nsamples_packed, + cudaStream_t stream, const float scale_out = 1.0f) { + static_assert(!do_add || do_multiply, "fusing add is not supported without multiplying"); + static_assert(!do_scale || !do_multiply, "fusing scale is not supported with multiplying"); + + const float * x = (const float *) x_t->data; + const float * mul = mul_t ? (const float *) mul_t->data : nullptr; + const float * add = add_t ? (const float *) add_t->data : nullptr; + + // dst is written at row * ncols, i.e. always at a multiple of ncols, so only its base needs checking here + bool vec = ncols % 4 == 0 && ncols > 0 && ((uintptr_t) dst & 15) == 0; + vec = vec && ggml_cuda_is_aligned(x_t, 16); + if constexpr (do_multiply) { + vec = vec && mul_ncols_packed.z == (uint32_t) ncols + && ggml_cuda_is_aligned(mul_t, 16); + } + if constexpr (do_add) { + vec = vec && add_ncols_packed.z == (uint32_t) ncols + && ggml_cuda_is_aligned(add_t, 16); + } + + const int n4 = ncols / 4; + if (vec) { + if (n4 <= 32) { + RMS_NORM_LAUNCH(32, 1, true); + } else if (n4 <= 128) { + RMS_NORM_LAUNCH(128, 1, true); + } else if (n4 <= 256) { + RMS_NORM_LAUNCH(256, 1, true); + } else if (n4 <= 512) { + RMS_NORM_LAUNCH(512, 1, true); + } else if (n4 <= 1024) { + RMS_NORM_LAUNCH(1024, 1, true); + } else if (n4 <= 4096) { + RMS_NORM_LAUNCH(1024, 4, true); + } else { + RMS_NORM_LAUNCH(1024, 1, false); + } + } else if (ncols < 1024) { + RMS_NORM_LAUNCH(256, 1, false); + } else { + RMS_NORM_LAUNCH(1024, 1, false); + } +} +#undef RMS_NORM_LAUNCH + template static void rms_norm_f32_cuda( - const float * x, float * dst, const int ncols, const int nrows, const int nchannels, const int nsamples, + const ggml_tensor * x_t, float * dst, const int ncols, const int nrows, const int nchannels, const int nsamples, const int64_t stride_row, const int64_t stride_channel, const int64_t stride_sample, const float eps, cudaStream_t stream, const float scale_out = 1.0f) { const dim3 blocks_num(nrows, MIN(nchannels, UINT16_MAX), MIN(nsamples, UINT16_MAX)); - if (ncols < 1024) { - const dim3 block_dims(256, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = {blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<256, false, false, do_scale>, launch_params, - x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, - // underlying cudaLaunchKernelEx does not support default params + rms_norm_f32_dispatch( + blocks_num, x_t, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), - nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), scale_out); - } else { - const dim3 block_dims(1024, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params{blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<1024, false, false, do_scale>, launch_params, x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, - // underlying cudaLaunchKernelEx does not support default params nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), - nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), scale_out); - } + stream, scale_out); } -static void rms_norm_mul_f32_cuda(const float * x, - const float * mul, - const float * add, - float * dst, +static void rms_norm_mul_f32_cuda(const ggml_tensor * x_t, + const ggml_tensor * mul_t, + const ggml_tensor * add_t, + float * dst, const int ncols, const int nrows, const int nchannels, @@ -384,59 +490,33 @@ static void rms_norm_mul_f32_cuda(const float * x, const float eps, cudaStream_t stream) { const dim3 blocks_num(nrows, MIN(nchannels, UINT16_MAX), MIN(nsamples, UINT16_MAX)); - if (mul == nullptr) { - rms_norm_f32_cuda(x, dst, ncols, nrows, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, stream); + if (mul_t == nullptr) { + rms_norm_f32_cuda(x_t, dst, ncols, nrows, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, stream); return; } - if (add == nullptr) { - const uint3 mul_ncols_packed = init_fastdiv_values(mul_ncols); - const uint3 mul_nrows_packed = init_fastdiv_values(mul_nrows); - const uint3 mul_nchannels_packed = init_fastdiv_values(mul_nchannels); - const uint3 mul_nsamples_packed = init_fastdiv_values(mul_nsamples); - if (ncols < 1024) { - const dim3 block_dims(256, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params{blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<256, true>, launch_params, - x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, - mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, - // underlying cudaLaunchKernelEx does not support default params - nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), 1.0f); - } else { - const dim3 block_dims(1024, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params{blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<1024, true>, launch_params, - x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, - mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, - // underlying cudaLaunchKernelEx does not support default params - nullptr, 0, 0, 0, make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), make_uint3(0, 0, 0), 1.0f); - } + const uint3 mul_ncols_packed = init_fastdiv_values(mul_ncols); + const uint3 mul_nrows_packed = init_fastdiv_values(mul_nrows); + const uint3 mul_nchannels_packed = init_fastdiv_values(mul_nchannels); + const uint3 mul_nsamples_packed = init_fastdiv_values(mul_nsamples); + const uint3 zero_packed = make_uint3(0, 0, 0); + + if (add_t == nullptr) { + rms_norm_f32_dispatch( + blocks_num, x_t, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, + mul_t, mul_stride_row, mul_stride_channel, mul_stride_sample, + mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, + nullptr, 0, 0, 0, zero_packed, zero_packed, zero_packed, zero_packed, stream); } else { - const uint3 mul_ncols_packed = init_fastdiv_values(mul_ncols); - const uint3 mul_nrows_packed = init_fastdiv_values(mul_nrows); - const uint3 mul_nchannels_packed = init_fastdiv_values(mul_nchannels); - const uint3 mul_nsamples_packed = init_fastdiv_values(mul_nsamples); - const uint3 add_ncols_packed = init_fastdiv_values(add_ncols); const uint3 add_nrows_packed = init_fastdiv_values(add_nrows); const uint3 add_nchannels_packed = init_fastdiv_values(add_nchannels); const uint3 add_nsamples_packed = init_fastdiv_values(add_nsamples); - if (ncols < 1024) { - const dim3 block_dims(256, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params{blocks_num, block_dims,block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<256, true, true>, launch_params, - x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, - mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, add, - add_stride_row, add_stride_channel, add_stride_sample, add_ncols_packed, add_nrows_packed, - add_nchannels_packed, add_nsamples_packed, 1.0f); - } else { - const dim3 block_dims(1024, 1, 1); - const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params{blocks_num, block_dims, block_dims.x > WARP_SIZE ? 32 * sizeof(float): 0, stream}; - ggml_cuda_kernel_launch(rms_norm_f32<1024, true, true>, launch_params, - x, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, - mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, add, - add_stride_row, add_stride_channel, add_stride_sample, add_ncols_packed, add_nrows_packed, - add_nchannels_packed, add_nsamples_packed, 1.0f); - } + rms_norm_f32_dispatch( + blocks_num, x_t, dst, ncols, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, + mul_t, mul_stride_row, mul_stride_channel, mul_stride_sample, + mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, + add_t, add_stride_row, add_stride_channel, add_stride_sample, + add_ncols_packed, add_nrows_packed, add_nchannels_packed, add_nsamples_packed, stream); } } @@ -510,7 +590,6 @@ void ggml_cuda_op_group_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst) void ggml_cuda_op_rms_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; - const float * src0_d = (const float *) src0->data; float * dst_d = (float *) dst->data; cudaStream_t stream = ctx.stream(); @@ -529,12 +608,11 @@ void ggml_cuda_op_rms_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const int64_t s02 = nb02 / ts0; const int64_t s03 = nb03 / ts0; - rms_norm_f32_cuda(src0_d, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream); + rms_norm_f32_cuda(src0, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream); } void ggml_cuda_op_rms_norm_scale_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * scale_tensor) { const ggml_tensor * src0 = dst->src[0]; - const float * src0_d = (const float *) src0->data; float * dst_d = (float *) scale_tensor->data; cudaStream_t stream = ctx.stream(); @@ -556,7 +634,7 @@ void ggml_cuda_op_rms_norm_scale_fused(ggml_backend_cuda_context & ctx, ggml_ten const int64_t s02 = nb02 / ts0; const int64_t s03 = nb03 / ts0; - rms_norm_f32_cuda(src0_d, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream, scale); + rms_norm_f32_cuda(src0, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream, scale); } void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * mul_tensor) { @@ -565,15 +643,11 @@ void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * memcpy(&eps, dst->op_params, sizeof(float)); - const float * src0_d = (const float *) rms_norm_src->data; - const float * mul_d = nullptr; const ggml_tensor * mul_src = nullptr; if (mul_tensor->src[0] == dst) { - mul_d = (float *) mul_tensor->src[1]->data; mul_src = mul_tensor->src[1]; } else if(mul_tensor->src[1] == dst) { - mul_d = (float *) mul_tensor->src[0]->data; mul_src = mul_tensor->src[0]; } else { GGML_ASSERT(false); @@ -609,7 +683,7 @@ void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * const int mul_nchannels = mul_src->ne[2]; const int mul_nsamples = mul_src->ne[3]; - rms_norm_mul_f32_cuda(src0_d, mul_d, nullptr, dst_d, + rms_norm_mul_f32_cuda(rms_norm_src, mul_src, nullptr, dst_d, ne00, ne01, ne02, ne03, /*s00*/ s01, s02, s03, /*mul_s00*/ mul_s01, mul_s02, mul_s03, @@ -628,28 +702,21 @@ void ggml_cuda_op_rms_norm_fused_add(ggml_backend_cuda_context & ctx, memcpy(&eps, dst->op_params, sizeof(float)); - const float * src0_d = (const float *) rms_norm_src->data; - const float * mul_d = nullptr; const ggml_tensor * mul_src = nullptr; if (mul_tensor->src[0] == dst) { - mul_d = (float *) mul_tensor->src[1]->data; mul_src = mul_tensor->src[1]; } else if (mul_tensor->src[1] == dst) { - mul_d = (float *) mul_tensor->src[0]->data; mul_src = mul_tensor->src[0]; } else { GGML_ASSERT(false); } - const float * add_d = nullptr; const ggml_tensor * add_src = nullptr; if (add_tensor->src[0] == mul_tensor) { - add_d = (float *) add_tensor->src[1]->data; add_src = add_tensor->src[1]; } else if (add_tensor->src[1] == mul_tensor) { - add_d = (float *) add_tensor->src[0]->data; add_src = add_tensor->src[0]; } else { GGML_ASSERT(false); @@ -697,7 +764,7 @@ void ggml_cuda_op_rms_norm_fused_add(ggml_backend_cuda_context & ctx, const int add_nchannels = add_src->ne[2]; const int add_nsamples = add_src->ne[3]; - rms_norm_mul_f32_cuda(src0_d, mul_d,add_d,dst_d, + rms_norm_mul_f32_cuda(rms_norm_src, mul_src,add_src,dst_d, ne00,ne01, ne02, ne03, /*s00*/ s01, s02, s03, /*mul_s00*/ mul_s01, mul_s02, mul_s03, diff --git a/ggml/src/ggml-cuda/rope.cu b/ggml/src/ggml-cuda/rope.cu index b4fca778fa69..45e813406597 100644 --- a/ggml/src/ggml-cuda/rope.cu +++ b/ggml/src/ggml-cuda/rope.cu @@ -196,9 +196,9 @@ static __global__ void rope_neox(const T * x, dst[idst + n_offs/2 + n_dims / 2] = ggml_cuda_cast(x0 * sin_theta + x1 * cos_theta); } -template +template static __global__ void rope_multi(const T * x, - T * dst, + D * dst, const int ne00, const int ne01, const int ne02, @@ -219,6 +219,8 @@ static __global__ void rope_multi(const T * x, const float * freq_factors, const mrope_sections sections, const bool is_imrope, + const int64_t * row_indices, + const int set_rows_stride, const bool inplace) { const int i0 = 2 * (blockDim.y * blockIdx.y + threadIdx.y); @@ -236,12 +238,20 @@ static __global__ void rope_multi(const T * x, const int ix = i0 / 2 + i1 * s01 + i2 * s02 + i3 * s03; ggml_cuda_pdl_sync(); + + // Fusion optimization: ROPE + VIEW + SET_ROWS. + // The rope output is viewed as a 1D tensor and offset based on a row index in row_indices. + if (set_rows_stride != 0) { + idst = i1 * s1 + i0 / 2; + idst += row_indices[i2] * set_rows_stride; + } + if (i0 < n_offs || i0 >= n_offs + n_dims) { if (inplace) { return; } - dst[idst + i0/2 + 0] = x[ix + i0/2 + 0]; - dst[idst + i0/2 + 1] = x[ix + i0/2 + 1]; + dst[idst + i0/2 + 0] = ggml_cuda_cast(x[ix + i0/2 + 0]); + dst[idst + i0/2 + 1] = ggml_cuda_cast(x[ix + i0/2 + 1]); return; } @@ -286,8 +296,8 @@ static __global__ void rope_multi(const T * x, const float x0 = x[ix + n_offs/2 + 0]; const float x1 = x[ix + n_offs/2 + n_dims/2]; - dst[idst + n_offs/2 + 0] = x0*cos_theta - x1*sin_theta; - dst[idst + n_offs/2 + n_dims/2] = x0*sin_theta + x1*cos_theta; + dst[idst + n_offs/2 + 0] = ggml_cuda_cast(x0*cos_theta - x1*sin_theta); + dst[idst + n_offs/2 + n_dims/2] = ggml_cuda_cast(x0*sin_theta + x1*cos_theta); } template @@ -443,9 +453,9 @@ static void rope_neox_cuda(const T * x, } } -template +template static void rope_multi_cuda(const T * x, - T * dst, + D * dst, const int ne00, const int ne01, const int ne02, @@ -467,6 +477,8 @@ static void rope_multi_cuda(const T * x, const float * freq_factors, const mrope_sections sections, const bool is_imrope, + const int64_t * row_indices, + const int set_rows_stride, const bool inplace, cudaStream_t stream) { GGML_ASSERT(ne00 % 2 == 0); @@ -478,14 +490,14 @@ static void rope_multi_cuda(const T * x, if (freq_factors == nullptr) { const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(block_nums, block_dims, 0, stream); - ggml_cuda_kernel_launch(rope_multi, launch_params, + ggml_cuda_kernel_launch(rope_multi, launch_params, x, dst, ne00, ne01, ne02, s01, s02, s03, s1, s2, s3, n_dims, n_offs, pos, freq_scale, ext_factor, - attn_factor, corr_dims, theta_scale, freq_factors, sections, is_imrope, inplace); + attn_factor, corr_dims, theta_scale, freq_factors, sections, is_imrope, row_indices, set_rows_stride, inplace); } else { const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(block_nums, block_dims, 0, stream); - ggml_cuda_kernel_launch(rope_multi, launch_params, + ggml_cuda_kernel_launch(rope_multi, launch_params, x, dst, ne00, ne01, ne02, s01, s02, s03, s1, s2, s3, n_dims, n_offs, pos, freq_scale, ext_factor, - attn_factor, corr_dims, theta_scale, freq_factors, sections, is_imrope, inplace); + attn_factor, corr_dims, theta_scale, freq_factors, sections, is_imrope, row_indices, set_rows_stride, inplace); } } @@ -648,14 +660,21 @@ void ggml_cuda_op_rope_impl(ggml_backend_cuda_context & ctx, GGML_ABORT("fatal error"); } } else if (is_mrope && !is_vision) { - if (src0->type == GGML_TYPE_F32) { - rope_multi_cuda((const float *) src0_d, (float *) dst_d, ne00, ne01, ne02, s01, s02, s03, s1, - s2, s3, n_dims, n_offs, nr, pos, freq_scale, freq_base, ext_factor, attn_factor, - corr_dims, freq_factors, sections, is_imrope, inplace, stream); - } else if (src0->type == GGML_TYPE_F16) { - rope_multi_cuda((const half *) src0_d, (half *) dst_d, ne00, ne01, ne02, s01, s02, s03, s1, - s2, s3, n_dims, n_offs, nr, pos, freq_scale, freq_base, ext_factor, attn_factor, - corr_dims, freq_factors, sections, is_imrope, inplace, stream); + if (src0->type == GGML_TYPE_F32 && dst_type == GGML_TYPE_F32) { + rope_multi_cuda((const float *) src0_d, (float *) dst_d, ne00, ne01, ne02, s01, s02, + s03, s1, s2, s3, n_dims, n_offs, nr, pos, freq_scale, freq_base, + ext_factor, attn_factor, corr_dims, freq_factors, sections, is_imrope, + row_indices, set_rows_stride, inplace, stream); + } else if (src0->type == GGML_TYPE_F32 && dst_type == GGML_TYPE_F16) { + rope_multi_cuda((const float *) src0_d, (half *) dst_d, ne00, ne01, ne02, s01, s02, + s03, s1, s2, s3, n_dims, n_offs, nr, pos, freq_scale, freq_base, + ext_factor, attn_factor, corr_dims, freq_factors, sections, is_imrope, + row_indices, set_rows_stride, inplace, stream); + } else if (src0->type == GGML_TYPE_F16 && dst_type == GGML_TYPE_F16) { + rope_multi_cuda((const half *) src0_d, (half *) dst_d, ne00, ne01, ne02, s01, s02, + s03, s1, s2, s3, n_dims, n_offs, nr, pos, freq_scale, freq_base, + ext_factor, attn_factor, corr_dims, freq_factors, sections, is_imrope, + row_indices, set_rows_stride, inplace, stream); } else { GGML_ABORT("fatal error"); } diff --git a/ggml/src/ggml-cuda/scale.cu b/ggml/src/ggml-cuda/scale.cu index 5648b9261cef..d53f906c5313 100644 --- a/ggml/src/ggml-cuda/scale.cu +++ b/ggml/src/ggml-cuda/scale.cu @@ -3,23 +3,45 @@ #define MAX_GRIDDIM_X 0x7FFFFFFF +// src and dst may be views: rows are contiguous, dims 1..3 follow the strides (in elements). template -static __global__ void scale_f32(const T * x, T * dst, const float scale, const float bias, const int64_t nelements) { +static __global__ void scale_f32(const T * x, T * dst, const float scale, const float bias, const uint32_t k, + const uint3 ne0, const uint3 ne1, const uint3 ne2, + const uint32_t s01, const uint32_t s02, const uint32_t s03, + const uint32_t s1, const uint32_t s2, const uint32_t s3) { ggml_cuda_pdl_lc(); - int64_t tid = (int64_t)blockIdx.x * (int64_t)blockDim.x + (int64_t)threadIdx.x; - int64_t stride = (int64_t)blockDim.x * (int64_t)gridDim.x; + const uint32_t i = blockIdx.x * blockDim.x + threadIdx.x; ggml_cuda_pdl_sync(); - for (int64_t i = tid; i < nelements; i += stride) { - dst[i] = ggml_cuda_cast(scale * ggml_cuda_cast(x[i]) + bias); + if (i >= k) { + return; } + + const uint2 d0 = fast_div_modulo(i, ne0); // + const uint2 d1 = fast_div_modulo(d0.x, ne1); // + const uint2 d2 = fast_div_modulo(d1.x, ne2); // + + const size_t i_src = d0.y + size_t(d1.y)*s01 + size_t(d2.y)*s02 + size_t(d2.x)*s03; + const size_t i_dst = d0.y + size_t(d1.y)*s1 + size_t(d2.y)*s2 + size_t(d2.x)*s3; + + dst[i_dst] = ggml_cuda_cast(scale * ggml_cuda_cast(x[i_src]) + bias); } template -static void scale_f32_cuda(const T * x, T * dst, const float scale, const float bias, const int64_t nelements, cudaStream_t stream) { - const int64_t num_blocks = (nelements + CUDA_SCALE_BLOCK_SIZE - 1) / CUDA_SCALE_BLOCK_SIZE; +static void scale_f32_cuda(const T * x, T * dst, const float scale, const float bias, const ggml_tensor * src0, const ggml_tensor * t, cudaStream_t stream) { + const int64_t k = ggml_nelements(src0); + const size_t ts = sizeof(T); + GGML_ASSERT(k <= std::numeric_limits::max()); + + const uint3 ne0 = init_fastdiv_values(src0->ne[0]); + const uint3 ne1 = init_fastdiv_values(src0->ne[1]); + const uint3 ne2 = init_fastdiv_values(src0->ne[2]); + + const int64_t num_blocks = (k + CUDA_SCALE_BLOCK_SIZE - 1) / CUDA_SCALE_BLOCK_SIZE; const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(MIN(MAX_GRIDDIM_X, num_blocks), CUDA_SCALE_BLOCK_SIZE, 0, stream); - ggml_cuda_kernel_launch(scale_f32, launch_params, x, dst, scale, bias, nelements); + ggml_cuda_kernel_launch(scale_f32, launch_params, x, dst, scale, bias, (uint32_t) k, ne0, ne1, ne2, + src0->nb[1]/ts, src0->nb[2]/ts, src0->nb[3]/ts, + t->nb[1]/ts, t->nb[2]/ts, t->nb[3]/ts); } void ggml_cuda_op_scale(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -28,6 +50,7 @@ void ggml_cuda_op_scale(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_BF16); GGML_ASSERT(dst->type == src0->type); + GGML_ASSERT(ggml_is_contiguous_rows(src0) && ggml_is_contiguous_rows(dst)); float scale; float bias; @@ -35,8 +58,8 @@ void ggml_cuda_op_scale(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { memcpy(&bias, (float *) dst->op_params + 1, sizeof(float)); if (src0->type == GGML_TYPE_BF16) { - scale_f32_cuda((const nv_bfloat16 *) src0->data, (nv_bfloat16 *) dst->data, scale, bias, ggml_nelements(src0), stream); + scale_f32_cuda((const nv_bfloat16 *) src0->data, (nv_bfloat16 *) dst->data, scale, bias, src0, dst, stream); } else { - scale_f32_cuda((const float *) src0->data, (float *) dst->data, scale, bias, ggml_nelements(src0), stream); + scale_f32_cuda((const float *) src0->data, (float *) dst->data, scale, bias, src0, dst, stream); } } diff --git a/ggml/src/ggml-cuda/ssm-conv.cu b/ggml/src/ggml-cuda/ssm-conv.cu index d1052772de39..24fb2a4e5a69 100644 --- a/ggml/src/ggml-cuda/ssm-conv.cu +++ b/ggml/src/ggml-cuda/ssm-conv.cu @@ -174,9 +174,10 @@ static void ssm_conv_f32_cuda(const float * src0, const float * src1, const floa case 3: launch_kernel(std::integral_constant{}); break; case 4: launch_kernel(std::integral_constant{}); break; case 5: launch_kernel(std::integral_constant{}); break; + case 7: launch_kernel(std::integral_constant{}); break; case 9: launch_kernel(std::integral_constant{}); break; case 15: launch_kernel(std::integral_constant{}); break; - default: GGML_ABORT("Only support kernel sizes 3, 4, 5, 9, 15 right now."); + default: GGML_ABORT("Only support kernel sizes 3, 4, 5, 7, 9, 15 right now."); } } diff --git a/ggml/src/ggml-cuda/top-k-mask.cu b/ggml/src/ggml-cuda/top-k-mask.cu new file mode 100644 index 000000000000..9ff995240085 --- /dev/null +++ b/ggml/src/ggml-cuda/top-k-mask.cu @@ -0,0 +1,141 @@ +#include "top-k-mask.cuh" +#include "convert.cuh" + +#define CUDA_TOP_K_MASK_BLOCK_SIZE 512 + +// one block per row: fill the row with -inf, then copy the mask cells of the live picks and the extra cells +template +static __global__ void top_k_mask_kernel( + const T * mask, const int32_t * top_k, const float * score, const int32_t * blocks, const int32_t * extra, T * dst, + const int64_t n_kv, const int64_t ne1, const int64_t ne2, + const int64_t m1, const int64_t m2, const int64_t m3, + const int64_t n_top, const int64_t n_pick, const int64_t n_blk, const int64_t n_extra, + const int64_t sm1, const int64_t sm2, const int64_t sm3, + const int64_t sd1, const int64_t sd2, const int64_t sd3, + const int64_t sk0, const int64_t sk1, const int64_t sk2, const int64_t sk3, + const int64_t ss0, const int64_t ss1, const int64_t ss2, const int64_t ss3, + const int64_t sb0, const int64_t sb1, + const int64_t se0, const int64_t se1, const int64_t se2, const int64_t se3, + const bool vec) { + ggml_cuda_pdl_lc(); + + const int64_t ir = blockIdx.x; + const int64_t i1 = ir % ne1; + const int64_t i2 = (ir / ne1) % ne2; + const int64_t i3 = ir / (ne1*ne2); + + const T * mask_row = mask + (i1 % m1)*sm1 + (i2 % m2)*sm2 + (i3 % m3)*sm3; + T * dst_row = dst + i1*sd1 + i2*sd2 + i3*sd3; + const int32_t * top_k_row = top_k + i1*sk1 + i2*sk2 + i3*sk3; + + ggml_cuda_pdl_sync(); + + const T ninf = ggml_cuda_cast(-INFINITY); + if (vec) { + constexpr int nv = sizeof(int4)/sizeof(T); + T fill[nv]; +#pragma unroll + for (int j = 0; j < nv; ++j) { + fill[j] = ninf; + } + const int4 fill4 = *(const int4 *) fill; + for (int64_t i = threadIdx.x; i < n_kv/nv; i += blockDim.x) { + ((int4 *) dst_row)[i] = fill4; + } + } else { + for (int64_t i = threadIdx.x; i < n_kv; i += blockDim.x) { + dst_row[i] = ninf; + } + } + + __syncthreads(); + + // one thread per pick or extra cell; cells kept twice get the same value + for (int64_t i = threadIdx.x; i < n_top + n_extra; i += blockDim.x) { + if (i >= n_top) { + const int32_t c = extra[(i - n_top)*se0 + i1*se1 + i2*se2 + i3*se3]; + if (c >= 0 && c < n_kv) { + dst_row[c] = mask_row[c]; + } + continue; + } + + const int32_t p = top_k_row[i*sk0]; + if (p < 0 || p >= n_pick) { + continue; + } + if (score && !(score[p*ss0 + i1*ss1 + i2*ss2 + i3*ss3] > -INFINITY)) { + continue; + } + if (!blocks) { + if (p < n_kv) { + dst_row[p] = mask_row[p]; + } + continue; + } + for (int64_t k = 0; k < n_blk; ++k) { + const int32_t c = blocks[k*sb0 + p*sb1]; + if (c >= 0 && c < n_kv) { + dst_row[c] = mask_row[c]; + } + } + } +} + +template +static void top_k_mask_cuda(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * mask = dst->src[0]; + const ggml_tensor * top_k = dst->src[1]; + const ggml_tensor * score = dst->src[2]; + const ggml_tensor * blocks = dst->src[3]; + const ggml_tensor * extra = dst->src[4]; + + const int64_t n_kv = mask->ne[0]; + + GGML_ASSERT(dst->nb[0] == sizeof(T) && mask->nb[0] == sizeof(T)); + GGML_ASSERT(dst->nb[1] % sizeof(T) == 0 && mask->nb[1] % sizeof(T) == 0); + + // 16-byte stores need every dst row aligned + const bool vec = (n_kv*sizeof(T)) % sizeof(int4) == 0 && + dst->nb[1] % sizeof(int4) == 0 && dst->nb[2] % sizeof(int4) == 0 && dst->nb[3] % sizeof(int4) == 0 && + (uintptr_t) dst->data % sizeof(int4) == 0; + + const int64_t n_pick = blocks ? blocks->ne[1] : score ? score->ne[0] : n_kv; + + const size_t si = sizeof(int32_t); + const size_t sf = sizeof(float); + + const dim3 block_dims(CUDA_TOP_K_MASK_BLOCK_SIZE, 1, 1); + const dim3 grid_dims(ggml_nrows(dst), 1, 1); + const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(grid_dims, block_dims, 0, ctx.stream()); + + ggml_cuda_kernel_launch(top_k_mask_kernel, launch_params, + (const T *) mask->data, (const int32_t *) top_k->data, + score ? (const float *) score->data : nullptr, + blocks ? (const int32_t *) blocks->data : nullptr, + extra ? (const int32_t *) extra->data : nullptr, + (T *) dst->data, + n_kv, dst->ne[1], dst->ne[2], + mask->ne[1], mask->ne[2], mask->ne[3], + top_k->ne[0], n_pick, blocks ? blocks->ne[0] : 1, extra ? extra->ne[0] : 0, + mask->nb[1]/sizeof(T), mask->nb[2]/sizeof(T), mask->nb[3]/sizeof(T), + dst->nb[1]/sizeof(T), dst->nb[2]/sizeof(T), dst->nb[3]/sizeof(T), + top_k->nb[0]/si, top_k->nb[1]/si, top_k->nb[2]/si, top_k->nb[3]/si, + score ? score->nb[0]/sf : 0, score ? score->nb[1]/sf : 0, score ? score->nb[2]/sf : 0, score ? score->nb[3]/sf : 0, + blocks ? blocks->nb[0]/si : 0, blocks ? blocks->nb[1]/si : 0, + extra ? extra->nb[0]/si : 0, extra ? extra->nb[1]/si : 0, extra ? extra->nb[2]/si : 0, extra ? extra->nb[3]/si : 0, + vec); +} + +void ggml_cuda_op_top_k_mask(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + switch (dst->type) { + case GGML_TYPE_F16: + top_k_mask_cuda(ctx, dst); + break; + case GGML_TYPE_F32: + top_k_mask_cuda(ctx, dst); + break; + default: + GGML_ABORT("unsupported type"); + } +} diff --git a/ggml/src/ggml-cuda/top-k-mask.cuh b/ggml/src/ggml-cuda/top-k-mask.cuh new file mode 100644 index 000000000000..930d6667bbe1 --- /dev/null +++ b/ggml/src/ggml-cuda/top-k-mask.cuh @@ -0,0 +1,3 @@ +#include "common.cuh" + +void ggml_cuda_op_top_k_mask(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/topk-moe.cu b/ggml/src/ggml-cuda/topk-moe.cu index d015e7ddefa5..a93d3a9785d8 100644 --- a/ggml/src/ggml-cuda/topk-moe.cu +++ b/ggml/src/ggml-cuda/topk-moe.cu @@ -11,6 +11,8 @@ struct topk_moe_config { bool use_sqrt_softplus; bool with_norm; bool delayed_softmax; + int n_groups; + int n_group_used; }; // Warp-local softmax used for both the pre-top-k logits and the post-top-k delayed path. @@ -74,10 +76,57 @@ __device__ void sqrt_softplus_warp_inplace(float (&vals)[experts_per_thread], co for (int i = 0; i < experts_per_thread; i++) { const int idx = lane + i * WARP_SIZE; const bool active = !use_limit || (idx < limit); - vals[i] = active ? sqrtf(vals[i] > 20.0f ? vals[i] : logf(1.0f + expf(vals[i]))) : -INFINITY; + vals[i] = active ? sqrtf(vals[i] > 20.0f ? vals[i] : log1pf(expf(vals[i]))) : -INFINITY; } } +#if !defined(GGML_USE_HIP) || HIP_VERSION >= 60300000 +// Set -inf for experts outside the top n_group_used groups. Group score is the sum of its top-2 experts (DeepSeek V3). +template +__device__ void group_mask_warp_inplace(float (&vals)[experts_per_thread], const int n_groups, const int n_group_used, const int lane) { + const int n_per_group = n_experts / n_groups; + + float score = -INFINITY; // lane g holds the score of group g + for (int g = 0; g < n_groups; g++) { + float top1 = -INFINITY; + float top2 = -INFINITY; +#pragma unroll + for (int i = 0; i < experts_per_thread; i++) { + if ((i * WARP_SIZE + lane) / n_per_group == g) { + top2 = fmaxf(top2, fminf(top1, vals[i])); + top1 = fmaxf(top1, vals[i]); + } + } +#pragma unroll + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) { + const float o1 = __shfl_xor_sync(0xFFFFFFFF, top1, offset, WARP_SIZE); + const float o2 = __shfl_xor_sync(0xFFFFFFFF, top2, offset, WARP_SIZE); + top2 = fmaxf(fminf(top1, o1), fmaxf(top2, o2)); + top1 = fmaxf(top1, o1); + } + if (lane == g) { + score = top1 + top2; + } + } + + // rank of each group, lower index wins ties + int rank = 0; + for (int g = 0; g < n_groups; g++) { + const float other = __shfl_sync(0xFFFFFFFF, score, g, WARP_SIZE); + rank += other > score || (other == score && g < lane); + } + const auto keep = __ballot_sync(0xFFFFFFFFULL, lane < n_groups && rank < n_group_used); + +#pragma unroll + for (int i = 0; i < experts_per_thread; i++) { + const int g = (i * WARP_SIZE + lane) / n_per_group; + if (g >= n_groups || !((keep >> g) & 1)) { + vals[i] = -INFINITY; + } + } +} +#endif // !defined(GGML_USE_HIP) || HIP_VERSION >= 60300000 + /* This kernel does the following: 1. optionally softmax over the logits per token [n_experts, n_tokens] @@ -171,6 +220,17 @@ __global__ void topk_moe_cuda(const float * logits, } } +#if !defined(GGML_USE_HIP) || HIP_VERSION >= 60300000 + // without bias, masking wt is safe: the matcher ensures the kept groups hold all used experts + if (config.n_groups > 0) { + if constexpr (has_bias) { + group_mask_warp_inplace(selection_wt, config.n_groups, config.n_group_used, threadIdx.x); + } else { + group_mask_warp_inplace(wt, config.n_groups, config.n_group_used, threadIdx.x); + } + } +#endif // !defined(GGML_USE_HIP) || HIP_VERSION >= 60300000 + //at this point, each thread holds either a portion of the softmax distribution //or the raw logits. We do the argmax reduce over n_expert_used, each time marking //the expert weight as -inf to exclude from the next iteration @@ -297,6 +357,10 @@ static void launch_topk_moe_cuda(ggml_backend_cuda_context & ctx, cudaStream_t stream = ctx.stream(); const ggml_cuda_kernel_launch_params launch_params = ggml_cuda_kernel_launch_params(grid_dims, block_dims, 0, stream); +#if defined(GGML_USE_HIP) && HIP_VERSION < 60300000 + GGML_ASSERT(config.n_groups == 0 && "expert groups fusion is not supported on this HIP version"); +#endif + switch (n_expert) { case 1: ggml_cuda_kernel_launch(topk_moe_cuda<1, has_bias>, launch_params, @@ -338,6 +402,10 @@ static void launch_topk_moe_cuda(ggml_backend_cuda_context & ctx, ggml_cuda_kernel_launch(topk_moe_cuda<288, has_bias>, launch_params, logits, weights, ids, bias, n_rows, n_expert_used, clamp_val, scale_val, config); break; + case 384: // DeepSeek V4.1 + ggml_cuda_kernel_launch(topk_moe_cuda<384, has_bias>, launch_params, + logits, weights, ids, bias, n_rows, n_expert_used, clamp_val, scale_val, config); + break; case 512: ggml_cuda_kernel_launch(topk_moe_cuda<512, has_bias>, launch_params, logits, weights, ids, bias, n_rows, n_expert_used, clamp_val, scale_val, config); @@ -389,6 +457,8 @@ void ggml_cuda_op_topk_moe(ggml_backend_cuda_context & ctx, config.use_sqrt_softplus = args.sqrt_softplus; config.with_norm = with_norm; config.delayed_softmax = args.delayed_softmax; + config.n_groups = args.n_groups; + config.n_group_used = args.n_group_used; if (bias) { launch_topk_moe_cuda(ctx, logits_d, weights_d, ids_d, bias_d, n_rows, n_experts, n_expert_used, clamp_val, @@ -406,7 +476,7 @@ bool ggml_cuda_should_use_topk_moe(const ggml_tensor * gating_op, // must match an instantiation of launch_topk_moe_cuda: a power of 2 up to 512, // or one of the non-power-of-2 expert counts of supported models const int n_expert = ids->nb[1] / ids->nb[0]; - if (((n_expert & (n_expert - 1)) != 0 || n_expert > 512) && n_expert != 288 && n_expert != 576) { + if (((n_expert & (n_expert - 1)) != 0 || n_expert > 512) && n_expert != 288 && n_expert != 384 && n_expert != 576) { return false; } diff --git a/ggml/src/ggml-cuda/topk-moe.cuh b/ggml/src/ggml-cuda/topk-moe.cuh index 061b37e2971e..3637500ff99d 100644 --- a/ggml/src/ggml-cuda/topk-moe.cuh +++ b/ggml/src/ggml-cuda/topk-moe.cuh @@ -14,6 +14,8 @@ struct ggml_cuda_topk_moe_args { bool prob_bias{}; bool norm{}; bool scale{}; + int n_groups{}; // > 0: pick experts only from the top n_group_used expert groups + int n_group_used{}; }; void ggml_cuda_op_topk_moe(ggml_backend_cuda_context & ctx, diff --git a/ggml/src/ggml-cuda/unary.cu b/ggml/src/ggml-cuda/unary.cu index af839acd7456..b3b6aa48d3ac 100644 --- a/ggml/src/ggml-cuda/unary.cu +++ b/ggml/src/ggml-cuda/unary.cu @@ -91,7 +91,7 @@ static __device__ __forceinline__ float op_expm1(float x) { } static __device__ __forceinline__ float op_softplus(float x) { - return (x > 20.0f) ? x : logf(1.0f + expf(x)); + return (x > 20.0f) ? x : log1pf(expf(x)); } static __device__ __forceinline__ float op_elu(float x) { diff --git a/ggml/src/ggml-cuda/unary.cuh b/ggml/src/ggml-cuda/unary.cuh index 04f3af6443a7..c6ffdb9d63e7 100644 --- a/ggml/src/ggml-cuda/unary.cuh +++ b/ggml/src/ggml-cuda/unary.cuh @@ -121,3 +121,18 @@ __device__ __forceinline__ float ggml_cuda_op_swiglu_clamp_single(float gate, fl return ggml_cuda_op_silu_single(gate) * up; } + +__device__ __forceinline__ float ggml_cuda_op_glu_single(ggml_glu_op op, float gate, float up, float limit) { + switch (op) { + case GGML_GLU_OP_SWIGLU: + return up * ggml_cuda_op_silu_single(gate); + case GGML_GLU_OP_GEGLU: + return up * ggml_cuda_op_gelu_single(gate); + case GGML_GLU_OP_SWIGLU_OAI: + return ggml_cuda_op_swiglu_oai_single(gate, up); + case GGML_GLU_OP_SWIGLU_CLAMP: + return ggml_cuda_op_swiglu_clamp_single(gate, up, limit); + default: + return up * gate; + } +} diff --git a/ggml/src/ggml-cuda/vecdotq.cuh b/ggml/src/ggml-cuda/vecdotq.cuh index 94a095de515d..d819db935e4b 100644 --- a/ggml/src/ggml-cuda/vecdotq.cuh +++ b/ggml/src/ggml-cuda/vecdotq.cuh @@ -40,18 +40,18 @@ static __device__ __forceinline__ int2 get_int_from_table_16(const int & q4, con const uint32_t q_odd = (q4 >> 4); // Perform lookups in the lower half of the table (indices 0-7). - uint32_t v_even_low = __builtin_amdgcn_perm(values[1], values[0], q_even & 0x07070707); - uint32_t v_odd_low = __builtin_amdgcn_perm(values[1], values[0], q_odd & 0x07070707); + uint32_t v_even_low = ggml_hip_perm(values[1], values[0], q_even & 0x07070707); + uint32_t v_odd_low = ggml_hip_perm(values[1], values[0], q_odd & 0x07070707); // Perform lookups in the upper half of the table (indices 8-15). - uint32_t v_even_high = __builtin_amdgcn_perm(values[3], values[2], q_even & 0x07070707); - uint32_t v_odd_high = __builtin_amdgcn_perm(values[3], values[2], q_odd & 0x07070707); + uint32_t v_even_high = ggml_hip_perm(values[3], values[2], q_even & 0x07070707); + uint32_t v_odd_high = ggml_hip_perm(values[3], values[2], q_odd & 0x07070707); // Select between the low and high results based on the MSB of each index nibble. uint32_t mask_even = 0x03020100 | ((q_even & 0x08080808) >> 1); - uint32_t res_x = __builtin_amdgcn_perm(v_even_high, v_even_low, mask_even); + uint32_t res_x = ggml_hip_perm(v_even_high, v_even_low, mask_even); uint32_t mask_odd = 0x03020100 | ((q_odd & 0x08080808) >> 1); - uint32_t res_y = __builtin_amdgcn_perm(v_odd_high, v_odd_low, mask_odd); + uint32_t res_y = ggml_hip_perm(v_odd_high, v_odd_low, mask_odd); return make_int2(res_x, res_y); #elif !defined(GGML_USE_MUSA) @@ -418,17 +418,17 @@ static __device__ __forceinline__ int2 rocmfp4_get_int_from_codebook_16(const in const uint32_t q_even = q4; const uint32_t q_odd = q4 >> 4; - const uint32_t v_even_low = __builtin_amdgcn_perm(values1, values0, q_even & 0x07070707u); - const uint32_t v_odd_low = __builtin_amdgcn_perm(values1, values0, q_odd & 0x07070707u); - const uint32_t v_even_high = __builtin_amdgcn_perm(values3, values2, q_even & 0x07070707u); - const uint32_t v_odd_high = __builtin_amdgcn_perm(values3, values2, q_odd & 0x07070707u); + const uint32_t v_even_low = ggml_hip_perm(values1, values0, q_even & 0x07070707u); + const uint32_t v_odd_low = ggml_hip_perm(values1, values0, q_odd & 0x07070707u); + const uint32_t v_even_high = ggml_hip_perm(values3, values2, q_even & 0x07070707u); + const uint32_t v_odd_high = ggml_hip_perm(values3, values2, q_odd & 0x07070707u); const uint32_t mask_even = 0x03020100u | ((q_even & 0x08080808u) >> 1); const uint32_t mask_odd = 0x03020100u | ((q_odd & 0x08080808u) >> 1); return make_int2( - __builtin_amdgcn_perm(v_even_high, v_even_low, mask_even), - __builtin_amdgcn_perm(v_odd_high, v_odd_low, mask_odd)); + ggml_hip_perm(v_even_high, v_even_low, mask_even), + ggml_hip_perm(v_odd_high, v_odd_low, mask_odd)); #else return get_int_from_table_16(q4, fallback_table); #endif @@ -476,12 +476,12 @@ static __device__ __forceinline__ float vec_dot_rocmfp4_fast_q8_1( return __low2float(bq8_1->ds) * rocmfp4_ue4m3_to_fp32_half_finite(bq4->e) * sumi; } -#define VDR_Q2_K_Q8_1_MMVQ 1 +#define VDR_Q2_K_Q8_1_MMVQ 2 #define VDR_Q2_K_Q8_1_MMQ 4 // contiguous v/x values static __device__ __forceinline__ float vec_dot_q2_K_q8_1_impl_mmvq( - const int & v, const int * __restrict__ u, const uint8_t * __restrict__ scales, + const int * __restrict__ v, const int * __restrict__ u, const int * __restrict__ scales, const half2 & dm2, const float * __restrict__ d8) { float sumf_d = 0.0f; @@ -489,17 +489,20 @@ static __device__ __forceinline__ float vec_dot_q2_K_q8_1_impl_mmvq( #pragma unroll for (int i = 0; i < QR2_K; ++i) { - const int sc = scales[2*i]; + const int sc = scales[i/2] >> (16*(i%2)); - const int vi = (v >> (2*i)) & 0x03030303; + int sumi_d = 0; + int sumi_m = 0; +#pragma unroll + for (int j = 0; j < VDR_Q2_K_Q8_1_MMVQ; ++j) { + const int vi = (v[j] >> (2*i)) & 0x03030303; - sumf_d += d8[i] * (ggml_cuda_dp4a(vi, u[i], 0) * (sc & 0xF)); // SIMD dot product + sumi_d = ggml_cuda_dp4a(vi, u[VDR_Q2_K_Q8_1_MMVQ*i + j], sumi_d); // SIMD dot product + sumi_m = ggml_cuda_dp4a(0x01010101, u[VDR_Q2_K_Q8_1_MMVQ*i + j], sumi_m); // sum of q8_1 values + } - // fill int with 4x m - int m = sc >> 4; - m |= m << 8; - m |= m << 16; - sumf_m += d8[i] * ggml_cuda_dp4a(m, u[i], 0); // multiply constant q2_K part with sum of q8_1 values + sumf_d += d8[i] * (sumi_d * (sc & 0xF)); + sumf_m += d8[i] * (sumi_m * ((sc >> 4) & 0xF)); // multiply constant q2_K part with sum of q8_1 values } const float2 dm2f = __half22float2(dm2); @@ -559,37 +562,35 @@ static __device__ __forceinline__ float vec_dot_q2_K_q8_1_impl_mmq( return sumf + d8*sumf_d8; } -#define VDR_Q3_K_Q8_1_MMVQ 1 +#define VDR_Q3_K_Q8_1_MMVQ 2 #define VDR_Q3_K_Q8_1_MMQ 2 // contiguous v/x values static __device__ __forceinline__ float vec_dot_q3_K_q8_1_impl_mmvq( - const int & vl, const int & vh, const int * __restrict__ u, const uint8_t * __restrict__ scales, - const int & scale_offset, const float & d3, const float * __restrict__ d8) { + const int * __restrict__ vl, const int * __restrict__ vh, const int * __restrict__ u, const int * __restrict__ scales, + const float & d3, const float * __restrict__ d8) { float sumf = 0.0f; #pragma unroll for (int i = 0; i < QR3_K; ++i) { - const int isc = scale_offset + 2*i; - - const int isc_low = isc % (QK_K/32); - const int sc_shift_low = 4 * (isc / (QK_K/32)); - const int sc_low = (scales[isc_low] >> sc_shift_low) & 0xF; - - const int isc_high = isc % (QK_K/64); - const int sc_shift_high = 2 * (isc / (QK_K/64)); - const int sc_high = ((scales[(QK_K/32) + isc_high] >> sc_shift_high) & 3) << 4; + // 4 low bits from scales[0..7], 2 high bits from scales[8..11] + const int sc_low = (scales[i/2] >> (16*(i%2))) & 0x0F; + const int sc_high = (scales[2] >> (16*(i%2) + 2*(i/2))) & 0x03; + const int sc = (sc_low | (sc_high << 4)) - 32; - const int sc = (sc_low | sc_high) - 32; - - const int vil = (vl >> (2*i)) & 0x03030303; - - const int vih = ((vh >> i) << 2) & 0x04040404; + int sumi = 0; +#pragma unroll + for (int j = 0; j < VDR_Q3_K_Q8_1_MMVQ; ++j) { + const int vil = (vl[j] >> (2*i)) & 0x03030303; + const int vih = ((vh[j] >> i) << 2) & 0x04040404; - const int vi = __vsub4(vil, vih); + // (vil | vih) - 4 for each byte, the - 4 is done by the second dp4a + sumi = ggml_cuda_dp4a(vil | vih, u[VDR_Q3_K_Q8_1_MMVQ*i + j], sumi); // SIMD dot product + sumi = ggml_cuda_dp4a(0xFCFCFCFC, u[VDR_Q3_K_Q8_1_MMVQ*i + j], sumi); + } - sumf += d8[i] * (ggml_cuda_dp4a(vi, u[i], 0) * sc); // SIMD dot product + sumf += d8[i] * (sumi * sc); } return d3 * sumf; @@ -832,12 +833,12 @@ static __device__ __forceinline__ float vec_dot_q5_K_q8_1_impl_mmq( return dm4f.x*sumf_d - dm4f.y*sumf_m; } -#define VDR_Q6_K_Q8_1_MMVQ 1 +#define VDR_Q6_K_Q8_1_MMVQ 2 #define VDR_Q6_K_Q8_1_MMQ 8 // contiguous v/x values static __device__ __forceinline__ float vec_dot_q6_K_q8_1_impl_mmvq( - const int & vl, const int & vh, const int * __restrict__ u, const int8_t * __restrict__ scales, + const int * __restrict__ vl, const int * __restrict__ vh, const int * __restrict__ u, const int8_t * __restrict__ scales, const float & d, const float * __restrict__ d8) { float sumf = 0.0f; @@ -846,13 +847,18 @@ static __device__ __forceinline__ float vec_dot_q6_K_q8_1_impl_mmvq( for (int i = 0; i < QR6_K; ++i) { const int sc = scales[4*i]; - const int vil = (vl >> (4*i)) & 0x0F0F0F0F; - - const int vih = ((vh >> (4*i)) << 4) & 0x30303030; + int sumi = 0; +#pragma unroll + for (int j = 0; j < VDR_Q6_K_Q8_1_MMVQ; ++j) { + const int vil = (vl[j] >> (4*i)) & 0x0F0F0F0F; + const int vih = ((vh[j] >> (4*i)) << 4) & 0x30303030; - const int vi = __vsub4((vil | vih), 0x20202020); // vi = (vil | vih) - 32 + // (vil | vih) - 32 for each byte, the - 32 is done by the second dp4a + sumi = ggml_cuda_dp4a(vil | vih, u[VDR_Q6_K_Q8_1_MMVQ*i + j], sumi); // SIMD dot product + sumi = ggml_cuda_dp4a(0xE0E0E0E0, u[VDR_Q6_K_Q8_1_MMVQ*i + j], sumi); + } - sumf += d8[i] * (ggml_cuda_dp4a(vi, u[i], 0) * sc); // SIMD dot product + sumf += d8[i] * (sumi * sc); } return d*sumf; @@ -931,6 +937,25 @@ static __device__ __forceinline__ float vec_dot_q1_0_q8_1( const int u2 = get_int_b4(bq8_1_chunk->qs, j*4+2); const int u3 = get_int_b4(bq8_1_chunk->qs, j*4+3); +#if defined(GGML_USE_HIP) + const uint32_t q_bits = (uint16_t) q; + + // Expand each group of four Q1_0 bits into byte selectors for v_perm_b32. + const uint32_t q0_bits = q_bits >> 0; + const uint32_t q1_bits = q_bits >> 4; + const uint32_t q2_bits = q_bits >> 8; + const uint32_t q3_bits = q_bits >> 12; + + const uint32_t q0_indices = (q0_bits & 0x01) | ((q0_bits & 0x02) << 7) | ((q0_bits & 0x04) << 14) | ((q0_bits & 0x08) << 21); + const uint32_t q1_indices = (q1_bits & 0x01) | ((q1_bits & 0x02) << 7) | ((q1_bits & 0x04) << 14) | ((q1_bits & 0x08) << 21); + const uint32_t q2_indices = (q2_bits & 0x01) | ((q2_bits & 0x02) << 7) | ((q2_bits & 0x04) << 14) | ((q2_bits & 0x08) << 21); + const uint32_t q3_indices = (q3_bits & 0x01) | ((q3_bits & 0x02) << 7) | ((q3_bits & 0x04) << 14) | ((q3_bits & 0x08) << 21); + + const int v0 = ggml_hip_perm(0x000001FF, 0x000001FF, q0_indices); + const int v1 = ggml_hip_perm(0x000001FF, 0x000001FF, q1_indices); + const int v2 = ggml_hip_perm(0x000001FF, 0x000001FF, q2_indices); + const int v3 = ggml_hip_perm(0x000001FF, 0x000001FF, q3_indices); +#else // unpack crumbs into nibble indices const int n0 = __byte_perm(0x11100100, 0x11100100, q >> 0); // [0, 1, 4, 5] [ 8, 9, 12, 13] const int n1 = __byte_perm(0x11100100, 0x11100100, q >> 2); // [2, 3, 6, 7] [10, 11, 14, 15] @@ -944,6 +969,7 @@ static __device__ __forceinline__ float vec_dot_q1_0_q8_1( const int v1 = __byte_perm(s0, s1, 0x7632); const int v2 = __byte_perm(s2, s3, 0x5410); const int v3 = __byte_perm(s2, s3, 0x7632); +#endif // defined(GGML_USE_HIP) sumi = ggml_cuda_dp4a(v0, u0, sumi); sumi = ggml_cuda_dp4a(v1, u1, sumi); @@ -983,8 +1009,8 @@ static __device__ __forceinline__ float vec_dot_q2_0_q8_1( const uint32_t qx_indices = (q & 0x03) | ((q & 0x0C) << 6) | ((q & 0x30) << 12) | ((q & 0xC0) << 18); const uint32_t qy_bits = q >> 8; const uint32_t qy_indices = (qy_bits & 0x03) | ((qy_bits & 0x0C) << 6) | ((qy_bits & 0x30) << 12) | ((qy_bits & 0xC0) << 18); - const int qx = __builtin_amdgcn_perm(0x020100FF, 0x020100FF, qx_indices); - const int qy = __builtin_amdgcn_perm(0x020100FF, 0x020100FF, qy_indices); + const int qx = ggml_hip_perm(0x020100FF, 0x020100FF, qx_indices); + const int qy = ggml_hip_perm(0x020100FF, 0x020100FF, qy_indices); #else // unpack even and odd crumbs into byte values const int qe = __byte_perm(0x020100FF, 0x020100FF, q >> 0); @@ -1102,18 +1128,31 @@ static __device__ __forceinline__ float vec_dot_q2_K_q8_1( const block_q2_K * bq2_K = (const block_q2_K *) vbq + kbx; + // iqs is in 0,2..14, each 32 bytes of qs hold 4 q8_1 blocks (one per 2 bit shift) const int bq8_offset = QR2_K * (iqs / QI8_1); - const int scale_offset = iqs - iqs % QI8_1 + (iqs % QI8_1) / (QI8_1/2); + const int iqs8 = iqs % QI8_1; - const uint8_t * scales = bq2_K->scales + scale_offset; + int v[VDR_Q2_K_Q8_1_MMVQ]; +#pragma unroll + for (int j = 0; j < VDR_Q2_K_Q8_1_MMVQ; ++j) { + v[j] = get_int_b4(bq2_K->qs, iqs + j); + } - const int v = get_int_b4(bq2_K->qs, iqs); - int u[QR2_K]; + // scale of shift i is byte 2*i + (iqs8 >= QI8_1/2) of the 8 bytes for this half + const int sc_shift = 8 * (iqs8 / (QI8_1/2)); + int scales[2]; + scales[0] = get_int_b4(bq2_K->scales, 2*(iqs / QI8_1) + 0) >> sc_shift; + scales[1] = get_int_b4(bq2_K->scales, 2*(iqs / QI8_1) + 1) >> sc_shift; + + int u[VDR_Q2_K_Q8_1_MMVQ*QR2_K]; float d8[QR2_K]; #pragma unroll - for (int i = 0; i < QR2_K; ++ i) { - u[i] = get_int_b4(bq8_1[bq8_offset + i].qs, iqs % QI8_1); + for (int i = 0; i < QR2_K; ++i) { +#pragma unroll + for (int j = 0; j < VDR_Q2_K_Q8_1_MMVQ; ++j) { + u[VDR_Q2_K_Q8_1_MMVQ*i + j] = get_int_b4(bq8_1[bq8_offset + i].qs, iqs8 + j); + } d8[i] = __low2float(bq8_1[bq8_offset + i].ds); } @@ -1125,26 +1164,42 @@ static __device__ __forceinline__ float vec_dot_q3_K_q8_1( const block_q3_K * bq3_K = (const block_q3_K *) vbq + kbx; + // iqs is in 0,2..14, each 32 bytes of qs hold 4 q8_1 blocks (one per 2 bit shift) const int bq8_offset = QR3_K * (iqs / (QI3_K/2)); - const int scale_offset = iqs - iqs % QI8_1 + (iqs % QI8_1) / (QI8_1/2); + const int iqs8 = iqs % QI8_1; const float d = bq3_K->d; - const int vl = get_int_b2(bq3_K->qs, iqs); + int vl[VDR_Q3_K_Q8_1_MMVQ]; + int vh[VDR_Q3_K_Q8_1_MMVQ]; +#pragma unroll + for (int j = 0; j < VDR_Q3_K_Q8_1_MMVQ; ++j) { + vl[j] = get_int_b2(bq3_K->qs, iqs + j); + vh[j] = get_int_b2(bq3_K->hmask, iqs8 + j) >> bq8_offset; + } - // invert the mask with ~ so that a 0/1 results in 4/0 being subtracted - const int vh = ~get_int_b2(bq3_K->hmask, iqs % (QI3_K/2)) >> bq8_offset; + // sub-block 8*(iqs/8) + 2*i + (iqs8 >= QI8_1/2) for shift i: + // 4 low bits in nibble iqs/8 of bytes, 2 high bits at bit 4*(iqs/8) + 2*(i/2) of bytes 8..11 + const int sc_shift = 8 * (iqs8 / (QI8_1/2)) + 4 * (iqs / (QI3_K/2)); + int scales[3]; +#pragma unroll + for (int l = 0; l < 3; ++l) { + scales[l] = get_int_b2(bq3_K->scales, l) >> sc_shift; + } - int u[QR3_K]; + int u[VDR_Q3_K_Q8_1_MMVQ*QR3_K]; float d8[QR3_K]; #pragma unroll for (int i = 0; i < QR3_K; ++i) { - u[i] = get_int_b4(bq8_1[bq8_offset + i].qs, iqs % QI8_1); +#pragma unroll + for (int j = 0; j < VDR_Q3_K_Q8_1_MMVQ; ++j) { + u[VDR_Q3_K_Q8_1_MMVQ*i + j] = get_int_b4(bq8_1[bq8_offset + i].qs, iqs8 + j); + } d8[i] = __low2float(bq8_1[bq8_offset + i].ds); } - return vec_dot_q3_K_q8_1_impl_mmvq(vl, vh, u, bq3_K->scales, scale_offset, d, d8); + return vec_dot_q3_K_q8_1_impl_mmvq(vl, vh, u, scales, d, d8); } static __device__ __forceinline__ float vec_dot_q4_K_q8_1( @@ -1288,17 +1343,25 @@ static __device__ __forceinline__ float vec_dot_q6_K_q8_1( const int scale_offset = (QI6_K/4) * (iqs / (QI6_K/2)) + (iqs % (QI6_K/2)) / (QI6_K/8); const int vh_shift = 2 * ((iqs % (QI6_K/2)) / (QI6_K/4)); - const int vl = get_int_b2(bq6_K->ql, iqs); - const int vh = get_int_b2(bq6_K->qh, (QI6_K/4) * (iqs / (QI6_K/2)) + iqs % (QI6_K/4)) >> vh_shift; + int vl[VDR_Q6_K_Q8_1_MMVQ]; + int vh[VDR_Q6_K_Q8_1_MMVQ]; +#pragma unroll + for (int j = 0; j < VDR_Q6_K_Q8_1_MMVQ; ++j) { + vl[j] = get_int_b2(bq6_K->ql, iqs + j); + vh[j] = get_int_b2(bq6_K->qh, (QI6_K/4) * (iqs / (QI6_K/2)) + iqs % (QI6_K/4) + j) >> vh_shift; + } const int8_t * scales = bq6_K->scales + scale_offset; - int u[QR6_K]; + int u[VDR_Q6_K_Q8_1_MMVQ*QR6_K]; float d8[QR6_K]; #pragma unroll for (int i = 0; i < QR6_K; ++i) { - u[i] = get_int_b4(bq8_1[bq8_offset + 2*i].qs, iqs % QI8_1); +#pragma unroll + for (int j = 0; j < VDR_Q6_K_Q8_1_MMVQ; ++j) { + u[VDR_Q6_K_Q8_1_MMVQ*i + j] = get_int_b4(bq8_1[bq8_offset + 2*i].qs, iqs % QI8_1 + j); + } d8[i] = __low2float(bq8_1[bq8_offset + 2*i].ds); } diff --git a/ggml/src/ggml-cuda/vendors/hip.h b/ggml/src/ggml-cuda/vendors/hip.h index da7e3da0b9ca..0db8e97c97a1 100644 --- a/ggml/src/ggml-cuda/vendors/hip.h +++ b/ggml/src/ggml-cuda/vendors/hip.h @@ -216,9 +216,13 @@ #define RDNA4 #endif // defined(__GFX12__) -#if defined(__GFX11__) +#if defined(__gfx1170__) || defined(__gfx1171__) +#define RDNA4_M +#endif // defined(__gfx1170__) || defined(__gfx1171__) + +#if defined(__GFX11__) && !defined(RDNA4_M) #define RDNA3 -#endif // defined(__GFX11__) +#endif // defined(__GFX11__) && !defined(RDNA4_M) #if defined(__gfx1150__) || defined(__gfx1151__) || defined(__gfx1152__) || defined(__gfx1153__) #define RDNA3_5 @@ -237,9 +241,9 @@ #define RDNA1 #endif // defined(__gfx1010__) || defined(__gfx1012__) -#if defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) +#if defined(RDNA4) || defined(RDNA4_M) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) #define RDNA // For the entire family -#endif // defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) +#endif // defined(RDNA4) || defined(RDNA4_M) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) #ifndef __has_builtin #define __has_builtin(x) 0 @@ -254,6 +258,10 @@ typedef __hip_fp8_e4m3 __nv_fp8_e4m3; #define FP8_AVAILABLE #endif // HIP_VERSION >= 60300000 +#if HIP_VERSION < 70000000 +#define __ballot_sync(mask, var) __ballot(var) +#endif //HIP_VERSION < 70000000 + typedef int8_t int8x4_t __attribute__((ext_vector_type(4))); typedef uint8_t uint8x4_t __attribute__((ext_vector_type(4))); static __device__ __forceinline__ int __vsubss4(const int a, const int b) { @@ -311,3 +319,22 @@ static __device__ __forceinline__ unsigned int __vcmpne4(unsigned int a, unsigne return (ne_any_bit >> 7) * 0xff; } + +// v_perm_b32 with selector bytes in [0, 7]: 0-3 pick bytes of lo, 4-7 pick bytes of hi. +static __device__ __forceinline__ uint32_t ggml_hip_perm(const uint32_t hi, const uint32_t lo, const uint32_t sel) { +#if __has_builtin(__builtin_amdgcn_is_invocable) + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_perm)) { + return __builtin_amdgcn_perm(hi, lo, sel); + } + const uint64_t src = ((uint64_t) hi << 32) | lo; + uint32_t res = 0; +#pragma unroll + for (int i = 0; i < 4; ++i) { + const uint32_t byte_sel = (sel >> (8 * i)) & 0x07; + res |= (uint32_t) ((src >> (8 * byte_sel)) & 0xFF) << (8 * i); + } + return res; +#else + return __builtin_amdgcn_perm(hi, lo, sel); +#endif // __has_builtin(__builtin_amdgcn_is_invocable) +} diff --git a/ggml/src/ggml-et/ggml-et.cpp b/ggml/src/ggml-et/ggml-et.cpp index 54a6d166dcc3..cdd947c5221c 100644 --- a/ggml/src/ggml-et/ggml-et.cpp +++ b/ggml/src/ggml-et/ggml-et.cpp @@ -373,6 +373,9 @@ static const struct ggml_backend_buffer_i ggml_backend_et_buffer_i = { /* .cpy_tensor = */ ggml_backend_et_buffer_cpy_tensor, /* .clear = */ ggml_backend_et_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; static const char * ggml_backend_et_buffer_type_get_name(ggml_backend_buffer_type_t buft) { @@ -1270,7 +1273,7 @@ static bool ggml_backend_et_device_supports_op(ggml_backend_dev_t dev, const ggm case GGML_OP_FLASH_ATTN_EXT: if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] && (op->src[1]->type == GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_F16) && op->src[2] && - (op->src[2]->type == GGML_TYPE_F32 || op->src[2]->type == GGML_TYPE_F16) && op->src[4] == nullptr && + (op->src[2]->type == GGML_TYPE_F32 || op->src[2]->type == GGML_TYPE_F16) && op->src[4] == nullptr && op->src[5] == nullptr && ggml_is_contiguous_rows(op) && ggml_is_contiguous_rows(op->src[0])) { float max_bias = 0.0f; float logit_softcap = 0.0f; diff --git a/ggml/src/ggml-feats.h b/ggml/src/ggml-feats.h index 79a0afd87a87..c45e4ad082fc 100644 --- a/ggml/src/ggml-feats.h +++ b/ggml/src/ggml-feats.h @@ -22,6 +22,10 @@ #define HWCAP2_I8MM (1ULL << 13) #endif +#if !defined(HWCAP2_SVEI8MM) +#define HWCAP2_SVEI8MM (1ULL << 9) +#endif + #if !defined(HWCAP_ASIMDDP) #define HWCAP_ASIMDDP (1 << 20) #endif @@ -63,6 +67,10 @@ #define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47 #endif +#if !defined(PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE) +#define PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE 57 +#endif + #if !defined(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) #define PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE 66 #endif @@ -87,6 +95,7 @@ typedef struct ggml_feats_arch64_runtime { bool has_sve; bool has_sve2; bool has_i8mm; + bool has_svei8mm; bool has_sme; bool has_sme2; int sve_cnt; @@ -104,6 +113,7 @@ static inline ggml_feats_arch64_runtime_t ggml_feats_get_arch64_runtime(void) { runtime_feat.has_sve = !!(hwcap & HWCAP_SVE); runtime_feat.has_sve2 = !!(hwcap2 & HWCAP2_SVE2); runtime_feat.has_i8mm = !!(hwcap2 & HWCAP2_I8MM); + runtime_feat.has_svei8mm = !!(hwcap2 & HWCAP2_SVEI8MM); runtime_feat.has_sme = !!(hwcap2 & HWCAP2_SME); runtime_feat.has_sme2 = !!(hwcap2 & HWCAP2_SME2); @@ -153,6 +163,7 @@ static inline ggml_feats_arch64_runtime_t ggml_feats_get_arch64_runtime(void) { runtime_feat.has_sve = IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE) != 0; runtime_feat.has_sve2 = IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE) != 0; runtime_feat.has_i8mm = IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != 0; + runtime_feat.has_svei8mm = IsProcessorFeaturePresent(PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE) != 0; runtime_feat.has_sme = IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE) != 0; runtime_feat.has_sme2 = IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE) != 0; diff --git a/ggml/src/ggml-hexagon/CMakeLists.txt b/ggml/src/ggml-hexagon/CMakeLists.txt index 20c720263b73..9444f732132d 100644 --- a/ggml/src/ggml-hexagon/CMakeLists.txt +++ b/ggml/src/ggml-hexagon/CMakeLists.txt @@ -21,6 +21,7 @@ message(STATUS "hexagon: using ${HEXAGON_SDK_ROOT} and ${HEXAGON_TOOLS_ROOT} for include(${HEXAGON_SDK_ROOT}/build/cmake/hexagon_fun.cmake) include(ExternalProject) +find_package(Python3 REQUIRED COMPONENTS Interpreter) option(GGML_HEXAGON_HTP_DEBUG "ggml-hexagon: enable HTP debug output" OFF) set(GGML_HEXAGON_HTP_BUILD_TYPE "Release" CACHE STRING "ggml-hexagon: HTP skel build type (Release, RelWithDebInfo, Debug)") @@ -50,6 +51,15 @@ endif() set(TARGET_NAME ggml-hexagon) ggml_add_backend_library(${TARGET_NAME} ggml-hexagon.cpp + htp-common.h + htp-kparams.cpp + htp-kparams.h + htp-opnode.cpp + htp-opnode.h + htp-fusion.cpp + htp-fusion.h + htp-repack.cpp + htp-repack.h htp-drv.cpp htp-drv.h libdl.h @@ -72,7 +82,8 @@ function(build_htp_skel V) -DHEXAGON_TOOLS_ROOT=${HEXAGON_TOOLS_ROOT} -DHEXAGON_HTP_DEBUG=${GGML_HEXAGON_HTP_DEBUG} -DDSP_VERSION=${V} - -DPREBUILT_LIB_DIR="toolv19_${V}") + -DPython3_EXECUTABLE=${Python3_EXECUTABLE} + -DPREBUILT_LIB_DIR="toolv21_${V}") list(APPEND HTP_SKELS ${CMAKE_CURRENT_BINARY_DIR}/libggml-htp-${V}.so) list(APPEND HTP_PROJECTS htp-${V}) set(HTP_SKELS ${HTP_SKELS} PARENT_SCOPE) @@ -83,6 +94,7 @@ build_htp_skel(v73) build_htp_skel(v75) build_htp_skel(v79) build_htp_skel(v81) +build_htp_skel(v85) # Install Hexagon skels required at runtime install(FILES ${HTP_SKELS} TYPE LIB) diff --git a/ggml/src/ggml-hexagon/ggml-hexagon.cpp b/ggml/src/ggml-hexagon/ggml-hexagon.cpp index 66d38ebf2f32..f619e76ec01b 100644 --- a/ggml/src/ggml-hexagon/ggml-hexagon.cpp +++ b/ggml/src/ggml-hexagon/ggml-hexagon.cpp @@ -26,10 +26,6 @@ #include #include -#ifndef M_LOG2E -# define M_LOG2E 1.44269504088896340736 -#endif - #ifdef _WIN32 # define WIN32_LEAN_AND_MEAN # ifndef NOMINMAX @@ -59,24 +55,13 @@ #include "ggml-impl.h" #include "ggml-quants.h" #include "htp-opnode.h" -#include "htp-ops.h" -#include "htp/matmul-ops.h" -#include "htp/binary-ops.h" -#include "htp/flash-attn-ops.h" -#include "htp/unary-ops.h" -#include "htp/get-rows-ops.h" -#include "htp/set-rows-ops.h" -#include "htp/softmax-ops.h" -#include "htp/pool-ops.h" -#include "htp/rope-ops.h" -#include "htp/ssm-conv.h" -#include "htp/gated-delta-net-ops.h" -#include "htp/argsort-ops.h" -#include "htp/concat-ops.h" -#include "htp/cpy-ops.h" -#include "htp/im2col-ops.h" +#include "htp/htp-ops.h" #include "htp_iface.h" #include "htp-drv.h" +#include "htp-repack.h" +#include "htp-common.h" +#include "htp-kparams.h" +#include "htp-fusion.h" using intvec = std::vector; using uintvec = std::vector; @@ -84,8 +69,6 @@ using u32vec = std::vector; #define GGML_HEXAGON_MAX_SESSIONS 16 -#define GGML_HEXAGON_FENCE_SLOT_SIZE 128 - struct ggml_hexagon_device_config { int physical_idx = 0; int virtual_idx = 0; @@ -98,17 +81,18 @@ struct ggml_hexagon_device_config { static ggml_hexagon_device_config opt_device_configs[GGML_HEXAGON_MAX_SESSIONS]; -static int opt_arch = 0; // autodetect -static size_t opt_ndev = 1; -static size_t opt_nhvx = 0; // use all -static int opt_nhmx = 1; // when set, enable HMX; when 0, use HVX only -static size_t opt_vmem = HTP_OP_MAX_VMEM_DEFAULT; // max available va space for buffer mappings -static int opt_etm = 0; -static int opt_verbose = 0; -static int opt_profile = 0; // profiling mode (0-disabled, 1-basic, 2-pmu) -static bool opt_hostbuf = false; -static bool opt_dma64 = false; -static int opt_power_mode = HTP_POWER_MODE_BURST; // DCVS/HMX power profile requested at session start +int opt_arch = 0; // autodetect +size_t opt_ndev = 1; +size_t opt_nhvx = 0; // use all +int opt_nhmx = 1; // when set, enable HMX; when 0, use HVX only +size_t opt_vtcm_size = 0; // VTCM size override in bytes; 0 = auto-detect +size_t opt_vmem = HTP_OP_MAX_VMEM_DEFAULT; // max available va space for buffer mappings +int opt_etm = 0; +int opt_verbose = 0; +int opt_profile = 0; // profiling mode (0-disabled, 1-basic, 2-pmu) +bool opt_hostbuf = false; +bool opt_dma64 = false; +int opt_power_mode = HTP_POWER_MODE_BURST; // DCVS/HMX power profile requested at session start static const std::pair htp_power_mode_names[] = { { "low_power_saver", HTP_POWER_MODE_LOW_POWER_SAVER }, @@ -144,48 +128,31 @@ static const char * htp_power_mode_to_str(int mode) { return "unknown"; } -static size_t opt_mbuf_dyn = 512ul * 1024 * 1024; // max dynamic (compute) buffer size -static size_t opt_mbuf_static = 1ul * 1024 * 1024 * 1024; // max static (weight/KV) buffer size -static size_t opt_mbuf_total = 0; // total buffer space limit (0 = unconstrained) +size_t opt_mbuf_dyn = 512ul * 1024 * 1024; // max dynamic (compute) buffer size +size_t opt_mbuf_static = 1ul * 1024 * 1024 * 1024; // max static (weight/KV) buffer size +size_t opt_mbuf_total = 0; // total buffer space limit (0 = unconstrained) -static int opt_mm_select = 2; // 2 = HMX -> HVX -> CPU, 1 = HVX -> CPU, 0 = CPU (unsupported) -static int opt_fa_select = 2; // 2 = HMX -> HVX -> CPU, 1 = HVX -> CPU, 0 = CPU (unsupported) -static int opt_fa_head_split = 1; // 1 = partition flash_attn by KV heads in multicore (default on), 0 = token-based (original) -static int opt_gdn_select = 2; // 2 = HMX -> HVX, 1 = HVX, 0 = CPU (unsupported) -static int opt_ar_select = 2; // 2 = fused ALLREDUCE+ADD (default), 1 = unfused ALLREDUCE, 0 = fallback to CPY+FENCE -static int opt_ar_scatter = 1; // 1 = reduce-scatter the fused ALLREDUCE+ADD (default), 0 = full reduction +int opt_mm_select = 2; // 2 = HMX -> HVX -> CPU, 1 = HVX -> CPU, 0 = CPU (unsupported) +int opt_fa_select = 2; // 2 = HMX -> HVX -> CPU, 1 = HVX -> CPU, 0 = CPU (unsupported) +int opt_fa_split = 1; // 1 = head-split + team-split when n_kv_heads < N_cores (default), 0 = off +int opt_gdn_select = 2; // 2 = HMX -> HVX, 1 = HVX, 0 = CPU (unsupported) +int opt_ar_select = 2; // 2 = fused ALLREDUCE+ADD (default), 1 = unfused ALLREDUCE, 0 = fallback to CPY+FENCE +int opt_ar_scatter = 1; // 1 = reduce-scatter the fused ALLREDUCE+ADD (default), 0 = full reduction // Default PMU events, if profiling with PMU (mode=2) is enabled // See https://docs.qualcomm.com/doc/80-N2040-60/topic/pmu-events.html // https://docs.qualcomm.com/doc/80-N2040-61/topic/hvx-pmu-events.html static u32vec opt_pmu_evt { 0x3, 0x111, 0x100, 0x105, 0x240, 0x256, 0x7D, 0x8C }; -static int opt_opbatch = 1280; // max number of ops in a batch -static int opt_opqueue = 8; // max number of pending batches -static int opt_optrace = 0; // trace buffer size per thread (0 means default) -static int opt_oppoll = 0; // polling for batch completions -static int opt_opfusion = 1; // enable/disable op fusion - -enum ggml_hexagon_fusion_flags { - GGML_HEXAGON_FUSE_ALLREDUCE_ADD = (1 << 1), // 2 - GGML_HEXAGON_FUSE_RMS_NORM_MUL = (1 << 2), // 4 - GGML_HEXAGON_FUSE_MUL_MAT_ADD = (1 << 3), // 8 - GGML_HEXAGON_FUSE_MUL_MAT_NX = (1 << 4), // 16 - GGML_HEXAGON_FUSE_MUL_MAT_ID_NX = (1 << 5), // 32 - GGML_HEXAGON_FUSE_GDN_CPY = (1 << 6), // 64 -}; - -static inline bool ggml_hexagon_is_fusion_enabled(int flag) { - if (opt_opfusion <= 0) return false; - if (opt_opfusion == 1) return true; // 1 enables all - return (opt_opfusion & flag) != 0; -} +int opt_opbatch = 2048; // max number of ops in a batch +int opt_opqueue = 8; // max number of pending batches +int opt_optrace = 0; // trace buffer size per thread (0 means default) +int opt_oppoll = 0; // polling for batch completions +int opt_opfusion = 1; // enable/disable op fusion +int opt_rt_repack = 1; // runtime repacking: 0 = disabled, 1 = quantized only (default), 2 = always static std::regex* opt_opfilter = NULL; // regex of ops to not claim -#define HEX_VERBOSE(...) \ - if (opt_verbose) GGML_LOG_DEBUG(__VA_ARGS__) - static const char * status_to_str(uint32_t status) { switch (status) { case HTP_STATUS_OK: @@ -205,20 +172,18 @@ static const char * status_to_str(uint32_t status) { // ** debug helpers -static void ggml_hexagon_dump_op_exec(const std::string &sess_name, const htp_opnode & node, const uint32_t req_flags) { +static void ggml_hexagon_dump_op_exec(const char * sess_name, const htp_opnode & node, const uint32_t req_flags) { if (!opt_verbose) return; - htp_opformat fmt(node); - GGML_LOG_DEBUG("ggml-hex: %s execute-op %s|%s|%s|%s|%s|%s|%s|flags 0x%x\n", sess_name.c_str(), - node.op_name().c_str(), fmt.names, fmt.dims, fmt.types, fmt.strides, fmt.buffs, fmt.kparams, req_flags); + GGML_LOG_DEBUG("ggml-hex: %s execute-op %s|flags 0x%x\n", + sess_name, htp_format_op(node, HTP_OPFMT_EXEC).c_str(), req_flags); } -static void ggml_hexagon_dump_op_supp(const std::string &sess_name, const struct ggml_tensor * op, bool supp) { +static void ggml_hexagon_dump_op_supp(const char * sess_name, const struct ggml_tensor * op, bool supp) { if (!opt_verbose) return; - htp_opformat fmt(htp_opformat(htp_opnode(HTP_OP_INVALID, const_cast(op)))); - GGML_LOG_DEBUG("ggml-hex: %s supports-op %s|%s|%s|%s|%s|%s|%s\n", sess_name.c_str(), - ggml_op_desc(op), fmt.names, fmt.dims, fmt.types, fmt.strides, fmt.buffs, supp ? "yes" : "no"); + GGML_LOG_DEBUG("ggml-hex: %s supports-op %s|%s\n", + sess_name, htp_format_op(op, HTP_OPFMT_SUPP).c_str(), supp ? "yes" : "no"); } static const char * htp_event_name(uint16_t id) { @@ -251,7 +216,7 @@ static const char * htp_event_name(uint16_t id) { } } -static void ggml_hexagon_dump_op_prof(const std::string &sess_name, const htp_opnode & node, const htp_prof_desc & pd) { +static void ggml_hexagon_dump_op_prof(const char * sess_name, const htp_opnode & node, const htp_prof_desc & pd) { if (!opt_profile) return; uint32_t op_usec = pd.usecs; @@ -265,13 +230,12 @@ static void ggml_hexagon_dump_op_prof(const std::string &sess_name, const htp_op pmu[0], pmu[1], pmu[2], pmu[3], pmu[4], pmu[5], pmu[6], pmu[7]); } - htp_opformat fmt(node); float mhz = op_usec > 0 ? (float) op_cycles / op_usec : 0.0f; - GGML_LOG_DEBUG("ggml-hex: %s profile-op %s|%s|%s|%s|%s|%s|usec %u cycles %u start %u mhz %.1f%s\n", sess_name.c_str(), - node.op_name().c_str(), fmt.names, fmt.dims, fmt.types, fmt.strides, fmt.kparams, op_usec, op_cycles, pd.cycles_start, mhz, pmu_str); + GGML_LOG_DEBUG("ggml-hex: %s profile-op %s|usec %u cycles %u start %u mhz %.1f%s\n", + sess_name, htp_format_op(node, HTP_OPFMT_PROF).c_str(), op_usec, op_cycles, pd.cycles_start, mhz, pmu_str); } -static void ggml_hexagon_dump_batch_prof(const std::string & sess_name, const htp_opbatch_rsp & rsp) { +static void ggml_hexagon_dump_batch_prof(const char * sess_name, const htp_opbatch_rsp & rsp) { uint64_t batch_cycles = rsp.cycles_stop - rsp.cycles_start; float batch_mhz = rsp.usecs > 0 ? (float) batch_cycles / rsp.usecs : 0.0f; @@ -284,10 +248,10 @@ static void ggml_hexagon_dump_batch_prof(const std::string & sess_name, const ht } GGML_LOG_DEBUG("ggml-hex: %s profile-op OPBATCH|----|n-ops %u|%s|----|----|usec %u cycles %llu start %llu mhz %.1f\n", - sess_name.c_str(), rsp.n_ops, evt_str, rsp.usecs, (unsigned long long) batch_cycles, (unsigned long long) rsp.cycles_start, batch_mhz); + sess_name, rsp.n_ops, evt_str, rsp.usecs, (unsigned long long) batch_cycles, (unsigned long long) rsp.cycles_start, batch_mhz); } -static void ggml_hexagon_dump_trace_events(const std::string & sess_name, const htp_opbatch_rsp & rsp, +static void ggml_hexagon_dump_trace_events(const char * sess_name, const htp_opbatch_rsp & rsp, const htp_trace_desc * trace_events, uint32_t n_traces) { if (opt_profile == 3 && trace_events) { uint32_t valid_cnt[HTP_MAX_NTHREADS + 1] = {0}; @@ -302,241 +266,14 @@ static void ggml_hexagon_dump_trace_events(const std::string & sess_name, const bool is_stop = (e.info & 0x8000) != 0; uint16_t info = e.info & 0x7FFF; GGML_LOG_DEBUG("ggml-hex: %s trace-evt %s: thread %u info %u %s %u\n", - sess_name.c_str(), htp_event_name(e.id), t, info, is_stop ? "stop" : "start", e.cycles); + sess_name, htp_event_name(e.id), t, info, is_stop ? "stop" : "start", e.cycles); } } } } -enum ggml_hexagon_tensor_flags { - GGML_HEXAGON_TENSOR_REPACK = (1 << 0), - GGML_HEXAGON_TENSOR_WEIGHT = (1 << 1), - GGML_HEXAGON_TENSOR_FENCE = (1 << 2), - GGML_HEXAGON_TENSOR_FUSEABLE = (1 << 3), -}; - -static inline bool ggml_hexagon_is_repack_type(enum ggml_type type) { - return type == GGML_TYPE_Q4_0 || type == GGML_TYPE_Q4_1 || - type == GGML_TYPE_Q8_0 || type == GGML_TYPE_IQ4_NL || - type == GGML_TYPE_MXFP4 || type == GGML_TYPE_Q6_K || - type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K || - type == GGML_TYPE_Q3_K || type == GGML_TYPE_Q2_K; -} - -// Size of one repacked row in the DSP tiled layout. The Q3_K..Q6_K tiles store uncompressed scales/mins, -// so they are larger than the ggml blocks. For the other repack types (Q2_K included) the tile has the same size. -static inline size_t ggml_hexagon_tiled_row_size(enum ggml_type type, int64_t ne0) { - if (type == GGML_TYPE_Q6_K) { - return (size_t) (ne0 / 32) * (HTP_MM_WEIGHT_TILE_SIZE_Q6_K / 32); - } - if (type == GGML_TYPE_Q4_K) { - return (size_t) (ne0 / 32) * (HTP_MM_WEIGHT_TILE_SIZE_Q4_1 / 32); - } - if (type == GGML_TYPE_Q5_K) { - return (size_t) (ne0 / 32) * (HTP_MM_WEIGHT_TILE_SIZE_Q5_K / 32); - } - if (type == GGML_TYPE_Q3_K) { - return (size_t) (ne0 / 32) * (HTP_MM_WEIGHT_TILE_SIZE_Q3_K / 32); - } - return ggml_row_size(type, ne0); -} - -static inline bool ggml_hexagon_is_hmx_weight_type(enum ggml_type type) { - return type == GGML_TYPE_F16 || type == GGML_TYPE_F32 || ggml_hexagon_is_repack_type(type); -} - -struct ggml_hexagon_session; - -static void ggml_hexagon_precompute_matmul_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_mm_kernel_params * kparams -); - -static void ggml_hexagon_precompute_fused_matmul_add_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * src2, - const struct ggml_tensor * dst, - struct htp_mm_kernel_params * kparams -); - -static void ggml_hexagon_precompute_unary_params( - const struct ggml_hexagon_session * sess, - uint32_t op, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_unary_kernel_params * kparams -); - -static bool ggml_hexagon_precompute_binary_params( - const struct ggml_hexagon_session * sess, - uint32_t op, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_binary_kernel_params * kparams, - const struct ggml_tensor * src2 = nullptr -); - -static void ggml_hexagon_precompute_get_rows_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_get_rows_kernel_params * kparams -); - -static void ggml_hexagon_precompute_set_rows_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_set_rows_kernel_params * kparams -); - -static void ggml_hexagon_precompute_softmax_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_softmax_kernel_params * kparams -); - -static void ggml_hexagon_precompute_rope_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_rope_kernel_params * kparams -); - -static void ggml_hexagon_precompute_ssm_conv_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_ssm_conv_kernel_params * kparams -); - -static void ggml_hexagon_precompute_gated_delta_net_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_gdn_kernel_params * kparams -); - -static void ggml_hexagon_precompute_sort_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - bool is_top_k, - struct htp_sort_kernel_params * kparams -); - -static void ggml_hexagon_precompute_pool_2d_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * dst, - struct htp_pool_2d_kernel_params * kparams, - bool is_pool_1d -); - -static bool ggml_hexagon_precompute_concat_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_concat_kernel_params * kparams -); - -static bool ggml_hexagon_precompute_cpy_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_copy_kernel_params * kparams -); - -static bool ggml_hexagon_precompute_im2col_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_im2col_kernel_params * kparams -); - -static bool ggml_hexagon_precompute_im2col_3d_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_im2col_kernel_params * kparams -); - -static void ggml_hexagon_precompute_fused_mmnx_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * act, - int32_t n_weights, - struct htp_mm_kernel_params * kparams -); - -static void ggml_hexagon_precompute_fused_mmidnx_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * act, - const struct ggml_tensor * dst, - int32_t n_weights, - struct htp_mm_kernel_params * kparams -); - -static bool ggml_hexagon_precompute_allreduce_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * dst, - uint32_t rank, - uint32_t n_ranks, - bool has_add, - bool is_row_bcast, - bool is_shard_ok, - struct htp_allreduce_kernel_params * kparams -); - -static bool ggml_hexagon_rows_stride(const int64_t * ne, const size_t * nb, size_t * stride); -static bool ggml_hexagon_matmul_can_collapse(const struct ggml_tensor * src0, const struct ggml_tensor * src1, const struct ggml_tensor * dst); -static ggml_tensor ggml_hexagon_tensor_collapse_rows(const struct ggml_tensor * t); - -static bool mm_is_hmx_eligible(const ggml_tensor * t); -static htp_op_code op_remap_to_htp(const ggml_tensor * t); -static bool is_supported_mul_mat_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams); -static bool is_supported_mul_mat_id_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams); -static bool is_mergeable_mul_mat(const ggml_tensor * t); -static bool is_mergeable_mul_mat_pair(const ggml_tensor * n1, const ggml_tensor * n2); -static bool is_mergeable_mul_mat_id(const ggml_tensor * t); -static bool is_mergeable_mul_mat_id_pair(const ggml_tensor * n1, const ggml_tensor * n2); - // ** backend sessions -struct ggml_hexagon_tensor_extra { - std::vector shadow_buf; - size_t shadow_size { 0 }; - uint32_t flags { 0 }; -}; - -static inline bool ggml_hexagon_tensor_is_fuseable(const struct ggml_tensor * t) { - if (!t->extra) return false; - auto extra = (const struct ggml_hexagon_tensor_extra *) t->extra; - return (extra->flags & GGML_HEXAGON_TENSOR_FUSEABLE) != 0; -} - -static inline bool ggml_hexagon_tensors_overlap(const struct ggml_tensor * a, const struct ggml_tensor * b) { - const uintptr_t a0 = (uintptr_t) a->data; - const uintptr_t b0 = (uintptr_t) b->data; - const uintptr_t a1 = a0 + ggml_nbytes(a); - const uintptr_t b1 = b0 + ggml_nbytes(b); - - return a0 < b1 && b0 < a1; -} - -static inline bool ggml_hexagon_can_row_partition(const struct ggml_tensor * t) { - if (t->ne[1] > 1 && (t->nb[1] & 127) != 0) return false; - if (t->ne[2] > 1 && (t->nb[2] & 127) != 0) return false; - if (t->ne[3] > 1 && (t->nb[3] & 127) != 0) return false; - return true; -} - -struct htp_opnode; - struct ggml_hexagon_opbatch; struct ggml_hexagon_opqueue; struct ggml_hexagon_shared_buffer; @@ -600,8 +337,6 @@ struct ggml_hexagon_session { uint64_t cached_uid = 0; std::vector cached_nodes; - mutable std::unordered_set needs_repack; - ggml_hexagon_mdev_group mdev; ggml_backend_dev_t dev = nullptr; ggml_backend_hexagon_device_context * dev_ctx = nullptr; @@ -615,8 +350,13 @@ struct ggml_hexagon_session { void allocate(const ggml_hexagon_device_config & config) noexcept(false); void release() noexcept(true); - uint8_t * alloc_fence(uint32_t n_slots = 1); - void free_fence(void * ptr, uint32_t n_slots = 1); + uint8_t * alloc_fence(uint32_t n_slots = 1); + void free_fence(void * ptr, uint32_t n_slots = 1); + ggml_tensor make_fence_tensor(const volatile void * slot, uint32_t n_slots = 1) const; + uint32_t next_fence_seq() { + if (++fence_seq == 0) fence_seq = 1; + return fence_seq; + } uint8_t * mdev_fence_slot = nullptr; std::unordered_map cpy_fence_slots; @@ -650,6 +390,12 @@ struct ggml_hexagon_session { } }; +const char * htp_session_name(const struct ggml_hexagon_session * sess) { return sess->c_name(); } +size_t htp_session_vtcm_size(const struct ggml_hexagon_session * sess) { return sess->vtcm_size; } +uint32_t htp_session_n_threads(const struct ggml_hexagon_session * sess) { return sess->n_threads; } +uint32_t htp_session_n_hmx(const struct ggml_hexagon_session * sess) { return sess->n_hmx; } +uint32_t htp_session_mdev_count(const struct ggml_hexagon_session * sess) { return sess->mdev.count; } + // ** backend buffers struct ggml_backend_hexagon_device_context { @@ -716,7 +462,7 @@ struct ggml_hexagon_rpcmem_block { struct ggml_hexagon_shared_buffer { ggml_hexagon_session * sess; std::shared_ptr mem; - std::vector tensor_extra; + std::vector tensor_extra; bool mapped; bool pinned; bool extended; @@ -828,7 +574,7 @@ struct ggml_hexagon_fence_buffer : public ggml_hexagon_shared_buffer { ggml_hexagon_fence_buffer(ggml_hexagon_session * sess, ggml_backend_buffer_type_t buft, size_t size) : ggml_hexagon_shared_buffer(sess, size, false /* pinned */), - slot_count(size / GGML_HEXAGON_FENCE_SLOT_SIZE), + slot_count(size / HTP_FENCE_SLOT_SIZE), slot_head(0) { backend_buffer.buft = buft; backend_buffer.context = static_cast(this); @@ -841,21 +587,21 @@ struct ggml_hexagon_fence_buffer : public ggml_hexagon_shared_buffer { if (n_slots == 1 && !free_slots.empty()) { uint32_t slot = free_slots.back(); free_slots.pop_back(); - ptr = base() + (size_t) slot * GGML_HEXAGON_FENCE_SLOT_SIZE; + ptr = base() + (size_t) slot * HTP_FENCE_SLOT_SIZE; } else if (slot_head + n_slots <= slot_count) { uint32_t slot = slot_head; slot_head += n_slots; - ptr = base() + (size_t) slot * GGML_HEXAGON_FENCE_SLOT_SIZE; + ptr = base() + (size_t) slot * HTP_FENCE_SLOT_SIZE; } if (ptr) { - memset(ptr, 0, (size_t) n_slots * GGML_HEXAGON_FENCE_SLOT_SIZE); + memset(ptr, 0, (size_t) n_slots * HTP_FENCE_SLOT_SIZE); } return ptr; } void free_slot(void * ptr, uint32_t n_slots = 1) { if (!ptr) return; - uint32_t slot = ((uint8_t *) ptr - base()) / GGML_HEXAGON_FENCE_SLOT_SIZE; + uint32_t slot = ((uint8_t *) ptr - base()) / HTP_FENCE_SLOT_SIZE; for (uint32_t i = 0; i < n_slots; i++) { free_slots.push_back(slot + i); } @@ -874,6 +620,26 @@ inline void ggml_hexagon_session::free_fence(void * ptr, uint32_t n_slots) { } } +inline ggml_tensor ggml_hexagon_session::make_fence_tensor(const volatile void * slot, uint32_t n_slots) const { + static htp_tensor_extra fence_extra { {}, 0, HTP_TENSOR_FENCE }; + + ggml_tensor t {}; + t.buffer = &this->fence_buf->backend_buffer; + t.extra = &fence_extra; + t.data = const_cast(slot); + t.type = GGML_TYPE_I8; + t.ne[0] = HTP_FENCE_SLOT_SIZE; + t.ne[1] = (int64_t) n_slots; + t.ne[2] = 1; + t.ne[3] = 1; + t.nb[0] = 1; + t.nb[1] = HTP_FENCE_SLOT_SIZE; + t.nb[2] = t.nb[1] * t.ne[1]; + t.nb[3] = t.nb[2]; + t.op = GGML_OP_NONE; + return t; +} + static void ggml_backend_hexagon_buffer_free_buffer(ggml_backend_buffer_t buffer) { auto sbuf = static_cast(buffer->context); sbuf->sess->unclone_buffer(sbuf); @@ -892,7661 +658,1713 @@ static enum ggml_status ggml_backend_hexagon_buffer_init_tensor(ggml_backend_buf HEX_VERBOSE("ggml-hex: %s init-tensor %s : base %p data %p nbytes %zu\n", sess->c_name(), tensor->name, (void *) sbuf->base(), tensor->data, ggml_nbytes(tensor)); - auto extra = new ggml_hexagon_tensor_extra(); + auto extra = new htp_tensor_extra(); sbuf->tensor_extra.push_back(extra); tensor->extra = extra; - if (ggml_hexagon_is_repack_type(tensor->type)) { - if (sess->needs_repack.count(tensor)) { - extra->flags |= GGML_HEXAGON_TENSOR_REPACK; - sess->needs_repack.erase(tensor); - } - } return GGML_STATUS_SUCCESS; } -// ** Repack helpers for tiled quantized weights - -static void unpack_q4_0_quants(uint8_t * qs, const block_q4_0 * x, unsigned int bi) { - static const int qk = QK4_0; +static void ggml_backend_hexagon_buffer_set_tensor(ggml_backend_buffer_t buffer, + ggml_tensor * tensor, + const void * data, + size_t offset, + size_t size) { + auto extra = (htp_tensor_extra *) tensor->extra; + auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; + auto sess = sbuf->sess; - for (unsigned int i = 0; i < qk / 2; ++i) { - const int x0 = (x->qs[i] & 0x0F); - const int x1 = (x->qs[i] >> 4); - qs[bi * qk + i + 0] = x0; - qs[bi * qk + i + qk / 2] = x1; + if (ggml_backend_buffer_get_usage(buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS) { + extra->flags |= HTP_TENSOR_WEIGHT; + if (htp_is_tiled_weight_tensor(tensor)) { + extra->flags |= HTP_TENSOR_TILED; + } } -} -static void pack_q4_0_quants(block_q4_0 * x, const uint8_t * qs, unsigned int bi) { - static const int qk = QK4_0; + HEX_VERBOSE("ggml-hex: %s set-tensor %s : data %p offset %zu size %zu usage %d flags 0x%x\n", + sess->c_name(), tensor->name, data, offset, size, (int) buffer->usage, extra->flags); - for (unsigned int i = 0; i < qk / 2; ++i) { - const uint8_t x0 = qs[bi * qk + i + 0]; - const uint8_t x1 = qs[bi * qk + i + qk / 2]; - x->qs[i] = x0 | (x1 << 4); + if ((extra->flags & HTP_TENSOR_TILED) == 0) { + memcpy((char *) tensor->data + offset, data, size); + return; } -} - -static void unpack_q4_1_quants(uint8_t * qs, const block_q4_1 * x, unsigned int bi) { - static const int qk = QK4_1; - for (unsigned int i = 0; i < qk / 2; ++i) { - const int x0 = (x->qs[i] & 0x0F); - const int x1 = (x->qs[i] >> 4); - qs[bi * qk + i + 0] = x0; - qs[bi * qk + i + qk / 2] = x1; + if (offset == 0 && size == ggml_nbytes(tensor) && extra->shadow_buf.empty()) { + htp_repack_tensor_tiled(tensor, data, size); + return; } -} -static void pack_q4_1_quants(block_q4_1 * x, const uint8_t * qs, unsigned int bi) { - static const int qk = QK4_1; + if (extra->shadow_buf.size() < ggml_nbytes(tensor)) { + extra->shadow_buf.resize(ggml_nbytes(tensor)); + } + memcpy(extra->shadow_buf.data() + offset, data, size); + extra->shadow_size += size; - for (unsigned int i = 0; i < qk / 2; ++i) { - const uint8_t x0 = qs[bi * qk + i + 0]; - const uint8_t x1 = qs[bi * qk + i + qk / 2]; - x->qs[i] = x0 | (x1 << 4); + if (extra->shadow_size >= ggml_nbytes(tensor)) { + htp_repack_tensor_tiled(tensor, extra->shadow_buf.data(), extra->shadow_buf.size()); + extra->shadow_buf.clear(); + extra->shadow_buf.shrink_to_fit(); + extra->shadow_size = 0; } } -static void unpack_mxfp4_quants(uint8_t * qs, const block_mxfp4 * x, unsigned int bi) { - static const int qk = QK_MXFP4; +static void ggml_backend_hexagon_buffer_get_tensor(ggml_backend_buffer_t buffer, + const ggml_tensor * tensor, + void * data, + size_t offset, + size_t size) { + auto extra = (htp_tensor_extra *) tensor->extra; + auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; + auto sess = sbuf->sess; + + HEX_VERBOSE("ggml-hex: %s get-tensor %s : data %p offset %zu size %zu usage %d flags 0x%x\n", + sess->c_name(), tensor->name, data, offset, size, (int) buffer->usage, extra->flags); - for (unsigned int i = 0; i < qk / 2; ++i) { - const int x0 = (x->qs[i] & 0x0F); - const int x1 = (x->qs[i] >> 4); - qs[bi * qk + i + 0] = x0; - qs[bi * qk + i + qk / 2] = x1; + if ((extra->flags & HTP_TENSOR_TILED) == 0) { + memcpy(data, (const char *) tensor->data + offset, size); + return; } + + htp_unpack_tensor_tiled(data, tensor, offset, size); } -static void pack_mxfp4_quants(block_mxfp4 * x, const uint8_t * qs, unsigned int bi) { - static const int qk = QK_MXFP4; +static bool ggml_backend_hexagon_buffer_cpy_tensor(ggml_backend_buffer_t buffer, + const struct ggml_tensor * src, + struct ggml_tensor * dst) { + // we might optimize this later, for now take the slow path (ie get/set_tensor) + return false; - for (unsigned int i = 0; i < qk / 2; ++i) { - const uint8_t x0 = qs[bi * qk + i + 0]; - const uint8_t x1 = qs[bi * qk + i + qk / 2]; - x->qs[i] = x0 | (x1 << 4); - } + GGML_UNUSED(buffer); + GGML_UNUSED(src); + GGML_UNUSED(dst); } -// repack q4_0 data into q4_0_tiled tensor -static void repack_q4_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - const block_q4_0 * src_matrix = (const block_q4_0 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_0; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - const block_q4_0 * src_slice = src_matrix + (slice_idx - start_slice) * (ne1 * (ne0 / 32)); - uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = 0; ct < n_col_tiles; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - uint8_t * tile_dst = matrix_dst + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r < ne1 && kt < ne0 / 32) { - unpack_q4_0_quants(tile_quants[row], &src_slice[r * (ne0 / 32) + kt], 0); - } else { - memset(tile_quants[row], 8, 32); - } - } - - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - tile_dst[cp * 32 + row] = (tile_quants[row][2 * cp + 1] << 4) | tile_quants[row][2 * cp]; - } - } +static void ggml_backend_hexagon_buffer_set_tensor_2d(ggml_backend_buffer_t buffer, + ggml_tensor * tensor, + const void * data, + size_t offset, + size_t size, + size_t n_copies, + size_t stride_tensor, + size_t stride_data) { + auto extra = (htp_tensor_extra *) tensor->extra; + auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; + auto sess = sbuf->sess; - ggml_half * scale_dst = (ggml_half *)(tile_dst + 512); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - scale_dst[row] = (r < ne1 && kt < ne0 / 32) ? src_slice[r * (ne0 / 32) + kt].d : 0; - } - } + if (ggml_backend_buffer_get_usage(buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS) { + extra->flags |= HTP_TENSOR_WEIGHT; + if (htp_is_tiled_weight_tensor(tensor)) { + extra->flags |= HTP_TENSOR_TILED; } } -} - -// repack q4_0_tiled tensor into q4_0 data -static void repack_tiled_q4_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { - block_q4_0 * dst_matrix = (block_q4_0 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_0; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - size_t row_size_bytes = ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); - size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); - size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; - size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; - - int64_t start_row = slice_offset_start / row_size_bytes; - int64_t end_row = (slice_offset_end + row_size_bytes - 1) / row_size_bytes; - end_row = (std::min)(end_row, ne1); - - int start_ct = start_row / 32; - int end_ct = (end_row + 31) / 32; - end_ct = (std::min)(end_ct, n_col_tiles); - - block_q4_0 * dst_slice = dst_matrix + (cur_start_byte - offset) / sizeof(block_q4_0); - const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = start_ct; ct < end_ct; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - const uint8_t * tile_src = matrix_src + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - uint8_t val = tile_src[cp * 32 + row]; - tile_quants[row][2 * cp + 0] = val & 0x0F; - tile_quants[row][2 * cp + 1] = val >> 4; - } - } - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - pack_q4_0_quants(&dst_slice[(r - start_row) * (ne0 / 32) + kt], tile_quants[row], 0); - } - } + HEX_VERBOSE("ggml-hex: %s set-tensor-2d %s : data %p offset %zu size %zu n_copies %zu stride_tensor %zu stride_data %zu usage %d flags 0x%x\n", + sess->c_name(), tensor->name, data, offset, size, n_copies, stride_tensor, stride_data, (int) buffer->usage, extra->flags); - const ggml_half * scale_src = (const ggml_half *)(tile_src + 512); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - dst_slice[(r - start_row) * (ne0 / 32) + kt].d = scale_src[row]; - } - } - } + if ((extra->flags & HTP_TENSOR_TILED) == 0) { + for (size_t i = 0; i < n_copies; i++) { + memcpy((uint8_t *) tensor->data + offset + i * stride_tensor, (const uint8_t *) data + i * stride_data, size); } + return; } -} -// repack q4_1 data into q4_1_tiled tensor -static void repack_q4_1_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - const block_q4_1 * src_matrix = (const block_q4_1 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_1; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - const block_q4_1 * src_slice = src_matrix + (slice_idx - start_slice) * (ne1 * (ne0 / 32)); - uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = 0; ct < n_col_tiles; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - uint8_t * tile_dst = matrix_dst + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r < ne1 && kt < ne0 / 32) { - unpack_q4_1_quants(tile_quants[row], &src_slice[r * (ne0 / 32) + kt], 0); - } else { - memset(tile_quants[row], 0, 32); - } - } - - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - tile_dst[cp * 32 + row] = (tile_quants[row][2 * cp + 1] << 4) | tile_quants[row][2 * cp]; - } - } + if (extra->shadow_buf.size() < ggml_nbytes(tensor)) { + extra->shadow_buf.resize(ggml_nbytes(tensor)); + } + for (size_t i = 0; i < n_copies; i++) { + memcpy(extra->shadow_buf.data() + offset + i * stride_tensor, (const uint8_t *) data + i * stride_data, size); + } + extra->shadow_size += n_copies * size; - ggml_half * scale_dst = (ggml_half *)(tile_dst + 512); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r < ne1 && kt < ne0 / 32) { - scale_dst[2 * row + 0] = src_slice[r * (ne0 / 32) + kt].d; - scale_dst[2 * row + 1] = src_slice[r * (ne0 / 32) + kt].m; - } else { - scale_dst[2 * row + 0] = 0; - scale_dst[2 * row + 1] = 0; - } - } - } - } + if (extra->shadow_size >= ggml_nbytes(tensor)) { + htp_repack_tensor_tiled(tensor, extra->shadow_buf.data(), extra->shadow_buf.size()); + extra->shadow_buf.clear(); + extra->shadow_buf.shrink_to_fit(); + extra->shadow_size = 0; } } -// repack q4_1_tiled tensor into q4_1 data -static void repack_tiled_q4_1(void * data, const ggml_tensor * t, size_t offset, size_t size) { - block_q4_1 * dst_matrix = (block_q4_1 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_1; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - size_t row_size_bytes = ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); - size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); - size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; - size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; - - int64_t start_row = slice_offset_start / row_size_bytes; - int64_t end_row = (slice_offset_end + row_size_bytes - 1) / row_size_bytes; - end_row = (std::min)(end_row, ne1); - - int start_ct = start_row / 32; - int end_ct = (end_row + 31) / 32; - end_ct = (std::min)(end_ct, n_col_tiles); - - block_q4_1 * dst_slice = dst_matrix + (cur_start_byte - offset) / sizeof(block_q4_1); - const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = start_ct; ct < end_ct; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - const uint8_t * tile_src = matrix_src + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - uint8_t val = tile_src[cp * 32 + row]; - tile_quants[row][2 * cp + 0] = val & 0x0F; - tile_quants[row][2 * cp + 1] = val >> 4; - } - } +static void ggml_backend_hexagon_buffer_get_tensor_2d(ggml_backend_buffer_t buffer, + const ggml_tensor * tensor, + void * data, + size_t offset, + size_t size, + size_t n_copies, + size_t stride_tensor, + size_t stride_data) { + auto extra = (htp_tensor_extra *) tensor->extra; + auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; + auto sess = sbuf->sess; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - pack_q4_1_quants(&dst_slice[(r - start_row) * (ne0 / 32) + kt], tile_quants[row], 0); - } - } + HEX_VERBOSE("ggml-hex: %s get-tensor-2d %s : data %p offset %zu size %zu n_copies %zu stride_tensor %zu stride_data %zu usage %d\n", + sess->c_name(), tensor->name, data, offset, size, n_copies, stride_tensor, stride_data, (int) buffer->usage); - const ggml_half * scale_src = (const ggml_half *)(tile_src + 512); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - dst_slice[(r - start_row) * (ne0 / 32) + kt].d = scale_src[2 * row]; - dst_slice[(r - start_row) * (ne0 / 32) + kt].m = scale_src[2 * row + 1]; - } - } - } + if ((extra->flags & HTP_TENSOR_TILED) == 0) { + for (size_t i = 0; i < n_copies; i++) { + memcpy((uint8_t *)data + i * stride_data, (const uint8_t *)tensor->data + offset + i * stride_tensor, size); } + return; } -} -// repack q8_0 data into q8_0_tiled tensor -static void repack_q8_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - const block_q8_0 * src_matrix = (const block_q8_0 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q8_0; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - const block_q8_0 * src_slice = src_matrix + (slice_idx - start_slice) * (ne1 * (ne0 / 32)); - uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = 0; ct < n_col_tiles; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - uint8_t * tile_dst = matrix_dst + (ct * n_k_tiles + kt) * tile_size; - - for (int cp = 0; cp < 16; cp++) { - int col0 = cp * 2; - int col1 = col0 + 1; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - const block_q8_0 * b = (r < ne1 && kt < ne0 / 32) ? &src_slice[r * (ne0 / 32) + kt] : NULL; - tile_dst[cp * 64 + 2 * row + 0] = b ? b->qs[col0] : 0; - tile_dst[cp * 64 + 2 * row + 1] = b ? b->qs[col1] : 0; - } - } + size_t temp_size = n_copies > 0 ? (n_copies - 1) * stride_tensor + size : 0; + size_t slice_size = tensor->ne[1] * ggml_row_size(tensor->type, tensor->ne[0]); + size_t slice_offset = offset % slice_size; + size_t row_size_bytes = ggml_row_size(tensor->type, tensor->ne[0]); - ggml_half * scale_dst = (ggml_half *)(tile_dst + 1024); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - scale_dst[row] = (r < ne1 && kt < ne0 / 32) ? src_slice[r * (ne0 / 32) + kt].d : 0; - } - } - } - } -} + GGML_ASSERT((slice_offset % row_size_bytes) == 0 && "offset must be aligned to row boundary"); + GGML_ASSERT((temp_size % row_size_bytes) == 0 && "temp_size must be a multiple of row size"); + GGML_ASSERT((offset + temp_size) <= ggml_nbytes(tensor)); -// repack q8_0_tiled tensor into q8_0 data -static void repack_tiled_q8_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { - block_q8_0 * dst_matrix = (block_q8_0 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q8_0; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - size_t row_size_bytes = ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); - size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); - size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; - size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; - - int64_t start_row = slice_offset_start / row_size_bytes; - int64_t end_row = (slice_offset_end + row_size_bytes - 1) / row_size_bytes; - end_row = (std::min)(end_row, ne1); - - int start_ct = start_row / 32; - int end_ct = (end_row + 31) / 32; - end_ct = (std::min)(end_ct, n_col_tiles); - - block_q8_0 * dst_slice = dst_matrix + (cur_start_byte - offset) / sizeof(block_q8_0); - const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = start_ct; ct < end_ct; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - const uint8_t * tile_src = matrix_src + (ct * n_k_tiles + kt) * tile_size; - - for (int cp = 0; cp < 16; cp++) { - int col0 = cp * 2; - int col1 = col0 + 1; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - block_q8_0 & b = dst_slice[(r - start_row) * (ne0 / 32) + kt]; - b.qs[col0] = tile_src[cp * 64 + 2 * row + 0]; - b.qs[col1] = tile_src[cp * 64 + 2 * row + 1]; - } - } - } + std::vector temp_buf(temp_size); + htp_unpack_tensor_tiled(temp_buf.data(), tensor, offset, temp_size); - const ggml_half * scale_src = (const ggml_half *)(tile_src + 1024); - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - dst_slice[(r - start_row) * (ne0 / 32) + kt].d = scale_src[row]; - } - } - } - } + for (size_t i = 0; i < n_copies; i++) { + memcpy((uint8_t *) data + i * stride_data, temp_buf.data() + i * stride_tensor, size); } } -// repack mxfp4 data into mxfp4_tiled tensor -static void repack_mxfp4_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - const block_mxfp4 * src_matrix = (const block_mxfp4 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_MXFP4; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - const block_mxfp4 * src_slice = src_matrix + (slice_idx - start_slice) * (ne1 * (ne0 / 32)); - uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = 0; ct < n_col_tiles; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - uint8_t * tile_dst = matrix_dst + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r < ne1 && kt < ne0 / 32) { - unpack_mxfp4_quants(tile_quants[row], &src_slice[r * (ne0 / 32) + kt], 0); - } else { - memset(tile_quants[row], 0, 32); - } - } - - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - tile_dst[cp * 32 + row] = (tile_quants[row][2 * cp + 1] << 4) | tile_quants[row][2 * cp]; - } - } - - uint8_t * scale_dst = tile_dst + 512; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - scale_dst[row] = (r < ne1 && kt < ne0 / 32) ? src_slice[r * (ne0 / 32) + kt].e : 0; - } - } - } - } +static void ggml_backend_hexagon_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { + auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; + auto sess = sbuf->sess; + HEX_VERBOSE("ggml-hex: %s clear-buff base %p size %zu\n", sess->c_name(), (void *) sbuf->base(), sbuf->size()); + memset(sbuf->base(), value, sbuf->size()); } -// repack mxfp4_tiled tensor into mxfp4 data -static void repack_tiled_mxfp4(void * data, const ggml_tensor * t, size_t offset, size_t size) { - block_mxfp4 * dst_matrix = (block_mxfp4 *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - int n_col_tiles = ne1_padded / 32; - int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_MXFP4; - const size_t matrix_size = n_col_tiles * n_k_tiles * tile_size; - - size_t slice_size = ne1 * ggml_row_size(t->type, ne0); - size_t row_size_bytes = ggml_row_size(t->type, ne0); - int64_t start_slice = offset / slice_size; - int64_t end_slice = (offset + size + slice_size - 1) / slice_size; - if (end_slice > ne2 * ne3) { - end_slice = ne2 * ne3; - } - - for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { - size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); - size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); - size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; - size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; - - int64_t start_row = slice_offset_start / row_size_bytes; - int64_t end_row = (slice_offset_end + row_size_bytes - 1) / row_size_bytes; - end_row = (std::min)(end_row, ne1); - - int start_ct = start_row / 32; - int end_ct = (end_row + 31) / 32; - end_ct = (std::min)(end_ct, n_col_tiles); - - block_mxfp4 * dst_slice = dst_matrix + (cur_start_byte - offset) / sizeof(block_mxfp4); - const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; - - for (int ct = start_ct; ct < end_ct; ct++) { - for (int kt = 0; kt < n_k_tiles; kt++) { - const uint8_t * tile_src = matrix_src + (ct * n_k_tiles + kt) * tile_size; - - uint8_t tile_quants[32][32]; - for (int cp = 0; cp < 16; cp++) { - for (int row = 0; row < 32; row++) { - uint8_t val = tile_src[cp * 32 + row]; - tile_quants[row][2 * cp + 0] = val & 0x0F; - tile_quants[row][2 * cp + 1] = val >> 4; - } - } +static ggml_backend_buffer_i ggml_backend_hexagon_buffer_interface = { + /* .free_buffer = */ ggml_backend_hexagon_buffer_free_buffer, + /* .get_base = */ ggml_backend_hexagon_buffer_get_base, + /* .init_tensor = */ ggml_backend_hexagon_buffer_init_tensor, + /* .memset_tensor = */ NULL, + /* .set_tensor = */ ggml_backend_hexagon_buffer_set_tensor, + /* .get_tensor = */ ggml_backend_hexagon_buffer_get_tensor, + /* .set_tensor_2d = */ ggml_backend_hexagon_buffer_set_tensor_2d, + /* .get_tensor_2d = */ ggml_backend_hexagon_buffer_get_tensor_2d, + /* .cpy_tensor = */ ggml_backend_hexagon_buffer_cpy_tensor, + /* .clear = */ ggml_backend_hexagon_buffer_clear, + /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, +}; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - pack_mxfp4_quants(&dst_slice[(r - start_row) * (ne0 / 32) + kt], tile_quants[row], 0); - } - } +// ** backend buffer type - const uint8_t * scale_src = tile_src + 512; - for (int row = 0; row < 32; row++) { - int64_t r = ct * 32 + row; - if (r >= start_row && r < end_row && kt < ne0 / 32) { - dst_slice[(r - start_row) * (ne0 / 32) + kt].e = scale_src[row]; - } - } - } - } - } +static void ggml_backend_hexagon_host_buffer_set_tensor(ggml_backend_buffer_t buffer, + ggml_tensor * tensor, + const void * data, + size_t offset, + size_t size) { + memcpy((char *) tensor->data + offset, data, size); + GGML_UNUSED(buffer); } -// unsigned 6-bit value (0..63) of element e of a Q6_K block, same bit layout as dequantize_row_q6_K -static inline uint8_t q6_K_get_quant(const block_q6_K * b, int e) { - const int c = e / 128; - const int w = e % 128; - const int g = w / 32; - const int l = w % 32; - const uint8_t * ql = b->ql + c * 64; - const uint8_t * qh = b->qh + c * 32; - uint8_t lo, hi; - switch (g) { - case 0: lo = ql[l] & 0xF; hi = (qh[l] >> 0) & 3; break; - case 1: lo = ql[l + 32] & 0xF; hi = (qh[l] >> 2) & 3; break; - case 2: lo = ql[l] >> 4; hi = (qh[l] >> 4) & 3; break; - default: lo = ql[l + 32] >> 4; hi = (qh[l] >> 6) & 3; break; - } - return (uint8_t) (lo | (hi << 4)); +static void ggml_backend_hexagon_host_buffer_get_tensor(ggml_backend_buffer_t buffer, + const ggml_tensor * tensor, + void * data, + size_t offset, + size_t size) { + memcpy(data, (const char *) tensor->data + offset, size); + GGML_UNUSED(buffer); } -// tile layout: see HTP_MM_WEIGHT_TILE_SIZE_Q6_K in htp/matmul-ops.h -static void repack_q6_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - const block_q6_K * src_matrix = (const block_q6_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q6_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - const block_q6_K * src_slice = src_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - uint8_t * matrix_dst = (uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - memset(matrix_dst, 0, matrix_size); // padding rows and the OR-ed nibbles below need zeroed tiles - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - const block_q6_K * src_row = src_slice + r * sb_per_row; - - for (int kt = 0; kt < n_k_tiles; kt++) { - const int kt_local = kt % 8; // k-tile within the super-block - const block_q6_K * b = &src_row[kt / 8]; - const float d = GGML_FP16_TO_FP32(b->d); - - uint8_t * tile = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; - uint8_t * lo_pl = tile; - uint8_t * hi_pl = tile + 512; - ggml_half * sc_pl = (ggml_half *) (tile + 768); - - for (int lk = 0; lk < 32; lk++) { - const uint8_t q6 = q6_K_get_quant(b, kt_local * 32 + lk); - const int g = lk >> 2; - const int pos = row * 4 + (lk & 3); - lo_pl[(g >> 1) * 128 + pos] |= (uint8_t) ((q6 & 0xF) << ((g & 1) * 4)); - hi_pl[(g >> 2) * 128 + pos] |= (uint8_t) ((q6 >> 4) << ((g & 3) * 2)); - } - for (int sub = 0; sub < 2; sub++) { - sc_pl[sub * 32 + row] = GGML_FP32_TO_FP16(d * (float) b->scales[kt_local * 2 + sub]); - } - } - } - } - } - - GGML_UNUSED(size); -} - -// Reverse of repack_q6_K_tiled. Unpacks quants losslessly and normalizes sub-block scales. Read-back only. -static void repack_tiled_q6_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - block_q6_K * dst_matrix = (block_q6_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q6_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - block_q6_K * dst_slice = dst_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - const uint8_t * matrix_src = (const uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - block_q6_K * dst_row = dst_slice + r * sb_per_row; - - for (int64_t sb = 0; sb < sb_per_row; sb++) { - block_q6_K * b = &dst_row[sb]; - memset(b, 0, sizeof(block_q6_K)); - - float sub_scales[16]; - for (int kt_local = 0; kt_local < 8; kt_local++) { - const int kt = sb * 8 + kt_local; - const uint8_t * tile = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; - const uint8_t * lo_pl = tile; - const uint8_t * hi_pl = tile + 512; - const ggml_half * sc_pl = (const ggml_half *) (tile + 768); - - const int c = kt_local / 4; - const int g = kt_local % 4; - uint8_t * ql = b->ql + c * 64; - uint8_t * qh = b->qh + c * 32; - - for (int lk = 0; lk < 32; lk++) { - const int g_tile = lk >> 2; - const int pos = row * 4 + (lk & 3); - const uint8_t lo = (lo_pl[(g_tile >> 1) * 128 + pos] >> ((g_tile & 1) * 4)) & 0xF; - const uint8_t hi = (hi_pl[(g_tile >> 2) * 128 + pos] >> ((g_tile & 3) * 2)) & 3; - - switch (g) { - case 0: - ql[lk] |= lo; - qh[lk] |= (hi << 0); - break; - case 1: - ql[lk + 32] |= lo; - qh[lk] |= (hi << 2); - break; - case 2: - ql[lk] |= (lo << 4); - qh[lk] |= (hi << 4); - break; - default: - ql[lk + 32] |= (lo << 4); - qh[lk] |= (hi << 6); - break; - } - } +static ggml_backend_buffer_i ggml_backend_hexagon_host_buffer_interface = { + /* .free_buffer = */ ggml_backend_hexagon_buffer_free_buffer, + /* .get_base = */ ggml_backend_hexagon_buffer_get_base, + /* .init_tensor = */ ggml_backend_hexagon_buffer_init_tensor, + /* .memset_tensor = */ NULL, + /* .set_tensor = */ ggml_backend_hexagon_host_buffer_set_tensor, + /* .get_tensor = */ ggml_backend_hexagon_host_buffer_get_tensor, + /* .set_tensor_2d = */ NULL, + /* .get_tensor_2d = */ NULL, + /* .cpy_tensor = */ ggml_backend_hexagon_buffer_cpy_tensor, + /* .clear = */ ggml_backend_hexagon_buffer_clear, + /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, +}; - for (int sub = 0; sub < 2; sub++) { - sub_scales[kt_local * 2 + sub] = GGML_FP16_TO_FP32(sc_pl[sub * 32 + row]); - } - } +// ** backend buffer type - float max_abs_scale = 0.0f; - for (int s = 0; s < 16; s++) { - float abs_scale = fabsf(sub_scales[s]); - if (abs_scale > max_abs_scale) { - max_abs_scale = abs_scale; - } - } +static const char * ggml_backend_hexagon_buffer_type_name(ggml_backend_buffer_type_t buffer_type) { + return static_cast(buffer_type->context)->name.c_str(); +} - if (max_abs_scale == 0.0f) { - b->d = GGML_FP32_TO_FP16(0.0f); - memset(b->scales, 0, sizeof(b->scales)); - } else { - float d_flt = max_abs_scale / 127.0f; - b->d = GGML_FP32_TO_FP16(d_flt); - float d_actual = GGML_FP16_TO_FP32(b->d); - float inv_d = (d_actual != 0.0f) ? (1.0f / d_actual) : 0.0f; - for (int s = 0; s < 16; s++) { - int sc = (int) roundf(sub_scales[s] * inv_d); - b->scales[s] = (int8_t) (std::max)(-128, (std::min)(127, sc)); - } - } - } - } - } +static ggml_backend_buffer_t ggml_backend_hexagon_buffer_type_alloc_buffer( + ggml_backend_buffer_type_t buffer_type, size_t size) { + auto dev_ctx = static_cast(buffer_type->context)->dev_ctx; + auto sess = dev_ctx->session(); + if (sess && sess->max_vmem && size > sess->max_vmem) { + GGML_LOG_ERROR("ggml-hex: %s buffer size %zu exceeds max_vmem %zu\n", + dev_ctx->c_name(), size, sess->max_vmem); + return nullptr; + } + try { + ggml_hexagon_shared_buffer * sbuf = new ggml_hexagon_shared_buffer(sess, size, false); + return ggml_backend_buffer_init(buffer_type, ggml_backend_hexagon_buffer_interface, sbuf, size); + } catch (const std::exception & exc) { + GGML_LOG_ERROR("ggml-hex: %s failed to allocate device buffer context: %s\n", dev_ctx->c_name(), exc.what()); + return nullptr; } - - GGML_UNUSED(size); } -// low 2 bits (0..3) of element e of a Q2_K or Q3_K block, same bit layout as dequantize_row_q2_K / q3_K -static inline uint8_t q2_3_K_get_low2(const uint8_t * qs, int e) { - const int c = e / 128; - const int j = (e % 128) / 32; - const int l = e % 32; - return (qs[c * 32 + l] >> (2 * j)) & 3; +static ggml_backend_buffer_t ggml_backend_hexagon_host_buffer_type_alloc_buffer( + ggml_backend_buffer_type_t buffer_type, size_t size) { + auto dev_ctx = static_cast(buffer_type->context)->dev_ctx; + auto sess = dev_ctx->session(); + if (sess && sess->max_vmem && size > sess->max_vmem) { + GGML_LOG_ERROR("ggml-hex: %s host buffer size %zu exceeds max_vmem %zu\n", + dev_ctx->c_name(), size, sess->max_vmem); + return nullptr; + } + try { + ggml_hexagon_shared_buffer * sbuf = new ggml_hexagon_shared_buffer(sess, size, false); + return ggml_backend_buffer_init(buffer_type, ggml_backend_hexagon_host_buffer_interface, sbuf, size); + } catch (const std::exception & exc) { + GGML_LOG_ERROR("ggml-hex: %s failed to allocate host buffer context: %s\n", dev_ctx->c_name(), exc.what()); + return nullptr; + } } -// hmask bit of element e of a Q3_K block, same bit layout as dequantize_row_q3_K -static inline bool q3_K_get_hbit(const block_q3_K * b, int e) { - const int c = e / 128; - const int j = (e % 128) / 32; - const int l = e % 32; - return (b->hmask[l] >> (c * 4 + j)) & 1; +static size_t ggml_backend_hexagon_buffer_type_get_alignment(ggml_backend_buffer_type_t buft) { + return 128; // HVX alignment + GGML_UNUSED(buft); } -// signed 6-bit scale j (-32..31) of a Q3_K block, same packing as quantize_row_q3_K_ref -static inline int q3_K_get_scale(const uint8_t * scales, int j) { - const int lo = (j < 8) ? (scales[j] & 0xF) : (scales[j - 8] >> 4); - const int hi = (scales[8 + j % 4] >> (2 * (j / 4))) & 3; - return (lo | (hi << 4)) - 32; +static size_t ggml_backend_hexagon_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const struct ggml_tensor * t) { + if (!ggml_backend_buft_is_host(buft) && htp_is_tiled_weight_tensor(t)) { + int64_t ne0 = hex_round_up(t->ne[0], 32); + int64_t ne1 = hex_round_up(t->ne[1], 32); + int64_t ne2 = t->ne[2]; + int64_t ne3 = t->ne[3]; + size_t tiled_size = htp_tiled_row_size(t->type, ne0) * ne1 * ne2 * ne3; + return std::max(tiled_size, ggml_nbytes(t)); + } + return ggml_nbytes(t); } -// read-back: find fp16 d and l[j] in [lmin, lmax] with fp16(d * l[j]) == prod[j] for all j, false if none -static bool hexagon_recover_k_scales(const ggml_half * prod, int n, int lmin, int lmax, ggml_half * d_out, int * l_out) { - int jmax = 0; - for (int j = 1; j < n; j++) { - if (fabsf(GGML_FP16_TO_FP32(prod[j])) > fabsf(GGML_FP16_TO_FP32(prod[jmax]))) { - jmax = j; - } +static size_t parse_size(const char * str, size_t default_unit = 1024 * 1024) { + if (!str || str[0] == '\0') { + return 0; } - const float pmax = GGML_FP16_TO_FP32(prod[jmax]); - if (pmax == 0.0f) { - *d_out = GGML_FP32_TO_FP16(0.0f); - for (int j = 0; j < n; j++) { - l_out[j] = 0; - } - return true; + char * end = NULL; + double val = strtod(str, &end); + if (val < 0) { + return 0; } - - // the quantizers put the largest scale at or near the range end, so try large |l| first - const int lext = (std::max)(-lmin, lmax); - for (int a = lext; a >= 1; a--) { - for (int sign : { 1, -1 }) { - const int lj = sign * a; - if (lj < lmin || lj > lmax) { - continue; - } - const ggml_half d0 = GGML_FP32_TO_FP16(pmax / (float) lj); - for (int ulp : { 0, -1, 1 }) { - ggml_half d = d0; - uint16_t bits; - memcpy(&bits, &d, sizeof(bits)); - bits = (uint16_t) (bits + ulp); - memcpy(&d, &bits, sizeof(bits)); - - const float df = GGML_FP16_TO_FP32(d); - if (!std::isfinite(df) || df == 0.0f) { - continue; - } - bool ok = true; - for (int j = 0; j < n && ok; j++) { - const int l = (int) roundf(GGML_FP16_TO_FP32(prod[j]) / df); - const ggml_half p = GGML_FP32_TO_FP16(df * (float) l); - ok = l >= lmin && l <= lmax && memcmp(&p, &prod[j], sizeof(p)) == 0; - l_out[j] = l; - } - if (ok) { - *d_out = d; - return true; - } - } + if (end && *end) { + while (*end == ' ') end++; + if (*end == 'k' || *end == 'K') { + return (size_t) (val * 1024); + } else if (*end == 'm' || *end == 'M') { + return (size_t) (val * 1024 * 1024); + } else if (*end == 'g' || *end == 'G') { + return (size_t) (val * 1024 * 1024 * 1024); } } - return false; + return (size_t) (val * default_unit); } -// tile layout: see HTP_MM_WEIGHT_TILE_SIZE_Q3_K in htp/matmul-ops.h -static void repack_q3_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - const block_q3_K * src_matrix = (const block_q3_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q3_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - const block_q3_K * src_slice = src_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - uint8_t * matrix_dst = (uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - memset(matrix_dst, 0, matrix_size); // padding rows and the OR-ed bits below need zeroed tiles - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - const block_q3_K * src_row = src_slice + r * sb_per_row; - - for (int kt = 0; kt < n_k_tiles; kt++) { - const int kt_local = kt % 8; // k-tile within the super-block - const block_q3_K * b = &src_row[kt / 8]; - const float d = GGML_FP16_TO_FP32(b->d); - - uint8_t * tile = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; - uint8_t * lo_pl = tile; - uint8_t * neg_pl = tile + 256; - ggml_half * sc_pl = (ggml_half *) (tile + 384); - - for (int lk = 0; lk < 32; lk++) { - const int e = kt_local * 32 + lk; - const int g = lk >> 2; - const int pos = row * 4 + (lk & 3); - lo_pl[(g >> 2) * 128 + pos] |= (uint8_t) (q2_3_K_get_low2(b->qs, e) << ((g & 3) * 2)); - if (!q3_K_get_hbit(b, e)) { - neg_pl[pos] |= (uint8_t) (1 << g); - } - } - for (int sub = 0; sub < 2; sub++) { - sc_pl[sub * 32 + row] = GGML_FP32_TO_FP16(d * (float) q3_K_get_scale(b->scales, kt_local * 2 + sub)); - } - } - } - } - } +static size_t ggml_backend_hexagon_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) { + return opt_mbuf_dyn; + GGML_UNUSED(buft); +} - GGML_UNUSED(size); +static bool ggml_backend_hexagon_buffer_type_is_host(ggml_backend_buffer_type_t buft) { + return false; + GGML_UNUSED(buft); } -// Reverse of repack_q3_K_tiled. Unpacks quants losslessly and normalizes sub-block scales. Read-back only. -static void repack_tiled_q3_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - block_q3_K * dst_matrix = (block_q3_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q3_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - block_q3_K * dst_slice = dst_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - const uint8_t * matrix_src = (const uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - block_q3_K * dst_row = dst_slice + r * sb_per_row; - - for (int64_t sb = 0; sb < sb_per_row; sb++) { - block_q3_K * b = &dst_row[sb]; - memset(b, 0, sizeof(block_q3_K)); - - ggml_half sub_scales[16]; - for (int kt_local = 0; kt_local < 8; kt_local++) { - const int kt = sb * 8 + kt_local; - const uint8_t * tile = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; - const uint8_t * lo_pl = tile; - const uint8_t * neg_pl = tile + 256; - const ggml_half * sc_pl = (const ggml_half *) (tile + 384); - - for (int lk = 0; lk < 32; lk++) { - const int e = kt_local * 32 + lk; - const int g = lk >> 2; - const int pos = row * 4 + (lk & 3); - const uint8_t lo = (lo_pl[(g >> 2) * 128 + pos] >> ((g & 3) * 2)) & 3; - - const int c = e / 128; - const int j = (e % 128) / 32; - const int l = e % 32; - b->qs[c * 32 + l] |= (uint8_t) (lo << (2 * j)); - if (!((neg_pl[pos] >> g) & 1)) { - b->hmask[l] |= (uint8_t) (1 << (c * 4 + j)); - } - } +static bool ggml_backend_hexagon_host_buffer_type_is_host(ggml_backend_buffer_type_t buft) { + return true; + GGML_UNUSED(buft); +} - for (int sub = 0; sub < 2; sub++) { - sub_scales[kt_local * 2 + sub] = sc_pl[sub * 32 + row]; - } - } +struct ggml_backend_hexagon_alloc_buffer_n_plan_item { + size_t size; + int first; + int last; +}; - int ls[16]; - if (!hexagon_recover_k_scales(sub_scales, 16, -32, 31, &b->d, ls)) { - // no exact match: same scale choice as quantize_row_q3_K_ref - float max_scale = 0.0f; - for (int s = 0; s < 16; s++) { - if (fabsf(GGML_FP16_TO_FP32(sub_scales[s])) > fabsf(max_scale)) { - max_scale = GGML_FP16_TO_FP32(sub_scales[s]); - } - } - b->d = GGML_FP32_TO_FP16(-max_scale / 32.0f); - const float d_actual = GGML_FP16_TO_FP32(b->d); - const float inv_d = (d_actual != 0.0f) ? (1.0f / d_actual) : 0.0f; - for (int s = 0; s < 16; s++) { - ls[s] = (std::max)(-32, (std::min)(31, (int) roundf(GGML_FP16_TO_FP32(sub_scales[s]) * inv_d))); - } - } +using ggml_backend_hexagon_alloc_buffer_n_plan_t = std::vector; - for (int s = 0; s < 16; s++) { - const int l = ls[s] + 32; - if (s < 8) { - b->scales[s] = l & 0xF; - } else { - b->scales[s - 8] |= (uint8_t) ((l & 0xF) << 4); - } - b->scales[s % 4 + 8] |= (uint8_t) ((l >> 4) << (2 * (s / 4))); - } - } - } - } +static const char * ggml_hexagon_kv_layer_suffix(const struct ggml_tensor * t) { + if (strncmp(t->name, "cache_", 6) != 0) { + return NULL; } - - GGML_UNUSED(size); + const char * p = strstr(t->name, "_l"); + if (!p || !isdigit((unsigned char)p[2])) { + return NULL; + } + return p; } -// tile layout: see HTP_MM_WEIGHT_TILE_SIZE_Q2_K in htp/matmul-ops.h -static void repack_q2_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - const block_q2_K * src_matrix = (const block_q2_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); +struct ggml_backend_hexagon_alloc_unit { + size_t size; + int first; + int last; +}; - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q2_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; +static ggml_backend_hexagon_alloc_buffer_n_plan_t ggml_backend_hexagon_alloc_buffer_n_plan( + ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { + ggml_backend_hexagon_alloc_buffer_n_plan_t plan; - const int64_t sb_per_row = ne0 / QK_K; + const size_t alignment = ggml_backend_buft_get_alignment(buft); + const size_t max_size = opt_mbuf_static > 0 ? opt_mbuf_static : SIZE_MAX; - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - const block_q2_K * src_slice = src_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - uint8_t * matrix_dst = (uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; + std::vector units; - memset(matrix_dst, 0, matrix_size); // padding rows and the OR-ed bits below need zeroed tiles + int i = 0; + while (i < n_tensors) { + struct ggml_tensor * t = tensors[i]; + size_t unit_size = 0; + int unit_first = i; + int unit_last = i + 1; - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - const block_q2_K * src_row = src_slice + r * sb_per_row; + if (t->data == NULL && t->view_src == NULL) { + unit_size += GGML_PAD(ggml_backend_buft_get_alloc_size(buft, t), alignment); + } - for (int kt = 0; kt < n_k_tiles; kt++) { - const int kt_local = kt % 8; // k-tile within the super-block - const block_q2_K * b = &src_row[kt / 8]; + const char * layer_suffix = ggml_hexagon_kv_layer_suffix(t); - uint8_t * tile = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; - uint8_t * lo_pl = tile; - uint8_t * sc_pl = tile + 256; - ggml_half * dd_pl = (ggml_half *) (tile + 320); + while (unit_last < n_tensors) { + struct ggml_tensor * next = tensors[unit_last]; - for (int lk = 0; lk < 32; lk++) { - const int g = lk >> 2; - const int pos = row * 4 + (lk & 3); - lo_pl[(g >> 2) * 128 + pos] |= (uint8_t) (q2_3_K_get_low2(b->qs, kt_local * 32 + lk) << ((g & 3) * 2)); - } - for (int sub = 0; sub < 2; sub++) { - sc_pl[sub * 32 + row] = b->scales[kt_local * 2 + sub]; - } - if (row / 8 == kt_local % 4) { - dd_pl[row % 8] = kt_local < 4 ? b->d : (ggml_half) (b->dmin ^ 0x8000); // -dmin - } - } + if (next->view_src != NULL) { + unit_last++; + continue; } - } - } - - GGML_UNUSED(size); -} - -// Reverse of repack_q2_K_tiled. Lossless. Read-back only. -static void repack_tiled_q2_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - block_q2_K * dst_matrix = (block_q2_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q2_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - block_q2_K * dst_slice = dst_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - const uint8_t * matrix_src = (const uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - block_q2_K * dst_row = dst_slice + r * sb_per_row; - - for (int64_t sb = 0; sb < sb_per_row; sb++) { - block_q2_K * b = &dst_row[sb]; - memset(b, 0, sizeof(block_q2_K)); - - for (int kt_local = 0; kt_local < 8; kt_local++) { - const int kt = sb * 8 + kt_local; - const uint8_t * tile = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; - const uint8_t * lo_pl = tile; - const uint8_t * sc_pl = tile + 256; - const ggml_half * dd_pl = (const ggml_half *) (tile + 320); - - for (int lk = 0; lk < 32; lk++) { - const int e = kt_local * 32 + lk; - const int g = lk >> 2; - const int pos = row * 4 + (lk & 3); - const uint8_t lo = (lo_pl[(g >> 2) * 128 + pos] >> ((g & 3) * 2)) & 3; - b->qs[(e / 128) * 32 + e % 32] |= (uint8_t) (lo << (2 * ((e % 128) / 32))); - } - for (int sub = 0; sub < 2; sub++) { - b->scales[kt_local * 2 + sub] = sc_pl[sub * 32 + row]; - } - if (row / 8 == kt_local % 4) { - if (kt_local < 4) { - b->d = dd_pl[row % 8]; - } else { - b->dmin = (ggml_half) (dd_pl[row % 8] ^ 0x8000); - } - } + if (layer_suffix != NULL) { + const char * next_suffix = ggml_hexagon_kv_layer_suffix(next); + if (next_suffix != NULL && strcmp(layer_suffix, next_suffix) == 0) { + if (next->data == NULL) { + unit_size += GGML_PAD(ggml_backend_buft_get_alloc_size(buft, next), alignment); } + unit_last++; + continue; } } - } - } - GGML_UNUSED(size); -} + break; + } -static inline void get_scale_min_k4(int j, const uint8_t * q, uint8_t * d, uint8_t * m) { - if (j < 4) { - *d = q[j] & 63; - *m = q[j + 4] & 63; - } else { - *d = (q[j + 4] & 0xF) | ((q[j - 4] >> 6) << 4); - *m = (q[j + 4] >> 4) | ((q[j - 0] >> 6) << 4); + units.push_back({ unit_size, unit_first, unit_last }); + i = unit_last; } -} - -// tile layout: see HTP_MM_WEIGHT_TILE_SIZE_Q4_1 in htp/matmul-ops.h -static void repack_q4_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - const block_q4_K * src_matrix = (const block_q4_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_1; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - const block_q4_K * src_slice = src_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - uint8_t * matrix_dst = (uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - memset(matrix_dst, 0, matrix_size); - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - const block_q4_K * src_row = src_slice + r * sb_per_row; - - for (int kt = 0; kt < n_k_tiles; kt++) { - const int kt_local = kt % 8; - const block_q4_K * b = &src_row[kt / 8]; - const float d = GGML_FP16_TO_FP32(b->d); - const float dmin = GGML_FP16_TO_FP32(b->dmin); - - uint8_t * tile_dst = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; - - uint8_t sc, m; - get_scale_min_k4(kt_local, b->scales, &sc, &m); + size_t cur_buf_size = 0; + int cur_buf_first = 0; - const float D = d * (float) sc; - const float M = -dmin * (float) m; + for (const auto & unit : units) { + if (unit.size == 0) { + continue; + } - const uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; - const int shift = (kt_local & 1) ? 4 : 0; + if (cur_buf_size > 0 && (cur_buf_size + unit.size) > max_size) { + plan.push_back({ cur_buf_size, cur_buf_first, unit.first }); + cur_buf_size = 0; + cur_buf_first = unit.first; + } - for (int cp = 0; cp < 16; cp++) { - const uint8_t q0 = (qs_sub[2 * cp + 0] >> shift) & 0x0F; - const uint8_t q1 = (qs_sub[2 * cp + 1] >> shift) & 0x0F; - tile_dst[cp * 32 + row] = (uint8_t) ((q1 << 4) | q0); - } + cur_buf_size += unit.size; + } - ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); - scale_dst[2 * row + 0] = GGML_FP32_TO_FP16(D); - scale_dst[2 * row + 1] = GGML_FP32_TO_FP16(M); - } - } - } + if (cur_buf_size > 0) { + plan.push_back({ cur_buf_size, cur_buf_first, n_tensors }); } - GGML_UNUSED(size); + return plan; } -// Reverse of repack_q4_K_tiled. Unpacks quants and normalizes scales/mins. Read-back only. -static void repack_tiled_q4_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - block_q4_K * dst_matrix = (block_q4_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q4_1; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - block_q4_K * dst_slice = dst_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - const uint8_t * matrix_src = (const uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - block_q4_K * dst_row = dst_slice + r * sb_per_row; - - for (int64_t sb = 0; sb < sb_per_row; sb++) { - block_q4_K * b = &dst_row[sb]; - memset(b, 0, sizeof(block_q4_K)); - - float sub_scales[8]; - float sub_mins[8]; - - for (int kt_local = 0; kt_local < 8; kt_local++) { - const int kt = sb * 8 + kt_local; - const uint8_t * tile_src = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; - const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); - - uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; - const int shift = (kt_local & 1) ? 4 : 0; - - for (int cp = 0; cp < 16; cp++) { - const uint8_t val = tile_src[cp * 32 + row]; - const uint8_t q0 = val & 0x0F; - const uint8_t q1 = val >> 4; - qs_sub[2 * cp + 0] |= (uint8_t) (q0 << shift); - qs_sub[2 * cp + 1] |= (uint8_t) (q1 << shift); - } +static ggml_backend_buffer_t ggml_backend_hexagon_buffer_type_alloc_buffer_n( + ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { + const ggml_backend_hexagon_alloc_buffer_n_plan_t plan = ggml_backend_hexagon_alloc_buffer_n_plan(buft, tensors, n_tensors); - const float D = GGML_FP16_TO_FP32(scale_src[2 * row + 0]); - const float M = GGML_FP16_TO_FP32(scale_src[2 * row + 1]); - sub_scales[kt_local] = (D > 0.0f) ? D : 0.0f; - sub_mins[kt_local] = (-M > 0.0f) ? -M : 0.0f; - } + std::vector buffers; + buffers.reserve(plan.size()); - float max_scale = 0.0f; - float max_min = 0.0f; - for (int j = 0; j < 8; j++) { - if (sub_scales[j] > max_scale) max_scale = sub_scales[j]; - if (sub_mins[j] > max_min) max_min = sub_mins[j]; - } + for (const auto & item : plan) { + ggml_backend_buffer_t buffer = ggml_backend_buft_alloc_buffer(buft, item.size); + if (buffer == NULL) { + GGML_LOG_ERROR("%s: failed to allocate %s buffer of size %zu\n", __func__, ggml_backend_buft_name(buft), item.size); + for (ggml_backend_buffer_t b : buffers) { + ggml_backend_buffer_free(b); + } + return NULL; + } - float inv_scale = 0.0f; - if (max_scale > 0.0f) { - b->d = GGML_FP32_TO_FP16(max_scale / 63.0f); - const float d_actual = GGML_FP16_TO_FP32(b->d); - inv_scale = (d_actual > 0.0f) ? (1.0f / d_actual) : 0.0f; - } else { - b->d = GGML_FP32_TO_FP16(0.0f); - } + struct ggml_tallocr tallocr = ggml_tallocr_new(buffer); - float inv_min = 0.0f; - if (max_min > 0.0f) { - b->dmin = GGML_FP32_TO_FP16(max_min / 63.0f); - const float dmin_actual = GGML_FP16_TO_FP32(b->dmin); - inv_min = (dmin_actual > 0.0f) ? (1.0f / dmin_actual) : 0.0f; - } else { - b->dmin = GGML_FP32_TO_FP16(0.0f); + struct ggml_tensor * t_failed = NULL; + for (int j = item.first; j < item.last; j++) { + struct ggml_tensor * t = tensors[j]; + if (t->data == NULL) { + if (t->view_src == NULL) { + if (ggml_tallocr_alloc(&tallocr, t) != GGML_STATUS_SUCCESS) { + t_failed = t; + break; } - - for (int j = 0; j < 8; j++) { - uint8_t ls = (uint8_t) roundf(inv_scale * sub_scales[j]); - uint8_t lm = (uint8_t) roundf(inv_min * sub_mins[j]); - ls = (std::min)((uint8_t) 63, ls); - lm = (std::min)((uint8_t) 63, lm); - if (j < 4) { - b->scales[j] = ls; - b->scales[j + 4] = lm; - } else { - b->scales[j + 4] = (ls & 0xF) | ((lm & 0xF) << 4); - b->scales[j - 4] |= ((ls >> 4) << 6); - b->scales[j - 0] |= ((lm >> 4) << 6); - } + } else if (t->buffer == NULL) { + if (ggml_backend_view_init(t) != GGML_STATUS_SUCCESS) { + t_failed = t; + break; } } + } else { + if (t->view_src != NULL && t->buffer == NULL) { + if (ggml_backend_view_init(t) != GGML_STATUS_SUCCESS) { + t_failed = t; + break; + } + } + } + } + if (t_failed != NULL) { + GGML_LOG_ERROR("%s: failed to initialize tensor %s\n", __func__, t_failed->name); + for (ggml_backend_buffer_t b : buffers) { + ggml_backend_buffer_free(b); } + ggml_backend_buffer_free(buffer); + return NULL; } + + buffers.push_back(buffer); } - GGML_UNUSED(size); -} + if (buffers.empty()) { + return NULL; + } -// tile layout: see HTP_MM_WEIGHT_TILE_SIZE_Q5_K in htp/matmul-ops.h -static void repack_q5_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); + if (buffers.size() == 1) { + return buffers[0]; + } - const block_q5_K * src_matrix = (const block_q5_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); + return ggml_backend_multi_buffer_alloc_buffer(buffers.data(), buffers.size()); +} - GGML_ASSERT(ne0 % QK_K == 0); +static size_t ggml_backend_hexagon_buffer_type_get_alloc_size_n( + ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { + const ggml_backend_hexagon_alloc_buffer_n_plan_t plan = ggml_backend_hexagon_alloc_buffer_n_plan(buft, tensors, n_tensors); - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q5_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + size_t total = 0; + for (const auto & item : plan) { + total += item.size; + } + return total; +} - const int64_t sb_per_row = ne0 / QK_K; +static ggml_backend_buffer_type_i ggml_backend_hexagon_buffer_type_interface = { + /* .get_name = */ ggml_backend_hexagon_buffer_type_name, + /* .alloc_buffer = */ ggml_backend_hexagon_buffer_type_alloc_buffer, + /* .alloc_buffer_n = */ ggml_backend_hexagon_buffer_type_alloc_buffer_n, + /* .get_alignment = */ ggml_backend_hexagon_buffer_type_get_alignment, + /* .get_max_size = */ ggml_backend_hexagon_buffer_type_get_max_size, + /* .get_alloc_size = */ ggml_backend_hexagon_buffer_type_get_alloc_size, + /* .get_alloc_size_n = */ ggml_backend_hexagon_buffer_type_get_alloc_size_n, + /* .is_host = */ ggml_backend_hexagon_buffer_type_is_host, +}; - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - const block_q5_K * src_slice = src_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - uint8_t * matrix_dst = (uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; +static ggml_backend_buffer_type_i ggml_backend_hexagon_host_buffer_type_interface = { + /* .get_name = */ ggml_backend_hexagon_buffer_type_name, + /* .alloc_buffer = */ ggml_backend_hexagon_host_buffer_type_alloc_buffer, + /* .alloc_buffer_n = */ ggml_backend_hexagon_buffer_type_alloc_buffer_n, + /* .get_alignment = */ ggml_backend_hexagon_buffer_type_get_alignment, + /* .get_max_size = */ ggml_backend_hexagon_buffer_type_get_max_size, + /* .get_alloc_size = */ ggml_backend_hexagon_buffer_type_get_alloc_size, + /* .get_alloc_size_n = */ ggml_backend_hexagon_buffer_type_get_alloc_size_n, + /* .is_host = */ ggml_backend_hexagon_host_buffer_type_is_host, +}; - memset(matrix_dst, 0, matrix_size); +ggml_backend_hexagon_device_context::ggml_backend_hexagon_device_context(int dev_id, const ggml_hexagon_device_config & config, ggml_backend_dev_t dev) + : dev_id(dev_id), config(config), dev(dev) { + buffer_type.device = dev; + buffer_type.iface = ggml_backend_hexagon_buffer_type_interface; + buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name, this); - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - const block_q5_K * src_row = src_slice + r * sb_per_row; + host_buffer_type.device = dev; + host_buffer_type.iface = ggml_backend_hexagon_host_buffer_type_interface; + host_buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name + "-HOST", this); - for (int kt = 0; kt < n_k_tiles; kt++) { - const int kt_local = kt % 8; - const block_q5_K * b = &src_row[kt / 8]; - const float d = GGML_FP16_TO_FP32(b->d); - const float dmin = GGML_FP16_TO_FP32(b->dmin); + fence_buffer_type.device = dev; + fence_buffer_type.iface = ggml_backend_hexagon_buffer_type_interface; + fence_buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name + "-FENCE", this); +} - uint8_t * tile_dst = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; - uint8_t * plane = tile_dst + 640; +ggml_backend_hexagon_device_context::~ggml_backend_hexagon_device_context() { + delete static_cast(buffer_type.context); + delete static_cast(host_buffer_type.context); + delete static_cast(fence_buffer_type.context); +} - uint8_t sc, m; - get_scale_min_k4(kt_local, b->scales, &sc, &m); +static bool ggml_backend_buffer_is_hexagon(const struct ggml_backend_buffer * b) { + return b->buft->iface.get_alignment == ggml_backend_hexagon_buffer_type_get_alignment; +} - const float D = d * (float) sc; - const float M = -dmin * (float) m; +struct ggml_hexagon_opbatch { + ggml_hexagon_session* sess; - const uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; - const int shift = (kt_local & 1) ? 4 : 0; - const uint8_t hbit = (uint8_t) (1 << kt_local); + std::vector ops; // htp_opnode of ops - for (int cp = 0; cp < 16; cp++) { - const uint8_t q0 = (qs_sub[2 * cp + 0] >> shift) & 0x0F; - const uint8_t q1 = (qs_sub[2 * cp + 1] >> shift) & 0x0F; - tile_dst[cp * 32 + row] = (uint8_t) ((q1 << 4) | q0); + std::vector h_bufs; // htp buffer descriptors + std::vector h_tens; // htp tensor descriptors + std::vector h_ops; // htp op descriptors - const int i = cp / 4; - const int lane = (cp % 4) * 32 + row; - if (b->qh[2 * cp + 0] & hbit) { - plane[lane] |= (uint8_t) (1 << (2 * i)); - } - if (b->qh[2 * cp + 1] & hbit) { - plane[lane] |= (uint8_t) (1 << (2 * i + 1)); - } - } + std::unordered_map t_map; // tensor ptr to index + std::unordered_multimap d_map; // tensor data to index - ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); - scale_dst[2 * row + 0] = GGML_FP32_TO_FP16(D); - scale_dst[2 * row + 1] = GGML_FP32_TO_FP16(M); - } - } - } - } + unsigned int n_bufs; // num buffers in the batch + unsigned int n_tens; // num tensors ... + unsigned int n_ops; // num ops ... + size_t b_vmem; // sum of non-extended buffer sizes - GGML_UNUSED(size); -} + unsigned int n_bufs_max; + unsigned int n_tens_max; + unsigned int n_ops_max; + size_t b_vmem_max; -// Reverse of repack_q5_K_tiled. Unpacks quants losslessly and normalizes scales/mins. Read-back only. -static void repack_tiled_q5_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { - GGML_ASSERT(offset == 0); - - block_q5_K * dst_matrix = (block_q5_K *) data; - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - int64_t ne0_padded = hex_round_up(ne0, 32); - int64_t ne1_padded = hex_round_up(ne1, 32); - - GGML_ASSERT(ne0 % QK_K == 0); - - const int n_col_tiles = ne1_padded / 32; - const int n_k_tiles = ne0_padded / 32; - const size_t tile_size = HTP_MM_WEIGHT_TILE_SIZE_Q5_K; - const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; - - const int64_t sb_per_row = ne0 / QK_K; - - for (int i3 = 0; i3 < ne3; i3++) { - for (int i2 = 0; i2 < ne2; i2++) { - block_q5_K * dst_slice = dst_matrix + (i3 * ne2 + i2) * (ne1 * sb_per_row); - const uint8_t * matrix_src = (const uint8_t *) t->data + (i3 * ne2 + i2) * matrix_size; - - for (int64_t r = 0; r < ne1; r++) { - const int ct = (int) (r / 32); - const int row = (int) (r % 32); - block_q5_K * dst_row = dst_slice + r * sb_per_row; - - for (int64_t sb = 0; sb < sb_per_row; sb++) { - block_q5_K * b = &dst_row[sb]; - memset(b, 0, sizeof(block_q5_K)); - - float sub_scales[8]; - float sub_mins[8]; - - for (int kt_local = 0; kt_local < 8; kt_local++) { - const int kt = sb * 8 + kt_local; - const uint8_t * tile_src = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; - const uint8_t * plane = tile_src + 640; - const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); - - uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; - const int shift = (kt_local & 1) ? 4 : 0; - const uint8_t hbit = (uint8_t) (1 << kt_local); - - for (int cp = 0; cp < 16; cp++) { - const uint8_t val = tile_src[cp * 32 + row]; - const uint8_t q0 = val & 0x0F; - const uint8_t q1 = val >> 4; - qs_sub[2 * cp + 0] |= (uint8_t) (q0 << shift); - qs_sub[2 * cp + 1] |= (uint8_t) (q1 << shift); - - const int i = cp / 4; - const int lane = (cp % 4) * 32 + row; - if (plane[lane] & (1 << (2 * i))) { - b->qh[2 * cp + 0] |= hbit; - } - if (plane[lane] & (1 << (2 * i + 1))) { - b->qh[2 * cp + 1] |= hbit; - } - } + void reset() { + n_bufs = 0; + n_tens = 0; + n_ops = 0; + b_vmem = 0; - const float D = GGML_FP16_TO_FP32(scale_src[2 * row + 0]); - const float M = GGML_FP16_TO_FP32(scale_src[2 * row + 1]); - sub_scales[kt_local] = (D > 0.0f) ? D : 0.0f; - sub_mins[kt_local] = (-M > 0.0f) ? -M : 0.0f; - } + t_map.clear(); + d_map.clear(); + ops.resize(n_ops_max); + } - float max_scale = 0.0f; - float max_min = 0.0f; - for (int j = 0; j < 8; j++) { - if (sub_scales[j] > max_scale) max_scale = sub_scales[j]; - if (sub_mins[j] > max_min) max_min = sub_mins[j]; - } + ggml_hexagon_opbatch(ggml_hexagon_session *sess, size_t batch_size, size_t max_vmem) { + this->sess = sess; - float inv_scale = 0.0f; - if (max_scale > 0.0f) { - b->d = GGML_FP32_TO_FP16(max_scale / 63.0f); - const float d_actual = GGML_FP16_TO_FP32(b->d); - inv_scale = (d_actual > 0.0f) ? (1.0f / d_actual) : 0.0f; - } else { - b->d = GGML_FP32_TO_FP16(0.0f); - } + n_bufs_max = HTP_OP_MAX_BUFS; + n_ops_max = batch_size; + n_tens_max = std::min(n_ops_max * 4 + HTP_OP_MAX_INPUTS + HTP_OP_MAX_OUTPUTS, HTP_OP_MAX_TENSORS); - float inv_min = 0.0f; - if (max_min > 0.0f) { - b->dmin = GGML_FP32_TO_FP16(max_min / 63.0f); - const float dmin_actual = GGML_FP16_TO_FP32(b->dmin); - inv_min = (dmin_actual > 0.0f) ? (1.0f / dmin_actual) : 0.0f; - } else { - b->dmin = GGML_FP32_TO_FP16(0.0f); - } + b_vmem_max = max_vmem; - for (int j = 0; j < 8; j++) { - uint8_t ls = (uint8_t) roundf(inv_scale * sub_scales[j]); - uint8_t lm = (uint8_t) roundf(inv_min * sub_mins[j]); - ls = (std::min)((uint8_t) 63, ls); - lm = (std::min)((uint8_t) 63, lm); - if (j < 4) { - b->scales[j] = ls; - b->scales[j + 4] = lm; - } else { - b->scales[j + 4] = (ls & 0xF) | ((lm & 0xF) << 4); - b->scales[j - 4] |= ((ls >> 4) << 6); - b->scales[j - 0] |= ((lm >> 4) << 6); - } - } - } - } - } - } + ops.resize(n_ops_max); - GGML_UNUSED(size); -} + h_bufs.resize(n_bufs_max); + h_tens.resize(n_tens_max); + h_ops.resize(n_ops_max); -static void repack_tensor_tiled(ggml_tensor * tensor, const void * data, size_t size) { - switch (tensor->type) { - case GGML_TYPE_Q4_0: - repack_q4_0_tiled(tensor, data, 0, size); - break; + t_map.reserve(n_tens_max); + d_map.reserve(n_tens_max); - case GGML_TYPE_Q4_1: - repack_q4_1_tiled(tensor, data, 0, size); - break; + GGML_LOG_INFO("ggml-hex: %s op batching: n-bufs %u n-tensors %u n-ops %u vmem %zu\n", + sess->c_name(), n_bufs_max, n_tens_max, n_ops_max, b_vmem_max); - case GGML_TYPE_Q4_K: - repack_q4_K_tiled(tensor, data, 0, size); - break; + reset(); + } - case GGML_TYPE_Q8_0: - repack_q8_0_tiled(tensor, data, 0, size); - break; + bool empty() const { return n_ops == 0; } + bool full() const { return n_ops >= n_ops_max; } - case GGML_TYPE_IQ4_NL: - repack_q4_0_tiled(tensor, data, 0, size); - break; + int find_buffer(int fd) const { + for (unsigned int i = 0; i < n_bufs; i++) { + if ((int) h_bufs[i].fd == fd) { + return (int) i; + } + } + return -1; + } - case GGML_TYPE_MXFP4: - repack_mxfp4_tiled(tensor, data, 0, size); - break; + // add buffer and return its index + int add_buffer(ggml_hexagon_shared_buffer * sbuf) { + // Lookup by fd + int bi = find_buffer(sbuf->fd()); + if (bi >= 0) { return bi; } - case GGML_TYPE_Q5_K: - repack_q5_K_tiled(tensor, data, 0, size); - break; + // Add new buffer to the batch + GGML_ASSERT(n_bufs < HTP_OP_MAX_BUFS); + bi = n_bufs++; - case GGML_TYPE_Q6_K: - repack_q6_K_tiled(tensor, data, 0, size); - break; + htp_buf_desc &b = h_bufs[bi]; + b.base = (uint64_t) sbuf->base(); + b.fd = sbuf->fd(); + b.size = sbuf->size(); + b.flags = sbuf->extended ? HTP_BUF_EXTENDED : 0; - case GGML_TYPE_Q3_K: - repack_q3_K_tiled(tensor, data, 0, size); - break; + if (!sbuf->extended) { + b_vmem += b.size; + } - case GGML_TYPE_Q2_K: - repack_q2_K_tiled(tensor, data, 0, size); - break; + HEX_VERBOSE("ggml-hex: %s add-buffer #%u : fd %d base %p size %zu : vmem %zu\n", sess->c_name(), bi, b.fd, (void*) sbuf->base(), (size_t) b.size, b_vmem); - default: - break; + return bi; } -} -static void ggml_backend_hexagon_buffer_set_tensor(ggml_backend_buffer_t buffer, - ggml_tensor * tensor, - const void * data, - size_t offset, - size_t size) { - auto extra = (ggml_hexagon_tensor_extra *) tensor->extra; - auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; - auto sess = sbuf->sess; + static void init_tensor_shape(htp_tensor & h, const ggml_tensor * t) { + auto extra = (htp_tensor_extra *) t->extra; - if (ggml_backend_buffer_get_usage(buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS) { - extra->flags |= GGML_HEXAGON_TENSOR_WEIGHT; - if (ggml_hexagon_is_repack_type(tensor->type)) { - extra->flags |= GGML_HEXAGON_TENSOR_REPACK; + h.type = t->type; + h.ne[0] = t->ne[0]; + h.ne[1] = t->ne[1]; + h.ne[2] = t->ne[2]; + h.ne[3] = t->ne[3]; + + if (extra->flags & HTP_TENSOR_TILED) { + if (t->type == GGML_TYPE_F32 || t->type == GGML_TYPE_BF16) { + h.type = GGML_TYPE_F16; + h.nb[0] = sizeof(ggml_fp16_t); + } else { + h.nb[0] = t->nb[0]; + } + const int64_t ne0_padded = hex_round_up(t->ne[0], 32); + const int64_t ne1_padded = hex_round_up(t->ne[1], 32); + h.nb[1] = htp_tiled_row_size(t->type, ne0_padded); + h.nb[2] = h.nb[1] * ne1_padded; + h.nb[3] = h.nb[2] * h.ne[2]; + h.size = h.nb[3] * h.ne[3]; + } else { + h.nb[0] = t->nb[0]; + h.nb[1] = t->nb[1]; + h.nb[2] = t->nb[2]; + h.nb[3] = t->nb[3]; + h.size = ggml_nbytes(t); } - } - - HEX_VERBOSE("ggml-hex: %s set-tensor %s : data %p offset %zu size %zu usage %d flags 0x%x\n", - sess->c_name(), tensor->name, data, offset, size, (int) buffer->usage, extra->flags); - if ((extra->flags & GGML_HEXAGON_TENSOR_REPACK) == 0) { - memcpy((char *) tensor->data + offset, data, size); - return; + h.flags = extra->flags & (HTP_TENSOR_WEIGHT | HTP_TENSOR_TILED | HTP_TENSOR_FENCE); } - if (offset == 0 && size == ggml_nbytes(tensor) && extra->shadow_buf.empty()) { - repack_tensor_tiled(tensor, data, size); - return; + static bool same_shape(const htp_tensor & a, const htp_tensor & b) { + return (a.type == b.type) && + (a.ne[0] == b.ne[0]) && (a.ne[1] == b.ne[1]) && (a.ne[2] == b.ne[2]) && (a.ne[3] == b.ne[3]) && + (a.nb[0] == b.nb[0]) && (a.nb[1] == b.nb[1]) && (a.nb[2] == b.nb[2]) && (a.nb[3] == b.nb[3]); } - if (extra->shadow_buf.size() < ggml_nbytes(tensor)) { - extra->shadow_buf.resize(ggml_nbytes(tensor)); - } - memcpy(extra->shadow_buf.data() + offset, data, size); - extra->shadow_size += size; + // add tensor and return its index + int add_tensor(const ggml_tensor * t) { + // Lookup by tensor ptr + auto it = t_map.find(t); + if (it != t_map.end()) { return it->second; } - if (extra->shadow_size >= ggml_nbytes(tensor)) { - repack_tensor_tiled(tensor, extra->shadow_buf.data(), extra->shadow_buf.size()); - extra->shadow_buf.clear(); - extra->shadow_buf.shrink_to_fit(); - extra->shadow_size = 0; - } -} + htp_tensor shape {}; + init_tensor_shape(shape, t); -static void ggml_backend_hexagon_buffer_get_tensor(ggml_backend_buffer_t buffer, - const ggml_tensor * tensor, - void * data, - size_t offset, - size_t size) { - auto extra = (ggml_hexagon_tensor_extra *) tensor->extra; - auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; - auto sess = sbuf->sess; + // Lookup by tensor data and shape + auto range = d_map.equal_range(t->data); + for (auto dit = range.first; dit != range.second; ++dit) { + if (same_shape(h_tens[dit->second], shape)) { + t_map.insert({t, dit->second}); + return dit->second; + } + } - HEX_VERBOSE("ggml-hex: %s get-tensor %s : data %p offset %zu size %zu usage %d flags 0x%x\n", - sess->c_name(), tensor->name, data, offset, size, (int) buffer->usage, extra->flags); + auto sbuf = static_cast(t->buffer->context); - if ((extra->flags & GGML_HEXAGON_TENSOR_REPACK) == 0) { - memcpy(data, (const char *) tensor->data + offset, size); - return; - } + // Add new tensor to the batch + int ti = n_tens++; + GGML_ASSERT(n_tens <= n_tens_max); - switch (tensor->type) { - case GGML_TYPE_Q4_0: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q4_0(data, tensor, offset, size); - break; + t_map.insert({t, ti}); + d_map.insert({t->data, ti}); - case GGML_TYPE_Q4_1: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q4_1(data, tensor, offset, size); - break; + uint64_t t_offset = (uint8_t *) t->data - sbuf->base(); - case GGML_TYPE_Q4_K: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q4_K(data, tensor, offset, size); - break; + htp_tensor & h = h_tens[ti]; + h = shape; + h.bi = add_buffer(sbuf); + h.ti = ti; + h.data = t_offset; - case GGML_TYPE_Q5_K: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q5_K(data, tensor, offset, size); - break; + HEX_VERBOSE("ggml-hex: %s add-tensor #%u %s : bi %d data %p offset %zu size %zu flags 0x%x : %zu:%zu:%zu:%zu\n", sess->c_name(), + ti, t->name, h.bi, (void*) t->data, (size_t) t_offset, (size_t) h.size, h.flags, + (size_t) h.ne[0], (size_t) h.ne[1], (size_t) h.ne[2], (size_t) h.ne[3]); - case GGML_TYPE_Q8_0: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q8_0(data, tensor, offset, size); - break; - - case GGML_TYPE_IQ4_NL: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q4_0(data, tensor, offset, size); - break; - - case GGML_TYPE_MXFP4: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_mxfp4(data, tensor, offset, size); - break; - - case GGML_TYPE_Q6_K: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q6_K(data, tensor, offset, size); - break; - - case GGML_TYPE_Q3_K: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q3_K(data, tensor, offset, size); - break; - - case GGML_TYPE_Q2_K: - GGML_ASSERT(offset == 0); - GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); - repack_tiled_q2_K(data, tensor, offset, size); - break; - - default: - memcpy(data, (const char *) tensor->data + offset, size); - break; - } -} - -static bool ggml_backend_hexagon_buffer_cpy_tensor(ggml_backend_buffer_t buffer, - const struct ggml_tensor * src, - struct ggml_tensor * dst) { - // we might optimize this later, for now take the slow path (ie get/set_tensor) - return false; - - GGML_UNUSED(buffer); - GGML_UNUSED(src); - GGML_UNUSED(dst); -} - -static void ggml_backend_hexagon_buffer_set_tensor_2d(ggml_backend_buffer_t buffer, - ggml_tensor * tensor, - const void * data, - size_t offset, - size_t size, - size_t n_copies, - size_t stride_tensor, - size_t stride_data) { - auto extra = (ggml_hexagon_tensor_extra *) tensor->extra; - auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; - auto sess = sbuf->sess; - - if (ggml_backend_buffer_get_usage(buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS) { - extra->flags |= GGML_HEXAGON_TENSOR_WEIGHT; - if (ggml_hexagon_is_repack_type(tensor->type)) { - extra->flags |= GGML_HEXAGON_TENSOR_REPACK; - } - } - - HEX_VERBOSE("ggml-hex: %s set-tensor-2d %s : data %p offset %zu size %zu n_copies %zu stride_tensor %zu stride_data %zu usage %d flags 0x%x\n", - sess->c_name(), tensor->name, data, offset, size, n_copies, stride_tensor, stride_data, (int) buffer->usage, extra->flags); - - if ((extra->flags & GGML_HEXAGON_TENSOR_REPACK) == 0) { - for (size_t i = 0; i < n_copies; i++) { - memcpy((uint8_t *) tensor->data + offset + i * stride_tensor, (const uint8_t *) data + i * stride_data, size); - } - return; - } - - if (extra->shadow_buf.size() < ggml_nbytes(tensor)) { - extra->shadow_buf.resize(ggml_nbytes(tensor)); - } - for (size_t i = 0; i < n_copies; i++) { - memcpy(extra->shadow_buf.data() + offset + i * stride_tensor, (const uint8_t *) data + i * stride_data, size); - } - extra->shadow_size += n_copies * size; - - if (extra->shadow_size >= ggml_nbytes(tensor)) { - repack_tensor_tiled(tensor, extra->shadow_buf.data(), extra->shadow_buf.size()); - extra->shadow_buf.clear(); - extra->shadow_buf.shrink_to_fit(); - extra->shadow_size = 0; - } -} - -static void ggml_backend_hexagon_buffer_get_tensor_2d(ggml_backend_buffer_t buffer, - const ggml_tensor * tensor, - void * data, - size_t offset, - size_t size, - size_t n_copies, - size_t stride_tensor, - size_t stride_data) { - auto extra = (ggml_hexagon_tensor_extra *) tensor->extra; - auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; - auto sess = sbuf->sess; - - HEX_VERBOSE("ggml-hex: %s get-tensor-2d %s : data %p offset %zu size %zu n_copies %zu stride_tensor %zu stride_data %zu usage %d\n", - sess->c_name(), tensor->name, data, offset, size, n_copies, stride_tensor, stride_data, (int) buffer->usage); - - if ((extra->flags & GGML_HEXAGON_TENSOR_REPACK) == 0) { - for (size_t i = 0; i < n_copies; i++) { - memcpy((uint8_t *)data + i * stride_data, (const uint8_t *)tensor->data + offset + i * stride_tensor, size); - } - return; - } - - size_t temp_size = n_copies > 0 ? (n_copies - 1) * stride_tensor + size : 0; - size_t slice_size = tensor->ne[1] * ggml_row_size(tensor->type, tensor->ne[0]); - size_t slice_offset = offset % slice_size; - size_t row_size_bytes = ggml_row_size(tensor->type, tensor->ne[0]); - - GGML_ASSERT((slice_offset % row_size_bytes) == 0 && "offset must be aligned to row boundary"); - GGML_ASSERT((temp_size % row_size_bytes) == 0 && "temp_size must be a multiple of row size"); - GGML_ASSERT((slice_offset / row_size_bytes) % 32 == 0 && "offset must be aligned to tile size (32 rows)"); - GGML_ASSERT((offset + temp_size) <= ggml_nbytes(tensor)); - - std::vector temp_buf(temp_size); - - switch (tensor->type) { - case GGML_TYPE_Q4_0: - repack_tiled_q4_0(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q4_1: - repack_tiled_q4_1(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q4_K: - repack_tiled_q4_K(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q5_K: - repack_tiled_q5_K(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q8_0: - repack_tiled_q8_0(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_IQ4_NL: - repack_tiled_q4_0(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_MXFP4: - repack_tiled_mxfp4(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q6_K: - repack_tiled_q6_K(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q3_K: - repack_tiled_q3_K(temp_buf.data(), tensor, offset, temp_size); - break; - - case GGML_TYPE_Q2_K: - repack_tiled_q2_K(temp_buf.data(), tensor, offset, temp_size); - break; - - default: - memcpy(temp_buf.data(), (const uint8_t *) tensor->data + offset, temp_size); - break; - } - - for (size_t i = 0; i < n_copies; i++) { - memcpy((uint8_t *) data + i * stride_data, temp_buf.data() + i * stride_tensor, size); - } -} - -static void ggml_backend_hexagon_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { - auto sbuf = (ggml_hexagon_shared_buffer *) buffer->context; - auto sess = sbuf->sess; - HEX_VERBOSE("ggml-hex: %s clear-buff base %p size %zu\n", sess->c_name(), (void *) sbuf->base(), sbuf->size()); - memset(sbuf->base(), value, sbuf->size()); -} - -static ggml_backend_buffer_i ggml_backend_hexagon_buffer_interface = { - /* .free_buffer = */ ggml_backend_hexagon_buffer_free_buffer, - /* .get_base = */ ggml_backend_hexagon_buffer_get_base, - /* .init_tensor = */ ggml_backend_hexagon_buffer_init_tensor, - /* .memset_tensor = */ NULL, - /* .set_tensor = */ ggml_backend_hexagon_buffer_set_tensor, - /* .get_tensor = */ ggml_backend_hexagon_buffer_get_tensor, - /* .set_tensor_2d = */ ggml_backend_hexagon_buffer_set_tensor_2d, - /* .get_tensor_2d = */ ggml_backend_hexagon_buffer_get_tensor_2d, - /* .cpy_tensor = */ ggml_backend_hexagon_buffer_cpy_tensor, - /* .clear = */ ggml_backend_hexagon_buffer_clear, - /* .reset = */ NULL, -}; - -// ** backend buffer type - -static void ggml_backend_hexagon_host_buffer_set_tensor(ggml_backend_buffer_t buffer, - ggml_tensor * tensor, - const void * data, - size_t offset, - size_t size) { - memcpy((char *) tensor->data + offset, data, size); - GGML_UNUSED(buffer); -} - -static void ggml_backend_hexagon_host_buffer_get_tensor(ggml_backend_buffer_t buffer, - const ggml_tensor * tensor, - void * data, - size_t offset, - size_t size) { - memcpy(data, (const char *) tensor->data + offset, size); - GGML_UNUSED(buffer); -} - -static ggml_backend_buffer_i ggml_backend_hexagon_host_buffer_interface = { - /* .free_buffer = */ ggml_backend_hexagon_buffer_free_buffer, - /* .get_base = */ ggml_backend_hexagon_buffer_get_base, - /* .init_tensor = */ ggml_backend_hexagon_buffer_init_tensor, - /* .memset_tensor = */ NULL, - /* .set_tensor = */ ggml_backend_hexagon_host_buffer_set_tensor, - /* .get_tensor = */ ggml_backend_hexagon_host_buffer_get_tensor, - /* .set_tensor_2d = */ NULL, - /* .get_tensor_2d = */ NULL, - /* .cpy_tensor = */ ggml_backend_hexagon_buffer_cpy_tensor, - /* .clear = */ ggml_backend_hexagon_buffer_clear, - /* .reset = */ NULL, -}; - -// ** backend buffer type - -static const char * ggml_backend_hexagon_buffer_type_name(ggml_backend_buffer_type_t buffer_type) { - return static_cast(buffer_type->context)->name.c_str(); -} - -static ggml_backend_buffer_t ggml_backend_hexagon_buffer_type_alloc_buffer( - ggml_backend_buffer_type_t buffer_type, size_t size) { - auto dev_ctx = static_cast(buffer_type->context)->dev_ctx; - auto sess = dev_ctx->session(); - if (sess && sess->max_vmem && size > sess->max_vmem) { - GGML_LOG_ERROR("ggml-hex: %s buffer size %zu exceeds max_vmem %zu\n", - dev_ctx->c_name(), size, sess->max_vmem); - return nullptr; - } - try { - ggml_hexagon_shared_buffer * sbuf = new ggml_hexagon_shared_buffer(sess, size, false); - return ggml_backend_buffer_init(buffer_type, ggml_backend_hexagon_buffer_interface, sbuf, size); - } catch (const std::exception & exc) { - GGML_LOG_ERROR("ggml-hex: %s failed to allocate device buffer context: %s\n", dev_ctx->c_name(), exc.what()); - return nullptr; - } -} - -static ggml_backend_buffer_t ggml_backend_hexagon_host_buffer_type_alloc_buffer( - ggml_backend_buffer_type_t buffer_type, size_t size) { - auto dev_ctx = static_cast(buffer_type->context)->dev_ctx; - auto sess = dev_ctx->session(); - if (sess && sess->max_vmem && size > sess->max_vmem) { - GGML_LOG_ERROR("ggml-hex: %s host buffer size %zu exceeds max_vmem %zu\n", - dev_ctx->c_name(), size, sess->max_vmem); - return nullptr; - } - try { - ggml_hexagon_shared_buffer * sbuf = new ggml_hexagon_shared_buffer(sess, size, false); - return ggml_backend_buffer_init(buffer_type, ggml_backend_hexagon_host_buffer_interface, sbuf, size); - } catch (const std::exception & exc) { - GGML_LOG_ERROR("ggml-hex: %s failed to allocate host buffer context: %s\n", dev_ctx->c_name(), exc.what()); - return nullptr; - } -} - -static size_t ggml_backend_hexagon_buffer_type_get_alignment(ggml_backend_buffer_type_t buft) { - return 128; // HVX alignment - GGML_UNUSED(buft); -} - -static size_t ggml_backend_hexagon_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const struct ggml_tensor * t) { - if (ggml_hexagon_is_repack_type(t->type)) { - int64_t ne0 = hex_round_up(t->ne[0], 32); - int64_t ne1 = hex_round_up(t->ne[1], 32); - int64_t ne2 = t->ne[2]; - int64_t ne3 = t->ne[3]; - return ggml_hexagon_tiled_row_size(t->type, ne0) * ne1 * ne2 * ne3; - } - return ggml_nbytes(t); - - GGML_UNUSED(buft); -} - -static size_t parse_size(const char * str, size_t default_unit = 1024 * 1024) { - if (!str || str[0] == '\0') { - return 0; - } - char * end = NULL; - double val = strtod(str, &end); - if (val < 0) { - return 0; - } - if (end && *end) { - while (*end == ' ') end++; - if (*end == 'k' || *end == 'K') { - return (size_t) (val * 1024); - } else if (*end == 'm' || *end == 'M') { - return (size_t) (val * 1024 * 1024); - } else if (*end == 'g' || *end == 'G') { - return (size_t) (val * 1024 * 1024 * 1024); - } - } - return (size_t) (val * default_unit); -} - -static size_t ggml_backend_hexagon_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) { - return opt_mbuf_dyn; - GGML_UNUSED(buft); -} - -static bool ggml_backend_hexagon_buffer_type_is_host(ggml_backend_buffer_type_t buft) { - return false; - GGML_UNUSED(buft); -} - -static bool ggml_backend_hexagon_host_buffer_type_is_host(ggml_backend_buffer_type_t buft) { - return true; - GGML_UNUSED(buft); -} - -struct ggml_backend_hexagon_alloc_buffer_n_plan_item { - size_t size; - int first; - int last; -}; - -using ggml_backend_hexagon_alloc_buffer_n_plan_t = std::vector; - -static const char * ggml_hexagon_kv_layer_suffix(const struct ggml_tensor * t) { - if (strncmp(t->name, "cache_", 6) != 0) { - return NULL; - } - const char * p = strstr(t->name, "_l"); - if (!p || !isdigit((unsigned char)p[2])) { - return NULL; - } - return p; -} - -struct ggml_backend_hexagon_alloc_unit { - size_t size; - int first; - int last; -}; - -static ggml_backend_hexagon_alloc_buffer_n_plan_t ggml_backend_hexagon_alloc_buffer_n_plan( - ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { - ggml_backend_hexagon_alloc_buffer_n_plan_t plan; - - const size_t alignment = ggml_backend_buft_get_alignment(buft); - const size_t max_size = opt_mbuf_static > 0 ? opt_mbuf_static : SIZE_MAX; - - std::vector units; - - int i = 0; - while (i < n_tensors) { - struct ggml_tensor * t = tensors[i]; - size_t unit_size = 0; - int unit_first = i; - int unit_last = i + 1; - - if (t->data == NULL && t->view_src == NULL) { - unit_size += GGML_PAD(ggml_backend_buft_get_alloc_size(buft, t), alignment); - } - - const char * layer_suffix = ggml_hexagon_kv_layer_suffix(t); - - while (unit_last < n_tensors) { - struct ggml_tensor * next = tensors[unit_last]; - - if (next->view_src != NULL) { - unit_last++; - continue; - } - - if (layer_suffix != NULL) { - const char * next_suffix = ggml_hexagon_kv_layer_suffix(next); - if (next_suffix != NULL && strcmp(layer_suffix, next_suffix) == 0) { - if (next->data == NULL) { - unit_size += GGML_PAD(ggml_backend_buft_get_alloc_size(buft, next), alignment); - } - unit_last++; - continue; - } - } - - break; - } - - units.push_back({ unit_size, unit_first, unit_last }); - i = unit_last; - } - - size_t cur_buf_size = 0; - int cur_buf_first = 0; - - for (const auto & unit : units) { - if (unit.size == 0) { - continue; - } - - if (cur_buf_size > 0 && (cur_buf_size + unit.size) > max_size) { - plan.push_back({ cur_buf_size, cur_buf_first, unit.first }); - cur_buf_size = 0; - cur_buf_first = unit.first; - } - - cur_buf_size += unit.size; - } - - if (cur_buf_size > 0) { - plan.push_back({ cur_buf_size, cur_buf_first, n_tensors }); - } - - return plan; -} - -static ggml_backend_buffer_t ggml_backend_hexagon_buffer_type_alloc_buffer_n( - ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { - const ggml_backend_hexagon_alloc_buffer_n_plan_t plan = ggml_backend_hexagon_alloc_buffer_n_plan(buft, tensors, n_tensors); - - std::vector buffers; - buffers.reserve(plan.size()); - - for (const auto & item : plan) { - ggml_backend_buffer_t buffer = ggml_backend_buft_alloc_buffer(buft, item.size); - if (buffer == NULL) { - GGML_LOG_ERROR("%s: failed to allocate %s buffer of size %zu\n", __func__, ggml_backend_buft_name(buft), item.size); - for (ggml_backend_buffer_t b : buffers) { - ggml_backend_buffer_free(b); - } - return NULL; - } - - struct ggml_tallocr tallocr = ggml_tallocr_new(buffer); - - struct ggml_tensor * t_failed = NULL; - for (int j = item.first; j < item.last; j++) { - struct ggml_tensor * t = tensors[j]; - if (t->data == NULL) { - if (t->view_src == NULL) { - if (ggml_tallocr_alloc(&tallocr, t) != GGML_STATUS_SUCCESS) { - t_failed = t; - break; - } - } else if (t->buffer == NULL) { - if (ggml_backend_view_init(t) != GGML_STATUS_SUCCESS) { - t_failed = t; - break; - } - } - } else { - if (t->view_src != NULL && t->buffer == NULL) { - if (ggml_backend_view_init(t) != GGML_STATUS_SUCCESS) { - t_failed = t; - break; - } - } - } - } - if (t_failed != NULL) { - GGML_LOG_ERROR("%s: failed to initialize tensor %s\n", __func__, t_failed->name); - for (ggml_backend_buffer_t b : buffers) { - ggml_backend_buffer_free(b); - } - ggml_backend_buffer_free(buffer); - return NULL; - } - - buffers.push_back(buffer); - } - - if (buffers.empty()) { - return NULL; - } - - if (buffers.size() == 1) { - return buffers[0]; - } - - return ggml_backend_multi_buffer_alloc_buffer(buffers.data(), buffers.size()); -} - -static size_t ggml_backend_hexagon_buffer_type_get_alloc_size_n( - ggml_backend_buffer_type_t buft, struct ggml_tensor ** tensors, int n_tensors) { - const ggml_backend_hexagon_alloc_buffer_n_plan_t plan = ggml_backend_hexagon_alloc_buffer_n_plan(buft, tensors, n_tensors); - - size_t total = 0; - for (const auto & item : plan) { - total += item.size; - } - return total; -} - -static ggml_backend_buffer_type_i ggml_backend_hexagon_buffer_type_interface = { - /* .get_name = */ ggml_backend_hexagon_buffer_type_name, - /* .alloc_buffer = */ ggml_backend_hexagon_buffer_type_alloc_buffer, - /* .alloc_buffer_n = */ ggml_backend_hexagon_buffer_type_alloc_buffer_n, - /* .get_alignment = */ ggml_backend_hexagon_buffer_type_get_alignment, - /* .get_max_size = */ ggml_backend_hexagon_buffer_type_get_max_size, - /* .get_alloc_size = */ ggml_backend_hexagon_buffer_type_get_alloc_size, - /* .get_alloc_size_n = */ ggml_backend_hexagon_buffer_type_get_alloc_size_n, - /* .is_host = */ ggml_backend_hexagon_buffer_type_is_host, -}; - -static ggml_backend_buffer_type_i ggml_backend_hexagon_host_buffer_type_interface = { - /* .get_name = */ ggml_backend_hexagon_buffer_type_name, - /* .alloc_buffer = */ ggml_backend_hexagon_host_buffer_type_alloc_buffer, - /* .alloc_buffer_n = */ ggml_backend_hexagon_buffer_type_alloc_buffer_n, - /* .get_alignment = */ ggml_backend_hexagon_buffer_type_get_alignment, - /* .get_max_size = */ ggml_backend_hexagon_buffer_type_get_max_size, - /* .get_alloc_size = */ ggml_backend_hexagon_buffer_type_get_alloc_size, - /* .get_alloc_size_n = */ ggml_backend_hexagon_buffer_type_get_alloc_size_n, - /* .is_host = */ ggml_backend_hexagon_host_buffer_type_is_host, -}; - -ggml_backend_hexagon_device_context::ggml_backend_hexagon_device_context(int dev_id, const ggml_hexagon_device_config & config, ggml_backend_dev_t dev) - : dev_id(dev_id), config(config), dev(dev) { - buffer_type.device = dev; - buffer_type.iface = ggml_backend_hexagon_buffer_type_interface; - buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name, this); - - host_buffer_type.device = dev; - host_buffer_type.iface = ggml_backend_hexagon_host_buffer_type_interface; - host_buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name + "-HOST", this); - - fence_buffer_type.device = dev; - fence_buffer_type.iface = ggml_backend_hexagon_buffer_type_interface; - fence_buffer_type.context = new ggml_backend_hexagon_buffer_type_context(config.name + "-FENCE", this); -} - -ggml_backend_hexagon_device_context::~ggml_backend_hexagon_device_context() { - delete static_cast(buffer_type.context); - delete static_cast(host_buffer_type.context); - delete static_cast(fence_buffer_type.context); -} - -static bool ggml_backend_buffer_is_hexagon(const struct ggml_backend_buffer * b) { - return b->buft->iface.get_alignment == ggml_backend_hexagon_buffer_type_get_alignment; -} - -struct ggml_hexagon_opbatch { - ggml_hexagon_session* sess; - - std::vector ops; // htp_opnode of ops - - std::vector h_bufs; // htp buffer descriptors - std::vector h_tens; // htp tensor descriptors - std::vector h_ops; // htp op descriptors - - std::unordered_map b_map; // buffer fd to index - std::unordered_map t_map; // tensor ptr to index - std::unordered_multimap d_map; // tensor data to index - - unsigned int n_bufs; // num buffers in the batch - unsigned int n_tens; // num tensors ... - unsigned int n_ops; // num ops ... - size_t b_vmem; // sum of non-extended buffer sizes - - unsigned int n_bufs_max; - unsigned int n_tens_max; - unsigned int n_ops_max; - size_t b_vmem_max; - - void reset() { - n_bufs = 0; - n_tens = 0; - n_ops = 0; - b_vmem = 0; - - b_map.clear(); - t_map.clear(); - d_map.clear(); - ops.resize(n_ops_max); - } - - ggml_hexagon_opbatch(ggml_hexagon_session *sess, size_t batch_size, size_t max_vmem) { - this->sess = sess; - - n_bufs_max = HTP_OP_MAX_BUFS; - n_ops_max = batch_size; - n_tens_max = std::min(n_ops_max + n_ops_max * HTP_OP_MAX_INPUTS, HTP_OP_MAX_TENSORS); - - b_vmem_max = max_vmem; - - ops.resize(n_ops_max); - - h_bufs.resize(n_bufs_max); - h_tens.resize(n_tens_max); - h_ops.resize(n_ops_max); - - b_map.reserve(n_bufs_max); - t_map.reserve(n_tens_max); - d_map.reserve(n_tens_max); - - GGML_LOG_INFO("ggml-hex: %s op batching: n-bufs %u n-tensors %u n-ops %u vmem %zu\n", - sess->c_name(), n_bufs_max, n_tens_max, n_ops_max, b_vmem_max); - - reset(); - } - - bool empty() const { return n_ops == 0; } - - // add buffer and return its index - int add_buffer(ggml_hexagon_shared_buffer * sbuf) { - // Lookup by fd - auto it = b_map.find(sbuf->fd()); - if (it != b_map.end()) { return it->second; } - - // Add new buffer to the batch - GGML_ASSERT(n_bufs < HTP_OP_MAX_BUFS); - int bi = n_bufs++; - - b_map.insert({sbuf->fd(), bi}); - - htp_buf_desc &b = h_bufs[bi]; - b.base = (uint64_t) sbuf->base(); - b.fd = sbuf->fd(); - b.size = sbuf->size(); - b.flags = sbuf->extended ? HTP_BUF_EXTENDED : 0; - - if (!sbuf->extended) { - b_vmem += b.size; - } - - HEX_VERBOSE("ggml-hex: %s add-buffer #%u : fd %d base %p size %zu : vmem %zu\n", sess->c_name(), bi, b.fd, (void*) sbuf->base(), (size_t) b.size, b_vmem); - - return bi; - } - - bool same_shape(const htp_tensor * h, const ggml_tensor * t) const { - auto extra = (ggml_hexagon_tensor_extra *) t->extra; - - int64_t ne0 = t->ne[0]; - int64_t ne1 = t->ne[1]; - const bool is_repack = (extra->flags & GGML_HEXAGON_TENSOR_REPACK) != 0; - if (is_repack) { - ne0 = hex_round_up(ne0, 32); - ne1 = hex_round_up(ne1, 32); - } - int64_t nb1 = is_repack ? (int64_t) ggml_hexagon_tiled_row_size(t->type, ne0) : t->nb[1]; - int64_t nb2 = is_repack ? nb1 * ne1 : t->nb[2]; - int64_t nb3 = is_repack ? nb2 * t->ne[2] : t->nb[3]; - - return (h->type == t->type) && - (h->ne[0] == ne0) && (h->ne[1] == ne1) && (h->ne[2] == t->ne[2]) && (h->ne[3] == t->ne[3]) && - (h->nb[0] == t->nb[0]) && (h->nb[1] == nb1) && (h->nb[2] == nb2) && (h->nb[3] == nb3); - } - - // add tensor and return its index - int add_tensor(const ggml_tensor * t) { - auto extra = (ggml_hexagon_tensor_extra *) t->extra; - auto sbuf = static_cast(t->buffer->context); - - // First lookup by tensor data - auto range = d_map.equal_range(t->data); - for (auto it = range.first; it != range.second; ++it) { - htp_tensor * h = &h_tens[it->second]; - if (same_shape(h, t)) { return it->second; } - } - - // Lookup by tensor ptr - auto it = t_map.find(t); - if (it != t_map.end()) { return it->second; } - - // Add new tensor to the batch - int ti = n_tens++; - GGML_ASSERT(n_tens <= n_tens_max); - - t_map.insert({t, ti}); - d_map.insert({t->data, ti}); - - uint64_t t_offset = (uint8_t *) t->data - sbuf->base(); - size_t t_size = ggml_nbytes(t); - - htp_tensor &h = h_tens[ti]; - h.bi = add_buffer(sbuf); - h.ti = ti; - h.data = t_offset; - h.type = t->type; - - const bool is_repack = (extra->flags & GGML_HEXAGON_TENSOR_REPACK) != 0; - if (is_repack) { - h.ne[0] = hex_round_up(t->ne[0], 32); - h.ne[1] = hex_round_up(t->ne[1], 32); - h.ne[2] = t->ne[2]; - h.ne[3] = t->ne[3]; - - h.nb[0] = t->nb[0]; - h.nb[1] = ggml_hexagon_tiled_row_size(t->type, h.ne[0]); - h.nb[2] = h.nb[1] * h.ne[1]; - h.nb[3] = h.nb[2] * h.ne[2]; - h.size = h.nb[3] * h.ne[3]; - t_size = h.size; - } else { - h.size = t_size; - h.ne[0] = t->ne[0]; h.ne[1] = t->ne[1]; h.ne[2] = t->ne[2]; h.ne[3] = t->ne[3]; - h.nb[0] = t->nb[0]; h.nb[1] = t->nb[1]; h.nb[2] = t->nb[2]; h.nb[3] = t->nb[3]; - } - - h.flags = 0; - if ((extra->flags & GGML_HEXAGON_TENSOR_WEIGHT) != 0) { - h.flags |= HTP_TENSOR_WEIGHT; - } - if ((extra->flags & GGML_HEXAGON_TENSOR_REPACK) != 0) { - h.flags |= HTP_TENSOR_REPACK; - } - if ((extra->flags & GGML_HEXAGON_TENSOR_FENCE) != 0) { - h.flags |= HTP_TENSOR_FENCE; - } - - HEX_VERBOSE("ggml-hex: %s add-tensor #%u %s : bi %d data %p offset %zu size %zu flags 0x%x : %zu:%zu:%zu:%zu\n", sess->c_name(), - ti, t->name, h.bi, (void*) t->data, (size_t) t_offset, t_size, h.flags, - (size_t) h.ne[0], (size_t) h.ne[1], (size_t) h.ne[2], (size_t) h.ne[3]); - - return ti; - } - - bool fit_op(const htp_opnode & node) const { - if (n_ops >= n_ops_max) return false; - - // check how much extras we will need - size_t extra_bufs = 0; - size_t extra_vmem = 0; - size_t extra_tens = 0; - - int seen_bufs[HTP_OP_MAX_BUFS]; - int n_seen_bufs = 0; - - auto fit_tensor = [&](const ggml_tensor *t) { - if (!t) return; - if (!t_map.count(t)) { - extra_tens++; - - auto sbuf = static_cast(t->buffer->context); - int fd = sbuf->fd(); - if (!b_map.count(fd)) { - for (int i = 0; i < n_seen_bufs; i++) { - if (seen_bufs[i] == fd) return; - } - if (n_seen_bufs < HTP_OP_MAX_BUFS) { - seen_bufs[n_seen_bufs++] = fd; - } - if (!sbuf->extended) { - extra_vmem += sbuf->size(); - } - extra_bufs += 1; - } - } - }; - - for (const auto * src : node.get_inputs()) { - fit_tensor(src); - } - for (const auto * output : node.get_outputs()) { - fit_tensor(output); - } - - if ((extra_bufs + n_bufs) > n_bufs_max) return false; - if ((extra_tens + n_tens) > n_tens_max) return false; - if ((extra_vmem + b_vmem) > b_vmem_max) return false; - - return true; - } - - // assumes that fit_op() was called first and returned true - void add_op(const htp_opnode & node) { - // Add new op - - unsigned int n = n_ops++; - GGML_ASSERT(n_ops <= n_ops_max); - - ops[n] = node; - - htp_op_desc &o = h_ops[n]; - memcpy(o.params, node.node->op_params, sizeof(node.node->op_params)); - memcpy(o.kernel_params, node.kernel_params, sizeof(o.kernel_params)); - o.opcode = node.opcode; - o.flags = 0; - - ggml_hexagon_dump_op_exec(sess->c_name(), ops[n], o.flags); - - auto inputs = node.get_inputs(); - for (unsigned int i=0; i < HTP_OP_MAX_INPUTS; i++) { - o.src[i] = (i < inputs.size() && inputs[i]) ? add_tensor(inputs[i]) : 0xffff; - } - - auto outputs = node.get_outputs(); - for (unsigned int i=0; i < HTP_OP_MAX_OUTPUTS; i++) { - o.dst[i] = (i < outputs.size() && outputs[i]) ? add_tensor(outputs[i]) : 0xffff; - } - } - - void sort_buffers() { - if (n_bufs <= 1) return; - - std::vector order(n_bufs); - for (unsigned int i = 0; i < n_bufs; i++) { order[i] = (int) i; } - - std::stable_sort(order.begin(), order.end(), [&](int a, int b) { - return h_bufs[a].size > h_bufs[b].size; - }); - - bool already_sorted = true; - for (unsigned int i = 0; i < n_bufs; i++) { - if (order[i] != (int) i) { - already_sorted = false; - break; - } - } - if (already_sorted) return; - - std::vector remap(n_bufs); - std::vector sorted_bufs(n_bufs); - for (unsigned int new_bi = 0; new_bi < n_bufs; new_bi++) { - int old_bi = order[new_bi]; - remap[old_bi] = (uint16_t) new_bi; - sorted_bufs[new_bi] = h_bufs[old_bi]; - } - - for (unsigned int i = 0; i < n_bufs; i++) { - h_bufs[i] = sorted_bufs[i]; - } - - for (unsigned int i = 0; i < n_tens; i++) { - h_tens[i].bi = remap[h_tens[i].bi]; - } - } - - void update_mdev_group(uint32_t mdev_idx) { - if (n_ops > 0 && h_ops[0].opcode == HTP_OP_MDEV_GROUP) { - h_ops[0].params[0] = (int32_t) mdev_idx; - } - } - - bool try_fuse_common(std::initializer_list tensors) const { - size_t extra_bufs = 0, extra_vmem = 0, extra_tens = 0; - - int seen_bufs[HTP_OP_MAX_BUFS]; - int n_seen_bufs = 0; - - for (const auto * t : tensors) { - if (!t || t_map.count(t)) { - continue; - } - extra_tens++; - auto sbuf = static_cast(t->buffer->context); - int fd = sbuf->fd(); - if (!b_map.count(fd)) { - bool found = false; - for (int i = 0; i < n_seen_bufs; i++) { - if (seen_bufs[i] == fd) { - found = true; - break; - } - } - if (!found) { - if (n_seen_bufs < HTP_OP_MAX_BUFS) { - seen_bufs[n_seen_bufs++] = fd; - } - if (!sbuf->extended) { - extra_vmem += sbuf->size(); - } - extra_bufs += 1; - } - } - } - - if ((extra_bufs + n_bufs) > n_bufs_max || (extra_tens + n_tens) > n_tens_max || (extra_vmem + b_vmem) > b_vmem_max) { - return false; - } - - return true; - } - - bool try_fuse_common(const ggml_tensor * t1, const ggml_tensor * t2) const { - return try_fuse_common({t1, t2}); - } - - bool try_fuse_allreduce_add(const htp_opnode & node) { - if (n_ops == 0 || opt_ar_select != 2) return false; - if (node.opcode != HTP_OP_ADD) return false; - - htp_opnode & last_node = ops[n_ops - 1]; - if (last_node.opcode != HTP_OP_ALLREDUCE) return false; - - auto * ar_kparams = (struct htp_allreduce_kernel_params *) last_node.kernel_params; - const uint32_t rank = (uint32_t) ar_kparams->rank; - const uint32_t n_ranks = (uint32_t) ar_kparams->n_ranks; - const ggml_tensor * ar_local = last_node.inputs[rank]; - const ggml_tensor * add_src0 = node.src0(); - const ggml_tensor * add_src1 = node.src1(); - const ggml_tensor * add_dst = node.dst(); - - if (!ggml_hexagon_tensor_is_fuseable(ar_local)) return false; - - const ggml_tensor * res_tensor; - if (add_src0 == ar_local || add_src0->data == ar_local->data) { - res_tensor = add_src1; - } else if (add_src1 == ar_local || add_src1->data == ar_local->data) { - res_tensor = add_src0; - } else { - return false; - } - - if (ar_local->type != res_tensor->type) return false; - - const bool is_same_shape = (ar_local->ne[0] == res_tensor->ne[0] && ar_local->ne[1] == res_tensor->ne[1] && - ar_local->ne[2] == res_tensor->ne[2] && ar_local->ne[3] == res_tensor->ne[3]); - const bool is_row_bcast = !is_same_shape && (ar_local->ne[0] == res_tensor->ne[0] && res_tensor->ne[1] == 1 && - res_tensor->ne[2] == 1 && res_tensor->ne[3] == 1); - - if (!is_same_shape && !is_row_bcast) return false; - - if (is_same_shape) { - if (ar_local->nb[1] != res_tensor->nb[1] || ar_local->nb[2] != res_tensor->nb[2] || - ar_local->nb[3] != res_tensor->nb[3]) { - return false; - } - if (ggml_is_contiguous(ar_local) != ggml_is_contiguous(res_tensor)) { - return false; - } - } - if (ggml_is_contiguous(ar_local) != ggml_is_contiguous(add_dst)) { - return false; - } - - // scatter is only valid for in-place add within max outputs - const bool is_shard_ok = n_ranks <= HTP_OP_MAX_OUTPUTS && add_dst->data == ar_local->data; - - struct htp_allreduce_kernel_params new_kparams; - if (!ggml_hexagon_precompute_allreduce_params( - sess, add_dst, (uint32_t) ar_kparams->rank, (uint32_t) ar_kparams->n_ranks, true, is_row_bcast, is_shard_ok, &new_kparams - )) { - HEX_VERBOSE("ggml-hex: %s skip ALLREDUCE_ADD fusion: solver failed\n", sess->c_name()); - return false; - } - - const bool scatter_ok = new_kparams.n_dsts > 1; - new_kparams.mode = scatter_ok ? HTP_ALLREDUCE_SHARDED_FANOUT : HTP_ALLREDUCE_FULL; - - for (uint32_t r = 0; r < n_ranks; r++) { - const ggml_tensor * ar_src = last_node.inputs[r]; - if (!ggml_hexagon_tensors_overlap(add_dst, ar_src)) { - continue; - } - // in-place aliasing is safe under reduce-scatter since each rank writes disjoint shards - if (scatter_ok && r == rank) { - continue; - } - HEX_VERBOSE("ggml-hex: %s skip ALLREDUCE_ADD fusion: dst overlaps allreduce src %u\n", sess->c_name(), r); - return false; - } - - if (!try_fuse_common(res_tensor, add_dst)) { - return false; - } - - last_node.opcode = HTP_OP_ALLREDUCE_ADD; - last_node.name = "ALLREDUCE+ADD"; - last_node.inputs.push_back(res_tensor); - last_node.outputs.clear(); - last_node.outputs.push_back(add_dst); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &new_kparams, sizeof(new_kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.opcode = HTP_OP_ALLREDUCE_ADD; - memcpy(o.kernel_params, &new_kparams, sizeof(new_kparams)); - - o.src[2 * n_ranks] = add_tensor(res_tensor); - if (new_kparams.mode == HTP_ALLREDUCE_SHARDED_FANOUT) { - // fan out shard to all per-rank partial buffers - GGML_ASSERT((uint32_t) new_kparams.n_dsts == n_ranks); - for (uint32_t d = 0; d < n_ranks; d++) { - GGML_ASSERT(o.src[d] != 0xffff); - o.dst[d] = o.src[d]; - } - for (uint32_t d = n_ranks; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - } else { - o.dst[0] = add_tensor(add_dst); - for (uint32_t d = 1; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - } - - HEX_VERBOSE("ggml-hex: %s fused ALLREDUCE+ADD (#%u) mode=%d n_dsts=%d\n", - sess->c_name(), n_ops - 1, (int) new_kparams.mode, (int) new_kparams.n_dsts); - return true; - } - - bool try_fuse_rms_norm_mul(const htp_opnode & node) { - if (n_ops == 0) return false; - if (node.opcode != HTP_OP_MUL) return false; - - htp_opnode & last_node = ops[n_ops - 1]; - if (last_node.opcode != HTP_OP_RMS_NORM) return false; - - const ggml_tensor * mul_src0 = node.src0(); - const ggml_tensor * mul_src1 = node.src1(); - const ggml_tensor * rms_out = last_node.dst(); - - if (!ggml_hexagon_tensor_is_fuseable(rms_out)) return false; - - const ggml_tensor * weight; - if (mul_src0 == rms_out || mul_src0->data == rms_out->data) { - weight = mul_src1; - } else if (mul_src1 == rms_out || mul_src1->data == rms_out->data) { - weight = mul_src0; - } else { - return false; - } - - const ggml_tensor * src0 = last_node.src0(); - - if (src0->ne[0] != weight->ne[0] || src0->ne[0] != node.dst()->ne[0]) { - return false; - } - - const bool is_row_bcast = (weight->ne[1] == 1 && weight->ne[2] == 1 && weight->ne[3] == 1); - const bool is_same_shape = (src0->ne[0] == weight->ne[0] && src0->ne[1] == weight->ne[1] && - src0->ne[2] == weight->ne[2] && src0->ne[3] == weight->ne[3]); - if (!is_row_bcast && !is_same_shape) return false; - - if (!ggml_are_same_shape(src0, node.dst())) { - return false; - } - if (ggml_is_contiguous(src0) != ggml_is_contiguous(node.dst())) { - return false; - } - - struct htp_unary_kernel_params new_kparams; - ggml_hexagon_precompute_unary_params( - sess, HTP_OP_RMS_NORM_MUL, src0, weight, node.dst(), &new_kparams - ); - - if ((size_t) new_kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip RMS_NORM_MUL fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), new_kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (!try_fuse_common(weight, node.dst())) { - return false; - } - - last_node.opcode = HTP_OP_RMS_NORM_MUL; - last_node.name = "RMS_NORM+MUL"; - last_node.inputs.clear(); - last_node.inputs.push_back(src0); - last_node.inputs.push_back(weight); - last_node.outputs.clear(); - last_node.outputs.push_back(node.dst()); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &new_kparams, sizeof(new_kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.opcode = HTP_OP_RMS_NORM_MUL; - memcpy(o.kernel_params, &new_kparams, sizeof(new_kparams)); - - o.src[0] = add_tensor(src0); - o.src[1] = add_tensor(weight); - for (uint32_t s = 2; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - o.dst[0] = add_tensor(node.dst()); - for (uint32_t d = 1; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused RMS_NORM+MUL (#%u)\n", sess->c_name(), n_ops - 1); - return true; - } - - bool try_fuse_mul_mat_add(const htp_opnode & node) { - if (n_ops == 0) return false; - if (node.opcode != HTP_OP_ADD) return false; - - htp_opnode & last_node = ops[n_ops - 1]; - if (last_node.opcode != HTP_OP_MUL_MAT) return false; - - const ggml_tensor * add_src0 = node.src0(); - const ggml_tensor * add_src1 = node.src1(); - const ggml_tensor * mm_out = last_node.dst(); - - if (!ggml_hexagon_tensor_is_fuseable(mm_out)) return false; - - const ggml_tensor * src2; - if (add_src0 == mm_out || add_src0->data == mm_out->data) { - src2 = add_src1; - } else if (add_src1 == mm_out || add_src1->data == mm_out->data) { - src2 = add_src0; - } else { - return false; - } - - const ggml_tensor * src0 = last_node.src0(); - const ggml_tensor * src1 = last_node.src1(); - - if (src2->type != GGML_TYPE_F32) return false; - - const struct htp_mm_kernel_params * orig_kparams = (const struct htp_mm_kernel_params *) last_node.kernel_params; - struct htp_mm_kernel_params kparams; - ggml_hexagon_precompute_fused_matmul_add_params(sess, src0, src1, src2, node.dst(), &kparams); - if (kparams.kernel_type == HTP_MM_KERNEL_UNSUPPORTED) { - return false; - } - - if (orig_kparams->collapse != kparams.collapse) { - return false; - } - - const int src1_nrows = src1->ne[1] * src1->ne[2] * src1->ne[3]; - const bool can_fuse = (kparams.n_hmx > 0) || (src1_nrows == 1); - if (!can_fuse) return false; - - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip MUL_MAT_ADD fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (kparams.n_hmx > 0 && orig_kparams->n_hmx > 0) { - if (kparams.m_chunk < orig_kparams->m_chunk || - kparams.n_chunk < orig_kparams->n_chunk || - kparams.n_act_threads < orig_kparams->n_act_threads) { - HEX_VERBOSE("ggml-hex: %s skip MUL_MAT_ADD fusion: HMX efficiency reduced (m %d->%d, n %d->%d, th %d->%d)\n", - sess->c_name(), orig_kparams->m_chunk, kparams.m_chunk, - orig_kparams->n_chunk, kparams.n_chunk, - orig_kparams->n_act_threads, kparams.n_act_threads); - return false; - } - } - - if (!try_fuse_common(src2, node.dst())) { - return false; - } - - last_node.opcode = HTP_OP_MUL_MAT_ADD; - last_node.name = "MUL_MAT+ADD"; - last_node.inputs.clear(); - last_node.inputs.push_back(src0); - last_node.inputs.push_back(src1); - last_node.inputs.push_back(src2); - last_node.outputs.clear(); - last_node.outputs.push_back(node.dst()); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &kparams, sizeof(kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.opcode = HTP_OP_MUL_MAT_ADD; - memcpy(o.kernel_params, &kparams, sizeof(kparams)); - - o.src[0] = add_tensor(src0); - o.src[1] = add_tensor(src1); - o.src[2] = add_tensor(src2); - for (uint32_t s = 3; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - o.dst[0] = add_tensor(node.dst()); - for (uint32_t d = 1; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused MUL_MAT+ADD (#%u)\n", sess->c_name(), n_ops - 1); - return true; - } - - bool try_fuse_mul_mat_nx(const htp_opnode & node) { - if (n_ops == 0 || node.opcode != HTP_OP_MUL_MAT) return false; - if (!is_mergeable_mul_mat(node.node)) return false; - - const ggml_tensor * w_in = node.src0(); - const ggml_tensor * x_in = node.src1(); - const ggml_tensor * d_in = node.dst(); - - htp_opnode & last_node = ops[n_ops - 1]; - - // Case 1: last_node is already MUL_MAT_NX - if (last_node.opcode == HTP_OP_MUL_MAT_NX) { - const uint32_t curr_n = (uint32_t) last_node.outputs.size(); - if (curr_n >= HTP_OP_MAX_OUTPUTS || curr_n + 1 >= HTP_OP_MAX_INPUTS) { - return false; - } - - const ggml_tensor * w0 = last_node.inputs[0]; - const ggml_tensor * x = last_node.inputs[curr_n]; - - if (x_in != x || w_in->type != w0->type || w_in->ne[0] != w0->ne[0]) { - return false; - } - if (!last_node.fused.empty() && (mm_is_hmx_eligible(last_node.fused[0]) != mm_is_hmx_eligible(node.node))) { - return false; - } - - const struct htp_mm_kernel_params * orig_kparams = (const struct htp_mm_kernel_params *) last_node.kernel_params; - const bool collapse = orig_kparams->collapse && ggml_hexagon_matmul_can_collapse(w_in, x, d_in); - if (orig_kparams->collapse && !collapse) { - return false; - } - - struct htp_mm_kernel_params kparams; - if (collapse) { - const ggml_tensor x_collapsed = ggml_hexagon_tensor_collapse_rows(x); - ggml_hexagon_precompute_fused_mmnx_params(sess, w0, &x_collapsed, curr_n + 1, &kparams); - kparams.collapse = 1; - } else { - ggml_hexagon_precompute_fused_mmnx_params(sess, w0, x, curr_n + 1, &kparams); - } - if (!is_supported_mul_mat_nx_kernel(w0, &kparams)) { - return false; - } - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip NX fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (!try_fuse_common(w_in, d_in)) { - return false; - } - - last_node.inputs[curr_n] = w_in; - last_node.inputs.push_back(x); - last_node.outputs.push_back(d_in); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &kparams, sizeof(kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - memcpy(o.kernel_params, &kparams, sizeof(kparams)); - - for (uint32_t s = 0; s <= curr_n + 1; s++) { - o.src[s] = add_tensor(last_node.inputs[s]); - } - for (uint32_t s = curr_n + 2; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - for (uint32_t d = 0; d <= curr_n; d++) { - o.dst[d] = add_tensor(last_node.outputs[d]); - } - for (uint32_t d = curr_n + 1; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused MUL_MAT_NX (N=%u, #%u)\n", sess->c_name(), curr_n + 1, n_ops - 1); - return true; - } - - // Case 2: last_node is single MUL_MAT - if (last_node.opcode == HTP_OP_MUL_MAT) { - if (!is_mergeable_mul_mat_pair(last_node.node, node.node)) { - return false; - } - - const ggml_tensor * w0 = last_node.src0(); - const ggml_tensor * x = last_node.src1(); - const ggml_tensor * w1 = node.src0(); - const ggml_tensor * dst_0 = last_node.dst(); - const ggml_tensor * dst_1 = node.dst(); - - const struct htp_mm_kernel_params * orig_kparams = (const struct htp_mm_kernel_params *) last_node.kernel_params; - const bool collapse = orig_kparams->collapse && ggml_hexagon_matmul_can_collapse(w1, x, dst_1); - if (orig_kparams->collapse && !collapse) { - return false; - } - - struct htp_mm_kernel_params kparams; - if (collapse) { - const ggml_tensor x_collapsed = ggml_hexagon_tensor_collapse_rows(x); - ggml_hexagon_precompute_fused_mmnx_params(sess, w0, &x_collapsed, 2, &kparams); - kparams.collapse = 1; - } else { - ggml_hexagon_precompute_fused_mmnx_params(sess, w0, x, 2, &kparams); - } - if (!is_supported_mul_mat_nx_kernel(w0, &kparams)) { - return false; - } - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip NX fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (!try_fuse_common(w1, node.dst())) { - return false; - } - - last_node.opcode = HTP_OP_MUL_MAT_NX; - last_node.name = "MUL_MAT_NX"; - last_node.inputs.clear(); - last_node.inputs.push_back(w0); - last_node.inputs.push_back(w1); - last_node.inputs.push_back(x); - last_node.outputs.clear(); - last_node.outputs.push_back(dst_0); - last_node.outputs.push_back(dst_1); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &kparams, sizeof(kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.opcode = HTP_OP_MUL_MAT_NX; - memcpy(o.kernel_params, &kparams, sizeof(kparams)); - - o.src[0] = add_tensor(w0); - o.src[1] = add_tensor(w1); - o.src[2] = add_tensor(x); - for (uint32_t s = 3; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - o.dst[0] = add_tensor(dst_0); - o.dst[1] = add_tensor(dst_1); - for (uint32_t d = 2; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused MUL_MAT_NX (N=2, #%u)\n", sess->c_name(), n_ops - 1); - return true; - } - - return false; - } - - bool try_fuse_mul_mat_id_nx(const htp_opnode & node) { - if (n_ops == 0 || node.opcode != HTP_OP_MUL_MAT_ID) return false; - if (!is_mergeable_mul_mat_id(node.node)) return false; - - const ggml_tensor * w_in = node.src0(); - const ggml_tensor * x_in = node.src1(); - const ggml_tensor * ids_in = node.node->src[2]; - const ggml_tensor * d_in = node.dst(); - - htp_opnode & last_node = ops[n_ops - 1]; - - // Case 1: last_node is already MUL_MAT_ID_NX - if (last_node.opcode == HTP_OP_MUL_MAT_ID_NX) { - const uint32_t curr_n = (uint32_t) last_node.outputs.size(); - if (curr_n >= HTP_OP_MAX_OUTPUTS || curr_n + 2 >= HTP_OP_MAX_INPUTS) { - return false; - } - - const ggml_tensor * w0 = last_node.inputs[0]; - const ggml_tensor * x = last_node.inputs[curr_n]; - const ggml_tensor * ids = last_node.inputs[curr_n + 1]; - - if (x_in != x || ids_in != ids || w_in->type != w0->type || w_in->ne[0] != w0->ne[0] || w_in->ne[2] != w0->ne[2]) { - return false; - } - if (!last_node.fused.empty() && (mm_is_hmx_eligible(last_node.fused[0]) != mm_is_hmx_eligible(node.node))) { - return false; - } - - struct htp_mm_kernel_params kparams; - ggml_hexagon_precompute_fused_mmidnx_params(sess, w0, x, d_in, curr_n + 1, &kparams); - if (!is_supported_mul_mat_id_nx_kernel(w0, &kparams)) { - return false; - } - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip ID NX fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (!try_fuse_common(w_in, d_in)) { - return false; - } - - last_node.inputs[curr_n] = w_in; - last_node.inputs[curr_n + 1] = x; - last_node.inputs.push_back(ids); - last_node.outputs.push_back(d_in); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &kparams, sizeof(kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - memcpy(o.kernel_params, &kparams, sizeof(kparams)); - - for (uint32_t s = 0; s <= curr_n + 2; s++) { - o.src[s] = add_tensor(last_node.inputs[s]); - } - for (uint32_t s = curr_n + 3; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - for (uint32_t d = 0; d <= curr_n; d++) { - o.dst[d] = add_tensor(last_node.outputs[d]); - } - for (uint32_t d = curr_n + 1; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused MUL_MAT_ID_NX (N=%u, #%u)\n", sess->c_name(), curr_n + 1, n_ops - 1); - return true; - } - - // Case 2: last_node is single MUL_MAT_ID - if (last_node.opcode == HTP_OP_MUL_MAT_ID) { - if (!is_mergeable_mul_mat_id_pair(last_node.node, node.node)) { - return false; - } - - const ggml_tensor * w0 = last_node.src0(); - const ggml_tensor * x = last_node.src1(); - const ggml_tensor * ids = last_node.node->src[2]; - const ggml_tensor * w1 = node.src0(); - - struct htp_mm_kernel_params kparams; - ggml_hexagon_precompute_fused_mmidnx_params(sess, w0, x, node.dst(), 2, &kparams); - if (!is_supported_mul_mat_id_nx_kernel(w0, &kparams)) { - return false; - } - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s skip ID NX fusion: VTCM needed (%d) > budget (%zu)\n", - sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - if (!try_fuse_common(w1, node.dst())) { - return false; - } - - const ggml_tensor * dst_0 = last_node.dst(); - const ggml_tensor * dst_1 = node.dst(); - - last_node.opcode = HTP_OP_MUL_MAT_ID_NX; - last_node.name = "MUL_MAT_ID_NX"; - last_node.inputs.clear(); - last_node.inputs.push_back(w0); - last_node.inputs.push_back(w1); - last_node.inputs.push_back(x); - last_node.inputs.push_back(ids); - last_node.outputs.clear(); - last_node.outputs.push_back(dst_0); - last_node.outputs.push_back(dst_1); - last_node.fused.push_back(node.node); - memcpy(last_node.kernel_params, &kparams, sizeof(kparams)); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.opcode = HTP_OP_MUL_MAT_ID_NX; - memcpy(o.kernel_params, &kparams, sizeof(kparams)); - - o.src[0] = add_tensor(w0); - o.src[1] = add_tensor(w1); - o.src[2] = add_tensor(x); - o.src[3] = add_tensor(ids); - for (uint32_t s = 4; s < HTP_OP_MAX_INPUTS; s++) { - o.src[s] = 0xffff; - } - o.dst[0] = add_tensor(dst_0); - o.dst[1] = add_tensor(dst_1); - for (uint32_t d = 2; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused MUL_MAT_ID_NX (N=2, #%u)\n", sess->c_name(), n_ops - 1); - return true; - } - - return false; - } - - bool try_fuse_gdn_cpy(const htp_opnode & node) { - if (n_ops == 0 || node.opcode != HTP_OP_CPY) return false; - - htp_opnode & last_node = ops[n_ops - 1]; - if (last_node.opcode != HTP_OP_GATED_DELTA_NET) return false; - if (last_node.outputs.size() != 1) return false; - - const ggml_tensor * gdn_out = last_node.dst(); - const ggml_tensor * cpy_node = node.node; - const ggml_tensor * cpy_src = node.src0(); - const ggml_tensor * cpy_dst = node.dst(); - - if (!cpy_src || !cpy_dst || !cpy_dst->data) return false; - if (gdn_out->type != GGML_TYPE_F32 || cpy_src->type != GGML_TYPE_F32 || cpy_dst->type != GGML_TYPE_F32) return false; - if ((gdn_out->flags & GGML_TENSOR_FLAG_OUTPUT) || (cpy_node->flags & GGML_TENSOR_FLAG_OUTPUT)) return false; - - const ggml_tensor * v = last_node.node->src[2]; - if (!v) return false; - - const int64_t S_v = v->ne[0]; - const int64_t H = v->ne[1]; - const int64_t n_tokens = v->ne[2]; - const int64_t n_seqs = v->ne[3]; - const int64_t K = ggml_get_op_params_i32(last_node.node, 0); - const size_t tail_off = (size_t) S_v * H * n_tokens * n_seqs * sizeof(float); - - const int64_t D = S_v * S_v * H; - const int64_t n_written = std::min(n_tokens, K); - - if (cpy_src->op != GGML_OP_VIEW || (cpy_src->view_src != gdn_out && cpy_src->view_src->data != gdn_out->data) || - cpy_src->view_offs != tail_off || !ggml_is_contiguous(cpy_src)) { - return false; - } - - if (cpy_dst->ne[0] != D || cpy_dst->ne[1] != n_seqs || cpy_dst->nb[0] != sizeof(float)) { - return false; - } - if (n_seqs > 1 && cpy_dst->nb[1] != (size_t) D * sizeof(float)) { - return false; - } - if (n_written > 1) { - if (cpy_dst->ne[2] != n_written || cpy_dst->nb[2] != (size_t) D * n_seqs * sizeof(float)) { - return false; - } - } - - if (!try_fuse_common({cpy_dst})) { - return false; - } - - last_node.name += "+CPY"; - last_node.outputs.push_back(cpy_dst); - last_node.fused.push_back(node.node); - - htp_op_desc & o = h_ops[n_ops - 1]; - o.dst[1] = add_tensor(cpy_dst); - for (uint32_t d = 2; d < HTP_OP_MAX_OUTPUTS; d++) { - o.dst[d] = 0xffff; - } - - HEX_VERBOSE("ggml-hex: %s fused GATED_DELTA_NET+CPY (#%u)\n", sess->c_name(), n_ops - 1); - return true; - } - - bool try_fuse(const htp_opnode & node) { - if (!opt_opfusion) return false; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_ALLREDUCE_ADD) && try_fuse_allreduce_add(node)) return true; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_RMS_NORM_MUL) && try_fuse_rms_norm_mul(node)) return true; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_MUL_MAT_ADD) && try_fuse_mul_mat_add(node)) return true; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_MUL_MAT_NX) && try_fuse_mul_mat_nx(node)) return true; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_MUL_MAT_ID_NX) && try_fuse_mul_mat_id_nx(node)) return true; - if (ggml_hexagon_is_fusion_enabled(GGML_HEXAGON_FUSE_GDN_CPY) && try_fuse_gdn_cpy(node)) return true; - return false; - } -}; - -struct ggml_hexagon_registry { - ggml_hexagon_registry(ggml_backend_reg_t reg); - ~ggml_hexagon_registry(); - - ggml_backend_device devices[GGML_HEXAGON_MAX_SESSIONS]; -}; - -struct ggml_hexagon_opqueue { - // Shared buffer for storing batches - ggml_hexagon_shared_buffer *shm_buf; - size_t shm_blk_size; - size_t depth; - - using opvec = std::vector; - - std::vector op_cache; // per batch op cache - std::vector start_usec; // per batch start time - - ggml_hexagon_opqueue(ggml_hexagon_session *sess, size_t batch_size, size_t depth) : depth(depth) { - size_t n_bufs = HTP_OP_MAX_BUFS; - size_t n_ops = batch_size; - size_t n_tensors = n_ops * HTP_OP_MAX_OUTPUTS + n_ops * HTP_OP_MAX_INPUTS; - - size_t tr_size = 0; - if (opt_profile == 3) { - tr_size = (HTP_MAX_NTHREADS + 1) * opt_optrace * sizeof(htp_trace_desc); - } - - shm_blk_size = sizeof(htp_buf_desc) * n_bufs + - sizeof(htp_tensor) * n_tensors + - sizeof(htp_op_desc) * n_ops + - sizeof(htp_prof_desc) * n_ops + - tr_size; - - shm_buf = new ggml_hexagon_shared_buffer(sess, shm_blk_size * depth, true /* pinned */); - - op_cache.resize(depth); - start_usec.resize(depth, 0); - - if (opt_verbose) { - GGML_LOG_INFO("ggml-hex: %s allocated opqueue : batch-size %zu depth %zu shm-size %zu shm-block-size %zu\n", - sess->c_name(), batch_size, depth, shm_buf->size(), shm_blk_size); - } - } - - ~ggml_hexagon_opqueue() { - delete shm_buf; - } - - size_t shm_size() const { return shm_buf ? shm_buf->size() : 0; } - - // push new batch - bool push(htp_opbatch_req& req, dspqueue_buffer& dbuf, const ggml_hexagon_opbatch* op_batch, uint64_t seq) { - static_assert(sizeof(htp_opbatch_req) % 8 == 0, "sizeof(htp_opbatch_req) must be multiple of 8"); - static_assert(sizeof(htp_opbatch_rsp) % 8 == 0, "sizeof(htp_opbatch_rsp) must be multiple of 8"); - static_assert(sizeof(htp_buf_desc) % 8 == 0, "sizeof(htp_buf_desc) must be multiple of 8"); - static_assert(sizeof(htp_tensor) % 8 == 0, "sizeof(htp_tensor) must be multiple of 8"); - static_assert(sizeof(htp_op_desc) % 8 == 0, "sizeof(htp_op_desc) must be multiple of 8"); - static_assert(sizeof(htp_prof_desc) % 8 == 0, "sizeof(htp_prof_desc) must be multiple of 8"); - - if (seq - shm_buf->sess->batch_rsp_seq > depth) { return false; } - - const uint32_t slot = (uint32_t) ((seq - 1) % depth); - - req.seq = seq; - req.n_bufs = op_batch->n_bufs; - req.n_tensors = op_batch->n_tens; - req.n_ops = op_batch->n_ops; - - op_cache[slot] = op_batch->ops; - start_usec[slot] = ggml_time_us(); - - const size_t b_size = sizeof(htp_buf_desc) * req.n_bufs; - const size_t t_size = sizeof(htp_tensor) * req.n_tensors; - const size_t o_size = sizeof(htp_op_desc) * req.n_ops; - const size_t p_size = sizeof(htp_prof_desc) * req.n_ops; - - size_t tr_size = 0; - if (opt_profile == 3) { - req.n_traces = opt_optrace; - tr_size = (HTP_MAX_NTHREADS + 1) * req.n_traces * sizeof(htp_trace_desc); - } else { - req.n_traces = 0; - } - - dbuf.ptr = shm_buf->base() + ((size_t) slot * shm_blk_size); - dbuf.fd = shm_buf->fd(); - dbuf.flags = DSPQUEUE_BUFFER_FLAG_FLUSH_SENDER | DSPQUEUE_BUFFER_FLAG_INVALIDATE_RECIPIENT; - dbuf.offset = (uint8_t*) dbuf.ptr - (uint8_t*) shm_buf->base(); - dbuf.size = b_size + t_size + o_size + p_size + tr_size; - - GGML_ASSERT(dbuf.size <= shm_blk_size); - - uint8_t * m_ptr = (uint8_t*) dbuf.ptr; - uint8_t * b_ptr = m_ptr; m_ptr += b_size; - uint8_t * t_ptr = m_ptr; m_ptr += t_size; - uint8_t * o_ptr = m_ptr; - - memcpy(b_ptr, (void *) op_batch->h_bufs.data(), b_size); - memcpy(t_ptr, (void *) op_batch->h_tens.data(), t_size); - memcpy(o_ptr, (void *) op_batch->h_ops.data(), o_size); - - HEX_VERBOSE("ggml-hex: %s opqueue-push batch #%llu : n-bufs %u n-tensors %u n-ops %u vmem %zu : b-size %zu t-size %zu o-size %zu m-size %zu\n", - shm_buf->sess->c_name(), (unsigned long long) req.seq, req.n_bufs, req.n_tensors, req.n_ops, op_batch->b_vmem, - b_size, t_size, o_size, (size_t) dbuf.size); - - if (opt_verbose > 1) { - htp_buf_desc *b = (htp_buf_desc*) b_ptr; - for (unsigned int i=0; i < req.n_bufs; i++) { - GGML_LOG_DEBUG("ggml-hex: %s htp-buf #%u : fd %d base %p size %zu\n", shm_buf->sess->c_name(), i, - b[i].fd, (void *) b[i].base, (size_t) b[i].size); - } - htp_tensor *t = (htp_tensor*) t_ptr; - for (unsigned int i=0; i < req.n_tensors; i++) { - GGML_LOG_DEBUG("ggml-hex: %s htp-tensor #%u : bi %u offset %llu size %u : %zu:%zu:%zu:%zu\n", - shm_buf->sess->c_name(), i, t[i].bi, (unsigned long long) t[i].data, t[i].size, - (size_t) t[i].ne[0], (size_t) t[i].ne[1], (size_t) t[i].ne[2], (size_t) t[i].ne[3]); - } - } - - return true; - } - - void pop(htp_opbatch_rsp rsp, dspqueue_buffer dbuf) { - const uint32_t slot = (uint32_t) ((rsp.seq - 1) % depth); - - const size_t b_size = sizeof(htp_buf_desc) * rsp.n_bufs; - const size_t t_size = sizeof(htp_tensor) * rsp.n_tensors; - const size_t o_size = sizeof(htp_op_desc) * rsp.n_ops; - const size_t p_size = sizeof(htp_prof_desc) * rsp.n_ops; - - size_t tr_size = 0; - uint32_t n_traces = 0; - if (opt_profile == 3) { - n_traces = opt_optrace; - tr_size = (HTP_MAX_NTHREADS + 1) * n_traces * sizeof(htp_trace_desc); - } - - const size_t m_size = b_size + t_size + o_size + p_size + tr_size; - GGML_ASSERT(m_size <= shm_blk_size); - - HEX_VERBOSE("ggml-hex: %s opqueue-pop batch #%llu : n-bufs %u n-tensors %u n-ops %u : m-size %zu b-size %zu t-size %zu o-size %zu\n", - shm_buf->sess->c_name(), (unsigned long long) rsp.seq, rsp.n_bufs, rsp.n_tensors, rsp.n_ops, - (size_t) dbuf.size, b_size, t_size, o_size); - - uint8_t * m_ptr = (uint8_t*) dbuf.ptr; - uint8_t * p_ptr = m_ptr + (b_size + t_size + o_size); - - if (rsp.n_ops > 0) { - auto & ops = op_cache[slot]; - GGML_ASSERT(rsp.n_ops <= ops.size()); - - const htp_prof_desc * pd = (const htp_prof_desc *) p_ptr; - const htp_trace_desc * trace_events = nullptr; - if (opt_profile == 3) { - trace_events = (const htp_trace_desc *) (p_ptr + p_size); - } - - if (opt_profile) { - ggml_hexagon_dump_batch_prof(shm_buf->sess->name, rsp); - } - - for (uint32_t i = 0; i < rsp.n_ops; i++) { - if (opt_profile) { - ggml_hexagon_dump_op_prof(shm_buf->sess->name, ops[i], pd[i]); - } - } - - if (opt_profile) { - ggml_hexagon_dump_trace_events(shm_buf->sess->name, rsp, trace_events, n_traces); - } - } - } -}; - -void ggml_hexagon_session::flush_peers() { - auto vpeers = std::move(virt_peers); - virt_peers.clear(); - for (auto * peer : vpeers) { - peer->flush_sync(); - } - - auto ppeers = std::move(phys_peers); - phys_peers.clear(); - for (auto * peer : ppeers) { - peer->flush_async(); - } - - for (auto & sub : this->mdev.sessions) { - sub->flush_peers(); - } -} - -void ggml_hexagon_session::flush_async() { - flush_peers(); - flush_batch(); -} - -void ggml_hexagon_session::flush_pending(bool all) { - for (auto & sub : this->mdev.sessions) { - sub->flush_pending(all); - if (sub->last_error > HTP_STATUS_OK) { - this->last_error = sub->last_error.load(); - } - } - - while (this->batch_rsp_seq < this->batch_req_seq) { - struct htp_opbatch_rsp rsp; - uint32_t rsp_size; - uint32_t flags; - - struct dspqueue_buffer dbuf; - uint32_t n_dbufs; - - // Read response packet from queue - const uint32_t timeo = opt_oppoll ? 0 : DSPQUEUE_TIMEOUT; - - int err = dspqueue_read(this->queue, &flags, 1, &n_dbufs, &dbuf, sizeof(rsp), &rsp_size, (uint8_t *) &rsp, timeo); - if (err == AEE_EEXPIRED || err == AEE_EWOULDBLOCK) { - continue; - } - - if (err != 0) { - GGML_ABORT("ggml-hex: dspqueue_read failed: 0x%08x\n", (unsigned) err); - } - - // Basic sanity checks - if (rsp_size != sizeof(rsp) || n_dbufs != 1) { - GGML_ABORT("ggml-hex: %s dspcall : bad response : size %u dspbufs %u\n", this->c_name(), rsp_size, n_dbufs); - } - - if (rsp.status > HTP_STATUS_OK) { - GGML_LOG_ERROR("ggml-hex: %s dspcall : dsp-rsp %s\n", this->c_name(), status_to_str(rsp.status)); - this->last_error = rsp.status; - for (auto & sub : this->mdev.sessions) { - sub->last_error = rsp.status; - } - } - - op_queue->pop(rsp, dbuf); - - GGML_ASSERT(rsp.seq == this->batch_rsp_seq + 1); - this->batch_rsp_seq = rsp.seq; - - if (!all) break; - } -} - -void ggml_hexagon_session::flush_sync(bool all) { - flush_async(); - flush_pending(all); -} - -void ggml_hexagon_session::start_batch() { - if (this->mdev.count > 1) { - enqueue_mdev_group(); - } -} - -void ggml_hexagon_session::flush_batch(size_t min_ops) { - if (op_batch->n_ops < min_ops) { return; } - - op_batch->sort_buffers(); - - htp_opbatch_req req {}; - dspqueue_buffer dbuf{}; - - const uint64_t seq = ++this->batch_req_seq; - - op_batch->update_mdev_group(this->mdev.idx); - - if (!op_queue->push(req, dbuf, op_batch, seq)) { - flush_pending(false); - op_queue->push(req, dbuf, op_batch, seq); - } - - for (auto & sub : this->mdev.sessions) { - htp_opbatch_req sub_req {}; - dspqueue_buffer sub_dbuf{}; - - sub->batch_req_seq = seq; - op_batch->update_mdev_group(sub->mdev.idx); - - if (!sub->op_queue->push(sub_req, sub_dbuf, op_batch, seq)) { - sub->flush_pending(false); - sub->op_queue->push(sub_req, sub_dbuf, op_batch, seq); - } - - HEX_VERBOSE("ggml-hex: %s queue-opbatch: %p size %u\n", sub->c_name(), sub_dbuf.ptr, sub_dbuf.size); - - int err = dspqueue_write(sub->queue, 0, 1, &sub_dbuf, sizeof(sub_req), (const uint8_t*) &sub_req, DSPQUEUE_TIMEOUT); - if (err != 0) { - GGML_ABORT("ggml-hex: %s dspqueue_write failed: 0x%08x\n", sub->c_name(), (unsigned) err); - } - } - - HEX_VERBOSE("ggml-hex: %s queue-opbatch: %p size %u\n", this->c_name(), dbuf.ptr, dbuf.size); - - int err = dspqueue_write(this->queue, 0, 1, &dbuf, sizeof(req), (const uint8_t*) &req, DSPQUEUE_TIMEOUT); - if (err != 0) { - GGML_ABORT("ggml-hex: %s dspqueue_write failed: 0x%08x\n", this->c_name(), (unsigned) err); - } - - op_batch->reset(); -} - -void ggml_hexagon_session::enqueue_op(const htp_opnode & node) { - auto clone_tensor_buffer = [this](const ggml_tensor * t) { - auto sbuf = this->mmap_tensor(t); - if (!sbuf) return; - if (sbuf->sess != this) { - this->clone_buffer(sbuf); - } - for (auto & sub : this->mdev.sessions) { - sub->clone_buffer(sbuf); - } - }; - - for (auto t : node.get_inputs()) { - clone_tensor_buffer(t); - } - for (auto t : node.get_outputs()) { - clone_tensor_buffer(t); - } - - if (opt_opfusion && op_batch->try_fuse(node)) { - return; - } - - if (!op_batch->fit_op(node)) { - flush_async(); - } - - if (op_batch->empty()) { - start_batch(); - } - - if (!op_batch->fit_op(node)) { - GGML_ABORT("ggml-hex: %s op does not fit into empty batch (vmem/tensor/buffer limit exceeded)\n", - c_name()); - } - - op_batch->add_op(node); -} - -void ggml_hexagon_session::enqueue_mdev_group() { - htp_opnode group_node(HTP_OP_MDEV_GROUP); - - uint8_t * fence_slot = this->mdev_fence_slot; - - static ggml_hexagon_tensor_extra fence_extra { {}, 0, GGML_HEXAGON_TENSOR_FENCE }; - ggml_tensor dummy_t {}; - dummy_t.buffer = &this->fence_buf->backend_buffer; - dummy_t.extra = &fence_extra; - dummy_t.data = (void *) fence_slot; - dummy_t.type = GGML_TYPE_I8; - dummy_t.ne[0] = HTP_FENCE_SLOT_SIZE; - dummy_t.ne[1] = (int64_t) this->mdev.count; - dummy_t.ne[2] = 1; - dummy_t.ne[3] = 1; - dummy_t.nb[0] = 1; - dummy_t.nb[1] = HTP_FENCE_SLOT_SIZE; - dummy_t.nb[2] = dummy_t.nb[1] * dummy_t.ne[1]; - dummy_t.nb[3] = dummy_t.nb[2]; - dummy_t.op = GGML_OP_NONE; - dummy_t.op_params[0] = (int32_t) this->mdev.idx; - - ggml_tensor * node = group_node.add_dummy(dummy_t); - node->src[0] = node; - group_node.init(node); - group_node.outputs.clear(); - group_node.name = "MDEV_GROUP"; - - for (auto & sub : this->mdev.sessions) { - sub->clone_buffer(this->fence_buf); - } - - op_batch->add_op(group_node); -} - -void ggml_hexagon_session::enqueue_cpy(const ggml_tensor * src, ggml_tensor * dst, const ggml_tensor * sync_tensor, uint32_t fence_seq) { - const bool with_fence = sync_tensor != nullptr; - htp_opnode cpy_node(with_fence ? HTP_OP_CPY_FENCE : HTP_OP_CPY); - - ggml_tensor* node = cpy_node.add_dummy(*dst); - node->op = GGML_OP_CPY; - node->src[0] = const_cast(src); - node->src[1] = with_fence ? cpy_node.add_dummy(*sync_tensor) : nullptr; - if (with_fence) { - node->op_params[0] = (int32_t) fence_seq; - } - - cpy_node.init(node); - if (with_fence) { - cpy_node.name = "CPY+FENCE"; - } - const bool ok = ggml_hexagon_precompute_cpy_params(this, node, (struct htp_copy_kernel_params *) cpy_node.kernel_params); - const auto * kparams = (const struct htp_copy_kernel_params *) cpy_node.kernel_params; - if (ok && !with_fence && kparams->total_elems == 0) { - return; - } - this->enqueue_op(cpy_node); -} - -void ggml_hexagon_session::enqueue_fence(const ggml_tensor * sync_tensor, uint32_t fence_seq, bool wait) { - htp_opnode sync_node(HTP_OP_FENCE); - - ggml_tensor* node = sync_node.add_dummy(*sync_tensor); - node->op = GGML_OP_NONE; - node->src[0] = node; - node->op_params[0] = (int32_t) fence_seq; - node->op_params[1] = wait ? 0 : 1; - - sync_node.init(node); - sync_node.name = wait ? "FENCE_WAIT" : "FENCE_SIGNAL"; - this->enqueue_op(sync_node); -} - -static bool ggml_hexagon_precompute_allreduce_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * dst, - uint32_t rank, - uint32_t n_ranks, - bool has_add, - bool is_row_bcast, - bool is_shard_ok, - struct htp_allreduce_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->rank = (int32_t) rank; - kparams->n_ranks = (int32_t) n_ranks; - kparams->is_row_bcast = (has_add && is_row_bcast) ? 1 : 0; - - const uint32_t nelem = (uint32_t) ggml_nelements(dst); - const uint32_t elem_size = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); - const bool is_contiguous = ggml_is_contiguous(dst); - - const uint32_t ne0 = (uint32_t) dst->ne[0]; - const uint32_t ne1 = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); - kparams->ne0 = (int32_t) ne0; - kparams->ne1 = (int32_t) ne1; - - const bool use_1d = is_contiguous && !(has_add && is_row_bcast && ne1 > 1); - - if (has_add) { - // sharded reduce-scatter for contiguous in-place add - if (opt_ar_scatter && is_shard_ok && use_1d && !is_row_bcast) { - const uint32_t rank_chunk_elems = hex_round_up((nelem + n_ranks - 1) / n_ranks, 128); - const uint32_t rank_elem_start = (std::min)(rank * rank_chunk_elems, nelem); - const uint32_t rank_elem_end = (std::min)(rank_elem_start + rank_chunk_elems, nelem); - kparams->n_dsts = (int32_t) n_ranks; - kparams->rank_elem_start = (int32_t) rank_elem_start; - kparams->rank_nelem = (int32_t) (rank_elem_end - rank_elem_start); - } else if (use_1d) { - kparams->n_dsts = 1; - kparams->rank_elem_start = 0; - kparams->rank_nelem = (int32_t) nelem; - } else { - kparams->n_dsts = 1; - kparams->rank_elem_start = 0; - kparams->rank_nelem = (int32_t) ne1; - } - } else { - kparams->n_dsts = (int32_t) n_ranks; - if (use_1d) { - const uint32_t rank_chunk_elems = hex_round_up((nelem + n_ranks - 1) / n_ranks, 128); - const uint32_t rank_elem_start = (std::min)(rank * rank_chunk_elems, nelem); - const uint32_t rank_elem_end = (std::min)(rank_elem_start + rank_chunk_elems, nelem); - const uint32_t rank_nelem = rank_elem_end - rank_elem_start; - kparams->rank_elem_start = (int32_t) rank_elem_start; - kparams->rank_nelem = (int32_t) rank_nelem; - } else { - const uint32_t rank_chunk_rows = (ne1 + n_ranks - 1) / n_ranks; - const uint32_t rank_r0 = (std::min)(rank * rank_chunk_rows, ne1); - const uint32_t rank_r1 = (std::min)(rank_r0 + rank_chunk_rows, ne1); - const uint32_t rank_nrows = rank_r1 - rank_r0; - kparams->rank_elem_start = (int32_t) rank_r0; - kparams->rank_nelem = (int32_t) rank_nrows; - } - } - - kparams->mode = (kparams->n_dsts > 1) ? HTP_ALLREDUCE_SHARDED_FANOUT : HTP_ALLREDUCE_FULL; - - if (use_1d) { - const uint32_t rank_nelem = (uint32_t) kparams->rank_nelem; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, (std::max)(1u, rank_nelem / 128)); - kparams->n_threads = n_threads; - const size_t n_vtcm_buffers = htp_allreduce_vtcm_buffer_count(n_ranks, n_threads, has_add, is_row_bcast); - - uint32_t block_elems = 65536; - if (block_elems > rank_nelem / n_threads && rank_nelem / n_threads > 128) { - block_elems = hex_round_up(rank_nelem / (n_threads * 2), 128); - } - block_elems = (std::max)(128u, block_elems); - - kparams->block_elems = block_elems; - kparams->vtcm_size_per_thread = 2 * block_elems * elem_size; - kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; - - while ((size_t) kparams->vtcm_size > sess->vtcm_size && block_elems > 128) { - const size_t max_bytes_per_buf = sess->vtcm_size / (n_vtcm_buffers * 2); - block_elems = (uint32_t) hex_align_down((size_t) (max_bytes_per_buf / elem_size), 128); - if (block_elems < 128) break; - kparams->block_elems = block_elems; - kparams->vtcm_size_per_thread = 2 * block_elems * elem_size; - kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; - } - - if (sess->vtcm_size < (size_t) kparams->vtcm_size || block_elems < 128) { - HEX_VERBOSE("ggml-hex: %s allreduce 1D solver failed to fit VTCM (%d > %zu)\n", - sess->c_name(), kparams->vtcm_size, sess->vtcm_size); - return false; - } - - kparams->elems_per_thread = hex_round_up((rank_nelem + n_threads - 1) / n_threads, block_elems); - kparams->kernel_type = HTP_ALLREDUCE_KERNEL_DMA_1D; - return true; - } else { - const uint32_t rank_nrows = (uint32_t) kparams->rank_nelem; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, (std::max)(1u, rank_nrows)); - kparams->n_threads = n_threads; - const size_t n_vtcm_buffers = htp_allreduce_vtcm_buffer_count(n_ranks, n_threads, has_add, is_row_bcast); - - const uint32_t row_bytes = ne0 * elem_size; - const uint32_t row_size_aligned = (uint32_t) hex_align_up(row_bytes, 128); - kparams->row_size_aligned = row_size_aligned; - - const uint32_t nrows_per_thread = (rank_nrows + n_threads - 1) / n_threads; - uint32_t block_rows = (std::min)(128u, nrows_per_thread); - block_rows = (std::max)(1u, block_rows); - kparams->block_elems = block_rows; - - kparams->vtcm_size_per_thread = 2 * (block_rows * row_size_aligned); - kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; - - while ((size_t) kparams->vtcm_size > sess->vtcm_size && block_rows > 1) { - const size_t max_rows_per_buf = sess->vtcm_size / (n_vtcm_buffers * 2 * row_size_aligned); - block_rows = (std::max)(1u, (uint32_t) max_rows_per_buf); - kparams->block_elems = block_rows; - kparams->vtcm_size_per_thread = 2 * (block_rows * row_size_aligned); - kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; - if (max_rows_per_buf == 0) break; - } - - if (sess->vtcm_size < (size_t) kparams->vtcm_size || block_rows < 1) { - HEX_VERBOSE("ggml-hex: %s allreduce 2D solver failed to fit VTCM (%d > %zu)\n", - sess->c_name(), kparams->vtcm_size, sess->vtcm_size); - return false; - } - - kparams->elems_per_thread = nrows_per_thread; - kparams->kernel_type = HTP_ALLREDUCE_KERNEL_DMA_2D; - return true; - } -} - -void ggml_hexagon_session::enqueue_allreduce( - const ggml_tensor * dst, - const std::vector & src_tensors, - const std::vector & sync_tensors, - uint32_t rank, - uint32_t n_ranks, - uint32_t fence_seq_entry, - uint32_t fence_seq_exit -) { - htp_opnode ar_node(HTP_OP_ALLREDUCE); - - ggml_tensor* node = ar_node.add_dummy(*dst); - node->op = GGML_OP_NONE; - node->op_params[0] = (int32_t) fence_seq_entry; - node->op_params[1] = (int32_t) fence_seq_exit; - - ar_node.init(node); - - ar_node.inputs.clear(); - for (size_t i = 0; i < src_tensors.size(); i++) { - ar_node.inputs.push_back(src_tensors[i]); - } - for (size_t i = 0; i < sync_tensors.size(); i++) { - ar_node.inputs.push_back(ar_node.add_dummy(*sync_tensors[i])); - } - - ar_node.outputs.clear(); - for (size_t i = 0; i < src_tensors.size(); i++) { - ar_node.outputs.push_back(src_tensors[i]); - } - - ggml_hexagon_precompute_allreduce_params( - this, dst, rank, n_ranks, false, false, /*is_shard_ok=*/ false, - (struct htp_allreduce_kernel_params *) ar_node.kernel_params); - - ar_node.name = "ALLREDUCE"; - this->enqueue_op(ar_node); -} - -ggml_hexagon_shared_buffer * ggml_hexagon_session::mmap_tensor(const ggml_tensor * t) { - if (!t) return nullptr; - - auto sbuf = static_cast(t->buffer->context); - if (!sbuf->mapped) { - const bool is_weight = ggml_backend_buffer_get_usage(t->buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS; - const bool extended = opt_dma64 && is_weight; - sbuf->mmap(extended); - } - return sbuf; -} - -bool ggml_hexagon_session::clone_buffer(const ggml_hexagon_shared_buffer * sbuf) -{ - GGML_ASSERT(sbuf && sbuf->mem); - if (sbuf->sess == this) return true; - - auto mem = sbuf->mem; - int fd = mem->fd; - - GGML_ASSERT(fd >= 0); - - if (this->cloned_buffers.find(fd) != this->cloned_buffers.end()) return true; - - GGML_ASSERT(sbuf->mapped); - - HEX_VERBOSE("ggml-hex: %s clone-buffer: %s base %p size %zu fd %d\n", this->name.c_str(), - sbuf->c_name(), sbuf->base(), sbuf->size(), fd); - - auto clone = std::make_unique(this, *sbuf); - try { - clone->mmap(sbuf->extended); - } catch (const std::exception & exc) { - GGML_LOG_ERROR("ggml-hex: %s lazy mapping of buffer context failed: %s\n", this->c_name(), exc.what()); - return false; - } - - this->cloned_buffers[fd] = std::move(clone); - mem->mapped_clones.insert(this); - return true; -} - -void ggml_hexagon_session::release_buffer(const ggml_hexagon_shared_buffer * sbuf) { - GGML_ASSERT(sbuf && sbuf->mem); - - auto mem = sbuf->mem; - int fd = mem->fd; - - GGML_ASSERT(fd >= 0); - - auto it = this->cloned_buffers.find(fd); - if (it != this->cloned_buffers.end()) { - auto clone = std::move(it->second); - this->cloned_buffers.erase(it); - } - mem->mapped_clones.erase(this); -} - -void ggml_hexagon_session::unclone_buffer(const ggml_hexagon_shared_buffer * sbuf) { - GGML_ASSERT(sbuf && sbuf->mem); - - auto mem = sbuf->mem; - std::vector sessions(mem->mapped_clones.begin(), mem->mapped_clones.end()); - - for (auto * sess : sessions) { - sess->release_buffer(sbuf); - } -} - -static size_t ggml_hexagon_measure_max_vmem(ggml_hexagon_session *sess) { - // Allocate a bunch pinned buffers till failure. - // This is kind of expensive but handy for figuring out exactly how much we can mmap on a specific device. - // Typically we're going to allocate all/most of these buffers anyway for the model weights. - - std::vector sbufs; - - const size_t MiB = 1024 * 1024; - const size_t GiB = MiB * 1024; - - size_t vmem = 0; - size_t step = 256u * MiB; - - try { - sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; - sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; - sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; - - while (1) { - sbufs.push_back(new ggml_hexagon_shared_buffer(sess, step, true)); - vmem += step; - } - } catch (...) { } - - for (auto b : sbufs) { delete b; } - - return vmem - step; // backoff to account for overhead from internal mappings -} - -void ggml_hexagon_session::allocate(const ggml_hexagon_device_config & config) noexcept(false) { - int phys_idx = config.physical_idx; - int virt_idx = config.virtual_idx; - - this->valid_session = false; - this->valid_handle = false; - this->valid_queue = false; - this->valid_iface = false; - - this->name = config.name; - this->phys_idx = phys_idx; - this->virt_idx = virt_idx; - this->domain_id = config.domain_id; - this->session_id = 0; - this->batch_req_seq = 0; - this->batch_rsp_seq = 0; - this->last_error = HTP_STATUS_OK; - - GGML_LOG_DEBUG("ggml-hex: %s allocating new session : domain %u phys-idx %u virt-idx %u\n", this->name.c_str(), this->domain_id, phys_idx, virt_idx); - - if (config.domain_id < 0 || config.domain_name.empty()) { - GGML_LOG_ERROR("ggml-hex: %s: invalid physical CDSP core %d\n", config.name.c_str(), config.physical_idx); - throw std::runtime_error("ggml-hex: invalid physical CDSP core"); - } - - const std::string & dom_name = config.domain_name; - - // Create new session if virtual_idx > 0 - if (virt_idx > 0) { - struct remote_rpc_reserve_new_session n {}; - n.domain_name_len = dom_name.size(); - n.domain_name = const_cast(dom_name.c_str()); - n.session_name = const_cast(this->name.c_str()); - n.session_name_len = this->name.size(); - n.session_id = virt_idx; - - int err = remote_session_control(FASTRPC_RESERVE_NEW_SESSION, (void *) &n, sizeof(n)); - if (err != AEE_SUCCESS) { - GGML_LOG_ERROR("ggml-hex: %s failed to reserve new session (physical %d, virtual %d) : error 0x%x\n", - this->c_name(), phys_idx, virt_idx, err); - throw std::runtime_error("ggml-hex: remote_session_control(new-sess) failed (see log for details)"); - } - - // Save the IDs - this->session_id = n.session_id; - this->domain_id = n.effective_domain_id; - this->valid_session = true; - } else { - struct remote_rpc_effective_domain_id eff {}; - eff.domain_name = const_cast(dom_name.c_str()); - eff.domain_name_len = dom_name.size(); - eff.session_id = 0; - - int err = remote_session_control(FASTRPC_GET_EFFECTIVE_DOMAIN_ID, (void *) &eff, sizeof(eff)); - if (err == AEE_SUCCESS) { - this->domain_id = eff.effective_domain_id; - } else { - GGML_LOG_DEBUG("ggml-hex: %s FASTRPC_GET_EFFECTIVE_DOMAIN_ID returned 0x%x, using domain_id %d\n", - this->name.c_str(), err, this->domain_id); - } - } - - // Enable unsigned modules - { - struct remote_rpc_control_unsigned_module u; - u.domain = this->domain_id; - u.enable = 1; - int err = remote_session_control(DSPRPC_CONTROL_UNSIGNED_MODULE, (void *) &u, sizeof(u)); - if (err != AEE_SUCCESS) { - GGML_LOG_ERROR("ggml-hex: %s failed to enable unsigned PD : error 0x%x\n", this->c_name(), err); - throw std::runtime_error("ggml-hex: remote_session_control(unsign) failed (see log for details)"); - } - } - - char session_uri[256]; - { - char htp_uri[256]; - snprintf(htp_uri, sizeof(htp_uri), "file:///libggml-htp-v%u.so?htp_iface_skel_handle_invoke&_modver=1.0", opt_arch); - - struct remote_rpc_get_uri u = {}; - u.session_id = this->session_id; - u.domain_name = const_cast(dom_name.c_str()); - u.domain_name_len = dom_name.size(); - u.module_uri = const_cast(htp_uri); - u.module_uri_len = strlen(htp_uri); - u.uri = session_uri; - u.uri_len = sizeof(session_uri); - - int err = remote_session_control(FASTRPC_GET_URI, (void *) &u, sizeof(u)); - if (err != AEE_SUCCESS) { - snprintf(session_uri, sizeof(session_uri), "%s&_dom=%s&_session=%u", - htp_uri, dom_name.c_str(), this->session_id); - - GGML_LOG_WARN("ggml-hex: %s failed to get URI (physical %d, virtual %d) : error 0x%x. Falling back to single session URI: %s\n", - this->c_name(), phys_idx, virt_idx, err, session_uri); - } - } - - // Open session - int err = htp_iface_open(session_uri, &this->handle); - if (err != AEE_SUCCESS) { - GGML_LOG_ERROR("ggml-hex: %s failed to open session : uri %s error 0x%x\n", this->c_name(), session_uri, err); - throw std::runtime_error("ggml-hex: failed to open session (see log for details)"); - } - - this->valid_handle = true; - - // Query HW info and resolve session options - { - unsigned int hw_n_threads = 0; - unsigned int hw_n_hvx = 0; - unsigned int hw_n_hmx = 0; - unsigned long long hw_vtcm_size = 0; - int hw_err = htp_iface_hwinfo(this->handle, &hw_n_threads, &hw_n_hvx, &hw_n_hmx, &hw_vtcm_size); - if (hw_err == 0) { - const uint32_t max_n_threads = (std::min)((uint32_t) HTP_MAX_NTHREADS, (uint32_t) hw_n_threads); - this->n_threads = opt_nhvx > 0 ? (uint32_t) (std::min)(opt_nhvx, (size_t) max_n_threads) : max_n_threads; - this->n_hvx = this->n_threads; - this->n_hmx = (opt_nhmx != 0) ? (uint32_t)hw_n_hmx : 0; - this->vtcm_size = (uint64_t)hw_vtcm_size; - GGML_LOG_INFO("ggml-hex: %s hwinfo: threads %u, hvx %u, hmx %u, vtcm %llu MB\n", - this->c_name(), this->n_threads, this->n_hvx, this->n_hmx, - (unsigned long long)(this->vtcm_size / (1024 * 1024))); - } else { - GGML_LOG_WARN("ggml-hex: %s failed to query hwinfo (0x%x), using defaults\n", this->c_name(), hw_err); - const uint32_t default_n_threads = (std::min)(8u, (uint32_t) HTP_MAX_NTHREADS); - this->n_threads = opt_nhvx > 0 ? (uint32_t) (std::min)(opt_nhvx, (size_t) HTP_MAX_NTHREADS) : default_n_threads; - this->n_hvx = this->n_threads; - this->n_hmx = (opt_nhmx != 0) ? 1 : 0; - this->vtcm_size = 8 * 1024 * 1024; - } - } - - // Enable FastRPC QoS mode - { - struct remote_rpc_control_latency l; - l.enable = 1; - - int err = remote_handle64_control(this->handle, DSPRPC_CONTROL_LATENCY, (void *) &l, sizeof(l)); - if (err != 0) { - GGML_LOG_WARN("ggml-hex: failed to enable fastrpc QOS mode: 0x%08x\n", (unsigned) err); - } - } - - GGML_LOG_INFO("ggml-hex: %s new session : session-id %d domain-id %d uri %s handle 0x%lx\n", this->c_name(), - this->session_id, this->domain_id, session_uri, (unsigned long) this->handle); - - const size_t req_q_size = (sizeof(htp_opbatch_req) * opt_opqueue * 2) + 1024; - const size_t rsp_q_size = (sizeof(htp_opbatch_rsp) * opt_opqueue * 2) + 1024; - - // Now let's setup the DSP queue - err = dspqueue_create(this->domain_id, - 0, // Flags - req_q_size, // Request queue size (in bytes) - rsp_q_size, // Response queue size (in bytes) - nullptr, // Read packet callback (we handle reads explicitly) - nullptr, // Error callback (we handle errors during reads) - (void *) this, // Callback context - &queue); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: %s dspqueue_create failed: 0x%08x\n", this->name.c_str(), (unsigned) err); - throw std::runtime_error("ggml-hex: failed to create dspqueue (see log for details)"); - } - - this->valid_queue = true; - - // Export queue for use on the DSP - err = dspqueue_export(queue, &this->queue_id); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: dspqueue_export failed: 0x%08x\n", (unsigned) err); - throw std::runtime_error("ggml-hex: dspqueue export failed (see log for details)"); - } - - if (opt_etm) { - err = htp_iface_etm(this->handle, 1); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: failed to enable ETM tracing: 0x%08x\n", (unsigned) err); - } - } - - // Allocate buffers and state for op batching - this->op_queue = new ggml_hexagon_opqueue(this, opt_opbatch, opt_opqueue); - - this->fence_buf = new ggml_hexagon_fence_buffer(this, &dev_ctx->fence_buffer_type, 64 * 1024); - if (this->mdev.count > 1) { - this->mdev_fence_slot = this->alloc_fence(this->mdev.count); - } - - if (!opt_vmem) { - opt_vmem = ggml_hexagon_measure_max_vmem(this); - GGML_LOG_INFO("ggml-hex: %s measured max vmem %zu\n", this->c_name(), opt_vmem); - } - const size_t shm_size = this->op_queue->shm_size(); - this->max_vmem = (opt_vmem > shm_size) ? (opt_vmem - shm_size) : opt_vmem; - - this->op_batch = new ggml_hexagon_opbatch(this, opt_opbatch, this->max_vmem); - - // Start dspqueue/opbatch processing - err = htp_iface_start(this->handle, this->session_id, this->queue_id, this->n_threads, opt_nhmx, this->max_vmem, (uint32_t) opt_power_mode); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: %s failed to start session: 0x%08x\n", this->c_name(), (unsigned) err); - throw std::runtime_error("ggml-hex: iface start failed (see log for details)"); - } - this->valid_iface = true; - GGML_LOG_INFO("ggml-hex: %s power mode: %s\n", this->c_name(), htp_power_mode_to_str(opt_power_mode)); - - if (opt_profile) { - htp_iface_pmu_conf pmu_conf{}; - std::copy(opt_pmu_evt.begin(), opt_pmu_evt.end(), pmu_conf.events); - - err = htp_iface_profiler(this->handle, opt_profile, &pmu_conf); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: failed to enable profiling: 0x%08x\n", (unsigned) err); - } - } -} - -void ggml_hexagon_session::release() noexcept(true) { - GGML_LOG_INFO("ggml-hex: releasing session: %s\n", this->name.c_str()); - - this->mdev.sessions.clear(); - - int err; - - if (this->valid_iface) { - // Stop dspqueue/opbatch processing - err = htp_iface_stop(this->handle); - if (err != 0) { - GGML_ABORT("ggml-hex: htp_iface_stop failed: 0x%08x\n", (unsigned) err); - } - } - - delete this->op_batch; - delete this->op_queue; - for (auto & it : this->cpy_fence_slots) { - free_fence((void *) it.second, 1); - } - this->cpy_fence_slots.clear(); - - if (this->fence_buf) { - unclone_buffer(this->fence_buf); - delete this->fence_buf; - this->fence_buf = nullptr; - } - while (!this->cloned_buffers.empty()) { - release_buffer(this->cloned_buffers.begin()->second.get()); - } - - if (opt_etm) { - err = htp_iface_etm(this->handle, 0); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: warn : failed to disable ETM tracing: 0x%08x\n", (unsigned) err); - } - } - - if (opt_profile) { - htp_iface_pmu_conf pmu_conf{}; - err = htp_iface_profiler(this->handle, 0, &pmu_conf); - if (err != 0) { - GGML_LOG_ERROR("ggml-hex: warn : failed to disable profiling: 0x%08x\n", (unsigned) err); - } - } - - if (this->valid_queue) { - err = dspqueue_close(queue); - if (err != 0) { - GGML_ABORT("ggml-hex: dspqueue_close failed: 0x%08x\n", (unsigned) err); - } - } - - if (this->valid_handle) { - htp_iface_close(this->handle); - } -} - -ggml_hexagon_session::ggml_hexagon_session(const ggml_hexagon_device_config & config, ggml_backend_dev_t dev, uint32_t mdev_idx, uint32_t mdev_count) noexcept(false) { - this->dev = dev; - this->dev_ctx = static_cast(dev->context); - this->mdev.idx = mdev_idx; - this->mdev.count = mdev_count > 0 ? mdev_count : (uint32_t) (1 + config.mdev_group.size()); - op_batch = nullptr; - op_queue = nullptr; - fence_buf = nullptr; - fence_seq = ((uintptr_t)this) & 0xFFFF; - - try { - allocate(config); - if (this->mdev.idx == 0 && !config.mdev_group.empty()) { - for (size_t i = 0; i < config.mdev_group.size(); i++) { - this->mdev.sessions.push_back(std::make_unique( - config.mdev_group[i], this->dev, (uint32_t) (i + 1), this->mdev.count)); - } - } - } catch (const std::exception & exc) { - release(); - throw; - } -} - -ggml_hexagon_session::~ggml_hexagon_session() noexcept(true) { - release(); -} - -// ** backend interface - -static bool ggml_hexagon_flash_attn_is_hmx_eligible( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * q, - const struct ggml_tensor * k, - const struct ggml_tensor * v, - const struct ggml_tensor * sinks -) { - if (sess->n_hmx == 0) { - return false; - } - - if (opt_fa_select < 2) { - return false; - } - - if ((k->type != GGML_TYPE_F16 && k->type != GGML_TYPE_Q8_0) || - (v->type != GGML_TYPE_F16 && v->type != GGML_TYPE_Q8_0)) { - return false; - } - - const uint32_t DK = q->ne[0]; - const uint32_t DV = v->ne[0]; - - // Head dims that are not multiples of 64 are handled by internally padding to - // DK_pad/DV_pad = round_up(.,64) and zero-filling the tail lanes. - if (DK % 8 != 0 || DV % 8 != 0) { - return false; - } - - GGML_UNUSED(sinks); - - // Explicit force mode - if (opt_fa_select > 2) { - return true; - } - - const uint32_t M = q->ne[1]; - - // Prefill or batched decode - if (M > 1) { - return true; - } - - // Compute-bound head dim - if (DK >= 256) { - return true; - } - - const uint32_t n_head = q->ne[2]; - const uint32_t n_kv_heads = k->ne[2]; - const uint32_t G = n_kv_heads > 0 ? n_head / n_kv_heads : 1; - const uint32_t S = k->ne[1]; - - // Tile alignment for 32-row HMX tiles - const bool is_tile_aligned = (G > 0 && (32 % G == 0)); - if (!is_tile_aligned) { - if (sess->n_threads >= 6) { - return false; - } - return S >= 1024; - } - - // Context depth crossover - uint32_t s_cross = 512; - if (DK <= 64) { - s_cross = (sess->n_threads >= 8) ? 2048 : ((sess->n_threads >= 6) ? 768 : 512); - } else { - s_cross = (sess->n_threads >= 8) ? 1024 : 512; - } - - return S >= s_cross; -} - -static bool ggml_hexagon_precompute_flash_attn_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_fa_kernel_params * kparams -) { - if (opt_fa_select < 1) { - return false; - } - - memset(kparams, 0, sizeof(*kparams)); - - const struct ggml_tensor * q = op->src[0]; - const struct ggml_tensor * k = op->src[1]; - const struct ggml_tensor * v = op->src[2]; - const struct ggml_tensor * mask = op->src[3]; - - const uint32_t neq0 = q->ne[0]; // head_dim (DK) - const uint32_t neq1 = q->ne[1]; // n_tokens - const uint32_t neq2 = q->ne[2]; // n_heads - - const uint32_t nek1 = k->ne[1]; // kv_len - - const uint32_t nev0 = v->ne[0]; // head_dim (DV) - - const uint32_t DK = neq0; - const uint32_t DV = nev0; - - const uint32_t n_kv_heads = k->ne[2]; - const uint32_t G = neq2 / n_kv_heads; - - float scale = 1.0f; - float max_bias = 0.0f; - float logit_softcap = 0.0f; - memcpy(&scale, &op->op_params[0], sizeof(float)); - memcpy(&max_bias, &op->op_params[1], sizeof(float)); - memcpy(&logit_softcap, &op->op_params[2], sizeof(float)); - - if (logit_softcap != 0.0f) { - scale /= logit_softcap; - } - - kparams->scale = scale; - kparams->max_bias = max_bias; - kparams->logit_softcap = logit_softcap; - - kparams->head_split = (opt_fa_head_split != 0) ? 1 : 0; - kparams->flags = 0; - kparams->G = G; - - const uint32_t n_head = q->ne[2]; - kparams->n_head_log2 = 1u << (uint32_t) std::floor(std::log2(n_head)); - kparams->m0 = std::pow(2.0f, -(max_bias) / kparams->n_head_log2); - kparams->m1 = std::pow(2.0f, -(max_bias / 2.0f) / kparams->n_head_log2); - - // Check HMX eligibility - const struct ggml_tensor * sinks = op->src[4]; - if (ggml_hexagon_flash_attn_is_hmx_eligible(sess, q, k, v, sinks)) { - // HMX tiles head_dim in units of 64; when DK/DV are not 64-aligned the kernel - // operates on padded dims with zero-filled tail lanes. VTCM budget and chunk-size - // are sized for the padded tiles. - const uint32_t DK_pad = hex_round_up(DK, 64); - const uint32_t DV_pad = hex_round_up(DV, 64); - size_t Br = 0, Bc = 0; - int ret = hmx_fa_find_chunk_size(&Br, &Bc, G, DK_pad, DV_pad, neq1, nek1, sess->vtcm_size, sess->n_threads, (q->type == GGML_TYPE_F32), sinks != nullptr, n_head); - if (ret == 0) { - kparams->kernel_type = HTP_FA_KERNEL_HMX; - if (logit_softcap == 0.0f) { - kparams->scale = scale * (float) M_LOG2E; - kparams->logit_softcap = 0.0f; - } else { - kparams->scale = scale; - kparams->logit_softcap = logit_softcap * (float) M_LOG2E; - } - kparams->Br = Br; - kparams->Bc = Bc; - kparams->n_kv_blocks = (nek1 + Bc - 1) / Bc; - kparams->n_threads = (kparams->n_kv_blocks >= 3 && sess->n_threads >= 2) ? sess->n_threads : 1; - - kparams->u.hmx.g_br = hex_align_up(G * Br, 32); - kparams->u.hmx.pipeline = (kparams->n_kv_blocks >= 3 && sess->n_threads >= 2) ? 1 : 0; - kparams->vtcm_size = hmx_fa_compute_vtcm_usage(G, DK_pad, DV_pad, Br, Bc, kparams->n_threads, kparams->u.hmx.pipeline != 0, (q->type == GGML_TYPE_F32), sinks != nullptr, n_head); - - const size_t row_vec_bytes = hex_align_up(Bc * sizeof(uint16_t), 256); - kparams->u.hmx.row_buf_stride = row_vec_bytes / 128; // HVX vector is 128 bytes - - const size_t m_line_bytes = hex_align_up(Bc * sizeof(uint16_t), 128); - kparams->u.hmx.mask_buf_row_stride = m_line_bytes / sizeof(uint16_t); - kparams->u.hmx.mask_broadcast = (mask != nullptr && mask->ne[2] == 1) ? 1 : 0; - kparams->u.hmx.div_G = init_fastdiv_values(G); - if (mask) { - kparams->src3_div2 = init_fastdiv_values(mask->ne[2]); - kparams->src3_div3 = init_fastdiv_values(mask->ne[3]); - } - - kparams->qrows = 0; - kparams->qrows_per_thread = 0; - return true; - } - } - - // Fallback to HVX - kparams->kernel_type = HTP_FA_KERNEL_HVX; - kparams->Br = 1; - kparams->Bc = 64; // FLASH_ATTN_BLOCK_SIZE - kparams->n_kv_blocks = (k->ne[1] + 64 - 1) / 64; - kparams->n_threads = sess->n_threads; - - const size_t size_q_row_padded = hex_round_up(q->ne[0] * ((q->type == GGML_TYPE_F32) ? 4 : 2), 128); - const size_t size_k_row_padded = hex_round_up(k->ne[0] * 2, 128); - const size_t size_v_row_padded = hex_round_up(v->ne[0] * 2, 128); - - kparams->vtcm_size = hvx_fa_compute_vtcm_usage(DK, DV, (q->type == GGML_TYPE_F32), mask != nullptr, sinks != nullptr, n_head, sess->n_threads); - - kparams->u.hvx.size_q_row_padded = size_q_row_padded; - kparams->u.hvx.size_k_row_padded = size_k_row_padded; - kparams->u.hvx.size_v_row_padded = size_v_row_padded; - kparams->u.hvx.src0_div21 = init_fastdiv_values(q->ne[2] * q->ne[1]); - kparams->u.hvx.src0_div1 = init_fastdiv_values(q->ne[1]); - kparams->broadcast_rk2 = init_fastdiv_values(q->ne[2]/k->ne[2]); - kparams->broadcast_rk3 = init_fastdiv_values(q->ne[3]/k->ne[3]); - kparams->broadcast_rv2 = init_fastdiv_values(q->ne[2]/v->ne[2]); - kparams->broadcast_rv3 = init_fastdiv_values(q->ne[3]/v->ne[3]); - if (mask) { - kparams->src3_div2 = init_fastdiv_values(mask->ne[2]); - kparams->src3_div3 = init_fastdiv_values(mask->ne[3]); - } - - kparams->qrows = q->ne[1] * q->ne[2] * q->ne[3]; - kparams->qrows_per_thread = (kparams->qrows + sess->n_threads - 1) / sess->n_threads; - - return true; -} - -static bool ggml_hexagon_supported_flash_attn_ext(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * src3 = op->src[3]; - const struct ggml_tensor * src4 = op->src[4]; - const struct ggml_tensor * dst = op; - - // Check for F16/Q8_0 support - if ((src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_F32) || - (src1->type != GGML_TYPE_F16 && src1->type != GGML_TYPE_Q8_0) || - (src2->type != GGML_TYPE_F16 && src2->type != GGML_TYPE_Q8_0)) { - return false; - } - - if (src3 && src3->type != GGML_TYPE_F16) { // mask - return false; - } - - if (src4 && src4->type != GGML_TYPE_F32) { // sinks - return false; - } - - // For now we support F32 or F16 output as htp backend often converts output on the fly if needed, - // but the op implementation writes to F16 or F32. - // Let's assume dst can be F32 or F16. - if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16) { - return false; - } - - if (dst->ne[3] != 1) { - return false; - } - - struct htp_fa_kernel_params kparams; - if (!ggml_hexagon_precompute_flash_attn_params(sess, op, &kparams)) { - return false; - } - - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: skip flash_attn_ext because VTCM needed (%d) > budget (%zu)\n", - kparams.vtcm_size, sess->vtcm_size); - return false; - } - - return true; -} - -static bool ggml_hexagon_supported_gated_delta_net(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - if (opt_gdn_select < 1) { - return false; - } - - const struct ggml_tensor * q = op->src[0]; - const struct ggml_tensor * k = op->src[1]; - const struct ggml_tensor * v = op->src[2]; - const struct ggml_tensor * g = op->src[3]; - const struct ggml_tensor * beta = op->src[4]; - const struct ggml_tensor * state = op->src[5]; - const struct ggml_tensor * dst = op; - - if (q->type != GGML_TYPE_F32 || k->type != GGML_TYPE_F32 || v->type != GGML_TYPE_F32 || - g->type != GGML_TYPE_F32 || beta->type != GGML_TYPE_F32 || state->type != GGML_TYPE_F32 || - dst->type != GGML_TYPE_F32) { - return false; - } - - if (!ggml_is_contiguous_rows(q) || !ggml_is_contiguous_rows(k) || !ggml_is_contiguous_rows(v) || - !ggml_is_contiguous(g) || !ggml_is_contiguous(beta) || !ggml_is_contiguous(state) || - !ggml_is_contiguous(dst)) { - return false; - } - - const int64_t S_v = v->ne[0]; - const int64_t H = v->ne[1]; - const int64_t n_tokens = v->ne[2]; - const int64_t n_seqs = v->ne[3]; - const int64_t K = ggml_get_op_params_i32(op, 0); - - if (S_v <= 0 || S_v > 128 || H <= 0 || n_tokens <= 0 || n_seqs <= 0) { - return false; - } - if (q->ne[0] != S_v || k->ne[0] != S_v || q->ne[1] <= 0 || k->ne[1] <= 0 || - q->ne[2] != n_tokens || k->ne[2] != n_tokens || q->ne[3] <= 0 || k->ne[3] <= 0 || - (n_seqs % q->ne[3]) != 0 || (n_seqs % k->ne[3]) != 0) { - return false; - } - if ((g->ne[0] != 1 && g->ne[0] != S_v) || beta->ne[0] != 1) { - return false; - } - // state holds s0 only [S_v, S_v, H, n_seqs]; K is op param 0. - if (ggml_nelements(state) != S_v * S_v * H * n_seqs) { - return false; - } - if (dst->ne[0] != S_v * H || dst->ne[1] != n_tokens * n_seqs + S_v * n_seqs * K) { - return false; - } - - const uint32_t total_rows = (uint32_t) (H * n_seqs); - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, total_rows); - - const bool can_use_hmx = (opt_gdn_select >= 2) && - (sess->n_hmx > 0) && - (S_v % 64 == 0) && - (n_tokens >= HTP_GDN_MIN_TOKENS) && - (g->ne[0] == 1) && - (K == 1); - - if (can_use_hmx) { - struct htp_gdn_hmx_vtcm_layout layout; - uint32_t n_heads_batch = 0; - if (!htp_gdn_hmx_solve_layout(&layout, (uint32_t) S_v, HTP_GDN_CHUNK_SIZE, total_rows, sess->vtcm_size, n_threads, true, &n_heads_batch)) { - return false; - } - } else { - struct htp_gdn_vtcm_layout layout; - htp_gdn_vtcm_layout_build(&layout, (uint32_t) S_v, n_threads); - if (layout.total_bytes > sess->vtcm_size) { - return false; - } - } - - return true; -} - -static bool ggml_hexagon_matmul_is_hmx_eligible( - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - int ne01_padded, - bool is_matmul_id, - bool is_batched -) { - if (src1->type != GGML_TYPE_F32 && (src1->type != GGML_TYPE_F16 || is_matmul_id)) { - return false; - } - - const int ne00 = src0->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int wtype = src0->type; - - // HMX weight tiles accept non-32-aligned N for non-matmul_id. - if (ne01_padded % 32 != 0 && is_matmul_id) { - return false; - } - - // HMX supports F16, F32, and repack quantized types. - if (!ggml_hexagon_is_hmx_weight_type((ggml_type) wtype)) { - return false; - } - - // HMX paths require K aligned to 32. - if (ne00 % 32 != 0) { - return false; - } - - // Quantized HMX kernels only handle flat 2D matmul (or matmul_id wrapping flat 2D matmuls). - if (!is_matmul_id && is_batched && wtype != GGML_TYPE_F16) { - return false; - } - - // HMX assumes contiguous row-major layout. - if (src0->nb[0] > src0->nb[1] || src1->nb[0] > src1->nb[1]) { - return false; - } - - // M alignment: Use HMX when M > HTP_MM_HMX_MIN_NROWS. - // For MUL_MAT_ID, src1 shape is [K, n_expert_used, n_tokens, 1], so n_tokens is ne12. - const int m = is_matmul_id ? ne12 : ne11; - if (m <= HTP_MM_HMX_MIN_NROWS) { - return false; - } - - return true; - - GGML_UNUSED(dst); -} - -static bool ggml_hexagon_precompute_hmx_mm_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * act, - const struct ggml_tensor * dst, - int wtype, - int ne00_padded, - int ne01_padded, - int ne02, - int ne11, - int ne12, - int ne11_padded, - bool is_matmul_id, - bool is_batched, - size_t src2_size, - size_t vtcm_budget, - struct htp_mm_kernel_params * kparams -) { - const int aligned_tile_size = htp_mm_get_weight_aligned_tile_size(wtype); - const int n_threads = (int)sess->n_threads; - const int ne10 = act->ne[0]; - - int m_for_solver = ne11; - int m_for_solver_padded = ne11_padded; - // matmul_id partitions by expert; regular matmul partitions M rows (ne11) across devices - if (!is_matmul_id && sess->mdev.count > 1 && ((uint32_t) ne11 >= sess->mdev.count)) { - // when dst is null, padded dims are used for estimate which are 128-byte aligned - const bool dst_row_split = dst ? ggml_hexagon_can_row_partition(dst) : true; - const bool act_row_split = ggml_hexagon_can_row_partition(act); - if (dst_row_split && act_row_split) { - m_for_solver = (ne11 + (int) sess->mdev.count - 1) / (int) sess->mdev.count; - m_for_solver_padded = hex_round_up(std::max(m_for_solver, 32), 32); - } - } - const bool pipeline = is_matmul_id ? false : htp_mm_hmx_pipeline(m_for_solver); - - const bool is_batched_val = is_matmul_id ? false : is_batched; - const int group_size = (ne02 > 0 ? ne12 / ne02 : 1); - - size_t m_chunk = 0; - size_t n_chunk = 0; - size_t vtcm_size = 0; - bool use_grouped = false; - int act_threads_selected = 0; - - if (is_batched_val && wtype == GGML_TYPE_F16 && group_size > 1) { - // Try grouped path first - if (htp_mm_hmx_solve_batched_params(wtype, ne00_padded, ne01_padded, m_for_solver, group_size, n_threads, pipeline, src2_size, vtcm_budget, &m_chunk, &n_chunk, &act_threads_selected, &vtcm_size)) { - use_grouped = true; - } - } - - if (!use_grouped) { - // Fallback to simple 2D path (group_size = 1) - int m_id_rows = 0; - if (dst && is_matmul_id) { - const int n_experts = ne02 > 0 ? ne02 : 1; - const size_t total_expert_rows = (size_t) dst->ne[1] * dst->ne[2]; - int m_per_expert = (int) ((total_expert_rows + n_experts - 1) / n_experts); - if (sess->mdev.count > 1 && ggml_hexagon_can_row_partition(dst)) { - m_per_expert = (m_per_expert + (int) sess->mdev.count - 1) / (int) sess->mdev.count; - } - m_id_rows = hex_round_up(std::max(m_per_expert, 32), 32); - } - const uint32_t cost_m = is_matmul_id ? (uint32_t) m_id_rows : (uint32_t) m_for_solver; - if (!htp_mm_hmx_solve_2d_params(wtype, ne00_padded, m_id_rows, ne01_padded, m_for_solver_padded, cost_m, n_threads, pipeline, is_matmul_id, aligned_tile_size, src2_size, vtcm_budget, &m_chunk, &n_chunk, &act_threads_selected, &vtcm_size)) { - return false; - } - } - - kparams->n_hmx = 1; - kparams->pipeline = pipeline ? 1 : 0; - kparams->m_chunk = m_chunk; - kparams->n_chunk = n_chunk; - kparams->n_threads = n_threads; - kparams->n_act_threads = act_threads_selected; - kparams->tile_size = htp_mm_get_weight_tile_size(wtype); - kparams->aligned_tile_size = aligned_tile_size; - kparams->act_row_size = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); - kparams->vtcm_size = vtcm_size; - kparams->vtcm_src0_size = 0; - kparams->div_n_act_threads = init_fastdiv_values(act_threads_selected); - kparams->div_ne00_padded = init_fastdiv_values(ne00_padded); - kparams->vtcm_act_size = 0; - kparams->vtcm_bias_size = (int32_t) src2_size; - kparams->vtcm_dst_size = 0; - - if (is_batched && !is_matmul_id) { - kparams->kernel_type = HTP_MM_KERNEL_HMX_F16_BATCHED; - } else { - kparams->kernel_type = HTP_MM_KERNEL_HMX_2D; - } - return true; - - GGML_UNUSED(src0); -} - -static void ggml_hexagon_precompute_hvx_mm_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - int wtype, - int ne02, - int ne03, - int ne10, - int ne11, - int ne12, - int ne13, - bool is_matmul_id, - const size_t src2_row_size, - size_t vtcm_budget, - struct htp_mm_kernel_params * kparams -) { - if (opt_mm_select < 1) { - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } - - kparams->n_hmx = 0; - kparams->n_threads = sess->n_threads; - - GGML_UNUSED(ne02); - GGML_UNUSED(ne03); - - const bool is_quant = (wtype != GGML_TYPE_F16 && wtype != GGML_TYPE_F32); - const int src1_nrows = ne11 * ne12 * ne13; - - if (is_quant) { - // Quantized HVX - kparams->tile_size = htp_mm_get_weight_tile_size(wtype); - kparams->aligned_tile_size = htp_mm_get_weight_aligned_tile_size(wtype); - - const bool k_align = (ne10 % 32 == 0); - - if (is_matmul_id) { - kparams->kernel_type = (src1_nrows < (int) sess->n_threads) ? HTP_MM_KERNEL_HVX_QUANT_BLOCK : HTP_MM_KERNEL_HVX_QUANT_ROW; - kparams->act_row_size = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); - - struct htp_mm_hvx_vtcm_layout L; - uint32_t max_prefetch = (src1_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; - uint32_t best_n_prefetch = 2; - for (uint32_t d = max_prefetch; d >= 2; d /= 2) { - htp_mm_hvx_vtcm_layout_build( - &L, kparams->kernel_type, wtype, ne10, src1_nrows, sess->n_threads, - 0, src0->nb[1], kparams->act_row_size, 0, d, true, false - ); - if (L.total_bytes <= vtcm_budget) { - best_n_prefetch = d; - break; - } - } - if (L.total_bytes > vtcm_budget) { - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } - kparams->n_prefetch = best_n_prefetch; - kparams->vtcm_size = L.total_bytes; - kparams->vtcm_src0_size = L.src0_bytes; - kparams->vtcm_act_size = L.act_bytes; - kparams->vtcm_bias_size = 0; - kparams->vtcm_dst_size = L.dst_bytes; - goto done_quant; - } else { - bool try_tiled = (k_align && opt_mm_select >= 1); - if (try_tiled) { - kparams->act_row_size = htp_mm_weight_has_offset(wtype) - ? htp_mm_q8_1_tiled_row_size(ne10) - : htp_mm_q8_0_tiled_row_size(ne10); - if (src1_nrows < (int) sess->n_threads) { - kparams->kernel_type = HTP_MM_KERNEL_HVX_QUANT_BLOCK; - } else { - kparams->kernel_type = HTP_MM_KERNEL_HVX_QUANT_ROW; - } - - struct htp_mm_hvx_vtcm_layout L; - uint32_t max_prefetch = (src1_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; - uint32_t best_n_prefetch = 2; - for (uint32_t d = max_prefetch; d >= 2; d /= 2) { - htp_mm_hvx_vtcm_layout_build( - &L, kparams->kernel_type, wtype, ne10, src1_nrows, sess->n_threads, - dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, d, false, false - ); - if (L.total_bytes <= vtcm_budget) { - best_n_prefetch = d; - break; - } - } - - uint32_t m_chunk = 0; - if (htp_mm_hvx_solve_vtcm_params( - kparams->kernel_type, wtype, ne10, src1_nrows, sess->n_threads, - dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, best_n_prefetch, vtcm_budget, - &L, &m_chunk)) { - kparams->n_prefetch = best_n_prefetch; - kparams->m_chunk = (m_chunk < (uint32_t) src1_nrows) ? m_chunk : 0; - kparams->vtcm_size = L.total_bytes; - kparams->vtcm_src0_size = L.src0_bytes; - kparams->vtcm_act_size = L.act_bytes; - kparams->vtcm_bias_size = L.bias_bytes; - kparams->vtcm_dst_size = L.dst_bytes; - goto done_quant; - } - } - - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } - - done_quant:; - } else if (wtype == GGML_TYPE_F16) { - // F16 HVX - struct htp_mm_hvx_vtcm_layout L; - uint32_t m_chunk = 0; - if (htp_mm_hvx_solve_vtcm_params( - HTP_MM_KERNEL_HVX_F16_F16_VTCM, wtype, ne10, src1_nrows, sess->n_threads, - dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, 16, vtcm_budget, - &L, &m_chunk)) { - kparams->kernel_type = HTP_MM_KERNEL_HVX_F16_F16_VTCM; - kparams->m_chunk = (m_chunk < (uint32_t) src1_nrows) ? m_chunk : 0; - kparams->act_row_size = hex_round_up(ne10 * 2, 128); - kparams->vtcm_size = L.total_bytes; - kparams->vtcm_src0_size = L.src0_bytes; - kparams->vtcm_act_size = L.act_bytes; - kparams->vtcm_bias_size = L.bias_bytes; - kparams->vtcm_dst_size = L.dst_bytes; - kparams->n_prefetch = 16; - return; - } - - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } else { - // F32 HVX - struct htp_mm_hvx_vtcm_layout L; - uint32_t m_chunk = 0; - if (htp_mm_hvx_solve_vtcm_params( - HTP_MM_KERNEL_HVX_F32_F32_VTCM, wtype, ne10, src1_nrows, sess->n_threads, - dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, 16, vtcm_budget, - &L, &m_chunk)) { - kparams->kernel_type = HTP_MM_KERNEL_HVX_F32_F32_VTCM; - kparams->m_chunk = (m_chunk < (uint32_t) src1_nrows) ? m_chunk : 0; - kparams->act_row_size = hex_round_up(ne10 * 4, 128); - kparams->vtcm_size = L.total_bytes; - kparams->vtcm_src0_size = L.src0_bytes; - kparams->vtcm_act_size = L.act_bytes; - kparams->vtcm_bias_size = L.bias_bytes; - kparams->vtcm_dst_size = L.dst_bytes; - kparams->n_prefetch = 16; - return; - } - - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } -} - -static void ggml_hexagon_precompute_matmul_params_impl( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - const size_t src2_row_size, - const size_t src2_size, - struct htp_mm_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; - - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int ne13 = src1->ne[3]; - - const int wtype = src0->type; - const bool is_repack = ggml_hexagon_is_repack_type((ggml_type) wtype); - const int ne00_padded = is_repack ? hex_round_up(ne00, 32) : ne00; - const int ne01_padded = is_repack ? hex_round_up(ne01, 32) : ne01; - const int ne11_padded = hex_round_up(ne11, 32); - // VTCM has to hold whole 32-row weight tiles, so size for the rounded-up N - // even when the tensor itself is ragged. - const int ne01_tiled = hex_round_up(ne01_padded, 32); - - const bool is_matmul_id = (dst->op == GGML_OP_MUL_MAT_ID); - const bool is_batched = (ne02 * ne03 > 1 || ne12 * ne13 > 1); - - const size_t vtcm_budget = sess->vtcm_size; - - // Check HMX eligibility and try precomputing HMX parameters - bool hmx_enabled = (sess->n_hmx > 0) && (opt_mm_select >= 2); - if (hmx_enabled && ggml_hexagon_matmul_is_hmx_eligible(src0, src1, dst, ne01_padded, is_matmul_id, is_batched)) { - if (ggml_hexagon_precompute_hmx_mm_params(sess, src0, src1, dst, wtype, ne00_padded, ne01_tiled, ne02, ne11, ne12, ne11_padded, is_matmul_id, is_batched, src2_size, vtcm_budget, kparams)) { - goto finalize; - } - } - - // Fallback to HVX parameter computation - ggml_hexagon_precompute_hvx_mm_params(sess, src0, src1, dst, wtype, ne02, ne03, ne10, ne11, ne12, ne13, is_matmul_id, src2_row_size, vtcm_budget, kparams); - -finalize: - kparams->div_ne12_ne1 = init_fastdiv_values(ne12 * ne11); - kparams->div_ne1 = init_fastdiv_values(ne11); - kparams->div_r2 = init_fastdiv_values(ne02 > 0 ? ne12 / ne02 : 1); - kparams->div_r3 = init_fastdiv_values(ne03 > 0 ? ne13 / ne03 : 1); - kparams->div_ne12 = init_fastdiv_values(ne12); -} - -// The rows of dims 1..3 can be walked with one stride (size-1 dims skipped); returns that stride -static bool ggml_hexagon_rows_stride(const int64_t * ne, const size_t * nb, size_t * stride) { - size_t s = 0, next = 0; - for (int i = 1; i < GGML_MAX_DIMS; i++) { - if (ne[i] == 1) continue; - if (s == 0) { s = nb[i]; next = s * ne[i]; continue; } - if (nb[i] != next) return false; - next *= ne[i]; - } - *stride = s ? s : nb[1]; - return true; -} - -// A 2D weight applied to a batched activation whose rows are evenly strided is the same matmul over ne11 * ne12 * ne13 rows -static bool ggml_hexagon_matmul_can_collapse(const struct ggml_tensor * src0, const struct ggml_tensor * src1, const struct ggml_tensor * dst) { - size_t s1, sd; - return (dst->op == GGML_OP_MUL_MAT || dst->op == GGML_OP_ADD) && - src0->ne[2] == 1 && src0->ne[3] == 1 && src1->ne[2] * src1->ne[3] > 1 && - src1->nb[0] == ggml_type_size(src1->type) && ggml_hexagon_rows_stride(src1->ne, src1->nb, &s1) && - dst->nb[0] == ggml_type_size(dst->type) && ggml_hexagon_rows_stride(dst->ne, dst->nb, &sd); -} - -static bool ggml_hexagon_matmul_add_can_collapse( - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * src2, - const struct ggml_tensor * dst -) { - if (!ggml_hexagon_matmul_can_collapse(src0, src1, dst)) { - return false; - } - if (!src2) { - return true; - } - const int64_t src2_nrows = src2->ne[1] * src2->ne[2] * src2->ne[3]; - if (src2_nrows == 1) { - return true; - } - size_t s2; - return src2->nb[0] == ggml_type_size(src2->type) && - src2->ne[0] == dst->ne[0] && - src2->ne[1] == dst->ne[1] && - src2->ne[2] == dst->ne[2] && - src2->ne[3] == dst->ne[3] && - ggml_hexagon_rows_stride(src2->ne, src2->nb, &s2); -} - -static ggml_tensor ggml_hexagon_tensor_collapse_rows(const struct ggml_tensor * t) { - size_t stride = 0; - ggml_hexagon_rows_stride(t->ne, t->nb, &stride); - ggml_tensor c = *t; - c.ne[1] = t->ne[1] * t->ne[2] * t->ne[3]; - c.ne[2] = 1; - c.ne[3] = 1; - c.nb[1] = stride; - c.nb[2] = c.nb[1] * c.ne[1]; - c.nb[3] = c.nb[2]; - return c; -} - -static void ggml_hexagon_precompute_matmul_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_mm_kernel_params * kparams -) { - if (ggml_hexagon_matmul_can_collapse(src0, src1, dst)) { - const ggml_tensor src1_collapsed = ggml_hexagon_tensor_collapse_rows(src1); - const ggml_tensor dst_collapsed = ggml_hexagon_tensor_collapse_rows(dst); - ggml_hexagon_precompute_matmul_params_impl(sess, src0, &src1_collapsed, &dst_collapsed, 0, 0, kparams); - kparams->collapse = 1; - return; - } - ggml_hexagon_precompute_matmul_params_impl(sess, src0, src1, dst, 0, 0, kparams); -} - -static void ggml_hexagon_precompute_fused_matmul_add_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * src2, - const struct ggml_tensor * dst, - struct htp_mm_kernel_params * kparams -) { - if (ggml_hexagon_matmul_add_can_collapse(src0, src1, src2, dst)) { - const ggml_tensor src1_collapsed = ggml_hexagon_tensor_collapse_rows(src1); - const ggml_tensor dst_collapsed = ggml_hexagon_tensor_collapse_rows(dst); - const ggml_tensor src2_collapsed = (src2 && (src2->ne[1] * src2->ne[2] * src2->ne[3] > 1)) - ? ggml_hexagon_tensor_collapse_rows(src2) - : (src2 ? *src2 : ggml_tensor{}); - const struct ggml_tensor * p_src2 = src2 ? &src2_collapsed : nullptr; - const size_t src2_size = p_src2 ? hex_round_up(ggml_nbytes(p_src2), 128) : 0; - ggml_hexagon_precompute_matmul_params_impl(sess, src0, &src1_collapsed, &dst_collapsed, p_src2 ? p_src2->nb[1] : 0, src2_size, kparams); - kparams->collapse = 1; - return; - } - const size_t src2_size = src2 ? hex_round_up(ggml_nbytes(src2), 128) : 0; - ggml_hexagon_precompute_matmul_params_impl(sess, src0, src1, dst, src2 ? src2->nb[1] : 0, src2_size, kparams); -} - -static bool ggml_hexagon_precompute_binary_params( - const struct ggml_hexagon_session * sess, - uint32_t op, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_binary_kernel_params * kparams, - const struct ggml_tensor * src2 -) { - memset(kparams, 0, sizeof(*kparams)); - - const size_t elem_size = ggml_type_size(src0->type); - const size_t src0_row_size = src0->ne[0] * elem_size; - const size_t src1_row_size = src1->ne[0] * elem_size; - const size_t dst_row_size = dst->ne[0] * elem_size; - - const size_t src0_row_size_aligned = hex_round_up(src0_row_size, 128); - const size_t src1_row_size_aligned = hex_round_up(src1_row_size, 128); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, 128); - - if (!htp_binary_strides_safe(src0, src1, dst, elem_size)) { - return false; - } - - const bool is_add_id = op == HTP_OP_ADD_ID; - const bool is_scalar = !is_add_id && src1->ne[0] == 1; - const bool is_row_bcast = !is_add_id && !is_scalar && - src1->ne[0] == src0->ne[0] && - (src0->ne[1] > 1 || src0->ne[2] > 1 || src0->ne[3] > 1) && - src1->ne[1] == 1 && src1->ne[2] == 1 && src1->ne[3] == 1; - const bool is_same_shape = !is_add_id && !is_scalar && - src1->ne[0] == src0->ne[0] && - src1->ne[1] == src0->ne[1] && - (src1->ne[2] == src0->ne[2] || src1->ne[2] == 1) && - (src1->ne[3] == src0->ne[3] || src1->ne[3] == 1); - const bool is_complex = !is_add_id && !is_scalar && !is_same_shape && !is_row_bcast && (src1->ne[0] == src0->ne[0]); - const bool is_contig = ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && ggml_is_contiguous(dst); - const bool is_scalar_broadcast = !is_add_id && (ggml_nelements(src1) == 1); - - if (!is_add_id && is_contig && (ggml_are_same_shape(src0, src1) || is_scalar_broadcast)) { - const uint32_t total_elems = (uint32_t) ggml_nelements(src0); - const uint32_t n_threads = sess->n_threads; - const uint32_t max_chunk_elems = 32768 / elem_size; - const uint32_t min_chunk_elems = 256; - const uint32_t target_chunk_elems = hex_round_up((total_elems + (2 * n_threads) - 1) / (2 * n_threads), 32); - const uint32_t chunk_size = (std::min)(max_chunk_elems, (std::max)(target_chunk_elems, min_chunk_elems)); - const uint32_t chunk_bytes = hex_round_up(chunk_size * elem_size, 128); - - kparams->kernel_type = HTP_BINARY_KERNEL_CHUNKED; - kparams->n_threads = n_threads; - kparams->rows_per_buffer = 1; - kparams->src0_row_size_aligned = src0_row_size_aligned; - kparams->src1_row_size_aligned = is_scalar_broadcast ? 0 : src1_row_size_aligned; - kparams->dst_row_size_aligned = dst_row_size_aligned; - kparams->src1_size = 0; - kparams->chunk_size = chunk_size; - kparams->chunk_bytes = chunk_bytes; - kparams->is_scalar = is_scalar_broadcast ? 1 : 0; - - struct htp_binary_vtcm_layout L; - htp_binary_vtcm_layout_build(&L, kparams, sess->vtcm_size); - if (L.total_bytes == 0 || L.total_bytes > sess->vtcm_size) { - return false; - } - - kparams->vtcm_size = L.total_bytes; - return true; - } - - enum htp_binary_kernel_type kernel_type; - size_t src1_size = 0; - size_t src2_size = 0; - - if (is_add_id) { - GGML_ASSERT(src2 != nullptr); - kernel_type = HTP_BINARY_KERNEL_ADD_ID; - src1_size = hex_round_up(src1->ne[1] * src1_row_size_aligned, 128); - src2_size = hex_round_up(ggml_nelements(src2) * sizeof(int32_t), 128); - if (src1_size + src2_size > sess->vtcm_size) { - return false; - } - } else if (is_row_bcast) { - kernel_type = HTP_BINARY_KERNEL_ROW_BCAST; - src1_size = src1_row_size_aligned; - } else if (is_scalar) { - src1_size = hex_round_up(ggml_nelements(src1) * elem_size, 128); - if (src1_size > sess->vtcm_size) { - return false; - } - kernel_type = HTP_BINARY_KERNEL_SCALAR; - kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; - } else if (is_same_shape) { - kernel_type = HTP_BINARY_KERNEL_SAME_SHAPE; - } else if (is_complex) { - src1_size = hex_round_up(ggml_nelements(src1) * elem_size + 128, 128); - if (src1_size > sess->vtcm_size) { - return false; - } - kernel_type = HTP_BINARY_KERNEL_COMPLEX; - kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; - } else { - src1_size = hex_round_up(ggml_nelements(src1) * elem_size + 128, 128); - if (src1_size > sess->vtcm_size) { - return false; - } - kernel_type = HTP_BINARY_KERNEL_REPEAT; - kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; - } - - kparams->kernel_type = kernel_type; - kparams->n_threads = sess->n_threads; - kparams->src0_row_size_aligned = src0_row_size_aligned; - kparams->src1_row_size_aligned = src1_row_size_aligned; - kparams->dst_row_size_aligned = dst_row_size_aligned; - kparams->src1_size = src1_size; - kparams->src2_size = src2_size; - - const bool src0_contig_dim1 = (src0->nb[2] == src0->ne[1] * src0->nb[1]); - const bool src1_contig_dim1 = (src1->nb[2] == src1->ne[1] * src1->nb[1]); - const bool dst_contig_dim1 = (dst->nb[2] == src0->ne[1] * dst->nb[1]); - - const bool src0_contig_dim2 = (src0->nb[3] == src0->ne[2] * src0->nb[2]); - const bool src1_contig_dim2 = (src1->nb[3] == src1->ne[2] * src1->nb[2]); - const bool dst_contig_dim2 = (dst->nb[3] == src0->ne[2] * dst->nb[2]); - - bool split_at_ne01 = false; - if (src0->ne[2] > 1) { - if (kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) { - split_at_ne01 = (src1->ne[2] != src0->ne[2]) || !src0_contig_dim1 || !src1_contig_dim1 || !dst_contig_dim1; - } else if (kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { - split_at_ne01 = !src0_contig_dim1 || !dst_contig_dim1; - } else { - split_at_ne01 = true; - } - } - kparams->split_at_ne01 = split_at_ne01 ? 1 : 0; - - bool split_at_ne02 = false; - if (src0->ne[3] > 1) { - if (kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) { - split_at_ne02 = (src1->ne[3] != src0->ne[3]) || !src0_contig_dim2 || !src1_contig_dim2 || !dst_contig_dim2; - } else if (kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { - split_at_ne02 = !src0_contig_dim2 || !dst_contig_dim2; - } else { - split_at_ne02 = true; - } - } - kparams->split_at_ne02 = split_at_ne02 ? 1 : 0; - - struct htp_binary_vtcm_layout L; - htp_binary_vtcm_layout_build(&L, kparams, sess->vtcm_size); - if (L.rows_per_buffer == 0 || L.total_bytes > sess->vtcm_size) { - if (!is_add_id && is_contig && (ggml_are_same_shape(src0, src1) || is_scalar_broadcast)) { - const uint32_t total_elems = (uint32_t) ggml_nelements(src0); - const uint32_t n_threads = sess->n_threads; - const uint32_t max_chunk_elems = 32768 / elem_size; - const uint32_t min_chunk_elems = 256; - const uint32_t target_chunk_elems = hex_round_up((total_elems + (2 * n_threads) - 1) / (2 * n_threads), 32); - const uint32_t chunk_size = (std::min)(max_chunk_elems, (std::max)(target_chunk_elems, min_chunk_elems)); - const uint32_t chunk_bytes = hex_round_up(chunk_size * elem_size, 128); - - kparams->kernel_type = HTP_BINARY_KERNEL_CHUNKED; - kparams->n_threads = n_threads; - kparams->rows_per_buffer = 1; - kparams->src1_row_size_aligned = is_scalar_broadcast ? 0 : src1_row_size_aligned; - kparams->src1_size = 0; - kparams->chunk_size = chunk_size; - kparams->chunk_bytes = chunk_bytes; - kparams->is_scalar = is_scalar_broadcast ? 1 : 0; - - htp_binary_vtcm_layout_build(&L, kparams, sess->vtcm_size); - if (L.total_bytes == 0 || L.total_bytes > sess->vtcm_size) { - return false; - } - - kparams->vtcm_size = L.total_bytes; - return true; - } - return false; - } - - kparams->rows_per_buffer = L.rows_per_buffer; - kparams->vtcm_size = L.total_bytes; - - return true; -} - -static void ggml_hexagon_precompute_unary_params( - const struct ggml_hexagon_session * sess, - uint32_t op, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_unary_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads = (std::min)((uint32_t)sess->n_threads, src0_nrows); - - kparams->n_threads = n_threads; - - const size_t elem_size = ggml_type_size(src0->type); - - const size_t src0_data_row_size = src0->ne[0] * elem_size; - const size_t dst_data_row_size = dst->ne[0] * ggml_type_size(dst->type); - - const size_t src0_row_size_aligned = hex_round_up(src0_data_row_size, 128); - const size_t dst_row_size_aligned = hex_round_up(dst_data_row_size, 128); - - kparams->src0_row_size_aligned = src0_row_size_aligned; - kparams->dst_row_size_aligned = dst_row_size_aligned; - - size_t src1_data_row_size = 0; - size_t src1_row_size_aligned = 0; - bool broadcast_weight = false; - - if (op == HTP_OP_RMS_NORM_MUL) { - GGML_ASSERT(src1 != nullptr); - src1_data_row_size = src1->ne[0] * ggml_type_size(src1->type); - src1_row_size_aligned = hex_round_up(src1_data_row_size, 128); - broadcast_weight = (src1->ne[1] * src1->ne[2] * src1->ne[3] == 1); - } - - kparams->src1_row_size_aligned = src1_row_size_aligned; - kparams->broadcast_weight = broadcast_weight; - - struct htp_unary_vtcm_layout L; - uint32_t col_tile = 0; - uint32_t vtcm_row_per_thread = 0; - - htp_unary_vtcm_layout_build(&L, op, src0->ne[0], dst->ne[0], - op == HTP_OP_RMS_NORM_MUL ? src1->ne[0] : 0, - broadcast_weight, n_threads, sess->vtcm_size, elem_size, - &col_tile, &vtcm_row_per_thread); - - kparams->col_tile = col_tile; - kparams->vtcm_row_per_thread = vtcm_row_per_thread; - kparams->vtcm_size = L.total_bytes; - - kparams->vtcm_src0_size_per_thread = L.src0_bytes; - kparams->vtcm_src1_size_per_thread = L.src1_bytes; - kparams->vtcm_dst_size_per_thread = L.dst_bytes; - - kparams->vtcm_src0_size = L.src0_bytes * n_threads; - kparams->vtcm_src1_size = L.src1_bytes * n_threads; - kparams->vtcm_dst_size = L.dst_bytes * n_threads; - - kparams->block = col_tile ? 0 : ((L.src0_bytes / 2) / src0_row_size_aligned); - - const uint32_t tiles_per_row = col_tile > 0 ? (src0->ne[0] + col_tile - 1) / col_tile : 1; - kparams->div_ne01 = init_fastdiv_values(src0->ne[1]); - kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); - kparams->div_ne012 = init_fastdiv_values(src0->ne[1] * src0->ne[2]); - kparams->div_tpr = init_fastdiv_values(tiles_per_row); -} - -static void ggml_hexagon_precompute_get_rows_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_get_rows_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const uint32_t ne00 = src0->ne[0]; - const uint32_t ne02 = src0->ne[2]; - const uint32_t ne03 = src0->ne[3]; - - const uint32_t ne10 = src1->ne[0]; - const uint32_t ne11 = src1->ne[1]; - const uint32_t ne12 = src1->ne[2]; - const uint32_t nr = ne10 * ne11 * ne12; - - const ggml_tensor * src0_base = src0->view_src ? src0->view_src : src0; - const auto * extra = src0_base->buffer && ggml_backend_buffer_is_hexagon(src0_base->buffer) ? - (const ggml_hexagon_tensor_extra *) src0_base->extra : nullptr; - const bool tiled = src0->type == GGML_TYPE_Q4_0 || (extra && (extra->flags & GGML_HEXAGON_TENSOR_REPACK) != 0) || - sess->needs_repack.count(src0_base) || sess->needs_repack.count(src0); - - if (src0->type == dst->type) { - kparams->kernel_type = HTP_GET_ROWS_KERNEL_SAMETYPE; - } else if (tiled) { - kparams->kernel_type = HTP_GET_ROWS_KERNEL_TILED; - } else { - kparams->kernel_type = HTP_GET_ROWS_KERNEL_FLAT; - } - - const uint32_t chunks_per_row = 1; - const uint32_t chunk_size = ne00; - const uint32_t total_tasks = nr; - - kparams->n_threads = (std::min)((uint32_t)sess->n_threads, total_tasks); - - struct htp_get_rows_vtcm_layout vtcm_layout = {}; - while (kparams->n_threads > 0) { - htp_get_rows_vtcm_layout_build(&vtcm_layout, kparams->kernel_type, src0->type, ne00, kparams->n_threads); - if (vtcm_layout.total_bytes <= sess->vtcm_size) { - break; - } - --kparams->n_threads; - } - - if (kparams->n_threads == 0 && total_tasks > 0) { - htp_get_rows_vtcm_layout_build(&vtcm_layout, kparams->kernel_type, src0->type, ne00, 1); - } - - kparams->vtcm_size = (total_tasks == 0) ? 0 : vtcm_layout.total_bytes; - kparams->tasks_per_thread = kparams->n_threads > 0 ? (total_tasks + kparams->n_threads - 1) / kparams->n_threads : 0; - - kparams->chunks_per_row = chunks_per_row; - kparams->chunk_size = chunk_size; - kparams->total_tasks = total_tasks; - - kparams->div_ne10 = ne10 > 0 ? init_fastdiv_values(ne10) : fastdiv_values{0, 0}; - kparams->div_ne10_ne11 = (ne10 * ne11) > 0 ? init_fastdiv_values(ne10 * ne11) : fastdiv_values{0, 0}; - kparams->div_chunks_per_row = chunks_per_row > 0 ? init_fastdiv_values(chunks_per_row) : fastdiv_values{0, 0}; - kparams->div_ne02 = ne02 > 0 ? init_fastdiv_values(ne02) : fastdiv_values{0, 0}; - kparams->div_ne03 = ne03 > 0 ? init_fastdiv_values(ne03) : fastdiv_values{0, 0}; -} - -static void ggml_hexagon_precompute_set_rows_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, // values - const struct ggml_tensor * src1, // indices - const struct ggml_tensor * dst, // destination - struct htp_set_rows_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const uint32_t nr = src0->ne[1]; - - kparams->n_threads = (std::min)((uint32_t)sess->n_threads, nr); - kparams->tasks_per_thread = (nr + kparams->n_threads - 1) / kparams->n_threads; - kparams->total_tasks = nr; - - kparams->div_ne11 = init_fastdiv_values(src1->ne[1]); - kparams->div_ne12 = init_fastdiv_values(src1->ne[2]); - kparams->div_tasks_per_thread = init_fastdiv_values(kparams->tasks_per_thread); - kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); - - struct htp_set_rows_vtcm_layout vtcm_layout; - htp_set_rows_vtcm_layout_build(&vtcm_layout, dst->type, src0->ne[0], kparams->n_threads); - kparams->vtcm_size = vtcm_layout.total_bytes; -} - -static void ggml_hexagon_precompute_softmax_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_softmax_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - - const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, src0_nrows); - - float scale = 1.0f; - float max_bias = 0.0f; - memcpy(&scale, &op->op_params[0], sizeof(float)); - memcpy(&max_bias, &op->op_params[1], sizeof(float)); - - kparams->scale = scale; - kparams->max_bias = max_bias; - - const uint32_t n_head = src0->ne[2]; - const uint32_t n_head_log2 = 1u << (uint32_t) floor(log2(n_head)); - kparams->n_head = n_head; - kparams->n_head_log2 = n_head_log2; - - if (max_bias > 0.0f && n_head_log2 > 0) { - kparams->m0 = powf(2.0f, -(max_bias) / n_head_log2); - kparams->m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); - } else { - kparams->m0 = 1.0f; - kparams->m1 = 1.0f; - } - - kparams->use_src1 = (src1 != nullptr) ? 1 : 0; - kparams->use_f16 = (src1 != nullptr && src1->type == GGML_TYPE_F16) ? 1 : 0; - - const uint32_t ne00 = src0->ne[0]; - const uint32_t ne10 = src1 ? src1->ne[0] : 1; - - struct htp_softmax_vtcm_layout layout; - htp_softmax_vtcm_layout_build(&layout, ne00, ne10, kparams->use_src1 != 0, kparams->use_f16 != 0, n_threads); - - kparams->n_threads = n_threads; - kparams->src0_nrows = src0_nrows; - kparams->src0_nrows_per_thread = (src0_nrows + n_threads - 1) / n_threads; - kparams->vtcm_size = (uint32_t) layout.total_bytes; - kparams->vtcm_src0_size_per_thread = (uint32_t) layout.src0_bytes_per_thread; - kparams->vtcm_src1_size_per_thread = (uint32_t) layout.src1_bytes_per_thread; - kparams->vtcm_dst_size_per_thread = (uint32_t) layout.dst_bytes_per_thread; - kparams->src0_row_size_aligned = (uint32_t) layout.src0_spad_half_size; - kparams->src1_row_size_aligned = (uint32_t) layout.src1_spad_half_size; - kparams->dst_row_size_aligned = (uint32_t) layout.dst_spad_half_size; - kparams->src0_spad_half_size = (uint32_t) layout.src0_spad_half_size; - kparams->src1_spad_half_size = (uint32_t) layout.src1_spad_half_size; - kparams->dst_spad_half_size = (uint32_t) layout.dst_spad_half_size; - if (!kparams->use_src1) { - kparams->kernel_id = HTP_SOFTMAX_KERNEL_NOMASK; - } else if (kparams->use_f16) { - kparams->kernel_id = HTP_SOFTMAX_KERNEL_MASK_F16; - } else { - kparams->kernel_id = HTP_SOFTMAX_KERNEL_MASK_F32; - } - - if (src0->ne[1] > 0) kparams->div_ne01 = init_fastdiv_values(src0->ne[1]); - if (src0->ne[2] > 0) kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); - const uint32_t ne12 = src1 ? src1->ne[2] : 1; - const uint32_t ne13 = src1 ? src1->ne[3] : 1; - if (ne12 > 0) kparams->div_ne12 = init_fastdiv_values(ne12); - if (ne13 > 0) kparams->div_ne13 = init_fastdiv_values(ne13); -} - -static void ggml_hexagon_precompute_rope_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_rope_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * dst = op; - - const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, src0_nrows); - const uint32_t n_freq_factors = src2 ? (uint32_t) src2->ne[0] : 0; - - struct htp_rope_vtcm_layout layout; - htp_rope_vtcm_layout_build(&layout, src0->ne[0], n_threads, n_freq_factors); - - kparams->n_threads = n_threads; - kparams->src0_nrows = src0_nrows; - kparams->src0_nrows_per_thread = (src0_nrows + n_threads - 1) / n_threads; - kparams->vtcm_size = (uint32_t) layout.total_bytes; - kparams->spad_per_thread = (uint32_t) layout.bytes_per_thread; - kparams->theta_cache_offset = (uint32_t) layout.theta_cache_size_aligned; - kparams->src0_row_size_aligned = (uint32_t) layout.src0_row_size_aligned; - kparams->freq_factors_offset = (uint32_t) (layout.bytes_per_thread * n_threads); - kparams->freq_factors_size = (uint32_t) layout.freq_factors_size_aligned; - - if (src0_nrows > 0) { - kparams->div_ne2_ne1 = init_fastdiv_values(dst->ne[2] * dst->ne[1]); - kparams->div_ne1 = init_fastdiv_values(dst->ne[1]); - } -} - -static void ggml_hexagon_precompute_ssm_conv_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * src1, - const struct ggml_tensor * dst, - struct htp_ssm_conv_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const uint32_t d_conv = (uint32_t) src1->ne[0]; - const uint32_t d_inner = (uint32_t) src0->ne[1]; - const uint32_t n_t = (uint32_t) dst->ne[1]; - const uint32_t n_s = (uint32_t) dst->ne[2]; - const uint32_t ncs = (uint32_t) src0->ne[0]; - - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, (d_inner + 31) / 32); - - kparams->n_threads = n_threads; - kparams->d_conv = d_conv; - kparams->d_inner = d_inner; - kparams->n_t = n_t; - kparams->n_s = n_s; - - const uint32_t raw_rpt = (d_inner + n_threads - 1) / n_threads; - const uint32_t d_inner_per_thread = hex_round_up(raw_rpt, 32); - - const uint32_t src1_raw_bytes = hex_round_up(d_inner_per_thread * d_conv * sizeof(float), 128) + 128; - const uint32_t src1_T_bytes = hex_round_up(d_conv * d_inner_per_thread * sizeof(float), 128); - const uint32_t vtcm_src1_per_thread = src1_raw_bytes + src1_T_bytes; - - uint32_t vtcm_src0_per_thread = 0; - uint32_t vtcm_dst_per_thread = 0; - - if (n_t == 1) { - kparams->d_inner_tile = d_inner_per_thread; - - const uint32_t src0_tile_raw_bytes = hex_round_up(d_inner_per_thread * d_conv * sizeof(float), 128); - const uint32_t src0_T_bytes = hex_round_up(d_conv * d_inner_per_thread * sizeof(float), 128); - vtcm_src0_per_thread = 2 * src0_tile_raw_bytes + src0_T_bytes; - - const uint32_t dst_tile_bytes = hex_round_up(d_inner_per_thread * sizeof(float), 128); - vtcm_dst_per_thread = 2 * dst_tile_bytes; - } else { - const size_t vtcm_budget = (sess->vtcm_size > 0 ? sess->vtcm_size / n_threads : (1024 * 1024)); - - // the kernel double-buffers the raw src0 tile and the dst tile, and transposes - // one 32-channel block at a time - const uint32_t src0_block_T = hex_round_up(ncs * 32 * sizeof(float), 128); - const size_t fixed_bytes = vtcm_src1_per_thread + src0_block_T; - const size_t avail_for_tiles = vtcm_budget > fixed_bytes ? vtcm_budget - fixed_bytes : (128 * 1024); - - uint32_t target_max_tile = hex_round_up((d_inner_per_thread + 3) / 4, 32); - target_max_tile = (std::max)(target_max_tile, 32u); - target_max_tile = (std::min)(target_max_tile, 128u); - - uint32_t d_inner_tile = (uint32_t)(avail_for_tiles / (2 * (ncs + n_t) * sizeof(float))); - d_inner_tile = (d_inner_tile / 32) * 32; - if (d_inner_tile == 0) { - d_inner_tile = 32; - } - if (d_inner_tile > target_max_tile) { - d_inner_tile = target_max_tile; - } - if (d_inner_tile > d_inner_per_thread) { - d_inner_tile = d_inner_per_thread; - } - kparams->d_inner_tile = d_inner_tile; - - const uint32_t src0_tile_raw = hex_round_up(d_inner_tile * ncs * sizeof(float), 128); - vtcm_src0_per_thread = 2 * src0_tile_raw + src0_block_T; - - vtcm_dst_per_thread = 2 * hex_round_up(d_inner_tile * n_t * sizeof(float), 128); - } - - kparams->vtcm_src0_size_per_thread = vtcm_src0_per_thread; - kparams->vtcm_src1_size_per_thread = vtcm_src1_per_thread; - kparams->vtcm_dst_size_per_thread = vtcm_dst_per_thread; - - kparams->vtcm_src0_size = vtcm_src0_per_thread * n_threads; - kparams->vtcm_src1_size = vtcm_src1_per_thread * n_threads; - kparams->vtcm_dst_size = vtcm_dst_per_thread * n_threads; - kparams->vtcm_size = kparams->vtcm_src0_size + kparams->vtcm_src1_size + kparams->vtcm_dst_size; -} - -static void ggml_hexagon_precompute_gated_delta_net_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_gdn_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const struct ggml_tensor * q = op->src[0]; - const struct ggml_tensor * k = op->src[1]; - const struct ggml_tensor * v = op->src[2]; - const struct ggml_tensor * g = op->src[3]; - const struct ggml_tensor * state = op->src[5]; - - const uint32_t S_v = (uint32_t) v->ne[0]; - const uint32_t H = (uint32_t) v->ne[1]; - const uint32_t n_tokens = (uint32_t) v->ne[2]; - const uint32_t n_seqs = (uint32_t) v->ne[3]; - const uint32_t K = (uint32_t) ggml_get_op_params_i32(op, 0); - - const uint32_t rq3 = (uint32_t) (n_seqs / q->ne[3]); - const uint32_t rk3 = (uint32_t) (n_seqs / k->ne[3]); - const uint32_t total_rows = H * n_seqs; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, total_rows); - - const bool can_use_hmx = (opt_gdn_select >= 2) && - (sess->n_hmx > 0) && - (S_v % 64 == 0) && - (n_tokens >= HTP_GDN_MIN_TOKENS) && - (g->ne[0] == 1) && - (K == 1); - - struct htp_gdn_hmx_vtcm_layout hmx_layout; - struct htp_gdn_vtcm_layout hvx_layout; - uint32_t n_heads_batch = 1; - - if (can_use_hmx && htp_gdn_hmx_solve_layout(&hmx_layout, S_v, HTP_GDN_CHUNK_SIZE, total_rows, sess->vtcm_size, n_threads, true, &n_heads_batch)) { - kparams->kernel_type = HTP_GDN_KERNEL_HMX_CHUNKED; - kparams->pipeline = hmx_layout.pipeline ? 1 : 0; - kparams->chunk_size = HTP_GDN_CHUNK_SIZE; - kparams->n_chunks = (n_tokens + HTP_GDN_CHUNK_SIZE - 1) / HTP_GDN_CHUNK_SIZE; - kparams->n_heads_batch = (uint16_t) n_heads_batch; - kparams->vtcm_size = (uint32_t) hmx_layout.total_bytes; - kparams->state_aligned = (uint32_t) hmx_layout.state_f32_bytes; - kparams->vtcm_per_thread = (uint32_t) (hmx_layout.total_bytes / (n_threads > 0 ? n_threads : 1)); - } else { - htp_gdn_vtcm_layout_build(&hvx_layout, S_v, n_threads); - kparams->kernel_type = HTP_GDN_KERNEL_HVX_RECURRENT; - kparams->pipeline = 0; - kparams->n_heads_batch = 1; - kparams->state_aligned = (uint32_t) hvx_layout.state_aligned; - kparams->vtcm_per_thread = (uint32_t) hvx_layout.bytes_per_thread; - kparams->vtcm_size = (uint32_t) hvx_layout.total_bytes; - } - - kparams->n_threads = n_threads; - kparams->S_v = S_v; - kparams->H = H; - kparams->n_tokens = n_tokens; - kparams->n_seqs = n_seqs; - kparams->K = K; - kparams->total_rows = total_rows; - kparams->rows_per_thread = (total_rows + kparams->n_threads - 1) / kparams->n_threads; - kparams->kda = (g->ne[0] == S_v) ? 1 : 0; - kparams->state_seq_stride = (uint32_t) (state->nb[3] / sizeof(float)); - kparams->state_size_per_snap = S_v * S_v * H * n_seqs; - kparams->scale = 1.0f / sqrtf((float) S_v); - - if (H > 0) kparams->div_H = init_fastdiv_values(H); - if (q->ne[1] > 0) kparams->div_q1 = init_fastdiv_values((uint32_t) q->ne[1]); - if (k->ne[1] > 0) kparams->div_k1 = init_fastdiv_values((uint32_t) k->ne[1]); - if (rq3 > 0) kparams->div_rq3 = init_fastdiv_values(rq3); - if (rk3 > 0) kparams->div_rk3 = init_fastdiv_values(rk3); - if (kparams->n_threads > 0) kparams->div_n_threads = init_fastdiv_values(kparams->n_threads); -} - -static void ggml_hexagon_precompute_sort_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - bool is_top_k, - struct htp_sort_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t ne00 = src0->ne[0]; - const uint32_t k = dst->ne[0]; - - int32_t order = GGML_SORT_ORDER_DESC; - if (!is_top_k) { - order = ((const int32_t *) op->op_params)[0]; - } - - const uint32_t n_threads_max = sess->n_threads > 0 ? sess->n_threads : 4; - const size_t vtcm_budget = sess->vtcm_size > 0 ? sess->vtcm_size : (8 * 1024 * 1024); - - struct htp_sort_vtcm_layout layout; - bool ok = htp_sort_solve_layout(&layout, ne00, total_rows, k, n_threads_max, vtcm_budget, is_top_k); - GGML_ASSERT(ok); - - kparams->n_threads = (int32_t) layout.n_threads; - kparams->total_rows = (int32_t) total_rows; - kparams->row_start = 0; - kparams->row_end = (int32_t) total_rows; - kparams->ne00 = (int32_t) ne00; - kparams->k = (int32_t) k; - kparams->order = order; - kparams->is_top_k = is_top_k ? 1 : 0; - kparams->use_dma = 1; - kparams->chunk_elems = (int32_t) layout.chunk_elems; - kparams->n_chunks = (int32_t) layout.n_chunks; - kparams->vtcm_size = (int32_t) layout.total_bytes; - kparams->phase1_slot_size = (int32_t) layout.phase1_slot_size; - kparams->merge_values_off = (int32_t) layout.merge_values_off; - kparams->merge_indices_off = (int32_t) layout.merge_indices_off; - kparams->merge_elems = (int32_t) layout.merge_elems; - kparams->n_slots = (int32_t) layout.n_slots; -} - -static void ggml_hexagon_pool_interior_range( - uint32_t src_x, uint32_t dst_x, uint32_t kernel_x, uint32_t stride_x, int32_t pad_x, - uint32_t * ox_lo, uint32_t * ox_hi) { - const uint32_t lo_raw = ((uint32_t) pad_x + stride_x - 1) / stride_x; - *ox_lo = (lo_raw < dst_x) ? lo_raw : dst_x; - - const int32_t numer_hi = (int32_t) src_x - (int32_t) kernel_x + pad_x; - if (numer_hi < 0) { - *ox_hi = 0; - } else { - const uint32_t hi_raw = (uint32_t) numer_hi / stride_x + 1; - *ox_hi = (hi_raw < dst_x) ? hi_raw : dst_x; - } - if (*ox_hi < *ox_lo) { - *ox_hi = *ox_lo; - } -} - -static bool ggml_hexagon_pool_shape_fits( - const struct ggml_tensor * src0, - const struct ggml_tensor * dst -) { - return ggml_nbytes(src0) <= UINT32_MAX - 256 && ggml_nbytes(dst) <= UINT32_MAX - 256; -} - -static void ggml_hexagon_precompute_pool_2d_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, - const struct ggml_tensor * dst, - struct htp_pool_2d_kernel_params * kparams, - bool is_pool_1d -) { - memset(kparams, 0, sizeof(*kparams)); - - const uint32_t src_x = (uint32_t) src0->ne[0]; - const uint32_t src_y = is_pool_1d ? 1 : (uint32_t) src0->ne[1]; - const uint32_t dst_x = (uint32_t) dst->ne[0]; - const uint32_t dst_y = is_pool_1d ? 1 : (uint32_t) dst->ne[1]; - const uint32_t src_plane_bytes = src_x * src_y * sizeof(float); - const uint32_t dst_plane_bytes = dst_x * dst_y * sizeof(float); - const uint32_t planes = (uint32_t) (is_pool_1d - ? (uint64_t) src0->ne[1] * (uint64_t) src0->ne[2] * (uint64_t) src0->ne[3] - : (uint64_t) src0->ne[2] * (uint64_t) src0->ne[3]); - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, planes > 0 ? planes : 1); - - struct htp_pool_vtcm_layout layout; - const bool ok = htp_pool_solve_layout(&layout, src_x, src_y, dst_x, dst_y, n_threads, sess->vtcm_size); - GGML_ASSERT(ok); - - kparams->src_x = src_x; - kparams->src_y = src_y; - kparams->dst_x = dst_x; - kparams->dst_y = dst_y; - kparams->kernel_x = (uint32_t) ggml_get_op_params_i32(dst, 1); - kparams->kernel_y = is_pool_1d ? 1 : (uint32_t) ggml_get_op_params_i32(dst, 2); - kparams->stride_x = (uint32_t) ggml_get_op_params_i32(dst, is_pool_1d ? 2 : 3); - kparams->stride_y = is_pool_1d ? 1 : (uint32_t) ggml_get_op_params_i32(dst, 4); - kparams->pad_x = ggml_get_op_params_i32(dst, is_pool_1d ? 3 : 5); - kparams->pad_y = is_pool_1d ? 0 : ggml_get_op_params_i32(dst, 6); - kparams->src_plane_bytes = src_plane_bytes; - kparams->dst_plane_bytes = dst_plane_bytes; - kparams->src_plane_bytes_aligned = (uint32_t) layout.src_spad_half_size; - kparams->dst_plane_bytes_aligned = (uint32_t) layout.dst_spad_half_size; - kparams->n_threads = n_threads; - kparams->planes = planes; - kparams->pool_op = (uint32_t) ggml_get_op_params_i32(dst, 0); - // Fast HVX path requires exact tiling and a supported kernel width. - kparams->fast_path = (kparams->pad_x == 0 && kparams->pad_y == 0 && - kparams->stride_x == kparams->kernel_x && kparams->stride_y == kparams->kernel_y && - (kparams->kernel_x == 1 || kparams->kernel_x == 2)) ? 1 : 0; - kparams->global_path = (kparams->pad_x == 0 && kparams->pad_y == 0 && - kparams->stride_x == kparams->kernel_x && - kparams->stride_y == kparams->kernel_y && - kparams->kernel_x == kparams->src_x && - kparams->kernel_y == kparams->src_y && - kparams->dst_x == 1 && kparams->dst_y == 1) ? 1 : 0; - kparams->block_path = (kparams->pad_x == 0 && kparams->pad_y == 0 && - kparams->kernel_y == 1 && kparams->stride_y == 1 && - kparams->stride_x == kparams->kernel_x && - kparams->kernel_x >= 32) ? 1 : 0; - kparams->avg_divide_count = (is_pool_1d && kparams->pool_op == GGML_OP_POOL_AVG) ? 1 : 0; - ggml_hexagon_pool_interior_range(kparams->src_x, kparams->dst_x, kparams->kernel_x, - kparams->stride_x, kparams->pad_x, - &kparams->ox_lo, &kparams->ox_hi); - - const bool narrow_ok = (uint64_t) kparams->dst_x * kparams->kernel_x <= 32; - kparams->narrow_path = (kparams->fast_path && narrow_ok) ? 1 : 0; - kparams->inv_kernel_area = 1.0f / (float) (kparams->kernel_x * kparams->kernel_y); -} - -static bool ggml_hexagon_precompute_concat_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_concat_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->kernel_type = HTP_CONCAT_KERNEL_UNSUPPORTED; - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; - - if (!src0 || !src1 || !dst) { - return false; - } - - int dim = ((const int32_t *) op->op_params)[0]; - if (dim < 0 || dim >= GGML_MAX_DIMS) { - return false; - } - kparams->dim = dim; - - if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_I32) { - return false; - } - if (src0->type != dst->type || src1->type != dst->type) { - return false; - } - - const uint32_t type_size = ggml_type_size(dst->type); - - for (int d = 0; d < GGML_MAX_DIMS; d++) { - const int64_t ne_d = (d == dim) ? src0->ne[d] + src1->ne[d] : src0->ne[d]; - if (dst->ne[d] != ne_d || (d != dim && src1->ne[d] != dst->ne[d])) { - return false; - } - } - - const uint32_t max_gather_ne0 = 128 / type_size; - const uint32_t total_rows = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); - const bool b_dense = (src1->nb[0] == type_size); - const bool gather_strides_ok = - src0->nb[1] >= (size_t) src0->ne[0] * type_size && - (b_dense ? src1->nb[1] >= (size_t) src1->ne[0] * type_size - : src1->nb[0] >= (size_t) src1->ne[1] * type_size); - - if (dim == 0 && - (dst->type == GGML_TYPE_F32 || dst->type == GGML_TYPE_F16) && - dst->ne[0] <= max_gather_ne0 && - dst->nb[0] == type_size && dst->nb[1] == (size_t) dst->ne[0] * type_size && - src0->nb[0] == type_size && - (src1->nb[0] == type_size || src1->nb[1] == type_size) && - gather_strides_ok && - htp_gather_rows_tensor_outer_contiguous(dst) && - htp_gather_rows_tensor_outer_contiguous(src0) && - htp_gather_rows_tensor_outer_contiguous(src1)) { - - if (htp_gather_rows_solve_layout(&kparams->u.gather, - (uint32_t) src0->ne[0], (uint32_t) src0->nb[1], - (uint32_t) src1->ne[0], (uint32_t) src1->nb[1], b_dense, - type_size, total_rows, - sess->n_threads, sess->mdev.count, sess->vtcm_size)) { - kparams->kernel_type = HTP_CONCAT_KERNEL_GATHER_ROWS; - kparams->n_threads = (uint8_t) sess->n_threads; - kparams->vtcm_size = kparams->u.gather.slice * sess->n_threads; - return true; - } - } - - const bool dma_strides_ok = (src0->nb[0] == type_size && src1->nb[0] == type_size && dst->nb[0] == type_size); - - if (dma_strides_ok) { - kparams->kernel_type = HTP_CONCAT_KERNEL_REGULAR; - kparams->n_threads = 1; - return true; - } - - const bool is_src1_transposed = (src1->nb[0] > src1->nb[1]); - const bool is_src0_transposed = (src0->nb[0] > src0->nb[1]); - const bool transposed_rows_ok = (src0->nb[0] == type_size && src1->nb[1] == type_size && dst->nb[0] == type_size); - - if (dim == 0 && is_src1_transposed && !is_src0_transposed && transposed_rows_ok && - (dst->type == GGML_TYPE_F32 || dst->type == GGML_TYPE_F16)) { - - const uint32_t n_threads = sess->n_threads > 0 ? (uint32_t) sess->n_threads : 8; - struct htp_concat_transposed_vtcm_layout layout; - htp_concat_transposed_vtcm_layout_build(&layout, (uint32_t) src0->ne[0], (uint32_t) src1->ne[0], type_size, n_threads); - - if (sess->vtcm_size > 0 && layout.total_bytes > sess->vtcm_size) { - return false; - } - - kparams->kernel_type = HTP_CONCAT_KERNEL_TRANSPOSED; - kparams->n_threads = n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->u.transposed.spad0_size_per_thread = layout.src0_spad_size_per_thread; - kparams->u.transposed.spad1_size_per_thread = layout.src1_spad_size_per_thread; - return true; - } - - return false; -} - -static bool ggml_hexagon_precompute_cpy_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_copy_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->kernel_type = HTP_COPY_KERNEL_UNSUPPORTED; - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - if (!src0 || !dst) { - return false; - } - - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_I32) { - return false; - } - if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_I32) { - return false; - } - - const int64_t nelem_src = ggml_nelements(src0); - const int64_t nelem_dst = ggml_nelements(dst); - if (nelem_src != nelem_dst || nelem_src < 0) { - return false; - } - - const uint32_t src_type_size = ggml_type_size(src0->type); - const uint32_t dst_type_size = ggml_type_size(dst->type); - - kparams->src0_type_size = (uint8_t) src_type_size; - kparams->dst_type_size = (uint8_t) dst_type_size; - kparams->total_elems = (uint32_t) nelem_src; - - if (nelem_src == 0) { - kparams->kernel_type = HTP_COPY_KERNEL_1D_CONTIG; - return true; - } - - if (nelem_src == 1) { - if (src0->type == dst->type) { - kparams->kernel_type = HTP_COPY_KERNEL_SCALAR; - return true; - } - if ((src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_I32) || - (src0->type == GGML_TYPE_I32 && dst->type == GGML_TYPE_F32) || - (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F16) || - (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F32)) { - kparams->kernel_type = HTP_COPY_KERNEL_SCALAR; - return true; - } - return false; - } - - const bool sametype = (src0->type == dst->type); - - bool same_extents = true; - for (int d = 0; d < GGML_MAX_DIMS; d++) { - if (src0->ne[d] != dst->ne[d]) { - same_extents = false; - break; - } - } - - const bool transposed = (src0->nb[0] > src0->nb[1]) || (dst->nb[0] > dst->nb[1]) || - (src0->nb[0] != src_type_size) || (dst->nb[0] != dst_type_size) || - (src0->nb[1] < (size_t) src0->ne[0] * src_type_size) || (dst->nb[1] < (size_t) dst->ne[0] * dst_type_size); - const bool sameshape = same_extents && !transposed; - - const bool src_is_contiguous = ggml_is_contiguous(src0); - const bool dst_is_contiguous = ggml_is_contiguous(dst); - - if (sametype) { - if (src_is_contiguous && dst_is_contiguous) { - kparams->kernel_type = HTP_COPY_KERNEL_1D_CONTIG; - return true; - } - - const uint32_t max_gather_ne0 = 128 / src_type_size; - const uint32_t total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); - if ((src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16) && - dst_is_contiguous && !src_is_contiguous && - src0->nb[0] == src_type_size && src0->ne[0] <= max_gather_ne0 && - src0->nb[1] >= (size_t) src0->ne[0] * src_type_size && - total_rows > 1 && - htp_gather_rows_tensor_outer_contiguous(src0)) { - - if (htp_gather_rows_solve_layout(&kparams->u.gather, - (uint32_t) src0->ne[0], (uint32_t) src0->nb[1], - 0, 0, false, - src_type_size, total_rows, - sess->n_threads, sess->mdev.count, sess->vtcm_size)) { - kparams->kernel_type = HTP_COPY_KERNEL_GATHER_ROWS; - kparams->n_threads = (uint8_t) sess->n_threads; - kparams->vtcm_size = kparams->u.gather.slice * sess->n_threads; - return true; - } - } - - if (sameshape) { - kparams->kernel_type = HTP_COPY_KERNEL_SAMESHAPE_SAMETYPE; - kparams->total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); - return true; - } - - kparams->kernel_type = HTP_COPY_KERNEL_RESHAPE; - kparams->n_threads = sess->n_threads > 0 ? (uint8_t) sess->n_threads : 4; - kparams->u.reshape.div_ne0 = init_fastdiv_values((uint32_t) dst->ne[0]); - kparams->u.reshape.div_ne1_ne0 = init_fastdiv_values((uint32_t) (dst->ne[1] * dst->ne[0])); - kparams->u.reshape.div_ne2_ne1_ne0 = init_fastdiv_values((uint32_t) (dst->ne[2] * dst->ne[1] * dst->ne[0])); - kparams->u.reshape.div_ne00 = init_fastdiv_values((uint32_t) src0->ne[0]); - kparams->u.reshape.div_ne01_ne00 = init_fastdiv_values((uint32_t) (src0->ne[1] * src0->ne[0])); - kparams->u.reshape.div_ne02_ne01_ne00 = init_fastdiv_values((uint32_t) (src0->ne[2] * src0->ne[1] * src0->ne[0])); - return true; - } - - if (!sameshape) { - return false; - } - - const bool valid_conversion = (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F16) || - (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F32) || - (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_I32) || - (src0->type == GGML_TYPE_I32 && dst->type == GGML_TYPE_F32); - if (!valid_conversion) { - return false; - } - - const uint32_t n_threads = sess->n_threads > 0 ? (uint32_t) sess->n_threads : 4; - struct htp_copy_convert_vtcm_layout layout; - htp_copy_convert_vtcm_layout_build(&layout, (uint32_t) src0->ne[0], (uint32_t) src0->ne[1], src_type_size, dst_type_size, n_threads); - - if (sess->vtcm_size > 0 && layout.total_bytes > sess->vtcm_size) { - return false; - } - - kparams->kernel_type = HTP_COPY_KERNEL_SAMESHAPE_CONVERT; - kparams->total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); - kparams->n_threads = (uint8_t) n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->u.convert.src0_buf_size = layout.src0_buf_size; - kparams->u.convert.dst_buf_size = layout.dst_buf_size; - kparams->u.convert.spad0_size_per_thread = layout.spad0_size_per_thread; - kparams->u.convert.spad1_size_per_thread = layout.spad1_size_per_thread; - kparams->u.convert.src0_row_stride = layout.src0_row_stride; - kparams->u.convert.dst_row_stride = layout.dst_row_stride; - kparams->u.convert.blk_rows = layout.blk_rows; - kparams->u.convert.div_ne01 = init_fastdiv_values((uint32_t) src0->ne[1]); - kparams->u.convert.div_ne02_ne01 = init_fastdiv_values((uint32_t) (src0->ne[2] * src0->ne[1])); - - return true; -} - -static void ggml_hexagon_precompute_fused_mmnx_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, // W0 - const struct ggml_tensor * act, // x - int32_t n_weights, - struct htp_mm_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->n_threads = sess->n_threads; - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; - - const int ne10 = act->ne[0]; - const int ne11 = act->ne[1]; - const int ne12 = act->ne[2]; - const int ne13 = act->ne[3]; - - const int wtype = src0->type; - const bool is_repack = ggml_hexagon_is_repack_type((ggml_type) wtype); - const int ne00_padded = is_repack ? hex_round_up(ne00, 32) : ne00; - const int ne01_padded = is_repack ? hex_round_up(ne01, 32) : ne01; - const int ne11_padded = hex_round_up(ne11, 32); - const int ne01_tiled = hex_round_up(ne01_padded, 32); - - const size_t vtcm_budget = sess->vtcm_size; - const bool is_batched = (ne02 * ne03 > 1 || ne12 * ne13 > 1); - - bool hmx_enabled = (sess->n_hmx > 0) && (opt_mm_select >= 2); - if (hmx_enabled && ggml_hexagon_matmul_is_hmx_eligible(src0, act, nullptr, ne01_padded, false, is_batched)) { - if (ggml_hexagon_precompute_hmx_mm_params(sess, src0, act, nullptr, wtype, ne00_padded, ne01_tiled, ne02, ne11, ne12, ne11_padded, false, is_batched, 0, vtcm_budget, kparams)) { - kparams->n_weights = n_weights; - goto finalize; - } - } - - if (!is_repack) { - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } - - { - const int act_nrows = ne11 * ne12 * ne13; - const size_t act_row_size = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); - const size_t src0_row_size = src0->nb[1]; - - uint32_t best_n_prefetch = 16; - - if (is_repack) { - const uint32_t max_prefetch = (act_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; - best_n_prefetch = 2; - for (uint32_t d = max_prefetch; d >= 2; d /= 2) { - struct htp_mm_hvx_vtcm_layout L; - htp_mm_hvx_vtcm_layout_build( - &L, HTP_MM_KERNEL_HVX_QUANT_ROW, wtype, ne10, act_nrows, sess->n_threads, - 0, src0_row_size, act_row_size, 0, d, false, true - ); - if (L.total_bytes <= sess->vtcm_size) { - best_n_prefetch = d; - break; - } - } - } - - struct htp_mm_hvx_vtcm_layout L; - bool try_tiled = (opt_mm_select >= 1); - - // Test tiled first - htp_mm_hvx_vtcm_layout_build( - &L, HTP_MM_KERNEL_HVX_QUANT_ROW, wtype, ne10, act_nrows, sess->n_threads, - 0, src0_row_size, act_row_size, 0, best_n_prefetch, false, true - ); - - if (try_tiled && L.total_bytes <= sess->vtcm_size) { - kparams->kernel_type = HTP_MM_KERNEL_HVX_QUANT_ROW; - kparams->act_row_size = act_row_size; - kparams->vtcm_src0_size = L.src0_bytes; - kparams->vtcm_act_size = L.act_bytes; - kparams->vtcm_bias_size = 0; - kparams->vtcm_dst_size = L.dst_bytes; - kparams->vtcm_size = L.total_bytes; - kparams->n_prefetch = best_n_prefetch; - kparams->n_weights = n_weights; - } else { - kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; - return; - } - } - -finalize: - kparams->div_ne12_ne1 = init_fastdiv_values(ne12 * ne11); - kparams->div_ne1 = init_fastdiv_values(ne11); - kparams->div_r2 = init_fastdiv_values(ne02 > 0 ? ne12 / ne02 : 1); - kparams->div_r3 = init_fastdiv_values(ne03 > 0 ? ne13 / ne03 : 1); - kparams->div_ne12 = init_fastdiv_values(ne12); -} - -static void ggml_hexagon_precompute_fused_mmidnx_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * src0, // W0 - const struct ggml_tensor * act, // x - const struct ggml_tensor * dst, // dst0 - int32_t n_weights, - struct htp_mm_kernel_params * kparams -) { - ggml_hexagon_precompute_matmul_params_impl(sess, src0, act, dst, 0, 0, kparams); - kparams->n_weights = n_weights; -} - -static bool ggml_hexagon_tensor_is_host(const struct ggml_hexagon_session * sess, const struct ggml_tensor * t) { - return t && t->buffer && ggml_backend_buft_is_host(t->buffer->buft); - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_tensor_is_non_host(const struct ggml_hexagon_session * sess, const struct ggml_tensor * t) { - return t && t->buffer && !ggml_backend_buft_is_host(t->buffer->buft); - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_mul_mat(const struct ggml_hexagon_session * sess, const struct ggml_tensor * dst) { - const struct ggml_tensor * src0 = dst->src[0]; - const struct ggml_tensor * src1 = dst->src[1]; - - if (dst->type != GGML_TYPE_F32) { - return false; - } - - if (src1->type != GGML_TYPE_F32 && src1->type != GGML_TYPE_F16) { - return false; - } - - switch (src0->type) { - case GGML_TYPE_Q4_0: - case GGML_TYPE_Q4_1: - case GGML_TYPE_Q8_0: - case GGML_TYPE_IQ4_NL: - case GGML_TYPE_MXFP4: - case GGML_TYPE_Q4_K: - case GGML_TYPE_Q5_K: - case GGML_TYPE_Q6_K: - case GGML_TYPE_Q3_K: - case GGML_TYPE_Q2_K: - if (!ggml_is_contiguous(src0) || ggml_is_permuted(src0)) { - return false; - } - - if (src0->ne[0] % ((src0->type == GGML_TYPE_Q6_K || src0->type == GGML_TYPE_Q5_K || src0->type == GGML_TYPE_Q4_K || - src0->type == GGML_TYPE_Q3_K || src0->type == GGML_TYPE_Q2_K) ? QK_K : 32)) { - return false; - } - - if (src1->ne[2] < src0->ne[2] || src1->ne[3] < src0->ne[3]) { - return false; - } - if (src1->ne[2] % src0->ne[2] != 0 || src1->ne[3] % src0->ne[3] != 0) { - return false; - } - - if (!src0->buffer) { - sess->needs_repack.insert(src0); - } - break; - - case GGML_TYPE_F16: - if (src0->nb[1] < src0->nb[0]) { - return false; - } - if (src1->ne[2] < src0->ne[2] || src1->ne[3] < src0->ne[3]) { - return false; - } - if (src1->ne[2] % src0->ne[2] != 0 || src1->ne[3] % src0->ne[3] != 0) { - return false; - } - break; - - case GGML_TYPE_F32: - if (src1->type != GGML_TYPE_F32) { - return false; - } - if (src0->nb[1] < src0->nb[0]) { - return false; - } - if (src1->ne[2] < src0->ne[2] || src1->ne[3] < src0->ne[3]) { - return false; - } - if (src1->ne[2] % src0->ne[2] != 0 || src1->ne[3] % src0->ne[3] != 0) { - return false; - } - break; - - default: - return false; - } - - struct htp_mm_kernel_params kparams; - ggml_hexagon_precompute_matmul_params(sess, src0, src1, dst, &kparams); - if (kparams.kernel_type == HTP_MM_KERNEL_UNSUPPORTED || (size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s supported MUL_MAT VTCM size needed (%d) > budget (%zu)\n", sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; + return ti; } - return true; -} - -static bool ggml_hexagon_supported_mul_mat_id(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * dst = op; - - if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32) { - return false; - } + bool fit_tensors(const htp_opnode & node) const { + // check how much extras we will need + size_t extra_bufs = 0; + size_t extra_vmem = 0; + size_t extra_tens = 0; - if (ggml_get_op_params_i32(op, 3) == GGML_PREC_F32) { - return false; - } + const bool check_tens = (n_tens + node.inputs.size() + node.outputs.size()) > n_tens_max; - switch (src0->type) { - case GGML_TYPE_Q4_0: - case GGML_TYPE_Q4_1: - case GGML_TYPE_Q8_0: - case GGML_TYPE_IQ4_NL: - case GGML_TYPE_MXFP4: - case GGML_TYPE_Q4_K: - case GGML_TYPE_Q5_K: - case GGML_TYPE_Q6_K: - case GGML_TYPE_Q3_K: - case GGML_TYPE_Q2_K: - if (!ggml_is_contiguous(src0) || ggml_is_permuted(src0)) { - return false; - } + int seen_bufs[HTP_OP_MAX_BUFS]; + int n_seen_bufs = 0; - if (src0->ne[0] % ((src0->type == GGML_TYPE_Q6_K || src0->type == GGML_TYPE_Q5_K || src0->type == GGML_TYPE_Q4_K || - src0->type == GGML_TYPE_Q3_K || src0->type == GGML_TYPE_Q2_K) ? QK_K : 32)) { - return false; + auto fit_tensor = [&](const ggml_tensor * t) { + if (!t) return; + if (check_tens) { + if (t_map.count(t)) return; + extra_tens++; } - if (!src0->buffer) { - sess->needs_repack.insert(src0); + auto sbuf = static_cast(t->buffer->context); + int fd = sbuf->fd(); + if (find_buffer(fd) < 0) { + for (int i = 0; i < n_seen_bufs; i++) { + if (seen_bufs[i] == fd) return; + } + if (n_seen_bufs < HTP_OP_MAX_BUFS) { + seen_bufs[n_seen_bufs++] = fd; + } + if (!sbuf->extended) { + extra_vmem += sbuf->size(); + } + extra_bufs += 1; } - break; - - default: - return false; - } - - struct htp_mm_kernel_params kparams; - ggml_hexagon_precompute_matmul_params(sess, src0, src1, dst, &kparams); - if (kparams.kernel_type == HTP_MM_KERNEL_UNSUPPORTED || (size_t) kparams.vtcm_size > sess->vtcm_size) { - HEX_VERBOSE("ggml-hex: %s supported MUL_MAT_ID VTCM size needed (%d) > budget (%zu)\n", sess->c_name(), kparams.vtcm_size, sess->vtcm_size); - return false; - } - - return true; -} - -static bool ggml_hexagon_supported_binary(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; + }; - if (src0->type == GGML_TYPE_F32) { - if (src1->type != GGML_TYPE_F32) { - return false; - } - if (dst->type != GGML_TYPE_F32) { - return false; - } - } - else if (src0->type == GGML_TYPE_F16) { - if (src1->type != GGML_TYPE_F16) { - return false; + for (const auto * src : node.get_inputs()) { + fit_tensor(src); } - if (dst->type != GGML_TYPE_F16) { - return false; + for (const auto * output : node.get_outputs()) { + fit_tensor(output); } - } - else { - return false; - } - - if (ggml_is_permuted(src0) || ggml_is_permuted(dst)) { - return false; - } - if (!ggml_are_same_shape(src0, dst)) { - return false; - } - if (!ggml_can_repeat(src1, src0) || ggml_is_permuted(src1)) { - return false; - } - - struct htp_binary_kernel_params kparams; - return ggml_hexagon_precompute_binary_params(sess, op_remap_to_htp(op), src0, src1, dst, &kparams); -} - -static bool ggml_hexagon_supported_add_id(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * dst = op; - if (!src2) { - return false; - } - if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32) { - return false; - } - if (!ggml_are_same_shape(src0, dst)) { - return false; - } - if (src1->ne[0] != src0->ne[0] || src1->ne[2] != 1 || src1->ne[3] != 1) { - return false; - } - if (src2->ne[0] != src0->ne[1] || src2->ne[1] != src0->ne[2]) { - return false; - } - if (src0->nb[0] != sizeof(float) || src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float) || src2->nb[0] != sizeof(int32_t)) { - return false; - } + if ((extra_bufs + n_bufs) > n_bufs_max) return false; + if (check_tens && (extra_tens + n_tens) > n_tens_max) return false; + if ((extra_vmem + b_vmem) > b_vmem_max) return false; - // REVISIT: add support for non-contiguous tensors - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1) || !ggml_is_contiguous(dst)) { - return false; - } - if (src2->nb[1] < src2->ne[0] * sizeof(int32_t)) { - return false; + return true; } - struct htp_binary_kernel_params kparams; - return ggml_hexagon_precompute_binary_params(sess, HTP_OP_ADD_ID, src0, src1, dst, &kparams, src2); -} - -static bool ggml_hexagon_supported_unary(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; + void sync_op_desc(unsigned int n) { + const htp_opnode & node = ops[n]; + htp_op_desc & o = h_ops[n]; - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) { - return false; - } - if (dst->type != src0->type) { - return false; - } - if (!ggml_is_contiguous_rows(src0)) { - return false; - } + memcpy(o.params, node.params, sizeof(o.params)); + memcpy(o.kernel_params, node.kernel_params, sizeof(o.kernel_params)); + o.opcode = node.opcode; - // F16 device kernels only cover this explicit whitelist (must stay in sync with - // the is_f16 whitelist in execute_op_unary(), unary-ops.c). - if (src0->type == GGML_TYPE_F16) { - switch (op->op) { - case GGML_OP_NORM: - case GGML_OP_RMS_NORM: - case GGML_OP_L2_NORM: - case GGML_OP_SCALE: - case GGML_OP_CLAMP: - case GGML_OP_SQR: - case GGML_OP_SQRT: - case GGML_OP_LOG: - break; - case GGML_OP_UNARY: - if (ggml_get_unary_op(op) != GGML_UNARY_OP_ABS && - ggml_get_unary_op(op) != GGML_UNARY_OP_STEP) { - return false; - } - break; - default: - return false; + const auto & inputs = node.get_inputs(); + for (unsigned int i = 0; i < HTP_OP_MAX_INPUTS; i++) { + o.src[i] = (i < inputs.size() && inputs[i]) ? add_tensor(inputs[i]) : 0xffff; } - } - - if (!ggml_are_same_shape(src0, dst)) { - return false; - } - - // dst must be contiguous; src0 may be non-contiguous - if (!ggml_is_contiguous(dst)) { - return false; - } - - return true; - - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_sum(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - if (src0->type != GGML_TYPE_F32) { - return false; - } - if (dst->type != GGML_TYPE_F32) { - return false; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { - return false; - } - - return true; - - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_sum_rows(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - if (src0->type != GGML_TYPE_F32) { - return false; - } - if (dst->type != GGML_TYPE_F32) { - return false; - } - - // TODO: add support for non-contigiuos tensors - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { - return false; - } - - return true; - - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_argmax(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - if (src0->type != GGML_TYPE_F32) { - return false; - } - if (dst->type != GGML_TYPE_I32) { - return false; - } - - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { - return false; + const auto & outputs = node.get_outputs(); + for (unsigned int i = 0; i < HTP_OP_MAX_OUTPUTS; i++) { + o.dst[i] = (i < outputs.size() && outputs[i]) ? add_tensor(outputs[i]) : 0xffff; + } } - return true; - - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_pool_2d(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const int32_t * params = op->op_params; - - if (params[0] != GGML_OP_POOL_AVG && params[0] != GGML_OP_POOL_MAX) { - return false; - } - if (src0->type != GGML_TYPE_F32 || op->type != GGML_TYPE_F32) { - return false; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(op)) { - return false; - } - if (!ggml_hexagon_pool_shape_fits(src0, op)) { - return false; - } + // caller must ensure the op fits + void add_op(const htp_opnode & node) { + unsigned int n = n_ops++; + GGML_ASSERT(n_ops <= n_ops_max); - const int32_t kernel_x = params[1]; - const int32_t kernel_y = params[2]; - const int32_t stride_x = params[3]; - const int32_t stride_y = params[4]; - const int32_t pad_x = params[5]; - const int32_t pad_y = params[6]; + ops[n] = node; + h_ops[n].flags = 0; - // Keep invalid parameters on CPU, avoiding unsafe unsigned values in HTP. - if (kernel_x <= 0 || kernel_y <= 0 || stride_x <= 0 || stride_y <= 0 || - pad_x < 0 || pad_y < 0) { - return false; + ggml_hexagon_dump_op_exec(sess->c_name(), ops[n], h_ops[n].flags); + sync_op_desc(n); } - const uint32_t planes = (uint32_t) (src0->ne[2] * src0->ne[3]); - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, planes > 0 ? planes : 1); - - struct htp_pool_vtcm_layout layout; - return htp_pool_solve_layout(&layout, (uint32_t) src0->ne[0], (uint32_t) src0->ne[1], - (uint32_t) op->ne[0], (uint32_t) op->ne[1], - n_threads, sess->vtcm_size); -} - -static bool ggml_hexagon_supported_pool_1d(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const int32_t * params = op->op_params; - - if (params[0] != GGML_OP_POOL_AVG && params[0] != GGML_OP_POOL_MAX) { - return false; - } - if (src0->type != GGML_TYPE_F32 || op->type != GGML_TYPE_F32) { - return false; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(op)) { - return false; - } - if (!ggml_hexagon_pool_shape_fits(src0, op)) { - return false; - } + void sort_buffers() { + if (n_bufs <= 1) return; - const int32_t kernel = params[1]; - const int32_t stride = params[2]; - const int32_t pad = params[3]; - if (kernel <= 0 || stride <= 0 || pad < 0) { - return false; - } + std::vector order(n_bufs); + for (unsigned int i = 0; i < n_bufs; i++) { order[i] = (int) i; } - const uint32_t planes = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, planes > 0 ? planes : 1); + std::stable_sort(order.begin(), order.end(), [&](int a, int b) { + return h_bufs[a].size > h_bufs[b].size; + }); - struct htp_pool_vtcm_layout layout; - return htp_pool_solve_layout(&layout, (uint32_t) src0->ne[0], 1, (uint32_t) op->ne[0], 1, n_threads, sess->vtcm_size); -} + bool already_sorted = true; + for (unsigned int i = 0; i < n_bufs; i++) { + if (order[i] != (int) i) { + already_sorted = false; + break; + } + } + if (already_sorted) return; -static bool ggml_hexagon_supported_activations(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; + std::vector remap(n_bufs); + std::vector sorted_bufs(n_bufs); + for (unsigned int new_bi = 0; new_bi < n_bufs; new_bi++) { + int old_bi = order[new_bi]; + remap[old_bi] = (uint16_t) new_bi; + sorted_bufs[new_bi] = h_bufs[old_bi]; + } - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) { - return false; - } - if (dst->type != src0->type) { - return false; - } + for (unsigned int i = 0; i < n_bufs; i++) { + h_bufs[i] = sorted_bufs[i]; + } - if (!ggml_is_contiguous_1(src0)) { - return false; - } - if (!ggml_is_contiguous(dst)) { - return false; + for (unsigned int i = 0; i < n_tens; i++) { + h_tens[i].bi = remap[h_tens[i].bi]; + } } - if (src1) { - if (src1->type != src0->type) { - return false; + void update_mdev_group(uint32_t mdev_idx) { + if (n_ops > 0 && h_ops[0].opcode == HTP_OP_MDEV_GROUP) { + h_ops[0].params[0] = (int32_t) mdev_idx; } - if (!ggml_are_same_shape(src0, src1)) { + } + + bool try_fuse(const htp_opnode & node) { + if (n_ops == 0) { return false; } - if (!ggml_is_contiguous_1(src1)) { + + htp_opnode & last_node = ops[n_ops - 1]; + if (!htp_fusion_try_fuse(sess, last_node, node)) { return false; } + + sync_op_desc(n_ops - 1); + HEX_VERBOSE("ggml-hex: %s fused %s (N=%zu, #%u)\n", + sess->c_name(), last_node.name().c_str(), last_node.fused.size() + 1, n_ops - 1); + return true; } +}; - return true; +struct ggml_hexagon_registry { + ggml_hexagon_registry(ggml_backend_reg_t reg); + ~ggml_hexagon_registry(); - GGML_UNUSED(sess); -} + ggml_backend_device devices[GGML_HEXAGON_MAX_SESSIONS]; +}; -static bool ggml_hexagon_supported_softmax(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * dst = op; +struct ggml_hexagon_opqueue { + // Shared buffer for storing batches + ggml_hexagon_shared_buffer *shm_buf; + size_t shm_blk_size; + size_t depth; - if (src2) { - return false; // FIXME: add support for sinks - } + using opvec = std::vector; - if (src0->type != GGML_TYPE_F32) { - return false; - } - if (dst->type != GGML_TYPE_F32) { - return false; - } + std::vector op_cache; // per batch op cache - if (src0->ne[2] > 512) { - return false; - } + ggml_hexagon_opqueue(ggml_hexagon_session *sess, size_t batch_size, size_t depth) : depth(depth) { + size_t n_bufs = HTP_OP_MAX_BUFS; + size_t n_ops = batch_size; + size_t n_tensors = std::min(n_ops * 4 + HTP_OP_MAX_INPUTS + HTP_OP_MAX_OUTPUTS, HTP_OP_MAX_TENSORS); - if (src1) { - if (src1->type != GGML_TYPE_F32 && src1->type != GGML_TYPE_F16) { - return false; - } - if (src0->ne[0] != src1->ne[0]) { - return false; - } - if (src1->ne[1] < src0->ne[1]) { - return false; - } - if (src0->ne[2] % src1->ne[2] != 0) { - return false; - } - if (src0->ne[3] % src1->ne[3] != 0) { - return false; + size_t tr_size = 0; + if (opt_profile == 3) { + tr_size = (HTP_MAX_NTHREADS + 1) * opt_optrace * sizeof(htp_trace_desc); } - } - if (src1) { - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1) || !ggml_is_contiguous(dst)) { - return false; - } - } else { - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { - return false; + shm_blk_size = sizeof(htp_buf_desc) * n_bufs + + sizeof(htp_tensor) * n_tensors + + sizeof(htp_op_desc) * n_ops + + sizeof(htp_prof_desc) * n_ops + + tr_size; + + shm_buf = new ggml_hexagon_shared_buffer(sess, shm_blk_size * depth, true /* pinned */); + + op_cache.resize(depth); + + if (opt_verbose) { + GGML_LOG_INFO("ggml-hex: %s allocated opqueue : batch-size %zu depth %zu shm-size %zu shm-block-size %zu\n", + sess->c_name(), batch_size, depth, shm_buf->size(), shm_blk_size); } } - // Reject non-HVX-aligned sizes when ne[0] > HVX_F32_LANES - // The HVX softmax implementation has issues with tail handling for larger non-aligned sizes - // Small sizes (ne[0] <= 32) work correctly with tail-only processing - const int64_t ne0 = src0->ne[0]; - if (ne0 > 32 && (ne0 & (32 - 1)) != 0) { - return false; + ~ggml_hexagon_opqueue() { + delete shm_buf; } - // HVX vector size constraints for softmax - #define SOFTMAX_MAX_ROW_SIZE 131072 // 128K elements max for numerical precision + size_t shm_size() const { return shm_buf ? shm_buf->size() : 0; } - // Reject very large row sizes to avoid numerical precision issues - // Softmax accumulation over many elements can lead to precision loss - if (ne0 > SOFTMAX_MAX_ROW_SIZE) { - return false; - } + // push new batch + bool push(htp_opbatch_req& req, dspqueue_buffer& dbuf, const ggml_hexagon_opbatch* op_batch, uint64_t seq) { + static_assert(sizeof(htp_opbatch_req) % 8 == 0, "sizeof(htp_opbatch_req) must be multiple of 8"); + static_assert(sizeof(htp_opbatch_rsp) % 8 == 0, "sizeof(htp_opbatch_rsp) must be multiple of 8"); + static_assert(sizeof(htp_buf_desc) % 8 == 0, "sizeof(htp_buf_desc) must be multiple of 8"); + static_assert(sizeof(htp_tensor) % 8 == 0, "sizeof(htp_tensor) must be multiple of 8"); + static_assert(sizeof(htp_op_desc) % 8 == 0, "sizeof(htp_op_desc) must be multiple of 8"); + static_assert(sizeof(htp_prof_desc) % 8 == 0, "sizeof(htp_prof_desc) must be multiple of 8"); - const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, src0_nrows); - struct htp_softmax_vtcm_layout layout; - htp_softmax_vtcm_layout_build(&layout, src0->ne[0], src1 ? src1->ne[0] : 1, src1 != nullptr, src1 && src1->type == GGML_TYPE_F16, n_threads); - if (layout.total_bytes > sess->vtcm_size) { - return false; - } + if (seq - shm_buf->sess->batch_rsp_seq > depth) { return false; } - return true; + const uint32_t slot = (uint32_t) ((seq - 1) % depth); - GGML_UNUSED(sess); -} + req.seq = seq; + req.n_bufs = op_batch->n_bufs; + req.n_tensors = op_batch->n_tens; + req.n_ops = op_batch->n_ops; -static bool ggml_hexagon_supported_set_rows(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; // values - const struct ggml_tensor * src1 = op->src[1]; // indices - const struct ggml_tensor * dst = op->src[2] ? op->src[2] : op; + if (opt_profile) { + op_cache[slot].assign(op_batch->ops.begin(), op_batch->ops.begin() + req.n_ops); + } - if (dst->type == GGML_TYPE_Q8_0 && src0->ne[0] < 32) { - return false; - } + const size_t b_size = sizeof(htp_buf_desc) * req.n_bufs; + const size_t t_size = sizeof(htp_tensor) * req.n_tensors; + const size_t o_size = sizeof(htp_op_desc) * req.n_ops; + const size_t p_size = sizeof(htp_prof_desc) * req.n_ops; - if (src0->type != GGML_TYPE_F32) { - return false; - } + size_t tr_size = 0; + if (opt_profile == 3) { + req.n_traces = opt_optrace; + tr_size = (HTP_MAX_NTHREADS + 1) * req.n_traces * sizeof(htp_trace_desc); + } else { + req.n_traces = 0; + } - if (src1->type != GGML_TYPE_I32 && src1->type != GGML_TYPE_I64) { - return false; - } + dbuf.ptr = shm_buf->base() + ((size_t) slot * shm_blk_size); + dbuf.fd = shm_buf->fd(); + dbuf.flags = DSPQUEUE_BUFFER_FLAG_FLUSH_SENDER | DSPQUEUE_BUFFER_FLAG_INVALIDATE_RECIPIENT; + dbuf.offset = (uint8_t*) dbuf.ptr - (uint8_t*) shm_buf->base(); + dbuf.size = b_size + t_size + o_size + p_size + tr_size; - if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_Q8_0) { - return false; - } + GGML_ASSERT(dbuf.size <= shm_blk_size); - return true; + uint8_t * m_ptr = (uint8_t*) dbuf.ptr; + uint8_t * b_ptr = m_ptr; m_ptr += b_size; + uint8_t * t_ptr = m_ptr; m_ptr += t_size; + uint8_t * o_ptr = m_ptr; - GGML_UNUSED(sess); -} + memcpy(b_ptr, (void *) op_batch->h_bufs.data(), b_size); + memcpy(t_ptr, (void *) op_batch->h_tens.data(), t_size); + memcpy(o_ptr, (void *) op_batch->h_ops.data(), o_size); + + HEX_VERBOSE("ggml-hex: %s opqueue-push batch #%llu : n-bufs %u n-tensors %u n-ops %u vmem %zu : b-size %zu t-size %zu o-size %zu m-size %zu\n", + shm_buf->sess->c_name(), (unsigned long long) req.seq, req.n_bufs, req.n_tensors, req.n_ops, op_batch->b_vmem, + b_size, t_size, o_size, (size_t) dbuf.size); -static bool ggml_hexagon_supported_get_rows(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; // values - const struct ggml_tensor * src1 = op->src[1]; // indices - const struct ggml_tensor * dst = op; + if (opt_verbose > 1) { + htp_buf_desc *b = (htp_buf_desc*) b_ptr; + for (unsigned int i=0; i < req.n_bufs; i++) { + GGML_LOG_DEBUG("ggml-hex: %s htp-buf #%u : fd %d base %p size %zu\n", shm_buf->sess->c_name(), i, + b[i].fd, (void *) b[i].base, (size_t) b[i].size); + } + htp_tensor *t = (htp_tensor*) t_ptr; + for (unsigned int i=0; i < req.n_tensors; i++) { + GGML_LOG_DEBUG("ggml-hex: %s htp-tensor #%u : bi %u offset %llu size %u : %zu:%zu:%zu:%zu\n", + shm_buf->sess->c_name(), i, t[i].bi, (unsigned long long) t[i].data, t[i].size, + (size_t) t[i].ne[0], (size_t) t[i].ne[1], (size_t) t[i].ne[2], (size_t) t[i].ne[3]); + } + } - if ((src0->type == GGML_TYPE_Q4_0 || src0->type == GGML_TYPE_Q4_K || src0->type == GGML_TYPE_Q6_K) && src0->view_src) { - return false; + return true; } - const ggml_tensor * src0_base = src0->view_src ? src0->view_src : src0; - bool is_repacked = false; - if (src0_base->buffer && ggml_backend_buffer_is_hexagon(src0_base->buffer) && src0_base->extra) { - const auto * extra = (const ggml_hexagon_tensor_extra *) src0_base->extra; - is_repacked = (extra->flags & GGML_HEXAGON_TENSOR_REPACK) != 0; - if (is_repacked && src0->type != GGML_TYPE_Q4_0 && src0->type != GGML_TYPE_Q4_K && src0->type != GGML_TYPE_Q6_K && src0->type != GGML_TYPE_Q8_0) { - return false; + void pop(htp_opbatch_rsp rsp, dspqueue_buffer dbuf) { + const uint32_t slot = (uint32_t) ((rsp.seq - 1) % depth); + + const size_t b_size = sizeof(htp_buf_desc) * rsp.n_bufs; + const size_t t_size = sizeof(htp_tensor) * rsp.n_tensors; + const size_t o_size = sizeof(htp_op_desc) * rsp.n_ops; + const size_t p_size = sizeof(htp_prof_desc) * rsp.n_ops; + + size_t tr_size = 0; + uint32_t n_traces = 0; + if (opt_profile == 3) { + n_traces = opt_optrace; + tr_size = (HTP_MAX_NTHREADS + 1) * n_traces * sizeof(htp_trace_desc); } - } - is_repacked = is_repacked || sess->needs_repack.count(src0_base) || sess->needs_repack.count(src0); - // View offsets use the raw quantized layout and cannot address a tiled allocation. - if (src0->view_src && is_repacked) { - return false; - } + const size_t m_size = b_size + t_size + o_size + p_size + tr_size; + GGML_ASSERT(m_size <= shm_blk_size); - if ((src0->type == GGML_TYPE_Q4_0 || src0->type == GGML_TYPE_Q4_K || src0->type == GGML_TYPE_Q6_K) && src0->buffer && ggml_backend_buffer_get_size(src0->buffer) != 0 && !is_repacked) { - return false; - } + HEX_VERBOSE("ggml-hex: %s opqueue-pop batch #%llu : n-bufs %u n-tensors %u n-ops %u : m-size %zu b-size %zu t-size %zu o-size %zu\n", + shm_buf->sess->c_name(), (unsigned long long) rsp.seq, rsp.n_bufs, rsp.n_tensors, rsp.n_ops, + (size_t) dbuf.size, b_size, t_size, o_size); - if (src0->type != dst->type && src0->ne[0] < 32) { - return false; - } + uint8_t * m_ptr = (uint8_t*) dbuf.ptr; + uint8_t * p_ptr = m_ptr + (b_size + t_size + o_size); - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16 && - src0->type != GGML_TYPE_Q4_0 && src0->type != GGML_TYPE_Q4_K && src0->type != GGML_TYPE_Q6_K && src0->type != GGML_TYPE_Q8_0 && src0->type != GGML_TYPE_I32) { - return false; - } + if (rsp.n_ops > 0 && opt_profile) { + auto & ops = op_cache[slot]; + GGML_ASSERT(rsp.n_ops <= ops.size()); - if ((src0->type == GGML_TYPE_Q4_K || src0->type == GGML_TYPE_Q6_K) && (!ggml_is_contiguous(src0) || ggml_is_permuted(src0) || src0->ne[0] % QK_K)) { - return false; - } + const htp_prof_desc * pd = (const htp_prof_desc *) p_ptr; + const htp_trace_desc * trace_events = nullptr; + if (opt_profile == 3) { + trace_events = (const htp_trace_desc *) (p_ptr + p_size); + } - if (src1->type != GGML_TYPE_I32 && src1->type != GGML_TYPE_I64) { - return false; - } + ggml_hexagon_dump_batch_prof(shm_buf->sess->c_name(), rsp); - if (src0->type == dst->type) { - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_I32 && src0->type != GGML_TYPE_F16) { - return false; + for (uint32_t i = 0; i < rsp.n_ops; i++) { + ggml_hexagon_dump_op_prof(shm_buf->sess->c_name(), ops[i], pd[i]); + } + + ggml_hexagon_dump_trace_events(shm_buf->sess->c_name(), rsp, trace_events, n_traces); } - } else if (src0->type == GGML_TYPE_I32) { - return false; - } else if (dst->type != GGML_TYPE_F32) { - return false; } +}; - // Empty recurrent-state gathers are skipped at execution; do not split the graph for them. - if (ggml_is_empty(op)) { - return true; +void ggml_hexagon_session::flush_peers() { + auto vpeers = std::move(virt_peers); + virt_peers.clear(); + for (auto * peer : vpeers) { + peer->flush_sync(); } - struct htp_get_rows_kernel_params kparams; - ggml_hexagon_precompute_get_rows_params(sess, src0, src1, dst, &kparams); - if (kparams.n_threads == 0 || (size_t) kparams.vtcm_size > sess->vtcm_size) { - return false; + auto ppeers = std::move(phys_peers); + phys_peers.clear(); + for (auto * peer : ppeers) { + peer->flush_async(); } - // Tiled quantized weights have no raw fallback. Mark only accepted tensors for repacking. - if ((src0->type == GGML_TYPE_Q4_0 || src0->type == GGML_TYPE_Q4_K || src0->type == GGML_TYPE_Q6_K) && !src0->buffer) { - sess->needs_repack.insert(src0); + for (auto & sub : this->mdev.sessions) { + sub->flush_peers(); } - - return true; - - GGML_UNUSED(sess); } -static bool ggml_hexagon_supported_argsort(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; // values - const struct ggml_tensor * dst = op; // indices +void ggml_hexagon_session::flush_async() { + flush_peers(); + flush_batch(); +} - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_I32) { - return false; +void ggml_hexagon_session::flush_pending(bool all) { + for (auto & sub : this->mdev.sessions) { + sub->flush_pending(all); + if (sub->last_error > HTP_STATUS_OK) { + this->last_error = sub->last_error.load(); + } } - const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads_max = sess->n_threads > 0 ? sess->n_threads : 4; - const size_t vtcm_budget = sess->vtcm_size > 0 ? sess->vtcm_size : (8 * 1024 * 1024); + while (this->batch_rsp_seq < this->batch_req_seq) { + struct htp_opbatch_rsp rsp; + uint32_t rsp_size; + uint32_t flags; - struct htp_sort_vtcm_layout layout; - if (!htp_sort_solve_layout(&layout, src0->ne[0], total_rows, dst->ne[0], n_threads_max, vtcm_budget, false)) { - return false; - } + struct dspqueue_buffer dbuf; + uint32_t n_dbufs; - return true; -} + // Read response packet from queue + const uint32_t timeo = opt_oppoll ? 0 : DSPQUEUE_TIMEOUT; -static bool ggml_hexagon_supported_top_k(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; // values - const struct ggml_tensor * dst = op; // indices + int err = dspqueue_read(this->queue, &flags, 1, &n_dbufs, &dbuf, sizeof(rsp), &rsp_size, (uint8_t *) &rsp, timeo); + if (err == AEE_EEXPIRED || err == AEE_EWOULDBLOCK) { + continue; + } - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_I32) { - return false; - } + if (err != 0) { + GGML_ABORT("ggml-hex: dspqueue_read failed: 0x%08x\n", (unsigned) err); + } - const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const uint32_t n_threads_max = sess->n_threads > 0 ? sess->n_threads : 4; - const size_t vtcm_budget = sess->vtcm_size > 0 ? sess->vtcm_size : (8 * 1024 * 1024); + // Basic sanity checks + if (rsp_size != sizeof(rsp) || n_dbufs != 1) { + GGML_ABORT("ggml-hex: %s dspcall : bad response : size %u dspbufs %u\n", this->c_name(), rsp_size, n_dbufs); + } - struct htp_sort_vtcm_layout layout; - if (!htp_sort_solve_layout(&layout, src0->ne[0], total_rows, dst->ne[0], n_threads_max, vtcm_budget, true)) { - return false; - } + if (rsp.status > HTP_STATUS_OK) { + GGML_LOG_ERROR("ggml-hex: %s dspcall : dsp-rsp %s\n", this->c_name(), status_to_str(rsp.status)); + this->last_error = rsp.status; + for (auto & sub : this->mdev.sessions) { + sub->last_error = rsp.status; + } + } - return true; -} + op_queue->pop(rsp, dbuf); -static bool ggml_hexagon_supported_rope(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * src2 = op->src[2]; - const struct ggml_tensor * dst = op; + GGML_ASSERT(rsp.seq == this->batch_rsp_seq + 1); + this->batch_rsp_seq = rsp.seq; - if (!ggml_are_same_shape(src0, dst)) { - return false; + if (!all) break; } +} - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_I32) { - return false; - } +void ggml_hexagon_session::flush_sync(bool all) { + flush_async(); + flush_pending(all); +} - if (src0->ne[0] <= 0) { - return false; +void ggml_hexagon_session::start_batch() { + if (this->mdev.count > 1) { + enqueue_mdev_group(); } +} - const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - if (src0_nrows == 0) { - return false; - } +void ggml_hexagon_session::flush_batch(size_t min_ops) { + if (op_batch->n_ops < min_ops) { return; } - const int32_t * op_params = &op->op_params[0]; - const int n_dims = op_params[1]; - const int mode = op_params[2]; - const int n_offs = op_params[15]; + op_batch->sort_buffers(); - // llama probes weight placement with a dummy rope where every param is 0 (llama-model-loader.cpp). - // Rejecting it puts rope_freqs on the CPU, which then splits the graph at every full-attention layer. - if (n_dims < 0 || n_dims % 2 != 0) { - return false; - } + htp_opbatch_req req {}; + dspqueue_buffer dbuf{}; - // ggml_rope_set_offset: HVX kernels need a VLEN-aligned window start (32 f32 elems) - if (n_offs < 0 || (n_offs % 32 != 0) || (n_offs + n_dims > src0->ne[0])) { - return false; - } + const uint64_t seq = ++this->batch_req_seq; - float freq_base; - memcpy(&freq_base, op_params + 5, sizeof(float)); - if (freq_base < 0.0f) { - return false; - } + op_batch->update_mdev_group(this->mdev.idx); - if (mode != GGML_ROPE_TYPE_NORMAL && - mode != GGML_ROPE_TYPE_NEOX && - mode != GGML_ROPE_TYPE_MROPE && - mode != GGML_ROPE_TYPE_VISION && - mode != GGML_ROPE_TYPE_IMROPE) { - return false; + if (!op_queue->push(req, dbuf, op_batch, seq)) { + flush_pending(false); + op_queue->push(req, dbuf, op_batch, seq); } - const bool is_mrope = (mode & GGML_ROPE_TYPE_MROPE) != 0; + for (auto & sub : this->mdev.sessions) { + htp_opbatch_req sub_req {}; + dspqueue_buffer sub_dbuf{}; - // n_dims == ne0/2, so the rotation spans the full row - if (mode == GGML_ROPE_TYPE_VISION) { - if (n_dims != (int) (src0->ne[0] / 2) || n_offs != 0) { - return false; - } - } + sub->batch_req_seq = seq; + op_batch->update_mdev_group(sub->mdev.idx); - if (is_mrope) { - const int32_t * sections = op_params + 11; - if (sections[0] <= 0 && sections[1] <= 0 && sections[2] <= 0) { - return false; + if (!sub->op_queue->push(sub_req, sub_dbuf, op_batch, seq)) { + sub->flush_pending(false); + sub->op_queue->push(sub_req, sub_dbuf, op_batch, seq); } - } - const int64_t min_pos_len = (is_mrope || mode == GGML_ROPE_TYPE_VISION) ? src0->ne[2] * 4 : src0->ne[2]; - if (src1->ne[0] < min_pos_len || !ggml_is_contiguous(src1)) { - return false; - } + HEX_VERBOSE("ggml-hex: %s queue-opbatch: %p size %u\n", sub->c_name(), sub_dbuf.ptr, sub_dbuf.size); - if (src2) { - if (src2->type != GGML_TYPE_F32 || !ggml_is_contiguous(src2)) { - return false; - } - if (src2->ne[0] < (n_dims / 2)) { - return false; + int err = dspqueue_write(sub->queue, 0, 1, &sub_dbuf, sizeof(sub_req), (const uint8_t*) &sub_req, DSPQUEUE_TIMEOUT); + if (err != 0) { + GGML_ABORT("ggml-hex: %s dspqueue_write failed: 0x%08x\n", sub->c_name(), (unsigned) err); } } - // src0/dst elements within a row must be contiguous (nb[0] == sizeof(float)). - // nb[1] may exceed ne[0]*sizeof(float) when the tensor is a strided view of a larger one - if (src0->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float)) { - return false; - } - if (src0->nb[1] < src0->ne[0] * sizeof(float) || dst->nb[1] < dst->ne[0] * sizeof(float)) { - return false; - } - - const uint32_t n_threads = (std::min)((uint32_t) sess->n_threads, src0_nrows); - const uint32_t n_freq_factors = src2 ? (uint32_t) src2->ne[0] : 0; + HEX_VERBOSE("ggml-hex: %s queue-opbatch: %p size %u\n", this->c_name(), dbuf.ptr, dbuf.size); - struct htp_rope_vtcm_layout layout; - htp_rope_vtcm_layout_build(&layout, src0->ne[0], n_threads, n_freq_factors); - if (layout.total_bytes > sess->vtcm_size) { - return false; + int err = dspqueue_write(this->queue, 0, 1, &dbuf, sizeof(req), (const uint8_t*) &req, DSPQUEUE_TIMEOUT); + if (err != 0) { + GGML_ABORT("ggml-hex: %s dspqueue_write failed: 0x%08x\n", this->c_name(), (unsigned) err); } - return true; + op_batch->reset(); } -static bool ggml_hexagon_supported_ssm_conv(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; +void ggml_hexagon_session::enqueue_op(const htp_opnode & node) { + auto clone_tensor_buffer = [this](const ggml_tensor * t) { + auto sbuf = this->mmap_tensor(t); + if (!sbuf) return; + if (sbuf->sess != this) { + this->clone_buffer(sbuf); + } + for (auto & sub : this->mdev.sessions) { + sub->clone_buffer(sbuf); + } + }; - // the channels-major input layout is only implemented on CPU/CUDA - if (ggml_ssm_conv_get_layout(op) != GGML_SSM_CONV_LAYOUT_TIME_MAJOR) { - return false; + for (auto t : node.get_inputs()) { + clone_tensor_buffer(t); } - - // Only support FP32 for now - if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; + for (auto t : node.get_outputs()) { + clone_tensor_buffer(t); } - // Check IO tensor shapes and dims - if (src0->ne[3] != 1 || src1->ne[2] != 1 || src1->ne[3] != 1 || dst->ne[3] != 1) { - return false; // src0 should be effectively 3D + const bool fits_tensors = op_batch->fit_tensors(node); + if (opt_opfusion && fits_tensors && op_batch->try_fuse(node)) { + return; } - const int d_conv = src1->ne[0]; - const int d_inner = src0->ne[1]; - const int n_t = dst->ne[1]; - const int n_s = dst->ne[2]; - - if (d_conv == 0 || d_conv > 32 || d_inner == 0) { - return false; - } - if (src0->ne[0] != d_conv - 1 + n_t || src0->ne[1] != d_inner || src0->ne[2] != n_s) { - return false; - } - if (src1->ne[0] != d_conv || src1->ne[1] != d_inner) { - return false; - } - if (dst->ne[0] != d_inner || dst->ne[1] != n_t || dst->ne[2] != n_s) { - return false; - } - if (src0->nb[0] != sizeof(float) || src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float)) { - return false; - } - if (src0->nb[1] != src0->ne[0] * sizeof(float) || src1->nb[1] != src1->ne[0] * sizeof(float)) { - return false; + if (op_batch->full() || !fits_tensors) { + flush_async(); } - struct htp_ssm_conv_kernel_params kparams; - ggml_hexagon_precompute_ssm_conv_params(sess, src0, src1, dst, &kparams); - if ((size_t) kparams.vtcm_size > sess->vtcm_size) { - return false; + if (op_batch->empty()) { + start_batch(); + if (!op_batch->fit_tensors(node)) { + GGML_ABORT("ggml-hex: %s op does not fit into empty batch (vmem/tensor/buffer limit exceeded)\n", c_name()); + } } - return true; + op_batch->add_op(node); } -static bool im2col_3d_calc_output_size(uint32_t input, uint32_t kernel, int32_t stride, int32_t padding, - int32_t dilation, uint32_t * output) { - if (stride <= 0 || padding < 0 || dilation <= 0 || kernel == 0) { - return false; - } +void ggml_hexagon_session::enqueue_mdev_group() { + htp_opnode group_node(HTP_OP_MDEV_GROUP); - const int64_t numerator = (int64_t) input + 2LL * padding - (int64_t) dilation * (kernel - 1) - 1; - if (numerator < 0) { - return false; - } + ggml_tensor dummy_t = make_fence_tensor(this->mdev_fence_slot, this->mdev.count); + dummy_t.op_params[0] = (int32_t) this->mdev.idx; - const uint64_t size = (uint64_t) (numerator / stride) + 1; - if (size == 0 || size > UINT32_MAX) { - return false; + ggml_tensor * node = group_node.add_dummy(dummy_t); + node->src[0] = node; + group_node.init(node); + group_node.outputs.clear(); + + for (auto & sub : this->mdev.sessions) { + sub->clone_buffer(this->fence_buf); } - *output = (uint32_t) size; - return true; + op_batch->add_op(group_node); } -static bool ggml_hexagon_precompute_im2col_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_im2col_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->kernel_type = HTP_IM2COL_KERNEL_UNSUPPORTED; - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; +void ggml_hexagon_session::enqueue_cpy(const ggml_tensor * src, ggml_tensor * dst, const ggml_tensor * sync_tensor, uint32_t fence_seq) { + const bool with_fence = sync_tensor != nullptr; + htp_opnode cpy_node(with_fence ? HTP_OP_CPY_FENCE : HTP_OP_CPY); - if (!src0 || !src1 || !dst) { - return false; + ggml_tensor* node = cpy_node.add_dummy(*dst); + node->op = GGML_OP_CPY; + node->src[0] = const_cast(src); + node->src[1] = with_fence ? cpy_node.add_dummy(*sync_tensor) : nullptr; + if (with_fence) { + node->op_params[0] = (int32_t) fence_seq; } - if (src1->type != GGML_TYPE_F32 || (dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_F32)) { - return false; + cpy_node.init(node); + const bool ok = htp_kparams_solve(this, node, cpy_node.kernel_params); + if (ok && !with_fence && cpy_node.kparams()->total_elems == 0) { + return; } + this->enqueue_op(cpy_node); +} - if (src1->nb[0] != sizeof(float) || !ggml_is_contiguous(dst)) { - return false; - } +void ggml_hexagon_session::enqueue_fence(const ggml_tensor * sync_tensor, uint32_t fence_seq, bool wait) { + htp_opnode sync_node(HTP_OP_FENCE); - const int32_t * op_params = (const int32_t *) op->op_params; - const int32_t s0 = op_params[0]; - const int32_t s1 = op_params[1]; - const int32_t p0 = op_params[2]; - const int32_t p1 = op_params[3]; - const int32_t d0 = op_params[4]; - const int32_t d1 = op_params[5]; - const bool is_2D = (op_params[6] == 1); + ggml_tensor* node = sync_node.add_dummy(*sync_tensor); + node->op = GGML_OP_NONE; + node->src[0] = node; + node->op_params[0] = (int32_t) fence_seq; + node->op_params[1] = wait ? 0 : 1; - if (s0 <= 0 || d0 <= 0 || p0 < 0) { - return false; - } - if (is_2D && (s1 <= 0 || d1 <= 0 || p1 < 0)) { - return false; - } + sync_node.init(node); + this->enqueue_op(sync_node); +} - const uint32_t N = is_2D ? (uint32_t) src1->ne[3] : (uint32_t) src1->ne[2]; - const uint32_t IC = is_2D ? (uint32_t) src1->ne[2] : (uint32_t) src1->ne[1]; - const uint32_t IH = is_2D ? (uint32_t) src1->ne[1] : 1; - const uint32_t IW = (uint32_t) src1->ne[0]; - const uint32_t KH = is_2D ? (uint32_t) src0->ne[1] : 1; - const uint32_t KW = (uint32_t) src0->ne[0]; - const uint32_t OH = is_2D ? (uint32_t) dst->ne[2] : 1; - const uint32_t OW = (uint32_t) dst->ne[1]; +void ggml_hexagon_session::enqueue_allreduce( + const ggml_tensor * dst, + const std::vector & src_tensors, + const std::vector & sync_tensors, + uint32_t rank, + uint32_t n_ranks, + uint32_t fence_seq_entry, + uint32_t fence_seq_exit +) { + htp_opnode ar_node(HTP_OP_ALLREDUCE); - if (KW == 0 || KH == 0 || IW == 0 || IH == 0 || IC == 0 || OW == 0 || OH == 0 || N == 0) { - return false; - } + ggml_tensor* node = ar_node.add_dummy(*dst); + node->op = GGML_OP_NONE; + node->op_params[0] = (int32_t) fence_seq_entry; + node->op_params[1] = (int32_t) fence_seq_exit; - const uint64_t patch_stride_64 = (uint64_t) IC * KH * KW; - const uint64_t total_rows_64 = (uint64_t) N * OH; - if (patch_stride_64 > UINT32_MAX || total_rows_64 > UINT32_MAX) { - return false; - } - const uint32_t patch_stride = (uint32_t) patch_stride_64; - const uint32_t total_rows = (uint32_t) total_rows_64; + ar_node.init(node); - if (dst->ne[0] != patch_stride || dst->ne[1] != OW) { - return false; + ar_node.inputs.clear(); + for (size_t i = 0; i < src_tensors.size(); i++) { + ar_node.inputs.push_back(src_tensors[i]); } - if (is_2D && dst->ne[2] != OH) { - return false; + for (size_t i = 0; i < sync_tensors.size(); i++) { + ar_node.inputs.push_back(ar_node.add_dummy(*sync_tensors[i])); } - const uint32_t dst_elem = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); - - bool is_patchembed = ggml_is_contiguous(src1) && (s0 == (int32_t) KW && p0 == 0 && d0 == 1); - if (is_2D) { - is_patchembed = is_patchembed && (s1 == (int32_t) KH && p1 == 0 && d1 == 1); - } - - const uint32_t max_threads = (sess && sess->n_threads > 0) ? (uint32_t) sess->n_threads : 8; - const uint32_t n_threads = (total_rows < max_threads) ? total_rows : max_threads; - const uint32_t vtcm_size = (sess && sess->vtcm_size > 0) ? sess->vtcm_size : 0; - - if (is_patchembed) { - const uint64_t src_row_bytes_raw = (uint64_t) IC * KH * IW * sizeof(float); - const uint64_t dst_row_bytes_raw = (uint64_t) OW * patch_stride * dst_elem; - if (src_row_bytes_raw <= UINT32_MAX && dst_row_bytes_raw <= UINT32_MAX) { - const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); - const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); - - struct htp_im2col_vtcm_layout layout; - htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads); - - if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { - kparams->kernel_type = HTP_IM2COL_KERNEL_PATCHEMBED_DMA; - kparams->is_2d = is_2D ? 1 : 0; - kparams->is_3d = 0; - kparams->n_threads = (uint8_t) n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->off_src = layout.off_src; - kparams->off_dst = layout.off_dst; - kparams->src_bytes_per_thread = layout.src_bytes_per_thread; - kparams->dst_bytes_per_thread = layout.dst_bytes_per_thread; - kparams->src_row_bytes = src_row_bytes; - kparams->dst_row_bytes = dst_row_bytes; - kparams->owb = OW; - kparams->wb = IW; - kparams->nbpr = 1; - kparams->N = N; - kparams->IC = IC; - kparams->ID = 1; - kparams->IH = IH; - kparams->IW = IW; - kparams->KD = 1; - kparams->KH = KH; - kparams->KW = KW; - kparams->OD = 1; - kparams->OH = OH; - kparams->OW = OW; - kparams->patch_stride = patch_stride; - kparams->total_rows = total_rows; - return true; - } - } + ar_node.outputs.clear(); + for (size_t i = 0; i < src_tensors.size(); i++) { + ar_node.outputs.push_back(src_tensors[i]); } - for (uint32_t owb = (OW < 256 ? OW : 256); owb >= 1; owb--) { - const uint64_t Wb = (uint64_t) (owb - 1) * s0 + (uint64_t) (KW - 1) * d0 + 1; - if (Wb > UINT32_MAX) { - if (owb == 1) break; - continue; - } - - const uint64_t src_row_bytes_raw = (uint64_t) IC * KH * Wb * sizeof(float); - const uint64_t dst_row_bytes_raw = (uint64_t) owb * patch_stride * dst_elem; - if (src_row_bytes_raw > UINT32_MAX || dst_row_bytes_raw > UINT32_MAX) { - if (owb == 1) break; - continue; - } - - const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); - const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); - - struct htp_im2col_vtcm_layout layout; - htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads); - - if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { - kparams->kernel_type = HTP_IM2COL_KERNEL_BLOCKED_DMA; - kparams->is_2d = is_2D ? 1 : 0; - kparams->is_3d = 0; - kparams->n_threads = (uint8_t) n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->off_src = layout.off_src; - kparams->off_dst = layout.off_dst; - kparams->src_bytes_per_thread = layout.src_bytes_per_thread; - kparams->dst_bytes_per_thread = layout.dst_bytes_per_thread; - kparams->src_row_bytes = src_row_bytes; - kparams->dst_row_bytes = dst_row_bytes; - kparams->owb = owb; - kparams->wb = (uint32_t) Wb; - kparams->nbpr = (OW + owb - 1) / owb; - kparams->N = N; - kparams->IC = IC; - kparams->ID = 1; - kparams->IH = IH; - kparams->IW = IW; - kparams->KD = 1; - kparams->KH = KH; - kparams->KW = KW; - kparams->OD = 1; - kparams->OH = OH; - kparams->OW = OW; - kparams->patch_stride = patch_stride; - kparams->total_rows = total_rows; - return true; - } - if (owb == 1) break; - } + htp_kparams_solve_allreduce( + this, dst, rank, n_ranks, false, false, /*is_shard_ok=*/ false, + ar_node.kparams()); - return false; + this->enqueue_op(ar_node); } -static bool ggml_hexagon_precompute_im2col_3d_params( - const struct ggml_hexagon_session * sess, - const struct ggml_tensor * op, - struct htp_im2col_kernel_params * kparams -) { - memset(kparams, 0, sizeof(*kparams)); - kparams->kernel_type = HTP_IM2COL_KERNEL_UNSUPPORTED; - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * src1 = op->src[1]; - const struct ggml_tensor * dst = op; +ggml_hexagon_shared_buffer * ggml_hexagon_session::mmap_tensor(const ggml_tensor * t) { + if (!t) return nullptr; - if (!src0 || !src1 || !dst) { - return false; + auto sbuf = static_cast(t->buffer->context); + if (!sbuf->mapped) { + const bool is_weight = ggml_backend_buffer_get_usage(t->buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS; + const bool extended = opt_dma64 && is_weight; + sbuf->mmap(extended); } + return sbuf; +} - if (src1->type != GGML_TYPE_F32 || (dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_F32)) { - return false; - } +bool ggml_hexagon_session::clone_buffer(const ggml_hexagon_shared_buffer * sbuf) +{ + GGML_ASSERT(sbuf && sbuf->mem); + if (sbuf->sess == this) return true; - if (src1->nb[0] != sizeof(float) || !ggml_is_contiguous(dst)) { - return false; - } + auto mem = sbuf->mem; + int fd = mem->fd; - const int32_t * params = (const int32_t *) op->op_params; - const int32_t s0 = params[0], s1 = params[1], s2 = params[2]; - const int32_t p0 = params[3], p1 = params[4], p2 = params[5]; - const int32_t d0 = params[6], d1 = params[7], d2 = params[8]; - const int32_t ic = params[9]; + GGML_ASSERT(fd >= 0); - if (s0 <= 0 || s1 <= 0 || s2 <= 0 || - p0 < 0 || p1 < 0 || p2 < 0 || - d0 <= 0 || d1 <= 0 || d2 <= 0 || ic <= 0) { - return false; - } + if (this->cloned_buffers.find(fd) != this->cloned_buffers.end()) return true; - if (src1->ne[3] % ic != 0) { - return false; - } + GGML_ASSERT(sbuf->mapped); - const uint32_t IC = (uint32_t) ic; - const uint32_t N = (uint32_t) (src1->ne[3] / IC); - if (N == 0) { - return false; - } + HEX_VERBOSE("ggml-hex: %s clone-buffer: %s base %p size %zu fd %d\n", this->name.c_str(), + sbuf->c_name(), sbuf->base(), sbuf->size(), fd); - uint32_t OW, OH, OD; - if (!im2col_3d_calc_output_size(src1->ne[0], src0->ne[0], s0, p0, d0, &OW) || - !im2col_3d_calc_output_size(src1->ne[1], src0->ne[1], s1, p1, d1, &OH) || - !im2col_3d_calc_output_size(src1->ne[2], src0->ne[2], s2, p2, d2, &OD)) { + auto clone = std::make_unique(this, *sbuf); + try { + clone->mmap(sbuf->extended); + } catch (const std::exception & exc) { + GGML_LOG_ERROR("ggml-hex: %s lazy mapping of buffer context failed: %s\n", this->c_name(), exc.what()); return false; } - const uint32_t KD = (uint32_t) src0->ne[2]; - const uint32_t KH = (uint32_t) src0->ne[1]; - const uint32_t KW = (uint32_t) src0->ne[0]; - const uint32_t ID = (uint32_t) src1->ne[2]; - const uint32_t IH = (uint32_t) src1->ne[1]; - const uint32_t IW = (uint32_t) src1->ne[0]; + this->cloned_buffers[fd] = std::move(clone); + mem->mapped_clones.insert(this); + return true; +} - const uint64_t patch_stride_64 = (uint64_t) IC * KD * KH * KW; - const uint64_t total_rows_64 = (uint64_t) N * OD * OH; - const uint64_t dst_ne3_64 = (uint64_t) OD * N; +void ggml_hexagon_session::release_buffer(const ggml_hexagon_shared_buffer * sbuf) { + GGML_ASSERT(sbuf && sbuf->mem); - if (patch_stride_64 > UINT32_MAX || total_rows_64 > UINT32_MAX || dst_ne3_64 > UINT32_MAX) { - return false; - } - const uint32_t patch_stride = (uint32_t) patch_stride_64; - const uint32_t total_rows = (uint32_t) total_rows_64; - const uint32_t dst_ne3 = (uint32_t) dst_ne3_64; + auto mem = sbuf->mem; + int fd = mem->fd; - if (dst->ne[0] != patch_stride || dst->ne[1] != OW || dst->ne[2] != OH || dst->ne[3] != dst_ne3) { - return false; - } + GGML_ASSERT(fd >= 0); - const uint32_t dst_elem = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); - - const bool is_patchembed = ggml_is_contiguous(src1) && - (s0 == (int32_t) KW && s1 == (int32_t) KH && s2 == (int32_t) KD && - p0 == 0 && p1 == 0 && p2 == 0 && - d0 == 1 && d1 == 1 && d2 == 1); - - const uint32_t max_threads = (sess && sess->n_threads > 0) ? (uint32_t) sess->n_threads : 8; - const uint32_t n_threads = (total_rows < max_threads) ? total_rows : max_threads; - const uint32_t vtcm_size = (sess && sess->vtcm_size > 0) ? sess->vtcm_size : 0; - - if (is_patchembed) { - const uint64_t src_row_bytes_raw = (uint64_t) IC * KD * KH * IW * sizeof(float); - const uint64_t dst_row_bytes_raw = (uint64_t) OW * patch_stride * dst_elem; - if (src_row_bytes_raw <= UINT32_MAX && dst_row_bytes_raw <= UINT32_MAX) { - const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); - const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); - - struct htp_im2col_vtcm_layout layout; - htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads); - - if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { - kparams->kernel_type = HTP_IM2COL_KERNEL_PATCHEMBED_DMA; - kparams->is_2d = 0; - kparams->is_3d = 1; - kparams->n_threads = (uint8_t) n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->off_src = layout.off_src; - kparams->off_dst = layout.off_dst; - kparams->src_bytes_per_thread = layout.src_bytes_per_thread; - kparams->dst_bytes_per_thread = layout.dst_bytes_per_thread; - kparams->src_row_bytes = src_row_bytes; - kparams->dst_row_bytes = dst_row_bytes; - kparams->owb = OW; - kparams->wb = IW; - kparams->nbpr = 1; - kparams->N = N; - kparams->IC = IC; - kparams->ID = ID; - kparams->IH = IH; - kparams->IW = IW; - kparams->KD = KD; - kparams->KH = KH; - kparams->KW = KW; - kparams->OD = OD; - kparams->OH = OH; - kparams->OW = OW; - kparams->patch_stride = patch_stride; - kparams->total_rows = total_rows; - return true; - } - } + auto it = this->cloned_buffers.find(fd); + if (it != this->cloned_buffers.end()) { + auto clone = std::move(it->second); + this->cloned_buffers.erase(it); } + mem->mapped_clones.erase(this); +} - for (uint32_t owb = (OW < 256 ? OW : 256); owb >= 1; owb--) { - const uint64_t Wb = (uint64_t) (owb - 1) * s0 + (uint64_t) (KW - 1) * d0 + 1; - if (Wb > UINT32_MAX) { - if (owb == 1) break; - continue; - } +void ggml_hexagon_session::unclone_buffer(const ggml_hexagon_shared_buffer * sbuf) { + GGML_ASSERT(sbuf && sbuf->mem); - const uint64_t src_row_bytes_raw = (uint64_t) IC * KD * KH * Wb * sizeof(float); - const uint64_t dst_row_bytes_raw = (uint64_t) owb * patch_stride * dst_elem; - if (src_row_bytes_raw > UINT32_MAX || dst_row_bytes_raw > UINT32_MAX) { - if (owb == 1) break; - continue; - } + auto mem = sbuf->mem; + std::vector sessions(mem->mapped_clones.begin(), mem->mapped_clones.end()); - const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); - const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); - - struct htp_im2col_vtcm_layout layout; - htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads); - - if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { - kparams->kernel_type = HTP_IM2COL_KERNEL_BLOCKED_DMA; - kparams->is_2d = 0; - kparams->is_3d = 1; - kparams->n_threads = (uint8_t) n_threads; - kparams->vtcm_size = layout.total_bytes; - kparams->off_src = layout.off_src; - kparams->off_dst = layout.off_dst; - kparams->src_bytes_per_thread = layout.src_bytes_per_thread; - kparams->dst_bytes_per_thread = layout.dst_bytes_per_thread; - kparams->src_row_bytes = src_row_bytes; - kparams->dst_row_bytes = dst_row_bytes; - kparams->owb = owb; - kparams->wb = (uint32_t) Wb; - kparams->nbpr = (OW + owb - 1) / owb; - kparams->N = N; - kparams->IC = IC; - kparams->ID = ID; - kparams->IH = IH; - kparams->IW = IW; - kparams->KD = KD; - kparams->KH = KH; - kparams->KW = KW; - kparams->OD = OD; - kparams->OH = OH; - kparams->OW = OW; - kparams->patch_stride = patch_stride; - kparams->total_rows = total_rows; - return true; - } - if (owb == 1) break; + for (auto * sess : sessions) { + sess->release_buffer(sbuf); } - - return false; } -static bool ggml_hexagon_supported_im2col(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - struct htp_im2col_kernel_params kparams; - return ggml_hexagon_precompute_im2col_params(sess, op, &kparams); -} +static size_t ggml_hexagon_measure_max_vmem(ggml_hexagon_session *sess) { + // Allocate a bunch pinned buffers till failure. + // This is kind of expensive but handy for figuring out exactly how much we can mmap on a specific device. + // Typically we're going to allocate all/most of these buffers anyway for the model weights. -static bool ggml_hexagon_supported_im2col_3d(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - struct htp_im2col_kernel_params kparams; - return ggml_hexagon_precompute_im2col_3d_params(sess, op, &kparams); -} + std::vector sbufs; -static bool ggml_hexagon_supported_pad(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; + const size_t MiB = 1024 * 1024; + const size_t GiB = MiB * 1024; - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; - } + size_t vmem = 0; + size_t step = 256u * MiB; - const int32_t lp0 = ((const int32_t *) op->op_params)[0]; - const int32_t rp0 = ((const int32_t *) op->op_params)[1]; - const int32_t circular = ((const int32_t *) op->op_params)[8]; + try { + sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; + sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; + sbufs.push_back(new ggml_hexagon_shared_buffer(sess, GiB, true)); vmem += GiB; - if (circular && (lp0 > src0->ne[0] || rp0 > src0->ne[0])) { - return false; - } + while (1) { + sbufs.push_back(new ggml_hexagon_shared_buffer(sess, step, true)); + vmem += step; + } + } catch (...) { } - return true; + for (auto b : sbufs) { delete b; } - GGML_UNUSED(sess); + return vmem - step; // backoff to account for overhead from internal mappings } -static bool ggml_hexagon_supported_cumsum(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; +void ggml_hexagon_session::allocate(const ggml_hexagon_device_config & config) noexcept(false) { + int phys_idx = config.physical_idx; + int virt_idx = config.virtual_idx; - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; - } + this->valid_session = false; + this->valid_handle = false; + this->valid_queue = false; + this->valid_iface = false; - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { - return false; + this->name = config.name; + this->phys_idx = phys_idx; + this->virt_idx = virt_idx; + this->domain_id = config.domain_id; + this->session_id = 0; + this->batch_req_seq = 0; + this->batch_rsp_seq = 0; + this->last_error = HTP_STATUS_OK; + + GGML_LOG_DEBUG("ggml-hex: %s allocating new session : domain %u phys-idx %u virt-idx %u\n", this->name.c_str(), this->domain_id, phys_idx, virt_idx); + + if (config.domain_id < 0 || config.domain_name.empty()) { + GGML_LOG_ERROR("ggml-hex: %s: invalid physical CDSP core %d\n", config.name.c_str(), config.physical_idx); + throw std::runtime_error("ggml-hex: invalid physical CDSP core"); } - return true; + const std::string & dom_name = config.domain_name; - GGML_UNUSED(sess); -} + // Create new session if virtual_idx > 0 + if (virt_idx > 0) { + struct remote_rpc_reserve_new_session n {}; + n.domain_name_len = dom_name.size(); + n.domain_name = const_cast(dom_name.c_str()); + n.session_name = const_cast(this->name.c_str()); + n.session_name_len = this->name.size(); + n.session_id = virt_idx; -static bool ggml_hexagon_supported_diag(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; + int err = remote_session_control(FASTRPC_RESERVE_NEW_SESSION, (void *) &n, sizeof(n)); + if (err != AEE_SUCCESS) { + GGML_LOG_ERROR("ggml-hex: %s failed to reserve new session (physical %d, virtual %d) : error 0x%x\n", + this->c_name(), phys_idx, virt_idx, err); + throw std::runtime_error("ggml-hex: remote_session_control(new-sess) failed (see log for details)"); + } - // diag only supports F32 currently - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; - } + // Save the IDs + this->session_id = n.session_id; + this->domain_id = n.effective_domain_id; + this->valid_session = true; + } else { + struct remote_rpc_effective_domain_id eff {}; + eff.domain_name = const_cast(dom_name.c_str()); + eff.domain_name_len = dom_name.size(); + eff.session_id = 0; - // Input must have ne[1] == 1 (vector input) - if (src0->ne[1] != 1) { - return false; + int err = remote_session_control(FASTRPC_GET_EFFECTIVE_DOMAIN_ID, (void *) &eff, sizeof(eff)); + if (err == AEE_SUCCESS) { + this->domain_id = eff.effective_domain_id; + } else { + GGML_LOG_DEBUG("ggml-hex: %s FASTRPC_GET_EFFECTIVE_DOMAIN_ID returned 0x%x, using domain_id %d\n", + this->name.c_str(), err, this->domain_id); + } } - // Output must be square in first two dimensions - if (dst->ne[0] != dst->ne[1] || dst->ne[0] != src0->ne[0]) { - return false; + // Enable unsigned modules + { + struct remote_rpc_control_unsigned_module u; + u.domain = this->domain_id; + u.enable = 1; + int err = remote_session_control(DSPRPC_CONTROL_UNSIGNED_MODULE, (void *) &u, sizeof(u)); + if (err != AEE_SUCCESS) { + GGML_LOG_ERROR("ggml-hex: %s failed to enable unsigned PD : error 0x%x\n", this->c_name(), err); + throw std::runtime_error("ggml-hex: remote_session_control(unsign) failed (see log for details)"); + } } - return true; + char session_uri[256]; + { + char htp_uri[256]; + snprintf(htp_uri, sizeof(htp_uri), "file:///libggml-htp-v%u.so?htp_iface_skel_handle_invoke&_modver=1.0", opt_arch); - GGML_UNUSED(sess); -} + struct remote_rpc_get_uri u = {}; + u.session_id = this->session_id; + u.domain_name = const_cast(dom_name.c_str()); + u.domain_name_len = dom_name.size(); + u.module_uri = const_cast(htp_uri); + u.module_uri_len = strlen(htp_uri); + u.uri = session_uri; + u.uri_len = sizeof(session_uri); -static bool ggml_hexagon_supported_solve_tri(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * src0 = op->src[0]; // A - const struct ggml_tensor * src1 = op->src[1]; // B - const struct ggml_tensor * dst = op; // X + int err = remote_session_control(FASTRPC_GET_URI, (void *) &u, sizeof(u)); + if (err != AEE_SUCCESS) { + snprintf(session_uri, sizeof(session_uri), "%s&_dom=%s&_session=%u", + htp_uri, dom_name.c_str(), this->session_id); - if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; + GGML_LOG_WARN("ggml-hex: %s failed to get URI (physical %d, virtual %d) : error 0x%x. Falling back to single session URI: %s\n", + this->c_name(), phys_idx, virt_idx, err, session_uri); + } } - if (src0->ne[0] != src0->ne[1]) { - return false; + // Open session + int err = htp_iface_open(session_uri, &this->handle); + if (err != AEE_SUCCESS) { + GGML_LOG_ERROR("ggml-hex: %s failed to open session : uri %s error 0x%x\n", this->c_name(), session_uri, err); + throw std::runtime_error("ggml-hex: failed to open session (see log for details)"); } - if (src0->ne[1] != src1->ne[1]) { - return false; - } + this->valid_handle = true; - if (src0->ne[2] != src1->ne[2] || src0->ne[3] != src1->ne[3]) { - return false; + // Query HW info and resolve session options + { + unsigned int hw_n_threads = 0; + unsigned int hw_n_hvx = 0; + unsigned int hw_n_hmx = 0; + unsigned long long hw_vtcm_size = 0; + int hw_err = htp_iface_hwinfo(this->handle, &hw_n_threads, &hw_n_hvx, &hw_n_hmx, &hw_vtcm_size); + if (hw_err == 0) { + const uint32_t max_n_threads = (std::min)((uint32_t) HTP_MAX_NTHREADS, (uint32_t) hw_n_threads); + this->n_threads = opt_nhvx > 0 ? (uint32_t) (std::min)(opt_nhvx, (size_t) max_n_threads) : max_n_threads; + this->n_hvx = this->n_threads; + this->n_hmx = (opt_nhmx != 0) ? (uint32_t)hw_n_hmx : 0; + this->vtcm_size = (uint64_t)hw_vtcm_size; + if (opt_vtcm_size > 0) { + if (opt_vtcm_size > hw_vtcm_size) { + GGML_LOG_WARN("ggml-hex: %s VTCM override %zu exceeds HW size %llu\n", this->c_name(), opt_vtcm_size, hw_vtcm_size); + } + this->vtcm_size = opt_vtcm_size; + } + GGML_LOG_INFO("ggml-hex: %s hwinfo: threads %u, hvx %u, hmx %u, vtcm %llu MB\n", + this->c_name(), this->n_threads, this->n_hvx, this->n_hmx, + (unsigned long long)(this->vtcm_size / (1024 * 1024))); + } else { + GGML_LOG_WARN("ggml-hex: %s failed to query hwinfo (0x%x), using defaults\n", this->c_name(), hw_err); + const uint32_t default_n_threads = (std::min)(8u, (uint32_t) HTP_MAX_NTHREADS); + this->n_threads = opt_nhvx > 0 ? (uint32_t) (std::min)(opt_nhvx, (size_t) HTP_MAX_NTHREADS) : default_n_threads; + this->n_hvx = this->n_threads; + this->n_hmx = (opt_nhmx != 0) ? 1 : 0; + this->vtcm_size = opt_vtcm_size > 0 ? opt_vtcm_size : 8 * 1024 * 1024; + } } - if (dst->ne[0] != src1->ne[0] || dst->ne[1] != src1->ne[1] || dst->ne[2] != src1->ne[2] || dst->ne[3] != src1->ne[3]) { - return false; + // Enable FastRPC QoS mode + { + struct remote_rpc_control_latency l; + l.enable = 1; + + int err = remote_handle64_control(this->handle, DSPRPC_CONTROL_LATENCY, (void *) &l, sizeof(l)); + if (err != 0) { + GGML_LOG_WARN("ggml-hex: failed to enable fastrpc QOS mode: 0x%08x\n", (unsigned) err); + } } - return true; + GGML_LOG_INFO("ggml-hex: %s new session : session-id %d domain-id %d uri %s handle 0x%lx\n", this->c_name(), + this->session_id, this->domain_id, session_uri, (unsigned long) this->handle); - GGML_UNUSED(sess); -} + const size_t req_q_size = (sizeof(htp_opbatch_req) * opt_opqueue * 2) + 1024; + const size_t rsp_q_size = (sizeof(htp_opbatch_rsp) * opt_opqueue * 2) + 1024; + + // Now let's setup the DSP queue + err = dspqueue_create(this->domain_id, + 0, // Flags + req_q_size, // Request queue size (in bytes) + rsp_q_size, // Response queue size (in bytes) + nullptr, // Read packet callback (we handle reads explicitly) + nullptr, // Error callback (we handle errors during reads) + (void *) this, // Callback context + &queue); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: %s dspqueue_create failed: 0x%08x\n", this->name.c_str(), (unsigned) err); + throw std::runtime_error("ggml-hex: failed to create dspqueue (see log for details)"); + } -static bool ggml_hexagon_supported_tri(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { + this->valid_queue = true; - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; + // Export queue for use on the DSP + err = dspqueue_export(queue, &this->queue_id); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: dspqueue_export failed: 0x%08x\n", (unsigned) err); + throw std::runtime_error("ggml-hex: dspqueue export failed (see log for details)"); + } - if (src0->type != GGML_TYPE_F32) { return false; } - if (dst->type != GGML_TYPE_F32) { return false; } - if (!ggml_are_same_shape(src0, dst)) { return false; } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { return false; } + if (opt_etm) { + err = htp_iface_etm(this->handle, 1); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: failed to enable ETM tracing: 0x%08x\n", (unsigned) err); + } + } - return true; + // Allocate buffers and state for op batching + this->op_queue = new ggml_hexagon_opqueue(this, opt_opbatch, opt_opqueue); - GGML_UNUSED(sess); -} + this->fence_buf = new ggml_hexagon_fence_buffer(this, &dev_ctx->fence_buffer_type, 64 * 1024); + if (this->mdev.count > 1) { + this->mdev_fence_slot = this->alloc_fence(this->mdev.count); + } -static const char * ggml_backend_hexagon_name(ggml_backend_t backend) { - auto sess = static_cast(backend->context); - return sess->c_name(); -} + if (!opt_vmem) { + opt_vmem = ggml_hexagon_measure_max_vmem(this); + GGML_LOG_INFO("ggml-hex: %s measured max vmem %zu\n", this->c_name(), opt_vmem); + } + const size_t shm_size = this->op_queue->shm_size(); + this->max_vmem = (opt_vmem > shm_size) ? (opt_vmem - shm_size) : opt_vmem; -static void ggml_backend_hexagon_free(ggml_backend_t backend) { - // we just need to delete the backend here - // the sessions are allocated & freed as part of the registry - delete backend; -} + this->op_batch = new ggml_hexagon_opbatch(this, opt_opbatch, this->max_vmem); -static htp_op_code op_remap_to_htp(const ggml_tensor * t) { - switch (t->op) { - case GGML_OP_FLASH_ATTN_EXT: return HTP_OP_FLASH_ATTN_EXT; - case GGML_OP_MUL_MAT: return HTP_OP_MUL_MAT; - case GGML_OP_MUL_MAT_ID: return HTP_OP_MUL_MAT_ID; - case GGML_OP_MUL: return HTP_OP_MUL; - case GGML_OP_ADD: return HTP_OP_ADD; - case GGML_OP_ADD_ID: return HTP_OP_ADD_ID; - case GGML_OP_SUB: return HTP_OP_SUB; - case GGML_OP_DIV: return HTP_OP_DIV; - case GGML_OP_DUP: - case GGML_OP_CPY: return HTP_OP_CPY; - case GGML_OP_CONT: return HTP_OP_CPY; - case GGML_OP_GET_ROWS: return HTP_OP_GET_ROWS; - case GGML_OP_SET_ROWS: return HTP_OP_SET_ROWS; - case GGML_OP_SUM: return HTP_OP_SUM; - case GGML_OP_SUM_ROWS: return HTP_OP_SUM_ROWS; - case GGML_OP_POOL_2D: return HTP_OP_POOL_2D; - case GGML_OP_POOL_1D: return HTP_OP_POOL_1D; - case GGML_OP_ARGSORT: return HTP_OP_ARGSORT; - case GGML_OP_TOP_K: return HTP_OP_TOP_K; - case GGML_OP_ARGMAX: return HTP_OP_ARGMAX; - case GGML_OP_NORM: return HTP_OP_NORM; - case GGML_OP_L2_NORM: return HTP_OP_L2_NORM; - case GGML_OP_RMS_NORM: return HTP_OP_RMS_NORM; - case GGML_OP_CONCAT: return HTP_OP_CONCAT; - case GGML_OP_SCALE: return HTP_OP_SCALE; - case GGML_OP_CLAMP: return HTP_OP_CLAMP; - case GGML_OP_LEAKY_RELU: return HTP_OP_LEAKY_RELU; - case GGML_OP_SQR: return HTP_OP_SQR; - case GGML_OP_SQRT: return HTP_OP_SQRT; - case GGML_OP_LOG: return HTP_OP_UNARY_LOG; - case GGML_OP_SOFT_MAX: return HTP_OP_SOFTMAX; - case GGML_OP_SSM_CONV: return HTP_OP_SSM_CONV; - case GGML_OP_GATED_DELTA_NET: return HTP_OP_GATED_DELTA_NET; - case GGML_OP_ROPE: return HTP_OP_ROPE; - case GGML_OP_REPEAT: return HTP_OP_REPEAT; - case GGML_OP_CUMSUM: return HTP_OP_CUMSUM; - case GGML_OP_FILL: return HTP_OP_FILL; - case GGML_OP_DIAG: return HTP_OP_DIAG; - case GGML_OP_SOLVE_TRI: return HTP_OP_SOLVE_TRI; - case GGML_OP_TRI: return HTP_OP_TRI; - case GGML_OP_PAD: return HTP_OP_PAD; - case GGML_OP_IM2COL: return HTP_OP_IM2COL; - case GGML_OP_IM2COL_3D: return HTP_OP_IM2COL_3D; - case GGML_OP_ROLL: return HTP_OP_ROLL; - - case GGML_OP_UNARY: - switch (ggml_get_unary_op(t)) { - case GGML_UNARY_OP_SILU: return HTP_OP_UNARY_SILU; - case GGML_UNARY_OP_GELU: return HTP_OP_UNARY_GELU; - case GGML_UNARY_OP_GELU_QUICK: return HTP_OP_UNARY_GELU_QUICK; - case GGML_UNARY_OP_GELU_ERF: return HTP_OP_UNARY_GELU_ERF; - case GGML_UNARY_OP_SIGMOID: return HTP_OP_UNARY_SIGMOID; - case GGML_UNARY_OP_NEG: return HTP_OP_UNARY_NEG; - case GGML_UNARY_OP_EXP: return HTP_OP_UNARY_EXP; - case GGML_UNARY_OP_SOFTPLUS: return HTP_OP_UNARY_SOFTPLUS; - case GGML_UNARY_OP_TANH: return HTP_OP_UNARY_TANH; - case GGML_UNARY_OP_ABS: return HTP_OP_UNARY_ABS; - case GGML_UNARY_OP_RELU: return HTP_OP_UNARY_RELU; - case GGML_UNARY_OP_STEP: return HTP_OP_UNARY_STEP; - default: - break; - } - break; + // Start dspqueue/opbatch processing + err = htp_iface_start(this->handle, this->session_id, this->queue_id, this->n_threads, opt_nhmx, opt_vtcm_size, this->max_vmem, + (uint32_t) opt_power_mode); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: %s failed to start session: 0x%08x\n", this->c_name(), (unsigned) err); + throw std::runtime_error("ggml-hex: iface start failed (see log for details)"); + } + this->valid_iface = true; + GGML_LOG_INFO("ggml-hex: %s power mode: %s\n", this->c_name(), htp_power_mode_to_str(opt_power_mode)); - case GGML_OP_GLU: - switch (ggml_get_glu_op(t)) { - case GGML_GLU_OP_SWIGLU: return HTP_OP_GLU_SWIGLU; - case GGML_GLU_OP_SWIGLU_OAI: return HTP_OP_GLU_SWIGLU_OAI; - case GGML_GLU_OP_SWIGLU_CLAMP: return HTP_OP_GLU_SWIGLU_CLAMP; - case GGML_GLU_OP_GEGLU: return HTP_OP_GLU_GEGLU; - case GGML_GLU_OP_GEGLU_QUICK: return HTP_OP_GLU_GEGLU_QUICK; - case GGML_GLU_OP_GEGLU_ERF: return HTP_OP_GLU_GEGLU_ERF; - default: break; - } - break; + if (opt_profile) { + htp_iface_pmu_conf pmu_conf{}; + std::copy(opt_pmu_evt.begin(), opt_pmu_evt.end(), pmu_conf.events); - default: - GGML_ABORT("\nggml-hex: graph-compute %s is not supported\n", ggml_op_desc(t)); + err = htp_iface_profiler(this->handle, opt_profile, &pmu_conf); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: failed to enable profiling: 0x%08x\n", (unsigned) err); + } } - return HTP_OP_INVALID; } -static inline bool op_is_compute(ggml_tensor *node) -{ - return !ggml_op_is_empty(node->op) && !ggml_is_empty(node) && (node->flags & GGML_TENSOR_FLAG_COMPUTE); -} +void ggml_hexagon_session::release() noexcept(true) { + GGML_LOG_INFO("ggml-hex: releasing session: %s\n", this->name.c_str()); -static bool mm_is_hmx_eligible(const ggml_tensor * t) { - if (opt_nhmx == 0) { return false; } + this->mdev.sessions.clear(); - const ggml_tensor * src0 = t->src[0]; - const ggml_tensor * src1 = t->src[1]; + int err; - if (ggml_hexagon_matmul_can_collapse(src0, src1, t)) { - const ggml_tensor src1_c = ggml_hexagon_tensor_collapse_rows(src1); - const int wtype = src0->type; - const bool is_repack = ggml_hexagon_is_repack_type((ggml_type) wtype); - const int ne01_padded = is_repack ? hex_round_up(src0->ne[1], 32) : src0->ne[1]; - return ggml_hexagon_matmul_is_hmx_eligible(src0, &src1_c, t, ne01_padded, false, false); + if (this->valid_iface) { + // Stop dspqueue/opbatch processing + err = htp_iface_stop(this->handle); + if (err != 0) { + GGML_ABORT("ggml-hex: htp_iface_stop failed: 0x%08x\n", (unsigned) err); + } } - const int wtype = src0->type; - const bool is_repack = ggml_hexagon_is_repack_type((ggml_type) wtype); - const bool is_matmul_id = (t->op == GGML_OP_MUL_MAT_ID); - const bool is_batched = (src0->ne[2] * src0->ne[3] > 1 || src1->ne[2] * src1->ne[3] > 1); - - const int ne01_padded = is_repack ? hex_round_up(src0->ne[1], 32) : src0->ne[1]; - - return ggml_hexagon_matmul_is_hmx_eligible(src0, src1, t, ne01_padded, is_matmul_id, is_batched); -} - -static bool is_supported_mul_mat_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams) { - if (kparams->n_hmx) { - return kparams->kernel_type == HTP_MM_KERNEL_HMX_2D; + delete this->op_batch; + delete this->op_queue; + for (auto & it : this->cpy_fence_slots) { + free_fence((void *) it.second, 1); } + this->cpy_fence_slots.clear(); - if (!ggml_hexagon_is_repack_type(src0->type) || src0->type == GGML_TYPE_Q6_K) { - return false; // Q6_K has no fused HVX kernel + if (this->fence_buf) { + unclone_buffer(this->fence_buf); + delete this->fence_buf; + this->fence_buf = nullptr; + } + while (!this->cloned_buffers.empty()) { + release_buffer(this->cloned_buffers.begin()->second.get()); } - return kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW; -} + if (opt_etm) { + err = htp_iface_etm(this->handle, 0); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: warn : failed to disable ETM tracing: 0x%08x\n", (unsigned) err); + } + } -static bool is_supported_mul_mat_id_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams) { - if (kparams->n_hmx) { - return kparams->kernel_type == HTP_MM_KERNEL_HMX_2D; + if (opt_profile) { + htp_iface_pmu_conf pmu_conf{}; + err = htp_iface_profiler(this->handle, 0, &pmu_conf); + if (err != 0) { + GGML_LOG_ERROR("ggml-hex: warn : failed to disable profiling: 0x%08x\n", (unsigned) err); + } } - if (!ggml_hexagon_is_repack_type(src0->type)) { - return false; + if (this->valid_queue) { + err = dspqueue_close(queue); + if (err != 0) { + GGML_ABORT("ggml-hex: dspqueue_close failed: 0x%08x\n", (unsigned) err); + } } - return kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK; + if (this->valid_handle) { + htp_iface_close(this->handle); + } } -static bool is_mergeable_mul_mat(const ggml_tensor * t) { - if (t->op != GGML_OP_MUL_MAT) return false; - - const ggml_tensor * src0 = t->src[0]; - const ggml_tensor * src1 = t->src[1]; - if (src0->ne[2] != 1 || src0->ne[3] != 1) return false; +ggml_hexagon_session::ggml_hexagon_session(const ggml_hexagon_device_config & config, ggml_backend_dev_t dev, uint32_t mdev_idx, uint32_t mdev_count) noexcept(false) { + this->dev = dev; + this->dev_ctx = static_cast(dev->context); + this->mdev.idx = mdev_idx; + this->mdev.count = mdev_count > 0 ? mdev_count : (uint32_t) (1 + config.mdev_group.size()); + op_batch = nullptr; + op_queue = nullptr; + fence_buf = nullptr; + fence_seq = ((uintptr_t)this) & 0xFFFF; - if (mm_is_hmx_eligible(t)) { - return ggml_hexagon_is_hmx_weight_type(src0->type); + try { + allocate(config); + if (this->mdev.idx == 0 && !config.mdev_group.empty()) { + for (size_t i = 0; i < config.mdev_group.size(); i++) { + this->mdev.sessions.push_back(std::make_unique( + config.mdev_group[i], this->dev, (uint32_t) (i + 1), this->mdev.count)); + } + } + } catch (const std::exception & exc) { + release(); + throw; } - - // HVX path requires F32 activations and repacked weights (except Q6_K) - if (src1->type != GGML_TYPE_F32) return false; - - return ggml_hexagon_is_repack_type(src0->type) && src0->type != GGML_TYPE_Q6_K; } -static bool is_mergeable_mul_mat_pair(const ggml_tensor * n1, const ggml_tensor * n2) { - if (!is_mergeable_mul_mat(n1) || !is_mergeable_mul_mat(n2)) { - return false; - } - if (n1->src[1] != n2->src[1]) { - return false; - } - if (n1->src[0]->ne[0] != n2->src[0]->ne[0]) { - return false; - } - if (n1->src[0]->type != n2->src[0]->type) { - return false; - } - if (mm_is_hmx_eligible(n1) != mm_is_hmx_eligible(n2)) { - return false; - } - return true; +ggml_hexagon_session::~ggml_hexagon_session() noexcept(true) { + release(); } -static bool is_mergeable_mul_mat_id(const ggml_tensor * t) { - if (t->op != GGML_OP_MUL_MAT_ID) return false; +// ** backend interface - const ggml_tensor * src0 = t->src[0]; - return ggml_hexagon_is_repack_type(src0->type); +static const char * ggml_backend_hexagon_name(ggml_backend_t backend) { + auto sess = static_cast(backend->context); + return sess->c_name(); } -static bool is_mergeable_mul_mat_id_pair(const ggml_tensor * n1, const ggml_tensor * n2) { - if (!is_mergeable_mul_mat_id(n1) || !is_mergeable_mul_mat_id(n2)) { - return false; - } - if (n1->src[1] != n2->src[1]) { - return false; - } - if (n1->src[2] != n2->src[2]) { - return false; - } - if (n1->src[0]->ne[0] != n2->src[0]->ne[0]) { - return false; - } - if (n1->src[0]->ne[2] != n2->src[0]->ne[2]) { - return false; - } - if (n1->src[0]->type != n2->src[0]->type) { - return false; - } - if (mm_is_hmx_eligible(n1) != mm_is_hmx_eligible(n2)) { - return false; - } - return true; +static void ggml_backend_hexagon_free(ggml_backend_t backend) { + // we just need to delete the backend here + // the sessions are allocated & freed as part of the registry + delete backend; +} + +static inline bool op_is_compute(ggml_tensor *node) +{ + return !ggml_op_is_empty(node->op) && !ggml_is_empty(node) && (node->flags & GGML_TENSOR_FLAG_COMPUTE); } static ggml_status ggml_backend_hexagon_graph_compute(ggml_backend_t backend, ggml_cgraph * graph) { @@ -8561,27 +2379,11 @@ static ggml_status ggml_backend_hexagon_graph_compute(ggml_backend_t backend, gg const std::vector * nodes_ptr = nullptr; std::vector computed_nodes; - // Check for cache hit bool cache_hit = (graph->uid != 0 && sess->cached_uid == graph->uid); if (cache_hit) { nodes_ptr = &sess->cached_nodes; } else { - // Tag fusable tensors in graph - for (int i = 0; i < graph->n_nodes; i++) { - auto * extra = (ggml_hexagon_tensor_extra *) graph->nodes[i]->extra; - if (!extra) continue; - - extra->flags &= ~GGML_HEXAGON_TENSOR_FUSEABLE; - - if (graph->nodes[i]->op == GGML_OP_RMS_NORM && ggml_can_fuse(graph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) { - extra->flags |= GGML_HEXAGON_TENSOR_FUSEABLE; - } else if (graph->nodes[i]->op == GGML_OP_MUL_MAT || graph->nodes[i]->op == GGML_OP_MUL_MAT_ID) { - if ((i + 1 < graph->n_nodes && graph->nodes[i + 1]->op == GGML_OP_ADD && ggml_can_fuse(graph, i, { graph->nodes[i]->op, GGML_OP_ADD })) || - ggml_node_has_n_uses(graph, i, 1)) { - extra->flags |= GGML_HEXAGON_TENSOR_FUSEABLE; - } - } - } + htp_fusion_tag_graph(graph); computed_nodes.reserve(graph->n_nodes); @@ -8591,98 +2393,29 @@ static ggml_status ggml_backend_hexagon_graph_compute(ggml_backend_t backend, gg continue; } - htp_opnode node(HTP_OP_INVALID, n); - node.opcode = op_remap_to_htp(n); - if (node.opcode == HTP_OP_MUL_MAT || node.opcode == HTP_OP_MUL_MAT_ID) { - ggml_hexagon_precompute_matmul_params(sess, - node.node->src[0], node.node->src[1], node.node, - (struct htp_mm_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_MUL || node.opcode == HTP_OP_ADD || node.opcode == HTP_OP_ADD_ID || node.opcode == HTP_OP_SUB || node.opcode == HTP_OP_DIV) { - const ggml_tensor * src1 = node.node->src[1]; - const ggml_tensor * src2 = (node.opcode == HTP_OP_ADD_ID) ? node.node->src[2] : nullptr; - GGML_ASSERT(ggml_hexagon_precompute_binary_params(sess, - node.opcode, node.node->src[0], src1, node.node, - (struct htp_binary_kernel_params *) node.kernel_params, src2)); - } else if (node.opcode == HTP_OP_FLASH_ATTN_EXT) { - ggml_hexagon_precompute_flash_attn_params(sess, - node.node, - (struct htp_fa_kernel_params *)node.kernel_params - ); - } else if (htp_op_is_unary(node.opcode)) { - auto inputs = node.get_inputs(); - const struct ggml_tensor * src0 = inputs[0]; - const struct ggml_tensor * src1 = inputs.size() > 1 ? inputs[1] : nullptr; - ggml_hexagon_precompute_unary_params(sess, - node.opcode, src0, src1, node.dst(), - (struct htp_unary_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_GET_ROWS) { - ggml_hexagon_precompute_get_rows_params(sess, - node.node->src[0], node.node->src[1], node.dst(), - (struct htp_get_rows_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_SET_ROWS) { - ggml_hexagon_precompute_set_rows_params(sess, - node.node->src[0], node.node->src[1], node.dst(), - (struct htp_set_rows_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_ROPE) { - ggml_hexagon_precompute_rope_params(sess, - node.node, - (struct htp_rope_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_SSM_CONV) { - ggml_hexagon_precompute_ssm_conv_params(sess, - node.node->src[0], node.node->src[1], node.dst(), - (struct htp_ssm_conv_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_SOFTMAX) { - ggml_hexagon_precompute_softmax_params(sess, - node.node, - (struct htp_softmax_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_GATED_DELTA_NET) { - ggml_hexagon_precompute_gated_delta_net_params(sess, - node.node, - (struct htp_gdn_kernel_params *)node.kernel_params - ); - } else if (node.opcode == HTP_OP_ARGSORT || node.opcode == HTP_OP_TOP_K) { - ggml_hexagon_precompute_sort_params(sess, - node.node, - node.opcode == HTP_OP_TOP_K, - (struct htp_sort_kernel_params *) node.kernel_params - ); - } else if (node.opcode == HTP_OP_POOL_2D || node.opcode == HTP_OP_POOL_1D) { - ggml_hexagon_precompute_pool_2d_params( - sess, node.node->src[0], node.dst(), - (struct htp_pool_2d_kernel_params *)node.kernel_params, - node.opcode == HTP_OP_POOL_1D); - } else if (node.opcode == HTP_OP_CONCAT) { - ggml_hexagon_precompute_concat_params(sess, - node.node, - (struct htp_concat_kernel_params *) node.kernel_params - ); - } else if (node.opcode == HTP_OP_CPY || node.opcode == HTP_OP_CPY_FENCE) { - const bool ok = ggml_hexagon_precompute_cpy_params(sess, - node.node, - (struct htp_copy_kernel_params *) node.kernel_params - ); - const auto * kparams = (const struct htp_copy_kernel_params *) node.kernel_params; - if (ok && node.opcode == HTP_OP_CPY && kparams->total_elems == 0) { - continue; + const htp_op_code opcode = htp_op_remap(n); + if (opcode == HTP_OP_INVALID) { + GGML_ABORT("\nggml-hex: graph-compute %s is not supported\n", ggml_op_desc(n)); + } + + htp_opnode node(opcode, n); + if (node.opcode == HTP_OP_MUL_MAT || node.opcode == HTP_OP_MUL_MAT_ID || node.opcode == HTP_OP_GET_ROWS) { + ggml_tensor * src0 = node.node->src[0]; + if (htp_needs_repack(src0)) { + HEX_VERBOSE("ggml-hex: %s rt-repack %s|size %zu\n", sess->c_name(), htp_format_tensor(src0, HTP_OPFMT_TENSOR).c_str(), ggml_nbytes(src0)); + std::vector raw(ggml_nbytes(src0)); + memcpy(raw.data(), src0->data, raw.size()); + htp_repack_tensor_tiled(src0, raw.data(), raw.size()); + auto * extra = (htp_tensor_extra *) src0->extra; + extra->flags |= HTP_TENSOR_TILED; } - } else if (node.opcode == HTP_OP_IM2COL) { - ggml_hexagon_precompute_im2col_params(sess, - node.node, - (struct htp_im2col_kernel_params *) node.kernel_params - ); - } else if (node.opcode == HTP_OP_IM2COL_3D) { - ggml_hexagon_precompute_im2col_3d_params(sess, - node.node, - (struct htp_im2col_kernel_params *) node.kernel_params - ); } + + GGML_ASSERT(htp_kparams_solve(sess, node)); + if (node.opcode == HTP_OP_CPY && node.kparams()->total_elems == 0) { + continue; + } + computed_nodes.push_back(std::move(node)); } @@ -8695,7 +2428,6 @@ static ggml_status ggml_backend_hexagon_graph_compute(ggml_backend_t backend, gg } } - // Queue and execute for (const auto & node : *nodes_ptr) { sess->enqueue_op(node); } @@ -8779,7 +2511,22 @@ static ggml_hexagon_mem_range ggml_hexagon_mem_range_from_tensor(const ggml_tens return mr; } -static void ggml_hexagon_mem_ranges_add_node(ggml_hexagon_mem_ranges & mrs, const htp_opnode & node) { +struct node_info { + ggml_tensor * node; + htp_opvec fused; + + const ggml_tensor * dst() const { return fused.empty() ? node : fused.back(); } + + bool is_empty() const { + return ggml_op_is_empty(node->op); + } + + void add_fused(ggml_tensor * t) { + fused.push_back(t); + } +}; + +static void ggml_hexagon_mem_ranges_add_node(ggml_hexagon_mem_ranges & mrs, const node_info & node) { if (node.is_empty()) return; for (int i = 0; i < GGML_MAX_SRC; i++) { @@ -8797,7 +2544,7 @@ static void ggml_hexagon_mem_ranges_add_node(ggml_hexagon_mem_ranges & mrs, cons mrs.add(ggml_hexagon_mem_range_from_tensor(node.dst(), HEXAGON_MEM_RANGE_TYPE_DST)); } -static bool ggml_hexagon_mem_ranges_check_node(const ggml_hexagon_mem_ranges & mrs, const htp_opnode & node) { +static bool ggml_hexagon_mem_ranges_check_node(const ggml_hexagon_mem_ranges & mrs, const node_info & node) { if (node.is_empty()) return true; for (int i = 0; i < GGML_MAX_SRC; i++) { @@ -8819,7 +2566,7 @@ static bool ggml_hexagon_mem_ranges_check_node(const ggml_hexagon_mem_ranges & m return mrs.check(ggml_hexagon_mem_range_from_tensor(node.dst(), HEXAGON_MEM_RANGE_TYPE_DST)); } -static std::vector ggml_hexagon_graph_optimize_reorder(const std::vector & nodes) { +static std::vector ggml_hexagon_graph_optimize_reorder(const std::vector & nodes) { const int n = nodes.size(); std::vector res; @@ -8839,16 +2586,16 @@ static std::vector ggml_hexagon_graph_optimize_reorder(const std::vector stack; + htp_opvec stack; stack.push_back(i0); mrs.reset(); @@ -8860,7 +2607,7 @@ static std::vector ggml_hexagon_graph_optimize_reorder(const std::vectorn_nodes; - constexpr int MAX_FUSE = 16; - - enum ggml_op ops[MAX_FUSE]; - - std::vector nodes; + std::vector nodes; nodes.reserve(gf->n_nodes); // Pack nodes for reordering for (int i = 0; i < n; i++) { - htp_opnode node(HTP_OP_INVALID, gf->nodes[i]); - - // fuse only ops that start with these operations - // can be expanded when needed - if (node.op() == GGML_OP_ADD || - node.op() == GGML_OP_NORM || - node.op() == GGML_OP_RMS_NORM) { - ops[0] = node.op(); - - int f = i + 1; - while (f < n && f < i + MAX_FUSE) { - // conservatively allow fusing only these ops - // can be expanded when needed - if (gf->nodes[f]->op != GGML_OP_ADD && - gf->nodes[f]->op != GGML_OP_MUL && - gf->nodes[f]->op != GGML_OP_NORM && - gf->nodes[f]->op != GGML_OP_RMS_NORM) { - break; - } - ops[f - i] = gf->nodes[f]->op; - f++; - } - - f -= i; - for (; f > 1; f--) { - if (ggml_can_fuse(gf, i, ops, f)) { - break; - } - } - - // add the fused tensors into the node info so we can unfuse them later - for (int k = 1; k < f; k++) { - ++i; + node_info node = { gf->nodes[i], {} }; - // the .dst() becomes the last fused tensor - node.add_fused(gf->nodes[i]); - } + const int f = htp_fusion_max(gf, i); + for (int k = 1; k < f; k++) { + node.add_fused(gf->nodes[++i]); } nodes.push_back(std::move(node)); @@ -8972,29 +2683,12 @@ static bool ggml_hexagon_cpy_tensor_async_phys(ggml_backend_t backend_src, ggml_ if (!sess_src->clone_buffer(sess_dst->fence_buf)) { return false; } - if (++sess_dst->fence_seq == 0) sess_dst->fence_seq = 1; - uint32_t fence_seq = sess_dst->fence_seq; + uint32_t fence_seq = sess_dst->next_fence_seq(); HEX_VERBOSE("ggml-hex: %s cpy-tensor-async %s -> %s size %zu : seq 0x%x\n", sess_dst->name.c_str(), src->name, dst->name, ggml_nbytes(src), fence_seq); - // dummy fence extra (must be static) - static ggml_hexagon_tensor_extra fence_extra { {}, 0, GGML_HEXAGON_TENSOR_FENCE }; - - ggml_tensor fence_tensor {}; - fence_tensor.buffer = &sess_dst->fence_buf->backend_buffer; - fence_tensor.extra = &fence_extra; - fence_tensor.data = (void *) fence_slot; - fence_tensor.type = GGML_TYPE_I32; - fence_tensor.ne[0] = 1; - fence_tensor.ne[1] = 1; - fence_tensor.ne[2] = 1; - fence_tensor.ne[3] = 1; - fence_tensor.nb[0] = sizeof(int32_t); - fence_tensor.nb[1] = sizeof(int32_t); - fence_tensor.nb[2] = sizeof(int32_t); - fence_tensor.nb[3] = sizeof(int32_t); - fence_tensor.op = GGML_OP_NONE; + ggml_tensor fence_tensor = sess_dst->make_fence_tensor(fence_slot); sess_src->enqueue_cpy(src, dst, &fence_tensor, fence_seq); sess_dst->enqueue_fence(&fence_tensor, fence_seq, /* wait = */ true); @@ -9032,9 +2726,9 @@ static bool ggml_backend_hexagon_cpy_tensor_async(ggml_backend_t backend_src, gg ggml_backend_buffer_init_tensor(dst->buffer, dst); } - auto * dst_extra = static_cast(dst->extra); - const auto * src_extra = static_cast(src->extra); - dst_extra->flags = src_extra->flags & ~GGML_HEXAGON_TENSOR_FUSEABLE; + auto * dst_extra = static_cast(dst->extra); + const auto * src_extra = static_cast(src->extra); + dst_extra->flags = src_extra->flags & ~HTP_TENSOR_FUSEABLE; auto sess_src = static_cast(backend_src->context); auto sess_dst = static_cast(backend_dst->context); @@ -9056,24 +2750,10 @@ static ggml_backend_event_t ggml_backend_hexagon_device_event_new(ggml_backend_d auto sess = dev_ctx->session(); ggml_hexagon_event * hex_event = new ggml_hexagon_event(); - hex_event->fence_sess = sess; - hex_event->sess = sess; - hex_event->fence_slot = (volatile uint32_t *) sess->alloc_fence(1); - - static ggml_hexagon_tensor_extra fence_extra { {}, 0, GGML_HEXAGON_TENSOR_FENCE }; - hex_event->fence_tensor.buffer = &sess->fence_buf->backend_buffer; - hex_event->fence_tensor.extra = &fence_extra; - hex_event->fence_tensor.data = (void *) hex_event->fence_slot; - hex_event->fence_tensor.type = GGML_TYPE_I32; - hex_event->fence_tensor.ne[0] = 1; - hex_event->fence_tensor.ne[1] = 1; - hex_event->fence_tensor.ne[2] = 1; - hex_event->fence_tensor.ne[3] = 1; - hex_event->fence_tensor.nb[0] = sizeof(int32_t); - hex_event->fence_tensor.nb[1] = sizeof(int32_t); - hex_event->fence_tensor.nb[2] = sizeof(int32_t); - hex_event->fence_tensor.nb[3] = sizeof(int32_t); - hex_event->fence_tensor.op = GGML_OP_NONE; + hex_event->fence_sess = sess; + hex_event->sess = sess; + hex_event->fence_slot = (volatile uint32_t *) sess->alloc_fence(1); + hex_event->fence_tensor = sess->make_fence_tensor(hex_event->fence_slot); HEX_VERBOSE("ggml-hex: %s event-new : event %p fence %p\n", ggml_backend_dev_name(dev), (void *)hex_event, (void *)hex_event->fence_slot); @@ -9128,9 +2808,8 @@ static void ggml_backend_hexagon_event_record(ggml_backend_t backend, ggml_backe auto sess = static_cast(backend->context); auto hex_event = static_cast(event->context); - if (++sess->fence_seq == 0) sess->fence_seq = 1; hex_event->sess = sess; - hex_event->seq = sess->fence_seq; + hex_event->seq = sess->next_fence_seq(); sess->enqueue_fence(&hex_event->fence_tensor, hex_event->seq, /* wait = */ false); @@ -9309,80 +2988,9 @@ static ggml_backend_buffer_type_t ggml_backend_hexagon_device_get_host_buffer_ty return &dev_ctx->host_buffer_type; } -static bool ggml_hexagon_supported_cpy(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - struct htp_copy_kernel_params kparams; - return ggml_hexagon_precompute_cpy_params(sess, op, &kparams); -} - -static bool ggml_hexagon_supported_cont(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - struct htp_copy_kernel_params kparams; - return ggml_hexagon_precompute_cpy_params(sess, op, &kparams); -} - -static bool ggml_hexagon_supported_repeat(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - GGML_UNUSED(sess); - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - // Support f32 and f16 - if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) return false; - - // src and dst must be the same type - if (src0->type != dst->type) return false; - - // dst dims must be multiples of src dims - if (dst->ne[0] % src0->ne[0] != 0) return false; - if (dst->ne[1] % src0->ne[1] != 0) return false; - if (dst->ne[2] % src0->ne[2] != 0) return false; - if (dst->ne[3] % src0->ne[3] != 0) return false; - - // require contiguous tensors (no transposition) - if (ggml_is_transposed(src0) || ggml_is_transposed(dst)) return false; - - return true; -} - -static bool ggml_hexagon_supported_concat(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - struct htp_concat_kernel_params kparams; - return ggml_hexagon_precompute_concat_params(sess, op, &kparams); -} - -static bool ggml_hexagon_supported_fill(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - const struct ggml_tensor * dst = op; - - if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16) { - return false; - } - - return true; - GGML_UNUSED(sess); -} - -static bool ggml_hexagon_supported_roll(const struct ggml_hexagon_session * sess, const struct ggml_tensor * op) { - GGML_UNUSED(sess); - - const struct ggml_tensor * src0 = op->src[0]; - const struct ggml_tensor * dst = op; - - if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; - } - - if (!ggml_are_same_shape(src0, dst)) { - return false; - } - - if (src0->nb[0] != ggml_type_size(src0->type) || dst->nb[0] != ggml_type_size(dst->type)) { - return false; - } - - if (!ggml_is_contiguous(dst)) { - return false; - } - - return true; -} - +// IMPORTANT: supports_op runs before buffer allocation and before tensor data is populated. +// Never check buffer usage, buffer properties, or repacking state (is_tiled) here. +// Support must depend only on static tensor properties (shape, type, strides). static bool ggml_backend_hexagon_device_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { auto dev_ctx = static_cast(dev->context); auto sess = dev_ctx->session(); @@ -9402,194 +3010,17 @@ static bool ggml_backend_hexagon_device_supports_op(ggml_backend_dev_t dev, cons supp = true; break; - case GGML_OP_MUL: - case GGML_OP_ADD: - case GGML_OP_SUB: - case GGML_OP_DIV: - supp = ggml_hexagon_supported_binary(sess, op); - break; - - case GGML_OP_MUL_MAT: - supp = ggml_hexagon_supported_mul_mat(sess, op); - break; - - case GGML_OP_MUL_MAT_ID: - supp = ggml_hexagon_supported_mul_mat_id(sess, op); - break; - - case GGML_OP_ADD_ID: - supp = ggml_hexagon_supported_add_id(sess, op); - break; - - case GGML_OP_NORM: - case GGML_OP_L2_NORM: - case GGML_OP_RMS_NORM: - case GGML_OP_SCALE: - case GGML_OP_CLAMP: - case GGML_OP_LEAKY_RELU: - supp = ggml_hexagon_supported_unary(sess, op); - break; - - case GGML_OP_SQR: - case GGML_OP_SQRT: - case GGML_OP_LOG: - supp = ggml_hexagon_supported_unary(sess, op); - break; - - case GGML_OP_SUM: - supp = ggml_hexagon_supported_sum(sess, op); - break; - - case GGML_OP_SUM_ROWS: - supp = ggml_hexagon_supported_sum_rows(sess, op); - break; - - case GGML_OP_ARGMAX: - supp = ggml_hexagon_supported_argmax(sess, op); - break; - - case GGML_OP_POOL_2D: - supp = ggml_hexagon_supported_pool_2d(sess, op); - break; - - case GGML_OP_POOL_1D: - supp = ggml_hexagon_supported_pool_1d(sess, op); - break; - - case GGML_OP_SOFT_MAX: - supp = ggml_hexagon_supported_softmax(sess, op); - break; - - case GGML_OP_UNARY: - switch (ggml_get_unary_op(op)) { - case GGML_UNARY_OP_NEG: - case GGML_UNARY_OP_EXP: - case GGML_UNARY_OP_SIGMOID: - case GGML_UNARY_OP_SOFTPLUS: - case GGML_UNARY_OP_TANH: - case GGML_UNARY_OP_ABS: - case GGML_UNARY_OP_SILU: - case GGML_UNARY_OP_GELU: - case GGML_UNARY_OP_GELU_QUICK: - case GGML_UNARY_OP_GELU_ERF: - case GGML_UNARY_OP_RELU: - case GGML_UNARY_OP_STEP: - supp = ggml_hexagon_supported_unary(sess, op); - break; - default: - supp = false; - break; - } - break; - - case GGML_OP_GLU: - switch (ggml_get_glu_op(op)) { - case GGML_GLU_OP_SWIGLU: - case GGML_GLU_OP_SWIGLU_OAI: - case GGML_GLU_OP_SWIGLU_CLAMP: - case GGML_GLU_OP_GEGLU: - supp = ggml_hexagon_supported_activations(sess, op); - break; - case GGML_GLU_OP_GEGLU_QUICK: - case GGML_GLU_OP_GEGLU_ERF: - supp = (op->src[0]->type == GGML_TYPE_F32) && ggml_hexagon_supported_activations(sess, op); - break; - default: - supp = false; - break; - } - break; - - case GGML_OP_ROPE: - supp = ggml_hexagon_supported_rope(sess, op); - break; - - case GGML_OP_FLASH_ATTN_EXT: - supp = ggml_hexagon_supported_flash_attn_ext(sess, op); - break; - - case GGML_OP_SET_ROWS: - supp = ggml_hexagon_supported_set_rows(sess, op); - break; - - case GGML_OP_GET_ROWS: - supp = ggml_hexagon_supported_get_rows(sess, op); - break; - - case GGML_OP_DUP: - case GGML_OP_CPY: - supp = ggml_hexagon_supported_cpy(sess, op); - break; - - case GGML_OP_CONT: - supp = ggml_hexagon_supported_cont(sess, op); - break; - - case GGML_OP_REPEAT: - supp = ggml_hexagon_supported_repeat(sess, op); - break; - - case GGML_OP_ARGSORT: - supp = ggml_hexagon_supported_argsort(sess, op); - break; - - case GGML_OP_TOP_K: - supp = ggml_hexagon_supported_top_k(sess, op); - break; - case GGML_OP_SSM_CONV: - supp = ggml_hexagon_supported_ssm_conv(sess, op); - break; - - case GGML_OP_IM2COL: - supp = ggml_hexagon_supported_im2col(sess, op); - break; - - case GGML_OP_IM2COL_3D: - supp = ggml_hexagon_supported_im2col_3d(sess, op); - break; - - case GGML_OP_GATED_DELTA_NET: - supp = ggml_hexagon_supported_gated_delta_net(sess, op); - break; - - case GGML_OP_CUMSUM: - supp = ggml_hexagon_supported_cumsum(sess, op); - break; - - case GGML_OP_CONCAT: - supp = ggml_hexagon_supported_concat(sess, op); - break; - - case GGML_OP_FILL: - supp = ggml_hexagon_supported_fill(sess, op); - break; - - case GGML_OP_DIAG: - supp = ggml_hexagon_supported_diag(sess, op); - break; - - case GGML_OP_SOLVE_TRI: - supp = ggml_hexagon_supported_solve_tri(sess, op); - break; - - case GGML_OP_TRI: - supp = ggml_hexagon_supported_tri(sess, op); - break; - - case GGML_OP_PAD: - supp = ggml_hexagon_supported_pad(sess, op); - break; - - case GGML_OP_ROLL: - supp = ggml_hexagon_supported_roll(sess, op); + // the channels-major input layout is only implemented on CPU/CUDA + supp = ggml_ssm_conv_get_layout(op) == GGML_SSM_CONV_LAYOUT_TIME_MAJOR && htp_kparams_check(sess, op); break; default: + supp = htp_kparams_check(sess, op); break; } - ggml_hexagon_dump_op_supp(sess->name, op, supp); + ggml_hexagon_dump_op_supp(sess->c_name(), op, supp); return supp; } @@ -9706,24 +3137,10 @@ static void * ggml_backend_hexagon_comm_init(ggml_backend_t * backends, size_t n ctx->backends.assign(backends, backends + n_backends); ctx->n_backends = n_backends; - static ggml_hexagon_tensor_extra fence_extra { {}, 0, GGML_HEXAGON_TENSOR_FENCE }; for (size_t i = 0; i < n_backends; i++) { auto sess_i = static_cast(backends[i]->context); - ctx->fence_slots[i] = (volatile uint32_t *) sess_i->alloc_fence(1); - ctx->fence_tensors[i] = {}; - ctx->fence_tensors[i].buffer = &sess_i->fence_buf->backend_buffer; - ctx->fence_tensors[i].extra = &fence_extra; - ctx->fence_tensors[i].data = (void *) ctx->fence_slots[i]; - ctx->fence_tensors[i].type = GGML_TYPE_I32; - ctx->fence_tensors[i].ne[0] = 4; - ctx->fence_tensors[i].ne[1] = 1; - ctx->fence_tensors[i].ne[2] = 1; - ctx->fence_tensors[i].ne[3] = 1; - ctx->fence_tensors[i].nb[0] = sizeof(int32_t); - ctx->fence_tensors[i].nb[1] = sizeof(int32_t); - ctx->fence_tensors[i].nb[2] = sizeof(int32_t); - ctx->fence_tensors[i].nb[3] = sizeof(int32_t); - ctx->fence_tensors[i].op = GGML_OP_NONE; + ctx->fence_slots[i] = (volatile uint32_t *) sess_i->alloc_fence(1); + ctx->fence_tensors[i] = sess_i->make_fence_tensor(ctx->fence_slots[i]); } return ctx; @@ -9777,8 +3194,7 @@ static bool ggml_backend_hexagon_comm_allreduce_tensor(void * comm_ctx_v, struct for (size_t r = 0; r < n_backends; r++) { auto sess = static_cast(comm_ctx->backends[r]->context); - struct htp_allreduce_kernel_params kparams; - if (!ggml_hexagon_precompute_allreduce_params(sess, tensors[r], (uint32_t) r, (uint32_t) n_backends, false, false, /*is_shard_ok=*/ false, &kparams)) { + if (!htp_kparams_check(sess, tensors[r], (uint32_t) r, (uint32_t) n_backends, false, false, false)) { return false; } } @@ -9976,20 +3392,28 @@ static void ggml_hexagon_init(ggml_backend_reg * reg) { "please update hexagon_type to match ggml_type"); static_assert((unsigned int) HTP_TYPE_Q2_K == (unsigned int) GGML_TYPE_Q2_K, "please update hexagon_type to match ggml_type"); + static_assert((unsigned int) HTP_TYPE_Q1_0 == (unsigned int) GGML_TYPE_Q1_0, + "please update hexagon_type to match ggml_type"); + static_assert((unsigned int) HTP_TYPE_Q2_0 == (unsigned int) GGML_TYPE_Q2_0, + "please update hexagon_type to match ggml_type"); + static_assert((unsigned int) HTP_TYPE_BF16 == (unsigned int) GGML_TYPE_BF16, + "please update hexagon_type to match ggml_type"); const char * str_verbose = getenv("GGML_HEXAGON_VERBOSE"); const char * str_opbatch = getenv("GGML_HEXAGON_OPBATCH"); const char * str_opqueue = getenv("GGML_HEXAGON_OPQUEUE"); const char * str_oppoll = getenv("GGML_HEXAGON_OPPOLL"); const char * str_opfusion = getenv("GGML_HEXAGON_OPFUSION"); + const char * str_rt_repack = getenv("GGML_HEXAGON_RT_REPACK"); const char * str_opfilter = getenv("GGML_HEXAGON_OPFILTER"); const char * str_profile = getenv("GGML_HEXAGON_PROFILE"); const char * str_etm = getenv("GGML_HEXAGON_ETM"); const char * str_nhvx = getenv("GGML_HEXAGON_NHVX"); const char * str_nhmx = getenv("GGML_HEXAGON_NHMX"); + const char * str_vtcm_size = getenv("GGML_HEXAGON_VTCM_SIZE"); const char * str_mm_select = getenv("GGML_HEXAGON_MM_SELECT"); const char * str_fa_select = getenv("GGML_HEXAGON_FA_SELECT"); - const char * str_fa_head_split = getenv("GGML_HEXAGON_FA_HEAD_SPLIT"); + const char * str_fa_split = getenv("GGML_HEXAGON_FA_SPLIT"); const char * str_gdn_select = getenv("GGML_HEXAGON_GDN_SELECT"); const char * str_ar_select = getenv("GGML_HEXAGON_AR_SELECT"); const char * str_ar_scatter = getenv("GGML_HEXAGON_AR_SCATTER"); @@ -10012,9 +3436,9 @@ static void ggml_hexagon_init(ggml_backend_reg * reg) { if (opt_arch < 73) { GGML_LOG_WARN("ggml-hex: Hexagon arch v%d is under supported range, capping at v73\n", opt_arch); opt_arch = 73; - } else if (opt_arch > 81) { - GGML_LOG_WARN("ggml-hex: Hexagon arch v%d is over supported range, capping at v81\n", opt_arch); - opt_arch = 81; + } else if (opt_arch > 85) { + GGML_LOG_WARN("ggml-hex: Hexagon arch v%d is over supported range, capping at v85\n", opt_arch); + opt_arch = 85; } } } else { @@ -10036,9 +3460,10 @@ static void ggml_hexagon_init(ggml_backend_reg * reg) { opt_verbose = str_verbose ? atoi(str_verbose) : 0; opt_opbatch = str_opbatch ? strtoul(str_opbatch, NULL, 0) : opt_opbatch; opt_opqueue = str_opqueue ? strtoul(str_opqueue, NULL, 0) : opt_opqueue; - opt_optrace = str_optrace ? strtoul(str_optrace, NULL, 0) : (opt_opbatch * 256); + opt_optrace = str_optrace ? strtoul(str_optrace, NULL, 0) : (opt_opbatch * HTP_TRACE_MAX_EVENTS + 131072); opt_oppoll = str_oppoll ? strtoul(str_oppoll, NULL, 0) : opt_oppoll; opt_opfusion = str_opfusion ? atoi(str_opfusion) : opt_opfusion; + opt_rt_repack = str_rt_repack ? atoi(str_rt_repack) : opt_rt_repack; opt_profile = str_profile ? atoi(str_profile) : 0; opt_etm = str_etm ? atoi(str_etm) : 0; if (str_power_mode) { @@ -10051,9 +3476,10 @@ static void ggml_hexagon_init(ggml_backend_reg * reg) { } opt_nhvx = str_nhvx ? strtoul(str_nhvx, NULL, 0) : opt_nhvx; opt_nhmx = str_nhmx ? atoi(str_nhmx) : opt_nhmx; + opt_vtcm_size = str_vtcm_size ? parse_size(str_vtcm_size) : opt_vtcm_size; opt_mm_select = str_mm_select ? atoi(str_mm_select) : opt_mm_select; opt_fa_select = str_fa_select ? atoi(str_fa_select) : opt_fa_select; - opt_fa_head_split = str_fa_head_split ? atoi(str_fa_head_split) : opt_fa_head_split; + opt_fa_split = str_fa_split ? atoi(str_fa_split) : opt_fa_split; opt_gdn_select = str_gdn_select ? atoi(str_gdn_select) : opt_gdn_select; opt_ar_select = str_ar_select ? atoi(str_ar_select) : opt_ar_select; opt_ar_scatter = str_ar_scatter ? atoi(str_ar_scatter) : opt_ar_scatter; diff --git a/ggml/src/ggml-hexagon/htp-common.h b/ggml/src/ggml-hexagon/htp-common.h new file mode 100644 index 000000000000..e51340d8a278 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-common.h @@ -0,0 +1,106 @@ +#ifndef HTP_COMMON_H +#define HTP_COMMON_H + +#include "htp-opnode.h" +#include "htp-repack.h" + +struct htp_tensor_extra { + std::vector shadow_buf; + size_t shadow_size { 0 }; + uint32_t flags { 0 }; +}; + +extern int opt_arch; +extern size_t opt_ndev; +extern size_t opt_nhvx; +extern int opt_nhmx; +extern size_t opt_vmem; +extern int opt_etm; +extern int opt_verbose; +extern int opt_profile; +extern bool opt_hostbuf; +extern bool opt_dma64; +extern int opt_power_mode; + +extern size_t opt_mbuf_dyn; +extern size_t opt_mbuf_static; +extern size_t opt_mbuf_total; + +extern int opt_mm_select; +extern int opt_fa_select; +extern int opt_fa_split; +extern int opt_gdn_select; +extern int opt_ar_select; +extern int opt_ar_scatter; + +extern int opt_opbatch; +extern int opt_opqueue; +extern int opt_optrace; +extern int opt_oppoll; +extern int opt_opfusion; +extern int opt_rt_repack; + +#ifndef HEX_VERBOSE +#define HEX_VERBOSE(...) \ + if (opt_verbose) GGML_LOG_DEBUG(__VA_ARGS__) +#endif + +static inline bool htp_tensor_is_fuseable(const struct ggml_tensor * t) { + if (!t || !t->extra) return false; + const auto * extra = (const struct htp_tensor_extra *) t->extra; + return (extra->flags & HTP_TENSOR_FUSEABLE) != 0; +} + +static inline bool htp_can_rt_repack(const struct ggml_tensor * t) { + if (opt_rt_repack == 0 || !htp_is_tiled_weight_tensor(t)) { + return false; + } + if (t->buffer && ggml_backend_buft_is_host(t->buffer->buft)) { + return false; + } + return opt_rt_repack > 1 || ggml_is_quantized(t->type); +} + +static inline bool htp_tensor_is_tiled(const struct ggml_tensor * t) { + const auto * extra = (const struct htp_tensor_extra *) t->extra; + if (extra && (extra->flags & HTP_TENSOR_TILED)) { + return true; + } + return htp_can_rt_repack(t); +} + +static inline bool htp_needs_repack(const struct ggml_tensor * t) { + const auto * extra = (const struct htp_tensor_extra *) t->extra; + if (extra && (extra->flags & HTP_TENSOR_TILED)) { + return false; + } + return htp_can_rt_repack(t); +} + +static inline bool htp_tensors_overlap(const struct ggml_tensor * a, const struct ggml_tensor * b) { + const uintptr_t a0 = (uintptr_t) a->data; + const uintptr_t b0 = (uintptr_t) b->data; + const uintptr_t a1 = a0 + ggml_nbytes(a); + const uintptr_t b1 = b0 + ggml_nbytes(b); + + return a0 < b1 && b0 < a1; +} + +static inline bool htp_can_row_partition(const struct ggml_tensor * t) { + if (t->ne[1] > 1 && (t->nb[1] & 127) != 0) return false; + if (t->ne[2] > 1 && (t->nb[2] & 127) != 0) return false; + if (t->ne[3] > 1 && (t->nb[3] & 127) != 0) return false; + return true; +} + +struct ggml_hexagon_session; + +const char * htp_session_name(const struct ggml_hexagon_session * sess); +size_t htp_session_vtcm_size(const struct ggml_hexagon_session * sess); +uint32_t htp_session_n_threads(const struct ggml_hexagon_session * sess); +uint32_t htp_session_n_hmx(const struct ggml_hexagon_session * sess); +uint32_t htp_session_mdev_count(const struct ggml_hexagon_session * sess); + +htp_op_code htp_op_remap(const struct ggml_tensor * t); + +#endif // HTP_COMMON_H diff --git a/ggml/src/ggml-hexagon/htp-fusion.cpp b/ggml/src/ggml-hexagon/htp-fusion.cpp new file mode 100644 index 000000000000..ba2dd64106c9 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-fusion.cpp @@ -0,0 +1,649 @@ +#include "htp-fusion.h" +#include "htp-kparams.h" +#include "ggml-impl.h" + +#include +#include + +static inline bool htp_same_tensor_data(const ggml_tensor * a, const ggml_tensor * b) { + return a && b && (a == b || a->data == b->data); +} + +static inline bool htp_same_shape_and_contiguity(const ggml_tensor * a, const ggml_tensor * b) { + return ggml_are_same_shape(a, b) && (ggml_is_contiguous(a) == ggml_is_contiguous(b)); +} + +static inline bool htp_inplace_overlap_unsafe(const ggml_tensor * dst, const ggml_tensor * in) { + return htp_tensors_overlap(dst, in) && (dst->data != in->data || !ggml_are_same_stride(dst, in)); +} + +static inline bool htp_inputs_overlap_unsafe(const htp_opnode & prev, const ggml_tensor * dst, const ggml_tensor * extra = nullptr) { + if (extra && htp_inplace_overlap_unsafe(dst, extra)) return true; + for (const auto * in : prev.inputs) { + if (htp_inplace_overlap_unsafe(dst, in)) return true; + } + return false; +} + +static inline bool htp_match_consumer( + const htp_opnode & prev, + const htp_opnode & cur, + bool commutative, + const ggml_tensor ** other_src = nullptr +) { + if (prev.outputs.size() != 1) { + return false; + } + const ggml_tensor * prev_out = prev.dst(); + if (!htp_tensor_is_fuseable(prev_out)) { + return false; + } + if (htp_same_tensor_data(cur.src0(), prev_out)) { + if (other_src) *other_src = cur.src1(); + return true; + } + if (commutative && htp_same_tensor_data(cur.src1(), prev_out)) { + if (other_src) *other_src = cur.src0(); + return true; + } + return false; +} + +static bool is_supported_mul_mat_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams) { + if (kparams->n_hmx) { + return kparams->kernel_type == HTP_MM_KERNEL_HMX_2D; + } + return htp_tensor_is_tiled(src0) && (kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW); +} + +static bool is_supported_mul_mat_id_nx_kernel(const ggml_tensor * src0, const struct htp_mm_kernel_params * kparams) { + if (kparams->n_hmx) { + return kparams->kernel_type == HTP_MM_KERNEL_HMX_2D; + } + return htp_tensor_is_tiled(src0) && + (kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK); +} + +// --- Fusion rules --- + +static bool fuse_allreduce_add(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (opt_ar_select != 2 || prev.opcode != HTP_OP_ALLREDUCE) return false; + + const auto * ar_kparams = prev.kparams(); + const uint32_t rank = (uint32_t) ar_kparams->rank; + const uint32_t n_ranks = (uint32_t) ar_kparams->n_ranks; + + const ggml_tensor * ar_local = prev.inputs[rank]; + if (!htp_tensor_is_fuseable(ar_local)) return false; + + const ggml_tensor * add_dst = cur.dst(); + const ggml_tensor * res_tensor = nullptr; + if (htp_same_tensor_data(cur.src0(), ar_local)) { + res_tensor = cur.src1(); + } else if (htp_same_tensor_data(cur.src1(), ar_local)) { + res_tensor = cur.src0(); + } else { + return false; + } + + if (ar_local->type != res_tensor->type) return false; + + const bool is_same_shape = ggml_are_same_shape(ar_local, res_tensor); + const bool is_row_bcast = !is_same_shape && (ar_local->ne[0] == res_tensor->ne[0] && + res_tensor->ne[1] == 1 && res_tensor->ne[2] == 1 && res_tensor->ne[3] == 1); + if (!is_same_shape && !is_row_bcast) return false; + + if (is_same_shape && !ggml_are_same_stride(ar_local, res_tensor)) { + return false; + } + if (ggml_is_contiguous(ar_local) != ggml_is_contiguous(add_dst)) return false; + + const bool is_shard_ok = n_ranks <= HTP_OP_MAX_OUTPUTS && add_dst->data == ar_local->data; + + struct htp_allreduce_kernel_params kparams; + if (!htp_kparams_solve_allreduce(sess, add_dst, rank, n_ranks, true, is_row_bcast, is_shard_ok, &kparams)) { + HEX_VERBOSE("ggml-hex: %s skip ALLREDUCE_ADD fusion: solver failed\n", htp_session_name(sess)); + return false; + } + + const bool scatter_ok = kparams.n_dsts > 1; + kparams.mode = scatter_ok ? HTP_ALLREDUCE_SHARDED_FANOUT : HTP_ALLREDUCE_FULL; + + for (uint32_t r = 0; r < n_ranks; r++) { + const ggml_tensor * ar_src = prev.inputs[r]; + if (!htp_tensors_overlap(add_dst, ar_src)) continue; + if (scatter_ok && r == rank) continue; + HEX_VERBOSE("ggml-hex: %s skip ALLREDUCE_ADD fusion: dst overlaps allreduce src %u\n", htp_session_name(sess), r); + return false; + } + + prev.opcode = HTP_OP_ALLREDUCE_ADD; + prev.inputs.push_back(res_tensor); + if (kparams.mode != HTP_ALLREDUCE_SHARDED_FANOUT) { + prev.outputs = { add_dst }; + } + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_rms_norm_mul(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_RMS_NORM) return false; + + const ggml_tensor * weight = nullptr; + if (!htp_match_consumer(prev, cur, /*commutative=*/ true, &weight)) return false; + + const ggml_tensor * src0 = prev.src0(); + const ggml_tensor * dst = cur.dst(); + if (src0->type != GGML_TYPE_F32 || src0->ne[0] != weight->ne[0] || !htp_same_shape_and_contiguity(prev.dst(), dst)) return false; + if (htp_inputs_overlap_unsafe(prev, dst, weight)) return false; + + const bool is_row_bcast = (weight->ne[1] == 1 && weight->ne[2] == 1 && weight->ne[3] == 1); + const bool is_same_shape = ggml_are_same_shape(src0, weight); + if (!is_row_bcast && !is_same_shape) return false; + + struct htp_unary_kernel_params kparams; + if (!htp_kparams_solve_rms_norm_mul(sess, src0, weight, dst, &kparams)) { + HEX_VERBOSE("ggml-hex: %s skip RMS_NORM_MUL fusion: VTCM needed (%d) > budget (%zu)\n", + htp_session_name(sess), kparams.vtcm_size, htp_session_vtcm_size(sess)); + return false; + } + + prev.opcode = HTP_OP_RMS_NORM_MUL; + prev.inputs = { src0, weight }; + prev.outputs = { dst }; + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_rms_norm_scale(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + GGML_UNUSED(sess); + if (prev.opcode != HTP_OP_RMS_NORM && prev.opcode != HTP_OP_RMS_NORM_MUL) return false; + if (!htp_match_consumer(prev, cur, /*commutative=*/ false)) return false; + + const ggml_tensor * src0 = prev.src0(); + const ggml_tensor * dst = cur.dst(); + if (src0->type != GGML_TYPE_F32 || !htp_same_shape_and_contiguity(prev.dst(), dst)) return false; + if (htp_inputs_overlap_unsafe(prev, dst)) return false; + + float scale = 0.0f; + float bias = 0.0f; + memcpy(&scale, (const float *) cur.params + 0, sizeof(float)); + memcpy(&bias, (const float *) cur.params + 1, sizeof(float)); + if (bias != 0.0f || scale == 0.0f) return false; + + float prev_scale = 0.0f; + memcpy(&prev_scale, &prev.params[1], sizeof(float)); + if (prev_scale != 0.0f) { + scale *= prev_scale; + } + memcpy(&prev.params[1], &scale, sizeof(float)); + + prev.outputs[0] = dst; + prev.fused.push_back(cur.node); + return true; +} + +static bool fuse_mul_mat_add(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_MUL_MAT) return false; + + const ggml_tensor * src2 = nullptr; + if (!htp_match_consumer(prev, cur, /*commutative=*/ true, &src2)) return false; + if (src2->type != GGML_TYPE_F32) return false; + + const ggml_tensor * src0 = prev.node->src[0]; + const ggml_tensor * src1 = prev.node->src[1]; + const ggml_tensor * dst = cur.node; + if (!ggml_are_same_shape(prev.node, dst)) return false; + + const bool prev_collapsed = htp_matmul_can_collapse(src0, src1, prev.node); + const bool cur_collapsed = htp_matmul_add_can_collapse(src0, src1, src2, dst); + if (prev_collapsed != cur_collapsed) { + return false; + } + + const auto * orig_kparams = prev.kparams(); + struct htp_mm_kernel_params kparams; + if (!htp_kparams_solve_matmul_add(sess, src0, src1, src2, dst, &kparams)) { + return false; + } + + const int src1_nrows = src1->ne[1] * src1->ne[2] * src1->ne[3]; + if (kparams.n_hmx == 0 && src1_nrows != 1) return false; + + if (kparams.n_hmx > 0 && orig_kparams->n_hmx > 0) { + if (kparams.m_chunk < orig_kparams->m_chunk || + kparams.n_chunk < orig_kparams->n_chunk || + kparams.n_act_threads < orig_kparams->n_act_threads) { + HEX_VERBOSE("ggml-hex: %s skip MUL_MAT_ADD fusion: HMX efficiency reduced (m %d->%d, n %d->%d, th %d->%d)\n", + htp_session_name(sess), orig_kparams->m_chunk, kparams.m_chunk, + orig_kparams->n_chunk, kparams.n_chunk, + orig_kparams->n_act_threads, kparams.n_act_threads); + return false; + } + } + + prev.opcode = HTP_OP_MUL_MAT_ADD; + prev.inputs = { src0, src1, src2 }; + prev.outputs = { dst }; + htp_opnode_collapse(sess, prev); + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_mul_mat_nx(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_MUL_MAT && prev.opcode != HTP_OP_MUL_MAT_NX) return false; + + const uint32_t curr_n = (uint32_t) prev.outputs.size(); + if (curr_n >= HTP_OP_MAX_OUTPUTS || curr_n + 1 >= HTP_OP_MAX_INPUTS) return false; + + const ggml_tensor * w0 = prev.inputs[0]; + const ggml_tensor * x_orig = prev.node->src[1]; + const ggml_tensor * w_in = cur.node->src[0]; + const ggml_tensor * x_in = cur.node->src[1]; + const ggml_tensor * d_in = cur.node; + + auto * orig_kparams = prev.kparams(); + const auto * cur_kparams = cur.kparams(); + + if (x_in != x_orig || w_in->type != w0->type || w_in->ne[0] != w0->ne[0] || + w0->ne[2] != 1 || w0->ne[3] != 1 || w_in->ne[2] != 1 || w_in->ne[3] != 1 || + htp_tensor_is_tiled(w_in) != htp_tensor_is_tiled(w0) || + orig_kparams->n_hmx != cur_kparams->n_hmx) { + return false; + } + + const bool collapse = htp_matmul_can_collapse(w0, x_orig, prev.node) && htp_matmul_can_collapse(w_in, x_in, d_in); + if ((x_orig->ne[2] > 1 || x_orig->ne[3] > 1) && !collapse) return false; + + if (prev.opcode == HTP_OP_MUL_MAT_NX) { + orig_kparams->n_weights = curr_n + 1; + } else { + struct htp_mm_kernel_params kparams; + const ggml_tensor x_collapsed = collapse ? htp_tensor_collapse_rows(x_orig) : *x_orig; + if (!htp_kparams_solve_mmnx(sess, w0, &x_collapsed, curr_n + 1, &kparams)) return false; + if (!is_supported_mul_mat_nx_kernel(w0, &kparams)) return false; + + prev.set_kparams(kparams); + prev.opcode = HTP_OP_MUL_MAT_NX; + } + + prev.inputs.insert(prev.inputs.begin() + curr_n, w_in); + prev.outputs.push_back(collapse ? prev.add_dummy(htp_tensor_collapse_rows(d_in)) : d_in); + prev.fused.push_back(cur.node); + return true; +} + +static bool fuse_mul_mat_id_nx(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_MUL_MAT_ID && prev.opcode != HTP_OP_MUL_MAT_ID_NX) return false; + + const uint32_t curr_n = (uint32_t) prev.outputs.size(); + if (curr_n >= HTP_OP_MAX_OUTPUTS || curr_n + 2 >= HTP_OP_MAX_INPUTS) return false; + + const ggml_tensor * w0 = prev.inputs[0]; + const ggml_tensor * x = prev.inputs[curr_n]; + const ggml_tensor * ids = prev.inputs[curr_n + 1]; + const ggml_tensor * w_in = cur.src0(); + const ggml_tensor * x_in = cur.src1(); + const ggml_tensor * ids_in = cur.node->src[2]; + const ggml_tensor * d_in = cur.dst(); + + auto * orig_kparams = prev.kparams(); + const auto * cur_kparams = cur.kparams(); + + if (x_in != x || ids_in != ids || w_in->type != w0->type || + w_in->ne[0] != w0->ne[0] || w_in->ne[2] != w0->ne[2] || + htp_tensor_is_tiled(w_in) != htp_tensor_is_tiled(w0) || + orig_kparams->n_hmx != cur_kparams->n_hmx) { + return false; + } + + struct htp_mm_kernel_params kparams; + if (d_in->nb[1] == prev.node->nb[1]) { + kparams = *orig_kparams; + kparams.n_weights = curr_n + 1; + } else if (!htp_kparams_solve_mmidnx(sess, w0, x, d_in, curr_n + 1, &kparams)) { + return false; + } + if (!is_supported_mul_mat_id_nx_kernel(w0, &kparams)) return false; + + prev.opcode = HTP_OP_MUL_MAT_ID_NX; + prev.inputs.insert(prev.inputs.begin() + curr_n, w_in); + prev.outputs.push_back(d_in); + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_gdn_cpy(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + GGML_UNUSED(sess); + if (prev.opcode != HTP_OP_GATED_DELTA_NET || prev.outputs.size() != 1) return false; + + const ggml_tensor * gdn_out = prev.dst(); + const ggml_tensor * cpy_node = cur.node; + const ggml_tensor * cpy_src = cur.src0(); + const ggml_tensor * cpy_dst = cur.dst(); + + if (gdn_out->type != GGML_TYPE_F32 || cpy_src->type != GGML_TYPE_F32 || cpy_dst->type != GGML_TYPE_F32) return false; + if ((gdn_out->flags & GGML_TENSOR_FLAG_OUTPUT) || (cpy_node->flags & GGML_TENSOR_FLAG_OUTPUT)) return false; + + const ggml_tensor * v = prev.node->src[2]; + if (!v) return false; + + const int64_t S_v = v->ne[0]; + const int64_t H = v->ne[1]; + const int64_t n_tokens = v->ne[2]; + const int64_t n_seqs = v->ne[3]; + const int64_t K = ggml_get_op_params_i32(prev.node, 0); + const size_t tail_off = (size_t) S_v * H * n_tokens * n_seqs * sizeof(float); + const int64_t D = S_v * S_v * H; + const int64_t n_written = std::min(n_tokens, K); + + if (cpy_src->op != GGML_OP_VIEW || !htp_same_tensor_data(cpy_src->view_src, gdn_out) || + cpy_src->view_offs != tail_off || !ggml_is_contiguous(cpy_src)) { + return false; + } + + if (cpy_dst->ne[0] != D || cpy_dst->ne[1] != n_seqs || cpy_dst->ne[2] != n_written || !ggml_is_contiguous(cpy_dst)) { + return false; + } + + prev.outputs.push_back(cpy_dst); + prev.fused.push_back(cur.node); + return true; +} + +static bool fuse_ssm_conv_silu(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + GGML_UNUSED(sess); + if (prev.opcode != HTP_OP_SSM_CONV) return false; + + auto * kparams = prev.kparams(); + if (kparams->silu) return false; + if (!htp_match_consumer(prev, cur, /*commutative=*/ false)) return false; + + const ggml_tensor * conv_dst = prev.dst(); + const ggml_tensor * dst = cur.dst(); + if (!ggml_are_same_layout(conv_dst, dst)) return false; + if (htp_tensors_overlap(dst, prev.src0()) || htp_tensors_overlap(dst, prev.src1())) return false; + + kparams->silu = 1; + prev.outputs[0] = dst; + prev.fused.push_back(cur.node); + return true; +} + +static bool fuse_repeat_get_rows(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_REPEAT) return false; + if (!htp_match_consumer(prev, cur, /*commutative=*/ false)) return false; + + const ggml_tensor * repeat_out = prev.dst(); + const ggml_tensor * repeat_src0 = prev.src0(); + const ggml_tensor * gr_src1 = cur.src1(); + const ggml_tensor * gr_dst = cur.dst(); + + if (repeat_src0->ne[0] != repeat_out->ne[0] || repeat_src0->ne[1] != repeat_out->ne[1]) return false; + if (repeat_src0->type != repeat_out->type) return false; + + struct htp_get_rows_kernel_params kparams; + if (!htp_kparams_solve_repeat_get_rows(sess, repeat_src0, gr_src1, gr_dst, &kparams) || kparams.vtcm_size == 0) return false; + + prev.opcode = HTP_OP_GET_ROWS; + prev.inputs = { repeat_src0, gr_src1 }; + prev.outputs = { gr_dst }; + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_unary_mul_glu(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + htp_op_code glu_op = HTP_OP_INVALID; + switch (prev.opcode) { + case HTP_OP_UNARY_SILU: glu_op = HTP_OP_GLU_SWIGLU; break; + case HTP_OP_UNARY_GELU: glu_op = HTP_OP_GLU_GEGLU; break; + case HTP_OP_UNARY_GELU_QUICK: glu_op = HTP_OP_GLU_GEGLU_QUICK; break; + case HTP_OP_UNARY_GELU_ERF: glu_op = HTP_OP_GLU_GEGLU_ERF; break; + case HTP_OP_UNARY_RELU: glu_op = HTP_OP_GLU_REGLU; break; + case HTP_OP_UNARY_SIGMOID: glu_op = HTP_OP_GLU_SIGMOID; break; + default: return false; + } + + const ggml_tensor * up = nullptr; + if (!htp_match_consumer(prev, cur, /*commutative=*/ true, &up)) return false; + + const ggml_tensor * gate = prev.src0(); + const ggml_tensor * dst = cur.dst(); + if (htp_inputs_overlap_unsafe(prev, dst, up)) return false; + + prev.opcode = glu_op; + prev.inputs = { gate, up }; + prev.outputs = { dst }; + if (!htp_kparams_solve(sess, prev)) return false; + + prev.fused.push_back(cur.node); + memset(prev.params, 0, sizeof(prev.params)); + return true; +} + +static bool fuse_mul_mul_scalar(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != HTP_OP_MUL || prev.inputs.size() != 2) return false; + + const auto * k0 = prev.kparams(); + const auto * k1 = cur.kparams(); + if (k0->kernel_type != HTP_BINARY_KERNEL_SCALAR || k1->kernel_type != HTP_BINARY_KERNEL_SCALAR) return false; + if (k0->src1_strided || k1->src1_strided) return false; + + const ggml_tensor * src2 = nullptr; + if (!htp_match_consumer(prev, cur, /*commutative=*/ false, &src2)) return false; + + const ggml_tensor * src1 = prev.src1(); + const ggml_tensor * dst = cur.dst(); + if (!ggml_are_same_shape(src1, src2) || !htp_same_shape_and_contiguity(prev.dst(), dst)) return false; + if (htp_inputs_overlap_unsafe(prev, dst, src2)) return false; + + const size_t vtcm_size = htp_session_vtcm_size(sess); + struct htp_binary_kernel_params kparams = *k0; + kparams.src2_size = kparams.src1_size; + kparams.rows_per_buffer = 0; + if (kparams.src1_size > 65536 || kparams.src1_size + kparams.src2_size > vtcm_size) return false; + + struct htp_binary_vtcm_layout L; + htp_binary_vtcm_layout_build(&L, &kparams, vtcm_size); + if (L.rows_per_buffer == 0 || L.total_bytes > vtcm_size) return false; + + kparams.rows_per_buffer = L.rows_per_buffer; + kparams.vtcm_size = L.total_bytes; + + prev.inputs.push_back(src2); + prev.outputs[0] = dst; + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +static bool fuse_binary_nx(const ggml_hexagon_session * sess, htp_opnode & prev, const htp_opnode & cur) { + if (prev.opcode != cur.opcode) return false; + + const uint32_t curr_n = (uint32_t) prev.inputs.size(); + if (curr_n < 2 || curr_n >= HTP_OP_MAX_INPUTS) return false; + + const auto * k0 = prev.kparams(); + const auto * k1 = cur.kparams(); + const bool k0_ok = (k0->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) || + (k0->kernel_type == HTP_BINARY_KERNEL_CHUNKED && !k0->is_scalar); + const bool k1_ok = (k1->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) || + (k1->kernel_type == HTP_BINARY_KERNEL_CHUNKED && !k1->is_scalar); + if (!k0_ok || !k1_ok) return false; + + const bool is_comm = (cur.opcode == HTP_OP_ADD || cur.opcode == HTP_OP_MUL); + const ggml_tensor * new_src = nullptr; + if (!htp_match_consumer(prev, cur, is_comm, &new_src)) return false; + + const ggml_tensor * src0 = prev.inputs[0]; + const ggml_tensor * dst = cur.dst(); + if (!ggml_are_same_shape(src0, prev.inputs[1]) || + !ggml_are_same_shape(src0, new_src) || + !htp_same_shape_and_contiguity(prev.dst(), dst)) { + return false; + } + if (htp_inputs_overlap_unsafe(prev, dst, new_src)) return false; + + const size_t vtcm_size = htp_session_vtcm_size(sess); + struct htp_binary_kernel_params kparams = *k0; + struct htp_binary_vtcm_layout L; + memset(&L, 0, sizeof(L)); + + const uint32_t n_srcs = curr_n + 1; + if (k0->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE || k1->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) { + if (k0->kernel_type != HTP_BINARY_KERNEL_SAME_SHAPE) { + kparams = *k1; + } + kparams.n_srcs = (uint8_t) n_srcs; + kparams.rows_per_buffer = 0; + + auto check_split = [&](const ggml_tensor * t) { + if (src0->ne[2] > 1 && t->nb[2] != t->ne[1] * t->nb[1]) kparams.split_at_ne01 = 1; + if (src0->ne[3] > 1 && t->nb[3] != t->ne[2] * t->nb[2]) kparams.split_at_ne02 = 1; + }; + for (const auto * in : prev.inputs) check_split(in); + check_split(new_src); + check_split(dst); + + htp_binary_vtcm_layout_build(&L, &kparams, vtcm_size); + } + + if (L.rows_per_buffer == 0 || L.total_bytes == 0 || L.total_bytes > vtcm_size) { + bool all_contig = ggml_is_contiguous(new_src) && ggml_is_contiguous(dst); + for (const auto * in : prev.inputs) { + all_contig = all_contig && ggml_is_contiguous(in); + } + if (!all_contig) return false; + + const uint32_t total_elems = (uint32_t) ggml_nelements(src0); + const uint32_t elem_size = (uint32_t) ggml_type_size(src0->type); + const uint32_t max_threads = htp_session_n_threads(sess); + if (!htp_binary_solve_chunked(&L, &kparams, total_elems, elem_size, max_threads, n_srcs, false, vtcm_size)) { + return false; + } + } + + kparams.rows_per_buffer = L.rows_per_buffer; + kparams.vtcm_size = (uint32_t) L.total_bytes; + + prev.inputs.push_back(new_src); + prev.outputs[0] = dst; + prev.fused.push_back(cur.node); + prev.set_kparams(kparams); + return true; +} + +bool htp_fusion_can_stack(const struct ggml_tensor * a) { + if (!a || !a->src[0] || !a->src[1]) return false; + switch (a->op) { + case GGML_OP_MUL_MAT: + if (!htp_fusion_enabled(HTP_FUSE_MUL_MAT_NX)) return false; + if (htp_is_hadamard(a)) return false; + if (a->src[0]->ne[2] != 1 || a->src[0]->ne[3] != 1) return false; + return ggml_is_quantized(a->src[0]->type); + case GGML_OP_MUL_MAT_ID: + if (!htp_fusion_enabled(HTP_FUSE_MUL_MAT_ID_NX)) return false; + return a->src[2] != nullptr && ggml_is_quantized(a->src[0]->type); + default: + return false; + } +} + +bool htp_fusion_can_stack(const struct ggml_tensor * a, const struct ggml_tensor * b) { + if (!htp_fusion_can_stack(b) || a->op != b->op || a->src[1] != b->src[1]) { + return false; + } + if (a->op == GGML_OP_MUL_MAT_ID && a->src[2] != b->src[2]) { + return false; + } + const ggml_tensor * w0 = a->src[0]; + const ggml_tensor * w1 = b->src[0]; + return w0->type == w1->type && w0->ne[0] == w1->ne[0] && w0->ne[2] == w1->ne[2]; +} + +int htp_fusion_max(const struct ggml_cgraph * graph, int idx) { + const int n = graph->n_nodes; + const ggml_op op0 = graph->nodes[idx]->op; + if (op0 != GGML_OP_ADD && op0 != GGML_OP_NORM && op0 != GGML_OP_RMS_NORM) { + return 1; + } + + enum ggml_op ops[HTP_OP_MAX_FUSED]; + ops[0] = op0; + + int f = idx + 1; + while (f < n && f < idx + HTP_OP_MAX_FUSED) { + const ggml_op op = graph->nodes[f]->op; + if (op != GGML_OP_ADD && op != GGML_OP_MUL && op != GGML_OP_SCALE && + op != GGML_OP_NORM && op != GGML_OP_RMS_NORM) { + break; + } + ops[f - idx] = op; + f++; + } + + f -= idx; + for (; f > 1; f--) { + if (ggml_can_fuse(graph, idx, ops, f)) { + break; + } + } + return f; +} + +void htp_fusion_tag_graph(struct ggml_cgraph * graph) { + for (int i = 0; i < graph->n_nodes; i++) { + auto * extra = (htp_tensor_extra *) graph->nodes[i]->extra; + if (!extra) continue; + + extra->flags &= ~HTP_TENSOR_FUSEABLE; + + const ggml_op op = graph->nodes[i]->op; + if ((op == GGML_OP_RMS_NORM || op == GGML_OP_SCALE || op == GGML_OP_REPEAT || + op == GGML_OP_UNARY || op == GGML_OP_ADD || op == GGML_OP_SUB || + op == GGML_OP_MUL || op == GGML_OP_DIV || op == GGML_OP_MUL_MAT_ID || + op == GGML_OP_SSM_CONV || + (op == GGML_OP_MUL_MAT && !htp_is_hadamard(graph->nodes[i]))) && + ggml_node_has_n_uses(graph, i, 1)) { + extra->flags |= HTP_TENSOR_FUSEABLE; + } + } +} + +bool htp_fusion_try_fuse(const struct ggml_hexagon_session * sess, struct htp_opnode & prev, const struct htp_opnode & cur) { + if (!opt_opfusion) return false; + + switch (cur.opcode) { + case HTP_OP_ADD: + return (htp_fusion_enabled(HTP_FUSE_ALLREDUCE_ADD) && fuse_allreduce_add(sess, prev, cur)) || + (htp_fusion_enabled(HTP_FUSE_MUL_MAT_ADD) && fuse_mul_mat_add(sess, prev, cur)) || + (htp_fusion_enabled(HTP_FUSE_BINARY_NX) && fuse_binary_nx(sess, prev, cur)); + case HTP_OP_MUL: + return (htp_fusion_enabled(HTP_FUSE_RMS_NORM_MUL) && fuse_rms_norm_mul(sess, prev, cur)) || + (htp_fusion_enabled(HTP_FUSE_UNARY_MUL_GLU) && fuse_unary_mul_glu(sess, prev, cur)) || + (htp_fusion_enabled(HTP_FUSE_MUL_MUL_SCALAR) && fuse_mul_mul_scalar(sess, prev, cur)) || + (htp_fusion_enabled(HTP_FUSE_BINARY_NX) && fuse_binary_nx(sess, prev, cur)); + case HTP_OP_SUB: + case HTP_OP_DIV: + return htp_fusion_enabled(HTP_FUSE_BINARY_NX) && fuse_binary_nx(sess, prev, cur); + case HTP_OP_SCALE: + return htp_fusion_enabled(HTP_FUSE_RMS_NORM_SCALE) && fuse_rms_norm_scale(sess, prev, cur); + case HTP_OP_UNARY_SILU: + return htp_fusion_enabled(HTP_FUSE_SSM_CONV_SILU) && fuse_ssm_conv_silu(sess, prev, cur); + case HTP_OP_GET_ROWS: + return htp_fusion_enabled(HTP_FUSE_REPEAT_GET_ROWS) && fuse_repeat_get_rows(sess, prev, cur); + case HTP_OP_CPY: + return htp_fusion_enabled(HTP_FUSE_GDN_CPY) && fuse_gdn_cpy(sess, prev, cur); + case HTP_OP_MUL_MAT: + return htp_fusion_enabled(HTP_FUSE_MUL_MAT_NX) && fuse_mul_mat_nx(sess, prev, cur); + case HTP_OP_MUL_MAT_ID: + return htp_fusion_enabled(HTP_FUSE_MUL_MAT_ID_NX) && fuse_mul_mat_id_nx(sess, prev, cur); + default: + return false; + } +} diff --git a/ggml/src/ggml-hexagon/htp-fusion.h b/ggml/src/ggml-hexagon/htp-fusion.h new file mode 100644 index 000000000000..e794c1daa301 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-fusion.h @@ -0,0 +1,33 @@ +#ifndef HTP_FUSION_H +#define HTP_FUSION_H + +#include "htp-common.h" + +enum htp_fusion_flags { + HTP_FUSE_ALLREDUCE_ADD = (1 << 1), // 2 + HTP_FUSE_RMS_NORM_MUL = (1 << 2), // 4 + HTP_FUSE_MUL_MAT_ADD = (1 << 3), // 8 + HTP_FUSE_MUL_MAT_NX = (1 << 4), // 16 + HTP_FUSE_MUL_MAT_ID_NX = (1 << 5), // 32 + HTP_FUSE_GDN_CPY = (1 << 6), // 64 + HTP_FUSE_REPEAT_GET_ROWS = (1 << 7), // 128 + HTP_FUSE_UNARY_MUL_GLU = (1 << 8), // 256 + HTP_FUSE_MUL_MUL_SCALAR = (1 << 9), // 512 + HTP_FUSE_BINARY_NX = (1 << 10), // 1024 + HTP_FUSE_RMS_NORM_SCALE = (1 << 11), // 2048 + HTP_FUSE_SSM_CONV_SILU = (1 << 12), // 4096 +}; + +static inline bool htp_fusion_enabled(int flag) { + if (opt_opfusion <= 0) return false; + if (opt_opfusion == 1) return true; // 1 enables all + return (opt_opfusion & flag) != 0; +} + +bool htp_fusion_can_stack(const struct ggml_tensor * a); +bool htp_fusion_can_stack(const struct ggml_tensor * a, const struct ggml_tensor * b); +int htp_fusion_max(const struct ggml_cgraph * graph, int idx); +void htp_fusion_tag_graph(struct ggml_cgraph * graph); +bool htp_fusion_try_fuse(const struct ggml_hexagon_session * sess, struct htp_opnode & prev, const struct htp_opnode & cur); + +#endif // HTP_FUSION_H diff --git a/ggml/src/ggml-hexagon/htp-kparams.cpp b/ggml/src/ggml-hexagon/htp-kparams.cpp new file mode 100644 index 000000000000..03b5a3b506d3 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-kparams.cpp @@ -0,0 +1,4276 @@ +#define _USE_MATH_DEFINES + +#include "htp-kparams.h" +#include "htp-opnode.h" +#include "ggml-impl.h" + +#include +#include +#include + +#ifndef M_LOG2E +# define M_LOG2E 1.44269504088896340736 +#endif + +htp_op_code htp_op_remap(const struct ggml_tensor * t) { + switch (t->op) { + case GGML_OP_FLASH_ATTN_EXT: return HTP_OP_FLASH_ATTN_EXT; + case GGML_OP_MUL_MAT: return htp_is_hadamard(t) ? HTP_OP_HADAMARD : HTP_OP_MUL_MAT; + case GGML_OP_MUL_MAT_ID: return HTP_OP_MUL_MAT_ID; + case GGML_OP_MUL: return HTP_OP_MUL; + case GGML_OP_ADD: return HTP_OP_ADD; + case GGML_OP_ADD_ID: return HTP_OP_ADD_ID; + case GGML_OP_SUB: return HTP_OP_SUB; + case GGML_OP_DIV: return HTP_OP_DIV; + case GGML_OP_DUP: + case GGML_OP_CPY: + case GGML_OP_CONT: return HTP_OP_CPY; + case GGML_OP_GET_ROWS: return HTP_OP_GET_ROWS; + case GGML_OP_SET_ROWS: return HTP_OP_SET_ROWS; + case GGML_OP_SUM: return HTP_OP_SUM; + case GGML_OP_SUM_ROWS: return HTP_OP_SUM_ROWS; + case GGML_OP_POOL_2D: return HTP_OP_POOL_2D; + case GGML_OP_POOL_1D: return HTP_OP_POOL_1D; + case GGML_OP_ARGSORT: return HTP_OP_ARGSORT; + case GGML_OP_TOP_K: return HTP_OP_TOP_K; + case GGML_OP_ARGMAX: return HTP_OP_ARGMAX; + case GGML_OP_NORM: return HTP_OP_NORM; + case GGML_OP_L2_NORM: return HTP_OP_L2_NORM; + case GGML_OP_RMS_NORM: return HTP_OP_RMS_NORM; + case GGML_OP_CONCAT: return HTP_OP_CONCAT; + case GGML_OP_SCALE: return HTP_OP_SCALE; + case GGML_OP_CLAMP: return HTP_OP_CLAMP; + case GGML_OP_LEAKY_RELU: return HTP_OP_LEAKY_RELU; + case GGML_OP_SQR: return HTP_OP_SQR; + case GGML_OP_SQRT: return HTP_OP_SQRT; + case GGML_OP_LOG: return HTP_OP_UNARY_LOG; + case GGML_OP_SOFT_MAX: return HTP_OP_SOFTMAX; + case GGML_OP_SSM_CONV: return HTP_OP_SSM_CONV; + case GGML_OP_GATED_DELTA_NET: return HTP_OP_GATED_DELTA_NET; + case GGML_OP_ROPE: return HTP_OP_ROPE; + case GGML_OP_REPEAT: return HTP_OP_REPEAT; + case GGML_OP_CUMSUM: return HTP_OP_CUMSUM; + case GGML_OP_FILL: return HTP_OP_FILL; + case GGML_OP_DIAG: return HTP_OP_DIAG; + case GGML_OP_SOLVE_TRI: return HTP_OP_SOLVE_TRI; + case GGML_OP_TRI: return HTP_OP_TRI; + case GGML_OP_PAD: return HTP_OP_PAD; + case GGML_OP_IM2COL: return HTP_OP_IM2COL; + case GGML_OP_IM2COL_3D: return HTP_OP_IM2COL_3D; + case GGML_OP_CONV_2D: return HTP_OP_CONV_2D; + case GGML_OP_CONV_2D_DW: return HTP_OP_CONV_2D_DW; + case GGML_OP_ROLL: return HTP_OP_ROLL; + case GGML_OP_UPSCALE: return HTP_OP_UPSCALE; + + case GGML_OP_UNARY: + switch (ggml_get_unary_op(t)) { + case GGML_UNARY_OP_SILU: return HTP_OP_UNARY_SILU; + case GGML_UNARY_OP_GELU: return HTP_OP_UNARY_GELU; + case GGML_UNARY_OP_GELU_QUICK: return HTP_OP_UNARY_GELU_QUICK; + case GGML_UNARY_OP_GELU_ERF: return HTP_OP_UNARY_GELU_ERF; + case GGML_UNARY_OP_SIGMOID: return HTP_OP_UNARY_SIGMOID; + case GGML_UNARY_OP_NEG: return HTP_OP_UNARY_NEG; + case GGML_UNARY_OP_EXP: return HTP_OP_UNARY_EXP; + case GGML_UNARY_OP_SOFTPLUS: return HTP_OP_UNARY_SOFTPLUS; + case GGML_UNARY_OP_TANH: return HTP_OP_UNARY_TANH; + case GGML_UNARY_OP_ABS: return HTP_OP_UNARY_ABS; + case GGML_UNARY_OP_RELU: return HTP_OP_UNARY_RELU; + case GGML_UNARY_OP_STEP: return HTP_OP_UNARY_STEP; + case GGML_UNARY_OP_CEIL: return HTP_OP_UNARY_CEIL; + case GGML_UNARY_OP_SGN: return HTP_OP_UNARY_SGN; + default: break; + } + break; + + case GGML_OP_GLU: + switch (ggml_get_glu_op(t)) { + case GGML_GLU_OP_REGLU: return HTP_OP_GLU_REGLU; + case GGML_GLU_OP_SWIGLU: return HTP_OP_GLU_SWIGLU; + case GGML_GLU_OP_SWIGLU_OAI: return HTP_OP_GLU_SWIGLU_OAI; + case GGML_GLU_OP_SWIGLU_CLAMP: return HTP_OP_GLU_SWIGLU_CLAMP; + case GGML_GLU_OP_GEGLU: return HTP_OP_GLU_GEGLU; + case GGML_GLU_OP_GEGLU_QUICK: return HTP_OP_GLU_GEGLU_QUICK; + case GGML_GLU_OP_GEGLU_ERF: return HTP_OP_GLU_GEGLU_ERF; + default: break; + } + break; + + default: + break; + } + return HTP_OP_INVALID; +} + +bool htp_rows_stride(const int64_t * ne, const size_t * nb, size_t * stride) { + size_t s = 0, next = 0; + for (int i = 1; i < GGML_MAX_DIMS; i++) { + if (ne[i] == 1) continue; + if (s == 0) { s = nb[i]; next = s * ne[i]; continue; } + if (nb[i] != next) return false; + next *= ne[i]; + } + *stride = s ? s : nb[1]; + return true; +} + +bool htp_matmul_can_collapse(const struct ggml_tensor * src0, const struct ggml_tensor * src1, const struct ggml_tensor * dst) { + size_t s1, sd; + return (dst->op == GGML_OP_MUL_MAT || dst->op == GGML_OP_ADD) && + src0->ne[2] == 1 && src0->ne[3] == 1 && src1->ne[2] * src1->ne[3] > 1 && + src1->nb[0] == ggml_type_size(src1->type) && htp_rows_stride(src1->ne, src1->nb, &s1) && + dst->nb[0] == ggml_type_size(dst->type) && htp_rows_stride(dst->ne, dst->nb, &sd); +} + +ggml_tensor htp_tensor_collapse_rows(const struct ggml_tensor * t) { + size_t stride = 0; + htp_rows_stride(t->ne, t->nb, &stride); + ggml_tensor c = *t; + c.ne[1] = t->ne[1] * t->ne[2] * t->ne[3]; + c.ne[2] = 1; + c.ne[3] = 1; + c.nb[1] = stride; + c.nb[2] = c.nb[1] * c.ne[1]; + c.nb[3] = c.nb[2]; + return c; +} + +bool htp_kparams_solve_allreduce( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * dst, + uint32_t rank, + uint32_t n_ranks, + bool has_add, + bool is_row_bcast, + bool is_shard_ok, + struct htp_allreduce_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + kparams->rank = (int32_t) rank; + kparams->n_ranks = (int32_t) n_ranks; + kparams->is_row_bcast = (has_add && is_row_bcast) ? 1 : 0; + + const uint32_t max_threads = htp_session_n_threads(sess); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + const uint32_t nelem = (uint32_t) ggml_nelements(dst); + const uint32_t elem_size = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); + const bool is_contiguous = ggml_is_contiguous(dst); + + const uint32_t ne0 = (uint32_t) dst->ne[0]; + const uint32_t ne1 = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); + kparams->ne0 = (int32_t) ne0; + kparams->ne1 = (int32_t) ne1; + + const bool use_1d = is_contiguous && !(has_add && is_row_bcast && ne1 > 1); + + if (has_add) { + if (opt_ar_scatter && is_shard_ok && use_1d && !is_row_bcast) { + const uint32_t rank_chunk_elems = hex_round_up((nelem + n_ranks - 1) / n_ranks, 128); + const uint32_t rank_elem_start = (std::min)(rank * rank_chunk_elems, nelem); + const uint32_t rank_elem_end = (std::min)(rank_elem_start + rank_chunk_elems, nelem); + kparams->n_dsts = (int32_t) n_ranks; + kparams->rank_elem_start = (int32_t) rank_elem_start; + kparams->rank_nelem = (int32_t) (rank_elem_end - rank_elem_start); + } else if (use_1d) { + kparams->n_dsts = 1; + kparams->rank_elem_start = 0; + kparams->rank_nelem = (int32_t) nelem; + } else { + kparams->n_dsts = 1; + kparams->rank_elem_start = 0; + kparams->rank_nelem = (int32_t) ne1; + } + } else { + kparams->n_dsts = (int32_t) n_ranks; + if (use_1d) { + const uint32_t rank_chunk_elems = hex_round_up((nelem + n_ranks - 1) / n_ranks, 128); + const uint32_t rank_elem_start = (std::min)(rank * rank_chunk_elems, nelem); + const uint32_t rank_elem_end = (std::min)(rank_elem_start + rank_chunk_elems, nelem); + const uint32_t rank_nelem = rank_elem_end - rank_elem_start; + kparams->rank_elem_start = (int32_t) rank_elem_start; + kparams->rank_nelem = (int32_t) rank_nelem; + } else { + const uint32_t rank_chunk_rows = (ne1 + n_ranks - 1) / n_ranks; + const uint32_t rank_r0 = (std::min)(rank * rank_chunk_rows, ne1); + const uint32_t rank_r1 = (std::min)(rank_r0 + rank_chunk_rows, ne1); + const uint32_t rank_nrows = rank_r1 - rank_r0; + kparams->rank_elem_start = (int32_t) rank_r0; + kparams->rank_nelem = (int32_t) rank_nrows; + } + } + + kparams->mode = (kparams->n_dsts > 1) ? HTP_ALLREDUCE_SHARDED_FANOUT : HTP_ALLREDUCE_FULL; + + if (use_1d) { + const uint32_t rank_nelem = (uint32_t) kparams->rank_nelem; + const uint32_t n_threads = (std::min)(max_threads, (std::max)(1u, rank_nelem / 128)); + kparams->n_threads = n_threads; + const size_t n_vtcm_buffers = htp_allreduce_vtcm_buffer_count(n_ranks, n_threads, has_add, is_row_bcast); + + uint32_t block_elems = 65536; + if (block_elems > rank_nelem / n_threads && rank_nelem / n_threads > 128) { + block_elems = hex_round_up(rank_nelem / (n_threads * 2), 128); + } + block_elems = (std::max)(128u, block_elems); + + kparams->block_elems = block_elems; + kparams->vtcm_size_per_thread = 2 * block_elems * elem_size; + kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; + + while ((size_t) kparams->vtcm_size > vtcm_size && block_elems > 128) { + const size_t max_bytes_per_buf = vtcm_size / (n_vtcm_buffers * 2); + block_elems = (uint32_t) hex_align_down((size_t) (max_bytes_per_buf / elem_size), 128); + if (block_elems < 128) break; + kparams->block_elems = block_elems; + kparams->vtcm_size_per_thread = 2 * block_elems * elem_size; + kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; + } + + if (vtcm_size < (size_t) kparams->vtcm_size || block_elems < 128) { + HEX_VERBOSE("ggml-hex: %s allreduce 1D solver failed to fit VTCM (%d > %zu)\n", + htp_session_name(sess), kparams->vtcm_size, vtcm_size); + return false; + } + + kparams->elems_per_thread = hex_round_up((rank_nelem + n_threads - 1) / n_threads, block_elems); + kparams->kernel_type = HTP_ALLREDUCE_KERNEL_DMA_1D; + return true; + } else { + const uint32_t rank_nrows = (uint32_t) kparams->rank_nelem; + const uint32_t n_threads = (std::min)(max_threads, (std::max)(1u, rank_nrows)); + kparams->n_threads = n_threads; + const size_t n_vtcm_buffers = htp_allreduce_vtcm_buffer_count(n_ranks, n_threads, has_add, is_row_bcast); + + const uint32_t row_bytes = ne0 * elem_size; + const uint32_t row_size_aligned = (uint32_t) hex_align_up(row_bytes, 128); + kparams->row_size_aligned = row_size_aligned; + + const uint32_t nrows_per_thread = (rank_nrows + n_threads - 1) / n_threads; + uint32_t block_rows = (std::min)(128u, nrows_per_thread); + block_rows = (std::max)(1u, block_rows); + kparams->block_elems = block_rows; + + kparams->vtcm_size_per_thread = 2 * (block_rows * row_size_aligned); + kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; + + while ((size_t) kparams->vtcm_size > vtcm_size && block_rows > 1) { + const size_t max_rows_per_buf = vtcm_size / (n_vtcm_buffers * 2 * row_size_aligned); + block_rows = (std::max)(1u, (uint32_t) max_rows_per_buf); + kparams->block_elems = block_rows; + kparams->vtcm_size_per_thread = 2 * (block_rows * row_size_aligned); + kparams->vtcm_size = n_vtcm_buffers * kparams->vtcm_size_per_thread; + if (max_rows_per_buf == 0) break; + } + + if (vtcm_size < (size_t) kparams->vtcm_size || block_rows < 1) { + HEX_VERBOSE("ggml-hex: %s allreduce 2D solver failed to fit VTCM (%d > %zu)\n", + htp_session_name(sess), kparams->vtcm_size, vtcm_size); + return false; + } + + kparams->elems_per_thread = nrows_per_thread; + kparams->kernel_type = HTP_ALLREDUCE_KERNEL_DMA_2D; + return true; + } +} + +static bool htp_flash_attn_is_hmx_eligible( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * q, + const struct ggml_tensor * k, + const struct ggml_tensor * v, + const struct ggml_tensor * sinks +) { + if (htp_session_n_hmx(sess) == 0 || opt_fa_select < 2) { + return false; + } + + if ((k->type != GGML_TYPE_F16 && k->type != GGML_TYPE_Q8_0) || + (v->type != GGML_TYPE_F16 && v->type != GGML_TYPE_Q8_0)) { + return false; + } + + const uint32_t DK = q->ne[0]; + const uint32_t DV = v->ne[0]; + + if (DK % 8 != 0 || DV % 8 != 0) { + return false; + } + + GGML_UNUSED(sinks); + + if (opt_fa_select > 2) { + return true; + } + + const uint32_t M = q->ne[1]; + if (M > 1) { + return true; + } + + const uint32_t n_threads = htp_session_n_threads(sess); + const uint32_t n_head = q->ne[2]; + const uint32_t n_kv_heads = k->ne[2]; + const uint32_t G = n_kv_heads > 0 ? n_head / n_kv_heads : 1; + const uint32_t S = k->ne[1]; + const uint32_t total_threads = n_threads * htp_session_mdev_count(sess); + + if (DK > 256 || (DK == 256 && (DV > 256 || n_kv_heads < total_threads))) { + return true; + } + + const bool is_tile_aligned = (G > 0 && (32 % G == 0)); + if (!is_tile_aligned) { + if (n_threads >= 6) { + return false; + } + return S >= 1024; + } + + uint32_t s_cross = 512; + if (DK == 256) { + s_cross = 4096; + } else if (DK <= 64) { + s_cross = (n_threads >= 8) ? 2048 : ((n_threads >= 6) ? 768 : 512); + } else { + s_cross = (n_threads >= 8) ? 1024 : 512; + } + + return S >= s_cross; +} + +static bool htp_kparams_solve_flash_attn( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_fa_kernel_params * kparams +) { + if (opt_fa_select < 1) { + return false; + } + + // K/V row lists (ggml_flash_attn_ext_rows) are not supported + if (op->src[5] != nullptr) { + return false; + } + + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * q = op->src[0]; + const struct ggml_tensor * k = op->src[1]; + const struct ggml_tensor * v = op->src[2]; + const struct ggml_tensor * mask = op->src[3]; + const struct ggml_tensor * sinks = op->src[4]; + const struct ggml_tensor * dst = op; + + if ((q->type != GGML_TYPE_F16 && q->type != GGML_TYPE_F32) || + (k->type != GGML_TYPE_F16 && k->type != GGML_TYPE_Q8_0) || + (v->type != GGML_TYPE_F16 && v->type != GGML_TYPE_Q8_0)) { + return false; + } + if (mask && mask->type != GGML_TYPE_F16) { + return false; + } + if (sinks && sinks->type != GGML_TYPE_F32) { + return false; + } + if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16) { + return false; + } + + const uint32_t n_threads = htp_session_n_threads(sess); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + const uint32_t neq0 = q->ne[0]; + const uint32_t neq1 = q->ne[1]; + const uint32_t neq2 = q->ne[2]; + const uint32_t nek1 = k->ne[1]; + const uint32_t nev0 = v->ne[0]; + + const uint32_t DK = neq0; + const uint32_t DV = nev0; + + const uint32_t n_kv_heads = k->ne[2]; + const uint32_t G = neq2 / n_kv_heads; + + float scale = 1.0f; + float max_bias = 0.0f; + float logit_softcap = 0.0f; + memcpy(&scale, &op->op_params[0], sizeof(float)); + memcpy(&max_bias, &op->op_params[1], sizeof(float)); + memcpy(&logit_softcap, &op->op_params[2], sizeof(float)); + + if (logit_softcap != 0.0f) { + scale /= logit_softcap; + } + + kparams->scale = scale; + kparams->max_bias = max_bias; + kparams->logit_softcap = logit_softcap; + kparams->head_split = (opt_fa_split != 0) ? 1 : 0; + kparams->flags = 0; + kparams->G = G; + + // team-split only when a team has >1 member (n_kv_heads < N_cores) + uint32_t fa_teams = 1, fa_team_size = 1; + const uint32_t mdev_count = htp_session_mdev_count(sess); + if (opt_fa_split && mdev_count > 1) { + htp_fa_mdev_teams(n_kv_heads, mdev_count, kparams->head_split != 0, &fa_teams, &fa_team_size); + if (fa_team_size > 1) { + kparams->flags |= HTP_FA_FLAG_TEAM_SPLIT; + } + } + + const uint32_t n_head = q->ne[2]; + kparams->n_head_log2 = 1u << (uint32_t) std::floor(std::log2(n_head)); + kparams->m0 = std::pow(2.0f, -(max_bias) / kparams->n_head_log2); + kparams->m1 = std::pow(2.0f, -(max_bias / 2.0f) / kparams->n_head_log2); + + if (htp_flash_attn_is_hmx_eligible(sess, q, k, v, sinks)) { + const uint32_t DK_pad = hex_round_up(DK, 64); + const uint32_t DV_pad = hex_round_up(DV, 64); + size_t Br = 0, Bc = 0; + int ret = hmx_fa_find_chunk_size(&Br, &Bc, G, DK_pad, DV_pad, neq1, nek1, vtcm_size, n_threads, (q->type == GGML_TYPE_F32), sinks != nullptr, n_head, fa_team_size); + if (ret == 0) { + kparams->kernel_type = HTP_FA_KERNEL_HMX; + if (logit_softcap == 0.0f) { + kparams->scale = scale * (float) M_LOG2E; + kparams->logit_softcap = 0.0f; + } else { + kparams->scale = scale; + kparams->logit_softcap = logit_softcap * (float) M_LOG2E; + } + kparams->Br = Br; + kparams->Bc = Bc; + kparams->n_kv_blocks = (nek1 + Bc - 1) / Bc; + kparams->n_threads = (kparams->n_kv_blocks >= 3 && n_threads >= 2) ? n_threads : 1; + kparams->u.hmx.g_br = hex_align_up(G * Br, 32); + kparams->u.hmx.pipeline = (kparams->n_kv_blocks >= 3 && n_threads >= 2) ? 1 : 0; + kparams->vtcm_size = hmx_fa_compute_vtcm_usage(G, DK_pad, DV_pad, Br, Bc, kparams->n_threads, kparams->u.hmx.pipeline != 0, (q->type == GGML_TYPE_F32), sinks != nullptr, n_head); + kparams->u.hmx.mask_broadcast = (mask != nullptr && mask->ne[2] == 1) ? 1 : 0; + kparams->u.hmx.div_G = init_fastdiv_values(G); + if (mask) { + kparams->src3_div2 = init_fastdiv_values(mask->ne[2]); + kparams->src3_div3 = init_fastdiv_values(mask->ne[3]); + } + return true; + } + } + + kparams->kernel_type = HTP_FA_KERNEL_HVX; + kparams->Br = 1; + kparams->Bc = 64; + kparams->n_kv_blocks = (k->ne[1] + 64 - 1) / 64; + kparams->n_threads = n_threads; + + const size_t size_q_row_padded = hex_round_up(q->ne[0] * ((q->type == GGML_TYPE_F32) ? 4 : 2), 128); + const size_t size_k_row_padded = hex_round_up(k->ne[0] * 2, 128); + const size_t size_v_row_padded = hex_round_up(v->ne[0] * 2, 128); + + kparams->vtcm_size = hvx_fa_compute_vtcm_usage(DK, DV, (q->type == GGML_TYPE_F32), mask != nullptr, sinks != nullptr, n_head, n_threads); + if ((size_t) kparams->vtcm_size > vtcm_size) { + HEX_VERBOSE("ggml-hex: skip flash_attn_ext because VTCM needed (%d) > budget (%zu)\n", + kparams->vtcm_size, vtcm_size); + return false; + } + + kparams->u.hvx.size_q_row_padded = size_q_row_padded; + kparams->u.hvx.size_k_row_padded = size_k_row_padded; + kparams->u.hvx.size_v_row_padded = size_v_row_padded; + kparams->u.hvx.src0_div21 = init_fastdiv_values(q->ne[2] * q->ne[1]); + kparams->u.hvx.src0_div1 = init_fastdiv_values(q->ne[1]); + kparams->broadcast_rk2 = init_fastdiv_values(q->ne[2] / k->ne[2]); + kparams->broadcast_rk3 = init_fastdiv_values(q->ne[3] / k->ne[3]); + kparams->broadcast_rv2 = init_fastdiv_values(q->ne[2] / v->ne[2]); + kparams->broadcast_rv3 = init_fastdiv_values(q->ne[3] / v->ne[3]); + if (mask) { + kparams->src3_div2 = init_fastdiv_values(mask->ne[2]); + kparams->src3_div3 = init_fastdiv_values(mask->ne[3]); + } + + return true; +} + +static bool htp_kparams_solve_gated_delta_net( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_gdn_kernel_params * kparams +) { + if (opt_gdn_select < 1) { + return false; + } + + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * q = op->src[0]; + const struct ggml_tensor * k = op->src[1]; + const struct ggml_tensor * v = op->src[2]; + const struct ggml_tensor * g = op->src[3]; + const struct ggml_tensor * beta = op->src[4]; + const struct ggml_tensor * state = op->src[5]; + const struct ggml_tensor * dst = op; + + if (q->type != GGML_TYPE_F32 || k->type != GGML_TYPE_F32 || v->type != GGML_TYPE_F32 || + g->type != GGML_TYPE_F32 || beta->type != GGML_TYPE_F32 || state->type != GGML_TYPE_F32 || + dst->type != GGML_TYPE_F32) { + return false; + } + + if (!ggml_is_contiguous_rows(q) || !ggml_is_contiguous_rows(k) || !ggml_is_contiguous_rows(v) || + !ggml_is_contiguous(g) || !ggml_is_contiguous(beta) || !ggml_is_contiguous(state) || + !ggml_is_contiguous(dst)) { + return false; + } + + const int64_t S_v = v->ne[0]; + const int64_t H = v->ne[1]; + const int64_t n_tokens = v->ne[2]; + const int64_t n_seqs = v->ne[3]; + const int64_t K = ggml_get_op_params_i32(op, 0); + + if (S_v <= 0 || S_v > 128 || H <= 0 || n_tokens <= 0 || n_seqs <= 0) { + return false; + } + if (q->ne[0] != S_v || k->ne[0] != S_v || q->ne[1] <= 0 || k->ne[1] <= 0 || + q->ne[2] != n_tokens || k->ne[2] != n_tokens || q->ne[3] <= 0 || k->ne[3] <= 0 || + (n_seqs % q->ne[3]) != 0 || (n_seqs % k->ne[3]) != 0) { + return false; + } + if ((g->ne[0] != 1 && g->ne[0] != S_v) || beta->ne[0] != 1) { + return false; + } + if (state->ne[0] != S_v || state->ne[1] != S_v || state->ne[2] != H || state->ne[3] != n_seqs) { + return false; + } + if (dst->ne[0] != S_v * H || dst->ne[1] != n_tokens * n_seqs + S_v * n_seqs * K || + dst->ne[2] != 1 || dst->ne[3] != 1) { + return false; + } + + const uint32_t rq3 = (uint32_t) (n_seqs / q->ne[3]); + const uint32_t rk3 = (uint32_t) (n_seqs / k->ne[3]); + const uint32_t total_rows = (uint32_t) (H * n_seqs); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), total_rows); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + const bool can_use_hmx = (opt_gdn_select >= 2) && + (htp_session_n_hmx(sess) > 0) && + (S_v % 64 == 0) && + (n_tokens >= HTP_GDN_MIN_TOKENS) && + (g->ne[0] == 1) && + (K == 1); + + struct htp_gdn_hmx_vtcm_layout hmx_layout; + struct htp_gdn_vtcm_layout hvx_layout; + uint32_t n_heads_batch = 1; + + if (can_use_hmx && htp_gdn_hmx_solve_layout(&hmx_layout, (uint32_t) S_v, HTP_GDN_CHUNK_SIZE, total_rows, vtcm_size, n_threads, true, &n_heads_batch)) { + kparams->kernel_type = HTP_GDN_KERNEL_HMX_CHUNKED; + kparams->pipeline = hmx_layout.pipeline ? 1 : 0; + kparams->chunk_size = HTP_GDN_CHUNK_SIZE; + kparams->n_chunks = ((uint32_t) n_tokens + HTP_GDN_CHUNK_SIZE - 1) / HTP_GDN_CHUNK_SIZE; + kparams->n_heads_batch = (uint16_t) n_heads_batch; + kparams->vtcm_size = (uint32_t) hmx_layout.total_bytes; + } else { + htp_gdn_vtcm_layout_build(&hvx_layout, (uint32_t) S_v, n_threads); + if (hvx_layout.total_bytes > vtcm_size) { + return false; + } + kparams->kernel_type = HTP_GDN_KERNEL_HVX_RECURRENT; + kparams->pipeline = 0; + kparams->n_heads_batch = 1; + kparams->vtcm_size = (uint32_t) hvx_layout.total_bytes; + } + + kparams->n_threads = n_threads; + kparams->S_v = (uint32_t) S_v; + kparams->H = (uint32_t) H; + kparams->n_tokens = (uint32_t) n_tokens; + kparams->n_seqs = (uint32_t) n_seqs; + kparams->K = (uint32_t) K; + kparams->total_rows = total_rows; + kparams->kda = (g->ne[0] == S_v) ? 1 : 0; + kparams->state_seq_stride = (uint32_t) (state->nb[3] / sizeof(float)); + kparams->state_size_per_snap = (uint32_t) (S_v * S_v * H * n_seqs); + kparams->scale = 1.0f / sqrtf((float) S_v); + + if (H > 0) kparams->div_H = init_fastdiv_values((uint32_t) H); + if (q->ne[1] > 0) kparams->div_q1 = init_fastdiv_values((uint32_t) q->ne[1]); + if (k->ne[1] > 0) kparams->div_k1 = init_fastdiv_values((uint32_t) k->ne[1]); + if (rq3 > 0) kparams->div_rq3 = init_fastdiv_values(rq3); + if (rk3 > 0) kparams->div_rk3 = init_fastdiv_values(rk3); + return true; +} + +static bool htp_matmul_is_hmx_eligible( + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + bool is_matmul_id, + bool is_batched +) { + GGML_UNUSED(dst); + + if (src1->type != GGML_TYPE_F32 && (src1->type != GGML_TYPE_F16 || is_matmul_id)) { + return false; + } + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int wtype = src0->type; + + if (ne01 % HTP_TENSOR_TILE_N_ROWS != 0 && is_matmul_id) { + return false; + } + + if (!htp_is_hmx_weight_type((ggml_type) wtype)) { + return false; + } + + if (ne00 % HTP_TENSOR_TILE_N_COLS != 0) { + return false; + } + + const bool is_tiled = htp_tensor_is_tiled(src0); + if (ggml_is_quantized((ggml_type) wtype) && !is_tiled) { + return false; + } + if (!is_matmul_id && is_batched && is_tiled) { + return false; + } + + if (src0->nb[0] > src0->nb[1] || src1->nb[0] > src1->nb[1]) { + return false; + } + + const int m = is_matmul_id ? ne12 : ne11; + if (m <= HTP_MM_HMX_MIN_NROWS) { + return false; + } + + return true; +} + +static bool htp_kparams_solve_hmx_mm( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * act, + const struct ggml_tensor * dst, + int wtype, + int ne00_padded, + int ne01_padded, + int ne02, + int ne11, + int ne12, + int ne11_padded, + bool is_matmul_id, + bool is_batched, + size_t src2_size, + size_t vtcm_budget, + struct htp_mm_kernel_params * kparams +) { + const bool is_tiled = htp_tensor_is_tiled(src0); + const int aligned_tile_size = is_tiled ? htp_tensor_get_tile_padded_size(wtype) : 0; + const int n_threads = (int) htp_session_n_threads(sess); + const uint32_t mdev_count = htp_session_mdev_count(sess); + const int ne10 = act->ne[0]; + + int m_for_solver = ne11; + int m_for_solver_padded = ne11_padded; + if (!is_matmul_id && mdev_count > 1 && ((uint32_t) ne11 >= mdev_count)) { + const bool dst_row_split = dst ? htp_can_row_partition(dst) : true; + const bool act_row_split = htp_can_row_partition(act); + if (dst_row_split && act_row_split) { + m_for_solver = (ne11 + (int) mdev_count - 1) / (int) mdev_count; + m_for_solver_padded = hex_round_up(std::max(m_for_solver, 32), 32); + } + } + const bool pipeline = is_matmul_id ? false : htp_mm_hmx_pipeline(m_for_solver); + const bool is_batched_val = is_matmul_id ? false : is_batched; + const int group_size = (ne02 > 0 ? ne12 / ne02 : 1); + + size_t m_chunk = 0; + size_t n_chunk = 0; + size_t vtcm_size = 0; + bool use_grouped = false; + int act_threads_selected = 0; + + if (is_batched_val && wtype == GGML_TYPE_F16 && !is_tiled && group_size > 1) { + if (htp_mm_hmx_solve_batched_params(wtype, ne00_padded, ne01_padded, m_for_solver, group_size, n_threads, pipeline, src2_size, vtcm_budget, &m_chunk, &n_chunk, &act_threads_selected, &vtcm_size)) { + use_grouped = true; + } + } + + if (!use_grouped) { + int m_id_rows = 0; + if (dst && is_matmul_id) { + const int n_experts = ne02 > 0 ? ne02 : 1; + const size_t total_expert_rows = (size_t) dst->ne[1] * dst->ne[2]; + int m_per_expert = (int) ((total_expert_rows + n_experts - 1) / n_experts); + if (mdev_count > 1 && htp_can_row_partition(dst)) { + m_per_expert = (m_per_expert + (int) mdev_count - 1) / (int) mdev_count; + } + m_id_rows = hex_round_up(std::max(m_per_expert, 32), 32); + } + const uint32_t cost_m = is_matmul_id ? (uint32_t) m_id_rows : (uint32_t) m_for_solver; + if (!htp_mm_hmx_solve_2d_params(wtype, ne00_padded, m_id_rows, ne01_padded, m_for_solver_padded, cost_m, n_threads, pipeline, is_matmul_id, aligned_tile_size, src2_size, vtcm_budget, &m_chunk, &n_chunk, &act_threads_selected, &vtcm_size)) { + return false; + } + } + + kparams->n_hmx = 1; + kparams->pipeline = pipeline ? 1 : 0; + kparams->m_chunk = m_chunk; + kparams->n_chunk = n_chunk; + kparams->n_threads = n_threads; + kparams->n_act_threads = act_threads_selected; + kparams->tile_size = is_tiled ? htp_tensor_get_tile_size(wtype) : 0; + kparams->aligned_tile_size = aligned_tile_size; + kparams->act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); + kparams->vtcm_size = vtcm_size; + kparams->div_n_act_threads = init_fastdiv_values(act_threads_selected); + kparams->div_ne00_padded = init_fastdiv_values(ne00_padded); + kparams->vtcm_bias_size = (int32_t) src2_size; + kparams->kernel_type = (is_batched && !is_matmul_id) ? HTP_MM_KERNEL_HMX_BATCHED : HTP_MM_KERNEL_HMX_2D; + return true; +} + +static void htp_kparams_solve_hvx_mm( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + int wtype, + bool is_tiled, + int ne02, + int ne03, + int ne10, + int ne11, + int ne12, + int ne13, + bool is_matmul_id, + const size_t src2_row_size, + size_t vtcm_budget, + struct htp_mm_kernel_params * kparams +) { + if (opt_mm_select < 1) { + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return; + } + + const uint32_t n_threads = htp_session_n_threads(sess); + kparams->n_hmx = 0; + kparams->n_threads = n_threads; + + GGML_UNUSED(ne02); + GGML_UNUSED(ne03); + + const int src1_nrows = ne11 * ne12 * ne13; + + if (is_tiled) { + kparams->tile_size = htp_tensor_get_tile_size(wtype); + kparams->aligned_tile_size = htp_tensor_get_tile_padded_size(wtype); + + const bool k_align = (ne10 % htp_tensor_get_tile_k(wtype) == 0); + + if (is_matmul_id) { + kparams->kernel_type = (src1_nrows < (int) n_threads) + ? HTP_MM_KERNEL_HVX_QUANT_BLOCK : HTP_MM_KERNEL_HVX_QUANT_ROW; + kparams->act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); + + struct htp_mm_hvx_vtcm_layout L; + uint32_t max_prefetch = (src1_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; + uint32_t best_n_prefetch = 2; + for (uint32_t d = max_prefetch; d >= 2; d /= 2) { + htp_mm_hvx_vtcm_layout_build( + &L, kparams->kernel_type, wtype, ne10, src1_nrows, n_threads, + 0, src0->nb[1], kparams->act_row_size, 0, d, true, false + ); + if (L.total_bytes <= vtcm_budget) { + best_n_prefetch = d; + break; + } + } + if (L.total_bytes > vtcm_budget) { + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return; + } + kparams->n_prefetch = best_n_prefetch; + kparams->vtcm_size = L.total_bytes; + kparams->vtcm_bias_size = 0; + return; + } else { + if (k_align && opt_mm_select >= 1) { + kparams->act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); + kparams->kernel_type = (src1_nrows < (int) n_threads) + ? HTP_MM_KERNEL_HVX_QUANT_BLOCK : HTP_MM_KERNEL_HVX_QUANT_ROW; + + struct htp_mm_hvx_vtcm_layout L; + uint32_t max_prefetch = (src1_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; + uint32_t best_n_prefetch = 2; + for (uint32_t d = max_prefetch; d >= 2; d /= 2) { + htp_mm_hvx_vtcm_layout_build( + &L, kparams->kernel_type, wtype, ne10, src1_nrows, n_threads, + dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, d, false, false + ); + if (L.total_bytes <= vtcm_budget) { + best_n_prefetch = d; + break; + } + } + + uint32_t m_chunk = 0; + if (htp_mm_hvx_solve_vtcm_params( + kparams->kernel_type, wtype, ne10, src1_nrows, n_threads, + dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, best_n_prefetch, vtcm_budget, + &L, &m_chunk)) { + kparams->n_prefetch = best_n_prefetch; + kparams->m_chunk = (m_chunk < (uint32_t) src1_nrows) ? m_chunk : 0; + kparams->vtcm_size = L.total_bytes; + kparams->vtcm_bias_size = L.bias_bytes; + return; + } + } + + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return; + } + } else if (is_matmul_id) { + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return; + } else if (wtype == GGML_TYPE_F16 || wtype == GGML_TYPE_F32 || wtype == GGML_TYPE_BF16) { + int32_t ktype = HTP_MM_KERNEL_HVX_F16_F16_VTCM; + int32_t act_elem = 2; + if (wtype == GGML_TYPE_F32) { + ktype = HTP_MM_KERNEL_HVX_F32_F32_VTCM; + act_elem = 4; + } else if (wtype == GGML_TYPE_BF16) { + ktype = HTP_MM_KERNEL_HVX_BF16_F32_VTCM; + act_elem = 4; + } + struct htp_mm_hvx_vtcm_layout L; + uint32_t m_chunk = 0; + if (htp_mm_hvx_solve_vtcm_params( + ktype, wtype, ne10, src1_nrows, n_threads, + dst->nb[1], src0->nb[1], src1->nb[1], src2_row_size, 16, vtcm_budget, + &L, &m_chunk)) { + kparams->kernel_type = ktype; + kparams->m_chunk = (m_chunk < (uint32_t) src1_nrows) ? m_chunk : 0; + kparams->act_row_size = hex_round_up(ne10 * act_elem, 128); + kparams->vtcm_size = L.total_bytes; + kparams->vtcm_bias_size = L.bias_bytes; + kparams->n_prefetch = 16; + return; + } + } + + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; +} + +static bool htp_kparams_solve_matmul_impl( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + const size_t src2_row_size, + const size_t src2_size, + struct htp_mm_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; + + const bool is_tiled = htp_tensor_is_tiled(src0); + const int wtype = (is_tiled && (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_BF16)) ? GGML_TYPE_F16 : src0->type; + const int ne00_padded = is_tiled ? hex_round_up(ne00, htp_tensor_get_tile_k(wtype)) : ne00; + const int ne11_padded = hex_round_up(ne11, 32); + const int ne01_tiled = hex_round_up(ne01, 32); + + const bool is_matmul_id = (dst->op == GGML_OP_MUL_MAT_ID); + const bool is_batched = (ne02 * ne03 > 1 || ne12 * ne13 > 1); + const size_t vtcm_budget = htp_session_vtcm_size(sess); + + const bool hmx_enabled = (htp_session_n_hmx(sess) > 0) && (opt_mm_select >= 2); + if (hmx_enabled && htp_matmul_is_hmx_eligible(src0, src1, dst, is_matmul_id, is_batched)) { + if (htp_kparams_solve_hmx_mm(sess, src0, src1, dst, wtype, ne00_padded, ne01_tiled, ne02, ne11, ne12, ne11_padded, is_matmul_id, is_batched, src2_size, vtcm_budget, kparams)) { + goto finalize; + } + } + + htp_kparams_solve_hvx_mm(sess, src0, src1, dst, wtype, is_tiled, ne02, ne03, ne10, ne11, ne12, ne13, is_matmul_id, src2_row_size, vtcm_budget, kparams); + +finalize: + kparams->div_ne12_ne1 = init_fastdiv_values(ne12 * ne11); + kparams->div_ne1 = init_fastdiv_values(ne11); + kparams->div_r2 = init_fastdiv_values(ne02 > 0 ? ne12 / ne02 : 1); + kparams->div_r3 = init_fastdiv_values(ne03 > 0 ? ne13 / ne03 : 1); + kparams->div_ne12 = init_fastdiv_values(ne12); + + if (kparams->kernel_type == HTP_MM_KERNEL_UNSUPPORTED || (size_t) kparams->vtcm_size > vtcm_budget) { + HEX_VERBOSE("ggml-hex: %s supported %s VTCM size needed (%d) > budget (%zu)\n", + htp_session_name(sess), is_matmul_id ? "MUL_MAT_ID" : "MUL_MAT", kparams->vtcm_size, vtcm_budget); + return false; + } + return true; +} + +static bool htp_matmul_check_types( + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst +) { + const bool is_matmul_id = (dst->op == GGML_OP_MUL_MAT_ID); + + if (dst->type != GGML_TYPE_F32) { + return false; + } + + if (is_matmul_id) { + const struct ggml_tensor * src2 = dst->src[2]; + if (src1->type != GGML_TYPE_F32 || !src2 || src2->type != GGML_TYPE_I32) { + return false; + } + if (ggml_get_op_params_i32(dst, 3) == GGML_PREC_F32) { + return false; + } + switch (src0->type) { + case GGML_TYPE_Q1_0: + case GGML_TYPE_Q2_0: + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q8_0: + case GGML_TYPE_IQ4_NL: + case GGML_TYPE_MXFP4: + case GGML_TYPE_Q4_K: + case GGML_TYPE_Q5_K: + case GGML_TYPE_Q6_K: + case GGML_TYPE_Q3_K: + case GGML_TYPE_Q2_K: + if (!ggml_is_contiguous(src0) || ggml_is_permuted(src0) || ggml_is_view(src0)) { + return false; + } + if (src0->ne[0] % ggml_blck_size(src0->type) != 0) { + return false; + } + return true; + + case GGML_TYPE_F16: + case GGML_TYPE_F32: + case GGML_TYPE_BF16: + if (!ggml_is_contiguous(src0) || ggml_is_permuted(src0)) { + return false; + } + return src0->ne[0] % 32 == 0; + + default: + return false; + } + } + + if (src1->type != GGML_TYPE_F32 && src1->type != GGML_TYPE_F16) { + return false; + } + if (src1->ne[2] < src0->ne[2] || src1->ne[3] < src0->ne[3] || + src1->ne[2] % src0->ne[2] != 0 || src1->ne[3] % src0->ne[3] != 0) { + return false; + } + + switch (src0->type) { + case GGML_TYPE_Q1_0: + case GGML_TYPE_Q2_0: + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q8_0: + case GGML_TYPE_IQ4_NL: + case GGML_TYPE_MXFP4: + case GGML_TYPE_Q4_K: + case GGML_TYPE_Q5_K: + case GGML_TYPE_Q6_K: + case GGML_TYPE_Q3_K: + case GGML_TYPE_Q2_K: + if (!ggml_is_contiguous(src0) || ggml_is_permuted(src0) || ggml_is_view(src0)) { + return false; + } + return src0->ne[0] % ggml_blck_size(src0->type) == 0; + + case GGML_TYPE_F32: + if (src1->type != GGML_TYPE_F32) { + return false; + } + return src0->nb[1] >= src0->nb[0]; + + case GGML_TYPE_F16: + case GGML_TYPE_BF16: + return src0->nb[1] >= src0->nb[0]; + + default: + return false; + } +} + +static bool htp_kparams_solve_matmul( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_mm_kernel_params * kparams +) { + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (!htp_matmul_check_types(src0, src1, dst)) { + return false; + } + if (htp_matmul_can_collapse(src0, src1, dst)) { + const ggml_tensor src1_collapsed = htp_tensor_collapse_rows(src1); + const ggml_tensor dst_collapsed = htp_tensor_collapse_rows(dst); + return htp_kparams_solve_matmul_impl(sess, src0, &src1_collapsed, &dst_collapsed, 0, 0, kparams); + } + return htp_kparams_solve_matmul_impl(sess, src0, src1, dst, 0, 0, kparams); +} + +bool htp_matmul_add_can_collapse( + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * src2, + const struct ggml_tensor * dst +) { + if (!htp_matmul_can_collapse(src0, src1, dst)) { + return false; + } + if (!src2) { + return true; + } + const int64_t src2_nrows = src2->ne[1] * src2->ne[2] * src2->ne[3]; + if (src2_nrows == 1) { + return true; + } + size_t s2; + return src2->nb[0] == ggml_type_size(src2->type) && + ggml_are_same_shape(src2, dst) && + htp_rows_stride(src2->ne, src2->nb, &s2); +} + +bool htp_kparams_solve_matmul_add( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * src2, + const struct ggml_tensor * dst, + struct htp_mm_kernel_params * kparams +) { + if (htp_matmul_add_can_collapse(src0, src1, src2, dst)) { + const ggml_tensor src1_collapsed = htp_tensor_collapse_rows(src1); + const ggml_tensor dst_collapsed = htp_tensor_collapse_rows(dst); + const ggml_tensor src2_collapsed = (src2 && (src2->ne[1] * src2->ne[2] * src2->ne[3] > 1)) + ? htp_tensor_collapse_rows(src2) + : (src2 ? *src2 : ggml_tensor{}); + const struct ggml_tensor * p_src2 = src2 ? &src2_collapsed : nullptr; + const size_t src2_size = p_src2 ? hex_round_up(ggml_nbytes(p_src2), 128) : 0; + return htp_kparams_solve_matmul_impl(sess, src0, &src1_collapsed, &dst_collapsed, p_src2 ? p_src2->nb[1] : 0, src2_size, kparams); + } + const size_t src2_size = src2 ? hex_round_up(ggml_nbytes(src2), 128) : 0; + return htp_kparams_solve_matmul_impl(sess, src0, src1, dst, src2 ? src2->nb[1] : 0, src2_size, kparams); +} + +bool htp_kparams_solve_mmnx( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * act, + int32_t n_weights, + struct htp_mm_kernel_params * kparams +) { + const uint32_t n_threads = htp_session_n_threads(sess); + const uint32_t n_hmx = htp_session_n_hmx(sess); + const size_t vtcm_budget = htp_session_vtcm_size(sess); + + memset(kparams, 0, sizeof(*kparams)); + kparams->n_threads = n_threads; + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + + const int ne10 = act->ne[0]; + const int ne11 = act->ne[1]; + const int ne12 = act->ne[2]; + const int ne13 = act->ne[3]; + + const bool is_tiled = htp_tensor_is_tiled(src0); + const int wtype = (is_tiled && (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_BF16)) ? GGML_TYPE_F16 : src0->type; + const int ne00_padded = is_tiled ? hex_round_up(ne00, 32) : ne00; + const int ne11_padded = hex_round_up(ne11, 32); + const int ne01_tiled = hex_round_up(ne01, 32); + const bool is_batched = (ne02 * ne03 > 1 || ne12 * ne13 > 1); + + const bool hmx_enabled = (n_hmx > 0) && (opt_mm_select >= 2); + if (hmx_enabled && htp_matmul_is_hmx_eligible(src0, act, nullptr, false, is_batched)) { + if (htp_kparams_solve_hmx_mm(sess, src0, act, nullptr, wtype, ne00_padded, ne01_tiled, ne02, ne11, ne12, ne11_padded, false, is_batched, 0, vtcm_budget, kparams)) { + kparams->n_weights = n_weights; + goto finalize; + } + } + + if (!is_tiled || act->type != GGML_TYPE_F32 || ne10 % 32 != 0) { + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return false; + } + + { + const int act_nrows = ne11 * ne12 * ne13; + const size_t act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); + const size_t src0_row_size = src0->nb[1]; + + const uint32_t max_prefetch = (act_nrows > HTP_MM_HMX_MIN_NROWS) ? 2 : 16; + uint32_t best_n_prefetch = 2; + for (uint32_t d = max_prefetch; d >= 2; d /= 2) { + struct htp_mm_hvx_vtcm_layout L; + htp_mm_hvx_vtcm_layout_build( + &L, HTP_MM_KERNEL_HVX_QUANT_ROW, wtype, ne10, act_nrows, n_threads, + 0, src0_row_size, act_row_size, 0, d, false, true + ); + if (L.total_bytes <= vtcm_budget) { + best_n_prefetch = d; + break; + } + } + + struct htp_mm_hvx_vtcm_layout L; + htp_mm_hvx_vtcm_layout_build( + &L, HTP_MM_KERNEL_HVX_QUANT_ROW, wtype, ne10, act_nrows, n_threads, + 0, src0_row_size, act_row_size, 0, best_n_prefetch, false, true + ); + + if (opt_mm_select >= 1 && L.total_bytes <= vtcm_budget) { + kparams->kernel_type = HTP_MM_KERNEL_HVX_QUANT_ROW; + kparams->tile_size = htp_tensor_get_tile_size(wtype); + kparams->aligned_tile_size = htp_tensor_get_tile_padded_size(wtype); + kparams->act_row_size = act_row_size; + kparams->vtcm_bias_size = 0; + kparams->vtcm_size = L.total_bytes; + kparams->n_prefetch = best_n_prefetch; + kparams->n_weights = n_weights; + } else { + kparams->kernel_type = HTP_MM_KERNEL_UNSUPPORTED; + return false; + } + } + +finalize: + kparams->div_ne12_ne1 = init_fastdiv_values(ne12 * ne11); + kparams->div_ne1 = init_fastdiv_values(ne11); + kparams->div_r2 = init_fastdiv_values(ne02 > 0 ? ne12 / ne02 : 1); + kparams->div_r3 = init_fastdiv_values(ne03 > 0 ? ne13 / ne03 : 1); + kparams->div_ne12 = init_fastdiv_values(ne12); + return (size_t) kparams->vtcm_size <= vtcm_budget; +} + +bool htp_kparams_solve_mmidnx( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * act, + const struct ggml_tensor * dst, + int32_t n_weights, + struct htp_mm_kernel_params * kparams +) { + const bool ok = htp_kparams_solve_matmul_impl(sess, src0, act, dst, 0, 0, kparams); + kparams->n_weights = n_weights; + return ok; +} + +static bool htp_kparams_solve_binary( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op_tensor, + struct htp_binary_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const uint32_t op = htp_op_remap(op_tensor); + const struct ggml_tensor * src0 = op_tensor->src[0]; + const struct ggml_tensor * src1 = op_tensor->src[1]; + const struct ggml_tensor * src2 = (op == HTP_OP_ADD_ID) ? op_tensor->src[2] : nullptr; + const struct ggml_tensor * dst = op_tensor; + + const bool is_add_id = (op == HTP_OP_ADD_ID); + if (is_add_id) { + if (!src2) { + return false; + } + if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32) { + return false; + } + if (!ggml_are_same_shape(src0, dst)) { + return false; + } + if (src1->ne[0] != src0->ne[0] || src1->ne[2] != 1 || src1->ne[3] != 1) { + return false; + } + if (src2->ne[0] != src0->ne[1] || src2->ne[1] != src0->ne[2]) { + return false; + } + if (src0->nb[0] != sizeof(float) || src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float) || src2->nb[0] != sizeof(int32_t)) { + return false; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1) || !ggml_is_contiguous(dst)) { + return false; + } + if (src2->nb[1] < src2->ne[0] * sizeof(int32_t)) { + return false; + } + } else { + if ((src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) || + src1->type != src0->type || dst->type != src0->type) { + return false; + } + if (ggml_is_permuted(src0) || ggml_is_permuted(dst) || !ggml_are_same_shape(src0, dst)) { + return false; + } + if (!ggml_can_repeat(src1, src0) || ggml_is_permuted(src1)) { + return false; + } + } + + const uint32_t max_threads_sess = htp_session_n_threads(sess); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + const size_t elem_size = ggml_type_size(src0->type); + const size_t src0_row_size = src0->ne[0] * elem_size; + const size_t src1_row_size = src1->ne[0] * elem_size; + const size_t dst_row_size = dst->ne[0] * elem_size; + + const size_t src0_row_size_aligned = hex_round_up(src0_row_size, 128); + const size_t src1_row_size_aligned = hex_round_up(src1_row_size, 128); + const size_t dst_row_size_aligned = hex_round_up(dst_row_size, 128); + + if (!htp_binary_strides_safe(src0, src1, dst, elem_size)) { + return false; + } + + const bool is_scalar = !is_add_id && src1->ne[0] == 1; + const bool is_row_bcast = !is_add_id && !is_scalar && + src1->ne[0] == src0->ne[0] && + (src0->ne[1] > 1 || src0->ne[2] > 1 || src0->ne[3] > 1) && + src1->ne[1] == 1 && src1->ne[2] == 1 && src1->ne[3] == 1; + const bool is_same_shape = !is_add_id && !is_scalar && + src1->ne[0] == src0->ne[0] && + src1->ne[1] == src0->ne[1] && + (src1->ne[2] == src0->ne[2] || src1->ne[2] == 1) && + (src1->ne[3] == src0->ne[3] || src1->ne[3] == 1); + const bool is_complex = !is_add_id && !is_scalar && !is_same_shape && !is_row_bcast && (src1->ne[0] == src0->ne[0]); + const bool is_contig = ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && ggml_is_contiguous(dst); + const bool is_scalar_broadcast = !is_add_id && (ggml_nelements(src1) == 1); + + if (!is_add_id && is_contig && (ggml_are_same_shape(src0, src1) || is_scalar_broadcast)) { + const uint32_t total_elems = (uint32_t) ggml_nelements(src0); + const uint32_t max_chunk_elems = 32768 / elem_size; + const uint32_t min_chunk_elems = 256; + const uint32_t target_chunk_elems = hex_round_up((total_elems + (2 * max_threads_sess) - 1) / (2 * max_threads_sess), 32); + const uint32_t chunk_size = (std::min)(max_chunk_elems, (std::max)(target_chunk_elems, min_chunk_elems)); + const uint32_t chunk_bytes = hex_round_up(chunk_size * elem_size, 128); + const uint32_t total_chunks = (total_elems + chunk_size - 1) / chunk_size; + const uint32_t n_threads = (total_chunks >= 2) ? (std::min)(max_threads_sess, total_chunks) : 1; + + kparams->kernel_type = HTP_BINARY_KERNEL_CHUNKED; + kparams->n_threads = n_threads; + kparams->n_srcs = 2; + kparams->rows_per_buffer = 1; + kparams->src0_row_size_aligned = src0_row_size_aligned; + kparams->src1_row_size_aligned = is_scalar_broadcast ? 0 : src1_row_size_aligned; + kparams->dst_row_size_aligned = dst_row_size_aligned; + kparams->src1_size = 0; + kparams->chunk_size = chunk_size; + kparams->chunk_bytes = chunk_bytes; + kparams->is_scalar = is_scalar_broadcast ? 1 : 0; + + struct htp_binary_vtcm_layout L; + htp_binary_vtcm_layout_build(&L, kparams, vtcm_size); + if (L.total_bytes == 0 || L.total_bytes > vtcm_size) { + return false; + } + + kparams->vtcm_size = L.total_bytes; + return true; + } + + enum htp_binary_kernel_type kernel_type; + size_t src1_size = 0; + size_t src2_size = 0; + + if (is_add_id) { + kernel_type = HTP_BINARY_KERNEL_ADD_ID; + src1_size = hex_round_up(src1->ne[1] * src1_row_size_aligned, 128); + src2_size = hex_round_up(ggml_nelements(src2) * sizeof(int32_t), 128); + if (src1_size + src2_size > vtcm_size) { + return false; + } + } else if (is_row_bcast) { + kernel_type = HTP_BINARY_KERNEL_ROW_BCAST; + src1_size = src1_row_size_aligned; + } else if (is_scalar) { + src1_size = hex_round_up(ggml_nelements(src1) * elem_size, 128); + if (src1_size > vtcm_size) { + return false; + } + kernel_type = HTP_BINARY_KERNEL_SCALAR; + kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; + } else if (is_same_shape) { + kernel_type = HTP_BINARY_KERNEL_SAME_SHAPE; + } else if (is_complex) { + src1_size = hex_round_up(ggml_nelements(src1) * elem_size + 128, 128); + if (src1_size > vtcm_size) { + return false; + } + kernel_type = HTP_BINARY_KERNEL_COMPLEX; + kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; + } else { + src1_size = hex_round_up(ggml_nelements(src1) * elem_size + 128, 128); + if (src1_size > vtcm_size) { + return false; + } + kernel_type = HTP_BINARY_KERNEL_REPEAT; + kparams->src1_strided = !ggml_is_contiguous(src1) ? 1 : 0; + } + + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const uint32_t min_rows_per_thread = (uint32_t) (std::max(1, (128 + dst_row_size - 1) / dst_row_size)); + const uint32_t max_threads = (std::max)(1u, src0_nrows / min_rows_per_thread); + + kparams->kernel_type = kernel_type; + kparams->n_threads = (std::min)(max_threads_sess, max_threads); + kparams->n_srcs = 2; + kparams->src0_row_size_aligned = src0_row_size_aligned; + kparams->src1_row_size_aligned = src1_row_size_aligned; + kparams->dst_row_size_aligned = dst_row_size_aligned; + kparams->src1_size = src1_size; + kparams->src2_size = src2_size; + + const bool src0_contig_dim1 = (src0->nb[2] == src0->ne[1] * src0->nb[1]); + const bool src1_contig_dim1 = (src1->nb[2] == src1->ne[1] * src1->nb[1]); + const bool dst_contig_dim1 = (dst->nb[2] == src0->ne[1] * dst->nb[1]); + + const bool src0_contig_dim2 = (src0->nb[3] == src0->ne[2] * src0->nb[2]); + const bool src1_contig_dim2 = (src1->nb[3] == src1->ne[2] * src1->nb[2]); + const bool dst_contig_dim2 = (dst->nb[3] == src0->ne[2] * dst->nb[2]); + + bool split_at_ne01 = false; + if (src0->ne[2] > 1) { + if (kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) { + split_at_ne01 = (src1->ne[2] != src0->ne[2]) || !src0_contig_dim1 || !src1_contig_dim1 || !dst_contig_dim1; + } else if (kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { + split_at_ne01 = !src0_contig_dim1 || !dst_contig_dim1; + } else { + split_at_ne01 = true; + } + } + kparams->split_at_ne01 = split_at_ne01 ? 1 : 0; + + bool split_at_ne02 = false; + if (src0->ne[3] > 1) { + if (kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) { + split_at_ne02 = (src1->ne[3] != src0->ne[3]) || !src0_contig_dim2 || !src1_contig_dim2 || !dst_contig_dim2; + } else if (kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { + split_at_ne02 = !src0_contig_dim2 || !dst_contig_dim2; + } else { + split_at_ne02 = true; + } + } + kparams->split_at_ne02 = split_at_ne02 ? 1 : 0; + + kparams->div_ne01 = init_fastdiv_values((uint32_t) src0->ne[1]); + kparams->div_ne02 = init_fastdiv_values((uint32_t) src0->ne[2]); + kparams->div_ne012 = init_fastdiv_values((uint32_t) (src0->ne[1] * src0->ne[2])); + kparams->div_ne11 = init_fastdiv_values((uint32_t) src1->ne[1]); + kparams->div_ne12 = init_fastdiv_values((uint32_t) src1->ne[2]); + kparams->div_ne13 = init_fastdiv_values((uint32_t) src1->ne[3]); + + struct htp_binary_vtcm_layout L; + htp_binary_vtcm_layout_build(&L, kparams, vtcm_size); + if (L.rows_per_buffer == 0 || L.total_bytes > vtcm_size) { + if (!is_add_id && is_contig && (ggml_are_same_shape(src0, src1) || is_scalar_broadcast)) { + const uint32_t total_elems = (uint32_t) ggml_nelements(src0); + return htp_binary_solve_chunked(&L, kparams, total_elems, (uint32_t) elem_size, + max_threads_sess, 2, is_scalar_broadcast, vtcm_size); + } + return false; + } + + kparams->rows_per_buffer = L.rows_per_buffer; + kparams->vtcm_size = L.total_bytes; + + return true; +} + +// collapse contiguous dims of elementwise ops so that rows fill at least one HVX vector +static void htp_collapse_dims(struct ggml_tensor ** tensors, size_t n_tensors, size_t elem_size, uint32_t n_threads) { + if (n_tensors == 0 || !tensors[0]) { + return; + } + for (size_t t = 0; t < n_tensors; t++) { + if (!tensors[t] || tensors[t]->nb[0] != elem_size) { + return; + } + if (t > 0 && !ggml_are_same_shape(tensors[0], tensors[t])) { + return; + } + } + + struct ggml_tensor * t0 = tensors[0]; + + while (t0->ne[1] > 1 || t0->ne[2] > 1 || t0->ne[3] > 1) { + const size_t row_size = (size_t) t0->ne[0] * elem_size; + bool rows_contig = true; + for (size_t t = 0; t < n_tensors; t++) { + if (tensors[t]->nb[1] != (size_t) tensors[t]->ne[0] * elem_size) { + rows_contig = false; + break; + } + } + bool all_ne1_one = true; + for (size_t t = 0; t < n_tensors; t++) { + if (tensors[t]->ne[1] != 1) { + all_ne1_one = false; + break; + } + } + const bool can_merge = all_ne1_one || + (rows_contig && (t0->ne[0] == 1 || (row_size < 128 && row_size * t0->ne[1] <= 2048))); + if (!can_merge) { + break; + } + for (size_t t = 0; t < n_tensors; t++) { + tensors[t]->ne[0] *= tensors[t]->ne[1]; + tensors[t]->ne[1] = tensors[t]->ne[2]; + tensors[t]->ne[2] = tensors[t]->ne[3]; + tensors[t]->ne[3] = 1; + tensors[t]->nb[1] = tensors[t]->nb[2]; + tensors[t]->nb[2] = tensors[t]->nb[3]; + tensors[t]->nb[3] = tensors[t]->nb[2] * tensors[t]->ne[2]; + } + } + + // ne1 too big to merge in full: merge it in chunks of k rows (k divides ne1) + const size_t row_size = (size_t) t0->ne[0] * elem_size; + bool rows_contig = true; + for (size_t t = 0; t < n_tensors; t++) { + if (tensors[t]->nb[1] != row_size) { + rows_contig = false; + break; + } + } + if (t0->ne[1] > 1 && row_size < 128 && rows_contig) { + int64_t k = 2048 / row_size; + while (k > 1 && t0->ne[1] % k != 0) { + k--; + } + if (k > 1) { + for (size_t t = 0; t < n_tensors; t++) { + tensors[t]->ne[0] *= k; + tensors[t]->ne[1] /= k; + tensors[t]->nb[1] *= k; + tensors[t]->nb[2] = tensors[t]->nb[1] * tensors[t]->ne[1]; + tensors[t]->nb[3] = tensors[t]->nb[2] * tensors[t]->ne[2]; + } + } + } + + // nrows too small to saturate threads: split ne0 into k rows (k divides ne0) + const size_t row_size_curr = (size_t) t0->ne[0] * elem_size; + const uint32_t nrows = (uint32_t) (t0->ne[1] * t0->ne[2] * t0->ne[3]); + rows_contig = true; + for (size_t t = 0; t < n_tensors; t++) { + if (tensors[t]->ne[1] != 1 && tensors[t]->nb[1] != row_size_curr) { + rows_contig = false; + break; + } + } + if (nrows < n_threads && rows_contig && row_size_curr >= 4096) { + const size_t vec_elems = 128 / elem_size; + int64_t k = std::max(row_size_curr / 16384, (n_threads * 4 + nrows - 1) / nrows); + k = std::min(k, row_size_curr / 2048); + while (k > 1 && t0->ne[0] % (k * vec_elems) != 0) { + k--; + } + if (k > 1) { + for (size_t t = 0; t < n_tensors; t++) { + tensors[t]->ne[0] /= k; + tensors[t]->ne[1] *= k; + tensors[t]->nb[1] = tensors[t]->ne[0] * elem_size; + tensors[t]->nb[2] = tensors[t]->nb[1] * tensors[t]->ne[1]; + tensors[t]->nb[3] = tensors[t]->nb[2] * tensors[t]->ne[2]; + } + } + } +} + +static bool htp_kparams_solve_unary_impl( + const struct ggml_hexagon_session * sess, + uint32_t op, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_unary_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + if (!htp_op_is_unary((htp_op_code) op)) { + return false; + } + + if (op == HTP_OP_HADAMARD) { + const int64_t n = src0->ne[0]; + if (n < 32 || (n & (n - 1)) != 0) { + return false; + } + if (!dst->src[0] || dst->src[0]->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || + (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16)) { + return false; + } + } else { + if ((src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) || dst->type != src0->type) { + return false; + } + if (op == HTP_OP_TRI && (src0->type != GGML_TYPE_F32 || !ggml_is_contiguous(src0))) { + return false; + } + if (src0->type == GGML_TYPE_F16) { + switch (op) { + case HTP_OP_NORM: + case HTP_OP_RMS_NORM: + case HTP_OP_L2_NORM: + case HTP_OP_SCALE: + case HTP_OP_CLAMP: + case HTP_OP_SQR: + case HTP_OP_SQRT: + case HTP_OP_UNARY_LOG: + case HTP_OP_UNARY_ABS: + case HTP_OP_UNARY_STEP: + case HTP_OP_UNARY_CEIL: + case HTP_OP_UNARY_SGN: + break; + default: + return false; + } + } + } + + if (!ggml_is_contiguous_rows(src0) || !ggml_is_contiguous(dst) || !ggml_are_same_shape(src0, dst)) { + return false; + } + + const size_t elem_size = ggml_type_size(src0->type); + + const size_t dst_data_row_size = dst->ne[0] * ggml_type_size(dst->type); + + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const uint32_t min_rows_per_thread = (uint32_t) (std::max(1, (128 + dst_data_row_size - 1) / dst_data_row_size)); + const uint32_t max_threads = (std::max)(1u, src0_nrows / min_rows_per_thread); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + kparams->n_threads = n_threads; + + const bool broadcast_weight = (op == HTP_OP_RMS_NORM_MUL) && (src1->ne[1] * src1->ne[2] * src1->ne[3] == 1); + kparams->broadcast_weight = broadcast_weight; + + const bool src0_contig = ggml_is_contiguous_1(src0); + const bool src1_contig = (op == HTP_OP_RMS_NORM_MUL && !broadcast_weight) ? ggml_is_contiguous_1(src1) : true; + const uint32_t src0_nrows_per_thread = (src0_nrows + n_threads - 1) / n_threads; + const uint32_t min_block_rows = (uint32_t) (std::max(1, 2048 / dst_data_row_size)); + uint32_t max_block = (src0_contig && src1_contig) ? src0_nrows : (uint32_t) src0->ne[1]; + if (src0_nrows_per_thread >= 2 * min_block_rows) { + max_block = (std::min)(max_block, (std::max)(min_block_rows, src0_nrows_per_thread / 4)); + } + + kparams->src0_contig = src0_contig ? 1 : 0; + kparams->src1_contig = src1_contig ? 1 : 0; + + struct htp_unary_vtcm_layout L; + uint32_t col_tile = 0; + uint32_t vtcm_row_per_thread = 0; + + htp_unary_solve_layout(&L, op, src0->ne[0], dst->ne[0], + op == HTP_OP_RMS_NORM_MUL ? src1->ne[0] : 0, + max_block, broadcast_weight, n_threads, vtcm_size, elem_size, + &col_tile, &vtcm_row_per_thread); + + kparams->col_tile = col_tile; + kparams->vtcm_size = L.total_bytes; + kparams->block = col_tile ? 0 : vtcm_row_per_thread; + + const uint32_t tiles_per_row = col_tile > 0 ? (src0->ne[0] + col_tile - 1) / col_tile : 1; + kparams->tiles_per_row = tiles_per_row; + kparams->div_ne01 = init_fastdiv_values(src0->ne[1]); + kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); + kparams->div_ne012 = init_fastdiv_values(src0->ne[1] * src0->ne[2]); + kparams->div_tpr = init_fastdiv_values(tiles_per_row); + + return (col_tile > 0 || vtcm_row_per_thread > 0) && L.total_bytes <= vtcm_size; +} + +static bool htp_kparams_solve_unary( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_unary_kernel_params * kparams +) { + const htp_op_code opcode = htp_op_remap(op); + const struct ggml_tensor * src0 = (opcode == HTP_OP_HADAMARD) ? op->src[1] : op->src[0]; + const struct ggml_tensor * src1 = (opcode == HTP_OP_HADAMARD) ? nullptr : op->src[1]; + return htp_kparams_solve_unary_impl(sess, opcode, src0, src1, op, kparams); +} + +bool htp_kparams_solve_rms_norm_mul( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_unary_kernel_params * kparams +) { + return htp_kparams_solve_unary_impl(sess, HTP_OP_RMS_NORM_MUL, src0, src1, dst, kparams); +} + +bool htp_kparams_solve_repeat_get_rows( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_get_rows_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_BF16 && src0->type != GGML_TYPE_I32 && + src0->type != GGML_TYPE_Q1_0 && src0->type != GGML_TYPE_Q2_0 && src0->type != GGML_TYPE_Q4_0 && src0->type != GGML_TYPE_Q8_0 && + src0->type != GGML_TYPE_Q4_K && src0->type != GGML_TYPE_Q5_K && src0->type != GGML_TYPE_Q6_K) { + return false; + } + + if (!ggml_is_contiguous_rows(src0) || !ggml_is_contiguous_rows(src1) || !ggml_is_contiguous_rows(dst)) { + return false; + } + + if (src1->type != GGML_TYPE_I32 && src1->type != GGML_TYPE_I64) { + return false; + } + + if (src0->type == dst->type) { + if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_I32 && src0->type != GGML_TYPE_F16) { + return false; + } + } else if (src0->type == GGML_TYPE_I32) { + return false; + } else if (dst->type != GGML_TYPE_F32) { + return false; + } + + const uint32_t ne00 = src0->ne[0]; + const uint32_t ne02 = src0->ne[2]; + const uint32_t ne03 = src0->ne[3]; + + const uint32_t ne10 = src1->ne[0]; + const uint32_t ne11 = src1->ne[1]; + const uint32_t ne12 = src1->ne[2]; + const uint32_t nr = ne10 * ne11 * ne12; + + const bool tiled = htp_tensor_is_tiled(src0); + const int wtype = (tiled && (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_BF16)) ? GGML_TYPE_F16 : src0->type; + + if (tiled) { + kparams->kernel_type = HTP_GET_ROWS_KERNEL_TILED; + } else if (src0->type == dst->type) { + kparams->kernel_type = HTP_GET_ROWS_KERNEL_SAMETYPE; + } else { + kparams->kernel_type = HTP_GET_ROWS_KERNEL_FLAT; + } + + const uint32_t total_tasks = nr; + const uint32_t min_tasks_per_thread = (uint32_t) (std::max(1, (128 + dst->nb[1] - 1) / dst->nb[1])); + const uint32_t max_threads = (std::max)(1u, total_tasks / min_tasks_per_thread); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + kparams->n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + struct htp_get_rows_vtcm_layout vtcm_layout = {}; + while (kparams->n_threads > 0) { + htp_get_rows_vtcm_layout_build(&vtcm_layout, kparams->kernel_type, wtype, ne00, total_tasks, src1->type, kparams->n_threads); + if (vtcm_layout.total_bytes <= vtcm_size) { + break; + } + --kparams->n_threads; + } + + if (kparams->n_threads == 0 && total_tasks > 0) { + htp_get_rows_vtcm_layout_build(&vtcm_layout, kparams->kernel_type, wtype, ne00, total_tasks, src1->type, 1); + } + + kparams->vtcm_size = (total_tasks == 0) ? 0 : vtcm_layout.total_bytes; + kparams->total_tasks = total_tasks; + + kparams->div_ne10 = ne10 > 0 ? init_fastdiv_values(ne10) : fastdiv_values{0, 0}; + kparams->div_ne10_ne11 = (ne10 * ne11) > 0 ? init_fastdiv_values(ne10 * ne11) : fastdiv_values{0, 0}; + kparams->div_ne02 = ne02 > 0 ? init_fastdiv_values(ne02) : fastdiv_values{0, 0}; + kparams->div_ne03 = ne03 > 0 ? init_fastdiv_values(ne03) : fastdiv_values{0, 0}; + + if (total_tasks == 0) { + return true; + } + return kparams->n_threads > 0 && (size_t) kparams->vtcm_size <= vtcm_size; +} + +static bool htp_kparams_solve_get_rows( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_get_rows_kernel_params * kparams +) { + return htp_kparams_solve_repeat_get_rows(sess, op->src[0], op->src[1], op, kparams); +} + +static bool htp_kparams_solve_set_rows( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_set_rows_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op->src[2] ? op->src[2] : op; + + if (dst->type == GGML_TYPE_Q8_0 && src0->ne[0] < 32) { + return false; + } + if (src0->type != GGML_TYPE_F32) { + return false; + } + if (src1->type != GGML_TYPE_I32 && src1->type != GGML_TYPE_I64) { + return false; + } + if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_Q8_0) { + return false; + } + + const uint32_t nr = src0->ne[1]; + + kparams->n_threads = (std::min)(htp_session_n_threads(sess), nr); + kparams->total_tasks = nr; + + struct htp_set_rows_vtcm_layout vtcm_layout; + htp_set_rows_vtcm_layout_build(&vtcm_layout, dst->type, src0->ne[0], kparams->n_threads); + kparams->vtcm_size = vtcm_layout.total_bytes; + + return vtcm_layout.total_bytes <= htp_session_vtcm_size(sess); +} + +static bool htp_kparams_solve_softmax( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_softmax_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * src2 = op->src[2]; + const struct ggml_tensor * dst = op; + + if (src2) { + return false; + } + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src0->ne[2] > 512) { + return false; + } + if (src1) { + if ((src1->type != GGML_TYPE_F32 && src1->type != GGML_TYPE_F16) || + src0->ne[0] != src1->ne[0] || src1->ne[1] < src0->ne[1] || + src0->ne[2] % src1->ne[2] != 0 || src0->ne[3] % src1->ne[3] != 0 || + !ggml_is_contiguous(src1)) { + return false; + } + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { + return false; + } + + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const size_t dst_data_row_size = op->ne[0] * ggml_type_size(op->type); + const uint32_t min_rows_per_thread = (uint32_t) (std::max(1, (128 + dst_data_row_size - 1) / dst_data_row_size)); + const uint32_t max_threads = (std::max)(1u, src0_nrows / min_rows_per_thread); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + float scale = 1.0f; + float max_bias = 0.0f; + memcpy(&scale, &op->op_params[0], sizeof(float)); + memcpy(&max_bias, &op->op_params[1], sizeof(float)); + + kparams->scale = scale; + kparams->max_bias = max_bias; + + const uint32_t n_head = src0->ne[2]; + const uint32_t n_head_log2 = 1u << (uint32_t) floor(log2(n_head)); + kparams->n_head = n_head; + kparams->n_head_log2 = n_head_log2; + + if (max_bias > 0.0f && n_head_log2 > 0) { + kparams->m0 = powf(2.0f, -(max_bias) / n_head_log2); + kparams->m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); + } else { + kparams->m0 = 1.0f; + kparams->m1 = 1.0f; + } + + kparams->use_src1 = (src1 != nullptr) ? 1 : 0; + kparams->use_f16 = (src1 != nullptr && src1->type == GGML_TYPE_F16) ? 1 : 0; + + const uint32_t ne00 = src0->ne[0]; + const uint32_t ne10 = src1 ? src1->ne[0] : 1; + + struct htp_softmax_vtcm_layout layout; + htp_softmax_vtcm_layout_build(&layout, ne00, ne10, kparams->use_src1 != 0, kparams->use_f16 != 0, n_threads); + if (layout.total_bytes > htp_session_vtcm_size(sess)) { + return false; + } + + kparams->n_threads = n_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + + if (!kparams->use_src1) { + kparams->kernel_type = HTP_SOFTMAX_KERNEL_NOMASK; + } else if (kparams->use_f16) { + kparams->kernel_type = HTP_SOFTMAX_KERNEL_MASK_F16; + } else { + kparams->kernel_type = HTP_SOFTMAX_KERNEL_MASK_F32; + } + + if (src0->ne[1] > 0) kparams->div_ne01 = init_fastdiv_values(src0->ne[1]); + if (src0->ne[2] > 0) kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); + const uint32_t ne12 = src1 ? src1->ne[2] : 1; + const uint32_t ne13 = src1 ? src1->ne[3] : 1; + if (ne12 > 0) kparams->div_ne12 = init_fastdiv_values(ne12); + if (ne13 > 0) kparams->div_ne13 = init_fastdiv_values(ne13); + + return true; +} + +static bool htp_kparams_solve_rope( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_rope_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * src2 = op->src[2]; + const struct ggml_tensor * dst = op; + + if (!ggml_are_same_shape(src0, dst)) { + return false; + } + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_I32) { + return false; + } + if (src0->ne[0] <= 0) { + return false; + } + + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + if (src0_nrows == 0) { + return false; + } + + const int32_t * op_params = &op->op_params[0]; + const int n_dims = op_params[1]; + const int mode = op_params[2]; + const int n_offs = op_params[15]; + + if (n_dims < 0 || n_dims % 2 != 0) { + return false; + } + if (n_offs < 0 || (n_offs % 32 != 0) || (n_offs + n_dims > src0->ne[0])) { + return false; + } + + float freq_base; + memcpy(&freq_base, op_params + 5, sizeof(float)); + if (freq_base < 0.0f) { + return false; + } + + if (mode != GGML_ROPE_TYPE_NORMAL && + mode != GGML_ROPE_TYPE_NEOX && + mode != GGML_ROPE_TYPE_MROPE && + mode != GGML_ROPE_TYPE_VISION && + mode != GGML_ROPE_TYPE_IMROPE) { + return false; + } + + const bool is_mrope = (mode & GGML_ROPE_TYPE_MROPE) != 0; + + if (mode == GGML_ROPE_TYPE_VISION && (n_dims != (int) (src0->ne[0] / 2) || n_offs != 0)) { + return false; + } + if (is_mrope) { + const int32_t * sections = op_params + 11; + if (sections[0] <= 0 && sections[1] <= 0 && sections[2] <= 0) { + return false; + } + } + + const int64_t min_pos_len = (is_mrope || mode == GGML_ROPE_TYPE_VISION) ? src0->ne[2] * 4 : src0->ne[2]; + if (src1->ne[0] < min_pos_len || !ggml_is_contiguous(src1)) { + return false; + } + + if (src2) { + if (src2->type != GGML_TYPE_F32 || !ggml_is_contiguous(src2) || src2->ne[0] < (n_dims / 2)) { + return false; + } + } + + if (src0->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float) || + src0->nb[1] < src0->ne[0] * sizeof(float) || dst->nb[1] < dst->ne[0] * sizeof(float)) { + return false; + } + + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), src0_nrows); + const uint32_t n_freq_factors = src2 ? (uint32_t) src2->ne[0] : 0; + + struct htp_rope_vtcm_layout layout; + htp_rope_vtcm_layout_build(&layout, src0->ne[0], n_threads, n_freq_factors); + if (layout.total_bytes > htp_session_vtcm_size(sess)) { + return false; + } + + kparams->n_threads = n_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->div_ne2_ne1 = init_fastdiv_values(dst->ne[2] * dst->ne[1]); + kparams->div_ne1 = init_fastdiv_values(dst->ne[1]); + + return true; +} + +static bool htp_kparams_solve_sum_rows( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_sum_rows_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32) { + return false; + } + if (op->op == GGML_OP_ARGMAX) { + if (dst->type != GGML_TYPE_I32) { + return false; + } + } else if (dst->type != GGML_TYPE_F32) { + return false; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { + return false; + } + + const uint32_t ne00 = src0->ne[0]; + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const uint32_t max_threads_sess = htp_session_n_threads(sess); + + if (op->op == GGML_OP_SUM) { + const uint32_t total_elems = (uint32_t) ggml_nelements(src0); + const uint32_t n_threads = (total_elems >= 1024) ? (std::min)(max_threads_sess, (uint32_t) HTP_MAX_NTHREADS) : 1; + const uint32_t raw_chunk = (total_elems + n_threads - 1) / n_threads; + + kparams->n_threads = n_threads; + kparams->elems_per_thread = hex_round_up(raw_chunk, 32); + } else if (op->op == GGML_OP_ARGMAX && src0_nrows <= 1) { + const uint32_t n_threads = (ne00 >= 1024) ? (std::min)(max_threads_sess, (uint32_t) HTP_MAX_NTHREADS) : 1; + const uint32_t raw_chunk = (ne00 + n_threads - 1) / n_threads; + + kparams->n_threads = n_threads; + kparams->elems_per_thread = hex_round_up(raw_chunk, 32); + } else { + const uint32_t min_rpt = (src0->nb[1] < 1024) ? 32 : 1; + const uint32_t max_threads = (std::max)(1u, src0_nrows / min_rpt); + + kparams->n_threads = (std::min)(max_threads_sess, max_threads); + } + + return true; +} + +bool htp_kparams_solve_unary_mul_glu( + const struct ggml_hexagon_session * sess, + uint32_t op, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_glu_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + if (!htp_op_is_glu((htp_op_code) op)) { + return false; + } + if ((src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) || dst->type != src0->type) { + return false; + } + if ((op == HTP_OP_GLU_GEGLU_QUICK || op == HTP_OP_GLU_GEGLU_ERF) && src0->type != GGML_TYPE_F32) { + return false; + } + + const size_t elem_size = ggml_type_size(src0->type); + const auto is_valid_src = [elem_size](const struct ggml_tensor * t) { + return ggml_is_contiguous_1(t) && t->nb[0] == elem_size && + (t->ne[1] <= 1 || t->nb[1] >= (size_t) t->ne[0] * elem_size); + }; + + if (!is_valid_src(src0) || !ggml_is_contiguous(dst)) { + return false; + } + if (src1 && (src1->type != src0->type || !ggml_are_same_shape(src0, src1) || !is_valid_src(src1))) { + return false; + } + + const size_t dst_row_size = dst->ne[0] * elem_size; + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const uint32_t min_rows_per_thread = (uint32_t) (std::max(1, (128 + dst_row_size - 1) / dst_row_size)); + const uint32_t max_threads = (std::max)(1u, src0_nrows / min_rows_per_thread); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + const size_t row_size_aligned = hex_round_up(dst_row_size, 128); + uint32_t vtcm_row_per_thread = (uint32_t) (vtcm_size / (n_threads * 3 * row_size_aligned)); + if (vtcm_row_per_thread < 2) { + return false; + } + + const uint32_t src0_nrows_per_thread = (src0_nrows + n_threads - 1) / n_threads; + if (src0_nrows_per_thread >= 2 && vtcm_row_per_thread > src0_nrows_per_thread) { + uint32_t target_rpt = (src0_nrows_per_thread >= 4) ? (src0_nrows_per_thread / 2) & ~1u : 2; + vtcm_row_per_thread = (std::max)(2u, (std::min)(vtcm_row_per_thread, target_rpt)); + } + + struct htp_glu_vtcm_layout L; + htp_glu_vtcm_layout_build(&L, dst_row_size, n_threads, vtcm_row_per_thread); + + kparams->n_threads = n_threads; + kparams->vtcm_row_per_thread = L.vtcm_row_per_thread; + kparams->vtcm_size = (uint32_t) L.total_bytes; + + return true; +} + +static bool htp_kparams_solve_glu( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_glu_kernel_params * kparams +) { + return htp_kparams_solve_unary_mul_glu(sess, htp_op_remap(op), op->src[0], op->src[1], op, kparams); +} + +static bool htp_kparams_solve_repeat( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_repeat_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if ((src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16) || src0->type != dst->type) { + return false; + } + if (!ggml_can_repeat(src0, dst) || ggml_is_transposed(src0) || ggml_is_transposed(dst)) { + return false; + } + + const uint32_t total_dst_rows = dst->ne[1] * dst->ne[2] * dst->ne[3]; + const size_t dst_row_size = dst->ne[0] * ggml_type_size(dst->type); + const uint32_t min_rows_per_thread = (uint32_t) (std::max(1, (128 + dst_row_size - 1) / dst_row_size)); + const uint32_t max_threads = (std::max)(1u, total_dst_rows / min_rows_per_thread); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + kparams->n_threads = n_threads; + kparams->nr0 = dst->ne[0] / src0->ne[0]; + kparams->nr1 = dst->ne[1] / src0->ne[1]; + kparams->nr2 = dst->ne[2] / src0->ne[2]; + kparams->nr3 = dst->ne[3] / src0->ne[3]; + + kparams->div_ne1 = init_fastdiv_values(dst->ne[1]); + kparams->div_ne12 = init_fastdiv_values(dst->ne[1] * dst->ne[2]); + kparams->div_ne01 = init_fastdiv_values(src0->ne[1]); + kparams->div_ne02 = init_fastdiv_values(src0->ne[2]); + kparams->div_ne03 = init_fastdiv_values(src0->ne[3]); + + return true; +} + +static bool htp_kparams_solve_ssm_conv( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_ssm_conv_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (src0->ne[3] != 1 || src1->ne[2] != 1 || src1->ne[3] != 1 || dst->ne[3] != 1) { + return false; + } + + const int64_t d_conv_64 = src1->ne[0]; + const int64_t d_inner_64 = src0->ne[1]; + const int64_t n_t_64 = dst->ne[1]; + const int64_t n_s_64 = dst->ne[2]; + + if (d_conv_64 <= 0 || d_conv_64 > 32 || d_inner_64 <= 0) { + return false; + } + if (src0->ne[0] != d_conv_64 - 1 + n_t_64 || src0->ne[1] != d_inner_64 || src0->ne[2] != n_s_64) { + return false; + } + if (src1->ne[0] != d_conv_64 || src1->ne[1] != d_inner_64) { + return false; + } + if (dst->ne[0] != d_inner_64 || dst->ne[1] != n_t_64 || dst->ne[2] != n_s_64) { + return false; + } + if (src0->nb[0] != sizeof(float) || src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float)) { + return false; + } + if (src0->nb[1] != src0->ne[0] * sizeof(float) || src1->nb[1] != src1->ne[0] * sizeof(float)) { + return false; + } + + const uint32_t d_conv = (uint32_t) d_conv_64; + const uint32_t d_inner = (uint32_t) d_inner_64; + const uint32_t n_t = (uint32_t) n_t_64; + const uint32_t n_s = (uint32_t) n_s_64; + const uint32_t ncs = (uint32_t) src0->ne[0]; + + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), (d_inner + 31) / 32); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + kparams->n_threads = n_threads; + kparams->d_conv = d_conv; + kparams->d_inner = d_inner; + kparams->n_t = n_t; + kparams->n_s = n_s; + + const uint32_t raw_rpt = (d_inner + n_threads - 1) / n_threads; + const uint32_t d_inner_per_thread = hex_round_up(raw_rpt, 32); + + if (n_t == 1) { + kparams->d_inner_tile = d_inner_per_thread; + } else { + const uint32_t src1_raw_bytes = hex_round_up(d_inner_per_thread * d_conv * sizeof(float), 128) + 128; + const uint32_t src1_T_bytes = hex_round_up(d_conv * d_inner_per_thread * sizeof(float), 128); + const uint32_t vtcm_src1_per_thread = src1_raw_bytes + src1_T_bytes; + + const size_t vtcm_budget = (vtcm_size > 0 ? vtcm_size / n_threads : (1024 * 1024)); + const uint32_t src0_block_T = hex_round_up(ncs * 32 * sizeof(float), 128); + const size_t fixed_bytes = vtcm_src1_per_thread + src0_block_T; + const size_t avail_for_tiles = vtcm_budget > fixed_bytes ? vtcm_budget - fixed_bytes : (128 * 1024); + + uint32_t target_max_tile = hex_round_up((d_inner_per_thread + 3) / 4, 32); + target_max_tile = (std::max)(target_max_tile, 32u); + target_max_tile = (std::min)(target_max_tile, 128u); + + const size_t raw_stride_bytes = ncs * sizeof(float) + sizeof(float); + uint32_t d_inner_tile = (uint32_t) (avail_for_tiles / (2 * (raw_stride_bytes + n_t * sizeof(float)))); + d_inner_tile = (d_inner_tile / 32) * 32; + if (d_inner_tile == 0) { + d_inner_tile = 32; + } + if (d_inner_tile > target_max_tile) { + d_inner_tile = target_max_tile; + } + if (d_inner_tile > d_inner_per_thread) { + d_inner_tile = d_inner_per_thread; + } + kparams->d_inner_tile = d_inner_tile; + } + + struct htp_ssm_conv_vtcm_layout L; + htp_ssm_conv_vtcm_layout_build(&L, d_inner_per_thread, d_conv, n_t, kparams->d_inner_tile, n_threads); + + kparams->vtcm_size = (uint32_t) L.total_bytes; + kparams->div_d_inner_tile = init_fastdiv_values(kparams->d_inner_tile); + + return L.total_bytes <= vtcm_size; +} + +static bool htp_kparams_solve_sort( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_sort_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + const bool is_top_k = (op->op == GGML_OP_TOP_K); + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_I32) { + return false; + } + + const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3]; + const uint32_t ne00 = src0->ne[0]; + const uint32_t k = dst->ne[0]; + const uint32_t n_threads_max = htp_session_n_threads(sess) > 0 ? htp_session_n_threads(sess) : 4; + const size_t vtcm_budget = htp_session_vtcm_size(sess) > 0 ? htp_session_vtcm_size(sess) : (8 * 1024 * 1024); + + int32_t order = GGML_SORT_ORDER_DESC; + if (!is_top_k) { + order = ((const int32_t *) op->op_params)[0]; + } + + struct htp_sort_vtcm_layout layout; + if (!htp_sort_solve_layout(&layout, ne00, total_rows, k, n_threads_max, vtcm_budget, is_top_k)) { + return false; + } + + kparams->n_threads = layout.n_threads; + kparams->order = (uint32_t) order; + kparams->is_top_k = is_top_k ? 1 : 0; + kparams->chunk_elems = layout.chunk_elems; + kparams->n_chunks = layout.n_chunks; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->merge_elems = layout.merge_elems; + kparams->n_slots = layout.n_slots; + kparams->div_ne01 = init_fastdiv_values((uint32_t) src0->ne[1]); + kparams->div_ne01_ne02 = init_fastdiv_values((uint32_t) (src0->ne[1] * src0->ne[2])); + + return true; +} + +static void htp_pool_interior_range( + uint32_t src_x, uint32_t dst_x, uint32_t kernel_x, uint32_t stride_x, int32_t pad_x, + uint32_t * ox_lo, uint32_t * ox_hi +) { + const uint32_t lo_raw = ((uint32_t) pad_x + stride_x - 1) / stride_x; + *ox_lo = (lo_raw < dst_x) ? lo_raw : dst_x; + + const int32_t numer_hi = (int32_t) src_x - (int32_t) kernel_x + pad_x; + if (numer_hi < 0) { + *ox_hi = 0; + } else { + const uint32_t hi_raw = (uint32_t) numer_hi / stride_x + 1; + *ox_hi = (hi_raw < dst_x) ? hi_raw : dst_x; + } + if (*ox_hi < *ox_lo) { + *ox_hi = *ox_lo; + } +} + +static bool htp_kparams_solve_pool_2d( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_pool_2d_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + const bool is_pool_1d = (op->op == GGML_OP_POOL_1D); + + const int32_t * params = dst->op_params; + if (params[0] != GGML_OP_POOL_AVG && params[0] != GGML_OP_POOL_MAX) { + return false; + } + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { + return false; + } + if (ggml_nbytes(src0) > UINT32_MAX - 256 || ggml_nbytes(dst) > UINT32_MAX - 256) { + return false; + } + + const int32_t kernel_x = params[1]; + const int32_t kernel_y = is_pool_1d ? 1 : params[2]; + const int32_t stride_x = params[is_pool_1d ? 2 : 3]; + const int32_t stride_y = is_pool_1d ? 1 : params[4]; + const int32_t pad_x = params[is_pool_1d ? 3 : 5]; + const int32_t pad_y = is_pool_1d ? 0 : params[6]; + + if (kernel_x <= 0 || kernel_y <= 0 || stride_x <= 0 || stride_y <= 0 || + pad_x < 0 || pad_y < 0) { + return false; + } + + const uint32_t src_x = (uint32_t) src0->ne[0]; + const uint32_t src_y = is_pool_1d ? 1 : (uint32_t) src0->ne[1]; + const uint32_t dst_x = (uint32_t) dst->ne[0]; + const uint32_t dst_y = is_pool_1d ? 1 : (uint32_t) dst->ne[1]; + const uint32_t dst_plane_bytes = dst_x * dst_y * sizeof(float); + const uint32_t planes = (uint32_t) (is_pool_1d + ? (uint64_t) src0->ne[1] * (uint64_t) src0->ne[2] * (uint64_t) src0->ne[3] + : (uint64_t) src0->ne[2] * (uint64_t) src0->ne[3]); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), planes > 0 ? planes : 1); + const uint32_t planes_per_chunk = (dst_plane_bytes > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(dst_plane_bytes, HEX_L2_LINE_SIZE)) : 1; + + struct htp_pool_vtcm_layout layout; + if (!htp_pool_solve_layout(&layout, src_x, src_y, dst_x, dst_y, n_threads, htp_session_vtcm_size(sess))) { + return false; + } + + kparams->src_x = src_x; + kparams->src_y = src_y; + kparams->dst_x = dst_x; + kparams->dst_y = dst_y; + kparams->kernel_x = (uint32_t) kernel_x; + kparams->kernel_y = (uint32_t) kernel_y; + kparams->stride_x = (uint32_t) stride_x; + kparams->stride_y = (uint32_t) stride_y; + kparams->pad_x = pad_x; + kparams->pad_y = pad_y; + kparams->n_threads = n_threads; + kparams->planes = planes; + kparams->planes_per_chunk = planes_per_chunk; + kparams->pool_op = (uint32_t) params[0]; + + const bool exact_tiling = (kparams->pad_x == 0 && kparams->pad_y == 0 && + kparams->stride_x == kparams->kernel_x && kparams->stride_y == kparams->kernel_y); + const bool fast_ok = exact_tiling && (kparams->kernel_x == 1 || kparams->kernel_x == 2); + const bool narrow_ok = fast_ok && ((uint64_t) kparams->dst_x * kparams->kernel_x <= 32); + const bool global_ok = exact_tiling && + kparams->kernel_x == kparams->src_x && kparams->kernel_y == kparams->src_y && + kparams->dst_x == 1 && kparams->dst_y == 1; + const bool block_ok = exact_tiling && + kparams->kernel_y == 1 && kparams->stride_y == 1 && + kparams->kernel_x >= 32; + + if (global_ok) { + kparams->kernel_type = HTP_POOL_KERNEL_GLOBAL; + } else if (block_ok) { + kparams->kernel_type = HTP_POOL_KERNEL_BLOCK; + } else if (narrow_ok) { + kparams->kernel_type = HTP_POOL_KERNEL_HVX_NARROW; + } else if (fast_ok) { + kparams->kernel_type = HTP_POOL_KERNEL_HVX; + } else { + kparams->kernel_type = HTP_POOL_KERNEL_GENERAL; + } + + kparams->avg_divide_count = (is_pool_1d && kparams->pool_op == GGML_OP_POOL_AVG) ? 1 : 0; + htp_pool_interior_range(kparams->src_x, kparams->dst_x, kparams->kernel_x, + kparams->stride_x, kparams->pad_x, + &kparams->ox_lo, &kparams->ox_hi); + kparams->inv_kernel_area = 1.0f / (float) (kparams->kernel_x * kparams->kernel_y); + + return true; +} + +bool htp_kparams_solve_upscale( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * dst, + struct htp_upscale_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + + const uint32_t src_x = (uint32_t) src0->ne[0]; + const uint32_t src_y = (uint32_t) src0->ne[1]; + const uint32_t src_z = (uint32_t) src0->ne[2]; + const uint32_t src_w = (uint32_t) src0->ne[3]; + + const uint32_t dst_x = (uint32_t) dst->ne[0]; + const uint32_t dst_y = (uint32_t) dst->ne[1]; + const uint32_t dst_z = (uint32_t) dst->ne[2]; + const uint32_t dst_w = (uint32_t) dst->ne[3]; + + if (src_x == 0 || src_y == 0 || src_z == 0 || src_w == 0 || + dst_x == 0 || dst_y == 0 || dst_z == 0 || dst_w == 0) { + return false; + } + + const bool is_src_contig_row = (src0->nb[0] == sizeof(float)); + const bool is_src_strided_2d = (src0->nb[0] > sizeof(float)) && + (src0->nb[0] % sizeof(float) == 0) && + (src0->nb[1] == (size_t) src_x * src0->nb[0]) && + ((size_t) src_x * src_y <= 0xFFFFu); + + if ((!is_src_contig_row && !is_src_strided_2d) || dst->nb[0] != sizeof(float)) { + return false; + } + + const int32_t mode_flags = dst->op_params[0]; + const uint32_t mode_raw = (uint32_t) (mode_flags & 0xFF); + if (mode_raw >= GGML_SCALE_MODE_COUNT) { + return false; + } + + const bool align_corners = (mode_flags & GGML_SCALE_FLAG_ALIGN_CORNERS) != 0; + const bool antialias = (mode_flags & GGML_SCALE_FLAG_ANTIALIAS) != 0; + + float sf0 = (float) dst_x / (float) src_x; + float sf1 = (float) dst_y / (float) src_y; + float sf2 = (float) dst_z / (float) src_z; + float sf3 = (float) dst_w / (float) src_w; + float pixel_offset = 0.5f; + + if (align_corners) { + pixel_offset = 0.0f; + sf0 = (dst_x > 1 && src_x > 1) ? (float) (dst_x - 1) / (float) (src_x - 1) : sf0; + sf1 = (dst_y > 1 && src_y > 1) ? (float) (dst_y - 1) / (float) (src_y - 1) : sf1; + } + + const float inv_sf0 = 1.0f / sf0; + const float inv_sf1 = 1.0f / sf1; + const float inv_sf2 = 1.0f / sf2; + const float inv_sf3 = 1.0f / sf3; + + const float filter_radius0 = antialias ? (std::max)(1.0f, inv_sf0) : 0.0f; + const float filter_radius1 = antialias ? (std::max)(1.0f, inv_sf1) : 0.0f; + const float invscale0 = antialias ? (1.0f / filter_radius0) : 0.0f; + const float invscale1 = antialias ? (1.0f / filter_radius1) : 0.0f; + + const uint32_t total_slices = dst_z * dst_w; + uint32_t n_threads = htp_session_n_threads(sess); + + struct htp_upscale_vtcm_layout layout; + uint32_t dst_nrows_per_chunk = 0; + while (n_threads > 0) { + if (htp_upscale_solve_layout(&layout, src_x, src_y, dst_x, dst_y, inv_sf1, filter_radius1, n_threads, + htp_session_vtcm_size(sess), &dst_nrows_per_chunk)) { + break; + } + n_threads--; + } + if (n_threads == 0) { + return false; + } + + size_t lut_x_size = 0; + size_t elem_y_sz = sizeof(uint32_t); + if (mode_raw == HTP_UPSCALE_MODE_BICUBIC) { + lut_x_size = hex_round_up(dst_x * sizeof(struct upscale_bicubic_x), 128); + elem_y_sz = sizeof(struct upscale_bicubic_y); + } else if (antialias) { + lut_x_size = hex_round_up(dst_x * sizeof(struct upscale_antialias_x), 128); + elem_y_sz = sizeof(struct upscale_antialias_y); + } else if (mode_raw == HTP_UPSCALE_MODE_BILINEAR) { + const uint32_t n_chunks = (dst_x + 31) / 32; + lut_x_size = hex_round_up(n_chunks * sizeof(struct upscale_bilinear_x_chunk), 128); + elem_y_sz = sizeof(struct upscale_bilinear_y); + } else { + lut_x_size = hex_round_up(dst_x * sizeof(uint32_t), 128); + } + const size_t total_lut_size = lut_x_size + hex_round_up(dst_y * elem_y_sz, 128); + if (total_lut_size > HTP_DDR_SPAD_SIZE) { + return false; + } + + const uint32_t chunks_per_slice = (dst_y + dst_nrows_per_chunk - 1) / dst_nrows_per_chunk; + const uint32_t total_chunks = total_slices * chunks_per_slice; + + n_threads = (std::min)(n_threads, total_chunks > 0 ? total_chunks : 1); + htp_upscale_vtcm_layout_build(&layout, src_x, src_y, dst_x, dst_y, dst_nrows_per_chunk, inv_sf1, filter_radius1, n_threads); + + const uint32_t slice_dst_bytes = dst_x * dst_y * sizeof(float); + const uint32_t chunk_dst_bytes = dst_x * dst_nrows_per_chunk * sizeof(float); + const bool dst_contig = (dst->nb[1] == (size_t) dst_x * sizeof(float)) && + (dst_z <= 1 || dst->nb[2] == (size_t) dst_y * dst->nb[1]) && + (dst_w <= 1 || dst->nb[3] == (size_t) dst_z * dst->nb[2]); + + uint32_t chunks_per_group = 0; + if (dst_contig) { + const uint32_t slices_per_group = (slice_dst_bytes > 0) + ? (HEX_L2_LINE_SIZE / hex_gcd_u32(slice_dst_bytes, HEX_L2_LINE_SIZE)) + : 1; + if (slices_per_group == 1 && (chunk_dst_bytes % HEX_L2_LINE_SIZE == 0)) { + chunks_per_group = 1; + } else { + chunks_per_group = slices_per_group * chunks_per_slice; + } + } + + uint8_t kernel_type = HTP_UPSCALE_KERNEL_BILINEAR; + if (mode_raw == HTP_UPSCALE_MODE_NEAREST) { + if (dst_x == 2 * src_x && dst_y == 2 * src_y && !align_corners) { + kernel_type = HTP_UPSCALE_KERNEL_NEAREST_2X; + } else if (dst_x == 4 * src_x && dst_y == 4 * src_y && !align_corners) { + kernel_type = HTP_UPSCALE_KERNEL_NEAREST_4X; + } else { + kernel_type = HTP_UPSCALE_KERNEL_NEAREST; + } + } else if (mode_raw == HTP_UPSCALE_MODE_BICUBIC) { + kernel_type = HTP_UPSCALE_KERNEL_BICUBIC; + } else if (antialias) { + kernel_type = HTP_UPSCALE_KERNEL_BILINEAR_AA; + } else if (dst_x == 2 * src_x && dst_y == 2 * src_y && !align_corners && (src_x % 32 == 0)) { + kernel_type = HTP_UPSCALE_KERNEL_BILINEAR_2X; + } else { + kernel_type = HTP_UPSCALE_KERNEL_BILINEAR; + } + + kparams->kernel_type = kernel_type; + kparams->mode = (uint8_t) mode_raw; + kparams->align_corners = align_corners ? 1 : 0; + kparams->antialias = antialias ? 1 : 0; + + kparams->inv_sf0 = inv_sf0; + kparams->inv_sf1 = inv_sf1; + kparams->inv_sf2 = inv_sf2; + kparams->inv_sf3 = inv_sf3; + kparams->pixel_offset = pixel_offset; + + kparams->filter_radius0 = filter_radius0; + kparams->filter_radius1 = filter_radius1; + kparams->invscale0 = invscale0; + kparams->invscale1 = invscale1; + + kparams->n_threads = n_threads; + kparams->chunks_per_group = chunks_per_group; + + kparams->dst_nrows_per_chunk = dst_nrows_per_chunk; + kparams->chunks_per_slice = chunks_per_slice; + kparams->total_chunks = total_chunks; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + + kparams->div_chunks_per_slice = init_fastdiv_values(chunks_per_slice > 0 ? chunks_per_slice : 1); + kparams->div_dst_z = init_fastdiv_values(dst_z > 0 ? dst_z : 1); + + return true; +} + +static bool htp_kparams_solve_concat( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_concat_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + kparams->kernel_type = HTP_CONCAT_KERNEL_UNSUPPORTED; + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (!src0 || !src1 || !dst) { + return false; + } + + int dim = ((const int32_t *) op->op_params)[0]; + if (dim < 0 || dim >= GGML_MAX_DIMS) { + return false; + } + kparams->dim = dim; + + if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_I32) { + return false; + } + if (src0->type != dst->type || src1->type != dst->type) { + return false; + } + + const uint32_t type_size = ggml_type_size(dst->type); + const uint32_t n_threads = htp_session_n_threads(sess); + const uint32_t mdev_count = htp_session_mdev_count(sess); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + for (int d = 0; d < GGML_MAX_DIMS; d++) { + const int64_t ne_d = (d == dim) ? src0->ne[d] + src1->ne[d] : src0->ne[d]; + if (dst->ne[d] != ne_d || (d != dim && src1->ne[d] != dst->ne[d])) { + return false; + } + } + + const uint32_t max_gather_ne0 = 128 / type_size; + const uint32_t total_rows = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); + const bool b_dense = (src1->nb[0] == type_size); + const bool gather_strides_ok = + src0->nb[1] >= (size_t) src0->ne[0] * type_size && + (b_dense ? src1->nb[1] >= (size_t) src1->ne[0] * type_size + : src1->nb[0] >= (size_t) src1->ne[1] * type_size); + + if (dim == 0 && + (dst->type == GGML_TYPE_F32 || dst->type == GGML_TYPE_F16) && + dst->ne[0] <= max_gather_ne0 && + dst->nb[0] == type_size && dst->nb[1] == (size_t) dst->ne[0] * type_size && + src0->nb[0] == type_size && + (src1->nb[0] == type_size || src1->nb[1] == type_size) && + gather_strides_ok && + htp_gather_rows_tensor_outer_contiguous(dst) && + htp_gather_rows_tensor_outer_contiguous(src0) && + htp_gather_rows_tensor_outer_contiguous(src1)) { + + if (htp_gather_rows_solve_layout(&kparams->u.gather, + (uint32_t) src0->ne[0], (uint32_t) src0->nb[1], + (uint32_t) src1->ne[0], (uint32_t) src1->nb[1], b_dense, + type_size, total_rows, + n_threads, mdev_count, vtcm_size)) { + kparams->kernel_type = HTP_CONCAT_KERNEL_GATHER_ROWS; + kparams->n_threads = (uint8_t) n_threads; + kparams->vtcm_size = kparams->u.gather.slice * n_threads; + return true; + } + } + + const bool dma_strides_ok = (src0->nb[0] == type_size && src1->nb[0] == type_size && dst->nb[0] == type_size); + if (dma_strides_ok) { + kparams->kernel_type = HTP_CONCAT_KERNEL_REGULAR; + kparams->n_threads = 1; + return true; + } + + const bool is_src1_transposed = (src1->nb[0] > src1->nb[1]); + const bool is_src0_transposed = (src0->nb[0] > src0->nb[1]); + const bool transposed_rows_ok = (src0->nb[0] == type_size && src1->nb[1] == type_size && dst->nb[0] == type_size); + + if (dim == 0 && is_src1_transposed && !is_src0_transposed && transposed_rows_ok && + (dst->type == GGML_TYPE_F32 || dst->type == GGML_TYPE_F16)) { + + const uint32_t nth = n_threads > 0 ? n_threads : 8; + struct htp_concat_transposed_vtcm_layout layout; + htp_concat_transposed_vtcm_layout_build(&layout, (uint32_t) src0->ne[0], (uint32_t) src1->ne[0], type_size, nth); + + if (vtcm_size > 0 && layout.total_bytes > vtcm_size) { + return false; + } + + kparams->kernel_type = HTP_CONCAT_KERNEL_TRANSPOSED; + kparams->n_threads = nth; + kparams->vtcm_size = layout.total_bytes; + kparams->u.transposed.div_ne2 = init_fastdiv_values((uint32_t) dst->ne[2]); + return true; + } + + return false; +} + +static bool htp_kparams_solve_cpy( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_copy_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + kparams->kernel_type = HTP_COPY_KERNEL_UNSUPPORTED; + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (!src0 || !dst) { + return false; + } + + if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_I32) { + return false; + } + if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_I32) { + return false; + } + + const int64_t nelem_src = ggml_nelements(src0); + const int64_t nelem_dst = ggml_nelements(dst); + if (nelem_src != nelem_dst || nelem_src < 0) { + return false; + } + + const uint32_t src_type_size = ggml_type_size(src0->type); + const uint32_t dst_type_size = ggml_type_size(dst->type); + + kparams->src0_type_size = (uint8_t) src_type_size; + kparams->dst_type_size = (uint8_t) dst_type_size; + kparams->total_elems = (uint32_t) nelem_src; + + if (nelem_src == 0) { + kparams->kernel_type = HTP_COPY_KERNEL_1D_CONTIG; + return true; + } + + if (nelem_src == 1) { + if (src0->type == dst->type) { + kparams->kernel_type = HTP_COPY_KERNEL_SCALAR; + return true; + } + if ((src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_I32) || + (src0->type == GGML_TYPE_I32 && dst->type == GGML_TYPE_F32) || + (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F16) || + (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F32)) { + kparams->kernel_type = HTP_COPY_KERNEL_SCALAR; + return true; + } + return false; + } + + const bool sametype = (src0->type == dst->type); + const bool same_extents = ggml_are_same_shape(src0, dst); + + const bool transposed = (src0->nb[0] > src0->nb[1]) || (dst->nb[0] > dst->nb[1]) || + (src0->nb[0] != src_type_size) || (dst->nb[0] != dst_type_size) || + (src0->nb[1] < (size_t) src0->ne[0] * src_type_size) || (dst->nb[1] < (size_t) dst->ne[0] * dst_type_size); + const bool sameshape = same_extents && !transposed; + + const bool src_is_contiguous = ggml_is_contiguous(src0); + const bool dst_is_contiguous = ggml_is_contiguous(dst); + + const uint32_t n_threads = htp_session_n_threads(sess); + const uint32_t mdev_count = htp_session_mdev_count(sess); + const size_t vtcm_size = htp_session_vtcm_size(sess); + + if (sametype) { + if (src_is_contiguous && dst_is_contiguous) { + kparams->kernel_type = HTP_COPY_KERNEL_1D_CONTIG; + return true; + } + + const uint32_t max_gather_ne0 = 128 / src_type_size; + const uint32_t total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); + if ((src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16) && + dst_is_contiguous && !src_is_contiguous && + src0->nb[0] == src_type_size && src0->ne[0] <= max_gather_ne0 && + src0->nb[1] >= (size_t) src0->ne[0] * src_type_size && + total_rows > 1 && + htp_gather_rows_tensor_outer_contiguous(src0)) { + + if (htp_gather_rows_solve_layout(&kparams->u.gather, + (uint32_t) src0->ne[0], (uint32_t) src0->nb[1], + 0, 0, false, + src_type_size, total_rows, + n_threads, mdev_count, vtcm_size)) { + kparams->kernel_type = HTP_COPY_KERNEL_GATHER_ROWS; + kparams->n_threads = (uint8_t) n_threads; + kparams->vtcm_size = kparams->u.gather.slice * n_threads; + return true; + } + } + + if (sameshape) { + kparams->kernel_type = HTP_COPY_KERNEL_SAMESHAPE_SAMETYPE; + kparams->total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); + return true; + } + + kparams->kernel_type = HTP_COPY_KERNEL_RESHAPE; + kparams->n_threads = n_threads > 0 ? (uint8_t) n_threads : 4; + kparams->u.reshape.div_ne0 = init_fastdiv_values((uint32_t) dst->ne[0]); + kparams->u.reshape.div_ne1_ne0 = init_fastdiv_values((uint32_t) (dst->ne[1] * dst->ne[0])); + kparams->u.reshape.div_ne2_ne1_ne0 = init_fastdiv_values((uint32_t) (dst->ne[2] * dst->ne[1] * dst->ne[0])); + kparams->u.reshape.div_ne00 = init_fastdiv_values((uint32_t) src0->ne[0]); + kparams->u.reshape.div_ne01_ne00 = init_fastdiv_values((uint32_t) (src0->ne[1] * src0->ne[0])); + kparams->u.reshape.div_ne02_ne01_ne00 = init_fastdiv_values((uint32_t) (src0->ne[2] * src0->ne[1] * src0->ne[0])); + return true; + } + + if (!sameshape) { + return false; + } + + const bool valid_conversion = (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F16) || + (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F32) || + (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_I32) || + (src0->type == GGML_TYPE_I32 && dst->type == GGML_TYPE_F32); + if (!valid_conversion) { + return false; + } + + const uint32_t nth = n_threads > 0 ? n_threads : 4; + struct htp_copy_convert_vtcm_layout layout; + htp_copy_convert_solve_layout(&layout, (uint32_t) src0->ne[0], (uint32_t) src0->ne[1], src_type_size, dst_type_size, nth); + + if (vtcm_size > 0 && layout.total_bytes > vtcm_size) { + return false; + } + + kparams->kernel_type = HTP_COPY_KERNEL_SAMESHAPE_CONVERT; + kparams->total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); + kparams->n_threads = (uint8_t) nth; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->u.convert.blk_rows = layout.blk_rows; + kparams->u.convert.div_ne01 = init_fastdiv_values((uint32_t) src0->ne[1]); + kparams->u.convert.div_ne02_ne01 = init_fastdiv_values((uint32_t) (src0->ne[2] * src0->ne[1])); + + return true; +} + +static bool im2col_3d_calc_output_size( + uint32_t input, uint32_t kernel, int32_t stride, int32_t padding, int32_t dilation, uint32_t * output +) { + if (stride <= 0 || padding < 0 || dilation <= 0 || kernel == 0) { + return false; + } + + const int64_t numerator = (int64_t) input + 2LL * padding - (int64_t) dilation * (kernel - 1) - 1; + if (numerator < 0) { + return false; + } + + const uint64_t size = (uint64_t) (numerator / stride) + 1; + if (size == 0 || size > UINT32_MAX) { + return false; + } + + *output = (uint32_t) size; + return true; +} + +static bool htp_kparams_solve_im2col( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_im2col_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + kparams->kernel_type = HTP_IM2COL_KERNEL_UNSUPPORTED; + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (!src0 || !src1 || !dst) { + return false; + } + if (src1->type != GGML_TYPE_F32 || (dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_F32)) { + return false; + } + if (src1->nb[0] != sizeof(float) || !ggml_is_contiguous(dst)) { + return false; + } + + const int32_t * op_params = (const int32_t *) op->op_params; + const int32_t s0 = op_params[0]; + const int32_t s1 = op_params[1]; + const int32_t p0 = op_params[2]; + const int32_t p1 = op_params[3]; + const int32_t d0 = op_params[4]; + const int32_t d1 = op_params[5]; + const bool is_2D = (op_params[6] == 1); + + if (s0 <= 0 || d0 <= 0 || p0 < 0) { + return false; + } + if (is_2D && (s1 <= 0 || d1 <= 0 || p1 < 0)) { + return false; + } + + const uint32_t N = is_2D ? (uint32_t) src1->ne[3] : (uint32_t) src1->ne[2]; + const uint32_t IC = is_2D ? (uint32_t) src1->ne[2] : (uint32_t) src1->ne[1]; + const uint32_t IH = is_2D ? (uint32_t) src1->ne[1] : 1; + const uint32_t IW = (uint32_t) src1->ne[0]; + const uint32_t KH = is_2D ? (uint32_t) src0->ne[1] : 1; + const uint32_t KW = (uint32_t) src0->ne[0]; + const uint32_t OH = is_2D ? (uint32_t) dst->ne[2] : 1; + const uint32_t OW = (uint32_t) dst->ne[1]; + + if (KW == 0 || KH == 0 || IW == 0 || IH == 0 || IC == 0 || OW == 0 || OH == 0 || N == 0) { + return false; + } + + const uint64_t patch_stride_64 = (uint64_t) IC * KH * KW; + const uint64_t total_rows_64 = (uint64_t) N * OH; + if (patch_stride_64 > UINT32_MAX || total_rows_64 > UINT32_MAX) { + return false; + } + const uint32_t patch_stride = (uint32_t) patch_stride_64; + const uint32_t total_rows = (uint32_t) total_rows_64; + + if (dst->ne[0] != patch_stride || dst->ne[1] != OW || (is_2D && dst->ne[2] != OH)) { + return false; + } + + const uint32_t dst_elem = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); + + bool is_patchembed = ggml_is_contiguous(src1) && (s0 == (int32_t) KW && p0 == 0 && d0 == 1); + if (is_2D) { + is_patchembed = is_patchembed && (s1 == (int32_t) KH && p1 == 0 && d1 == 1); + } + + const uint32_t max_threads = (sess && htp_session_n_threads(sess) > 0) ? htp_session_n_threads(sess) : 8; + const uint32_t n_threads = (total_rows < max_threads) ? total_rows : max_threads; + const uint32_t vtcm_size = (sess && htp_session_vtcm_size(sess) > 0) ? (uint32_t) htp_session_vtcm_size(sess) : 0; + const uint32_t row_size = (uint32_t) dst->nb[2]; + const uint32_t rows_per_chunk = (row_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(row_size, HEX_L2_LINE_SIZE)) : 1; + + if (is_patchembed) { + const uint64_t src_row_bytes_raw = (uint64_t) IC * KH * IW * sizeof(float); + const uint64_t dst_row_bytes_raw = (uint64_t) OW * patch_stride * dst_elem; + if (src_row_bytes_raw <= UINT32_MAX && dst_row_bytes_raw <= UINT32_MAX) { + const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); + const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads, + htp_im2col_scratch_bytes(HTP_IM2COL_KERNEL_PATCHEMBED_DMA, KH, patch_stride)); + + if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { + kparams->kernel_type = HTP_IM2COL_KERNEL_PATCHEMBED_DMA; + kparams->n_threads = (uint8_t) n_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->src_row_bytes = src_row_bytes; + kparams->dst_row_bytes = dst_row_bytes; + kparams->owb = OW; + kparams->wb = IW; + kparams->nbpr = 1; + kparams->N = N; + kparams->IC = IC; + kparams->ID = 1; + kparams->IH = IH; + kparams->IW = IW; + kparams->KD = 1; + kparams->KH = KH; + kparams->KW = KW; + kparams->OD = 1; + kparams->OH = OH; + kparams->OW = OW; + kparams->patch_stride = patch_stride; + kparams->total_rows = total_rows; + kparams->rows_per_chunk = rows_per_chunk; + kparams->div_OH = init_fastdiv_values(OH); + kparams->div_OD = init_fastdiv_values(1); + return true; + } + } + } + + for (uint32_t owb = (OW < 256 ? OW : 256); owb >= 1; owb--) { + const uint64_t Wb = (uint64_t) (owb - 1) * s0 + (uint64_t) (KW - 1) * d0 + 1; + if (Wb > UINT32_MAX) { + if (owb == 1) break; + continue; + } + + const uint64_t src_row_bytes_raw = (uint64_t) IC * KH * Wb * sizeof(float); + const uint64_t dst_row_bytes_raw = (uint64_t) owb * patch_stride * dst_elem; + if (src_row_bytes_raw > UINT32_MAX || dst_row_bytes_raw > UINT32_MAX) { + if (owb == 1) break; + continue; + } + + const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); + const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); + + // threads work on output-col blocks, so a single output row (1D) can use them all + const uint32_t nbpr = (OW + owb - 1) / owb; + const uint64_t nblocks = (uint64_t) total_rows * nbpr; + const uint32_t blk_threads = (uint32_t) (nblocks < max_threads ? nblocks : max_threads); + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, blk_threads, + htp_im2col_scratch_bytes(HTP_IM2COL_KERNEL_BLOCKED_DMA, KH, patch_stride)); + + if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { + kparams->kernel_type = HTP_IM2COL_KERNEL_BLOCKED_DMA; + kparams->n_threads = (uint8_t) blk_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->src_row_bytes = src_row_bytes; + kparams->dst_row_bytes = dst_row_bytes; + kparams->owb = owb; + kparams->wb = (uint32_t) Wb; + kparams->nbpr = nbpr; + kparams->N = N; + kparams->IC = IC; + kparams->ID = 1; + kparams->IH = IH; + kparams->IW = IW; + kparams->KD = 1; + kparams->KH = KH; + kparams->KW = KW; + kparams->OD = 1; + kparams->OH = OH; + kparams->OW = OW; + kparams->patch_stride = patch_stride; + kparams->total_rows = total_rows; + kparams->rows_per_chunk = rows_per_chunk; + kparams->div_OH = init_fastdiv_values(OH); + kparams->div_OD = init_fastdiv_values(1); + kparams->div_nbpr = init_fastdiv_values(nbpr); + return true; + } + if (owb == 1) break; + } + + return false; +} + +static bool htp_kparams_solve_im2col_3d( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_im2col_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + kparams->kernel_type = HTP_IM2COL_KERNEL_UNSUPPORTED; + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (!src0 || !src1 || !dst) { + return false; + } + if (src1->type != GGML_TYPE_F32 || (dst->type != GGML_TYPE_F16 && dst->type != GGML_TYPE_F32)) { + return false; + } + if (src1->nb[0] != sizeof(float) || !ggml_is_contiguous(dst)) { + return false; + } + + const int32_t * params = (const int32_t *) op->op_params; + const int32_t s0 = params[0], s1 = params[1], s2 = params[2]; + const int32_t p0 = params[3], p1 = params[4], p2 = params[5]; + const int32_t d0 = params[6], d1 = params[7], d2 = params[8]; + const int32_t ic = params[9]; + + if (s0 <= 0 || s1 <= 0 || s2 <= 0 || + p0 < 0 || p1 < 0 || p2 < 0 || + d0 <= 0 || d1 <= 0 || d2 <= 0 || ic <= 0) { + return false; + } + if (src1->ne[3] % ic != 0) { + return false; + } + + const uint32_t IC = (uint32_t) ic; + const uint32_t N = (uint32_t) (src1->ne[3] / IC); + if (N == 0) { + return false; + } + + uint32_t OW, OH, OD; + if (!im2col_3d_calc_output_size(src1->ne[0], src0->ne[0], s0, p0, d0, &OW) || + !im2col_3d_calc_output_size(src1->ne[1], src0->ne[1], s1, p1, d1, &OH) || + !im2col_3d_calc_output_size(src1->ne[2], src0->ne[2], s2, p2, d2, &OD)) { + return false; + } + + const uint32_t KD = (uint32_t) src0->ne[2]; + const uint32_t KH = (uint32_t) src0->ne[1]; + const uint32_t KW = (uint32_t) src0->ne[0]; + const uint32_t ID = (uint32_t) src1->ne[2]; + const uint32_t IH = (uint32_t) src1->ne[1]; + const uint32_t IW = (uint32_t) src1->ne[0]; + + const uint64_t patch_stride_64 = (uint64_t) IC * KD * KH * KW; + const uint64_t total_rows_64 = (uint64_t) N * OD * OH; + const uint64_t dst_ne3_64 = (uint64_t) OD * N; + + if (patch_stride_64 > UINT32_MAX || total_rows_64 > UINT32_MAX || dst_ne3_64 > UINT32_MAX) { + return false; + } + const uint32_t patch_stride = (uint32_t) patch_stride_64; + const uint32_t total_rows = (uint32_t) total_rows_64; + const uint32_t dst_ne3 = (uint32_t) dst_ne3_64; + + if (dst->ne[0] != patch_stride || dst->ne[1] != OW || dst->ne[2] != OH || dst->ne[3] != dst_ne3) { + return false; + } + + const uint32_t dst_elem = (dst->type == GGML_TYPE_F16) ? sizeof(ggml_fp16_t) : sizeof(float); + + const bool is_patchembed = ggml_is_contiguous(src1) && + (s0 == (int32_t) KW && s1 == (int32_t) KH && s2 == (int32_t) KD && + p0 == 0 && p1 == 0 && p2 == 0 && + d0 == 1 && d1 == 1 && d2 == 1); + + const uint32_t max_threads = (sess && htp_session_n_threads(sess) > 0) ? htp_session_n_threads(sess) : 8; + const uint32_t n_threads = (total_rows < max_threads) ? total_rows : max_threads; + const uint32_t vtcm_size = (sess && htp_session_vtcm_size(sess) > 0) ? (uint32_t) htp_session_vtcm_size(sess) : 0; + const uint32_t row_size = (uint32_t) dst->nb[2]; + const uint32_t rows_per_chunk = (row_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(row_size, HEX_L2_LINE_SIZE)) : 1; + + if (is_patchembed) { + const uint64_t src_row_bytes_raw = (uint64_t) IC * KD * KH * IW * sizeof(float); + const uint64_t dst_row_bytes_raw = (uint64_t) OW * patch_stride * dst_elem; + if (src_row_bytes_raw <= UINT32_MAX && dst_row_bytes_raw <= UINT32_MAX) { + const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); + const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads, 256); + + if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { + kparams->kernel_type = HTP_IM2COL_KERNEL_PATCHEMBED_DMA; + kparams->n_threads = (uint8_t) n_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->src_row_bytes = src_row_bytes; + kparams->dst_row_bytes = dst_row_bytes; + kparams->owb = OW; + kparams->wb = IW; + kparams->nbpr = 1; + kparams->N = N; + kparams->IC = IC; + kparams->ID = ID; + kparams->IH = IH; + kparams->IW = IW; + kparams->KD = KD; + kparams->KH = KH; + kparams->KW = KW; + kparams->OD = OD; + kparams->OH = OH; + kparams->OW = OW; + kparams->patch_stride = patch_stride; + kparams->total_rows = total_rows; + kparams->rows_per_chunk = rows_per_chunk; + kparams->div_OH = init_fastdiv_values(OH); + kparams->div_OD = init_fastdiv_values(OD); + return true; + } + } + } + + for (uint32_t owb = (OW < 256 ? OW : 256); owb >= 1; owb--) { + const uint64_t Wb = (uint64_t) (owb - 1) * s0 + (uint64_t) (KW - 1) * d0 + 1; + if (Wb > UINT32_MAX) { + if (owb == 1) break; + continue; + } + + const uint64_t src_row_bytes_raw = (uint64_t) IC * KD * KH * Wb * sizeof(float); + const uint64_t dst_row_bytes_raw = (uint64_t) owb * patch_stride * dst_elem; + if (src_row_bytes_raw > UINT32_MAX || dst_row_bytes_raw > UINT32_MAX) { + if (owb == 1) break; + continue; + } + + const uint32_t src_row_bytes = hex_round_up((uint32_t) src_row_bytes_raw, 256); + const uint32_t dst_row_bytes = hex_round_up((uint32_t) dst_row_bytes_raw, 256); + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, src_row_bytes, dst_row_bytes, n_threads, 256); + + if (vtcm_size == 0 || layout.total_bytes <= vtcm_size) { + kparams->kernel_type = HTP_IM2COL_KERNEL_BLOCKED_DMA; + kparams->n_threads = (uint8_t) n_threads; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->src_row_bytes = src_row_bytes; + kparams->dst_row_bytes = dst_row_bytes; + kparams->owb = owb; + kparams->wb = (uint32_t) Wb; + kparams->nbpr = (OW + owb - 1) / owb; + kparams->N = N; + kparams->IC = IC; + kparams->ID = ID; + kparams->IH = IH; + kparams->IW = IW; + kparams->KD = KD; + kparams->KH = KH; + kparams->KW = KW; + kparams->OD = OD; + kparams->OH = OH; + kparams->OW = OW; + kparams->patch_stride = patch_stride; + kparams->total_rows = total_rows; + kparams->rows_per_chunk = rows_per_chunk; + kparams->div_OH = init_fastdiv_values(OH); + kparams->div_OD = init_fastdiv_values(OD); + return true; + } + if (owb == 1) break; + } + + return false; +} + +static bool htp_kparams_solve_pad( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_pad_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + + const int32_t lp0 = ((const int32_t *) op->op_params)[0]; + const int32_t rp0 = ((const int32_t *) op->op_params)[1]; + const bool circular = (((const int32_t *) op->op_params)[8] != 0); + + if (circular && (lp0 > src0->ne[0] || rp0 > src0->ne[0])) { + return false; + } + + const uint32_t type_size = (uint32_t) ggml_type_size(src0->type); + const uint32_t total_dst_rows = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); + const uint32_t max_threads = (std::max)(1u, total_dst_rows); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + struct htp_pad_vtcm_layout layout; + htp_pad_vtcm_layout_build(&layout, (uint32_t) src0->ne[0] * type_size, (uint32_t) dst->ne[0] * type_size, n_threads); + + const bool use_dma = (src0->nb[0] == type_size) && (src0->ne[0] >= 512) && + (htp_session_vtcm_size(sess) >= layout.total_bytes); + + kparams->n_threads = n_threads; + kparams->total_rows = total_dst_rows; + kparams->use_dma = use_dma ? 1 : 0; + kparams->elem_size = type_size; + kparams->vtcm_size = use_dma ? (uint32_t) layout.total_bytes : 0; + + if (circular && use_dma) { + kparams->kernel_type = HTP_PAD_KERNEL_HVX_CIRCULAR_DMA; + } else if (circular) { + kparams->kernel_type = HTP_PAD_KERNEL_HVX_CIRCULAR; + } else if (use_dma) { + kparams->kernel_type = HTP_PAD_KERNEL_HVX_DMA; + } else { + kparams->kernel_type = HTP_PAD_KERNEL_HVX; + } + + kparams->div_ne1 = init_fastdiv_values((uint32_t) dst->ne[1]); + kparams->div_ne1_ne2 = init_fastdiv_values((uint32_t) (dst->ne[1] * dst->ne[2])); + kparams->div_ne01 = init_fastdiv_values((uint32_t) src0->ne[1]); + kparams->div_ne02 = init_fastdiv_values((uint32_t) src0->ne[2]); + kparams->div_ne03 = init_fastdiv_values((uint32_t) src0->ne[3]); + + return true; +} + +static bool htp_kparams_solve_cumsum( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_cumsum_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(dst)) { + return false; + } + + const uint32_t total_rows = (uint32_t) (src0->ne[1] * src0->ne[2] * src0->ne[3]); + const uint32_t max_threads = (std::max)(1u, total_rows); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + struct htp_cumsum_vtcm_layout layout; + htp_cumsum_vtcm_layout_build(&layout, (uint32_t) src0->nb[1], (uint32_t) dst->nb[1], n_threads); + + const bool use_dma = (htp_session_vtcm_size(sess) >= layout.total_bytes); + + kparams->n_threads = n_threads; + kparams->total_rows = total_rows; + kparams->use_dma = use_dma ? 1 : 0; + kparams->vtcm_size = use_dma ? (uint32_t) layout.total_bytes : 0; + + return true; +} + +static bool htp_kparams_solve_fill( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_fill_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * dst = op; + + if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16) { + return false; + } + if (!ggml_is_contiguous_rows(dst) || ggml_is_permuted(dst)) { + return false; + } + + const uint32_t ne1 = (uint32_t) dst->ne[1]; + const uint32_t ne2 = (uint32_t) dst->ne[2]; + const uint32_t ne3 = (uint32_t) dst->ne[3]; + const uint32_t nb1 = (uint32_t) dst->nb[1]; + + const uint32_t total_rows = ne1 * ne2 * ne3; + const uint32_t max_threads = (std::max)(1u, total_rows); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + const uint32_t elem_size = (uint32_t) ggml_type_size(dst->type); + const uint32_t rows_per_chunk = (nb1 > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(nb1, HEX_L2_LINE_SIZE)) : 1; + + kparams->n_threads = n_threads; + kparams->total_rows = total_rows; + kparams->elem_size = elem_size; + kparams->kernel_type = ggml_is_contiguous(dst) ? HTP_FILL_KERNEL_CONTIGUOUS : HTP_FILL_KERNEL_STRIDED; + kparams->rows_per_chunk = rows_per_chunk; + kparams->div_ne1 = init_fastdiv_values(ne1); + kparams->div_ne1_ne2 = init_fastdiv_values(ne1 * ne2); + + return true; +} + +static bool htp_kparams_solve_roll( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_roll_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (!ggml_are_same_shape(src0, dst)) { + return false; + } + if (!ggml_is_contiguous_rows(src0) || !ggml_is_contiguous(dst)) { + return false; + } + + const uint32_t ne0 = (uint32_t) dst->ne[0]; + const uint32_t ne1 = (uint32_t) dst->ne[1]; + const uint32_t ne2 = (uint32_t) dst->ne[2]; + const uint32_t ne3 = (uint32_t) dst->ne[3]; + + const int32_t s0 = ((const int32_t *) op->op_params)[0]; + uint32_t i0_src0 = 0; + if (-s0 < 0) { + i0_src0 = (uint32_t) (-s0 + (int32_t) ne0); + } else if ((uint32_t) (-s0) >= ne0) { + i0_src0 = (uint32_t) (-s0) - ne0; + } else { + i0_src0 = (uint32_t) (-s0); + } + + const uint32_t total_rows = ne1 * ne2 * ne3; + const uint32_t max_threads = (std::max)(1u, total_rows); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + + kparams->n_threads = n_threads; + kparams->total_rows = total_rows; + kparams->i0_src0 = i0_src0; + kparams->n0 = ne0 - i0_src0; + + if (htp_session_mdev_count(sess) <= 1) { + if (ggml_is_contiguous(src0) && ggml_is_contiguous(dst)) { + kparams->kernel_type = HTP_ROLL_KERNEL_DMA_CONTIGUOUS; + } else { + kparams->kernel_type = HTP_ROLL_KERNEL_DMA_STRIDED; + } + } else { + kparams->kernel_type = HTP_ROLL_KERNEL_HVX; + } + + kparams->div_ne1 = init_fastdiv_values(ne1); + kparams->div_ne2_ne1 = init_fastdiv_values(ne2 * ne1); + + return true; +} + +static bool htp_kparams_solve_diag( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_diag_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (src0->ne[1] != 1 || dst->ne[0] != dst->ne[1] || dst->ne[0] != src0->ne[0]) { + return false; + } + if (!ggml_is_contiguous_rows(src0) || !ggml_is_contiguous_rows(dst) || + ggml_is_permuted(src0) || ggml_is_permuted(dst)) { + return false; + } + + const uint32_t total_batches = (uint32_t) (src0->ne[2] * src0->ne[3]); + const uint32_t max_threads = (std::max)(1u, total_batches); + const uint32_t n_threads = (std::min)(htp_session_n_threads(sess), max_threads); + const uint32_t dst_batch_size = (uint32_t) (dst->ne[1] * dst->nb[1]); + + bool can_split = (dst->ne[0] == 1 || dst->nb[0] == sizeof(float)) && !ggml_is_permuted(dst); + uint32_t batches_per_chunk = 1; + if (can_split) { + if (dst->ne[2] > 1 && (dst->nb[2] & (HEX_L2_LINE_SIZE - 1)) == 0 && + (dst->ne[3] <= 1 || (dst->nb[3] & (HEX_L2_LINE_SIZE - 1)) == 0)) { + batches_per_chunk = 1; + } else if (dst->nb[2] == dst_batch_size && + (dst->ne[3] <= 1 || dst->nb[3] == dst->nb[2] * dst->ne[2])) { + batches_per_chunk = (dst_batch_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(dst_batch_size, HEX_L2_LINE_SIZE)) : 1; + } else { + can_split = false; + } + } + + const uint32_t src_batch_size = (uint32_t) (src0->ne[0] * sizeof(float)); + const uint32_t dst_row_size = (uint32_t) (dst->ne[0] * sizeof(float)); + + struct htp_diag_vtcm_layout layout; + htp_diag_vtcm_layout_build(&layout, src_batch_size, dst_row_size, n_threads); + + const bool use_dma = (htp_session_vtcm_size(sess) >= layout.total_bytes); + + kparams->n_threads = n_threads; + kparams->total_batches = total_batches; + kparams->use_dma = use_dma ? 1 : 0; + kparams->can_split = can_split ? 1 : 0; + kparams->batches_per_chunk = batches_per_chunk; + kparams->vtcm_size = use_dma ? (uint32_t) layout.total_bytes : 0; + kparams->div_ne02 = init_fastdiv_values((uint32_t) src0->ne[2]); + + return true; +} + +static bool htp_kparams_solve_solve_tri( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_solve_tri_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (src0->ne[0] != src0->ne[1] || src0->ne[1] != src1->ne[1] || + src0->ne[2] != src1->ne[2] || src0->ne[3] != src1->ne[3] || + !ggml_are_same_shape(src1, dst)) { + return false; + } + + const uint32_t max_threads_sess = htp_session_n_threads(sess); + const uint32_t k = (uint32_t) src1->ne[0]; + const uint32_t col_block = 32; + const uint32_t k_chunks = (k + col_block - 1) / col_block; + const uint32_t total_batches = (uint32_t) (src0->ne[2] * src0->ne[3]); + const bool batched = total_batches >= max_threads_sess; + const uint32_t total_jobs = batched ? total_batches : (total_batches * k_chunks); + const uint32_t max_threads = (std::max)(1u, total_jobs); + const uint32_t n_threads = (std::min)(max_threads_sess, max_threads); + const uint32_t batch_size = (uint32_t) dst->nb[2]; + const uint32_t batches_per_chunk = (batch_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(batch_size, HEX_L2_LINE_SIZE)) : 1; + + kparams->n_threads = n_threads; + kparams->total_batches = total_batches; + kparams->total_jobs = total_jobs; + kparams->k_chunks = k_chunks; + kparams->col_block = col_block; + kparams->batched = batched ? 1 : 0; + kparams->batches_per_chunk = batches_per_chunk; + kparams->div_ne02 = init_fastdiv_values((uint32_t) src0->ne[2]); + kparams->div_k_chunks = init_fastdiv_values(k_chunks > 0 ? k_chunks : 1); + + return true; +} + +// Implicit GEMM over sliding windows of fp16 input croutons (HMX activation:single), no im2col +static bool htp_kparams_conv2d_win( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * dst, + struct htp_conv2d_kernel_params * kp +) { + if (htp_session_n_hmx(sess) == 0) { + return false; + } + + const struct ggml_tensor * src0 = dst->src[0]; + const struct ggml_tensor * src1 = dst->src[1]; + const int32_t s0 = ggml_get_op_params_i32(dst, 0); + const int32_t s1 = ggml_get_op_params_i32(dst, 1); + const int32_t p0 = ggml_get_op_params_i32(dst, 2); + const int32_t p1 = ggml_get_op_params_i32(dst, 3); + const int32_t d0 = ggml_get_op_params_i32(dst, 4); + const int32_t d1 = ggml_get_op_params_i32(dst, 5); + + const uint32_t KW = src0->ne[0]; + const uint32_t KH = src0->ne[1]; + const uint32_t Cin = src0->ne[2]; + const uint32_t Cout = src0->ne[3]; + const uint32_t IW = src1->ne[0]; + const uint32_t IH = src1->ne[1]; + const uint32_t OW = dst->ne[0]; + const uint32_t OH = dst->ne[1]; + const uint32_t N = dst->ne[3]; + const size_t es = ggml_type_size(src0->type); + + if (s0 != 1 || s1 != 1 || p0 < 0 || p1 < 0 || dst->nb[0] != sizeof(float)) { + return false; + } + if (dst->nb[1] < OW * sizeof(float) || (Cout > 1 && dst->nb[2] < OW * sizeof(float))) { + return false; + } + + const bool whcn = src1->nb[0] == sizeof(float) && src1->nb[1] >= IW * sizeof(float) && (Cin == 1 || src1->nb[2] >= IH * src1->nb[1]); + const bool cwhn = !whcn && src1->nb[2] == sizeof(float) && src1->nb[0] == Cin * sizeof(float) && src1->nb[1] >= IW * src1->nb[0]; + if (!whcn && !cwhn) { + return false; + } + + const bool w_rows = src0->nb[0] == es && (KH == 1 || src0->nb[1] == KW * es) && (Cin == 1 || src0->nb[2] == KW * KH * es); + const bool co_c = (Cout == 1 || src0->nb[3] == es) && (Cin == 1 || src0->nb[2] >= (std::min)(Cout, 32u) * es); + if (!w_rows && !co_c) { + return false; + } + + // short output rows: fold the kw taps into channels so the virtual row is OW wide and output rows are contiguous + const bool fold = (whcn || (cwhn && d0 == 1)) && KW > 1 && KW * Cin <= 32 && OW < 64 && KW * KH <= 16 && Cout >= 16; + + const uint32_t T = KW * KH; + const uint32_t n_ch = fold ? KW * Cin : Cin; + const uint32_t n_cc = (n_ch + 31) / 32; + const uint32_t rem = n_ch - (n_cc - 1) * 32; + const uint32_t stop = (rem + 7) / 8 * 8 - 1; + const uint32_t SR = fold ? OW : IW + 2 * p0; + const uint32_t IHS = IH + 2 * p1; + const uint32_t n_wt = fold ? KH : T; + const uint32_t moff = (KH - 1) * d1 * SR + (fold ? 0 : (KW - 1) * d0); + const uint32_t halo = moff / 32 + 1; + const uint32_t n_rt = (Cout + 31) / 32; + const uint64_t n_q = (uint64_t) (N * IHS - (IHS - OH) - 1) * SR + OW; + const uint32_t nth = kp->n_threads; + const size_t tile = 2048; + + if ((uint64_t) N * IHS * SR + moff + 64 >= (1ull << 31)) { + return false; + } + const uint32_t n_tiles = (uint32_t) ((n_q + 31) / 32); + + // weight packing scratch + uint32_t w_cs = 0; + size_t wraw = 0; + size_t wscr = 0; + if (w_rows) { + const uint32_t kpw = es == 2 ? 64 : 32; + for (uint32_t cs = 32; cs >= 2; cs /= 2) { + w_cs = cs; + wraw = (size_t) 32 * ((cs * T + kpw - 1) / kpw) * 128; + if (3 * wraw + 64 * 128 <= 256 * 1024 || (fold && cs == 32)) { + break; + } + } + // enough packing units for all threads + const uint32_t kpw2 = es == 2 ? 64 : 32; + while (!fold && w_cs > 2 && n_rt * ((Cin + 31) / 32) * (32 / w_cs) < kp->n_threads) { + w_cs /= 2; + } + wraw = (std::min)(wraw, (size_t) 32 * ((w_cs * T + kpw2 - 1) / kpw2) * 128); + wscr = 3 * wraw + 64 * 128 + 128; + } else { + w_cs = fold ? KW : (std::min)(T, 16u); + while (!fold && w_cs > 1 && n_rt * ((Cin + 31) / 32) * ((T + w_cs - 1) / w_cs) < kp->n_threads) { + w_cs = (w_cs + 1) / 2; + } + wscr = 2 * (size_t) w_cs * 32 * 128; + } + + uint32_t rt_block = n_rt; + uint32_t ct = (std::max)(4 * halo, (n_tiles + 3) / 4); + ct = (std::min)((std::max)(ct, 8u), 512u); + ct = (std::min)(ct, n_tiles); + uint32_t seg_b = 8; + // longer output rows make the output DMA more efficient + uint32_t seg_t = (std::min)(32u, (std::max)(8u, (OW + 31) / 32)); + + while (rt_block > 1 && (size_t) rt_block * n_wt * n_cc * tile > htp_session_vtcm_size(sess) / 2) { + rt_block = (rt_block + 1) / 2; + } + + size_t stage = 0, thr = 0, act = 0, out = 0, w_size = 0, total = 0; + uint32_t n_bc = 0; + while (true) { + n_bc = ct + halo; + stage = cwhn ? (size_t) seg_b * 32 * Cin * sizeof(float) + 256 : (size_t) n_ch * seg_b * 32 * sizeof(float); + if (fold) { + // raw input rows of the staged pixels with 128 bytes of read slack on both sides + stage = (size_t) Cin * ((seg_b * 32 + OW - 1) / OW + 1) * IW * sizeof(float) + 256; + } + stage = hex_round_up(stage, 128); + thr = hex_round_up((std::max)(2 * stage + (size_t) HTP_CONV2D_WIN_OBUF * 32 * seg_t * 32 * sizeof(float), wscr), tile); + w_size = (size_t) rt_block * n_wt * n_cc * tile; + act = (size_t) n_cc * n_bc * tile; + out = (size_t) rt_block * ct * tile; + struct htp_conv2d_vtcm_layout L; + htp_conv2d_vtcm_layout_build(&L, rt_block, w_size, act, out, thr, nth); + total = L.total_bytes; + if (total <= htp_session_vtcm_size(sess)) { + break; + } + if (ct > 64) { + ct /= 2; + } else if (rt_block > 1) { + rt_block = (rt_block + 1) / 2; + } else if (seg_b > 1 || seg_t > 1) { + seg_b = (std::max)(seg_b / 2, 1u); + seg_t = (std::max)(seg_t / 2, 1u); + } else if (ct > 1) { + ct /= 2; + } else { + return false; + } + } + + if (hex_round_up((size_t) T * sizeof(uint32_t), 128) + 2 * hex_round_up((size_t) ct, 128) > HTP_DDR_SPAD_SIZE) { + return false; + } + + const uint32_t TG = w_cs; + const uint32_t CS = w_cs; + const uint32_t n_tg = (T + TG - 1) / TG; + const uint32_t n_cs = (32 + CS - 1) / CS; + + kp->kernel_type = (uint8_t) HTP_CONV2D_KERNEL_HMX_WINDOW; + kp->n_threads = (uint8_t) nth; + kp->cwhn = cwhn ? 1 : 0; + kp->w_kmajor = !w_rows ? 1 : 0; + kp->n_row_tiles = n_rt; + kp->ct_chunk = ct; + kp->rt_block = rt_block; + kp->stage_size = stage; + kp->thr_size = thr; + kp->vtcm_size = total; + kp->window.fold = fold; + kp->window.n_cc = n_cc; + kp->window.act_rt_last = 0x780 | 0x2 | (stop << 2); + kp->window.sr = SR; + kp->window.ihs = IHS; + kp->window.max_off = moff; + kp->window.n_bc = n_bc; + kp->window.seg_b = seg_b; + kp->window.seg_t = seg_t; + kp->window.w_cs = w_cs; + kp->window.div_sr = init_fastdiv_values(SR); + kp->window.div_ihs = init_fastdiv_values(IHS); + kp->window.div_kw = init_fastdiv_values(KW); + kp->window.div_tg = init_fastdiv_values(n_tg); + kp->window.div_cc = init_fastdiv_values(n_cc); + kp->window.div_cs = init_fastdiv_values(n_cs); + return true; +} + +// Tiled implicit GEMM, MMA on HMX if available, else HVX +static bool htp_kparams_conv2d_tiled( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * dst, + struct htp_conv2d_kernel_params * kp +) { + if (htp_session_n_hmx(sess) == 0) { + return false; + } + + const struct ggml_tensor * src0 = dst->src[0]; + const struct ggml_tensor * src1 = dst->src[1]; + const int32_t s0 = ggml_get_op_params_i32(dst, 0); + const int32_t d0 = ggml_get_op_params_i32(dst, 4); + + const uint32_t KW = src0->ne[0]; + const uint32_t KH = src0->ne[1]; + const uint32_t Cin = src0->ne[2]; + const uint32_t Cout = src0->ne[3]; + const uint32_t OW = dst->ne[0]; + const uint32_t OH = dst->ne[1]; + const uint32_t N = dst->ne[3]; + const size_t es = ggml_type_size(src0->type); + + if (s0 != 1 || dst->nb[0] != sizeof(float)) { + return false; + } + + // kernel k order must match the staged input: (cin, kh, kw) for WHCN input, (kh, kw, cin) for CWHN input. + // Kernel is either k-contiguous rows per cout (WHCN only) or cout-contiguous with a uniform k stride. + const bool whcn = src1->nb[0] == sizeof(float); + const bool cwhn = !whcn && src1->nb[2] == sizeof(float) && src1->nb[0] == Cin * sizeof(float); + const bool co_c = Cout == 1 || src0->nb[3] == es; + const bool w_rows = whcn && src0->nb[0] == es && (KH == 1 || src0->nb[1] == KW * es) && (Cin == 1 || src0->nb[2] == KW * KH * es); + const size_t ks = whcn ? src0->nb[0] : src0->nb[2]; + bool kmajor = false; + if (whcn) { + kmajor = co_c && ks >= Cout * es && (KH == 1 || src0->nb[1] == KW * ks) && (Cin == 1 || src0->nb[2] == KW * KH * ks); + } else if (cwhn) { + kmajor = co_c && ks >= Cout * es && src0->nb[0] == Cin * ks && (KH == 1 || src0->nb[1] == KW * Cin * ks); + } + if (!w_rows && !kmajor) { + return false; + } + kmajor = kmajor && !w_rows; + + const uint32_t K = KW * KH * Cin; + const uint32_t kg = !cwhn ? K : d0 == 1 ? KW * Cin : Cin; + const uint32_t n_grp = K / kg; + const uint32_t kg_p = hex_round_up(kg, 32); + const uint32_t k_pad = hex_round_up(n_grp * kg_p, 64); + const uint32_t n_kt = k_pad / 32; + const uint32_t n_rt = (Cout + 31) / 32; + const uint32_t n_owt = (OW + 31) / 32; + const uint32_t n_ct = N * OH * n_owt; + const uint32_t wk = (std::min)(k_pad, 512u); + const uint32_t nth = htp_session_n_threads(sess); + const size_t tile = 2048; + + uint32_t rt_block = n_rt; + uint32_t ct = (std::min)(n_ct, 64u); + uint32_t seg = (std::min)(8u, n_owt); + uint32_t n_stage = 1; + uint32_t sr = 0; + size_t stage = 0, ostage = 0, prow = 0, wpack = 0; + size_t w_size = 0, act_size = 0, out_size = 0, thr_size = 0, total = 0; + + while (true) { + const uint32_t wb = 32 * seg + (KW - 1) * d0; + sr = cwhn ? hex_round_up(wb * Cin, 64) : hex_round_up(wb, 32); + stage = cwhn ? (size_t) KH * sr * sizeof(float) : (size_t) Cin * KH * sr * sizeof(float); + ostage = 2 * 32 * (size_t) seg * 32 * sizeof(float); + prow = cwhn ? stage / 2 + 256 + 64 * 128 : 0; + wpack = kmajor ? 2 * (size_t) wk * 64 * sizeof(float) + 96 * 128 : 2 * (size_t) 32 * wk * (sizeof(float) + sizeof(uint16_t)); + thr_size = hex_round_up((std::max)(stage + ostage + prow, wpack), tile); + w_size = (size_t) rt_block * n_kt * tile; + act_size = (size_t) ct * n_kt * tile; + out_size = (size_t) rt_block * ct * tile; + struct htp_conv2d_vtcm_layout L; + htp_conv2d_vtcm_layout_build(&L, rt_block, w_size, act_size, out_size, thr_size, nth); + total = L.total_bytes; + if (total <= htp_session_vtcm_size(sess)) { + break; + } + if (ct > 8) { + ct /= 2; + } else if (seg > 1) { + seg--; + } else if (rt_block > 1) { + rt_block = (rt_block + 1) / 2; + } else if (ct > 1) { + ct /= 2; + } else { + return false; + } + } + + // Second stage buffer: DMA of the next segment overlaps HVX pack of this one. + // Skip large stages. They already fill VTCM, and the extra DMA slows HMX. + { + const size_t thr2 = hex_round_up((std::max)(2 * stage + ostage + prow, wpack), tile); + struct htp_conv2d_vtcm_layout L2; + htp_conv2d_vtcm_layout_build(&L2, rt_block, w_size, act_size, out_size, thr2, nth); + if (stage <= 128 * 1024 && L2.total_bytes <= htp_session_vtcm_size(sess)) { + n_stage = 2; + thr_size = thr2; + total = L2.total_bytes; + } + } + + kp->kernel_type = (uint8_t) HTP_CONV2D_KERNEL_HMX_TILED; + kp->n_threads = (uint8_t) nth; + kp->cwhn = cwhn ? 1 : 0; + kp->w_kmajor = kmajor ? 1 : 0; + kp->n_row_tiles = n_rt; + kp->ct_chunk = ct; + kp->rt_block = rt_block; + kp->stage_size = stage; + kp->thr_size = thr_size; + kp->vtcm_size = total; + kp->tiled.w_kstride = ks; + kp->tiled.k_size = K; + kp->tiled.k_group = kg; + kp->tiled.k_group_pad = kg_p; + kp->tiled.n_groups = n_grp; + kp->tiled.n_k_tiles = n_kt; + kp->tiled.n_ow_tiles = n_owt; + kp->tiled.seg_tiles = seg; + kp->tiled.stage_row = sr; + kp->tiled.n_stage = n_stage; + kp->tiled.wk_chunk = wk; + kp->tiled.div_ow_tiles = init_fastdiv_values(n_owt); + kp->tiled.div_oh = init_fastdiv_values(OH); + return true; +} + +static bool htp_kparams_solve_conv2d_unchecked( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * dst, + struct htp_conv2d_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const uint32_t total_rows = (uint32_t) (dst->ne[1] * dst->ne[2] * dst->ne[3]); + kparams->total_rows = total_rows; + kparams->n_threads = total_rows == 0 ? 1 : (std::min)((uint32_t) htp_session_n_threads(sess), total_rows); + + if (htp_kparams_conv2d_win(sess, dst, kparams)) { + return true; + } + + return htp_kparams_conv2d_tiled(sess, dst, kparams); +} + +static bool htp_kparams_solve_conv2d( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_conv2d_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if ((src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_F32) || + src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + + if (src0->ne[2] != src1->ne[2]) { + return false; + } + + const int32_t s0 = ggml_get_op_params_i32(op, 0); + const int32_t s1 = ggml_get_op_params_i32(op, 1); + const int32_t p0 = ggml_get_op_params_i32(op, 2); + const int32_t p1 = ggml_get_op_params_i32(op, 3); + const int32_t d0 = ggml_get_op_params_i32(op, 4); + const int32_t d1 = ggml_get_op_params_i32(op, 5); + + const int64_t ow = (src1->ne[0] + 2 * p0 - d0 * (src0->ne[0] - 1) - 1) / s0 + 1; + const int64_t oh = (src1->ne[1] + 2 * p1 - d1 * (src0->ne[1] - 1) - 1) / s1 + 1; + if (ow != dst->ne[0] || oh != dst->ne[1] || src0->ne[3] != dst->ne[2] || src1->ne[3] != dst->ne[3]) { + return false; + } + + return htp_kparams_solve_conv2d_unchecked(sess, op, kparams); +} + +static bool htp_kparams_solve_conv2d_dw( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_conv2d_dw_kernel_params * kparams +) { + memset(kparams, 0, sizeof(*kparams)); + + const struct ggml_tensor * src0 = op->src[0]; + const struct ggml_tensor * src1 = op->src[1]; + const struct ggml_tensor * dst = op; + + if ((src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_F32) || + src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + + if (src0->ne[2] != 1 || src0->ne[3] != src1->ne[2]) { + return false; + } + + if (src0->ne[0] * src0->ne[1] > 64) { + return false; + } + + const int32_t s0 = ggml_get_op_params_i32(op, 0); + const int32_t s1 = ggml_get_op_params_i32(op, 1); + const int32_t p0 = ggml_get_op_params_i32(op, 2); + const int32_t p1 = ggml_get_op_params_i32(op, 3); + const int32_t d0 = ggml_get_op_params_i32(op, 4); + const int32_t d1 = ggml_get_op_params_i32(op, 5); + + if (s0 <= 0 || s1 <= 0 || d0 <= 0 || d1 <= 0) { + return false; + } + + const int64_t ow = (src1->ne[0] + 2 * p0 - d0 * (src0->ne[0] - 1) - 1) / s0 + 1; + const int64_t oh = (src1->ne[1] + 2 * p1 - d1 * (src0->ne[1] - 1) - 1) / s1 + 1; + if (ow != dst->ne[0] || oh != dst->ne[1] || dst->ne[2] != src1->ne[2] || dst->ne[3] != src1->ne[3]) { + return false; + } + + const bool cwhn = ggml_is_contiguous_channels(src1); + if (!cwhn && !ggml_is_contiguous(src1)) { + return false; + } + + if (!cwhn && (d0 != 1 || (s0 != 1 && s0 != 2))) { + return false; + } + + const uint32_t c = (uint32_t) src1->ne[2]; + const uint32_t n = (uint32_t) src1->ne[3]; + const uint32_t w = (uint32_t) src1->ne[0]; + const uint32_t h = (uint32_t) src1->ne[1]; + const uint32_t kw = (uint32_t) src0->ne[0]; + const uint32_t kh = (uint32_t) src0->ne[1]; + const uint32_t ow_u = (uint32_t) ow; + const uint32_t oh_u = (uint32_t) oh; + + const uint32_t row_src_bytes = cwhn + ? (w * c * (uint32_t) sizeof(float)) + : (w * (uint32_t) sizeof(float)); + const uint32_t row_dst_bytes = cwhn + ? (ow_u * c * (uint32_t) sizeof(float)) + : (ow_u * (uint32_t) sizeof(float)); + + uint8_t kernel_type = HTP_CONV2D_DW_KERNEL_UNSUPPORTED; + if (cwhn) { + kernel_type = HTP_CONV2D_DW_KERNEL_CWHN; + } else if ((w & 31) == 0 && kw == 3 && kh == 3 && p0 == 1 && p1 == 1 && d0 == 1 && d1 == 1 && s0 == 1 && s1 == 1) { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S1_K3X3; + } else if ((w & 31) == 0 && kw == 3 && kh == 3 && p0 == 1 && p1 == 1 && d0 == 1 && d1 == 1 && s0 == 2 && s1 == 2) { + if (w == 32 && ow_u == 16) { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W32; + } else if (w == 64 && ow_u == 32) { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W64; + } else { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3; + } + } else if (s0 == 1) { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S1; + } else { + kernel_type = HTP_CONV2D_DW_KERNEL_WHCN_S2; + } + + const bool fast_k3x3 = kernel_type >= HTP_CONV2D_DW_KERNEL_WHCN_S1_K3X3; + const uint32_t pad_rows = fast_k3x3 ? 4 : 0; + const uint32_t pad_top_stride = fast_k3x3 ? w : 0; + + const size_t vtcm_budget = (sess && htp_session_vtcm_size(sess) > 0) ? htp_session_vtcm_size(sess) : 0; + if (vtcm_budget == 0) { + return false; + } + + const uint32_t w_size = (uint32_t) (kw * kh * c * ggml_type_size(src0->type)); + + uint32_t max_threads_sess = (uint32_t) htp_session_n_threads(sess); + uint32_t oh_chunk = oh_u; + + uint32_t n_threads = max_threads_sess; + struct htp_conv2d_dw_vtcm_layout layout; + + while (true) { + const uint32_t max_ih_chunk = (std::min)(h, (oh_chunk - 1) * (uint32_t) s1 + (kh - 1) * (uint32_t) d1 + 1); + const uint32_t max_src_bytes = (max_ih_chunk + pad_rows) * row_src_bytes + 128; + const uint32_t max_dst_bytes = oh_chunk * row_dst_bytes + 128; + + htp_conv2d_dw_vtcm_layout_build(&layout, max_src_bytes, max_dst_bytes, w_size, n_threads); + + if (layout.total_bytes <= vtcm_budget && layout.total_bytes > 0) { + break; + } + + if (oh_chunk > 1) { + oh_chunk = (oh_chunk + 1) / 2; + } else if (n_threads > 1) { + n_threads--; + } else { + return false; + } + } + + const uint32_t n_chunks = (oh_u + oh_chunk - 1) / oh_chunk; + const uint32_t total_tasks = cwhn ? (n * n_chunks) : (c * n * n_chunks); + n_threads = (std::min)(n_threads, total_tasks); + if (n_threads == 0) { + n_threads = 1; + } + + const uint32_t max_ih_chunk = (std::min)(h, (oh_chunk - 1) * (uint32_t) s1 + (kh - 1) * (uint32_t) d1 + 1); + const uint32_t max_src_bytes = (max_ih_chunk + pad_rows) * row_src_bytes + 128; + const uint32_t max_dst_bytes = oh_chunk * row_dst_bytes + 128; + htp_conv2d_dw_vtcm_layout_build(&layout, max_src_bytes, max_dst_bytes, w_size, n_threads); + + kparams->kernel_type = kernel_type; + kparams->n_threads = (uint8_t) n_threads; + kparams->cwhn = cwhn ? 1 : 0; + kparams->is_f16 = (src0->type == GGML_TYPE_F16) ? 1 : 0; + kparams->total_tasks = total_tasks; + kparams->vtcm_size = (uint32_t) layout.total_bytes; + kparams->w = w; + kparams->h = h; + kparams->c = c; + kparams->n = n; + kparams->kw = kw; + kparams->kh = kh; + kparams->ow = ow_u; + kparams->oh = oh_u; + kparams->s0 = s0; + kparams->s1 = s1; + kparams->p0 = p0; + kparams->p1 = p1; + kparams->d0 = d0; + kparams->d1 = d1; + kparams->oh_chunk = oh_chunk; + kparams->n_chunks = n_chunks; + kparams->row_src_bytes = row_src_bytes; + kparams->row_dst_bytes = row_dst_bytes; + kparams->pad_top_stride = pad_top_stride; + kparams->div_c = init_fastdiv_values(c); + kparams->div_n_chunks = init_fastdiv_values(n_chunks > 0 ? n_chunks : 1); + + return true; +} + +template +static inline bool htp_kparams_invoke( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + void * kparams +) { + using KParams = decltype(htp_kparams_type(SolveFn)); + KParams tmp; + return SolveFn(sess, op, kparams ? (KParams *) kparams : &tmp); +} + +void htp_opnode_collapse(const struct ggml_hexagon_session * sess, htp_opnode & node) { + const uint32_t n_threads = htp_session_n_threads(sess); + + if (htp_op_is_unary(node.opcode) && htp_unary_is_elementwise(node.opcode)) { + if (node.inputs.empty() || !node.inputs[0] || node.outputs.empty() || !node.outputs[0]) { + return; + } + if (!ggml_are_same_shape(node.inputs[0], node.outputs[0])) { + return; + } + const size_t elem_size = ggml_type_size(node.inputs[0]->type); + struct ggml_tensor src0_c = *node.inputs[0]; + struct ggml_tensor dst_c = *node.outputs[0]; + struct ggml_tensor * tensors[2] = { &src0_c, &dst_c }; + htp_collapse_dims(tensors, 2, elem_size, n_threads); + if (src0_c.ne[0] != node.inputs[0]->ne[0] || src0_c.ne[1] != node.inputs[0]->ne[1]) { + node.inputs[0] = node.add_dummy(src0_c); + node.outputs[0] = node.add_dummy(dst_c); + } + return; + } + + if (htp_op_is_glu(node.opcode)) { + if (node.inputs.size() < 2 || !node.inputs[0] || !node.inputs[1] || node.outputs.empty() || !node.outputs[0]) { + return; + } + if (!ggml_are_same_shape(node.inputs[0], node.outputs[0]) || + !ggml_are_same_shape(node.inputs[1], node.outputs[0])) { + return; + } + const size_t elem_size = ggml_type_size(node.inputs[0]->type); + struct ggml_tensor src0_c = *node.inputs[0]; + struct ggml_tensor src1_c = *node.inputs[1]; + struct ggml_tensor dst_c = *node.outputs[0]; + struct ggml_tensor * tensors[3] = { &src0_c, &src1_c, &dst_c }; + htp_collapse_dims(tensors, 3, elem_size, n_threads); + if (src0_c.ne[0] != node.inputs[0]->ne[0] || src0_c.ne[1] != node.inputs[0]->ne[1]) { + node.inputs[0] = node.add_dummy(src0_c); + node.inputs[1] = node.add_dummy(src1_c); + node.outputs[0] = node.add_dummy(dst_c); + } + return; + } + + if (node.opcode == HTP_OP_MUL_MAT) { + if (node.inputs.size() < 2 || !node.inputs[0] || !node.inputs[1] || node.outputs.empty() || !node.outputs[0]) { + return; + } + const struct ggml_tensor * src0 = node.inputs[0]; + const struct ggml_tensor * src1 = node.inputs[1]; + const struct ggml_tensor * dst = node.outputs[0]; + if (htp_matmul_can_collapse(src0, src1, dst)) { + node.inputs[1] = node.add_dummy(htp_tensor_collapse_rows(src1)); + node.outputs[0] = node.add_dummy(htp_tensor_collapse_rows(dst)); + } + return; + } + + if (node.opcode == HTP_OP_MUL_MAT_ADD) { + if (node.inputs.size() < 2 || !node.inputs[0] || !node.inputs[1] || node.outputs.empty() || !node.outputs[0]) { + return; + } + const struct ggml_tensor * src0 = node.inputs[0]; + const struct ggml_tensor * src1 = node.inputs[1]; + const struct ggml_tensor * src2 = node.inputs.size() > 2 ? node.inputs[2] : nullptr; + const struct ggml_tensor * dst = node.outputs[0]; + if (htp_matmul_add_can_collapse(src0, src1, src2, dst)) { + node.inputs[1] = node.add_dummy(htp_tensor_collapse_rows(src1)); + node.outputs[0] = node.add_dummy(htp_tensor_collapse_rows(dst)); + if (src2 && (src2->ne[1] * src2->ne[2] * src2->ne[3] > 1)) { + node.inputs[2] = node.add_dummy(htp_tensor_collapse_rows(src2)); + } + } + return; + } + + if (node.opcode == HTP_OP_UPSCALE) { + if (node.inputs.empty() || !node.inputs[0] || node.outputs.empty() || !node.outputs[0]) { + return; + } + const struct ggml_tensor * src0 = node.inputs[0]; + const struct ggml_tensor * dst = node.outputs[0]; + + if ((src0->ne[3] > 1 || dst->ne[3] > 1) && + src0->ne[2] == dst->ne[2] && src0->ne[3] == dst->ne[3] && + src0->nb[3] == (size_t) src0->ne[2] * src0->nb[2] && + dst->nb[3] == (size_t) dst->ne[2] * dst->nb[2]) { + struct ggml_tensor src0_c = *src0; + struct ggml_tensor dst_c = *dst; + src0_c.ne[2] *= src0_c.ne[3]; + src0_c.ne[3] = 1; + src0_c.nb[3] = (size_t) src0_c.ne[2] * src0_c.nb[2]; + dst_c.ne[2] *= dst_c.ne[3]; + dst_c.ne[3] = 1; + dst_c.nb[3] = (size_t) dst_c.ne[2] * dst_c.nb[2]; + node.inputs[0] = node.add_dummy(src0_c); + node.outputs[0] = node.add_dummy(dst_c); + } + return; + } +} + +bool htp_kparams_solve( + const struct ggml_hexagon_session * sess, + htp_opnode & node +) { + htp_opnode_collapse(sess, node); + + const ggml_tensor * src0 = node.inputs.empty() ? nullptr : node.inputs[0]; + const ggml_tensor * src1 = node.inputs.size() > 1 ? node.inputs[1] : nullptr; + const ggml_tensor * dst = node.dst(); + + if (htp_op_is_unary(node.opcode)) { + return htp_kparams_solve_unary_impl(sess, node.opcode, src0, src1, dst, node.kparams()); + } + if (htp_op_is_glu(node.opcode)) { + return htp_kparams_solve_unary_mul_glu(sess, node.opcode, src0, src1, dst, node.kparams()); + } + if (node.opcode == HTP_OP_MUL_MAT) { + if (!htp_matmul_check_types(src0, src1, dst)) { + return false; + } + return htp_kparams_solve_matmul_impl(sess, src0, src1, dst, 0, 0, node.kparams()); + } + if (node.opcode == HTP_OP_MUL_MAT_ADD) { + const ggml_tensor * src2 = node.inputs.size() > 2 ? node.inputs[2] : nullptr; + const size_t src2_size = src2 ? hex_round_up(ggml_nbytes(src2), 128) : 0; + return htp_kparams_solve_matmul_impl(sess, src0, src1, dst, src2 ? src2->nb[1] : 0, src2_size, node.kparams()); + } + if (node.opcode == HTP_OP_UPSCALE) { + return htp_kparams_solve_upscale(sess, src0, dst, node.kparams()); + } + + return htp_kparams_solve(sess, node.node, node.kernel_params); +} + +bool htp_kparams_solve( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + void * kparams +) { + const htp_op_code opcode = htp_op_remap(op); + if (htp_op_is_unary(opcode) || htp_op_is_glu(opcode) || opcode == HTP_OP_UPSCALE) { + htp_opnode tmp(opcode, op); + if (!htp_kparams_solve(sess, tmp)) { + return false; + } + if (kparams) { + memcpy(kparams, tmp.kernel_params, sizeof(tmp.kernel_params)); + } + return true; + } + + switch (opcode) { + case HTP_OP_MUL_MAT: + case HTP_OP_MUL_MAT_ID: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_MUL: + case HTP_OP_ADD: + case HTP_OP_ADD_ID: + case HTP_OP_SUB: + case HTP_OP_DIV: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_FLASH_ATTN_EXT: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_GET_ROWS: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_SET_ROWS: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_ROPE: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_SSM_CONV: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_SOFTMAX: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_GATED_DELTA_NET: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_ARGSORT: + case HTP_OP_TOP_K: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_POOL_2D: + case HTP_OP_POOL_1D: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_CONCAT: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_CPY: + case HTP_OP_CPY_FENCE: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_IM2COL: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_IM2COL_3D: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_CONV_2D: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_CONV_2D_DW: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_SUM_ROWS: + case HTP_OP_SUM: + case HTP_OP_ARGMAX: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_REPEAT: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_PAD: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_CUMSUM: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_FILL: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_ROLL: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_DIAG: + return htp_kparams_invoke(sess, op, kparams); + + case HTP_OP_SOLVE_TRI: + return htp_kparams_invoke(sess, op, kparams); + + default: + if (htp_op_is_unary(opcode)) { + return htp_kparams_invoke(sess, op, kparams); + } + if (htp_op_is_glu(opcode)) { + return htp_kparams_invoke(sess, op, kparams); + } + return false; + } +} diff --git a/ggml/src/ggml-hexagon/htp-kparams.h b/ggml/src/ggml-hexagon/htp-kparams.h new file mode 100644 index 000000000000..b757f430b83c --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-kparams.h @@ -0,0 +1,153 @@ +#ifndef HTP_KPARAMS_H +#define HTP_KPARAMS_H + +#include "htp-common.h" + +#include "htp/allreduce-ops.h" +#include "htp/argsort-ops.h" +#include "htp/binary-ops.h" +#include "htp/concat-ops.h" +#include "htp/conv2d-ops.h" +#include "htp/cpy-ops.h" +#include "htp/cumsum-ops.h" +#include "htp/diag-ops.h" +#include "htp/fill-ops.h" +#include "htp/flash-attn-ops.h" +#include "htp/gated-delta-net-ops.h" +#include "htp/get-rows-ops.h" +#include "htp/glu-ops.h" +#include "htp/im2col-ops.h" +#include "htp/matmul-ops.h" +#include "htp/pad-ops.h" +#include "htp/pool-ops.h" +#include "htp/repeat-ops.h" +#include "htp/roll-ops.h" +#include "htp/rope-ops.h" +#include "htp/set-rows-ops.h" +#include "htp/softmax-ops.h" +#include "htp/solve-tri-ops.h" +#include "htp/ssm-conv.h" +#include "htp/sum-rows-ops.h" +#include "htp/unary-ops.h" +#include "htp/upscale-ops.h" + +#include +#include + +bool htp_rows_stride(const int64_t * ne, const size_t * nb, size_t * stride); +bool htp_matmul_can_collapse(const struct ggml_tensor * src0, const struct ggml_tensor * src1, const struct ggml_tensor * dst); +bool htp_matmul_add_can_collapse(const struct ggml_tensor * src0, const struct ggml_tensor * src1, const struct ggml_tensor * src2, const struct ggml_tensor * dst); +ggml_tensor htp_tensor_collapse_rows(const struct ggml_tensor * t); + +template +auto htp_kparams_type(bool (*)(Args...)) -> std::remove_pointer_t(), ...))>>; + +template +static inline bool htp_kparams_check(Args &&... args) { + decltype(htp_kparams_type(SolveFn)) kparams; + return SolveFn(std::forward(args)..., &kparams); +} + +struct htp_opnode; + +bool htp_kparams_solve( + const struct ggml_hexagon_session * sess, + struct htp_opnode & node +); + +void htp_opnode_collapse( + const struct ggml_hexagon_session * sess, + struct htp_opnode & node +); + +bool htp_kparams_solve( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + void * kparams = nullptr +); + +static inline bool htp_kparams_check( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op +) { + return htp_kparams_solve(sess, op, nullptr); +} + +bool htp_kparams_solve_allreduce( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * dst, + uint32_t rank, + uint32_t n_ranks, + bool has_add, + bool is_row_bcast, + bool is_shard_ok, + struct htp_allreduce_kernel_params * kparams +); + +bool htp_kparams_solve_rms_norm_mul( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_unary_kernel_params * kparams +); + +bool htp_kparams_solve_matmul_add( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * src2, + const struct ggml_tensor * dst, + struct htp_mm_kernel_params * kparams +); + +bool htp_kparams_solve_mmnx( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * act, + int32_t n_weights, + struct htp_mm_kernel_params * kparams +); + +bool htp_kparams_solve_mmidnx( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * act, + const struct ggml_tensor * dst, + int32_t n_weights, + struct htp_mm_kernel_params * kparams +); + +bool htp_kparams_solve_repeat_get_rows( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_get_rows_kernel_params * kparams +); + +bool htp_kparams_solve_unary_mul_glu( + const struct ggml_hexagon_session * sess, + uint32_t op, + const struct ggml_tensor * src0, + const struct ggml_tensor * src1, + const struct ggml_tensor * dst, + struct htp_glu_kernel_params * kparams +); + +bool htp_kparams_solve_upscale( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * src0, + const struct ggml_tensor * dst, + struct htp_upscale_kernel_params * kparams +); + +static inline bool htp_kparams_solve_upscale( + const struct ggml_hexagon_session * sess, + const struct ggml_tensor * op, + struct htp_upscale_kernel_params * kparams +) { + return htp_kparams_solve_upscale(sess, op->src[0], op, kparams); +} + +#endif // HTP_KPARAMS_H diff --git a/ggml/src/ggml-hexagon/htp-opnode.cpp b/ggml/src/ggml-hexagon/htp-opnode.cpp new file mode 100644 index 000000000000..d4e5150c0f28 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-opnode.cpp @@ -0,0 +1,274 @@ +#include "htp-opnode.h" + +#include "htp/allreduce-ops.h" +#include "htp/argsort-ops.h" +#include "htp/binary-ops.h" +#include "htp/cumsum-ops.h" +#include "htp/diag-ops.h" +#include "htp/fill-ops.h" +#include "htp/flash-attn-ops.h" +#include "htp/gated-delta-net-ops.h" +#include "htp/get-rows-ops.h" +#include "htp/glu-ops.h" +#include "htp/matmul-ops.h" +#include "htp/pad-ops.h" +#include "htp/repeat-ops.h" +#include "htp/roll-ops.h" +#include "htp/softmax-ops.h" +#include "htp/solve-tri-ops.h" +#include "htp/ssm-conv.h" +#include "htp/sum-rows-ops.h" +#include "htp/unary-ops.h" +#include "htp/upscale-ops.h" + +#include + +std::string htp_opnode::name() const { + switch (opcode) { + case HTP_OP_MDEV_GROUP: return "MDEV_GROUP"; + case HTP_OP_CPY_FENCE: return "CPY+FENCE"; + case HTP_OP_FENCE: return (node && node->op_params[1] == 0) ? "FENCE_WAIT" : "FENCE_SIGNAL"; + case HTP_OP_ALLREDUCE: return "ALLREDUCE"; + case HTP_OP_ALLREDUCE_ADD: return "ALLREDUCE+ADD"; + case HTP_OP_HADAMARD: return "MUL_MAT_HADAMARD"; + case HTP_OP_MUL_MAT_NX: return "MUL_MAT_NX"; + case HTP_OP_MUL_MAT_ID_NX: return "MUL_MAT_ID_NX"; + case HTP_OP_ADD: + case HTP_OP_SUB: + case HTP_OP_MUL: + case HTP_OP_DIV: + if (!fused.empty()) { + const auto * kp = kparams(); + if (kp->kernel_type != HTP_BINARY_KERNEL_SCALAR) { + switch (opcode) { + case HTP_OP_ADD: return "ADD_NX"; + case HTP_OP_SUB: return "SUB_NX"; + case HTP_OP_MUL: return "MUL_NX"; + case HTP_OP_DIV: return "DIV_NX"; + default: break; + } + } + } + break; + default: + break; + } + + if (!node) { + return ""; + } + if (htp_is_hadamard(node)) { + return "MUL_MAT_HADAMARD"; + } + + std::string res = ggml_op_desc(node); + for (const auto * t : fused) { + res += "+"; + res += ggml_op_desc(t); + } + return res; +} + +static const char * format_tensor_name(const struct ggml_tensor * t) { + return t ? t->name : "NONE"; +} + +static std::string format_tensor_dims(const struct ggml_tensor * t) { + if (!t) { + return "NONE"; + } + char buf[64]; + if (t->ne[2] == 1 && t->ne[3] == 1) { + snprintf(buf, sizeof(buf), "%d:%d", (int) t->ne[0], (int) t->ne[1]); + } else { + snprintf(buf, sizeof(buf), "%d:%d:%d:%d", (int) t->ne[0], (int) t->ne[1], (int) t->ne[2], (int) t->ne[3]); + } + return buf; +} + +static const char * format_tensor_type(const struct ggml_tensor * t) { + return t ? ggml_type_name(t->type) : "NONE"; +} + +static std::string format_tensor_strides(const struct ggml_tensor * t) { + if (!t) { + return "NONE"; + } + char buf[64]; + const char * c = ggml_is_contiguous(t) ? "" : "!"; + if (t->ne[2] == 1 && t->ne[3] == 1) { + snprintf(buf, sizeof(buf), "%zu:%zu%s", (size_t) t->nb[0], (size_t) t->nb[1], c); + } else { + snprintf(buf, sizeof(buf), "%zu:%zu:%zu:%zu%s", (size_t) t->nb[0], (size_t) t->nb[1], (size_t) t->nb[2], (size_t) t->nb[3], c); + } + return buf; +} + +static const char * format_tensor_buff(const struct ggml_tensor * t) { + if (t && t->buffer) { + return ggml_backend_buffer_name(t->buffer); + } + return "NONE"; +} + +template +static std::string format_op_tensors(const htp_opnode & node, Fn fn) { + std::string res; + const auto & inputs = node.get_inputs(); + const auto & outputs = node.get_outputs(); + + if (!inputs.empty()) { + for (size_t i = 0; i < inputs.size(); i++) { + if (i > 0) res += " x "; + res += fn(inputs[i]); + } + res += " -> "; + } + + if (outputs.empty()) { + res += fn(node.dst()); + } else { + for (size_t i = 0; i < outputs.size(); i++) { + if (i > 0) res += " x "; + res += fn(outputs[i]); + } + } + return res; +} + +static std::string format_kernel_params(const htp_opnode & node) { + char str[128]; + const size_t max_size = sizeof(str); + + if (node.opcode == HTP_OP_MUL_MAT || node.opcode == HTP_OP_MUL_MAT_ID || + node.opcode == HTP_OP_MUL_MAT_NX || node.opcode == HTP_OP_MUL_MAT_ID_NX || + node.opcode == HTP_OP_MUL_MAT_ADD) { + const auto * kparams = node.kparams(); + const char * path = "unknown"; + int32_t type = kparams->kernel_type; + if (type == HTP_MM_KERNEL_HMX_2D || type == HTP_MM_KERNEL_HMX_BATCHED) { + path = (kparams->tile_size > 0) ? "hmx-tiled" : "hmx-flat"; + } else if (type == HTP_MM_KERNEL_HVX_F16_F16_VTCM || type == HTP_MM_KERNEL_HVX_F32_F32_VTCM || + type == HTP_MM_KERNEL_HVX_BF16_F32_VTCM) { + path = "hvx-flat"; + } else if (type == HTP_MM_KERNEL_HVX_QUANT_ROW || type == HTP_MM_KERNEL_HVX_QUANT_BLOCK) { + path = "hvx-tiled"; + } + snprintf(str, max_size, "%s vtcm %d", path, (int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_FLASH_ATTN_EXT) { + const auto * kparams = node.kparams(); + const char * path = "unknown"; + int32_t type = kparams->kernel_type; + if (type == HTP_FA_KERNEL_HMX) { + path = kparams->u.hmx.pipeline ? "hmx-pipe" : "hmx-seq"; + } else if (type == HTP_FA_KERNEL_HVX) { + path = "hvx"; + } + snprintf(str, max_size, "%s vtcm %d", path, (int) kparams->vtcm_size); + } else if (htp_op_is_unary(node.opcode)) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s vtcm %d", kparams->col_tile ? "wide-row" : "row-block", (int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_MDEV_GROUP && node.node) { + snprintf(str, max_size, "idx %d count %d", (int) node.node->op_params[0], (int) node.dst()->ne[1]); + } else if ((node.opcode == HTP_OP_FENCE || node.opcode == HTP_OP_CPY_FENCE) && node.node) { + snprintf(str, max_size, "seq 0x%x", (uint32_t) node.node->op_params[0]); + } else if (node.opcode == HTP_OP_ALLREDUCE && node.node) { + snprintf(str, max_size, "seq 0x%x -> 0x%x", (uint32_t) node.node->op_params[0], (uint32_t) node.node->op_params[1]); + } else if (node.opcode == HTP_OP_SSM_CONV) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s vtcm %d", kparams->n_t == 1 ? "decode" : "prefill", (int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_SOFTMAX) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "k%d nth %d vtcm %d", (int) kparams->kernel_type, (int) kparams->n_threads, (int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_GATED_DELTA_NET) { + const auto * kparams = node.kparams(); + const char * path = (kparams->kernel_type == HTP_GDN_KERNEL_HMX_CHUNKED) ? "hmx-chunked" : "hvx-recurrent"; + snprintf(str, max_size, "%s-%s vtcm %u", path, kparams->kda ? "kda" : "scalar", + (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_MUL || node.opcode == HTP_OP_ADD || node.opcode == HTP_OP_ADD_ID || + node.opcode == HTP_OP_SUB || node.opcode == HTP_OP_DIV) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "vtcm %u", (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_ARGSORT || node.opcode == HTP_OP_TOP_K) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s nth %d nchk %d chk %d vtcm %d", + node.opcode == HTP_OP_TOP_K ? "top_k" : "argsort", + (int) kparams->n_threads, (int) kparams->n_chunks, + (int) kparams->chunk_elems, (int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_GET_ROWS) { + const auto * kparams = node.kparams(); + const char * ktype_str = "unknown"; + switch (kparams->kernel_type) { + case HTP_GET_ROWS_KERNEL_SAMETYPE: ktype_str = "sametype"; break; + case HTP_GET_ROWS_KERNEL_TILED: ktype_str = "tiled"; break; + case HTP_GET_ROWS_KERNEL_FLAT: ktype_str = "flat"; break; + } + snprintf(str, max_size, "%s%s vtcm %u", ktype_str, kparams->n_threads > 1 ? "-multi" : "", (unsigned int) kparams->vtcm_size); + } else if (htp_op_is_glu(node.opcode)) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "nth %d vtcm %u", (int) kparams->n_threads, (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_PAD) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "k%d nth %d vtcm %u", (int) kparams->kernel_type, (int) kparams->n_threads, (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_CUMSUM) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s nth %d vtcm %u", kparams->use_dma ? "dma" : "hvx", (int) kparams->n_threads, (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_FILL) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s nth %d", kparams->kernel_type == HTP_FILL_KERNEL_CONTIGUOUS ? "contig" : "strided", (int) kparams->n_threads); + } else if (node.opcode == HTP_OP_ROLL) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "k%d nth %d", (int) kparams->kernel_type, (int) kparams->n_threads); + } else if (node.opcode == HTP_OP_DIAG) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s nth %d vtcm %u", kparams->use_dma ? "dma" : "hvx", (int) kparams->n_threads, (unsigned int) kparams->vtcm_size); + } else if (node.opcode == HTP_OP_SOLVE_TRI) { + const auto * kparams = node.kparams(); + snprintf(str, max_size, "%s nth %d", kparams->batched ? "batched" : "chunked", (int) kparams->n_threads); + } else if (node.opcode == HTP_OP_UPSCALE) { + const auto * kparams = node.kparams(); + const char * ktype_str = "unknown"; + switch (kparams->kernel_type) { + case HTP_UPSCALE_KERNEL_NEAREST: ktype_str = "nearest"; break; + case HTP_UPSCALE_KERNEL_NEAREST_2X: ktype_str = "nearest-2x"; break; + case HTP_UPSCALE_KERNEL_NEAREST_4X: ktype_str = "nearest-4x"; break; + case HTP_UPSCALE_KERNEL_BILINEAR: ktype_str = kparams->align_corners ? "bilinear-ac" : "bilinear"; break; + case HTP_UPSCALE_KERNEL_BILINEAR_2X: ktype_str = "bilinear-2x"; break; + case HTP_UPSCALE_KERNEL_BILINEAR_AA: ktype_str = "bilinear-aa"; break; + case HTP_UPSCALE_KERNEL_BICUBIC: ktype_str = "bicubic"; break; + } + snprintf(str, max_size, "%s nth %d chk %d vtcm %u", ktype_str, (int) kparams->n_threads, (int) kparams->dst_nrows_per_chunk, (unsigned int) kparams->vtcm_size); + } else { + snprintf(str, max_size, "----"); + } + return str; +} + +static void append_section(std::string & res, const std::string & sec) { + if (!res.empty()) { + res += "|"; + } + res += sec; +} + +std::string htp_format_tensor(const ggml_tensor * t, uint32_t flags) { + std::string res; + if (flags & HTP_OPFMT_NAMES) append_section(res, format_tensor_name(t)); + if (flags & HTP_OPFMT_DIMS) append_section(res, format_tensor_dims(t)); + if (flags & HTP_OPFMT_TYPES) append_section(res, format_tensor_type(t)); + if (flags & HTP_OPFMT_STRIDES) append_section(res, format_tensor_strides(t)); + if (flags & HTP_OPFMT_BUFFS) append_section(res, format_tensor_buff(t)); + return res; +} + +std::string htp_format_op(const htp_opnode & node, uint32_t flags) { + std::string res; + if (flags & HTP_OPFMT_OP) append_section(res, node.name()); + if (flags & HTP_OPFMT_NAMES) append_section(res, format_op_tensors(node, format_tensor_name)); + if (flags & HTP_OPFMT_DIMS) append_section(res, format_op_tensors(node, format_tensor_dims)); + if (flags & HTP_OPFMT_TYPES) append_section(res, format_op_tensors(node, format_tensor_type)); + if (flags & HTP_OPFMT_STRIDES) append_section(res, format_op_tensors(node, format_tensor_strides)); + if (flags & HTP_OPFMT_BUFFS) append_section(res, format_op_tensors(node, format_tensor_buff)); + if (flags & HTP_OPFMT_KPARAMS) append_section(res, format_kernel_params(node)); + return res; +} diff --git a/ggml/src/ggml-hexagon/htp-opnode.h b/ggml/src/ggml-hexagon/htp-opnode.h index 8ff38545c74e..a30c5b600bcb 100644 --- a/ggml/src/ggml-hexagon/htp-opnode.h +++ b/ggml/src/ggml-hexagon/htp-opnode.h @@ -1,38 +1,74 @@ #ifndef HTP_OPNODE_H #define HTP_OPNODE_H -#define GGML_COMMON_IMPL_CPP #include "ggml-backend-impl.h" -#include "ggml-common.h" +#include "ggml-impl.h" +#include "htp/htp-ops.h" -#include +#include +#include +#include #include #include -#include -#include -#include "htp-ops.h" -#include "htp/matmul-ops.h" -#include "htp/flash-attn-ops.h" -#include "htp/unary-ops.h" -#include "htp/binary-ops.h" -#include "htp/allreduce-ops.h" -#include "htp/ssm-conv.h" -#include "htp/gated-delta-net-ops.h" -#include "htp/softmax-ops.h" -#include "htp/argsort-ops.h" -#include "htp/get-rows-ops.h" + +#define HTP_OP_MAX_FUSED 16 + +// local std::inplace_vector replacement +template +struct htp_opvec { + T data[MAX_N] {}; + size_t n = 0; + + htp_opvec() = default; + htp_opvec(std::initializer_list init) { + GGML_ASSERT(init.size() <= MAX_N); + for (const auto & v : init) { + data[n++] = v; + } + } + + size_t size() const { return n; } + bool empty() const { return n == 0; } + void clear() { n = 0; } + T * begin() { return data; } + T * end() { return data + n; } + const T * begin() const { return data; } + const T * end() const { return data + n; } + T & back() { return data[n - 1]; } + const T & back() const { return data[n - 1]; } + T & operator[](size_t i) { return data[i]; } + const T & operator[](size_t i) const { return data[i]; } + + void push_back(T val) { + GGML_ASSERT(n < MAX_N); + data[n++] = val; + } + + void insert(T * pos, T val) { + GGML_ASSERT(n < MAX_N); + for (T * p = data + n; p > pos; --p) { + *p = *(p - 1); + } + *pos = val; + n++; + } +}; + +static inline bool htp_is_hadamard(const struct ggml_tensor * t) { + return t && t->op == GGML_OP_MUL_MAT && ggml_get_op_params_i32(t, 1) == GGML_HINT_SRC0_IS_HADAMARD; +} struct htp_opnode { - ggml_tensor * node { nullptr }; - htp_op_code opcode { HTP_OP_INVALID }; - int32_t kernel_params[HTP_OP_MAX_KERN_PARAMS] {0}; + const ggml_tensor * node { nullptr }; + htp_op_code opcode { HTP_OP_INVALID }; + int32_t params[HTP_OP_MAX_PARAMS] {0}; + int32_t kernel_params[HTP_OP_MAX_KERN_PARAMS] {0}; - std::vector fused; - std::vector> dummy; + std::vector> dummy; - std::vector inputs; - std::vector outputs; - std::string name; + htp_opvec fused; + htp_opvec inputs; + htp_opvec outputs; int n_active_src(const ggml_tensor * t) const { if (!t) return 0; @@ -44,28 +80,36 @@ struct htp_opnode { return 0; } - void init(ggml_tensor * node) { + void init(const ggml_tensor * node) { + static_assert(sizeof(this->params) == sizeof(this->node->op_params), "params size mismatch"); + this->node = node; - if (this->node) { - this->name = ggml_op_desc(this->node); + if (!node) return; - // Build inputs (preserving optional nullptrs) + memcpy(this->params, this->node->op_params, sizeof(this->params)); + + // Build inputs (preserving optional nullptrs) + if (htp_is_hadamard(this->node)) { + this->inputs.push_back(this->node->src[1]); + } else { int n_inputs = n_active_src(this->node); - this->inputs.resize(n_inputs, nullptr); for (int i = 0; i < n_inputs; i++) { - this->inputs[i] = this->node->src[i]; + this->inputs.push_back(this->node->src[i]); } - - // Build outputs - this->outputs.push_back(this->dst()); } + + // Build outputs + this->outputs.push_back(this->dst()); } - htp_opnode(htp_op_code opcode = HTP_OP_INVALID, ggml_tensor * node = nullptr) : opcode(opcode) { + htp_opnode(htp_op_code opcode = HTP_OP_INVALID, const ggml_tensor * node = nullptr) : opcode(opcode) { + init(node); + } + + htp_opnode(const ggml_tensor * node) : opcode(HTP_OP_INVALID) { init(node); } - ggml_op op() const { return node->op; } const ggml_tensor * src0() const { return node->src[0]; } const ggml_tensor * src1() const { return node->src[1]; } const ggml_tensor * dst() const { return outputs.empty() ? node : outputs.back(); } @@ -75,337 +119,54 @@ struct htp_opnode { return dummy.back().get(); } - void add_fused(ggml_tensor * t, bool extra_dst = false) { - fused.push_back(t); - - name += "+"; - name += ggml_op_desc(t); - - if (extra_dst) { - outputs.push_back(t); - } else { - outputs.clear(); - outputs.push_back(t); - } - - // Remove the newly fused intermediate output tensor t from inputs (if it was there) - inputs.erase(std::remove(inputs.begin(), inputs.end(), t), inputs.end()); - - // Append new inputs from t, preserving middle nullptrs - int n_inputs = n_active_src(t); - for (int i = 0; i < n_inputs; i++) { - const auto * src = t->src[i]; - if (!src) { - inputs.push_back(nullptr); - } else if (src != node && - std::find(fused.begin(), fused.end(), src) == fused.end() && - std::find(inputs.begin(), inputs.end(), src) == inputs.end()) { - inputs.push_back(src); - } - } - } - - const std::vector & get_inputs() const { + const htp_opvec & get_inputs() const { return inputs; } - const std::vector & get_outputs() const { + const htp_opvec & get_outputs() const { return outputs; } - std::string op_name() const { - return name; + template + T * kparams() { + static_assert(sizeof(T) <= sizeof(kernel_params), "kparams size exceeds HTP_OP_MAX_KERN_PARAMS"); + static_assert(alignof(T) <= alignof(int32_t), "kparams alignment exceeds int32_t"); + return reinterpret_cast(kernel_params); } - bool is_empty() const { - return ggml_op_is_empty(node->op); + template + const T * kparams() const { + static_assert(sizeof(T) <= sizeof(kernel_params), "kparams size exceeds HTP_OP_MAX_KERN_PARAMS"); + static_assert(alignof(T) <= alignof(int32_t), "kparams alignment exceeds int32_t"); + return reinterpret_cast(kernel_params); } - bool stackable() const { - switch (this->op()) { - case GGML_OP_MUL_MAT: - case GGML_OP_MUL_MAT_ID: - return ggml_is_quantized(this->src0()->type); - default: - return false; - } + template + void set_kparams(const T & kp) { + static_assert(sizeof(T) <= sizeof(kernel_params), "kparams size exceeds HTP_OP_MAX_KERN_PARAMS"); + static_assert(alignof(T) <= alignof(int32_t), "kparams alignment exceeds int32_t"); + memcpy(kernel_params, &kp, sizeof(T)); } - bool same_input(const htp_opnode& n) const { - return n.src1() == this->src1(); - } + std::string name() const; }; -struct htp_opformat { - char strides[64 * GGML_MAX_SRC]; - char dims[64 * GGML_MAX_SRC]; - char types[16 * GGML_MAX_SRC]; - char buffs[64 * GGML_MAX_SRC]; - char names[64 * GGML_MAX_SRC]; - char kparams[128]; - - int format_tensor_dims(char * str, size_t max_size, const struct ggml_tensor * t) { - if (!t) { - return snprintf(str, max_size, "NONE"); - } - if (t->ne[2] == 1 && t->ne[3] == 1) { - return snprintf(str, max_size, "%d:%d", (int) t->ne[0], (int) t->ne[1]); - } else { - return snprintf(str, max_size, "%d:%d:%d:%d", (int) t->ne[0], (int) t->ne[1], (int) t->ne[2], (int) t->ne[3]); - } - } - - void format_op_dims(char * str, size_t max_size, const htp_opnode & node) { - char * p = str; - char * p_end = str + max_size; - auto inputs = node.get_inputs(); - - if (!inputs.empty()) { - p += std::min((size_t)format_tensor_dims(p, p_end - p, inputs[0]), (size_t)(p_end - p)); - - for (size_t i = 1; i < inputs.size(); i++) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " x "), (size_t)(p_end - p)); - } - if (p < p_end) { - p += std::min((size_t)format_tensor_dims(p, p_end - p, inputs[i]), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " -> "), (size_t)(p_end - p)); - } - } - - char self[64]; - format_tensor_dims(self, sizeof(self), node.dst()); - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", self), (size_t)(p_end - p)); - } - } - - int format_tensor_strides(char * str, size_t max_size, const struct ggml_tensor * t) { - if (!t) { - return snprintf(str, max_size, "NONE"); - } - const char * c = ggml_is_contiguous(t) ? "" : "!"; - - if (t->ne[2] == 1 && t->ne[3] == 1) { - return snprintf(str, max_size, "%zu:%zu%s", (size_t) t->nb[0], (size_t) t->nb[1], c); - } else { - return snprintf(str, max_size, "%zu:%zu:%zu:%zu%s", (size_t) t->nb[0], (size_t) t->nb[1], (size_t) t->nb[2], (size_t) t->nb[3], c); - } - } - - void format_op_strides(char * str, size_t max_size, const htp_opnode & node) { - char * p = str; - char * p_end = str + max_size; - auto inputs = node.get_inputs(); - - if (!inputs.empty()) { - p += std::min((size_t)format_tensor_strides(p, p_end - p, inputs[0]), (size_t)(p_end - p)); - - for (size_t i = 1; i < inputs.size(); i++) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " x "), (size_t)(p_end - p)); - } - if (p < p_end) { - p += std::min((size_t)format_tensor_strides(p, p_end - p, inputs[i]), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " -> "), (size_t)(p_end - p)); - } - } - - char self[64]; - format_tensor_strides(self, sizeof(self), node.dst()); - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", self), (size_t)(p_end - p)); - } - } - - void format_op_types(char * str, size_t max_size, const htp_opnode & node) { - char * p = str; - char * p_end = str + max_size; - auto inputs = node.get_inputs(); - - if (!inputs.empty()) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", inputs[0] ? ggml_type_name(inputs[0]->type) : "NONE"), (size_t)(p_end - p)); - } - - for (size_t i = 1; i < inputs.size(); i++) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " x "), (size_t)(p_end - p)); - } - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", inputs[i] ? ggml_type_name(inputs[i]->type) : "NONE"), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " -> "), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", ggml_type_name(node.dst()->type)), (size_t)(p_end - p)); - } - } - - const char * tensor_buff_name(const struct ggml_tensor * t) { - if (t && t->buffer) { - return ggml_backend_buffer_name(t->buffer); - } - return "NONE"; - } - - void format_op_buffs(char * str, size_t max_size, const htp_opnode & node) { - char * p = str; - char * p_end = str + max_size; - auto inputs = node.get_inputs(); - - if (!inputs.empty()) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", tensor_buff_name(inputs[0])), (size_t)(p_end - p)); - } - - for (size_t i = 1; i < inputs.size(); i++) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " x "), (size_t)(p_end - p)); - } - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", tensor_buff_name(inputs[i])), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " -> "), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", tensor_buff_name(node.dst())), (size_t)(p_end - p)); - } - } - - void format_op_names(char * str, size_t max_size, const htp_opnode & node) { - char * p = str; - char * p_end = str + max_size; - auto inputs = node.get_inputs(); - - if (!inputs.empty()) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", inputs[0] ? inputs[0]->name : "NONE"), (size_t)(p_end - p)); - } - - for (size_t i = 1; i < inputs.size(); i++) { - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " x "), (size_t)(p_end - p)); - } - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", inputs[i] ? inputs[i]->name : "NONE"), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, " -> "), (size_t)(p_end - p)); - } - } - - if (p < p_end) { - p += std::min((size_t)snprintf(p, p_end - p, "%s", node.dst()->name), (size_t)(p_end - p)); - } - } - void format_kernel_params(char * str, size_t max_size, const htp_opnode & node) { - if (node.opcode == HTP_OP_MUL_MAT || node.opcode == HTP_OP_MUL_MAT_ID || - node.opcode == HTP_OP_MUL_MAT_NX || node.opcode == HTP_OP_MUL_MAT_ID_NX || - node.opcode == HTP_OP_MUL_MAT_ADD) { - const auto * kparams = (const struct htp_mm_kernel_params *) node.kernel_params; - const char * path = "unknown"; - int32_t type = kparams->kernel_type; - if (type == HTP_MM_KERNEL_HMX_2D || type == HTP_MM_KERNEL_HMX_F16_BATCHED) { - path = "hmx-tiled"; - } else if (type == HTP_MM_KERNEL_HVX_F16_F16_VTCM || type == HTP_MM_KERNEL_HVX_F32_F32_VTCM || - type == HTP_MM_KERNEL_HVX_QUANT_ROW || type == HTP_MM_KERNEL_HVX_QUANT_BLOCK) { - path = "hvx-tiled"; - } - snprintf(str, max_size, "%s vtcm %d", path, (int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_FLASH_ATTN_EXT) { - const auto * kparams = (const struct htp_fa_kernel_params *) node.kernel_params; - const char * path = "unknown"; - int32_t type = kparams->kernel_type; - if (type == HTP_FA_KERNEL_HMX) { - path = kparams->u.hmx.pipeline ? "hmx-pipe" : "hmx-seq"; - } else if (type == HTP_FA_KERNEL_HVX) { - path = "hvx"; - } - snprintf(str, max_size, "%s vtcm %d", path, (int) kparams->vtcm_size); - } else if (htp_op_is_unary(node.opcode)) { - const auto * kparams = (const struct htp_unary_kernel_params *) node.kernel_params; - snprintf(str, max_size, "%s vtcm %d", kparams->col_tile ? "wide-row" : "row-block", (int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_MDEV_GROUP && node.node) { - snprintf(str, max_size, "idx %d count %d", (int) node.node->op_params[0], (int) node.dst()->ne[1]); - } else if ((node.opcode == HTP_OP_FENCE || node.opcode == HTP_OP_CPY_FENCE) && node.node) { - snprintf(str, max_size, "seq 0x%x", (uint32_t) node.node->op_params[0]); - } else if (node.opcode == HTP_OP_ALLREDUCE && node.node) { - snprintf(str, max_size, "seq 0x%x -> 0x%x", (uint32_t) node.node->op_params[0], (uint32_t) node.node->op_params[1]); - } else if (node.opcode == HTP_OP_SSM_CONV) { - const auto * kparams = (const struct htp_ssm_conv_kernel_params *) node.kernel_params; - snprintf(str, max_size, "%s vtcm %d", kparams->n_t == 1 ? "decode" : "prefill", (int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_SOFTMAX) { - const auto * kparams = (const struct htp_softmax_kernel_params *) node.kernel_params; - snprintf(str, max_size, "k%d nth %d vtcm %d", (int) kparams->kernel_id, (int) kparams->n_threads, (int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_GATED_DELTA_NET) { - const auto * kparams = (const struct htp_gdn_kernel_params *) node.kernel_params; - const char * path = (kparams->kernel_type == HTP_GDN_KERNEL_HMX_CHUNKED) ? "hmx-chunked" : "hvx-recurrent"; - snprintf(str, max_size, "%s-%s vtcm %u", path, kparams->kda ? "kda" : "scalar", - (unsigned int) (kparams->vtcm_size ? kparams->vtcm_size : kparams->vtcm_per_thread * kparams->n_threads)); - } else if (node.opcode == HTP_OP_MUL || node.opcode == HTP_OP_ADD || node.opcode == HTP_OP_ADD_ID || - node.opcode == HTP_OP_SUB || node.opcode == HTP_OP_DIV) { - const auto * kparams = (const struct htp_binary_kernel_params *) node.kernel_params; - snprintf(str, max_size, "vtcm %u", (unsigned int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_ARGSORT || node.opcode == HTP_OP_TOP_K) { - const auto * kparams = (const struct htp_sort_kernel_params *) node.kernel_params; - snprintf(str, max_size, "%s nth %d nchk %d chk %d vtcm %d", - node.opcode == HTP_OP_TOP_K ? "top_k" : "argsort", - (int) kparams->n_threads, (int) kparams->n_chunks, - (int) kparams->chunk_elems, (int) kparams->vtcm_size); - } else if (node.opcode == HTP_OP_GET_ROWS) { - const auto * kparams = (const struct htp_get_rows_kernel_params *) node.kernel_params; - const char * ktype_str = "unknown"; - switch (kparams->kernel_type) { - case HTP_GET_ROWS_KERNEL_SAMETYPE: ktype_str = "sametype"; break; - case HTP_GET_ROWS_KERNEL_TILED: ktype_str = "tiled"; break; - case HTP_GET_ROWS_KERNEL_FLAT: ktype_str = "flat"; break; - } - snprintf(str, max_size, "%s%s vtcm %u", ktype_str, kparams->n_threads > 1 ? "-multi" : "", (unsigned int) kparams->vtcm_size); - } else { - snprintf(str, max_size, "----"); - } - - } - - void format(const htp_opnode & node) { - format_op_dims(dims, sizeof(dims), node); - format_op_strides(strides, sizeof(strides), node); - format_op_types(types, sizeof(types), node); - format_op_buffs(buffs, sizeof(buffs), node); - format_op_names(names, sizeof(names), node); - format_kernel_params(kparams, sizeof(kparams), node); - } - - htp_opformat() { - strides[0] = '\0'; - dims[0] = '\0'; - types[0] = '\0'; - buffs[0] = '\0'; - names[0] = '\0'; - kparams[0] = '\0'; - } - htp_opformat(const htp_opnode & node) { format(node); } +enum htp_opformat_flags { + HTP_OPFMT_OP = (1 << 0), + HTP_OPFMT_NAMES = (1 << 1), + HTP_OPFMT_DIMS = (1 << 2), + HTP_OPFMT_TYPES = (1 << 3), + HTP_OPFMT_STRIDES = (1 << 4), + HTP_OPFMT_BUFFS = (1 << 5), + HTP_OPFMT_KPARAMS = (1 << 6), + + HTP_OPFMT_EXEC = HTP_OPFMT_OP | HTP_OPFMT_NAMES | HTP_OPFMT_DIMS | HTP_OPFMT_TYPES | HTP_OPFMT_STRIDES | HTP_OPFMT_BUFFS | HTP_OPFMT_KPARAMS, + HTP_OPFMT_SUPP = HTP_OPFMT_OP | HTP_OPFMT_NAMES | HTP_OPFMT_DIMS | HTP_OPFMT_TYPES | HTP_OPFMT_STRIDES | HTP_OPFMT_BUFFS, + HTP_OPFMT_PROF = HTP_OPFMT_OP | HTP_OPFMT_NAMES | HTP_OPFMT_DIMS | HTP_OPFMT_TYPES | HTP_OPFMT_STRIDES | HTP_OPFMT_KPARAMS, + HTP_OPFMT_TENSOR = HTP_OPFMT_NAMES | HTP_OPFMT_DIMS | HTP_OPFMT_TYPES | HTP_OPFMT_STRIDES, }; +std::string htp_format_op(const htp_opnode & node, uint32_t flags = HTP_OPFMT_EXEC); +std::string htp_format_tensor(const ggml_tensor * t, uint32_t flags = HTP_OPFMT_TENSOR); + #endif // HTP_OPNODE_H diff --git a/ggml/src/ggml-hexagon/htp-repack.cpp b/ggml/src/ggml-hexagon/htp-repack.cpp new file mode 100644 index 000000000000..d2e3df2cf4b4 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-repack.cpp @@ -0,0 +1,1636 @@ +#include "htp-repack.h" + +#define GGML_COMMON_IMPL_CPP +#include "ggml-common.h" +#include "ggml-impl.h" +#include "ggml-quants.h" + +#include +#include +#include +#include +#include + +#if defined(__ARM_NEON) || defined(__aarch64__) +# include +#endif + +// --- 4-bit block-32 nibble helpers (shared by Q4_0, IQ4_NL, Q4_1, MXFP4) --- + +static inline void unpack_nibbles_32(uint8_t * dst, const uint8_t * qs) { + for (unsigned int i = 0; i < 16; ++i) { + dst[i + 0] = qs[i] & 0x0F; + dst[i + 16] = qs[i] >> 4; + } +} + +static inline void pack_nibbles_32(uint8_t * qs, const uint8_t * src) { + for (unsigned int i = 0; i < 16; ++i) { + qs[i] = src[i + 0] | (src[i + 16] << 4); + } +} + +static inline void transpose_nibbles_to_tile(uint8_t * tile_dst, const uint8_t tile_quants[32][32]) { + for (int cp = 0; cp < 16; cp++) { + for (int row = 0; row < 32; row++) { + tile_dst[cp * 32 + row] = (tile_quants[row][2 * cp + 1] << 4) | tile_quants[row][2 * cp]; + } + } +} + +static inline void transpose_tile_to_nibbles(uint8_t tile_quants[32][32], const uint8_t * tile_src) { + for (int cp = 0; cp < 16; cp++) { + for (int row = 0; row < 32; row++) { + const uint8_t val = tile_src[cp * 32 + row]; + tile_quants[row][2 * cp + 0] = val & 0x0F; + tile_quants[row][2 * cp + 1] = val >> 4; + } + } +} + +#if defined(__ARM_NEON) || defined(__aarch64__) +static void repack_neon_transpose8x8(const uint8x8_t rows[8], uint8x8_t columns[8]) { + const uint8x8x2_t t0 = vtrn_u8(rows[0], rows[1]); + const uint8x8x2_t t1 = vtrn_u8(rows[2], rows[3]); + const uint8x8x2_t t2 = vtrn_u8(rows[4], rows[5]); + const uint8x8x2_t t3 = vtrn_u8(rows[6], rows[7]); + const uint16x4x2_t t4 = vtrn_u16(vreinterpret_u16_u8(t0.val[0]), vreinterpret_u16_u8(t1.val[0])); + const uint16x4x2_t t5 = vtrn_u16(vreinterpret_u16_u8(t0.val[1]), vreinterpret_u16_u8(t1.val[1])); + const uint16x4x2_t t6 = vtrn_u16(vreinterpret_u16_u8(t2.val[0]), vreinterpret_u16_u8(t3.val[0])); + const uint16x4x2_t t7 = vtrn_u16(vreinterpret_u16_u8(t2.val[1]), vreinterpret_u16_u8(t3.val[1])); + const uint32x2x2_t t8 = vtrn_u32(vreinterpret_u32_u16(t4.val[0]), vreinterpret_u32_u16(t6.val[0])); + const uint32x2x2_t t9 = vtrn_u32(vreinterpret_u32_u16(t4.val[1]), vreinterpret_u32_u16(t6.val[1])); + const uint32x2x2_t ta = vtrn_u32(vreinterpret_u32_u16(t5.val[0]), vreinterpret_u32_u16(t7.val[0])); + const uint32x2x2_t tb = vtrn_u32(vreinterpret_u32_u16(t5.val[1]), vreinterpret_u32_u16(t7.val[1])); + columns[0] = vreinterpret_u8_u32(t8.val[0]); + columns[1] = vreinterpret_u8_u32(ta.val[0]); + columns[2] = vreinterpret_u8_u32(t9.val[0]); + columns[3] = vreinterpret_u8_u32(tb.val[0]); + columns[4] = vreinterpret_u8_u32(t8.val[1]); + columns[5] = vreinterpret_u8_u32(ta.val[1]); + columns[6] = vreinterpret_u8_u32(t9.val[1]); + columns[7] = vreinterpret_u8_u32(tb.val[1]); +} + +static uint8x8_t repack_neon_pack_4bit_pairs(uint8x8_t first, uint8x8_t second, bool high) { + const uint8x8x2_t separated = vuzp_u8(first, second); + const uint8x8_t mask = vdup_n_u8(0x0F); + uint8x8_t even = separated.val[0]; + uint8x8_t odd = separated.val[1]; + + if (high) { + even = vshr_n_u8(even, 4); + odd = vshr_n_u8(odd, 4); + } + + even = vand_u8(even, mask); + odd = vand_u8(odd, mask); + return vorr_u8(vshl_n_u8(odd, 4), even); +} + +static void repack_neon_4bit_rows(const uint8_t * qs[8], uint8_t * tile_dst, int row0) { + uint8x8_t low_rows[8]; + uint8x8_t high_rows[8]; + uint8x8_t columns[8]; + + for (int rr = 0; rr < 8; ++rr) { + const uint8x16_t packed = vld1q_u8(qs[rr]); + const uint8x8_t first = vget_low_u8(packed); + const uint8x8_t second = vget_high_u8(packed); + low_rows[rr] = repack_neon_pack_4bit_pairs(first, second, false); + high_rows[rr] = repack_neon_pack_4bit_pairs(first, second, true); + } + + repack_neon_transpose8x8(low_rows, columns); + for (int cp = 0; cp < 8; ++cp) { + vst1_u8(tile_dst + cp * 32 + row0, columns[cp]); + } + + repack_neon_transpose8x8(high_rows, columns); + for (int cp = 0; cp < 8; ++cp) { + vst1_u8(tile_dst + (cp + 8) * 32 + row0, columns[cp]); + } +} + +static void repack_neon_k4_rows(const uint8_t * qs[8], uint8_t * tile_dst, int row0, bool high) { + uint8x8_t first_rows[8]; + uint8x8_t second_rows[8]; + uint8x8_t columns[8]; + + for (int rr = 0; rr < 8; ++rr) { + first_rows[rr] = repack_neon_pack_4bit_pairs(vld1_u8(qs[rr]), vld1_u8(qs[rr] + 8), high); + second_rows[rr] = repack_neon_pack_4bit_pairs(vld1_u8(qs[rr] + 16), vld1_u8(qs[rr] + 24), high); + } + + repack_neon_transpose8x8(first_rows, columns); + for (int cp = 0; cp < 8; ++cp) { + vst1_u8(tile_dst + cp * 32 + row0, columns[cp]); + } + + repack_neon_transpose8x8(second_rows, columns); + for (int cp = 0; cp < 8; ++cp) { + vst1_u8(tile_dst + (cp + 8) * 32 + row0, columns[cp]); + } +} + +static void repack_neon_q8_rows(const uint8_t * qs[8], uint8_t * tile_dst, int row0) { + uint8x8_t rows[8]; + uint8x8_t columns[8]; + + for (int cp = 0; cp < 16; cp += 4) { + for (int rr = 0; rr < 8; ++rr) { + rows[rr] = vld1_u8(qs[rr] + 2 * cp); + } + repack_neon_transpose8x8(rows, columns); + + for (int pair = 0; pair < 4; ++pair) { + const uint8x8x2_t interleaved = vzip_u8(columns[2 * pair], columns[2 * pair + 1]); + uint8_t * dst = tile_dst + (cp + pair) * 64 + 2 * row0; + vst1_u8(dst, interleaved.val[0]); + vst1_u8(dst + 8, interleaved.val[1]); + } + } +} + +static inline void repack_store_u32(uint8_t * dst, uint32_t v) { + memcpy(dst, &v, sizeof(v)); +} + +static inline uint32x4_t repack_neon_transpose_2bit_4x4(uint32x4_t w) { + uint32x4_t t = vandq_u32(veorq_u32(w, vshrq_n_u32(w, 6)), vdupq_n_u32(0x00CC00CCu)); + w = veorq_u32(w, veorq_u32(t, vshlq_n_u32(t, 6))); + t = vandq_u32(veorq_u32(w, vshrq_n_u32(w, 12)), vdupq_n_u32(0x0000F0F0u)); + return veorq_u32(w, veorq_u32(t, vshlq_n_u32(t, 12))); +} + +static inline void repack_neon_q2_0_block(const uint8_t * qs, uint8_t * tile, int row) { + const uint32x4_t w = repack_neon_transpose_2bit_4x4(vreinterpretq_u32_u8(vld1q_u8(qs))); + repack_store_u32(tile + 0 * 128 + 4 * row, vgetq_lane_u32(w, 0)); + repack_store_u32(tile + 1 * 128 + 4 * row, vgetq_lane_u32(w, 1)); + repack_store_u32(tile + 2 * 128 + 4 * row, vgetq_lane_u32(w, 2)); + repack_store_u32(tile + 3 * 128 + 4 * row, vgetq_lane_u32(w, 3)); +} + +static inline void repack_neon_q1_0_block(const uint8_t * qs, uint8_t * tile, int row) { + uint32x4_t w = vreinterpretq_u32_u8(vld1q_u8(qs)); + uint32x4_t t = vandq_u32(veorq_u32(w, vshrq_n_u32(w, 1)), vdupq_n_u32(0x22222222u)); + w = veorq_u32(w, veorq_u32(t, vshlq_n_u32(t, 1))); + t = vandq_u32(veorq_u32(w, vshrq_n_u32(w, 3)), vdupq_n_u32(0x0A0A0A0Au)); + w = veorq_u32(w, veorq_u32(t, vshlq_n_u32(t, 3))); + w = repack_neon_transpose_2bit_4x4(w); + repack_store_u32(tile + 0 * 128 + 4 * row, vgetq_lane_u32(w, 0)); + repack_store_u32(tile + 1 * 128 + 4 * row, vgetq_lane_u32(w, 1)); + repack_store_u32(tile + 2 * 128 + 4 * row, vgetq_lane_u32(w, 2)); + repack_store_u32(tile + 3 * 128 + 4 * row, vgetq_lane_u32(w, 3)); +} + +static inline void repack_neon_pack_2bit_plane(uint8x16_t v0, uint8x16_t v1, uint8_t * dst, int row) { + const uint32x4x2_t z = vuzpq_u32(vreinterpretq_u32_u8(v0), vreinterpretq_u32_u8(v1)); + const uint32x4_t p01 = vorrq_u32(z.val[0], vshlq_n_u32(z.val[1], 2)); + const uint32x2x2_t u = vuzp_u32(vget_low_u32(p01), vget_high_u32(p01)); + const uint32x2_t out = vorr_u32(u.val[0], vshl_n_u32(u.val[1], 4)); + repack_store_u32(dst + 0 * 128 + row * 4, vget_lane_u32(out, 0)); + repack_store_u32(dst + 1 * 128 + row * 4, vget_lane_u32(out, 1)); +} + +static inline void repack_neon_q2_3_k_low2(const uint8_t * qs, int kt_local, uint8_t * lo_pl, int row) { + const uint8_t * qs_sub = qs + (kt_local / 4) * 32; + const int8x16_t shift = vdupq_n_s8(-2 * (kt_local % 4)); + const uint8x16_t mask = vdupq_n_u8(0x03); + const uint8x16_t v0 = vandq_u8(vshlq_u8(vld1q_u8(qs_sub + 0), shift), mask); + const uint8x16_t v1 = vandq_u8(vshlq_u8(vld1q_u8(qs_sub + 16), shift), mask); + repack_neon_pack_2bit_plane(v0, v1, lo_pl, row); +} + +static inline void repack_neon_q3_k_hmask(const uint8_t * hmask, int kt_local, uint8_t * neg_pl, int row) { + static const uint32_t mask_words[4] = { 0x01010101u, 0x02020202u, 0x04040404u, 0x08080808u }; + const uint8x16_t m0 = vreinterpretq_u8_u32(vld1q_u32(mask_words)); + const uint8x16_t m1 = vshlq_n_u8(m0, 4); + const uint8x16_t hbit = vdupq_n_u8((uint8_t) (1u << kt_local)); + const uint8x16_t b0 = vbicq_u8(m0, vtstq_u8(vld1q_u8(hmask + 0), hbit)); + const uint8x16_t b1 = vbicq_u8(m1, vtstq_u8(vld1q_u8(hmask + 16), hbit)); + const uint32x4_t b01 = vreinterpretq_u32_u8(vorrq_u8(b0, b1)); + const uint32x2_t f0 = vorr_u32(vget_low_u32(b01), vget_high_u32(b01)); + const uint32x2_t f1 = vpadd_u32(f0, f0); + repack_store_u32(neg_pl + row * 4, vget_lane_u32(f1, 0)); +} + +static inline void repack_neon_q6_k(const block_q6_K * b, int kt_local, uint8_t * lo_pl, uint8_t * hi_pl, int row) { + const int c = kt_local / 4; + const int g_sb = kt_local % 4; + const uint8_t * ql = b->ql + c * 64 + (g_sb & 1) * 32; + const uint8_t * qh = b->qh + c * 32; + const int8x16_t lshift = vdupq_n_s8((g_sb >= 2) ? -4 : 0); + const int8x16_t hshift = vdupq_n_s8(-2 * g_sb); + const uint8x16_t mask4 = vdupq_n_u8(0x0F); + const uint8x16_t mask2 = vdupq_n_u8(0x03); + + const uint8x16_t lo0 = vandq_u8(vshlq_u8(vld1q_u8(ql + 0), lshift), mask4); + const uint8x16_t lo1 = vandq_u8(vshlq_u8(vld1q_u8(ql + 16), lshift), mask4); + const uint32x4x2_t lz = vuzpq_u32(vreinterpretq_u32_u8(lo0), vreinterpretq_u32_u8(lo1)); + const uint32x4_t lout = vorrq_u32(lz.val[0], vshlq_n_u32(lz.val[1], 4)); + repack_store_u32(lo_pl + 0 * 128 + row * 4, vgetq_lane_u32(lout, 0)); + repack_store_u32(lo_pl + 1 * 128 + row * 4, vgetq_lane_u32(lout, 1)); + repack_store_u32(lo_pl + 2 * 128 + row * 4, vgetq_lane_u32(lout, 2)); + repack_store_u32(lo_pl + 3 * 128 + row * 4, vgetq_lane_u32(lout, 3)); + + const uint8x16_t hi0 = vandq_u8(vshlq_u8(vld1q_u8(qh + 0), hshift), mask2); + const uint8x16_t hi1 = vandq_u8(vshlq_u8(vld1q_u8(qh + 16), hshift), mask2); + repack_neon_pack_2bit_plane(hi0, hi1, hi_pl, row); +} + +static inline void repack_neon_q5_k_qh(const uint8_t * qh, uint8_t hbit, uint8_t * plane, int row) { + static const uint8_t mask_bytes[16] = { 1, 2, 1, 2, 1, 2, 1, 2, 4, 8, 4, 8, 4, 8, 4, 8 }; + const uint8x16_t m0 = vld1q_u8(mask_bytes); + const uint8x16_t m1 = vshlq_n_u8(m0, 4); + const uint8x16_t vbit = vdupq_n_u8(hbit); + const uint8x16_t b0 = vandq_u8(vtstq_u8(vld1q_u8(qh + 0), vbit), m0); + const uint8x16_t b1 = vandq_u8(vtstq_u8(vld1q_u8(qh + 16), vbit), m1); + const uint8x16_t b01 = vorrq_u8(b0, b1); + const uint8x8_t fold = vorr_u8(vget_low_u8(b01), vget_high_u8(b01)); + const uint8x8_t out = vpadd_u8(fold, fold); + plane[0 * 32 + row] = vget_lane_u8(out, 0); + plane[1 * 32 + row] = vget_lane_u8(out, 1); + plane[2 * 32 + row] = vget_lane_u8(out, 2); + plane[3 * 32 + row] = vget_lane_u8(out, 3); +} + +static inline uint16x8_t repack_neon_load_f16x8(const uint16_t * src) { + return vld1q_u16(src); +} + +#if defined(__aarch64__) || defined(__ARM_FP16_FORMAT_IEEE) +static inline uint16x8_t repack_neon_load_f16x8(const float * src) { + const float16x4_t lo = vcvt_f16_f32(vld1q_f32(src)); + const float16x4_t hi = vcvt_f16_f32(vld1q_f32(src + 4)); + return vreinterpretq_u16_f16(vcombine_f16(lo, hi)); +} + +static inline uint16x8_t repack_neon_load_f16x8(const ggml_bf16_t * src) { + const uint16x8_t bf = vld1q_u16((const uint16_t *) src); + const float32x4_t f_lo = vreinterpretq_f32_u32(vshll_n_u16(vget_low_u16(bf), 16)); + const float32x4_t f_hi = vreinterpretq_f32_u32(vshll_n_u16(vget_high_u16(bf), 16)); + const float16x4_t lo = vcvt_f16_f32(f_lo); + const float16x4_t hi = vcvt_f16_f32(f_hi); + return vreinterpretq_u16_f16(vcombine_f16(lo, hi)); +} +#else +static inline uint16x8_t repack_neon_load_f16x8(const float * src) { + uint16_t tmp[8]; + for (int i = 0; i < 8; ++i) { + tmp[i] = GGML_FP32_TO_FP16(src[i]); + } + return vld1q_u16(tmp); +} + +static inline uint16x8_t repack_neon_load_f16x8(const ggml_bf16_t * src) { + uint16_t tmp[8]; + for (int i = 0; i < 8; ++i) { + tmp[i] = GGML_FP32_TO_FP16(GGML_BF16_TO_FP32(src[i])); + } + return vld1q_u16(tmp); +} +#endif + +template +static void repack_neon_f16_tile(uint16_t * tile_dst, const SrcT * src_slice, int64_t row_stride, int ct, int kt) { + for (int row0 = 0; row0 < 32; row0 += 4) { + const SrcT * r0 = src_slice + (int64_t) (ct * 32 + row0 + 0) * row_stride + kt * 32; + const SrcT * r1 = src_slice + (int64_t) (ct * 32 + row0 + 1) * row_stride + kt * 32; + const SrcT * r2 = src_slice + (int64_t) (ct * 32 + row0 + 2) * row_stride + kt * 32; + const SrcT * r3 = src_slice + (int64_t) (ct * 32 + row0 + 3) * row_stride + kt * 32; + for (int cp = 0; cp < 16; cp += 4) { + const uint32x4_t v0 = vreinterpretq_u32_u16(repack_neon_load_f16x8(r0 + 2 * cp)); + const uint32x4_t v1 = vreinterpretq_u32_u16(repack_neon_load_f16x8(r1 + 2 * cp)); + const uint32x4_t v2 = vreinterpretq_u32_u16(repack_neon_load_f16x8(r2 + 2 * cp)); + const uint32x4_t v3 = vreinterpretq_u32_u16(repack_neon_load_f16x8(r3 + 2 * cp)); + + const uint32x2x2_t t0 = vtrn_u32(vget_low_u32(v0), vget_low_u32(v1)); + const uint32x2x2_t t1 = vtrn_u32(vget_high_u32(v0), vget_high_u32(v1)); + const uint32x2x2_t t2 = vtrn_u32(vget_low_u32(v2), vget_low_u32(v3)); + const uint32x2x2_t t3 = vtrn_u32(vget_high_u32(v2), vget_high_u32(v3)); + + vst1q_u16(tile_dst + (cp + 0) * 64 + row0 * 2, vreinterpretq_u16_u32(vcombine_u32(t0.val[0], t2.val[0]))); + vst1q_u16(tile_dst + (cp + 1) * 64 + row0 * 2, vreinterpretq_u16_u32(vcombine_u32(t0.val[1], t2.val[1]))); + vst1q_u16(tile_dst + (cp + 2) * 64 + row0 * 2, vreinterpretq_u16_u32(vcombine_u32(t1.val[0], t3.val[0]))); + vst1q_u16(tile_dst + (cp + 3) * 64 + row0 * 2, vreinterpretq_u16_u32(vcombine_u32(t1.val[1], t3.val[1]))); + } + } +} +#endif + +// --- Generic 32x32 tile grid walkers for block-32 and float types --- + +template +static void repack_parallel_for_ct(size_t slice_bytes, int n_col_tiles, Fn && fn) { + int n_threads = 1; + if (slice_bytes > 128 * 1024) { + for (int nt : { 4, 3, 2 }) { + if (n_col_tiles % nt == 0) { + n_threads = nt; + break; + } + } + } + + if (n_threads <= 1) { + fn(0, n_col_tiles); + return; + } + + const int chunk = n_col_tiles / n_threads; + std::thread workers[3]; + for (int i = 0; i < n_threads - 1; ++i) { + workers[i] = std::thread([&fn, i, chunk]() { + fn(i * chunk, (i + 1) * chunk); + }); + } + fn((n_threads - 1) * chunk, n_col_tiles); + for (int i = 0; i < n_threads - 1; ++i) { + workers[i].join(); + } +} + +template +static void repack_to_tiled_grid_32(ggml_tensor * t, const void * data, size_t offset, size_t size, + size_t tile_size, PackTileFn && pack_tile) { + const SrcElemT * src_matrix = (const SrcElemT *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = hex_round_up(ne0, 32) / 32; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + + const size_t slice_size = (size_t) ne1 * ggml_row_size(t->type, ne0); + const int64_t start_slice = offset / slice_size; + int64_t end_slice = (offset + size + slice_size - 1) / slice_size; + if (end_slice > ne2 * ne3) { + end_slice = ne2 * ne3; + } + + const int64_t row_stride = (ne0 / (32 / ELEMS_PER_KTILE)); + + for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { + const SrcElemT * src_slice = src_matrix + (slice_idx - start_slice) * (ne1 * row_stride); + uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; + + repack_parallel_for_ct(matrix_size, n_col_tiles, [&](int ct0, int ct1) { + for (int ct = ct0; ct < ct1; ct++) { + for (int kt = 0; kt < n_k_tiles; kt++) { + uint8_t * tile_dst = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; + pack_tile(tile_dst, src_slice, ne0, ne1, row_stride, ct, kt); + } + } + }); + } +} + +template +static void unpack_from_tiled_grid_32(void * data, const ggml_tensor * t, size_t offset, size_t size, + size_t tile_size, UnpackTileFn && unpack_tile) { + uint8_t * dst_bytes = (uint8_t *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = hex_round_up(ne0, 32) / 32; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + + const size_t row_size_bytes = ggml_row_size(t->type, ne0); + const size_t slice_size = (size_t) ne1 * row_size_bytes; + const int64_t start_slice = offset / slice_size; + int64_t end_slice = (offset + size + slice_size - 1) / slice_size; + if (end_slice > ne2 * ne3) { + end_slice = ne2 * ne3; + } + + const int64_t row_stride = (ne0 / (32 / ELEMS_PER_KTILE)); + + for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { + const size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); + const size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); + const size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; + const size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; + + const int64_t start_row = slice_offset_start / row_size_bytes; + const int64_t end_row = (std::min)((int64_t) ((slice_offset_end + row_size_bytes - 1) / row_size_bytes), ne1); + + const int start_ct = (int) (start_row / 32); + const int end_ct = (std::min)((int) ((end_row + 31) / 32), n_col_tiles); + + DstElemT * dst_slice = (DstElemT *) (dst_bytes + (cur_start_byte - offset)); + const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; + + for (int ct = start_ct; ct < end_ct; ct++) { + for (int kt = 0; kt < n_k_tiles; kt++) { + const uint8_t * tile_src = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; + unpack_tile(dst_slice, tile_src, ne0, start_row, end_row, row_stride, ct, kt); + } + } + } +} + +// --- Block-32 Quantized Types (Q4_0, IQ4_NL, Q4_1, Q8_0, MXFP4) --- + +static void repack_q4_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_to_tiled_grid_32(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q4_0, + [](uint8_t * tile_dst, const block_q4_0 * src_slice, int64_t ne0, int64_t ne1, int64_t row_stride, int ct, int kt) { + ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); +#if defined(__ARM_NEON) || defined(__aarch64__) + if (ct * 32 + 32 <= ne1 && kt < ne0 / 32) { + for (int row0 = 0; row0 < 32; row0 += 8) { + const uint8_t * qs[8]; + for (int rr = 0; rr < 8; ++rr) { + qs[rr] = src_slice[(ct * 32 + row0 + rr) * row_stride + kt].qs; + } + repack_neon_4bit_rows(qs, tile_dst, row0); + } + + for (int row = 0; row < 32; ++row) { + scale_dst[row] = src_slice[(ct * 32 + row) * row_stride + kt].d; + } + return; + } +#endif + uint8_t tile_quants[32][32]; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r < ne1 && kt < ne0 / 32) { + const block_q4_0 & b = src_slice[r * row_stride + kt]; + unpack_nibbles_32(tile_quants[row], b.qs); + scale_dst[row] = b.d; + } else { + memset(tile_quants[row], 8, 32); + scale_dst[row] = 0; + } + } + transpose_nibbles_to_tile(tile_dst, tile_quants); + }); +} + +static void repack_tiled_q4_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_from_tiled_grid_32(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q4_0, + [](block_q4_0 * dst_slice, const uint8_t * tile_src, int64_t ne0, int64_t start_row, int64_t end_row, int64_t row_stride, int ct, int kt) { + uint8_t tile_quants[32][32]; + transpose_tile_to_nibbles(tile_quants, tile_src); + const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row && kt < ne0 / 32) { + block_q4_0 & b = dst_slice[(r - start_row) * row_stride + kt]; + pack_nibbles_32(b.qs, tile_quants[row]); + b.d = scale_src[row]; + } + } + }); +} + +static void repack_q4_1_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_to_tiled_grid_32(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q4_1, + [](uint8_t * tile_dst, const block_q4_1 * src_slice, int64_t ne0, int64_t ne1, int64_t row_stride, int ct, int kt) { + ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); +#if defined(__ARM_NEON) || defined(__aarch64__) + if (ct * 32 + 32 <= ne1 && kt < ne0 / 32) { + for (int row0 = 0; row0 < 32; row0 += 8) { + const uint8_t * qs[8]; + for (int rr = 0; rr < 8; ++rr) { + qs[rr] = src_slice[(ct * 32 + row0 + rr) * row_stride + kt].qs; + } + repack_neon_4bit_rows(qs, tile_dst, row0); + } + + for (int row = 0; row < 32; ++row) { + const block_q4_1 & src_block = src_slice[(ct * 32 + row) * row_stride + kt]; + scale_dst[2 * row + 0] = src_block.d; + scale_dst[2 * row + 1] = src_block.m; + } + return; + } +#endif + uint8_t tile_quants[32][32]; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r < ne1 && kt < ne0 / 32) { + const block_q4_1 & b = src_slice[r * row_stride + kt]; + unpack_nibbles_32(tile_quants[row], b.qs); + scale_dst[2 * row + 0] = b.d; + scale_dst[2 * row + 1] = b.m; + } else { + memset(tile_quants[row], 0, 32); + scale_dst[2 * row + 0] = 0; + scale_dst[2 * row + 1] = 0; + } + } + transpose_nibbles_to_tile(tile_dst, tile_quants); + }); +} + +static void repack_tiled_q4_1(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_from_tiled_grid_32(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q4_1, + [](block_q4_1 * dst_slice, const uint8_t * tile_src, int64_t ne0, int64_t start_row, int64_t end_row, int64_t row_stride, int ct, int kt) { + uint8_t tile_quants[32][32]; + transpose_tile_to_nibbles(tile_quants, tile_src); + const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row && kt < ne0 / 32) { + block_q4_1 & b = dst_slice[(r - start_row) * row_stride + kt]; + pack_nibbles_32(b.qs, tile_quants[row]); + b.d = scale_src[2 * row + 0]; + b.m = scale_src[2 * row + 1]; + } + } + }); +} + +static void repack_mxfp4_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_to_tiled_grid_32(t, data, offset, size, HTP_TENSOR_TILE_SIZE_MXFP4, + [](uint8_t * tile_dst, const block_mxfp4 * src_slice, int64_t ne0, int64_t ne1, int64_t row_stride, int ct, int kt) { + uint8_t * scale_dst = tile_dst + 512; +#if defined(__ARM_NEON) || defined(__aarch64__) + if (ct * 32 + 32 <= ne1 && kt < ne0 / 32) { + for (int row0 = 0; row0 < 32; row0 += 8) { + const uint8_t * qs[8]; + for (int rr = 0; rr < 8; ++rr) { + qs[rr] = src_slice[(ct * 32 + row0 + rr) * row_stride + kt].qs; + } + repack_neon_4bit_rows(qs, tile_dst, row0); + } + + for (int row = 0; row < 32; ++row) { + scale_dst[row] = src_slice[(ct * 32 + row) * row_stride + kt].e; + } + return; + } +#endif + uint8_t tile_quants[32][32]; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r < ne1 && kt < ne0 / 32) { + const block_mxfp4 & b = src_slice[r * row_stride + kt]; + unpack_nibbles_32(tile_quants[row], b.qs); + scale_dst[row] = b.e; + } else { + memset(tile_quants[row], 0, 32); + scale_dst[row] = 0; + } + } + transpose_nibbles_to_tile(tile_dst, tile_quants); + }); +} + +static void repack_tiled_mxfp4(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_from_tiled_grid_32(data, t, offset, size, HTP_TENSOR_TILE_SIZE_MXFP4, + [](block_mxfp4 * dst_slice, const uint8_t * tile_src, int64_t ne0, int64_t start_row, int64_t end_row, int64_t row_stride, int ct, int kt) { + uint8_t tile_quants[32][32]; + transpose_tile_to_nibbles(tile_quants, tile_src); + const uint8_t * scale_src = tile_src + 512; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row && kt < ne0 / 32) { + block_mxfp4 & b = dst_slice[(r - start_row) * row_stride + kt]; + pack_nibbles_32(b.qs, tile_quants[row]); + b.e = scale_src[row]; + } + } + }); +} + +static void repack_q8_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_to_tiled_grid_32(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q8_0, + [](uint8_t * tile_dst, const block_q8_0 * src_slice, int64_t ne0, int64_t ne1, int64_t row_stride, int ct, int kt) { + ggml_half * scale_dst = (ggml_half *) (tile_dst + 1024); +#if defined(__ARM_NEON) || defined(__aarch64__) + if (ct * 32 + 32 <= ne1 && kt < ne0 / 32) { + for (int row0 = 0; row0 < 32; row0 += 8) { + const uint8_t * qs[8]; + for (int rr = 0; rr < 8; ++rr) { + qs[rr] = (const uint8_t *) src_slice[(ct * 32 + row0 + rr) * row_stride + kt].qs; + } + repack_neon_q8_rows(qs, tile_dst, row0); + } + + for (int row = 0; row < 32; ++row) { + scale_dst[row] = src_slice[(ct * 32 + row) * row_stride + kt].d; + } + return; + } +#endif + for (int cp = 0; cp < 16; cp++) { + const int col0 = cp * 2; + const int col1 = col0 + 1; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + const block_q8_0 * b = (r < ne1 && kt < ne0 / 32) ? &src_slice[r * row_stride + kt] : nullptr; + tile_dst[cp * 64 + 2 * row + 0] = b ? b->qs[col0] : 0; + tile_dst[cp * 64 + 2 * row + 1] = b ? b->qs[col1] : 0; + } + } + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + scale_dst[row] = (r < ne1 && kt < ne0 / 32) ? src_slice[r * row_stride + kt].d : 0; + } + }); +} + +static void repack_tiled_q8_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_from_tiled_grid_32(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q8_0, + [](block_q8_0 * dst_slice, const uint8_t * tile_src, int64_t ne0, int64_t start_row, int64_t end_row, int64_t row_stride, int ct, int kt) { + for (int cp = 0; cp < 16; cp++) { + const int col0 = cp * 2; + const int col1 = col0 + 1; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row && kt < ne0 / 32) { + block_q8_0 & b = dst_slice[(r - start_row) * row_stride + kt]; + b.qs[col0] = tile_src[cp * 64 + 2 * row + 0]; + b.qs[col1] = tile_src[cp * 64 + 2 * row + 1]; + } + } + } + const ggml_half * scale_src = (const ggml_half *) (tile_src + 1024); + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row && kt < ne0 / 32) { + dst_slice[(r - start_row) * row_stride + kt].d = scale_src[row]; + } + } + }); +} + +// --- Float Types (F16, F32, BF16 -> f16_tiled HMX layout) --- + +static void repack_q2_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + GGML_ASSERT(offset == 0); + GGML_ASSERT(t->ne[0] % 64 == 0); + GGML_ASSERT(size == ggml_nbytes(t)); + + const block_q2_0 * src = (const block_q2_0 *) data; + const int64_t blocks_per_row = t->ne[0] / 64; + const int64_t n_col_tiles = hex_round_up(t->ne[1], 32) / 32; + const int64_t n_weight_tiles = blocks_per_row; + const size_t matrix_size = (size_t) n_col_tiles * n_weight_tiles * HTP_TENSOR_TILE_SIZE_Q2_0; + + for (int64_t slice = 0; slice < t->ne[2] * t->ne[3]; ++slice) { + const block_q2_0 * src_slice = src + slice * t->ne[1] * blocks_per_row; + uint8_t * dst_slice = (uint8_t *) t->data + slice * matrix_size; + const size_t ct_bytes = (size_t) n_weight_tiles * HTP_TENSOR_TILE_SIZE_Q2_0; + + repack_parallel_for_ct(matrix_size, (int) n_col_tiles, [&](int ct0, int ct1) { + memset(dst_slice + (size_t) ct0 * ct_bytes, 0, (size_t) (ct1 - ct0) * ct_bytes); + const int64_t r0 = (int64_t) ct0 * 32; + const int64_t r1 = (std::min)((int64_t) ct1 * 32, t->ne[1]); + for (int64_t row_index = r0; row_index < r1; ++row_index) { + const int64_t ct = row_index / 32; + const int row = (int) (row_index % 32); + for (int64_t kt = 0; kt < n_weight_tiles; ++kt) { + const block_q2_0 * block = src_slice + row_index * blocks_per_row + kt; + uint8_t * tile = dst_slice + (ct * n_weight_tiles + kt) * HTP_TENSOR_TILE_SIZE_Q2_0; +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q2_0_block(block->qs, tile, row); +#else + for (int group = 0; group < 16; ++group) { + for (int byte = 0; byte < 4; ++byte) { + const int k = 4 * group + byte; + const uint8_t code = (block->qs[k / 4] >> (2 * (k % 4))) & 3; + tile[(group >> 2) * 128 + 4 * row + byte] |= code << (2 * (group & 3)); + } + } +#endif + memcpy(tile + 512 + 2 * row, &block->d, sizeof(block->d)); + } + } + }); + } +} + +static void repack_tiled_q2_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { + GGML_ASSERT(t->ne[0] % 64 == 0); + GGML_ASSERT(offset + size <= ggml_nbytes(t)); + + const size_t first_block = offset / sizeof(block_q2_0); + const size_t end_block = (offset + size + sizeof(block_q2_0) - 1) / sizeof(block_q2_0); + const size_t blocks_per_row = t->ne[0] / 64; + const size_t blocks_per_slice = t->ne[1] * blocks_per_row; + const size_t n_weight_tiles = blocks_per_row; + const size_t n_col_tiles = hex_round_up(t->ne[1], 32) / 32; + const size_t matrix_size = n_col_tiles * n_weight_tiles * HTP_TENSOR_TILE_SIZE_Q2_0; + + for (size_t block_index = first_block; block_index < end_block; ++block_index) { + const size_t slice = block_index / blocks_per_slice; + const size_t in_slice = block_index % blocks_per_slice; + const size_t row_index = in_slice / blocks_per_row; + const size_t kt = in_slice % blocks_per_row; + const size_t ct = row_index / 32; + const size_t row = row_index % 32; + const uint8_t * tile = (const uint8_t *) t->data + slice * matrix_size + + (ct * n_weight_tiles + kt) * HTP_TENSOR_TILE_SIZE_Q2_0; + + block_q2_0 block = {}; + memcpy(&block.d, tile + 512 + 2 * row, sizeof(block.d)); + for (int group = 0; group < 16; ++group) { + for (int byte = 0; byte < 4; ++byte) { + const uint8_t packed = tile[(group >> 2) * 128 + 4 * row + byte]; + const uint8_t code = (packed >> (2 * (group & 3))) & 3; + block.qs[group] |= code << (2 * byte); + } + } + + const size_t block_begin = block_index * sizeof(block_q2_0); + const size_t copy_begin = (std::max)(block_begin, offset); + const size_t copy_end = (std::min)(block_begin + sizeof(block_q2_0), offset + size); + memcpy((uint8_t *) data + copy_begin - offset, (const uint8_t *) &block + copy_begin - block_begin, copy_end - copy_begin); + } +} + +template +static void repack_float_to_f16_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size, ToFp16Fn && to_fp16) { + repack_to_tiled_grid_32(t, data, offset, size, HTP_TENSOR_TILE_SIZE_F16, + [&](uint8_t * tile_bytes, const SrcT * src_slice, int64_t ne0, int64_t ne1, int64_t row_stride, int ct, int kt) { + uint16_t * tile_dst = (uint16_t *) tile_bytes; +#if defined(__ARM_NEON) || defined(__aarch64__) + if (ct * 32 + 32 <= ne1 && kt * 32 + 32 <= ne0) { + repack_neon_f16_tile(tile_dst, src_slice, row_stride, ct, kt); + return; + } +#endif + for (int cp = 0; cp < 16; cp++) { + const int64_t c0 = kt * 32 + cp * 2; + const int64_t c1 = c0 + 1; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + const SrcT * r_ptr = (r < ne1) ? &src_slice[r * row_stride] : nullptr; + tile_dst[cp * 64 + row * 2 + 0] = (r_ptr && c0 < ne0) ? to_fp16(r_ptr[c0]) : 0; + tile_dst[cp * 64 + row * 2 + 1] = (r_ptr && c1 < ne0) ? to_fp16(r_ptr[c1]) : 0; + } + } + }); +} + +template +static void unpack_f16_tiled_to_float(void * data, const ggml_tensor * t, size_t offset, size_t size, FromFp16Fn && from_fp16) { + unpack_from_tiled_grid_32(data, t, offset, size, HTP_TENSOR_TILE_SIZE_F16, + [&](DstT * dst_slice, const uint8_t * tile_bytes, int64_t ne0, int64_t start_row, int64_t end_row, int64_t row_stride, int ct, int kt) { + const uint16_t * tile_src = (const uint16_t *) tile_bytes; + for (int cp = 0; cp < 16; cp++) { + const int64_t c0 = kt * 32 + cp * 2; + const int64_t c1 = c0 + 1; + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= start_row && r < end_row) { + DstT * r_ptr = dst_slice + (r - start_row) * row_stride; + if (c0 < ne0) r_ptr[c0] = from_fp16(tile_src[cp * 64 + row * 2 + 0]); + if (c1 < ne0) r_ptr[c1] = from_fp16(tile_src[cp * 64 + row * 2 + 1]); + } + } + } + }); +} + +// --- Generic K-Quant (super-block 256) grid walkers --- + +template +static void repack_kquant_to_tiled_grid(ggml_tensor * t, const void * data, size_t offset, size_t size, + size_t tile_size, PackKtFn && pack_kt) { + GGML_ASSERT(offset == 0); + GGML_UNUSED(size); + + const BlockT * src_matrix = (const BlockT *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + GGML_ASSERT(ne0 % QK_K == 0); + + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = hex_round_up(ne0, 32) / 32; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + const int64_t sb_per_row = ne0 / QK_K; + + for (int64_t slice_idx = 0; slice_idx < ne2 * ne3; slice_idx++) { + const BlockT * src_slice = src_matrix + slice_idx * (ne1 * sb_per_row); + uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; + const size_t ct_bytes = (size_t) n_k_tiles * tile_size; + + repack_parallel_for_ct(matrix_size, n_col_tiles, [&](int ct0, int ct1) { + // Padding rows and OR-ed bit planes require zeroed tiles + memset(matrix_dst + (size_t) ct0 * ct_bytes, 0, (size_t) (ct1 - ct0) * ct_bytes); + + const int64_t r0 = (int64_t) ct0 * 32; + const int64_t r1 = (std::min)((int64_t) ct1 * 32, ne1); + for (int64_t r = r0; r < r1; r++) { + const int ct = (int) (r / 32); + const int row = (int) (r % 32); + const BlockT * src_row = src_slice + r * sb_per_row; + + for (int kt = 0; kt < n_k_tiles; kt++) { + uint8_t * tile = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; + pack_kt(tile, &src_row[kt / 8], row, kt % 8); + } + } + }); + } +} + +template +static void unpack_kquant_from_tiled_grid(void * data, const ggml_tensor * t, size_t offset, size_t size, + size_t tile_size, UnpackSbFn && unpack_sb) { + uint8_t * dst_bytes = (uint8_t *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + GGML_ASSERT(ne0 % QK_K == 0); + + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = hex_round_up(ne0, 32) / 32; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + const int64_t sb_per_row = ne0 / QK_K; + + const size_t row_size_bytes = ggml_row_size(t->type, ne0); + const size_t slice_size = (size_t) ne1 * row_size_bytes; + const int64_t start_slice = offset / slice_size; + int64_t end_slice = (offset + size + slice_size - 1) / slice_size; + if (end_slice > ne2 * ne3) { + end_slice = ne2 * ne3; + } + + for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { + const size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); + const size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); + const size_t slice_offset_start = cur_start_byte - (size_t) slice_idx * slice_size; + const size_t slice_offset_end = cur_end_byte - (size_t) slice_idx * slice_size; + + const int64_t start_row = slice_offset_start / row_size_bytes; + const int64_t end_row = (std::min)((int64_t) ((slice_offset_end + row_size_bytes - 1) / row_size_bytes), ne1); + + BlockT * dst_slice = (BlockT *) (dst_bytes + (cur_start_byte - offset)); + const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; + + for (int64_t r = start_row; r < end_row; r++) { + const int ct = (int) (r / 32); + const int row = (int) (r % 32); + BlockT * dst_row = dst_slice + (r - start_row) * sb_per_row; + + for (int64_t sb = 0; sb < sb_per_row; sb++) { + BlockT * b = &dst_row[sb]; + memset(b, 0, sizeof(BlockT)); + const uint8_t * sb_tiles = matrix_src + ((size_t) ct * n_k_tiles + sb * 8) * tile_size; + unpack_sb(b, sb_tiles, tile_size, row); + } + } + } +} + +// --- K-Quant Helpers & Per-Type Implementations (Q2_K, Q3_K, Q4_K, Q5_K, Q6_K) --- + +#if !defined(__ARM_NEON) && !defined(__aarch64__) +// unsigned 6-bit value (0..63) of element e of a Q6_K block, same bit layout as dequantize_row_q6_K +static inline uint8_t q6_K_get_quant(const block_q6_K * b, int e) { + const int c = e / 128; + const int w = e % 128; + const int g = w / 32; + const int l = w % 32; + const uint8_t * ql = b->ql + c * 64; + const uint8_t * qh = b->qh + c * 32; + uint8_t lo, hi; + switch (g) { + case 0: lo = ql[l] & 0xF; hi = (qh[l] >> 0) & 3; break; + case 1: lo = ql[l + 32] & 0xF; hi = (qh[l] >> 2) & 3; break; + case 2: lo = ql[l] >> 4; hi = (qh[l] >> 4) & 3; break; + default: lo = ql[l + 32] >> 4; hi = (qh[l] >> 6) & 3; break; + } + return (uint8_t) (lo | (hi << 4)); +} +#endif + +static void repack_q6_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_kquant_to_tiled_grid(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q6_K, + [](uint8_t * tile, const block_q6_K * b, int row, int kt_local) { + const float d = GGML_FP16_TO_FP32(b->d); + uint8_t * lo_pl = tile; + uint8_t * hi_pl = tile + 512; + ggml_half * sc_pl = (ggml_half *) (tile + 768); + +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q6_k(b, kt_local, lo_pl, hi_pl, row); +#else + for (int lk = 0; lk < 32; lk++) { + const uint8_t q6 = q6_K_get_quant(b, kt_local * 32 + lk); + const int g = lk >> 2; + const int pos = row * 4 + (lk & 3); + lo_pl[(g >> 1) * 128 + pos] |= (uint8_t) ((q6 & 0xF) << ((g & 1) * 4)); + hi_pl[(g >> 2) * 128 + pos] |= (uint8_t) ((q6 >> 4) << ((g & 3) * 2)); + } +#endif + for (int sub = 0; sub < 2; sub++) { + sc_pl[sub * 32 + row] = GGML_FP32_TO_FP16(d * (float) b->scales[kt_local * 2 + sub]); + } + }); +} + +static void repack_tiled_q6_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_kquant_from_tiled_grid(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q6_K, + [](block_q6_K * b, const uint8_t * sb_tiles, size_t tile_size, int row) { + float sub_scales[16]; + for (int kt_local = 0; kt_local < 8; kt_local++) { + const uint8_t * tile = sb_tiles + kt_local * tile_size; + const uint8_t * lo_pl = tile; + const uint8_t * hi_pl = tile + 512; + const ggml_half * sc_pl = (const ggml_half *) (tile + 768); + + const int c = kt_local / 4; + const int g = kt_local % 4; + uint8_t * ql = b->ql + c * 64; + uint8_t * qh = b->qh + c * 32; + + for (int lk = 0; lk < 32; lk++) { + const int g_tile = lk >> 2; + const int pos = row * 4 + (lk & 3); + const uint8_t lo = (lo_pl[(g_tile >> 1) * 128 + pos] >> ((g_tile & 1) * 4)) & 0xF; + const uint8_t hi = (hi_pl[(g_tile >> 2) * 128 + pos] >> ((g_tile & 3) * 2)) & 3; + + switch (g) { + case 0: ql[lk] |= lo; qh[lk] |= (hi << 0); break; + case 1: ql[lk + 32] |= lo; qh[lk] |= (hi << 2); break; + case 2: ql[lk] |= (lo << 4); qh[lk] |= (hi << 4); break; + default: ql[lk + 32] |= (lo << 4); qh[lk] |= (hi << 6); break; + } + } + + for (int sub = 0; sub < 2; sub++) { + sub_scales[kt_local * 2 + sub] = GGML_FP16_TO_FP32(sc_pl[sub * 32 + row]); + } + } + + float max_abs_scale = 0.0f; + for (int s = 0; s < 16; s++) { + max_abs_scale = (std::max)(max_abs_scale, fabsf(sub_scales[s])); + } + + if (max_abs_scale == 0.0f) { + b->d = GGML_FP32_TO_FP16(0.0f); + } else { + b->d = GGML_FP32_TO_FP16(max_abs_scale / 127.0f); + const float d_actual = GGML_FP16_TO_FP32(b->d); + const float inv_d = (d_actual != 0.0f) ? (1.0f / d_actual) : 0.0f; + for (int s = 0; s < 16; s++) { + const int sc = (int) roundf(sub_scales[s] * inv_d); + b->scales[s] = (int8_t) (std::max)(-128, (std::min)(127, sc)); + } + } + }); +} + +#if !defined(__ARM_NEON) && !defined(__aarch64__) +// low 2 bits (0..3) of element e of a Q2_K or Q3_K block, same bit layout as dequantize_row_q2_K / q3_K +static inline uint8_t q2_3_K_get_low2(const uint8_t * qs, int e) { + const int c = e / 128; + const int j = (e % 128) / 32; + const int l = e % 32; + return (qs[c * 32 + l] >> (2 * j)) & 3; +} + +// hmask bit of element e of a Q3_K block, same bit layout as dequantize_row_q3_K +static inline bool q3_K_get_hbit(const block_q3_K * b, int e) { + const int c = e / 128; + const int j = (e % 128) / 32; + const int l = e % 32; + return (b->hmask[l] >> (c * 4 + j)) & 1; +} +#endif + +// signed 6-bit scale j (-32..31) of a Q3_K block, same packing as quantize_row_q3_K_ref +static inline int q3_K_get_scale(const uint8_t * scales, int j) { + const int lo = (j < 8) ? (scales[j] & 0xF) : (scales[j - 8] >> 4); + const int hi = (scales[8 + j % 4] >> (2 * (j / 4))) & 3; + return (lo | (hi << 4)) - 32; +} + +// read-back: find fp16 d and l[j] in [lmin, lmax] with fp16(d * l[j]) == prod[j] for all j, false if none +static bool hexagon_recover_k_scales(const ggml_half * prod, int n, int lmin, int lmax, ggml_half * d_out, int * l_out) { + int jmax = 0; + for (int j = 1; j < n; j++) { + if (fabsf(GGML_FP16_TO_FP32(prod[j])) > fabsf(GGML_FP16_TO_FP32(prod[jmax]))) { + jmax = j; + } + } + const float pmax = GGML_FP16_TO_FP32(prod[jmax]); + if (pmax == 0.0f) { + *d_out = GGML_FP32_TO_FP16(0.0f); + for (int j = 0; j < n; j++) { + l_out[j] = 0; + } + return true; + } + + // the quantizers put the largest scale at or near the range end, so try large |l| first + const int lext = (std::max)(-lmin, lmax); + for (int a = lext; a >= 1; a--) { + for (int sign : { 1, -1 }) { + const int lj = sign * a; + if (lj < lmin || lj > lmax) { + continue; + } + const ggml_half d0 = GGML_FP32_TO_FP16(pmax / (float) lj); + for (int ulp : { 0, -1, 1 }) { + ggml_half d = d0; + uint16_t bits; + memcpy(&bits, &d, sizeof(bits)); + bits = (uint16_t) (bits + ulp); + memcpy(&d, &bits, sizeof(bits)); + + const float df = GGML_FP16_TO_FP32(d); + if (!std::isfinite(df) || df == 0.0f) { + continue; + } + bool ok = true; + for (int j = 0; j < n && ok; j++) { + const int l = (int) roundf(GGML_FP16_TO_FP32(prod[j]) / df); + const ggml_half p = GGML_FP32_TO_FP16(df * (float) l); + ok = l >= lmin && l <= lmax && memcmp(&p, &prod[j], sizeof(p)) == 0; + l_out[j] = l; + } + if (ok) { + *d_out = d; + return true; + } + } + } + } + return false; +} + +static void repack_q3_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_kquant_to_tiled_grid(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q3_K, + [](uint8_t * tile, const block_q3_K * b, int row, int kt_local) { + const float d = GGML_FP16_TO_FP32(b->d); + uint8_t * lo_pl = tile; + uint8_t * neg_pl = tile + 256; + ggml_half * sc_pl = (ggml_half *) (tile + 384); + +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q2_3_k_low2(b->qs, kt_local, lo_pl, row); + repack_neon_q3_k_hmask(b->hmask, kt_local, neg_pl, row); +#else + for (int lk = 0; lk < 32; lk++) { + const int e = kt_local * 32 + lk; + const int g = lk >> 2; + const int pos = row * 4 + (lk & 3); + lo_pl[(g >> 2) * 128 + pos] |= (uint8_t) (q2_3_K_get_low2(b->qs, e) << ((g & 3) * 2)); + if (!q3_K_get_hbit(b, e)) { + neg_pl[pos] |= (uint8_t) (1 << g); + } + } +#endif + for (int sub = 0; sub < 2; sub++) { + sc_pl[sub * 32 + row] = GGML_FP32_TO_FP16(d * (float) q3_K_get_scale(b->scales, kt_local * 2 + sub)); + } + }); +} + +static void repack_tiled_q3_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_kquant_from_tiled_grid(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q3_K, + [](block_q3_K * b, const uint8_t * sb_tiles, size_t tile_size, int row) { + ggml_half sub_scales[16]; + for (int kt_local = 0; kt_local < 8; kt_local++) { + const uint8_t * tile = sb_tiles + kt_local * tile_size; + const uint8_t * lo_pl = tile; + const uint8_t * neg_pl = tile + 256; + const ggml_half * sc_pl = (const ggml_half *) (tile + 384); + + for (int lk = 0; lk < 32; lk++) { + const int e = kt_local * 32 + lk; + const int g = lk >> 2; + const int pos = row * 4 + (lk & 3); + const uint8_t lo = (lo_pl[(g >> 2) * 128 + pos] >> ((g & 3) * 2)) & 3; + + const int c = e / 128; + const int j = (e % 128) / 32; + const int l = e % 32; + b->qs[c * 32 + l] |= (uint8_t) (lo << (2 * j)); + if (!((neg_pl[pos] >> g) & 1)) { + b->hmask[l] |= (uint8_t) (1 << (c * 4 + j)); + } + } + + for (int sub = 0; sub < 2; sub++) { + sub_scales[kt_local * 2 + sub] = sc_pl[sub * 32 + row]; + } + } + + int ls[16]; + if (!hexagon_recover_k_scales(sub_scales, 16, -32, 31, &b->d, ls)) { + float max_scale = 0.0f; + for (int s = 0; s < 16; s++) { + if (fabsf(GGML_FP16_TO_FP32(sub_scales[s])) > fabsf(max_scale)) { + max_scale = GGML_FP16_TO_FP32(sub_scales[s]); + } + } + b->d = GGML_FP32_TO_FP16(-max_scale / 32.0f); + const float d_actual = GGML_FP16_TO_FP32(b->d); + const float inv_d = (d_actual != 0.0f) ? (1.0f / d_actual) : 0.0f; + for (int s = 0; s < 16; s++) { + ls[s] = (std::max)(-32, (std::min)(31, (int) roundf(GGML_FP16_TO_FP32(sub_scales[s]) * inv_d))); + } + } + + for (int s = 0; s < 16; s++) { + const int l = ls[s] + 32; + if (s < 8) { + b->scales[s] = l & 0xF; + } else { + b->scales[s - 8] |= (uint8_t) ((l & 0xF) << 4); + } + b->scales[s % 4 + 8] |= (uint8_t) ((l >> 4) << (2 * (s / 4))); + } + }); +} + +static void repack_q2_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + repack_kquant_to_tiled_grid(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q2_K, + [](uint8_t * tile, const block_q2_K * b, int row, int kt_local) { + uint8_t * lo_pl = tile; + uint8_t * sc_pl = tile + 256; + ggml_half * dd_pl = (ggml_half *) (tile + 320); + +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q2_3_k_low2(b->qs, kt_local, lo_pl, row); +#else + for (int lk = 0; lk < 32; lk++) { + const int g = lk >> 2; + const int pos = row * 4 + (lk & 3); + lo_pl[(g >> 2) * 128 + pos] |= (uint8_t) (q2_3_K_get_low2(b->qs, kt_local * 32 + lk) << ((g & 3) * 2)); + } +#endif + for (int sub = 0; sub < 2; sub++) { + sc_pl[sub * 32 + row] = b->scales[kt_local * 2 + sub]; + } + if (row / 8 == kt_local % 4) { + dd_pl[row % 8] = kt_local < 4 ? b->d : (ggml_half) (b->dmin ^ 0x8000); + } + }); +} + +static void repack_tiled_q2_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_kquant_from_tiled_grid(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q2_K, + [](block_q2_K * b, const uint8_t * sb_tiles, size_t tile_size, int row) { + for (int kt_local = 0; kt_local < 8; kt_local++) { + const uint8_t * tile = sb_tiles + kt_local * tile_size; + const uint8_t * lo_pl = tile; + const uint8_t * sc_pl = tile + 256; + const ggml_half * dd_pl = (const ggml_half *) (tile + 320); + + for (int lk = 0; lk < 32; lk++) { + const int e = kt_local * 32 + lk; + const int g = lk >> 2; + const int pos = row * 4 + (lk & 3); + const uint8_t lo = (lo_pl[(g >> 2) * 128 + pos] >> ((g & 3) * 2)) & 3; + b->qs[(e / 128) * 32 + e % 32] |= (uint8_t) (lo << (2 * ((e % 128) / 32))); + } + + for (int sub = 0; sub < 2; sub++) { + b->scales[kt_local * 2 + sub] = sc_pl[sub * 32 + row]; + } + if (row / 8 == kt_local % 4) { + if (kt_local < 4) { + b->d = dd_pl[row % 8]; + } else { + b->dmin = (ggml_half) (dd_pl[row % 8] ^ 0x8000); + } + } + } + }); +} + +static inline void get_scale_min_k4(int j, const uint8_t * q, uint8_t * d, uint8_t * m) { + if (j < 4) { + *d = q[j] & 63; + *m = q[j + 4] & 63; + } else { + *d = (q[j + 4] & 0xF) | ((q[j - 4] >> 6) << 4); + *m = (q[j + 4] >> 4) | ((q[j - 0] >> 6) << 4); + } +} + +static inline void pack_k4_scales_mins(uint8_t * scales, ggml_half * d, ggml_half * dmin, + const float * sub_scales, const float * sub_mins) { + float max_scale = 0.0f; + float max_min = 0.0f; + for (int j = 0; j < 8; j++) { + if (sub_scales[j] > max_scale) max_scale = sub_scales[j]; + if (sub_mins[j] > max_min) max_min = sub_mins[j]; + } + + float inv_scale = 0.0f; + if (max_scale > 0.0f) { + *d = GGML_FP32_TO_FP16(max_scale / 63.0f); + const float d_actual = GGML_FP16_TO_FP32(*d); + inv_scale = (d_actual > 0.0f) ? (1.0f / d_actual) : 0.0f; + } else { + *d = GGML_FP32_TO_FP16(0.0f); + } + + float inv_min = 0.0f; + if (max_min > 0.0f) { + *dmin = GGML_FP32_TO_FP16(max_min / 63.0f); + const float dmin_actual = GGML_FP16_TO_FP32(*dmin); + inv_min = (dmin_actual > 0.0f) ? (1.0f / dmin_actual) : 0.0f; + } else { + *dmin = GGML_FP32_TO_FP16(0.0f); + } + + for (int j = 0; j < 8; j++) { + uint8_t ls = (std::min)((uint8_t) 63, (uint8_t) roundf(inv_scale * sub_scales[j])); + uint8_t lm = (std::min)((uint8_t) 63, (uint8_t) roundf(inv_min * sub_mins[j])); + if (j < 4) { + scales[j] = ls; + scales[j + 4] = lm; + } else { + scales[j + 4] = (ls & 0xF) | ((lm & 0xF) << 4); + scales[j - 4] |= ((ls >> 4) << 6); + scales[j - 0] |= ((lm >> 4) << 6); + } + } +} + +template +static inline void repack_k4_quants(uint8_t * tile_dst, const BlockT * b, int row, int kt_local, + int64_t sb_per_row, bool use_neon) { +#if defined(__ARM_NEON) || defined(__aarch64__) + if (use_neon) { + if ((row & 7) == 0) { + const uint8_t * qs[8]; + for (int rr = 0; rr < 8; ++rr) { + qs[rr] = b[rr * sb_per_row].qs + (kt_local / 2) * 32; + } + repack_neon_k4_rows(qs, tile_dst, row, (kt_local & 1) != 0); + } + return; + } +#else + GGML_UNUSED(sb_per_row); + GGML_UNUSED(use_neon); +#endif + const uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; + const int shift = (kt_local & 1) ? 4 : 0; + + for (int cp = 0; cp < 16; cp++) { + const uint8_t q0 = (qs_sub[2 * cp + 0] >> shift) & 0x0F; + const uint8_t q1 = (qs_sub[2 * cp + 1] >> shift) & 0x0F; + tile_dst[cp * 32 + row] = (uint8_t) ((q1 << 4) | q0); + } +} + +static void repack_q4_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + const int64_t sb_per_row = t->ne[0] / QK_K; + const bool use_neon = (t->ne[1] % 8 == 0); + repack_kquant_to_tiled_grid(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q4_K, + [sb_per_row, use_neon](uint8_t * tile_dst, const block_q4_K * b, int row, int kt_local) { + const float d = GGML_FP16_TO_FP32(b->d); + const float dmin = GGML_FP16_TO_FP32(b->dmin); + + uint8_t sc, m; + get_scale_min_k4(kt_local, b->scales, &sc, &m); + + repack_k4_quants(tile_dst, b, row, kt_local, sb_per_row, use_neon); + + ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); + scale_dst[2 * row + 0] = GGML_FP32_TO_FP16(d * (float) sc); + scale_dst[2 * row + 1] = GGML_FP32_TO_FP16(-dmin * (float) m); + }); +} + +static void repack_tiled_q4_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_kquant_from_tiled_grid(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q4_K, + [](block_q4_K * b, const uint8_t * sb_tiles, size_t tile_size, int row) { + float sub_scales[8]; + float sub_mins[8]; + + for (int kt_local = 0; kt_local < 8; kt_local++) { + const uint8_t * tile_src = sb_tiles + kt_local * tile_size; + const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); + + uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; + const int shift = (kt_local & 1) ? 4 : 0; + + for (int cp = 0; cp < 16; cp++) { + const uint8_t val = tile_src[cp * 32 + row]; + qs_sub[2 * cp + 0] |= (uint8_t) ((val & 0x0F) << shift); + qs_sub[2 * cp + 1] |= (uint8_t) ((val >> 4) << shift); + } + + const float D = GGML_FP16_TO_FP32(scale_src[2 * row + 0]); + const float M = GGML_FP16_TO_FP32(scale_src[2 * row + 1]); + sub_scales[kt_local] = (D > 0.0f) ? D : 0.0f; + sub_mins[kt_local] = (-M > 0.0f) ? -M : 0.0f; + } + + pack_k4_scales_mins(b->scales, &b->d, &b->dmin, sub_scales, sub_mins); + }); +} + +static void repack_q5_K_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + const int64_t sb_per_row = t->ne[0] / QK_K; + const bool use_neon = (t->ne[1] % 8 == 0); + repack_kquant_to_tiled_grid(t, data, offset, size, HTP_TENSOR_TILE_SIZE_Q5_K, + [sb_per_row, use_neon](uint8_t * tile_dst, const block_q5_K * b, int row, int kt_local) { + const float d = GGML_FP16_TO_FP32(b->d); + const float dmin = GGML_FP16_TO_FP32(b->dmin); + uint8_t * plane = tile_dst + 640; + + uint8_t sc, m; + get_scale_min_k4(kt_local, b->scales, &sc, &m); + + repack_k4_quants(tile_dst, b, row, kt_local, sb_per_row, use_neon); + + const uint8_t hbit = (uint8_t) (1 << kt_local); +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q5_k_qh(b->qh, hbit, plane, row); +#else + for (int cp = 0; cp < 16; cp++) { + const int i = cp / 4; + const int lane = (cp % 4) * 32 + row; + if (b->qh[2 * cp + 0] & hbit) { + plane[lane] |= (uint8_t) (1 << (2 * i)); + } + if (b->qh[2 * cp + 1] & hbit) { + plane[lane] |= (uint8_t) (1 << (2 * i + 1)); + } + } +#endif + + ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); + scale_dst[2 * row + 0] = GGML_FP32_TO_FP16(d * (float) sc); + scale_dst[2 * row + 1] = GGML_FP32_TO_FP16(-dmin * (float) m); + }); +} + +static void repack_tiled_q5_K(void * data, const ggml_tensor * t, size_t offset, size_t size) { + unpack_kquant_from_tiled_grid(data, t, offset, size, HTP_TENSOR_TILE_SIZE_Q5_K, + [](block_q5_K * b, const uint8_t * sb_tiles, size_t tile_size, int row) { + float sub_scales[8]; + float sub_mins[8]; + + for (int kt_local = 0; kt_local < 8; kt_local++) { + const uint8_t * tile_src = sb_tiles + kt_local * tile_size; + const uint8_t * plane = tile_src + 640; + const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); + + uint8_t * qs_sub = b->qs + (kt_local / 2) * 32; + const int shift = (kt_local & 1) ? 4 : 0; + const uint8_t hbit = (uint8_t) (1 << kt_local); + + for (int cp = 0; cp < 16; cp++) { + const uint8_t val = tile_src[cp * 32 + row]; + qs_sub[2 * cp + 0] |= (uint8_t) ((val & 0x0F) << shift); + qs_sub[2 * cp + 1] |= (uint8_t) ((val >> 4) << shift); + + const int i = cp / 4; + const int lane = (cp % 4) * 32 + row; + if (plane[lane] & (1 << (2 * i))) { + b->qh[2 * cp + 0] |= hbit; + } + if (plane[lane] & (1 << (2 * i + 1))) { + b->qh[2 * cp + 1] |= hbit; + } + } + + const float D = GGML_FP16_TO_FP32(scale_src[2 * row + 0]); + const float M = GGML_FP16_TO_FP32(scale_src[2 * row + 1]); + sub_scales[kt_local] = (D > 0.0f) ? D : 0.0f; + sub_mins[kt_local] = (-M > 0.0f) ? -M : 0.0f; + } + + pack_k4_scales_mins(b->scales, &b->d, &b->dmin, sub_scales, sub_mins); + }); +} + +static inline void q1_0_tiled_bit_location(int k, int row, int & byte_offset, int & bit) { + const int quarter = k / 32; + const int kq = k % 32; + + byte_offset = quarter * 128 + 4 * row + (kq % 4); + bit = kq / 4; +} + +static void repack_q1_0_tiled(ggml_tensor * t, const void * data, size_t offset, size_t size) { + const block_q1_0 * src_matrix = (const block_q1_0 *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = ne0 / QK1_0; + const size_t tile_size = HTP_TENSOR_TILE_SIZE_Q1_0; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + const size_t slice_size = ne1 * ggml_row_size(t->type, ne0); + const int64_t start_slice = offset / slice_size; + const int64_t end_slice = (std::min)((int64_t) ((offset + size + slice_size - 1) / slice_size), ne2 * ne3); + + GGML_ASSERT(ne0 % QK1_0 == 0); + + for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { + const block_q1_0 * src_slice = src_matrix + (slice_idx - start_slice) * ne1 * n_k_tiles; + uint8_t * matrix_dst = (uint8_t *) t->data + slice_idx * matrix_size; + + repack_parallel_for_ct(matrix_size, n_col_tiles, [&](int ct0, int ct1) { + for (int ct = ct0; ct < ct1; ct++) { + for (int kt = 0; kt < n_k_tiles; kt++) { + uint8_t * tile_dst = matrix_dst + ((size_t) ct * n_k_tiles + kt) * tile_size; + ggml_half * scale_dst = (ggml_half *) (tile_dst + 512); + memset(tile_dst, 0, tile_size); + + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r >= ne1) { + continue; + } + + const block_q1_0 & block = src_slice[r * n_k_tiles + kt]; + scale_dst[row] = block.d; +#if defined(__ARM_NEON) || defined(__aarch64__) + repack_neon_q1_0_block(block.qs, tile_dst, row); +#else + for (int k = 0; k < QK1_0; k++) { + int byte_offset; + int bit; + q1_0_tiled_bit_location(k, row, byte_offset, bit); + if (block.qs[k / 8] & (1u << (k % 8))) { + tile_dst[byte_offset] |= (uint8_t) (1u << bit); + } + } +#endif + } + } + } + }); + } +} + +static void repack_tiled_q1_0(void * data, const ggml_tensor * t, size_t offset, size_t size) { + block_q1_0 * dst_matrix = (block_q1_0 *) data; + const int64_t ne0 = t->ne[0]; + const int64_t ne1 = t->ne[1]; + const int64_t ne2 = t->ne[2]; + const int64_t ne3 = t->ne[3]; + const int n_col_tiles = hex_round_up(ne1, 32) / 32; + const int n_k_tiles = ne0 / QK1_0; + const size_t tile_size = HTP_TENSOR_TILE_SIZE_Q1_0; + const size_t matrix_size = (size_t) n_col_tiles * n_k_tiles * tile_size; + const size_t row_size_bytes = ggml_row_size(t->type, ne0); + const size_t slice_size = ne1 * row_size_bytes; + const int64_t start_slice = offset / slice_size; + const int64_t end_slice = (std::min)((int64_t) ((offset + size + slice_size - 1) / slice_size), ne2 * ne3); + + GGML_ASSERT(ne0 % QK1_0 == 0); + + for (int64_t slice_idx = start_slice; slice_idx < end_slice; slice_idx++) { + const size_t cur_start_byte = (std::max)(offset, (size_t) slice_idx * slice_size); + const size_t cur_end_byte = (std::min)(offset + size, (size_t) (slice_idx + 1) * slice_size); + const int64_t start_row = (cur_start_byte - (size_t) slice_idx * slice_size) / row_size_bytes; + const int64_t end_row = (std::min)((int64_t) ((cur_end_byte - (size_t) slice_idx * slice_size + row_size_bytes - 1) / row_size_bytes), ne1); + block_q1_0 * dst_slice = dst_matrix + (cur_start_byte - offset) / sizeof(block_q1_0); + const uint8_t * matrix_src = (const uint8_t *) t->data + slice_idx * matrix_size; + + for (int ct = start_row / 32; ct < (end_row + 31) / 32; ct++) { + for (int kt = 0; kt < n_k_tiles; kt++) { + const uint8_t * tile_src = matrix_src + ((size_t) ct * n_k_tiles + kt) * tile_size; + const ggml_half * scale_src = (const ggml_half *) (tile_src + 512); + + for (int row = 0; row < 32; row++) { + const int64_t r = ct * 32 + row; + if (r < start_row || r >= end_row) { + continue; + } + + block_q1_0 & block = dst_slice[(r - start_row) * n_k_tiles + kt]; + memset(block.qs, 0, sizeof(block.qs)); + block.d = scale_src[row]; + for (int k = 0; k < QK1_0; k++) { + int byte_offset; + int bit; + q1_0_tiled_bit_location(k, row, byte_offset, bit); + if (tile_src[byte_offset] & (1u << bit)) { + block.qs[k / 8] |= (uint8_t) (1u << (k % 8)); + } + } + } + } + } + } +} + +// --- Top-level Repack / Unpack Dispatchers --- + +void htp_repack_tensor_tiled(ggml_tensor * tensor, const void * data, size_t size) { + switch (tensor->type) { + case GGML_TYPE_Q1_0: + repack_q1_0_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q4_0: + case GGML_TYPE_IQ4_NL: + repack_q4_0_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q4_1: + repack_q4_1_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q8_0: + repack_q8_0_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_MXFP4: + repack_mxfp4_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q2_0: + repack_q2_0_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q2_K: + repack_q2_K_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q3_K: + repack_q3_K_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q4_K: + repack_q4_K_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q5_K: + repack_q5_K_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_Q6_K: + repack_q6_K_tiled(tensor, data, 0, size); + break; + case GGML_TYPE_F16: + repack_float_to_f16_tiled(tensor, data, 0, size, + [](uint16_t v) { return v; }); + break; + case GGML_TYPE_F32: + repack_float_to_f16_tiled(tensor, data, 0, size, + [](float v) { return (uint16_t) GGML_FP32_TO_FP16(v); }); + break; + case GGML_TYPE_BF16: + repack_float_to_f16_tiled(tensor, data, 0, size, + [](ggml_bf16_t v) { return (uint16_t) GGML_FP32_TO_FP16(GGML_BF16_TO_FP32(v)); }); + break; + default: + break; + } +} + +void htp_unpack_tensor_tiled(void * data, const ggml_tensor * tensor, size_t offset, size_t size) { + GGML_ASSERT(offset + size <= ggml_nbytes(tensor)); + + switch (tensor->type) { + case GGML_TYPE_Q1_0: + repack_tiled_q1_0(data, tensor, offset, size); + break; + case GGML_TYPE_Q4_0: + case GGML_TYPE_IQ4_NL: + repack_tiled_q4_0(data, tensor, offset, size); + break; + case GGML_TYPE_Q4_1: + repack_tiled_q4_1(data, tensor, offset, size); + break; + case GGML_TYPE_Q8_0: + repack_tiled_q8_0(data, tensor, offset, size); + break; + case GGML_TYPE_MXFP4: + repack_tiled_mxfp4(data, tensor, offset, size); + break; + case GGML_TYPE_Q2_0: + repack_tiled_q2_0(data, tensor, offset, size); + break; + case GGML_TYPE_Q2_K: + repack_tiled_q2_K(data, tensor, offset, size); + break; + case GGML_TYPE_Q3_K: + repack_tiled_q3_K(data, tensor, offset, size); + break; + case GGML_TYPE_Q4_K: + repack_tiled_q4_K(data, tensor, offset, size); + break; + case GGML_TYPE_Q5_K: + repack_tiled_q5_K(data, tensor, offset, size); + break; + case GGML_TYPE_Q6_K: + repack_tiled_q6_K(data, tensor, offset, size); + break; + case GGML_TYPE_F16: + unpack_f16_tiled_to_float(data, tensor, offset, size, + [](uint16_t v) { return v; }); + break; + case GGML_TYPE_F32: + unpack_f16_tiled_to_float(data, tensor, offset, size, + [](uint16_t v) { return ggml_fp16_to_fp32((ggml_fp16_t) v); }); + break; + case GGML_TYPE_BF16: + unpack_f16_tiled_to_float(data, tensor, offset, size, + [](uint16_t v) { return ggml_fp32_to_bf16(ggml_fp16_to_fp32((ggml_fp16_t) v)); }); + break; + default: + memcpy(data, (const char *) tensor->data + offset, size); + break; + } +} diff --git a/ggml/src/ggml-hexagon/htp-repack.h b/ggml/src/ggml-hexagon/htp-repack.h new file mode 100644 index 000000000000..f656e9b8ddbe --- /dev/null +++ b/ggml/src/ggml-hexagon/htp-repack.h @@ -0,0 +1,69 @@ +#ifndef HTP_REPACK_H +#define HTP_REPACK_H + +#include +#include + +#include "ggml.h" +#include "htp/htp-tensor.h" + +static inline bool htp_is_tiled_weight_type(enum ggml_type type) { + return type == GGML_TYPE_Q4_0 || type == GGML_TYPE_Q4_1 || + type == GGML_TYPE_Q8_0 || type == GGML_TYPE_IQ4_NL || + type == GGML_TYPE_MXFP4 || type == GGML_TYPE_Q1_0 || + type == GGML_TYPE_Q6_K || + type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K || + type == GGML_TYPE_Q3_K || type == GGML_TYPE_Q2_K || + type == GGML_TYPE_Q2_0 || + type == GGML_TYPE_F16 || type == GGML_TYPE_F32 || + type == GGML_TYPE_BF16; +} + +static inline bool htp_is_tiled_weight_tensor(const struct ggml_tensor * t) { + if (!ggml_is_contiguous(t) || ggml_is_view(t)) { + return false; + } + if (!htp_is_tiled_weight_type(t->type)) { + return false; + } + if (t->ne[0] < 32) { + return false; + } + if (!ggml_is_quantized(t->type)) { + return (t->ne[0] % 32 == 0) && (t->ne[1] % 32 == 0) && (t->ne[2] == 1) && (t->ne[3] == 1); + } + return t->ne[3] == 1; +} + +// Size of one tiled row in the DSP tiled layout. The Q3_K..Q6_K tiles store uncompressed scales/mins, +// so they are larger than the ggml blocks. For the other tiled types (Q2_K included) the tile has the same size. +static inline size_t htp_tiled_row_size(enum ggml_type type, int64_t ne0) { + if (type == GGML_TYPE_F16 || type == GGML_TYPE_F32 || type == GGML_TYPE_BF16) { + return (size_t) ne0 * sizeof(ggml_fp16_t); + } + if (type == GGML_TYPE_Q6_K) { + return (size_t) (ne0 / 32) * (HTP_TENSOR_TILE_SIZE_Q6_K / 32); + } + if (type == GGML_TYPE_Q2_0) { + return (size_t) (ne0 / 64) * 18; + } + if (type == GGML_TYPE_Q4_K) { + return (size_t) (ne0 / 32) * (HTP_TENSOR_TILE_SIZE_Q4_K / 32); + } + if (type == GGML_TYPE_Q5_K) { + return (size_t) (ne0 / 32) * (HTP_TENSOR_TILE_SIZE_Q5_K / 32); + } + if (type == GGML_TYPE_Q3_K) { + return (size_t) (ne0 / 32) * (HTP_TENSOR_TILE_SIZE_Q3_K / 32); + } + return ggml_row_size(type, ne0); +} + +static inline bool htp_is_hmx_weight_type(enum ggml_type type) { + return htp_is_tiled_weight_type(type); +} + +void htp_repack_tensor_tiled(struct ggml_tensor * t, const void * data, size_t size); +void htp_unpack_tensor_tiled(void * data, const struct ggml_tensor * t, size_t offset, size_t size); + +#endif // HTP_REPACK_H diff --git a/ggml/src/ggml-hexagon/htp/CMakeLists.txt b/ggml/src/ggml-hexagon/htp/CMakeLists.txt index bc1474ae8320..b5d6d55daf41 100644 --- a/ggml/src/ggml-hexagon/htp/CMakeLists.txt +++ b/ggml/src/ggml-hexagon/htp/CMakeLists.txt @@ -20,7 +20,7 @@ add_library(${HTP_LIB} SHARED work-queue.c dma-queue.c hmx-queue.c - htp-tensor.c + htp-dcache.c matmul-ops.c flash-attn-ops.c gated-delta-net-ops.c @@ -28,7 +28,7 @@ add_library(${HTP_LIB} SHARED unary-ops.c sum-rows-ops.c softmax-ops.c - act-ops.c + glu-ops.c rope-ops.c set-rows-ops.c get-rows-ops.c @@ -44,8 +44,10 @@ add_library(${HTP_LIB} SHARED pad-ops.c argsort-ops.c im2col-ops.c + conv2d-ops.c roll-ops.c pool-ops.c + upscale-ops.c allreduce-ops.c ) @@ -53,9 +55,17 @@ target_compile_definitions(${HTP_LIB} PRIVATE $,HTP_DEBUG=1,NDEBUG=1> $,FARF_HIGH=1,>) - build_idl(htp_iface.idl ${HTP_LIB}) set_target_properties(${HTP_LIB} PROPERTIES EXPORT_COMPILE_COMMANDS ON) +if (NOT Python3_EXECUTABLE) + find_package(Python3 REQUIRED COMPONENTS Interpreter) +endif() + +add_custom_command(TARGET ${HTP_LIB} POST_BUILD + COMMAND ${CMAKE_COMMAND} -E echo "Adding SWIV section $" + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/htp-swiv.py -i $ -o $ + VERBATIM) + install(TARGETS ${HTP_LIB}) diff --git a/ggml/src/ggml-hexagon/htp/allreduce-ops.h b/ggml/src/ggml-hexagon/htp/allreduce-ops.h index 54ef60378fa1..1264c1cbbcc3 100644 --- a/ggml/src/ggml-hexagon/htp/allreduce-ops.h +++ b/ggml/src/ggml-hexagon/htp/allreduce-ops.h @@ -32,6 +32,7 @@ static inline size_t htp_allreduce_vtcm_buffer_count( } struct htp_allreduce_kernel_params { + uint8_t kernel_type; int32_t rank; int32_t n_ranks; int32_t n_threads; @@ -39,7 +40,6 @@ struct htp_allreduce_kernel_params { int32_t elems_per_thread; // 1D: nelem_per_thread, 2D: nrows_per_thread int32_t vtcm_size_per_thread; int32_t vtcm_size; - int32_t kernel_type; int32_t ne0; int32_t ne1; int32_t row_size_aligned; @@ -50,6 +50,12 @@ struct htp_allreduce_kernel_params { int32_t mode; // enum htp_allreduce_mode: FULL or SHARDED_FANOUT }; +#if defined(__cplusplus) +static_assert(sizeof(struct htp_allreduce_kernel_params) <= 128, "htp_allreduce_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_allreduce_kernel_params) <= 128, "htp_allreduce_kernel_params is too large for kernel_params blob"); +#endif + #ifdef __cplusplus } #endif diff --git a/ggml/src/ggml-hexagon/htp/argsort-ops.c b/ggml/src/ggml-hexagon/htp/argsort-ops.c index 6f24d95f90bb..7aa7ca8e41c9 100644 --- a/ggml/src/ggml-hexagon/htp/argsort-ops.c +++ b/ggml/src/ggml-hexagon/htp/argsort-ops.c @@ -453,7 +453,10 @@ static void merge_runs( struct htp_sort_chunk_ctx { struct htp_ops_context * octx; const struct htp_sort_kernel_params * kparams; - uint8_t * vtcm_base; + uint8_t * phase1_base; + size_t phase1_slot_size; + float * merge_values; + int32_t * merge_indices; uint32_t real_count[HTP_MAX_NTHREADS]; }; @@ -462,26 +465,27 @@ static void htp_sort_chunk_job(unsigned int n, unsigned int i, void * data) { struct htp_ops_context * octx = cctx->octx; const struct htp_sort_kernel_params * kparams = cctx->kparams; const struct htp_tensor * src0 = octx->src[0]; + const struct htp_tensor * dst = octx->dst; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; - uint32_t ne00 = (uint32_t) kparams->ne00; + uint32_t ne00 = src0->ne[0]; uint32_t chunk_base = i * chunk_elems; uint32_t real_count = (chunk_base < ne00) ? MIN(chunk_elems, ne00 - chunk_base) : 0; cctx->real_count[i] = real_count; - uint8_t * spad = cctx->vtcm_base + (size_t) kparams->phase1_slot_size * i; + uint8_t * spad = cctx->phase1_base + cctx->phase1_slot_size * i; float * values_buf = (float *) spad; int32_t * indices_buf = (int32_t *) (spad + chunk_elems * sizeof(float)); - float * merge_values = (float *) (cctx->vtcm_base + kparams->merge_values_off); - int32_t * merge_indices = (int32_t *) (cctx->vtcm_base + kparams->merge_indices_off); + float * merge_values = cctx->merge_values; + int32_t * merge_indices = cctx->merge_indices; struct htp_thread_trace * tr = &octx->ctx->trace[i]; const dma_addr_t src_addr = src0->data + (size_t) chunk_base * sizeof(float); if (kparams->is_top_k) { - uint32_t k = (uint32_t) kparams->k; + uint32_t k = dst->ne[0]; uint32_t local_k = MIN(k, chunk_elems); if (real_count == 0) { @@ -559,17 +563,17 @@ static void htp_argsort_merge_l1_job(unsigned int n, unsigned int i, void * data uint32_t count0 = cctx->real_count[c0]; uint32_t count1 = cctx->real_count[c1]; - size_t slot_size = (size_t) kparams->phase1_slot_size; + size_t slot_size = cctx->phase1_slot_size; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; - const float * val0 = (const float *) (cctx->vtcm_base + slot_size * c0); - const int32_t * idx0 = (const int32_t *) (cctx->vtcm_base + slot_size * c0 + chunk_elems * sizeof(float)); - const float * val1 = (const float *) (cctx->vtcm_base + slot_size * c1); - const int32_t * idx1 = (const int32_t *) (cctx->vtcm_base + slot_size * c1 + chunk_elems * sizeof(float)); + const float * val0 = (const float *) (cctx->phase1_base + slot_size * c0); + const int32_t * idx0 = (const int32_t *) (cctx->phase1_base + slot_size * c0 + chunk_elems * sizeof(float)); + const float * val1 = (const float *) (cctx->phase1_base + slot_size * c1); + const int32_t * idx1 = (const int32_t *) (cctx->phase1_base + slot_size * c1 + chunk_elems * sizeof(float)); uint32_t out_offset = (2 * i) * chunk_elems; - float * out_val = (float *) (cctx->vtcm_base + kparams->merge_values_off) + out_offset; - int32_t * out_idx = (int32_t *) (cctx->vtcm_base + kparams->merge_indices_off) + out_offset; + float * out_val = cctx->merge_values + out_offset; + int32_t * out_idx = cctx->merge_indices + out_offset; struct htp_thread_trace * tr = &cctx->octx->ctx->trace[i]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); @@ -587,21 +591,21 @@ static void htp_argsort_merge_l2_job(unsigned int n, unsigned int i, void * data struct htp_sort_chunk_ctx * cctx = mctx->cctx; const struct htp_sort_kernel_params * kparams = cctx->kparams; - size_t slot_size = (size_t) kparams->phase1_slot_size; + size_t slot_size = cctx->phase1_slot_size; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; uint32_t off0 = (4 * i) * chunk_elems; uint32_t off1 = (4 * i + 2) * chunk_elems; - const float * val0 = (const float *) (cctx->vtcm_base + kparams->merge_values_off) + off0; - const int32_t * idx0 = (const int32_t *) (cctx->vtcm_base + kparams->merge_indices_off) + off0; - const float * val1 = (const float *) (cctx->vtcm_base + kparams->merge_values_off) + off1; - const int32_t * idx1 = (const int32_t *) (cctx->vtcm_base + kparams->merge_indices_off) + off1; + const float * val0 = cctx->merge_values + off0; + const int32_t * idx0 = cctx->merge_indices + off0; + const float * val1 = cctx->merge_values + off1; + const int32_t * idx1 = cctx->merge_indices + off1; uint32_t count0 = cctx->real_count[4*i + 0] + cctx->real_count[4*i + 1]; uint32_t count1 = cctx->real_count[4*i + 2] + cctx->real_count[4*i + 3]; - uint8_t * slot_base = cctx->vtcm_base + (4 * i) * slot_size; + uint8_t * slot_base = cctx->phase1_base + (4 * i) * slot_size; float * out_val = (float *) slot_base; int32_t * out_idx = (int32_t *) (slot_base + 4 * chunk_elems * sizeof(float)); @@ -614,7 +618,10 @@ static void htp_argsort_merge_l2_job(unsigned int n, unsigned int i, void * data struct htp_sort_multi_row_ctx { struct htp_ops_context * octx; const struct htp_sort_kernel_params * kparams; - uint8_t * vtcm_base; + uint8_t * phase1_base; + size_t phase1_slot_size; + uint32_t row_start; + uint32_t row_end; uint32_t nrows_per_thread; }; @@ -624,12 +631,18 @@ struct htp_tensor_row_coord { uint32_t i03; }; -static inline struct htp_tensor_row_coord init_row_coord(uint32_t r, uint32_t ne01, uint32_t ne02) { +static inline struct htp_tensor_row_coord init_row_coord( + uint32_t r, + uint32_t ne01, + uint32_t ne02, + const struct fastdiv_values * div_ne01, + const struct fastdiv_values * div_ne01_ne02 +) { uint32_t ne01_ne02 = ne01 * ne02; - uint32_t i03 = (ne01_ne02 > 0) ? (r / ne01_ne02) : 0; - uint32_t rem = (ne01_ne02 > 0) ? (r % ne01_ne02) : 0; - uint32_t i02 = (ne01 > 0) ? (rem / ne01) : 0; - uint32_t i01 = (ne01 > 0) ? (rem % ne01) : 0; + uint32_t i03 = (ne01_ne02 > 0) ? fastdiv(r, div_ne01_ne02) : 0; + uint32_t rem = (ne01_ne02 > 0) ? (r - i03 * ne01_ne02) : 0; + uint32_t i02 = (ne01 > 0) ? fastdiv(rem, div_ne01) : 0; + uint32_t i01 = (ne01 > 0) ? (rem - i02 * ne01) : 0; return (struct htp_tensor_row_coord){ i01, i02, i03 }; } @@ -701,7 +714,7 @@ static void htp_sort_multi_row_job(unsigned int n, unsigned int ith, void * data const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; - uint32_t ne00 = (uint32_t) kparams->ne00; + uint32_t ne00 = src0->ne[0]; uint32_t ne01 = src0->ne[1]; uint32_t ne02 = src0->ne[2]; @@ -713,16 +726,16 @@ static void htp_sort_multi_row_job(unsigned int n, unsigned int ith, void * data uint32_t nb2 = dst->nb[2]; uint32_t nb3 = dst->nb[3]; - uint32_t row_start = (uint32_t) kparams->row_start; - uint32_t row_end = (uint32_t) kparams->row_end; + uint32_t row_start = mctx->row_start; + uint32_t row_end = mctx->row_end; uint32_t r_start = row_start + ith * mctx->nrows_per_thread; uint32_t r_end = MIN(r_start + mctx->nrows_per_thread, row_end); if (r_start >= r_end) return; - size_t spad_offset = ith * (size_t) (kparams->phase1_slot_size * kparams->n_slots); - uint8_t * thread_spad = mctx->vtcm_base + spad_offset; - size_t slot_size = (size_t) kparams->phase1_slot_size; + size_t slot_size = mctx->phase1_slot_size; + size_t spad_offset = ith * slot_size * (size_t) kparams->n_slots; + uint8_t * thread_spad = mctx->phase1_base + spad_offset; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; float * values_buf = (float *) thread_spad; @@ -732,14 +745,14 @@ static void htp_sort_multi_row_job(unsigned int n, unsigned int ith, void * data struct htp_thread_trace * tr = &octx->ctx->trace[ith]; bool is_top_k = kparams->is_top_k != 0; - uint32_t k = (uint32_t) kparams->k; + uint32_t k = dst->ne[0]; enum ggml_sort_order order = (enum ggml_sort_order) kparams->order; const uint32_t src_bytes = ne00 * sizeof(float); const uint32_t dst_bytes = (is_top_k ? k : ne00) * sizeof(int32_t); if (kparams->n_slots == 2) { - struct htp_tensor_row_coord prime_coord = init_row_coord(r_start, ne01, ne02); + struct htp_tensor_row_coord prime_coord = init_row_coord(r_start, ne01, ne02, &kparams->div_ne01, &kparams->div_ne01_ne02); for (uint32_t r = r_start, spad_idx = 0; r < r_end && spad_idx < 2; r++, spad_idx++) { uint8_t * cur_spad = thread_spad + spad_idx * slot_size; float * cur_values = (float *) cur_spad; @@ -759,8 +772,8 @@ static void htp_sort_multi_row_job(unsigned int n, unsigned int ith, void * data step_row_coord(&prime_coord, ne01, ne02); } - struct htp_tensor_row_coord dst_coord = init_row_coord(r_start, ne01, ne02); - struct htp_tensor_row_coord next_src_coord = init_row_coord(r_start + 2, ne01, ne02); + struct htp_tensor_row_coord dst_coord = init_row_coord(r_start, ne01, ne02, &kparams->div_ne01, &kparams->div_ne01_ne02); + struct htp_tensor_row_coord next_src_coord = init_row_coord(r_start + 2, ne01, ne02, &kparams->div_ne01, &kparams->div_ne01_ne02); for (uint32_t r = r_start; r < r_end; r++) { uint32_t cur_slot = (r - r_start) & 1; @@ -796,7 +809,7 @@ static void htp_sort_multi_row_job(unsigned int n, unsigned int ith, void * data dma_queue_flush(dma_q); } else { - struct htp_tensor_row_coord coord = init_row_coord(r_start, ne01, ne02); + struct htp_tensor_row_coord coord = init_row_coord(r_start, ne01, ne02, &kparams->div_ne01, &kparams->div_ne01_ne02); for (uint32_t r = r_start; r < r_end; r++) { dma_addr_t src_addr = src0->data + coord_offset(coord, nb01, nb02, nb03); dma_addr_t dst_addr = dst->data + coord_offset(coord, nb1, nb2, nb3); @@ -847,52 +860,39 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { uint32_t ne00 = src0->ne[0]; uint32_t k = dst->ne[0]; - struct htp_sort_kernel_params kparams_local; const struct htp_sort_kernel_params * kparams = (const struct htp_sort_kernel_params *) octx->kernel_params; - if (kparams->n_threads == 0) { - struct htp_sort_vtcm_layout layout; - if (!htp_sort_solve_layout(&layout, ne00, total_rows, k, octx->n_threads, octx->ctx->vtcm_size, is_top_k)) { - return HTP_STATUS_VTCM_TOO_SMALL; - } - memset(&kparams_local, 0, sizeof(kparams_local)); - kparams_local.n_threads = (int32_t) layout.n_threads; - kparams_local.total_rows = (int32_t) total_rows; - kparams_local.row_start = (int32_t) row_start; - kparams_local.row_end = (int32_t) row_end; - kparams_local.ne00 = (int32_t) ne00; - kparams_local.k = (int32_t) k; - kparams_local.order = is_top_k ? GGML_SORT_ORDER_DESC : (int32_t) octx->op_params[0]; - kparams_local.is_top_k = is_top_k ? 1 : 0; - kparams_local.use_dma = 1; - kparams_local.chunk_elems = (int32_t) layout.chunk_elems; - kparams_local.n_chunks = (int32_t) layout.n_chunks; - kparams_local.vtcm_size = (int32_t) layout.total_bytes; - kparams_local.phase1_slot_size = (int32_t) layout.phase1_slot_size; - kparams_local.merge_values_off = (int32_t) layout.merge_values_off; - kparams_local.merge_indices_off = (int32_t) layout.merge_indices_off; - kparams_local.merge_elems = (int32_t) layout.merge_elems; - kparams_local.n_slots = (int32_t) layout.n_slots; - kparams = &kparams_local; - } else if (octx->ctx->mdev.count > 1) { - memcpy(&kparams_local, kparams, sizeof(kparams_local)); - kparams_local.row_start = (int32_t) row_start; - kparams_local.row_end = (int32_t) row_end; - kparams = &kparams_local; + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; } - if (octx->ctx->vtcm_size < (size_t) kparams->vtcm_size) { - FARF(ERROR, "sort: VTCM size too small. Needed %d, have %zu", kparams->vtcm_size, octx->ctx->vtcm_size); + struct htp_sort_vtcm_layout layout; + htp_sort_vtcm_layout_build(&layout, + total_rows, + (uint32_t) kparams->chunk_elems, + (uint32_t) kparams->n_chunks, + (uint32_t) kparams->merge_elems, + (uint32_t) kparams->n_threads, + (uint32_t) kparams->n_slots); + + if (octx->ctx->vtcm_size < layout.total_bytes) { + FARF(ERROR, "sort: VTCM size too small. Needed %zu, have %zu", layout.total_bytes, octx->ctx->vtcm_size); return HTP_STATUS_VTCM_TOO_SMALL; } - uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; + uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; + uint8_t * phase1_base = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, layout.off_phase1); + float * merge_values = VTCM_LAYOUT_PTR(float, vtcm_base, layout.off_merge_values); + int32_t * merge_indices = VTCM_LAYOUT_PTR(int32_t, vtcm_base, layout.off_merge_indices); if (total_rows == 1 && kparams->n_chunks > 1) { struct htp_sort_chunk_ctx cctx; - cctx.octx = octx; - cctx.kparams = kparams; - cctx.vtcm_base = vtcm_base; + cctx.octx = octx; + cctx.kparams = kparams; + cctx.phase1_base = phase1_base; + cctx.phase1_slot_size = layout.phase1_slot_size; + cctx.merge_values = merge_values; + cctx.merge_indices = merge_indices; memset(cctx.real_count, 0, sizeof(cctx.real_count)); work_queue_run(octx->ctx->work_queue, htp_sort_chunk_job, &cctx, (uint32_t) kparams->n_chunks); @@ -902,8 +902,8 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { uint32_t local_k = MIN(k, chunk_elems); if (k == 1 && ne00 >= 128*1024) { - float * cand_vals = (float *) (vtcm_base + kparams->merge_values_off); - int32_t * cand_idxs = (int32_t *) (vtcm_base + kparams->merge_indices_off); + float * cand_vals = merge_values; + int32_t * cand_idxs = merge_indices; float best_val = cand_vals[0]; int32_t best_idx = cand_idxs[0]; for (int32_t c = 1; c < kparams->n_chunks; c++) { @@ -918,8 +918,8 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { } uint32_t total_candidates = (uint32_t) kparams->n_chunks * local_k; - float * cand_vals = (float *) (vtcm_base + kparams->merge_values_off); - int32_t * cand_idxs = (int32_t *) (vtcm_base + kparams->merge_indices_off); + float * cand_vals = merge_values; + int32_t * cand_idxs = merge_indices; uint32_t merge_elems = (uint32_t) kparams->merge_elems; if (merge_elems > total_candidates) { @@ -943,18 +943,18 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { struct htp_argsort_merge_l2_ctx l2ctx = { &cctx, asc }; work_queue_run(octx->ctx->work_queue, htp_argsort_merge_l2_job, &l2ctx, 2); - size_t slot_size = (size_t) kparams->phase1_slot_size; + size_t slot_size = layout.phase1_slot_size; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; - const float * val0 = (const float *) vtcm_base; - const int32_t * idx0 = (const int32_t *) (vtcm_base + 4 * chunk_elems * sizeof(float)); - const float * val1 = (const float *) (vtcm_base + 4 * slot_size); - const int32_t * idx1 = (const int32_t *) (vtcm_base + 4 * slot_size + 4 * chunk_elems * sizeof(float)); + const float * val0 = (const float *) phase1_base; + const int32_t * idx0 = (const int32_t *) (phase1_base + 4 * chunk_elems * sizeof(float)); + const float * val1 = (const float *) (phase1_base + 4 * slot_size); + const int32_t * idx1 = (const int32_t *) (phase1_base + 4 * slot_size + 4 * chunk_elems * sizeof(float)); uint32_t n01 = cctx.real_count[0] + cctx.real_count[1] + cctx.real_count[2] + cctx.real_count[3]; uint32_t n23 = cctx.real_count[4] + cctx.real_count[5] + cctx.real_count[6] + cctx.real_count[7]; - int32_t * final_idx = (int32_t *) (vtcm_base + kparams->merge_indices_off); + int32_t * final_idx = merge_indices; struct htp_thread_trace * tr = &octx->ctx->trace[0]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, 0); merge_runs(val0, idx0, n01, val1, idx1, n23, NULL, final_idx, asc); @@ -968,27 +968,27 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { uint32_t n01 = cctx.real_count[0] + cctx.real_count[1]; uint32_t n23 = cctx.real_count[2] + cctx.real_count[3]; - const float * val01 = (const float *) (vtcm_base + kparams->merge_values_off); - const int32_t * idx01 = (const int32_t *) (vtcm_base + kparams->merge_indices_off); - const float * val23 = (const float *) (vtcm_base + kparams->merge_values_off) + 2 * chunk_elems; - const int32_t * idx23 = (const int32_t *) (vtcm_base + kparams->merge_indices_off) + 2 * chunk_elems; + const float * val01 = merge_values; + const int32_t * idx01 = merge_indices; + const float * val23 = merge_values + 2 * chunk_elems; + const int32_t * idx23 = merge_indices + 2 * chunk_elems; - int32_t * final_idx = (int32_t *) vtcm_base; + int32_t * final_idx = (int32_t *) phase1_base; struct htp_thread_trace * tr = &octx->ctx->trace[0]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, 0); merge_runs(val01, idx01, n01, val23, idx23, n23, NULL, final_idx, asc); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, 0); dma_sync_write(octx->ctx->dma[0], dst->data, final_idx, ne00 * sizeof(int32_t)); } else if (kparams->n_chunks == 2) { - size_t slot_size = (size_t) kparams->phase1_slot_size; + size_t slot_size = layout.phase1_slot_size; uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; - const float * val0 = (const float *) (vtcm_base); - const int32_t * idx0 = (const int32_t *) (vtcm_base + chunk_elems * sizeof(float)); - const float * val1 = (const float *) (vtcm_base + slot_size); - const int32_t * idx1 = (const int32_t *) (vtcm_base + slot_size + chunk_elems * sizeof(float)); + const float * val0 = (const float *) (phase1_base); + const int32_t * idx0 = (const int32_t *) (phase1_base + chunk_elems * sizeof(float)); + const float * val1 = (const float *) (phase1_base + slot_size); + const int32_t * idx1 = (const int32_t *) (phase1_base + slot_size + chunk_elems * sizeof(float)); - int32_t * final_idx = (int32_t *) (vtcm_base + kparams->merge_indices_off); + int32_t * final_idx = merge_indices; struct htp_thread_trace * tr = &octx->ctx->trace[0]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, 0); merge_runs(val0, idx0, cctx.real_count[0], val1, idx1, cctx.real_count[1], NULL, final_idx, asc); @@ -996,7 +996,7 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { dma_sync_write(octx->ctx->dma[0], dst->data, final_idx, ne00 * sizeof(int32_t)); } else { uint32_t chunk_elems = (uint32_t) kparams->chunk_elems; - int32_t * final_idx = (int32_t *) (vtcm_base + chunk_elems * sizeof(float)); + int32_t * final_idx = (int32_t *) (phase1_base + chunk_elems * sizeof(float)); dma_sync_write(octx->ctx->dma[0], dst->data, final_idx, ne00 * sizeof(int32_t)); } } @@ -1006,7 +1006,10 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { struct htp_sort_multi_row_ctx mctx; mctx.octx = octx; mctx.kparams = kparams; - mctx.vtcm_base = vtcm_base; + mctx.phase1_base = phase1_base; + mctx.phase1_slot_size = layout.phase1_slot_size; + mctx.row_start = row_start; + mctx.row_end = row_end; uint32_t dst_row_bytes = (uint32_t) dst_row_size; uint32_t rows_per_chunk = 0; @@ -1014,13 +1017,13 @@ static int op_sort_common(struct htp_ops_context * octx, bool is_top_k) { if (rows_per_chunk == 0) { rows_per_chunk = 1; } - uint32_t dr = (nrows + (uint32_t) kparams->n_threads - 1) / (uint32_t) kparams->n_threads; + uint32_t dr = fastdiv(nrows + octx->n_threads - 1, &octx->n_threads_div); if (rows_per_chunk > 1) { dr = hex_round_up(dr, rows_per_chunk); } mctx.nrows_per_thread = dr; - work_queue_run(octx->ctx->work_queue, htp_sort_multi_row_job, &mctx, (uint32_t) kparams->n_threads); + work_queue_run(octx->ctx->work_queue, htp_sort_multi_row_job, &mctx, octx->n_threads); return HTP_STATUS_OK; } diff --git a/ggml/src/ggml-hexagon/htp/argsort-ops.h b/ggml/src/ggml-hexagon/htp/argsort-ops.h index 05320a2e91c8..f74189fba5d4 100644 --- a/ggml/src/ggml-hexagon/htp/argsort-ops.h +++ b/ggml/src/ggml-hexagon/htp/argsort-ops.h @@ -7,33 +7,27 @@ #include #include "hex-fastdiv.h" +#include "htp-vtcm.h" struct htp_sort_kernel_params { - int32_t n_threads; - int32_t total_rows; - int32_t row_start; - int32_t row_end; - int32_t ne00; - int32_t k; - int32_t order; // GGML_SORT_ORDER_ASC (0) or GGML_SORT_ORDER_DESC (1) - int32_t is_top_k; // 1 if TOP_K, 0 if ARGSORT - int32_t use_dma; // 1 if DMA enabled - int32_t chunk_elems; - int32_t n_chunks; - int32_t vtcm_size; - int32_t phase1_slot_size; - int32_t merge_values_off; - int32_t merge_indices_off; - int32_t merge_elems; - int32_t n_slots; - int32_t pad[15]; + uint32_t n_threads; + uint32_t order; // GGML_SORT_ORDER_ASC (0) or GGML_SORT_ORDER_DESC (1) + uint32_t is_top_k; // 1 if TOP_K, 0 if ARGSORT + uint32_t chunk_elems; + uint32_t n_chunks; + uint32_t vtcm_size; + uint32_t merge_elems; + uint32_t n_slots; + struct fastdiv_values div_ne01; + struct fastdiv_values div_ne01_ne02; }; struct htp_sort_vtcm_layout { size_t total_bytes; size_t phase1_slot_size; - size_t merge_values_off; - size_t merge_indices_off; + size_t off_phase1; + size_t off_merge_values; + size_t off_merge_indices; uint32_t chunk_elems; uint32_t n_chunks; uint32_t merge_elems; @@ -41,6 +35,39 @@ struct htp_sort_vtcm_layout { uint32_t n_slots; }; +static inline void htp_sort_vtcm_layout_build( + struct htp_sort_vtcm_layout * L, + uint32_t total_rows, + uint32_t chunk_elems, + uint32_t n_chunks, + uint32_t merge_elems, + uint32_t n_threads, + uint32_t n_slots) { + + memset(L, 0, sizeof(*L)); + L->chunk_elems = chunk_elems; + L->n_chunks = n_chunks; + L->merge_elems = merge_elems; + L->n_threads = n_threads; + L->n_slots = n_slots; + + const size_t values_size = ((chunk_elems * sizeof(float)) + 127) & ~127; + const size_t indices_size = ((chunk_elems * sizeof(int32_t)) + 127) & ~127; + L->phase1_slot_size = ((values_size + indices_size) + 255) & ~255; + + size_t off = 0; + if (total_rows > 1) { + VTCM_LAYOUT_ALLOC(off, off_phase1, L->phase1_slot_size * n_slots * n_threads); + } else { + VTCM_LAYOUT_ALLOC(off, off_phase1, L->phase1_slot_size * n_chunks * n_slots); + const size_t merge_values_size = ((merge_elems * sizeof(float)) + 127) & ~127; + const size_t merge_indices_size = ((merge_elems * sizeof(int32_t)) + 127) & ~127; + VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_merge_values, merge_values_size, n_chunks > 1); + VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_merge_indices, merge_indices_size, n_chunks > 1); + } + L->total_bytes = off; +} + static inline bool htp_sort_solve_layout( struct htp_sort_vtcm_layout * layout, uint32_t ne00, @@ -75,18 +102,8 @@ static inline bool htp_sort_solve_layout( n_threads--; } - size_t total_bytes = spad_per_thread * n_threads; - if (total_bytes > vtcm_budget) { - return false; - } - - layout->total_bytes = total_bytes; - layout->phase1_slot_size = spad_per_slot; - layout->chunk_elems = ne00_padded; - layout->n_chunks = 1; - layout->n_threads = n_threads; - layout->n_slots = n_slots; - return true; + htp_sort_vtcm_layout_build(layout, total_rows, ne00_padded, 1, 0, n_threads, n_slots); + return layout->total_bytes <= vtcm_budget; } uint32_t n_vec = (ne00 + 31) / 32; @@ -102,17 +119,7 @@ static inline bool htp_sort_solve_layout( uint32_t chunk_n_vec = n_vec_pow2 / n_chunks; uint32_t chunk_elems = chunk_n_vec * 32; - - size_t phase1_values_size = ((chunk_elems * sizeof(float)) + 127) & ~127; - size_t phase1_indices_size = ((chunk_elems * sizeof(int32_t)) + 127) & ~127; - size_t phase1_slot_size = ((phase1_values_size + phase1_indices_size) + 255) & ~255; - size_t phase1_total_size = phase1_slot_size * n_chunks; - - size_t merge_values_size = 0; - size_t merge_indices_size = 0; - size_t merge_values_off = phase1_total_size; - size_t merge_indices_off = 0; - uint32_t merge_elems = 0; + uint32_t merge_elems = 0; if (n_chunks > 1) { if (is_top_k) { @@ -125,47 +132,25 @@ static inline bool htp_sort_solve_layout( } else { merge_elems = n_vec_pow2 * 32; } - merge_values_size = ((merge_elems * sizeof(float)) + 127) & ~127; - merge_indices_size = ((merge_elems * sizeof(int32_t)) + 127) & ~127; - merge_indices_off = merge_values_off + merge_values_size; } - size_t total_bytes = phase1_total_size + merge_values_size + merge_indices_size; + htp_sort_vtcm_layout_build(layout, 1, chunk_elems, n_chunks, merge_elems, n_chunks, 1); - if (total_bytes > vtcm_budget && n_chunks > 1) { - n_chunks = 1; + if (layout->total_bytes > vtcm_budget && n_chunks > 1) { + n_chunks = 1; chunk_elems = n_vec_pow2 * 32; - phase1_values_size = ((chunk_elems * sizeof(float)) + 127) & ~127; - phase1_indices_size = ((chunk_elems * sizeof(int32_t)) + 127) & ~127; - phase1_slot_size = ((phase1_values_size + phase1_indices_size) + 255) & ~255; - phase1_total_size = phase1_slot_size; - merge_values_size = 0; - merge_indices_size = 0; - merge_values_off = phase1_total_size; - merge_indices_off = 0; - merge_elems = 0; - total_bytes = phase1_total_size; + merge_elems = 0; + htp_sort_vtcm_layout_build(layout, 1, chunk_elems, n_chunks, merge_elems, 1, 1); } - if (total_bytes > vtcm_budget) { + if (layout->total_bytes > vtcm_budget) { return false; } - uint32_t n_slots = 1; - if (n_chunks == 1 && phase1_slot_size * 2 <= vtcm_budget) { - n_slots = 2; - total_bytes = phase1_slot_size * 2; + if (n_chunks == 1 && layout->phase1_slot_size * 2 <= vtcm_budget) { + htp_sort_vtcm_layout_build(layout, 1, chunk_elems, 1, 0, 1, 2); } - layout->total_bytes = total_bytes; - layout->phase1_slot_size = phase1_slot_size; - layout->merge_values_off = merge_values_off; - layout->merge_indices_off = merge_indices_off; - layout->chunk_elems = chunk_elems; - layout->n_chunks = n_chunks; - layout->merge_elems = merge_elems; - layout->n_threads = n_chunks; - layout->n_slots = n_slots; return true; } diff --git a/ggml/src/ggml-hexagon/htp/binary-ops.c b/ggml/src/ggml-hexagon/htp/binary-ops.c index 78ce4bb63d1b..48f461e46673 100644 --- a/ggml/src/ggml-hexagon/htp/binary-ops.c +++ b/ggml/src/ggml-hexagon/htp/binary-ops.c @@ -42,6 +42,7 @@ struct htp_binary_context { uint32_t nrows_per_thread; uint32_t total_rows; uint32_t row_start; + uint32_t n_srcs; size_t src0_row_size_aligned; size_t src1_row_size_aligned; size_t dst_row_size_aligned; @@ -380,6 +381,7 @@ static void binary_thread_vector_same_shape(unsigned int nth, unsigned int ith, size_t dst_spad_half = layout->dst_spad_half_size; dma_queue * dma_q = octx->ctx->dma[ith]; + const uint32_t n_srcs = bctx->n_srcs; uint32_t ir_prefetch = start_row; int spad_idx = 0; @@ -391,12 +393,7 @@ static void binary_thread_vector_same_shape(unsigned int nth, unsigned int ith, i02 = fastdiv(rem, &bctx->src0_dim1_div); i01 = rem - i02 * ne01; - uint32_t i13 = (ne13 == 1) ? 0 : i03; - uint32_t i12 = (ne12 == 1) ? 0 : i02; - uint32_t i11 = (ne11 == 1) ? 0 : i01; - dma_addr_t src0_curr = src0->data + i03 * nb03 + i02 * nb02 + i01 * nb01; - dma_addr_t src1_curr = src1->data + i13 * nb13 + i12 * nb12 + i11 * nb11; dma_addr_t dst_curr = dst->data + i03 * nb3 + i02 * nb2 + i01 * nb1; uint8_t * s0_spad = src0_spad_base + spad_idx * src0_spad_half; @@ -405,7 +402,15 @@ static void binary_thread_vector_same_shape(unsigned int nth, unsigned int ith, dma_queue_push(dma_q, dma_make_data(dst_curr, d_spad), nb1, bctx->dst_row_size_aligned, row_size_bytes, 0); dma_queue_push(dma_q, dma_make_data(s0_spad, src0_curr), bctx->src0_row_size_aligned, nb01, row_size_bytes, current_block_size); - dma_queue_push(dma_q, dma_make_data(s1_spad, src1_curr), bctx->src1_row_size_aligned, nb11, row_size_bytes, current_block_size); + for (uint32_t s = 1; s < n_srcs; s++) { + const struct htp_tensor * src_s = octx->src[s]; + uint32_t is3 = (src_s->ne[3] == 1) ? 0 : i03; + uint32_t is2 = (src_s->ne[2] == 1) ? 0 : i02; + uint32_t is1 = (src_s->ne[1] == 1) ? 0 : i01; + dma_addr_t s_curr = src_s->data + is3 * src_s->nb[3] + is2 * src_s->nb[2] + is1 * src_s->nb[1]; + uint8_t * s_spad = s1_spad + (s - 1) * 2 * src1_spad_half; + dma_queue_push(dma_q, dma_make_data(s_spad, s_curr), bctx->src1_row_size_aligned, src_s->nb[1], row_size_bytes, current_block_size); + } ir_prefetch += current_block_size; spad_idx ^= 1; } @@ -422,6 +427,11 @@ static void binary_thread_vector_same_shape(unsigned int nth, unsigned int ith, htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir); compute(d_spad, s0_spad, s1_spad, current_block_size, bctx->dst_row_size_aligned, bctx->src0_row_size_aligned, bctx->src1_row_size_aligned, ne00); + for (uint32_t s = 2; s < n_srcs; s++) { + uint8_t * ss_spad = (uint8_t *) dma_queue_pop(dma_q).dst; + compute(d_spad, d_spad, ss_spad, current_block_size, + bctx->dst_row_size_aligned, bctx->dst_row_size_aligned, bctx->src1_row_size_aligned, ne00); + } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir); uint32_t i03, i02, i01, rem; @@ -440,15 +450,18 @@ static void binary_thread_vector_same_shape(unsigned int nth, unsigned int ith, p02 = fastdiv(prem, &bctx->src0_dim1_div); p01 = prem - p02 * ne01; - uint32_t p13 = (ne13 == 1) ? 0 : p03; - uint32_t p12 = (ne12 == 1) ? 0 : p02; - uint32_t p11 = (ne11 == 1) ? 0 : p01; - dma_addr_t s0_next = src0->data + p03 * nb03 + p02 * nb02 + p01 * nb01; - dma_addr_t s1_next = src1->data + p13 * nb13 + p12 * nb12 + p11 * nb11; - dma_queue_push(dma_q, dma_make_data(s0_spad, s0_next), bctx->src0_row_size_aligned, nb01, row_size_bytes, next_block_size); - dma_queue_push(dma_q, dma_make_data(s1_spad, s1_next), bctx->src1_row_size_aligned, nb11, row_size_bytes, next_block_size); + + for (uint32_t s = 1; s < n_srcs; s++) { + const struct htp_tensor * src_s = octx->src[s]; + uint32_t ps3 = (src_s->ne[3] == 1) ? 0 : p03; + uint32_t ps2 = (src_s->ne[2] == 1) ? 0 : p02; + uint32_t ps1 = (src_s->ne[1] == 1) ? 0 : p01; + dma_addr_t s_next = src_s->data + ps3 * src_s->nb[3] + ps2 * src_s->nb[2] + ps1 * src_s->nb[1]; + uint8_t * s_spad = s1_spad + (s - 1) * 2 * src1_spad_half; + dma_queue_push(dma_q, dma_make_data(s_spad, s_next), bctx->src1_row_size_aligned, src_s->nb[1], row_size_bytes, next_block_size); + } ir_prefetch += next_block_size; } @@ -859,6 +872,7 @@ struct binary_chunked_context { uint32_t chunk_size; uint32_t chunks_per_thread; uint32_t total_chunks; + uint32_t n_srcs; bool is_scalar; float scalar_f32; _Float16 scalar_f16; @@ -872,7 +886,6 @@ static void binary_thread_chunked(unsigned int nth, unsigned int ith, void * dat struct binary_chunked_context * ctx = (struct binary_chunked_context *) data; struct htp_ops_context * octx = ctx->octx; const struct htp_tensor * src0 = octx->src[0]; - const struct htp_tensor * src1 = octx->src[1]; const struct htp_tensor * dst = octx->dst; const uint32_t start_chunk = ctx->chunks_per_thread * ith; @@ -895,6 +908,7 @@ static void binary_thread_chunked(unsigned int nth, unsigned int ith, void * dat uint8_t * dst_spad_base = VTCM_LAYOUT_PTR(uint8_t, ctx->vtcm_base, layout->off_dst) + (ith * layout->dst_bytes_per_thread); dma_queue * dma_q = octx->ctx->dma[ith]; + const uint32_t n_srcs = ctx->n_srcs; uint32_t prefetch_chunk = start_chunk; int spad_idx = 0; @@ -913,9 +927,12 @@ static void binary_thread_chunked(unsigned int nth, unsigned int ith, void * dat dma_queue_push(dma_q, dma_make_data(d_curr, d_spad), chunk_bytes, chunk_bytes, cur_bytes, 0); dma_queue_push(dma_q, dma_make_data(s0_spad, s0_curr), chunk_bytes, chunk_bytes, cur_bytes, 1); if (!ctx->is_scalar) { - dma_addr_t s1_curr = src1->data + (size_t) c_start * elem_size; uint8_t * s1_spad = src1_spad_base + spad_idx * chunk_bytes; - dma_queue_push(dma_q, dma_make_data(s1_spad, s1_curr), chunk_bytes, chunk_bytes, cur_bytes, 1); + for (uint32_t s = 1; s < n_srcs; s++) { + dma_addr_t s_curr = octx->src[s]->data + (size_t) c_start * elem_size; + uint8_t * s_spad = s1_spad + (s - 1) * 2 * chunk_bytes; + dma_queue_push(dma_q, dma_make_data(s_spad, s_curr), chunk_bytes, chunk_bytes, cur_bytes, 1); + } } prefetch_chunk++; @@ -943,6 +960,10 @@ static void binary_thread_chunked(unsigned int nth, unsigned int ith, void * dat } } else { ctx->compute(d_spad, s0_spad, s1_spad, cur_elems); + for (uint32_t s = 2; s < n_srcs; s++) { + uint8_t * s_spad = (uint8_t *) dma_queue_pop(dma_q).dst; + ctx->compute(d_spad, d_spad, s_spad, cur_elems); + } } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) c); @@ -958,8 +979,11 @@ static void binary_thread_chunked(unsigned int nth, unsigned int ith, void * dat dma_addr_t s0_next = src0->data + (size_t) pc_start * elem_size; dma_queue_push(dma_q, dma_make_data(s0_spad, s0_next), chunk_bytes, chunk_bytes, p_bytes, 1); if (!ctx->is_scalar) { - dma_addr_t s1_next = src1->data + (size_t) pc_start * elem_size; - dma_queue_push(dma_q, dma_make_data(s1_spad, s1_next), chunk_bytes, chunk_bytes, p_bytes, 1); + for (uint32_t s = 1; s < n_srcs; s++) { + dma_addr_t s_next = octx->src[s]->data + (size_t) pc_start * elem_size; + uint8_t * s_spad = s1_spad + (s - 1) * 2 * chunk_bytes; + dma_queue_push(dma_q, dma_make_data(s_spad, s_next), chunk_bytes, chunk_bytes, p_bytes, 1); + } } prefetch_chunk++; @@ -974,6 +998,7 @@ static int execute_op_binary(struct htp_ops_context * octx) { const struct htp_tensor * src1 = octx->src[1]; const struct htp_tensor * dst = octx->dst; const struct htp_binary_kernel_params * kparams = (const struct htp_binary_kernel_params *) octx->kernel_params; + const uint32_t n_srcs = kparams->n_srcs > 2 ? kparams->n_srcs : 2; const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; @@ -985,7 +1010,7 @@ static int execute_op_binary(struct htp_ops_context * octx) { const size_t dst_row_size = dst->ne[0] * elem_size; if (kparams->kernel_type == HTP_BINARY_KERNEL_CHUNKED) { - const bool is_scalar = kparams->is_scalar || (src1->ne[0] == 1 && src1->ne[1] == 1 && src1->ne[2] == 1 && src1->ne[3] == 1); + const bool is_scalar = kparams->is_scalar; compute_binary_chunked_t compute = NULL; compute_binary_scalar_chunked_f32_t compute_scalar_f32 = NULL; @@ -1045,12 +1070,16 @@ static int execute_op_binary(struct htp_ops_context * octx) { const uint32_t elems_per_line = (src0_type == HTP_TYPE_F32) ? 32 : 64; if (octx->ctx->mdev.count > 1) { - const bool can_split = htp_tensor_mdev_data_aligned(dst) && - htp_tensor_mdev_data_aligned(src0) && - (is_scalar || htp_tensor_mdev_data_aligned(src1)) && - htp_tensor_is_contiguous(dst, elem_size) && - htp_tensor_is_contiguous(src0, elem_size) && - (is_scalar || htp_tensor_is_contiguous(src1, elem_size)); + bool can_split = htp_tensor_mdev_data_aligned(dst) && + htp_tensor_mdev_data_aligned(src0) && + (is_scalar || htp_tensor_mdev_data_aligned(src1)) && + htp_tensor_is_contiguous(dst, elem_size) && + htp_tensor_is_contiguous(src0, elem_size) && + (is_scalar || htp_tensor_is_contiguous(src1, elem_size)); + for (uint32_t s = 2; can_split && s < n_srcs; s++) { + can_split = htp_tensor_mdev_data_aligned(octx->src[s]) && + htp_tensor_is_contiguous(octx->src[s], elem_size); + } const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( total_elems, can_split ? elems_per_line : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); @@ -1072,7 +1101,7 @@ static int execute_op_binary(struct htp_ops_context * octx) { return HTP_STATUS_VTCM_TOO_SMALL; } - const uint32_t chunk_size = kparams->chunk_size > 0 ? kparams->chunk_size : (32768 / elem_size); + const uint32_t chunk_size = kparams->chunk_size; const uint32_t total_chunks = (nelem + chunk_size - 1) / chunk_size; const uint32_t n_threads = (total_chunks >= 2) ? MIN(octx->n_threads, total_chunks) : 1; const uint32_t chunks_per_thread = (total_chunks + n_threads - 1) / n_threads; @@ -1101,6 +1130,7 @@ static int execute_op_binary(struct htp_ops_context * octx) { .chunk_size = chunk_size, .chunks_per_thread = chunks_per_thread, .total_chunks = total_chunks, + .n_srcs = n_srcs, .is_scalar = is_scalar, .scalar_f32 = scalar_f32, .scalar_f16 = scalar_f16, @@ -1146,65 +1176,6 @@ static int execute_op_binary(struct htp_ops_context * octx) { return HTP_STATUS_VTCM_TOO_SMALL; } - dma_queue * dma_q = octx->ctx->dma[0]; - uint8_t * vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src1); - if (kparams->kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { - dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), bctx.vtcm_layout.src1_size, 0, src1->ne[0] * elem_size, 1); - } else if (kparams->kernel_type == HTP_BINARY_KERNEL_SCALAR || - kparams->kernel_type == HTP_BINARY_KERNEL_REPEAT || - kparams->kernel_type == HTP_BINARY_KERNEL_COMPLEX) { - if (!kparams->src1_strided) { - const size_t src1_bytes = (size_t) src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3] * elem_size; - dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), bctx.vtcm_layout.src1_size, 0, src1_bytes, 1); - } else { - const uint32_t ne11 = src1->ne[1]; - const uint32_t ne12 = src1->ne[2]; - const uint32_t ne13 = src1->ne[3]; - const size_t row_bytes = src1->ne[0] * elem_size; - for (uint32_t i13 = 0; i13 < ne13; i13++) { - for (uint32_t i12 = 0; i12 < ne12; i12++) { - dma_addr_t src_addr = src1->data + i13 * src1->nb[3] + i12 * src1->nb[2]; - uint8_t * dst_ptr = vtcm_src1 + (i13 * ne12 * ne11 + i12 * ne11) * row_bytes; - while (!dma_queue_push(dma_q, dma_make_data(dst_ptr, src_addr), - row_bytes, src1->nb[1], row_bytes, ne11)) { - dma_queue_pop(dma_q); - } - } - } - } - } else if (kparams->kernel_type == HTP_BINARY_KERNEL_ADD_ID) { - const struct htp_tensor * src2 = octx->src[2]; - uint8_t * vtcm_src2 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src2); - dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), - kparams->src1_row_size_aligned, src1->nb[1], - src1->ne[0] * elem_size, src1->ne[1]); - const size_t src2_row_bytes = src2->ne[0] * sizeof(int32_t); - dma_queue_push(dma_q, dma_make_data(vtcm_src2, src2->data), - src2_row_bytes, src2->nb[1], - src2_row_bytes, src2->ne[1]); - } - - bctx.octx = octx; - bctx.nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); - bctx.total_rows = nrows; - bctx.row_start = row_start; - bctx.block_max = bctx.vtcm_layout.rows_per_buffer; - bctx.src0_row_size_aligned = src0_row_size_aligned; - bctx.src1_row_size_aligned = src1_row_size_aligned; - bctx.dst_row_size_aligned = dst_row_size_aligned; - bctx.row_size_bytes = src0_row_size; - - bctx.src0_dim1_div = init_fastdiv_values(src0->ne[1]); - bctx.src0_dim2_div = init_fastdiv_values(src0->ne[2]); - bctx.src0_dim12_div = init_fastdiv_values(src0->ne[1] * src0->ne[2]); - - bctx.src1_dim1_div = init_fastdiv_values(src1->ne[1]); - bctx.src1_dim2_div = init_fastdiv_values(src1->ne[2]); - bctx.src1_dim3_div = init_fastdiv_values(src1->ne[3]); - - bctx.split_at_ne01 = kparams->split_at_ne01; - bctx.split_at_ne02 = kparams->split_at_ne02; - worker_callback_t worker_func = NULL; void * compute_func = NULL; @@ -1322,7 +1293,70 @@ static int execute_op_binary(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } - bctx.compute = compute_func; + dma_queue * dma_q = octx->ctx->dma[0]; + uint8_t * vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src1); + if (kparams->kernel_type == HTP_BINARY_KERNEL_ROW_BCAST) { + dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), bctx.vtcm_layout.src1_size, 0, src1->ne[0] * elem_size, 1); + } else if (kparams->kernel_type == HTP_BINARY_KERNEL_SCALAR || + kparams->kernel_type == HTP_BINARY_KERNEL_REPEAT || + kparams->kernel_type == HTP_BINARY_KERNEL_COMPLEX) { + if (!kparams->src1_strided) { + const size_t src1_bytes = (size_t) src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3] * elem_size; + dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), bctx.vtcm_layout.src1_size, 0, src1_bytes, 1); + if (kparams->kernel_type == HTP_BINARY_KERNEL_SCALAR && octx->src[2] != NULL) { + uint8_t * vtcm_src2 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src2); + dma_queue_push(dma_q, dma_make_data(vtcm_src2, octx->src[2]->data), bctx.vtcm_layout.src2_size, 0, src1_bytes, 1); + } + } else { + const uint32_t ne11 = src1->ne[1]; + const uint32_t ne12 = src1->ne[2]; + const uint32_t ne13 = src1->ne[3]; + const size_t row_bytes = src1->ne[0] * elem_size; + for (uint32_t i13 = 0; i13 < ne13; i13++) { + for (uint32_t i12 = 0; i12 < ne12; i12++) { + dma_addr_t src_addr = src1->data + i13 * src1->nb[3] + i12 * src1->nb[2]; + uint8_t * dst_ptr = vtcm_src1 + (i13 * ne12 * ne11 + i12 * ne11) * row_bytes; + while (!dma_queue_push(dma_q, dma_make_data(dst_ptr, src_addr), + row_bytes, src1->nb[1], row_bytes, ne11)) { + dma_queue_pop(dma_q); + } + } + } + } + } else if (kparams->kernel_type == HTP_BINARY_KERNEL_ADD_ID) { + const struct htp_tensor * src2 = octx->src[2]; + uint8_t * vtcm_src2 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src2); + dma_queue_push(dma_q, dma_make_data(vtcm_src1, src1->data), + kparams->src1_row_size_aligned, src1->nb[1], + src1->ne[0] * elem_size, src1->ne[1]); + const size_t src2_row_bytes = src2->ne[0] * sizeof(int32_t); + dma_queue_push(dma_q, dma_make_data(vtcm_src2, src2->data), + src2_row_bytes, src2->nb[1], + src2_row_bytes, src2->ne[1]); + } + + bctx.octx = octx; + bctx.nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); + bctx.total_rows = nrows; + bctx.row_start = row_start; + bctx.n_srcs = n_srcs; + bctx.block_max = bctx.vtcm_layout.rows_per_buffer; + bctx.src0_row_size_aligned = src0_row_size_aligned; + bctx.src1_row_size_aligned = src1_row_size_aligned; + bctx.dst_row_size_aligned = dst_row_size_aligned; + bctx.row_size_bytes = src0_row_size; + + bctx.src0_dim1_div = kparams->div_ne01; + bctx.src0_dim2_div = kparams->div_ne02; + bctx.src0_dim12_div = kparams->div_ne012; + + bctx.src1_dim1_div = kparams->div_ne11; + bctx.src1_dim2_div = kparams->div_ne12; + bctx.src1_dim3_div = kparams->div_ne13; + + bctx.split_at_ne01 = kparams->split_at_ne01; + bctx.split_at_ne02 = kparams->split_at_ne02; + bctx.compute = compute_func; if (kparams->kernel_type == HTP_BINARY_KERNEL_ROW_BCAST || kparams->kernel_type == HTP_BINARY_KERNEL_SCALAR || @@ -1330,6 +1364,15 @@ static int execute_op_binary(struct htp_ops_context * octx) { kparams->kernel_type == HTP_BINARY_KERNEL_COMPLEX || kparams->kernel_type == HTP_BINARY_KERNEL_ADD_ID) { dma_queue_flush(dma_q); + if (kparams->kernel_type == HTP_BINARY_KERNEL_SCALAR && octx->src[2] != NULL && octx->op == HTP_OP_MUL) { + uint8_t * vtcm_src2 = VTCM_LAYOUT_PTR(uint8_t, bctx.vtcm_base, bctx.vtcm_layout.off_src2); + const uint32_t n_scalars = src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3]; + if (src0_type == HTP_TYPE_F32) { + hvx_mul_f32_aaa(vtcm_src1, vtcm_src1, vtcm_src2, n_scalars); + } else if (src0_type == HTP_TYPE_F16) { + hvx_mul_f16_aaa(vtcm_src1, vtcm_src1, vtcm_src2, n_scalars); + } + } } work_queue_run(octx->ctx->work_queue, worker_func, &bctx, n_threads); diff --git a/ggml/src/ggml-hexagon/htp/binary-ops.h b/ggml/src/ggml-hexagon/htp/binary-ops.h index db3d51489559..8c5e683e81b3 100644 --- a/ggml/src/ggml-hexagon/htp/binary-ops.h +++ b/ggml/src/ggml-hexagon/htp/binary-ops.h @@ -6,6 +6,7 @@ #include #include "hex-common.h" +#include "hex-fastdiv.h" #include "htp-ops.h" #include "htp-vtcm.h" @@ -20,7 +21,15 @@ enum htp_binary_kernel_type { }; struct htp_binary_kernel_params { - uint32_t kernel_type; + uint8_t kernel_type; + uint8_t split_at_ne01; + uint8_t split_at_ne02; + uint8_t src1_strided; + + uint8_t n_srcs; + uint8_t is_scalar; + uint8_t pad[2]; + uint32_t n_threads; uint32_t rows_per_buffer; @@ -34,12 +43,14 @@ struct htp_binary_kernel_params { uint32_t chunk_size; uint32_t chunk_bytes; - uint32_t is_scalar; - uint8_t split_at_ne01; - uint8_t split_at_ne02; - uint8_t src1_strided; - uint8_t pad; + struct fastdiv_values div_ne01; + struct fastdiv_values div_ne02; + struct fastdiv_values div_ne012; + + struct fastdiv_values div_ne11; + struct fastdiv_values div_ne12; + struct fastdiv_values div_ne13; }; #if defined(__cplusplus) @@ -100,6 +111,8 @@ static inline void htp_binary_vtcm_layout_build( return; } + const uint32_t n_srcs = kparams->n_srcs > 2 ? kparams->n_srcs : 2; + if (kparams->kernel_type == HTP_BINARY_KERNEL_CHUNKED) { const size_t chunk_bytes = kparams->chunk_bytes; if (chunk_bytes == 0) { @@ -107,7 +120,7 @@ static inline void htp_binary_vtcm_layout_build( } L->src0_bytes_per_thread = 2 * chunk_bytes; - L->src1_bytes_per_thread = kparams->is_scalar ? 0 : (2 * chunk_bytes); + L->src1_bytes_per_thread = kparams->is_scalar ? 0 : (2 * (n_srcs - 1) * chunk_bytes); L->dst_bytes_per_thread = 2 * chunk_bytes; L->src0_spad_half_size = chunk_bytes; @@ -135,7 +148,7 @@ static inline void htp_binary_vtcm_layout_build( } const size_t spad_row_total = (kparams->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) - ? 2 * (kparams->src0_row_size_aligned + kparams->src1_row_size_aligned + kparams->dst_row_size_aligned) + ? 2 * (kparams->src0_row_size_aligned + (n_srcs - 1) * kparams->src1_row_size_aligned + kparams->dst_row_size_aligned) : 2 * (kparams->src0_row_size_aligned + kparams->dst_row_size_aligned); const size_t static_vtcm_size = kparams->src1_size + kparams->src2_size; @@ -143,7 +156,9 @@ static inline void htp_binary_vtcm_layout_build( return; } - const size_t rows_per_buffer = (vtcm_size - static_vtcm_size) / (n_threads * spad_row_total); + const size_t rows_per_buffer = (kparams->rows_per_buffer > 0) + ? kparams->rows_per_buffer + : (vtcm_size - static_vtcm_size) / (n_threads * spad_row_total); if (rows_per_buffer == 0) { return; } @@ -155,11 +170,13 @@ static inline void htp_binary_vtcm_layout_build( L->src0_bytes_per_thread = rows_per_buffer * 2 * kparams->src0_row_size_aligned; L->dst_bytes_per_thread = rows_per_buffer * 2 * kparams->dst_row_size_aligned; L->src1_bytes_per_thread = (kparams->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) - ? rows_per_buffer * 2 * kparams->src1_row_size_aligned + ? rows_per_buffer * 2 * (n_srcs - 1) * kparams->src1_row_size_aligned : 0; L->src0_spad_half_size = L->src0_bytes_per_thread / 2; - L->src1_spad_half_size = L->src1_bytes_per_thread / 2; + L->src1_spad_half_size = (kparams->kernel_type == HTP_BINARY_KERNEL_SAME_SHAPE) + ? rows_per_buffer * kparams->src1_row_size_aligned + : 0; L->dst_spad_half_size = L->dst_bytes_per_thread / 2; const size_t src0_total = n_threads * L->src0_bytes_per_thread; @@ -178,4 +195,53 @@ static inline void htp_binary_vtcm_layout_build( L->total_bytes = off; } +static inline bool htp_binary_solve_chunked( + struct htp_binary_vtcm_layout * L, + struct htp_binary_kernel_params * kparams, + uint32_t total_elems, + uint32_t elem_size, + uint32_t max_threads, + uint32_t n_srcs, + bool is_scalar, + size_t vtcm_size +) { + const size_t n_bufs = is_scalar ? 2 : (size_t) n_srcs + 1; + const size_t scalar_bytes = is_scalar ? 128 : 0; + const size_t budget_per_buf = (max_threads > 0 && vtcm_size > scalar_bytes) + ? hex_align_down((vtcm_size - scalar_bytes) / (2 * max_threads * n_bufs), 128) + : 0; + const uint32_t max_chunk_bytes = (budget_per_buf > 0 && budget_per_buf < 32768) ? (uint32_t) budget_per_buf : 32768u; + const uint32_t max_chunk_elems = max_chunk_bytes / elem_size; + if (max_chunk_elems == 0) { + return false; + } + + const uint32_t min_chunk_elems = 256 < max_chunk_elems ? 256 : max_chunk_elems; + const uint32_t target_chunk_elems = hex_round_up((total_elems + (2 * max_threads) - 1) / (2 * max_threads), 32); + const uint32_t chunk_size = (target_chunk_elems < min_chunk_elems) ? min_chunk_elems + : (target_chunk_elems > max_chunk_elems) ? max_chunk_elems + : target_chunk_elems; + const uint32_t chunk_bytes = hex_round_up(chunk_size * elem_size, 128); + const uint32_t total_chunks = (total_elems + chunk_size - 1) / chunk_size; + const uint32_t n_threads = (total_chunks >= 2) ? (max_threads < total_chunks ? max_threads : total_chunks) : 1; + + kparams->kernel_type = HTP_BINARY_KERNEL_CHUNKED; + kparams->n_threads = n_threads; + kparams->n_srcs = (uint8_t) n_srcs; + kparams->rows_per_buffer = 1; + kparams->src1_row_size_aligned = is_scalar ? 0 : kparams->src0_row_size_aligned; + kparams->src1_size = 0; + kparams->chunk_size = chunk_size; + kparams->chunk_bytes = chunk_bytes; + kparams->is_scalar = is_scalar ? 1 : 0; + + htp_binary_vtcm_layout_build(L, kparams, vtcm_size); + if (L->total_bytes == 0 || L->total_bytes > vtcm_size) { + return false; + } + + kparams->vtcm_size = (uint32_t) L->total_bytes; + return true; +} + #endif diff --git a/ggml/src/ggml-hexagon/htp/concat-ops.c b/ggml/src/ggml-hexagon/htp/concat-ops.c index 40fa09151b69..8f3e199c252e 100644 --- a/ggml/src/ggml-hexagon/htp/concat-ops.c +++ b/ggml/src/ggml-hexagon/htp/concat-ops.c @@ -47,87 +47,108 @@ static void concat_2d_f32_transposed(unsigned int nth, unsigned int ith, void * const uint32_t src0_ne0 = src0->ne[0]; const uint32_t src1_ne0 = src1->ne[0]; - const uint32_t row_end = cctx->row_start + cctx->nrows; - const uint32_t start_i = cctx->row_start + ith * cctx->nrows_per_thread; - const uint32_t end_i = (start_i + cctx->nrows_per_thread < row_end) ? (start_i + cctx->nrows_per_thread) : row_end; - if (start_i >= end_i) return; + // dst rows [row_begin, row_end) of this thread; a dst row is a src0 row followed by a src1 column + const uint32_t row_begin = cctx->row_start + ith * cctx->nrows_per_thread; + const uint32_t row_end = MIN(row_begin + cctx->nrows_per_thread, cctx->row_start + cctx->nrows); + if (row_begin >= row_end) return; dma_queue * dma_q = octx->ctx->dma[ith]; + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - uint8_t * spad0_base = cctx->spad0_base + ith * cctx->spad0_size_per_thread; - uint8_t * spad1_base = cctx->spad1_base + ith * cctx->spad1_size_per_thread; + const struct fastdiv_values * div_ne2 = &cctx->div_ne2; + const uint32_t ne2 = dst->ne[2]; - const uint32_t block_i = 32; - const uint32_t spad1_stride = block_i * sizeof(float); + // tile: block_rows dst rows x block_cols src1 columns + const uint32_t block_rows = 128; + const uint32_t block_cols = 256; + // +1 element spreads the gather lanes across VTCM, so they do not serialize on one path + const uint32_t spad1_stride = block_rows * sizeof(float) + sizeof(float); const HVX_Vector offsets = hvx_vec_gather_offsets_w(spad1_stride); - const uint32_t src1_ne0_padded = hex_round_up(src1_ne0, 32); - const uint32_t src0_row_bytes = src0_ne0 * sizeof(float); - const uint32_t src0_row_padded = hex_round_up(src0_row_bytes, VLEN); - const uint32_t src0_pre = src0_row_padded - src0_row_bytes; - const uint32_t spad0_row_bytes = src0_row_padded + src1_ne0_padded * sizeof(float); + const uint32_t block_cols_padded = MIN(hex_round_up(src1_ne0, 32), block_cols); + const uint32_t src0_row_bytes = src0_ne0 * sizeof(float); + const uint32_t src0_row_padded = hex_round_up(src0_row_bytes, VLEN); + const uint32_t src0_pre = src0_row_padded - src0_row_bytes; + const uint32_t spad0_stride = src0_row_padded + block_cols_padded * sizeof(float); - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - - const struct fastdiv_values * div_ne2 = &cctx->div_ne2; - const uint32_t ne2 = dst->ne[2]; + // two slots per scratchpad: tile b gathers in slot b&1 while dst[b-1] and src1[b+1] DMA in the other + uint8_t * spad0_base = cctx->spad0_base + ith * cctx->spad0_size_per_thread; + uint8_t * spad1_base = cctx->spad1_base + ith * cctx->spad1_size_per_thread; + const uint32_t spad0_slot = block_rows * spad0_stride; + const uint32_t spad1_slot = block_cols_padded * spad1_stride; - uint32_t p = 0; - uint32_t i = start_i; + // tiles walk (plane, row, col) with col fastest; src0 goes out with the col == 0 tile only + uint32_t plane = 0; + uint32_t row = row_begin; + uint32_t col = 0; + uint32_t slot = 0; + bool dst_pending = false; - const dma_addr_t src1_addr = concat_plane_addr(src1, p, div_ne2, ne2) + i * src1->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad1_base, src1_addr), spad1_stride, src1->nb[0], MIN(end_i - i, block_i) * sizeof(float), src1_ne0); + const dma_addr_t src1_addr = concat_plane_addr(src1, plane, div_ne2, ne2) + row * src1->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad1_base, src1_addr), spad1_stride, src1->nb[0], MIN(row_end - row, block_rows) * sizeof(float), MIN(src1_ne0, block_cols)); - const dma_addr_t src0_addr = concat_plane_addr(src0, p, div_ne2, ne2) + i * src0->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, src0_addr), spad0_row_bytes, src0->nb[1], src0_row_bytes, MIN(end_i - i, block_i)); + const dma_addr_t src0_addr = concat_plane_addr(src0, plane, div_ne2, ne2) + row * src0->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, src0_addr), spad0_stride, src0->nb[1], src0_row_bytes, MIN(row_end - row, block_rows)); - dma_queue_pop(dma_q); // src1 + while (plane < cctx->nplanes) { + const uint32_t nrows = MIN(row_end - row, block_rows); + const uint32_t ncols = MIN(src1_ne0 - col, block_cols); - while (p < cctx->nplanes) { - const uint32_t current_block_i = MIN(end_i - i, block_i); + uint8_t * spad0 = spad0_base + slot * spad0_slot; + uint8_t * spad1 = spad1_base + slot * spad1_slot; - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); - for (uint32_t j = 0; j < src1_ne0; j += 32) { - const uint8_t * src_ptr = spad1_base + j * spad1_stride; - uint8_t * dst_ptr = spad0_base + src0_row_padded + j * sizeof(float); - hvx_transpose_32x32_w_gather(dst_ptr, spad0_row_bytes, src_ptr, spad1_stride, offsets, current_block_i, MIN(src1_ne0 - j, 32)); + dma_queue_pop(dma_q); // src1 + if (col == 0) { + dma_queue_pop(dma_q); // src0 } - hvx_gather_sync(spad0_base + src0_row_padded); - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); - - uint32_t np = p; - uint32_t ni = i + block_i; - if (ni >= end_i) { - ni = start_i; - np++; + + uint32_t next_plane = plane; + uint32_t next_row = row; + uint32_t next_col = col + block_cols; + if (next_col >= src1_ne0) { + next_col = 0; + next_row = row + block_rows; + if (next_row >= row_end) { + next_row = row_begin; + next_plane++; + } } - const bool has_next = np < cctx->nplanes; - const uint32_t next_block_i = MIN(end_i - ni, block_i); + const bool has_next = next_plane < cctx->nplanes; + const uint32_t next_nrows = MIN(row_end - next_row, block_rows); + const uint32_t next_ncols = MIN(src1_ne0 - next_col, block_cols); - // spad1 is free after the gather sync, prefetch next src1 ahead of the dst write + // other spad1 slot is free since the previous gather sync if (has_next) { - const dma_addr_t nsrc1_addr = concat_plane_addr(src1, np, div_ne2, ne2) + ni * src1->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad1_base, nsrc1_addr), spad1_stride, src1->nb[0], next_block_i * sizeof(float), src1_ne0); + const dma_addr_t addr = concat_plane_addr(src1, next_plane, div_ne2, ne2) + next_row * src1->nb[1] + next_col * src1->nb[0]; + dma_queue_push(dma_q, dma_make_data(spad1_base + (slot ^ 1) * spad1_slot, addr), spad1_stride, src1->nb[0], next_nrows * sizeof(float), next_ncols); } - dma_queue_pop(dma_q); // src0 - - const dma_addr_t dst_addr = concat_plane_addr(dst, p, div_ne2, ne2) + i * dst->nb[1]; - dma_queue_push(dma_q, dma_make_data(dst_addr, spad0_base + src0_pre), dst->nb[1], spad0_row_bytes, (src0_ne0 + src1_ne0) * sizeof(float), current_block_i); - - if (has_next) { - dma_queue_pop(dma_q); // next src1 + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) row); + for (uint32_t c = 0; c < ncols; c += 32) { + hvx_transpose_32x32_w_gather(spad0 + src0_row_padded + c * sizeof(float), spad0_stride, spad1 + c * spad1_stride, spad1_stride, offsets, nrows, MIN(ncols - c, 32)); } - dma_queue_pop(dma_q); // dst + hvx_gather_sync(spad0 + src0_row_padded); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) row); - // spad0 is free after the dst write - if (has_next) { - const dma_addr_t nsrc0_addr = concat_plane_addr(src0, np, div_ne2, ne2) + ni * src0->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, nsrc0_addr), spad0_row_bytes, src0->nb[1], src0_row_bytes, next_block_i); + // other spad0 slot is free once dst[b-1] is written + if (dst_pending) { + dma_queue_pop(dma_q); // dst } + if (has_next && next_col == 0) { + const dma_addr_t addr = concat_plane_addr(src0, next_plane, div_ne2, ne2) + next_row * src0->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad0_base + (slot ^ 1) * spad0_slot + src0_pre, addr), spad0_stride, src0->nb[1], src0_row_bytes, next_nrows); + } + + // the col == 0 tile also carries the src0 columns in front + const uint32_t lead = (col == 0) ? src0_row_bytes : 0; + const dma_addr_t dst_addr = concat_plane_addr(dst, plane, div_ne2, ne2) + row * dst->nb[1] + src0_row_bytes + col * sizeof(float) - lead; + dma_queue_push(dma_q, dma_make_data(dst_addr, spad0 + src0_row_padded - lead), dst->nb[1], spad0_stride, lead + ncols * sizeof(float), nrows); + dst_pending = true; - p = np; - i = ni; + plane = next_plane; + row = next_row; + col = next_col; + slot ^= 1; } dma_queue_flush(dma_q); } @@ -143,87 +164,108 @@ static void concat_2d_f16_transposed(unsigned int nth, unsigned int ith, void * const uint32_t src0_ne0 = src0->ne[0]; const uint32_t src1_ne0 = src1->ne[0]; - const uint32_t row_end = cctx->row_start + cctx->nrows; - const uint32_t start_i = cctx->row_start + ith * cctx->nrows_per_thread; - const uint32_t end_i = (start_i + cctx->nrows_per_thread < row_end) ? (start_i + cctx->nrows_per_thread) : row_end; - if (start_i >= end_i) return; + // dst rows [row_begin, row_end) of this thread; a dst row is a src0 row followed by a src1 column + const uint32_t row_begin = cctx->row_start + ith * cctx->nrows_per_thread; + const uint32_t row_end = MIN(row_begin + cctx->nrows_per_thread, cctx->row_start + cctx->nrows); + if (row_begin >= row_end) return; dma_queue * dma_q = octx->ctx->dma[ith]; + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - uint8_t * spad0_base = cctx->spad0_base + ith * cctx->spad0_size_per_thread; - uint8_t * spad1_base = cctx->spad1_base + ith * cctx->spad1_size_per_thread; + const struct fastdiv_values * div_ne2 = &cctx->div_ne2; + const uint32_t ne2 = dst->ne[2]; - const uint32_t block_i = 64; - const uint32_t spad1_stride = block_i * sizeof(__fp16); + // tile: block_rows dst rows x block_cols src1 columns + const uint32_t block_rows = 128; + const uint32_t block_cols = 512; + // +1 element spreads the gather lanes across VTCM, so they do not serialize on one path + const uint32_t spad1_stride = block_rows * sizeof(__fp16) + sizeof(__fp16); const HVX_Vector offsets = hvx_vec_gather_offsets_h(spad1_stride); - const uint32_t src1_ne0_padded = hex_round_up(src1_ne0, 64); - const uint32_t src0_row_bytes = src0_ne0 * sizeof(__fp16); - const uint32_t src0_row_padded = hex_round_up(src0_row_bytes, VLEN); - const uint32_t src0_pre = src0_row_padded - src0_row_bytes; - const uint32_t spad0_row_bytes = src0_row_padded + src1_ne0_padded * sizeof(__fp16); + const uint32_t block_cols_padded = MIN(hex_round_up(src1_ne0, 64), block_cols); + const uint32_t src0_row_bytes = src0_ne0 * sizeof(__fp16); + const uint32_t src0_row_padded = hex_round_up(src0_row_bytes, VLEN); + const uint32_t src0_pre = src0_row_padded - src0_row_bytes; + const uint32_t spad0_stride = src0_row_padded + block_cols_padded * sizeof(__fp16); - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - - const struct fastdiv_values * div_ne2 = &cctx->div_ne2; - const uint32_t ne2 = dst->ne[2]; + // two slots per scratchpad: tile b gathers in slot b&1 while dst[b-1] and src1[b+1] DMA in the other + uint8_t * spad0_base = cctx->spad0_base + ith * cctx->spad0_size_per_thread; + uint8_t * spad1_base = cctx->spad1_base + ith * cctx->spad1_size_per_thread; + const uint32_t spad0_slot = block_rows * spad0_stride; + const uint32_t spad1_slot = block_cols_padded * spad1_stride; - uint32_t p = 0; - uint32_t i = start_i; + // tiles walk (plane, row, col) with col fastest; src0 goes out with the col == 0 tile only + uint32_t plane = 0; + uint32_t row = row_begin; + uint32_t col = 0; + uint32_t slot = 0; + bool dst_pending = false; - const dma_addr_t src1_addr = concat_plane_addr(src1, p, div_ne2, ne2) + i * src1->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad1_base, src1_addr), spad1_stride, src1->nb[0], MIN(end_i - i, block_i) * sizeof(__fp16), src1_ne0); + const dma_addr_t src1_addr = concat_plane_addr(src1, plane, div_ne2, ne2) + row * src1->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad1_base, src1_addr), spad1_stride, src1->nb[0], MIN(row_end - row, block_rows) * sizeof(__fp16), MIN(src1_ne0, block_cols)); - const dma_addr_t src0_addr = concat_plane_addr(src0, p, div_ne2, ne2) + i * src0->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, src0_addr), spad0_row_bytes, src0->nb[1], src0_row_bytes, MIN(end_i - i, block_i)); + const dma_addr_t src0_addr = concat_plane_addr(src0, plane, div_ne2, ne2) + row * src0->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, src0_addr), spad0_stride, src0->nb[1], src0_row_bytes, MIN(row_end - row, block_rows)); - dma_queue_pop(dma_q); // src1 + while (plane < cctx->nplanes) { + const uint32_t nrows = MIN(row_end - row, block_rows); + const uint32_t ncols = MIN(src1_ne0 - col, block_cols); - while (p < cctx->nplanes) { - const uint32_t current_block_i = MIN(end_i - i, block_i); + uint8_t * spad0 = spad0_base + slot * spad0_slot; + uint8_t * spad1 = spad1_base + slot * spad1_slot; - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); - for (uint32_t j = 0; j < src1_ne0; j += 64) { - const uint8_t * src_ptr = spad1_base + j * spad1_stride; - uint8_t * dst_ptr = spad0_base + src0_row_padded + j * sizeof(__fp16); - hvx_transpose_64x64_h_gather(dst_ptr, spad0_row_bytes, src_ptr, spad1_stride, offsets, current_block_i, MIN(src1_ne0 - j, 64)); + dma_queue_pop(dma_q); // src1 + if (col == 0) { + dma_queue_pop(dma_q); // src0 } - hvx_gather_sync(spad0_base + src0_row_padded); - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); - - uint32_t np = p; - uint32_t ni = i + block_i; - if (ni >= end_i) { - ni = start_i; - np++; + + uint32_t next_plane = plane; + uint32_t next_row = row; + uint32_t next_col = col + block_cols; + if (next_col >= src1_ne0) { + next_col = 0; + next_row = row + block_rows; + if (next_row >= row_end) { + next_row = row_begin; + next_plane++; + } } - const bool has_next = np < cctx->nplanes; - const uint32_t next_block_i = MIN(end_i - ni, block_i); + const bool has_next = next_plane < cctx->nplanes; + const uint32_t next_nrows = MIN(row_end - next_row, block_rows); + const uint32_t next_ncols = MIN(src1_ne0 - next_col, block_cols); - // spad1 is free after the gather sync, prefetch next src1 ahead of the dst write + // other spad1 slot is free since the previous gather sync if (has_next) { - const dma_addr_t nsrc1_addr = concat_plane_addr(src1, np, div_ne2, ne2) + ni * src1->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad1_base, nsrc1_addr), spad1_stride, src1->nb[0], next_block_i * sizeof(__fp16), src1_ne0); + const dma_addr_t addr = concat_plane_addr(src1, next_plane, div_ne2, ne2) + next_row * src1->nb[1] + next_col * src1->nb[0]; + dma_queue_push(dma_q, dma_make_data(spad1_base + (slot ^ 1) * spad1_slot, addr), spad1_stride, src1->nb[0], next_nrows * sizeof(__fp16), next_ncols); } - dma_queue_pop(dma_q); // src0 - - const dma_addr_t dst_addr = concat_plane_addr(dst, p, div_ne2, ne2) + i * dst->nb[1]; - dma_queue_push(dma_q, dma_make_data(dst_addr, spad0_base + src0_pre), dst->nb[1], spad0_row_bytes, (src0_ne0 + src1_ne0) * sizeof(__fp16), current_block_i); - - if (has_next) { - dma_queue_pop(dma_q); // next src1 + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) row); + for (uint32_t c = 0; c < ncols; c += 64) { + hvx_transpose_64x64_h_gather(spad0 + src0_row_padded + c * sizeof(__fp16), spad0_stride, spad1 + c * spad1_stride, spad1_stride, offsets, nrows, MIN(ncols - c, 64)); } - dma_queue_pop(dma_q); // dst + hvx_gather_sync(spad0 + src0_row_padded); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) row); - // spad0 is free after the dst write - if (has_next) { - const dma_addr_t nsrc0_addr = concat_plane_addr(src0, np, div_ne2, ne2) + ni * src0->nb[1]; - dma_queue_push(dma_q, dma_make_data(spad0_base + src0_pre, nsrc0_addr), spad0_row_bytes, src0->nb[1], src0_row_bytes, next_block_i); + // other spad0 slot is free once dst[b-1] is written + if (dst_pending) { + dma_queue_pop(dma_q); // dst } + if (has_next && next_col == 0) { + const dma_addr_t addr = concat_plane_addr(src0, next_plane, div_ne2, ne2) + next_row * src0->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad0_base + (slot ^ 1) * spad0_slot + src0_pre, addr), spad0_stride, src0->nb[1], src0_row_bytes, next_nrows); + } + + // the col == 0 tile also carries the src0 columns in front + const uint32_t lead = (col == 0) ? src0_row_bytes : 0; + const dma_addr_t dst_addr = concat_plane_addr(dst, plane, div_ne2, ne2) + row * dst->nb[1] + src0_row_bytes + col * sizeof(__fp16) - lead; + dma_queue_push(dma_q, dma_make_data(dst_addr, spad0 + src0_row_padded - lead), dst->nb[1], spad0_stride, lead + ncols * sizeof(__fp16), nrows); + dst_pending = true; - p = np; - i = ni; + plane = next_plane; + row = next_row; + col = next_col; + slot ^= 1; } dma_queue_flush(dma_q); } @@ -294,22 +336,21 @@ static int concat_transposed(struct htp_ops_context * octx, const struct htp_con const uint32_t n_threads = octx->n_threads; - // layout precomputed on host; kept for reference: - // struct htp_concat_transposed_vtcm_layout layout; - // htp_concat_transposed_vtcm_layout_build(&layout, octx->src[0]->ne[0], octx->src[1]->ne[0], type_size, n_threads); + struct htp_concat_transposed_vtcm_layout layout; + htp_concat_transposed_vtcm_layout_build(&layout, octx->src[0]->ne[0], octx->src[1]->ne[0], type_size, n_threads); uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; struct htp_concat_context cctx; cctx.octx = octx; - cctx.spad0_base = vtcm_base; - cctx.spad1_base = vtcm_base + n_threads * kparams->u.transposed.spad0_size_per_thread; - cctx.spad0_size_per_thread = kparams->u.transposed.spad0_size_per_thread; - cctx.spad1_size_per_thread = kparams->u.transposed.spad1_size_per_thread; + cctx.spad0_base = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, layout.off_spad0); + cctx.spad1_base = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, layout.off_spad1); + cctx.spad0_size_per_thread = layout.src0_spad_size_per_thread; + cctx.spad1_size_per_thread = layout.src1_spad_size_per_thread; cctx.row_start = row_start; cctx.nrows = nrows; cctx.nplanes = dst->ne[2] * dst->ne[3]; - cctx.div_ne2 = init_fastdiv_values(dst->ne[2]); + cctx.div_ne2 = kparams->u.transposed.div_ne2; cctx.nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); work_queue_func_t worker_func = (type_size == 4) ? concat_2d_f32_transposed : concat_2d_f16_transposed; diff --git a/ggml/src/ggml-hexagon/htp/concat-ops.h b/ggml/src/ggml-hexagon/htp/concat-ops.h index 4bfba9894af5..1f07444349bf 100644 --- a/ggml/src/ggml-hexagon/htp/concat-ops.h +++ b/ggml/src/ggml-hexagon/htp/concat-ops.h @@ -2,6 +2,8 @@ #define HTP_CONCAT_OPS_H #include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-vtcm.h" #include "gather-rows.h" #include @@ -13,8 +15,7 @@ enum htp_concat_kernel_type { }; struct htp_concat_transposed_params { - uint32_t spad0_size_per_thread; - uint32_t spad1_size_per_thread; + struct fastdiv_values div_ne2; }; struct htp_concat_kernel_params { @@ -40,24 +41,34 @@ _Static_assert(sizeof(struct htp_concat_kernel_params) <= 128, "htp_concat_kerne struct htp_concat_transposed_vtcm_layout { uint32_t src0_spad_size_per_thread; uint32_t src1_spad_size_per_thread; + size_t off_spad0; + size_t off_spad1; uint32_t total_bytes; }; static inline void htp_concat_transposed_vtcm_layout_build( - struct htp_concat_transposed_vtcm_layout * layout, + struct htp_concat_transposed_vtcm_layout * L, uint32_t src0_ne0, uint32_t src1_ne0, uint32_t type_size, uint32_t n_threads) { - uint32_t block_i = (type_size == 4) ? 32 : 64; - uint32_t spad1_stride = block_i * type_size; - uint32_t src1_ne0_padded = hex_round_up(src1_ne0, block_i); - uint32_t spad0_row_bytes = hex_round_up(src0_ne0 * type_size, 128) + src1_ne0_padded * type_size; + // src1_ne0 is processed in chunks of block_cols tokens, so VTCM does not grow with the batch + uint32_t block_rows = 128; + uint32_t block_cols = (type_size == 4) ? 256 : 512; + // +1 element spreads the gather lanes across VTCM, so they do not serialize on one path + uint32_t spad1_stride = block_rows * type_size + type_size; + uint32_t block_cols_padded = MIN(hex_round_up(src1_ne0, (type_size == 4) ? 32 : 64), block_cols); + uint32_t spad0_row_bytes = hex_round_up(src0_ne0 * type_size, 128) + block_cols_padded * type_size; - layout->src0_spad_size_per_thread = block_i * spad0_row_bytes; - layout->src1_spad_size_per_thread = src1_ne0_padded * spad1_stride; - layout->total_bytes = n_threads * (layout->src0_spad_size_per_thread + layout->src1_spad_size_per_thread); + // double-buffered: two slots per thread + L->src0_spad_size_per_thread = 2 * block_rows * spad0_row_bytes; + L->src1_spad_size_per_thread = 2 * block_cols_padded * spad1_stride; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_spad0, (size_t) n_threads * L->src0_spad_size_per_thread); + VTCM_LAYOUT_ALLOC(off, off_spad1, (size_t) n_threads * L->src1_spad_size_per_thread); + L->total_bytes = (uint32_t) off; } #endif // HTP_CONCAT_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/conv2d-ops.c b/ggml/src/ggml-hexagon/htp/conv2d-ops.c new file mode 100644 index 000000000000..42e70e089640 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/conv2d-ops.c @@ -0,0 +1,3177 @@ +#pragma clang diagnostic ignored "-Wunused-variable" +#pragma clang diagnostic ignored "-Wunused-function" + +#include +#include +#include + +#define GGML_COMMON_DECL_C +#include "ggml-common.h" +#include "conv2d-ops.h" +#include "dma-copy.h" +#include "dma-queue.h" +#include "hex-common.h" +#include "hex-fastdiv.h" +#include "hex-profile.h" +#include "htp-ctx.h" +#include "htp-ops.h" +#include "htp-tensor.h" +#include "htp-vtcm.h" +#include "hvx-base.h" +#include "hvx-copy.h" +#include "hvx-reduce.h" +#include "hmx-queue.h" +#include "hmx-utils.h" + +// fp16 elements between the HMX scales of two row tiles +#define CONV2D_HMX_SCALES_N (HTP_CONV2D_HMX_SCALES_SIZE / sizeof(__fp16)) + +struct htp_conv2d_hmx_task { + __fp16 * output; + const __fp16 * kernel_tiles; + const __fp16 * patch_tiles; + const __fp16 * scales; + uint32_t n_row_tiles; + uint32_t n_col_tiles; + uint32_t n_dot_tiles; +}; + +// hvx_vec_f32_to_f16_shuff() on v81 turns an exact 0 into 2^-24, which shows up as a nonzero conv output where the result is 0 +static inline HVX_Vector conv2d_f32_to_f16_shuff_z(HVX_Vector v0, HVX_Vector v1, HVX_Vector zero) { + const HVX_Vector q0 = Q6_Vqf32_vadd_VsfVsf(v0, zero); + const HVX_Vector q1 = Q6_Vqf32_vadd_VsfVsf(v1, zero); + return Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(q1, q0)); +} + +static inline HVX_Vector conv2d_f32_to_f16_shuff(HVX_Vector v0, HVX_Vector v1) { + return conv2d_f32_to_f16_shuff_z(v0, v1, Q6_V_vzero()); +} + +static inline HVX_Vector conv2d_f32_to_f16(HVX_Vector v0, HVX_Vector v1) { + return Q6_Vh_vdeal_Vh(conv2d_f32_to_f16_shuff(v0, v1)); +} + +// v if keep, else 0. Loops with transposes use this for padding rows: a hoisted zero vector would spill. +static inline HVX_Vector conv2d_keep(HVX_Vector v, bool keep) { + return Q6_V_vand_VV(v, Q6_V_vsplat_R(keep ? ~0u : 0)); +} + +// HMX output scale of one row tile: 2^-e with 2^e >= K * max|w|, so the fp16 result |y| * 2^-e <= max|x| does not overflow +static void conv2d_hmx_rt_scale(__fp16 * scales, const __fp16 * w, uint32_t n_tiles, uint32_t K) { + const HVX_Vector * v = (const HVX_Vector *) w; + const uint32_t n = n_tiles * (HMX_FP16_TILE_N_ELMS / 64); + + // |w| fp16 bits compare like unsigned ints + HVX_Vector m = Q6_V_vzero(); + for (uint32_t i = 0; i < n; i++) { + m = Q6_Vuh_vmax_VuhVuh(m, hvx_vec_abs_f16(v[i])); + } + m = hvx_vec_reduce_max_f16(m); + + // every lane holds the max, convert on HVX to avoid a scalar fp16 promotion + union { uint32_t u; float f; } wmax = { .u = Q6_R_vextract_VR(Q6_V_lo_W(hvx_vec_f16_to_f32(m)), 0) }; + union { float f; uint32_t u; } bound = { .f = (float) K * wmax.f }; + + int32_t e = (int32_t) (bound.u >> 23) - 127 + ((bound.u & 0x7fffff) != 0); + e = MAX(0, MIN(e, 24)); + + // 2^-e in fp16, subnormal below 2^-14 + const uint32_t s16 = e <= 14 ? (uint32_t) (15 - e) << 10 : 1u << (24 - e); + hmx_init_column_scales(scales, Q6_V_vsplat_R(s16)); +} + +// f32 splat of 1 / scale of row tile rt. The scale is 2^-e, so decode e from its fp16 bits (subnormal for e > 14). +static inline HVX_Vector conv2d_hmx_rt_restore(const __fp16 * scales, uint32_t rt) { + const uint32_t s16 = Q6_R_vextract_VR(*(const HVX_Vector *) (scales + (size_t) rt * CONV2D_HMX_SCALES_N), 0) & 0xffff; + const uint32_t e = s16 >= 0x400 ? 15 - (s16 >> 10) : 24 - (31 - __builtin_clz(s16)); + return Q6_V_vsplat_R((127 + e) << 23); +} + +// Output rows [*row_base, *row_base + *n_rows) of N * OH for this device. +// The output is written by DMA only, so device ranges need no cache line alignment. +static void conv2d_mdev_rows(const struct htp_ops_context * octx, uint32_t * row_base, uint32_t * n_rows) { + *row_base = 0; + *n_rows = octx->dst->ne[3] * octx->dst->ne[1]; + if (octx->ctx->mdev.count > 1) { + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( + *n_rows, 1, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + *row_base = range.start; + *n_rows = range.count; + } +} + +static void conv2d_hmx_worker(void * data) { + struct htp_conv2d_hmx_task * task = (struct htp_conv2d_hmx_task *) data; + + const size_t dot_stride = task->n_dot_tiles * HMX_FP16_TILE_N_ELMS; + + for (uint32_t r = 0; r < task->n_row_tiles; ++r) { + asm volatile(HMX_SET_BIAS("%0") :: "r"((unsigned int) (task->scales + r * CONV2D_HMX_SCALES_N))); + + const __fp16 * row_base = task->kernel_tiles + r * dot_stride; + const __fp16 * col_base = task->patch_tiles; + __fp16 * out_tile = task->output + r * task->n_col_tiles * HMX_FP16_TILE_N_ELMS; + + for (uint32_t c = 0; c < task->n_col_tiles; ++c) { + const __fp16 * row_tiles = row_base; + const __fp16 * col_tiles = col_base; + asm volatile(HMX_CLRACC_F16()); + + uint32_t rem = task->n_dot_tiles; + while (rem > 0) { + const uint32_t n_tiles = MIN(rem, 32); + const uint32_t range = 2048u * n_tiles - 1; + asm volatile(HMX_LOAD_MPY_DEEP_F16("%1", "%2", "%0") : : "r"(range), "r"(row_tiles), "r"(col_tiles)); + row_tiles += n_tiles * HMX_FP16_TILE_N_ELMS; + col_tiles += n_tiles * HMX_FP16_TILE_N_ELMS; + rem -= n_tiles; + } + + asm volatile(HMX_STORE_AFTER_F16("%0", "%1") : : "r"(out_tile), "r"(0) : "memory"); + col_base += dot_stride; + out_tile += HMX_FP16_TILE_N_ELMS; + } + } +} + +struct htp_conv2d_hmx_context { + struct htp_ops_context * octx; + const struct htp_conv2d_kernel_params * kp; + struct htp_conv2d_vtcm_layout layout; + __fp16 * scales; // [rt] HMX scales + __fp16 * w_tiles; + __fp16 * act[2]; + __fp16 * out[2]; + uint8_t * thr_base; + uint32_t t_base; + uint32_t t_end; + uint32_t rt0; + uint32_t n_rt; + int32_t pack_chunk; + int32_t unpack_chunk; + uint32_t pack_tpt; + uint32_t unpack_tpt; +}; + +// col tiles [t0, t1) of chunk c for thread ith, returns first col tile of the chunk +static inline uint32_t conv2d_hmx_chunk_range(const struct htp_conv2d_hmx_context * hc, uint32_t c, uint32_t tpt, + uint32_t ith, uint32_t * t0, uint32_t * t1) { + const uint32_t cs = hc->t_base + c * hc->kp->ct_chunk; + const uint32_t ce = MIN(cs + hc->kp->ct_chunk, hc->t_end); + *t0 = MIN(cs + ith * tpt, ce); + *t1 = MIN(*t0 + tpt, ce); + return cs; +} + +static void conv2d_hmx_wpack_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_hmx_context * hc = (const struct htp_conv2d_hmx_context *) data; + struct htp_ops_context * octx = hc->octx; + const struct htp_conv2d_kernel_params * kp = hc->kp; + const struct htp_tensor * kernel = octx->src[0]; + + const uint32_t Cout = kernel->ne[3]; + const uint32_t K = kp->tiled.k_size; + const uint32_t k_pad = kp->tiled.n_k_tiles * HMX_FP16_TILE_N_COLS; + const uint32_t WK = kp->tiled.wk_chunk; + const bool is_f16 = kernel->type == HTP_TYPE_F16; + const uint32_t es = is_f16 ? sizeof(__fp16) : sizeof(float); + + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * thr = hc->thr_base + (size_t) ith * kp->thr_size; + const size_t w_buf_size = (size_t) WK * 32 * sizeof(__fp16); + const size_t w_raw_size = (size_t) WK * 32 * sizeof(float); + const size_t w_step = w_buf_size + w_raw_size; + + __fp16 * wbuf[2] = { (__fp16 *) thr, (__fp16 *) (thr + w_step) }; + float * wraw[2] = { (float *) ((uint8_t *) wbuf[0] + w_buf_size), + (float *) ((uint8_t *) wbuf[1] + w_buf_size) }; + uint8_t * wdma[2] = { is_f16 ? (uint8_t *) wbuf[0] : (uint8_t *) wraw[0], + is_f16 ? (uint8_t *) wbuf[1] : (uint8_t *) wraw[1] }; + + const HVX_Vector zero = Q6_V_vzero(); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + for (uint32_t rt = ith; rt < hc->n_rt; rt += nth) { + const uint32_t co0 = (hc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, Cout - co0); + + uint32_t bi = 0; + for (uint32_t i = 0; i < 2 && i * WK < k_pad; i++) { + const uint32_t kc = i * WK; + const uint32_t kv = MIN(WK, K - kc); + dma_queue_push(dmaq, dma_make_data(wdma[i], kernel->data + (size_t) co0 * kernel->nb[3] + (size_t) kc * es), + WK * es, kernel->nb[3], kv * es, nco); + } + + for (uint32_t kc = 0; kc < k_pad; kc += WK) { + const uint32_t kv = MIN(WK, K - kc); + const uint32_t hd = MIN(WK, k_pad - kc); + + dma_queue_pop(dmaq); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) kc); + + for (uint32_t r = 0; r < 32; r++) { + HVX_Vector * dv = (HVX_Vector *) (wbuf[bi] + (size_t) r * WK); + const HVX_Vector * sv = (const HVX_Vector *) (wraw[bi] + (size_t) r * WK); + for (uint32_t j = 0; j < hd; j += 64) { + HVX_Vector v = zero; + if (r < nco && j < kv) { + v = is_f16 ? dv[j / 64] : conv2d_f32_to_f16(sv[j / 32], sv[j / 32 + 1]); + if (kv - j < 64) { + v = Q6_V_vmux_QVV(Q6_Q_vsetq_R((kv - j) * sizeof(__fp16)), v, zero); + } + } + dv[j / 64] = v; + } + } + + __fp16 * tiles = hc->w_tiles + ((size_t) rt * kp->tiled.n_k_tiles + kc / 32) * HMX_FP16_TILE_N_ELMS; + hmx_interleave_cols_to_tiles(tiles, wbuf[bi], 32, hd, WK, 1, 0, 32); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) kc); + + const uint32_t next_kc = kc + 2 * WK; + if (next_kc < k_pad) { + const uint32_t next_kv = MIN(WK, K - next_kc); + dma_queue_push(dmaq, dma_make_data(wdma[bi], kernel->data + (size_t) co0 * kernel->nb[3] + (size_t) next_kc * es), + WK * es, kernel->nb[3], next_kv * es, nco); + } + bi ^= 1; + } + } +} + +// Stage Cin*KH input rows for G col tiles: stage[(cin*KH + kh)*SR + j] = x[n][cin][ih(kh)][ow0 - p0 + j], zero outside +static void conv2d_hmx_stage(const struct htp_ops_context * octx, const struct htp_conv2d_kernel_params * kp, + dma_queue * dmaq, float * stage, uint32_t n, uint32_t oh, uint32_t ow0, uint32_t G) { + const struct htp_tensor * kernel = octx->src[0]; + const struct htp_tensor * input = octx->src[1]; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const int32_t IW = input->ne[0]; + const int32_t IH = input->ne[1]; + const int32_t s1 = octx->op_params[1]; + const int32_t p0 = octx->op_params[2]; + const int32_t p1 = octx->op_params[3]; + const int32_t d0 = octx->op_params[4]; + const int32_t d1 = octx->op_params[5]; + const uint32_t SR = kp->tiled.stage_row; + + const int32_t Wb = 32 * G + (KW - 1) * d0; + const int32_t iw0 = (int32_t) ow0 - p0; + const int32_t lo = MAX(0, -iw0); + const int32_t hi = MIN(Wb, IW - iw0); + + for (uint32_t kh = 0; kh < KH; kh++) { + const int32_t ih = (int32_t) oh * s1 + (int32_t) kh * d1 - p1; + float * rows = stage + (size_t) kh * SR; + + if (ih < 0 || ih >= IH || hi <= lo) { + for (uint32_t c = 0; c < Cin; c++) { + hvx_splat_f32_u(rows + (size_t) c * KH * SR, 0.0f, Wb); + } + dma_queue_push(dmaq, dma_make_data(rows, 0), 0, 0, 0, 0); + continue; + } + + const dma_addr_t src = input->data + (size_t) n * input->nb[3] + (size_t) ih * input->nb[1] + (size_t) (iw0 + lo) * sizeof(float); + dma_queue_push(dmaq, dma_make_data(rows + lo, src), (size_t) KH * SR * sizeof(float), input->nb[2], + (size_t) (hi - lo) * sizeof(float), Cin); + + if (lo > 0 || hi < Wb) { + for (uint32_t c = 0; c < Cin; c++) { + float * row = rows + (size_t) c * KH * SR; + if (lo > 0) { + hvx_splat_f32_u(row, 0.0f, lo); + } + if (hi < Wb) { + hvx_splat_f32_u(row + hi, 0.0f, Wb - hi); + } + } + } + } +} + +// One weight-side tile column: vector i holds k rows 2i and 2i+1 interleaved over 32 pixels +static inline void conv2d_hmx_pack_tile(__fp16 * restrict dst, const float * restrict src, uint32_t K, uint32_t KW, + uint32_t d0, uint32_t SR, uint32_t n_vec) { + HVX_Vector * restrict out = (HVX_Vector *) dst; + const HVX_Vector zero = Q6_V_vzero(); + const uint32_t wrap = SR - KW * d0; + + const float * p = src; + uint32_t kw = 0; + uint32_t i = 0; + + for (; i < K / 2; i++) { + const HVX_Vector a = hvx_vmemu(p); + p += d0; + if (++kw == KW) { + kw = 0; + p += wrap; + } + const HVX_Vector b = hvx_vmemu(p); + p += d0; + if (++kw == KW) { + kw = 0; + p += wrap; + } + out[i] = conv2d_f32_to_f16_shuff(a, b); + } + if (K & 1) { + out[i++] = conv2d_f32_to_f16_shuff(hvx_vmemu(p), zero); + } + for (; i < n_vec; i++) { + out[i] = zero; + } +} + +// CWHN: stage[kh*SR + j*Cin + cin] = x[n][ih(kh)][ow0 - p0 + j][cin], zero outside +static void conv2d_hmx_stage_cwhn(const struct htp_ops_context * octx, const struct htp_conv2d_kernel_params * kp, + dma_queue * dmaq, float * stage, uint32_t n, uint32_t oh, uint32_t ow0, uint32_t G) { + const struct htp_tensor * kernel = octx->src[0]; + const struct htp_tensor * input = octx->src[1]; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const int32_t IW = input->ne[0]; + const int32_t IH = input->ne[1]; + const int32_t s1 = octx->op_params[1]; + const int32_t p0 = octx->op_params[2]; + const int32_t p1 = octx->op_params[3]; + const int32_t d0 = octx->op_params[4]; + const int32_t d1 = octx->op_params[5]; + const uint32_t SR = kp->tiled.stage_row; + + const int32_t Wb = 32 * G + (KW - 1) * d0; + const int32_t iw0 = (int32_t) ow0 - p0; + const int32_t lo = MAX(0, -iw0); + const int32_t hi = MIN(Wb, IW - iw0); + + for (uint32_t kh = 0; kh < KH; kh++) { + const int32_t ih = (int32_t) oh * s1 + (int32_t) kh * d1 - p1; + float * row = stage + (size_t) kh * SR; + + if (ih < 0 || ih >= IH || hi <= lo) { + hvx_splat_f32_u(row, 0.0f, Wb * Cin); + dma_queue_push(dmaq, dma_make_data(row, 0), 0, 0, 0, 0); + continue; + } + + const dma_addr_t src = input->data + (size_t) n * input->nb[3] + (size_t) ih * input->nb[1] + (size_t) (iw0 + lo) * input->nb[0]; + const size_t size = (size_t) (hi - lo) * Cin * sizeof(float); + dma_queue_push(dmaq, dma_make_data(row + lo * Cin, src), size, size, size, 1); + + if (lo > 0) { + hvx_splat_f32_u(row, 0.0f, lo * Cin); + } + if (hi < Wb) { + hvx_splat_f32_u(row + hi * Cin, 0.0f, (Wb - hi) * Cin); + } + } +} + +static void conv2d_hmx_cwhn_f16(__fp16 * restrict dst, const float * restrict src, uint32_t KH, uint32_t SR, uint32_t n) { + for (uint32_t kh = 0; kh < KH; kh++) { + hvx_copy_f16_f32_aa((uint8_t *) (dst + (size_t) kh * SR), (const uint8_t *) (src + (size_t) kh * SR), n); + } +} + +// Stage the segment of col tiles starting at t, returns its number of col tiles +static uint32_t conv2d_hmx_issue_seg(const struct htp_ops_context * octx, const struct htp_conv2d_kernel_params * kp, + dma_queue * dmaq, float * stage, uint32_t t, uint32_t t1) { + const uint32_t OH = octx->dst->ne[1]; + const uint32_t n_owt = kp->tiled.n_ow_tiles; + const uint32_t row = fastdiv(t, &kp->tiled.div_ow_tiles); + const uint32_t owt = t - row * n_owt; + const uint32_t G = MIN(MIN(kp->tiled.seg_tiles, t1 - t), n_owt - owt); + const uint32_t n = fastdiv(row, &kp->tiled.div_oh); + const uint32_t oh = row - n * OH; + + if (kp->cwhn) { + conv2d_hmx_stage_cwhn(octx, kp, dmaq, stage, n, oh, owt * 32, G); + } else { + conv2d_hmx_stage(octx, kp, dmaq, stage, n, oh, owt * 32, G); + } + return G; +} + +static inline void conv2d_vshuff_w(HVX_Vector * a, HVX_Vector * b) { + const HVX_VectorPair p = Q6_W_vshuff_VVR(*b, *a, -4); + *a = Q6_V_lo_W(p); + *b = Q6_V_hi_W(p); +} + +static inline void conv2d_transpose_finish(HVX_Vector * restrict scratch, HVX_Vector * restrict lo, HVX_Vector * restrict hi); + +// 32x32 word transpose: out[i] word j = in[j * in_stride] word i; out 0..15 -> lo, 16..31 -> hi +static inline void conv2d_transpose_w32(const HVX_Vector * restrict in, uint32_t in_stride, HVX_Vector * restrict scratch, + HVX_Vector * restrict lo, HVX_Vector * restrict hi) { + for (uint32_t i = 0; i < 8; i++) { + HVX_Vector v0 = in[(i + 0) * in_stride]; + HVX_Vector v1 = in[(i + 8) * in_stride]; + HVX_Vector v2 = in[(i + 16) * in_stride]; + HVX_Vector v3 = in[(i + 24) * in_stride]; + conv2d_vshuff_w(&v0, &v2); + conv2d_vshuff_w(&v1, &v3); + conv2d_vshuff_w(&v0, &v1); + conv2d_vshuff_w(&v2, &v3); + scratch[i + 0] = v0; + scratch[i + 8] = v1; + scratch[i + 16] = v2; + scratch[i + 24] = v3; + } + conv2d_transpose_finish(scratch, lo, hi); +} + +static inline void conv2d_transpose_finish(HVX_Vector * restrict scratch, HVX_Vector * restrict lo, HVX_Vector * restrict hi) { + for (uint32_t g = 0; g < 4; g++) { + HVX_Vector w0 = scratch[8 * g + 0]; + HVX_Vector w1 = scratch[8 * g + 1]; + HVX_Vector w2 = scratch[8 * g + 2]; + HVX_Vector w3 = scratch[8 * g + 3]; + HVX_Vector w4 = scratch[8 * g + 4]; + HVX_Vector w5 = scratch[8 * g + 5]; + HVX_Vector w6 = scratch[8 * g + 6]; + HVX_Vector w7 = scratch[8 * g + 7]; + conv2d_vshuff_w(&w0, &w4); + conv2d_vshuff_w(&w1, &w5); + conv2d_vshuff_w(&w2, &w6); + conv2d_vshuff_w(&w3, &w7); + conv2d_vshuff_w(&w0, &w2); + conv2d_vshuff_w(&w1, &w3); + conv2d_vshuff_w(&w4, &w6); + conv2d_vshuff_w(&w5, &w7); + conv2d_vshuff_w(&w0, &w1); + conv2d_vshuff_w(&w2, &w3); + conv2d_vshuff_w(&w4, &w5); + conv2d_vshuff_w(&w6, &w7); + HVX_Vector * o = (g < 2 ? lo : hi) + 8 * (g & 1); + o[0] = w0; + o[1] = w1; + o[2] = w2; + o[3] = w3; + o[4] = w4; + o[5] = w5; + o[6] = w6; + o[7] = w7; + } +} + +// Same transpose, but pixel j is base + j * stride. Skips the vin store/reload. +static inline void conv2d_transpose_strided(const __fp16 * restrict base, uint32_t stride, HVX_Vector * restrict scratch, + HVX_Vector * restrict lo, HVX_Vector * restrict hi) { + for (uint32_t i = 0; i < 8; i++) { + HVX_Vector v0 = hvx_vmemu(base + (i + 0) * stride); + HVX_Vector v1 = hvx_vmemu(base + (i + 8) * stride); + HVX_Vector v2 = hvx_vmemu(base + (i + 16) * stride); + HVX_Vector v3 = hvx_vmemu(base + (i + 24) * stride); + conv2d_vshuff_w(&v0, &v2); + conv2d_vshuff_w(&v1, &v3); + conv2d_vshuff_w(&v0, &v1); + conv2d_vshuff_w(&v2, &v3); + scratch[i + 0] = v0; + scratch[i + 8] = v1; + scratch[i + 16] = v2; + scratch[i + 24] = v3; + } + conv2d_transpose_finish(scratch, lo, hi); +} + +// CWHN: k is n_groups groups of k_group contiguous values (per kh, or per (kh, kw) if d0 > 1), each padded to k_group_pad. +// A full 64-wide block is one vector per pixel and is transposed in place. A partial block is two masked loads, +// the second one rotated into the upper half. +static void conv2d_hmx_pack_tile_cwhn(__fp16 * restrict dst, const __fp16 * restrict src, HVX_Vector * restrict vin, + HVX_Vector * restrict scratch, const struct htp_conv2d_kernel_params * kp, + uint32_t gpr, uint32_t Cin, uint32_t d0) { + const uint32_t k_pad = kp->tiled.n_k_tiles * HMX_FP16_TILE_N_COLS; + const uint32_t KG = kp->tiled.k_group; + const uint32_t KGp = kp->tiled.k_group_pad; + const uint32_t NG = kp->tiled.n_groups; + const uint32_t SR = kp->tiled.stage_row; + + HVX_Vector * restrict out = (HVX_Vector *) dst; + + uint32_t g = 0; + uint32_t gw = 0; + uint32_t r = 0; + size_t roff = 0; + size_t goff = 0; + + for (uint32_t b = 0; b < k_pad / 64; b++) { + const __fp16 * pa[2]; + uint32_t va[2]; + for (uint32_t h = 0; h < 2; h++) { + va[h] = g < NG && r < KG ? MIN(32, KG - r) : 0; + pa[h] = g < NG ? src + goff + r : src; + r += 32; + if (r >= KGp) { + r = 0; + g++; + if (++gw == gpr) { + gw = 0; + roff += SR; + goff = roff; + } else { + goff += d0 * Cin; + } + } + } + + if (va[0] == 32 && va[1] == 32 && pa[1] == pa[0] + 32) { + conv2d_transpose_strided(pa[0], Cin, scratch, out + 32 * b, out + 32 * b + 16); + continue; + } + + const HVX_VectorPred q0 = Q6_Q_vsetq_R(va[0] * sizeof(__fp16)); + const HVX_VectorPred q1 = Q6_Q_vsetq_R(va[1] * sizeof(__fp16)); + for (uint32_t j = 0; j < 32; j++) { + const HVX_Vector v0 = Q6_V_vand_QV(q0, hvx_vmemu(pa[0] + j * Cin)); + const HVX_Vector v1 = Q6_V_vand_QV(q1, hvx_vmemu(pa[1] + j * Cin)); + vin[j] = Q6_V_vor_VV(v0, Q6_V_vror_VR(v1, 64)); + } + + conv2d_transpose_w32(vin, 1, scratch, out + 32 * b, out + 32 * b + 16); + } +} + +struct wpack_kmajor_task { + uint32_t rt; + uint32_t g; + uint32_t kc; + uint32_t nco; + uint32_t nk; + uint32_t hk; +}; + +static inline void conv2d_hmx_wpack_kmajor_compute(const struct htp_conv2d_hmx_context * hc, + const uint8_t * wraw, + const struct wpack_kmajor_task * task, + HVX_Vector * vin, + HVX_Vector * scratch, + HVX_Vector * sink, + bool is_f16, + uint32_t es) { + const struct htp_conv2d_kernel_params * kp = hc->kp; + const uint32_t KGp = kp->tiled.k_group_pad; + const HVX_VectorPred qco = Q6_Q_vsetq2_R(task->nco * sizeof(__fp16)); + for (uint32_t kt = 0; kt < task->hk / 32; kt++) { + for (uint32_t j = 0; j < 32; j++) { + const uint32_t k = kt * 32 + j; + const HVX_Vector * sv = (const HVX_Vector *) (wraw + (size_t) k * 64 * es); + const HVX_Vector v = is_f16 ? sv[0] : conv2d_f32_to_f16(sv[0], sv[1]); + vin[j] = conv2d_keep(Q6_V_vand_QV(qco, v), k < task->nk); + } + + const uint32_t ktg = (task->g * KGp + task->kc) / 32 + kt; + HVX_Vector * lo = (HVX_Vector *) (hc->w_tiles + ((size_t) task->rt * kp->tiled.n_k_tiles + ktg) * HMX_FP16_TILE_N_ELMS); + HVX_Vector * hi = task->rt + 1 < hc->n_rt ? + (HVX_Vector *) (hc->w_tiles + ((size_t) (task->rt + 1) * kp->tiled.n_k_tiles + ktg) * HMX_FP16_TILE_N_ELMS) : sink; + conv2d_transpose_w32(vin, 1, scratch, lo, hi); + } +} + +static inline void conv2d_hmx_wpack_kmajor_dma(const struct htp_conv2d_hmx_context * hc, + dma_queue * dmaq, + uint8_t * wraw, + const struct wpack_kmajor_task * task, + uint32_t es, + size_t ks) { + const struct htp_tensor * kernel = hc->octx->src[0]; + const uint32_t KG = hc->kp->tiled.k_group; + if (task->nk > 0) { + const dma_addr_t src = kernel->data + ((size_t) task->g * KG + task->kc) * ks + (size_t) (hc->rt0 + task->rt) * 32 * es; + dma_queue_push(dmaq, dma_make_data(wraw, src), 64 * es, ks, task->nco * es, task->nk); + } else { + dma_queue_push(dmaq, dma_make_data(wraw, 0), 0, 0, 0, 0); + } +} + +struct conv2d_wpack_kmajor_iter { + uint32_t cb; + uint32_t g; + uint32_t kc; + uint32_t owner; + uint32_t n_cb; + uint32_t NG; + uint32_t KG; + uint32_t KGp; + uint32_t k_pad; + uint32_t WK; + uint32_t Cout; + uint32_t rt0; + uint32_t nth; + uint32_t ith; +}; + +static inline bool conv2d_wpack_kmajor_next_task(struct conv2d_wpack_kmajor_iter * it, struct wpack_kmajor_task * task) { + while (it->cb < it->n_cb) { + const uint32_t span = it->g + 1 == it->NG ? it->k_pad - it->g * it->KGp : it->KGp; + while (it->kc < span) { + const bool mine = it->owner == it->ith; + it->owner = it->owner + 1 == it->nth ? 0 : it->owner + 1; + const uint32_t kc = it->kc; + it->kc += it->WK; + if (mine) { + const uint32_t rt = 2 * it->cb; + const uint32_t co0 = (it->rt0 + rt) * 32; + task->rt = rt; + task->g = it->g; + task->kc = kc; + task->nco = MIN(64, it->Cout - co0); + task->nk = kc < it->KG ? MIN(it->WK, it->KG - kc) : 0; + task->hk = MIN(it->WK, span - kc); + return true; + } + } + it->kc = 0; + if (++it->g == it->NG) { + it->g = 0; + it->cb++; + } + } + return false; +} + +// Kernel stored as [k][cout] (cout contiguous): DMA k rows of 64 cout, transpose into two row tiles +static void conv2d_hmx_wpack_kmajor_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_hmx_context * hc = (const struct htp_conv2d_hmx_context *) data; + struct htp_ops_context * octx = hc->octx; + const struct htp_conv2d_kernel_params * kp = hc->kp; + const struct htp_tensor * kernel = octx->src[0]; + + const uint32_t Cout = kernel->ne[3]; + const uint32_t k_pad = kp->tiled.n_k_tiles * HMX_FP16_TILE_N_COLS; + const uint32_t WK = kp->tiled.wk_chunk; + const uint32_t KG = kp->tiled.k_group; + const uint32_t KGp = kp->tiled.k_group_pad; + const uint32_t NG = kp->tiled.n_groups; + const size_t ks = kp->tiled.w_kstride; + const bool is_f16 = kernel->type == HTP_TYPE_F16; + const uint32_t es = is_f16 ? sizeof(__fp16) : sizeof(float); + const uint32_t n_cb = (hc->n_rt + 1) / 2; + + dma_queue * dmaq = octx->ctx->dma[ith]; + const size_t w_raw_size = (size_t) WK * 64 * sizeof(float); + uint8_t * wraws[2] = { hc->thr_base + (size_t) ith * kp->thr_size, + hc->thr_base + (size_t) ith * kp->thr_size + w_raw_size }; + HVX_Vector * vin = (HVX_Vector *) (wraws[1] + w_raw_size); + HVX_Vector * scratch = vin + 32; + HVX_Vector * sink = scratch + 32; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + struct conv2d_wpack_kmajor_iter it = { + .cb = 0, + .g = 0, + .kc = 0, + .owner = 0, + .n_cb = n_cb, + .NG = NG, + .KG = KG, + .KGp = KGp, + .k_pad = k_pad, + .WK = WK, + .Cout = Cout, + .rt0 = hc->rt0, + .nth = nth, + .ith = ith, + }; + + struct wpack_kmajor_task tasks[2]; + uint32_t n_tasks = 0; + + // push(0), push(1) + for (uint32_t i = 0; i < 2; i++) { + if (conv2d_wpack_kmajor_next_task(&it, &tasks[i])) { + conv2d_hmx_wpack_kmajor_dma(hc, dmaq, wraws[i], &tasks[i], es, ks); + n_tasks++; + } + } + + // pop(N), compute(N), push(N + 2) + uint32_t bi = 0; + while (n_tasks > 0) { + dma_queue_pop(dmaq); + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) tasks[bi].kc); + conv2d_hmx_wpack_kmajor_compute(hc, wraws[bi], &tasks[bi], vin, scratch, sink, is_f16, es); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) tasks[bi].kc); + n_tasks--; + + struct wpack_kmajor_task next_task; + if (conv2d_wpack_kmajor_next_task(&it, &next_task)) { + tasks[bi] = next_task; + conv2d_hmx_wpack_kmajor_dma(hc, dmaq, wraws[bi], &tasks[bi], es, ks); + n_tasks++; + } + bi ^= 1; + } +} + +static void conv2d_hmx_pack(const struct htp_conv2d_hmx_context * hc, uint32_t ith) { + struct htp_ops_context * octx = hc->octx; + const struct htp_conv2d_kernel_params * kp = hc->kp; + const struct htp_tensor * kernel = octx->src[0]; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const uint32_t d0 = octx->op_params[4]; + const uint32_t n_vec = kp->tiled.n_k_tiles * (HMX_FP16_TILE_N_ELMS / 64); + + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * thr = hc->thr_base + (size_t) ith * kp->thr_size; + float * stages[2] = { + (float *) thr, + (float *) (thr + kp->stage_size), + }; + __fp16 * act = hc->act[hc->pack_chunk & 1]; + + // CWHN: fp16 stage (+256 bytes of over-read slack), then 32 + 32 vectors for the transpose + const uint32_t n_stage = kp->tiled.n_stage > 1 ? 2 : 1; + __fp16 * stage16 = (__fp16 *) (thr + (size_t) n_stage * kp->stage_size + (size_t) 2 * 32 * kp->tiled.seg_tiles * 32 * sizeof(float)); + HVX_Vector * vin = (HVX_Vector *) ((uint8_t *) stage16 + kp->stage_size / 2 + 256); + HVX_Vector * scratch = vin + 32; + const uint32_t gpr = kp->tiled.n_groups == KH ? 1 : KW; + + uint32_t t0, t1; + const uint32_t cs = conv2d_hmx_chunk_range(hc, hc->pack_chunk, hc->pack_tpt, ith, &t0, &t1); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + if (t0 >= t1) { + return; + } + + uint32_t ng[2] = { 0, 0 }; + uint32_t tq = t0; + for (uint32_t i = 0; i < n_stage && tq < t1; i++) { + ng[i] = conv2d_hmx_issue_seg(octx, kp, dmaq, stages[i], tq, t1); + tq += ng[i]; + } + + uint32_t bi = 0; + for (uint32_t t = t0; t < t1;) { + const uint32_t G = ng[bi]; + float * stage = stages[bi]; + + for (uint32_t p = 0; p < KH; p++) { + dma_queue_pop(dmaq); + } + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) t); + if (kp->cwhn) { + const uint32_t Wb = 32 * G + (KW - 1) * d0; + conv2d_hmx_cwhn_f16(stage16, stage, KH, kp->tiled.stage_row, Wb * Cin); + for (uint32_t g = 0; g < G; g++) { + __fp16 * tile = act + (size_t) (t - cs + g) * n_vec * 64; + conv2d_hmx_pack_tile_cwhn(tile, stage16 + (size_t) g * 32 * Cin, vin, scratch, kp, gpr, Cin, d0); + } + } else { + for (uint32_t g = 0; g < G; g++) { + __fp16 * tile = act + (size_t) (t - cs + g) * n_vec * 64; + conv2d_hmx_pack_tile(tile, stage + g * 32, kp->tiled.k_size, KW, d0, kp->tiled.stage_row, n_vec); + } + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) t); + + if (tq < t1) { + ng[bi] = conv2d_hmx_issue_seg(octx, kp, dmaq, stage, tq, t1); + tq += ng[bi]; + } + t += G; + bi = bi + 1 == n_stage ? 0 : bi + 1; + } +} + +static void conv2d_hmx_unpack(const struct htp_conv2d_hmx_context * hc, uint32_t ith) { + struct htp_ops_context * octx = hc->octx; + const struct htp_conv2d_kernel_params * kp = hc->kp; + const struct htp_tensor * dst = octx->dst; + + const uint32_t OW = dst->ne[0]; + const uint32_t OH = dst->ne[1]; + const uint32_t Cout = dst->ne[2]; + const uint32_t n_owt = kp->tiled.n_ow_tiles; + const uint32_t OS = kp->tiled.seg_tiles * 32; + + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * thr = hc->thr_base + (size_t) ith * kp->thr_size + (size_t) (kp->tiled.n_stage > 1 ? 2 : 1) * kp->stage_size; + float * ostage[2] = { + (float *) thr, + (float *) (thr + (size_t) 32 * OS * sizeof(float)), + }; + const __fp16 * out = hc->out[hc->unpack_chunk & 1]; + + uint32_t t0, t1; + const uint32_t cs = conv2d_hmx_chunk_range(hc, hc->unpack_chunk, hc->unpack_tpt, ith, &t0, &t1); + const uint32_t nct = MIN(cs + kp->ct_chunk, hc->t_end) - cs; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + if (t0 >= t1) { + return; + } + + uint32_t b = 0; + uint32_t n_pushed = 0; + + for (uint32_t t = t0; t < t1;) { + const uint32_t row = fastdiv(t, &kp->tiled.div_ow_tiles); + const uint32_t owt = t - row * n_owt; + const uint32_t G = MIN(MIN(kp->tiled.seg_tiles, t1 - t), n_owt - owt); + const uint32_t n = fastdiv(row, &kp->tiled.div_oh); + const uint32_t oh = row - n * OH; + const uint32_t ow0 = owt * 32; + const uint32_t nv = MIN(G * 32, OW - ow0); + + for (uint32_t rt = 0; rt < hc->n_rt; rt++) { + const uint32_t co0 = (hc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, Cout - co0); + const HVX_Vector restore = conv2d_hmx_rt_restore(hc->scales, rt); + + if (n_pushed >= 2) { + dma_queue_pop(dmaq); + } + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) t); + float * ob = ostage[b]; + for (uint32_t g = 0; g < G; g++) { + const HVX_Vector * tv = (const HVX_Vector *) (out + ((size_t) rt * nct + (t - cs + g)) * HMX_FP16_TILE_N_ELMS); + for (uint32_t r = 0; r < 16; r++) { + const HVX_VectorPair pr = hvx_vec_f16_to_f32_shuff(tv[r]); + *(HVX_Vector *) (ob + (size_t) (2 * r + 0) * OS + g * 32) = hvx_vec_mul_f32_f32(Q6_V_lo_W(pr), restore); + *(HVX_Vector *) (ob + (size_t) (2 * r + 1) * OS + g * 32) = hvx_vec_mul_f32_f32(Q6_V_hi_W(pr), restore); + } + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) t); + + const dma_addr_t ddr = dst->data + (size_t) n * dst->nb[3] + (size_t) oh * dst->nb[1] + (size_t) co0 * dst->nb[2] + (size_t) ow0 * sizeof(float); + dma_queue_push(dmaq, dma_make_data(ddr, ob), dst->nb[2], (size_t) OS * sizeof(float), (size_t) nv * sizeof(float), nco); + n_pushed++; + b ^= 1; + } + t += G; + } + + // Drain the pipeline + if (n_pushed >= 1) { + dma_queue_pop(dmaq); + } + if (n_pushed >= 2) { + dma_queue_pop(dmaq); + } +} + +static void conv2d_hmx_phase_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_hmx_context * hc = (const struct htp_conv2d_hmx_context *) data; + + if (hc->unpack_chunk >= 0) { + conv2d_hmx_unpack(hc, ith); + } + // weights of this rt block are packed before its first chunk + if (hc->pack_chunk == 0) { + const uint32_t n_kt = hc->kp->tiled.n_k_tiles; + for (uint32_t rt = ith; rt < hc->n_rt; rt += nth) { + conv2d_hmx_rt_scale(hc->scales + rt * CONV2D_HMX_SCALES_N, hc->w_tiles + (size_t) rt * n_kt * HMX_FP16_TILE_N_ELMS, n_kt, + hc->kp->tiled.k_size); + } + } + if (hc->pack_chunk >= 0) { + conv2d_hmx_pack(hc, ith); + } +} + +static inline uint32_t conv2d_hmx_tpt(const struct htp_conv2d_hmx_context * hc, int32_t c, uint32_t nth) { + if (c < 0) { + return 0; + } + const uint32_t cs = hc->t_base + (uint32_t) c * hc->kp->ct_chunk; + const uint32_t nct = MIN(hc->kp->ct_chunk, hc->t_end - cs); + return (nct + nth - 1) / nth; +} + +static void conv2d_hmx_run_phase(struct htp_conv2d_hmx_context * hc, int32_t pack, int32_t unpack, uint32_t nth) { + hc->pack_chunk = pack; + hc->unpack_chunk = unpack; + hc->pack_tpt = conv2d_hmx_tpt(hc, pack, nth); + hc->unpack_tpt = conv2d_hmx_tpt(hc, unpack, nth); + work_queue_run(hc->octx->ctx->work_queue, conv2d_hmx_phase_thread, hc, nth); +} + +static int conv2d_hmx_tiled(struct htp_ops_context * octx, const struct htp_conv2d_kernel_params * kp) { + uint32_t row_base, n_rows; + conv2d_mdev_rows(octx, &row_base, &n_rows); + if (n_rows == 0) { + return HTP_STATUS_OK; + } + + const size_t tile = 2048; + const size_t w_size = (size_t) kp->rt_block * kp->tiled.n_k_tiles * tile; + const size_t act_size = (size_t) kp->ct_chunk * kp->tiled.n_k_tiles * tile; + const size_t out_size = (size_t) kp->rt_block * kp->ct_chunk * tile; + + struct htp_conv2d_vtcm_layout layout; + htp_conv2d_vtcm_layout_build(&layout, kp->rt_block, w_size, act_size, out_size, kp->thr_size, kp->n_threads); + + uint8_t * base = (uint8_t *) octx->ctx->vtcm_base; + + struct htp_conv2d_hmx_context hc = { + .octx = octx, + .kp = kp, + .layout = layout, + .scales = VTCM_LAYOUT_PTR(__fp16, base, layout.off_scales), + .w_tiles = VTCM_LAYOUT_PTR(__fp16, base, layout.off_w), + .act = { VTCM_LAYOUT_PTR(__fp16, base, layout.off_act[0]), VTCM_LAYOUT_PTR(__fp16, base, layout.off_act[1]) }, + .out = { VTCM_LAYOUT_PTR(__fp16, base, layout.off_out[0]), VTCM_LAYOUT_PTR(__fp16, base, layout.off_out[1]) }, + .thr_base = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_thr), + .t_base = row_base * kp->tiled.n_ow_tiles, + .t_end = (row_base + n_rows) * kp->tiled.n_ow_tiles, + }; + + const uint32_t nth = kp->n_threads; + const int32_t n_chunks = (int32_t) ((hc.t_end - hc.t_base + kp->ct_chunk - 1) / kp->ct_chunk); + + struct htp_conv2d_hmx_task task; + + for (uint32_t rt0 = 0; rt0 < kp->n_row_tiles; rt0 += kp->rt_block) { + hc.rt0 = rt0; + hc.n_rt = MIN(kp->rt_block, kp->n_row_tiles - rt0); + work_queue_run(octx->ctx->work_queue, kp->w_kmajor ? conv2d_hmx_wpack_kmajor_thread : conv2d_hmx_wpack_thread, &hc, nth); + + conv2d_hmx_run_phase(&hc, 0, -1, nth); + + for (int32_t c = 0; c < n_chunks; c++) { + const uint32_t cs = hc.t_base + (uint32_t) c * kp->ct_chunk; + + task.output = hc.out[c & 1]; + task.kernel_tiles = hc.w_tiles; + task.patch_tiles = hc.act[c & 1]; + task.scales = hc.scales; + task.n_row_tiles = hc.n_rt; + task.n_col_tiles = MIN(kp->ct_chunk, hc.t_end - cs); + task.n_dot_tiles = kp->tiled.n_k_tiles; + hmx_queue_push(octx->ctx->hmx_queue, hmx_queue_make_desc(conv2d_hmx_worker, &task)); + + const int32_t pack = c + 1 < n_chunks ? c + 1 : -1; + const int32_t unpack = c - 1; + if (pack >= 0 || unpack >= 0) { + conv2d_hmx_run_phase(&hc, pack, unpack, nth); + } + + hmx_queue_pop(octx->ctx->hmx_queue); + } + + conv2d_hmx_run_phase(&hc, -1, n_chunks - 1, nth); + } + + return HTP_STATUS_OK; +} + +// ---- HMX_WIN: implicit GEMM over sliding crouton windows ---- + +#define CONV2D_WIN_RT_FULL 0x7FE // spatial mask 11111, channel stop 31 +#define CONV2D_WIN_SCAT_MAX 4 // scatter croutons for Cin <= 2 * CONV2D_WIN_SCAT_MAX + +// whcn small Cin: crouton byte offset of word j of a [c | c + 1] pixel pair vector +static const int32_t conv2d_hmx_win_scat_off[32] __attribute__((aligned(VLEN))) = { + 0 * 128, 1 * 128, 2 * 128, 3 * 128, 4 * 128, 5 * 128, 6 * 128, 7 * 128, + 8 * 128, 9 * 128, 10 * 128, 11 * 128, 12 * 128, 13 * 128, 14 * 128, 15 * 128, + 0 * 128 + 4, 1 * 128 + 4, 2 * 128 + 4, 3 * 128 + 4, 4 * 128 + 4, 5 * 128 + 4, 6 * 128 + 4, 7 * 128 + 4, + 8 * 128 + 4, 9 * 128 + 4, 10 * 128 + 4, 11 * 128 + 4, 12 * 128 + 4, 13 * 128 + 4, 14 * 128 + 4, 15 * 128 + 4, +}; + +struct htp_conv2d_win_context { + struct htp_ops_context * octx; + const struct htp_conv2d_kernel_params * kp; + struct htp_conv2d_vtcm_layout layout; + __fp16 * scales; // [rt] HMX scales + __fp16 * w_tiles; // [rt][tap][cc] weight tiles + __fp16 * act[2]; // [cc][b] croutons of a chunk + __fp16 * out[2]; // [rt][tile] output tiles of a chunk + uint8_t * thr_base; + uint32_t t_base; // device col tile range + uint32_t t_end; + uint32_t vr0; // device virtual output row range + uint32_t vr1; + uint32_t rt0; + uint32_t n_rt; + int32_t pack_chunk; + int32_t unpack_chunk; + uint32_t n_scat; // small Cin: scatters per crouton into zeroed croutons, else 0 + uint8_t * live[2]; // per chunk: tiles with an output row to write +}; + +struct htp_conv2d_win_task { + __fp16 * out; + const __fp16 * w; + const __fp16 * act; + const __fp16 * scales; + const uint32_t * taps; // activation address offset of each tap (crouton + window offset fields) + uint32_t n_taps; + uint32_t n_rt; + uint32_t n_tiles; + uint32_t out_stride; // elements between row tiles in out + uint32_t n_cc; + uint32_t plane; // bytes between channel chunks in act + uint32_t rt_last; + uint32_t wr_last; + const uint8_t * live; // tiles with at least one output row to write +}; + +// Activation address offset of input pixel offset u: crouton u / 32, window offset u % 32 in Rs[10:7] and Rs[1] +static inline uint32_t conv2d_hmx_win_act_off(uint32_t u) { + return ((u >> 5) << 11) | ((u & 30) << 6) | ((u & 1) << 1); +} + +static void conv2d_hmx_win_worker(void * data) { + const struct htp_conv2d_win_task * j = (const struct htp_conv2d_win_task *) data; + + const uint32_t * taps = j->taps; + const uint32_t T = j->n_taps; + const uint32_t n_cc = j->n_cc; + const uint32_t plane = j->plane; + const uint32_t rt_last = HMX_FP16_TILE_SIZE | j->rt_last; + const uint32_t wr_last = j->wr_last; + const uint32_t n_tiles = j->n_tiles; + const uint32_t n_rt = j->n_rt; + const uint32_t ostride = j->out_stride; + const uint32_t act = (uint32_t) j->act; + const size_t wstride = (size_t) T * n_cc * HMX_FP16_TILE_N_ELMS; + + for (uint32_t r = 0; r < n_rt; r++) { + asm volatile(HMX_SET_BIAS("%0") :: "r"((unsigned int) (j->scales + r * CONV2D_HMX_SCALES_N))); + + __fp16 * o = j->out + r * ostride; + const __fp16 * w0 = j->w + r * wstride; + + for (uint32_t i = 0; i < n_tiles; i++, o += HMX_FP16_TILE_N_ELMS) { + if (!j->live[i]) { + continue; + } + const uint32_t base = act + i * HMX_FP16_TILE_SIZE; + const __fp16 * w = w0; + + asm volatile(HMX_CLRACC_F16()); + if (n_cc == 1) { + for (uint32_t t = 0; t < T; t++) { + asm volatile("{ activation.hf = mxmem(%0, %1):single\n weight.hf = mxmem(%2, %3) }" + :: "r"(base + taps[t]), "r"(rt_last), "r"(w), "r"(wr_last)); + w += HMX_FP16_TILE_N_ELMS; + } + } else { + for (uint32_t t = 0; t < T; t++) { + uint32_t rs = base + taps[t]; + for (uint32_t cc = 1; cc < n_cc; cc++) { + asm volatile("{ activation.hf = mxmem(%0, %1):single\n weight.hf = mxmem(%2, %3) }" + :: "r"(rs), "r"(HMX_FP16_TILE_SIZE | CONV2D_WIN_RT_FULL), "r"(w), "r"(HMX_FP16_TILE_SIZE - 1)); + rs += plane; + w += HMX_FP16_TILE_N_ELMS; + } + asm volatile("{ activation.hf = mxmem(%0, %1):single\n weight.hf = mxmem(%2, %3) }" + :: "r"(rs), "r"(rt_last), "r"(w), "r"(wr_last)); + w += HMX_FP16_TILE_N_ELMS; + } + } + asm volatile(HMX_STORE_AFTER_F16("%0", "%1") : : "r"(o), "r"(0) : "memory"); + } + } +} + +static inline void conv2d_vdeal_w(HVX_Vector * a, HVX_Vector * b) { + const HVX_VectorPair p = Q6_W_vdeal_VVR(*b, *a, -4); + *a = Q6_V_lo_W(p); + *b = Q6_V_hi_W(p); +} + +#define CONV2D_XPOSE_STAGE(v, m, op) \ + _Pragma("unroll") for (uint32_t i = 0; i < 16; i++) { \ + if (!(i & (m))) { \ + op(&(v)[i], &(v)[i | (m)]); \ + } \ + } + +// 16x32 word transpose: in[i] = [rows 2i, 2i + 1 of 16 words each], out[slot(v)] word c = row c word v +static inline void conv2d_xpose_w16(HVX_Vector * restrict v) { + CONV2D_XPOSE_STAGE(v, 8, conv2d_vshuff_w); + CONV2D_XPOSE_STAGE(v, 4, conv2d_vshuff_w); + CONV2D_XPOSE_STAGE(v, 2, conv2d_vshuff_w); + CONV2D_XPOSE_STAGE(v, 1, conv2d_vshuff_w); + CONV2D_XPOSE_STAGE(v, 8, conv2d_vshuff_w); +} + +// Inverse of conv2d_xpose_w16 +static inline void conv2d_unxpose_w16(HVX_Vector * restrict v) { + CONV2D_XPOSE_STAGE(v, 8, conv2d_vdeal_w); + CONV2D_XPOSE_STAGE(v, 1, conv2d_vdeal_w); + CONV2D_XPOSE_STAGE(v, 2, conv2d_vdeal_w); + CONV2D_XPOSE_STAGE(v, 4, conv2d_vdeal_w); + CONV2D_XPOSE_STAGE(v, 8, conv2d_vdeal_w); +} + +// conv2d_xpose_w16 output position of row v +static inline uint32_t conv2d_xpose_slot(uint32_t v) { + return ((v & 1) << 3) | (v >> 1); +} + +static inline uint32_t conv2d_hmx_win_chunk_tiles(const struct htp_conv2d_win_context * wc, uint32_t c, uint32_t * ts) { + *ts = wc->t_base + c * wc->kp->ct_chunk; + return MIN(wc->kp->ct_chunk, wc->t_end - *ts); +} + +struct conv2d_win_wpack_kmajor_task { + uint32_t rt; + uint32_t cc; + uint32_t tg; + uint32_t t0; + uint32_t nt; + uint32_t c0; + uint32_t nc; + uint32_t co0; + uint32_t nco; + uint32_t kh0; + uint32_t kw0; +}; + +static inline struct conv2d_win_wpack_kmajor_task conv2d_hmx_win_wpack_kmajor_make_task( + const struct htp_conv2d_win_context * wc, + uint32_t unit, + uint32_t n_tg, + uint32_t n_cc, + const struct fastdiv_values * div_tg, + const struct fastdiv_values * div_cc, + const struct fastdiv_values * div_kw, + uint32_t TG, + uint32_t T, + uint32_t KW, + uint32_t Cin, + uint32_t Cout) { + const uint32_t tg = fastmodulo(unit, n_tg, div_tg); + const uint32_t u_cc = fastdiv(unit, div_tg); + const uint32_t cc = fastmodulo(u_cc, n_cc, div_cc); + const uint32_t rt = fastdiv(u_cc, div_cc); + const uint32_t co0 = (wc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, Cout - co0); + const uint32_t c0 = cc * 32; + const uint32_t nc = MIN(32, Cin - c0); + const uint32_t t0 = tg * TG; + const uint32_t nt = MIN(TG, T - t0); + const uint32_t kh0 = fastdiv(t0, div_kw); + const uint32_t kw0 = fastmodulo(t0, KW, div_kw); + + return (struct conv2d_win_wpack_kmajor_task) { + .rt = rt, + .cc = cc, + .tg = tg, + .t0 = t0, + .nt = nt, + .c0 = c0, + .nc = nc, + .co0 = co0, + .nco = nco, + .kh0 = kh0, + .kw0 = kw0, + }; +} + +static inline uint32_t conv2d_hmx_win_wpack_kmajor_dma(const struct htp_conv2d_win_context * wc, + dma_queue * dmaq, + uint8_t * raw, + const struct conv2d_win_wpack_kmajor_task * task, + uint32_t KW, + uint32_t es) { + const struct htp_tensor * kernel = wc->octx->src[0]; + uint32_t kh = task->kh0; + uint32_t kw = task->kw0; + + for (uint32_t t = 0; t < task->nt; t++) { + const dma_addr_t src = kernel->data + (size_t) kw * kernel->nb[0] + (size_t) kh * kernel->nb[1] + + (size_t) task->c0 * kernel->nb[2] + (size_t) task->co0 * es; + dma_queue_push(dmaq, dma_make_data(raw + (size_t) t * 32 * VLEN, src), VLEN, kernel->nb[2], task->nco * es, task->nc); + if (++kw == KW) { + kw = 0; + kh++; + } + } + return task->nt; +} + +static inline void conv2d_hmx_win_wpack_kmajor_compute(const struct htp_conv2d_win_context * wc, + const uint8_t * raw, + const struct conv2d_win_wpack_kmajor_task * task, + uint32_t n_cc, + uint32_t T, + uint32_t KW, + uint32_t KH, + uint32_t Cin, + uint32_t es, + bool is_f16, + HVX_Vector zero) { + const struct htp_conv2d_kernel_params * kp = wc->kp; + const HVX_VectorPred qco = Q6_Q_vsetq2_R(task->nco * es); + if (kp->window.fold) { + const HVX_Vector * rows = (const HVX_Vector *) raw; + HVX_Vector * tile = (HVX_Vector *) (wc->w_tiles + ((size_t) (task->rt * KH + task->tg) * n_cc + task->cc) * HMX_FP16_TILE_N_ELMS); + uint32_t kw = 0; + uint32_t c = 0; + for (uint32_t p = 0; p < 16; p++) { + const HVX_Vector a = kw < KW ? Q6_V_vmux_QVV(qco, rows[kw * 32 + c], zero) : zero; + if (++c == Cin) { + c = 0; + kw++; + } + const HVX_Vector b = kw < KW ? Q6_V_vmux_QVV(qco, rows[kw * 32 + c], zero) : zero; + if (++c == Cin) { + c = 0; + kw++; + } + tile[p] = is_f16 ? Q6_V_lo_W(Q6_W_vshuff_VVR(b, a, -2)) : conv2d_f32_to_f16_shuff(a, b); + } + return; + } + for (uint32_t t = 0; t < task->nt; t++) { + const HVX_Vector * rows = (const HVX_Vector *) (raw + (size_t) t * 32 * VLEN); + HVX_Vector * tile = (HVX_Vector *) (wc->w_tiles + ((size_t) (task->rt * T + task->t0 + t) * n_cc + task->cc) * HMX_FP16_TILE_N_ELMS); + for (uint32_t p = 0; p < 16; p++) { + const HVX_Vector a = 2 * p + 0 < task->nc ? Q6_V_vmux_QVV(qco, rows[2 * p + 0], zero) : zero; + const HVX_Vector b = 2 * p + 1 < task->nc ? Q6_V_vmux_QVV(qco, rows[2 * p + 1], zero) : zero; + tile[p] = is_f16 ? Q6_V_lo_W(Q6_W_vshuff_VVR(b, a, -2)) : conv2d_f32_to_f16_shuff(a, b); + } + } +} + +// Cout-contiguous kernel: DMA w[t][c][32 cout] rows, tile vector p = (row 2p, row 2p+1) interleaved per cout +static void conv2d_hmx_win_wpack_kmajor(const struct htp_conv2d_win_context * wc, unsigned int nth, unsigned int ith) { + struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * kernel = octx->src[0]; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const uint32_t Cout = kernel->ne[3]; + const uint32_t T = KW * KH; + const uint32_t n_cc = kp->window.n_cc; + const uint32_t TG = kp->window.w_cs; + const bool is_f16 = kernel->type == HTP_TYPE_F16; + const uint32_t es = is_f16 ? sizeof(__fp16) : sizeof(float); + + dma_queue * dmaq = octx->ctx->dma[ith]; + const size_t w_raw_size = (size_t) TG * 32 * VLEN; + uint8_t * raws[2] = { wc->thr_base + (size_t) ith * kp->thr_size, + wc->thr_base + (size_t) ith * kp->thr_size + w_raw_size }; + const HVX_Vector zero = Q6_V_vzero(); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + const uint32_t n_tg = (T + TG - 1) / TG; + const uint32_t n_units = wc->n_rt * n_cc * n_tg; + + struct conv2d_win_wpack_kmajor_task tasks[2]; + uint32_t nd[2] = { 0, 0 }; + for (uint32_t k = 0, unit = ith; k < 2 && unit < n_units; k++, unit += nth) { + tasks[k] = conv2d_hmx_win_wpack_kmajor_make_task(wc, unit, n_tg, n_cc, &kp->window.div_tg, &kp->window.div_cc, &kp->window.div_kw, TG, T, KW, Cin, Cout); + nd[k] = conv2d_hmx_win_wpack_kmajor_dma(wc, dmaq, raws[k], &tasks[k], KW, es); + } + for (uint32_t unit = ith, k = 0; unit < n_units; unit += nth, k++) { + const uint32_t bi = k & 1; + uint8_t * raw = raws[bi]; + + for (uint32_t p = 0; p < nd[bi]; p++) { + dma_queue_pop(dmaq); + } + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) unit); + conv2d_hmx_win_wpack_kmajor_compute(wc, raw, &tasks[bi], n_cc, T, KW, KH, Cin, es, is_f16, zero); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) unit); + + if (unit + 2 * nth < n_units) { + tasks[bi] = conv2d_hmx_win_wpack_kmajor_make_task(wc, unit + 2 * nth, n_tg, n_cc, &kp->window.div_tg, &kp->window.div_cc, &kp->window.div_kw, TG, T, KW, Cin, Cout); + nd[bi] = conv2d_hmx_win_wpack_kmajor_dma(wc, dmaq, raw, &tasks[bi], KW, es); + } + } +} + +// K-contiguous kernel: DMA 32 cout rows of the w_cs cin of a packing unit, a dummy DMA if the unit has nothing to load +static void conv2d_hmx_win_wrows_dma(const struct htp_conv2d_win_context * wc, dma_queue * dmaq, uint8_t * raw, uint32_t unit, uint32_t n_cs) { + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * kernel = wc->octx->src[0]; + + const uint32_t T = kernel->ne[0] * kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const uint32_t CS = kp->window.w_cs; + const uint32_t es = kernel->type == HTP_TYPE_F16 ? sizeof(__fp16) : sizeof(float); + const uint32_t kpw = VLEN / es; + + const uint32_t cs = fastmodulo(unit, n_cs, &kp->window.div_cs); + const uint32_t u_cc = fastdiv(unit, &kp->window.div_cs); + const uint32_t cc = fastmodulo(u_cc, kp->window.n_cc, &kp->window.div_cc); + const uint32_t rt = fastdiv(u_cc, &kp->window.div_cc); + const uint32_t co0 = (wc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, (uint32_t) kernel->ne[3] - co0); + const uint32_t c0 = cc * 32 + cs * CS; + const uint32_t nk = c0 < Cin ? MIN(CS, Cin - c0) * T : 0; + if (nk == 0 || (kp->window.fold && cs > 0)) { + dma_queue_push(dmaq, dma_make_data(raw, raw), 0, 0, 0, 0); + return; + } + dma_queue_push(dmaq, dma_make_data(raw, kernel->data + (size_t) co0 * kernel->nb[3] + (size_t) c0 * kernel->nb[2]), + (size_t) ((nk + kpw - 1) / kpw) * VLEN, kernel->nb[3], (size_t) nk * es, nco); +} + +// K-contiguous kernel (k = cin * T + t): transpose the 32 cout rows of a packing unit to k rows of 32 cout, then into tiles +__attribute__((noinline)) +static void conv2d_hmx_win_wrows_pack(const struct htp_conv2d_win_context * wc, const uint8_t * raw, uint8_t * xr, HVX_Vector * vin, + HVX_Vector * scratch, uint32_t unit, uint32_t n_cs) { + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * kernel = wc->octx->src[0]; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t Cin = kernel->ne[2]; + const uint32_t Cout = kernel->ne[3]; + const uint32_t T = KW * KH; + const uint32_t n_cc = kp->window.n_cc; + const uint32_t CS = kp->window.w_cs; + const bool is_f16 = kernel->type == HTP_TYPE_F16; + const uint32_t kpw = is_f16 ? 64 : 32; // k per vector + const uint32_t rstep = is_f16 ? 64 : 128; // bytes per transposed k row + + const uint32_t cs = fastmodulo(unit, n_cs, &kp->window.div_cs); + const uint32_t u_cc = fastdiv(unit, &kp->window.div_cs); + const uint32_t cc = fastmodulo(u_cc, n_cc, &kp->window.div_cc); + const uint32_t rt = fastdiv(u_cc, &kp->window.div_cc); + const uint32_t co0 = (wc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, Cout - co0); + const uint32_t c0 = cc * 32 + cs * CS; + const uint32_t nc = c0 < Cin ? MIN(CS, Cin - c0) : 0; + const uint32_t nk = nc * T; + const uint32_t nvec = (nk + kpw - 1) / kpw; + const size_t rs = (size_t) nvec * VLEN; + + if (kp->window.fold && cs > 0) { + return; + } + + for (uint32_t b = 0; b < nvec; b++) { + // rows past nco are in the buffer but not loaded + for (uint32_t o = 0; o < 32; o++) { + vin[o] = conv2d_keep(*(const HVX_Vector *) (raw + o * rs + (size_t) b * VLEN), o < nco); + } + HVX_Vector * xo = (HVX_Vector *) (xr + (size_t) b * 32 * VLEN); + conv2d_transpose_w32(vin, 1, scratch, xo, xo + 16); + if (is_f16) { + for (uint32_t i = 0; i < 32; i++) { + xo[i] = Q6_Vh_vdeal_Vh(xo[i]); + } + } + } + + // rows past the valid ones are still inside xr, so they are loaded and masked like the rows of vin + const HVX_Vector zero = Q6_V_vzero(); + if (kp->window.fold) { + // tile kh, crouton channel kw * Cin + c is k row c * T + kh * KW + kw + for (uint32_t kh = 0; kh < KH; kh++) { + HVX_Vector * tile = (HVX_Vector *) (wc->w_tiles + ((size_t) (rt * KH + kh) * n_cc + cc) * HMX_FP16_TILE_N_ELMS); + uint32_t kw = 0; + uint32_t c = 0; + for (uint32_t p = 0; p < 16; p++) { + const HVX_Vector a = conv2d_keep(hvx_vmemu(xr + (size_t) (c * T + kh * KW + kw) * rstep), kw < KW); + if (++c == Cin) { + c = 0; + kw++; + } + const HVX_Vector b = conv2d_keep(hvx_vmemu(xr + (size_t) (c * T + kh * KW + kw) * rstep), kw < KW); + if (++c == Cin) { + c = 0; + kw++; + } + tile[p] = is_f16 ? Q6_V_lo_W(Q6_W_vshuff_VVR(b, a, -2)) : conv2d_f32_to_f16_shuff_z(a, b, zero); + } + } + return; + } + + // tile (t, cc) vector p takes cin rows 2p, 2p + 1 of this step + for (uint32_t t = 0; t < T; t++) { + HVX_Vector * tile = (HVX_Vector *) (wc->w_tiles + ((size_t) (rt * T + t) * n_cc + cc) * HMX_FP16_TILE_N_ELMS); + for (uint32_t pc = 0; pc < CS; pc += 2) { + const uint32_t c = cs * CS + pc; + const uint32_t p = c / 2; + const HVX_Vector a = conv2d_keep(hvx_vmemu(xr + (size_t) ((pc + 0) * T + t) * rstep), pc + 0 < nc); + const HVX_Vector b = conv2d_keep(hvx_vmemu(xr + (size_t) ((pc + 1) * T + t) * rstep), pc + 1 < nc); + tile[p] = is_f16 ? Q6_V_lo_W(Q6_W_vshuff_VVR(b, a, -2)) : conv2d_f32_to_f16_shuff_z(a, b, zero); + } + } +} + +static void conv2d_hmx_win_wpack_rows(const struct htp_conv2d_win_context * wc, unsigned int nth, unsigned int ith) { + struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * kernel = octx->src[0]; + + const uint32_t T = kernel->ne[0] * kernel->ne[1]; + const uint32_t CS = kp->window.w_cs; + const uint32_t kpw = kernel->type == HTP_TYPE_F16 ? 64 : 32; // k per vector + + const size_t wraw = (size_t) 32 * ((CS * T + kpw - 1) / kpw) * VLEN; + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * raws[2] = { wc->thr_base + (size_t) ith * kp->thr_size, wc->thr_base + (size_t) ith * kp->thr_size + wraw }; + uint8_t * xr = raws[1] + wraw; + HVX_Vector * vin = (HVX_Vector *) (xr + wraw); + HVX_Vector * scratch = vin + 32; + + const uint32_t n_cs = (32 + CS - 1) / CS; + const uint32_t n_units = wc->n_rt * kp->window.n_cc * n_cs; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + // one DMA per unit: push(N), push(N + 1), pop(N), pack(N), push(N + 2), ... + for (uint32_t k = 0, unit = ith; k < 2 && unit < n_units; k++, unit += nth) { + conv2d_hmx_win_wrows_dma(wc, dmaq, raws[k], unit, n_cs); + } + for (uint32_t unit = ith, k = 0; unit < n_units; unit += nth, k++) { + uint8_t * raw = raws[k & 1]; + + dma_queue_pop(dmaq); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) unit); + conv2d_hmx_win_wrows_pack(wc, raw, xr, vin, scratch, unit, n_cs); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_PREP, (uint16_t) unit); + + if (unit + 2 * nth < n_units) { + conv2d_hmx_win_wrows_dma(wc, dmaq, raw, unit + 2 * nth, n_cs); + } + } +} + +static void conv2d_hmx_win_wpack_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_win_context * wc = (const struct htp_conv2d_win_context *) data; + + if (wc->kp->w_kmajor) { + conv2d_hmx_win_wpack_kmajor(wc, nth, ith); + } else { + conv2d_hmx_win_wpack_rows(wc, nth, ith); + } +} + +// Fill stage with input pixels [ua, ub): whcn stage[c][u - ua], cwhn stage[u - ua][c]. Zero outside the image. +// Returns the number of DMAs pushed. +static uint32_t conv2d_hmx_win_stage(const struct htp_conv2d_win_context * wc, dma_queue * dmaq, float * stage, uint32_t ua, uint32_t ub) { + const struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * input = octx->src[1]; + + const uint32_t IW = input->ne[0]; + const uint32_t IH = input->ne[1]; + const uint32_t Cin = input->ne[2]; + const uint32_t N = input->ne[3]; + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const uint32_t p0 = octx->op_params[2]; + const uint32_t p1 = octx->op_params[3]; + const uint32_t span = kp->window.seg_b * 32; + const bool cwhn = kp->cwhn; + + // rows of one image are contiguous when there is no column padding + const bool rows_contig = p0 == 0 && input->nb[1] == (size_t) IW * input->nb[0]; + + uint32_t nd = 0; + uint32_t u = ua; + while (u < ub) { + const uint32_t vr = fastdiv(u, &kp->window.div_sr); + const uint32_t col = u - vr * SR; + const uint32_t n = fastdiv(vr, &kp->window.div_ihs); + const uint32_t r = vr - n * IHS; + const int32_t ih = (int32_t) r - (int32_t) p1; + + uint32_t end = MIN(ub, (vr + 1) * SR); + if (n >= N || ih < 0 || ih >= (int32_t) IH) { + const uint32_t len = end - u; + if (cwhn) { + hvx_splat_f32_u(stage + (size_t) (u - ua) * Cin, 0.0f, len * Cin); + } else { + for (uint32_t c = 0; c < Cin; c++) { + hvx_splat_f32_u(stage + (size_t) c * span + (u - ua), 0.0f, len); + } + } + u = end; + continue; + } + + if (rows_contig) { + end = MIN(ub, (vr + (IH - (uint32_t) ih)) * SR); + } + + // valid columns [a, b) of the first row, all columns of the following rows + const uint32_t a = MAX(col, p0); + const uint32_t len = end - u; + uint32_t b = MIN(col + len, p0 + IW); + if (rows_contig) { + b = col + len; + } + + if (a > col) { + const uint32_t z = MIN(a, col + len) - col; + if (cwhn) { + hvx_splat_f32_u(stage + (size_t) (u - ua) * Cin, 0.0f, z * Cin); + } else { + for (uint32_t c = 0; c < Cin; c++) { + hvx_splat_f32_u(stage + (size_t) c * span + (u - ua), 0.0f, z); + } + } + } + if (b < col + len) { + const uint32_t z0 = MAX(a, b); + const uint32_t z = col + len - z0; + if (cwhn) { + hvx_splat_f32_u(stage + (size_t) (u - ua + z0 - col) * Cin, 0.0f, z * Cin); + } else { + for (uint32_t c = 0; c < Cin; c++) { + hvx_splat_f32_u(stage + (size_t) c * span + (u - ua + z0 - col), 0.0f, z); + } + } + } + if (b > a) { + const dma_addr_t src = input->data + (size_t) n * input->nb[3] + (size_t) ih * input->nb[1] + (size_t) (a - p0) * input->nb[0]; + const uint32_t off = u - ua + (a - col); + if (cwhn) { + const size_t sz = (size_t) (b - a) * Cin * sizeof(float); + dma_queue_push(dmaq, dma_make_data(stage + (size_t) off * Cin, src), sz, sz, sz, 1); + } else { + dma_queue_push(dmaq, dma_make_data(stage + off, src), (size_t) span * sizeof(float), input->nb[2], + (size_t) (b - a) * sizeof(float), Cin); + } + nd++; + } + u = end; + } + return nd; +} + +// Fold staging: stage holds the raw input rows of the virtual rows of [ua, ub), after 128 bytes of slack for reads before +// the first row. whcn: raw[c][vr - vr_a][iw], cwhn: raw[vr - vr_a][iw][c]. +// Folded pixel (kw * Cin + c, u = vr * OW + ow) is input pixel (vr, ow + kw * d0 - p0), channel c. +static inline float * conv2d_hmx_win_fold_raw(float * stage) { + return stage + VLEN_FP32; +} + +static inline uint32_t conv2d_hmx_win_fold_rplane(const struct htp_conv2d_win_context * wc) { + const uint32_t IW = wc->octx->src[1]->ne[0]; + return ((wc->kp->window.seg_b * 32 + wc->kp->window.sr - 1) / wc->kp->window.sr + 1) * IW; +} + +// DMA the raw input rows of [ua, ub), returns the number of DMAs pushed +static uint32_t conv2d_hmx_win_stage_fold(const struct htp_conv2d_win_context * wc, dma_queue * dmaq, float * stage, uint32_t ua, uint32_t ub) { + const struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * input = octx->src[1]; + + const uint32_t IW = input->ne[0]; + const int32_t IH = input->ne[1]; + const uint32_t Cin = input->ne[2]; + const uint32_t N = input->ne[3]; + const uint32_t IHS = kp->window.ihs; + const int32_t p1 = octx->op_params[3]; + const uint32_t RP = conv2d_hmx_win_fold_rplane(wc); + const bool cont = input->nb[1] == (size_t) IW * input->nb[0]; + float * raw = conv2d_hmx_win_fold_raw(stage); + + const uint32_t vr_a = fastdiv(ua, &kp->window.div_sr); + const uint32_t vr_b = fastdiv(ub - 1, &kp->window.div_sr) + 1; + + uint32_t nd = 0; + for (uint32_t vr = vr_a; vr < vr_b;) { + const uint32_t n = fastdiv(vr, &kp->window.div_ihs); + const int32_t ih = (int32_t) (vr - n * IHS) - p1; + if (n >= N || ih < 0 || ih >= IH) { + vr++; + continue; + } + // rows of one image are contiguous in DDR + const uint32_t nr = cont ? MIN(vr_b - vr, (uint32_t) (IH - ih)) : 1; + const dma_addr_t src = input->data + (size_t) n * input->nb[3] + (size_t) ih * input->nb[1]; + if (kp->cwhn) { + // raw[vr - vr_a][iw][c] + const size_t sz = (size_t) nr * IW * Cin * sizeof(float); + dma_queue_push(dmaq, dma_make_data(raw + (size_t) (vr - vr_a) * IW * Cin, src), sz, sz, sz, 1); + } else { + dma_queue_push(dmaq, dma_make_data(raw + (size_t) (vr - vr_a) * IW, src), (size_t) RP * sizeof(float), input->nb[2], + (size_t) nr * IW * sizeof(float), Cin); + } + nd++; + vr += nr; + } + return nd; +} + +// Build croutons [ba, ba + nb) (relative to the chunk crouton base b0) from a filled stage +static void conv2d_hmx_win_croutons(const struct htp_conv2d_win_context * wc, const float * stage, __fp16 * act, uint32_t bo, uint32_t nb) { + const struct htp_conv2d_kernel_params * kp = wc->kp; + const uint32_t Cin = wc->octx->src[1]->ne[2] * (kp->window.fold ? wc->octx->src[0]->ne[0] : 1); + const uint32_t n_cc = kp->window.n_cc; + const uint32_t span = kp->window.seg_b * 32; + const size_t pl = (size_t) kp->window.n_bc * HMX_FP16_TILE_N_ELMS; + const HVX_Vector zero = Q6_V_vzero(); + + if (wc->n_scat) { + // word j of the [c = 2k | c = 2k + 1] pixel pairs goes to (j % 16) * 128 + (2k + j / 16) * 4 + const HVX_Vector soff = *(const HVX_Vector *) conv2d_hmx_win_scat_off; + for (uint32_t i = 0; i < nb; i++) { + const size_t dst = (size_t) (act + (size_t) (bo + i) * HMX_FP16_TILE_N_ELMS); + for (uint32_t k = 0; k < wc->n_scat; k++) { + const HVX_Vector a = *(const HVX_Vector *) (stage + (size_t) (2 * k) * span + i * 32); + const HVX_Vector b = 2 * k + 1 < Cin ? *(const HVX_Vector *) (stage + (size_t) (2 * k + 1) * span + i * 32) : zero; + const HVX_VectorPred q = Q6_Q_vsetq2_R(2 * k + 1 < Cin ? VLEN : VLEN / 2); + Q6_vscatter_QRMVwV(q, dst, HMX_FP16_TILE_SIZE - 1, Q6_Vw_vadd_VwVw(soff, Q6_V_vsplat_R(8 * k)), conv2d_f32_to_f16(a, b)); + } + } + if (nb > 0) { + hvx_gather_sync(act + (size_t) (bo + nb - 1) * HMX_FP16_TILE_N_ELMS); + } + return; + } + + if (kp->cwhn) { + for (uint32_t cc = 0; cc < n_cc; cc++) { + const uint32_t nc = MIN(32, Cin - cc * 32); + const HVX_VectorPred qc = Q6_Q_vsetq2_R(nc * sizeof(float)); + for (uint32_t i = 0; i < nb; i++) { + HVX_Vector * dst = (HVX_Vector *) (act + cc * pl + (size_t) (bo + i) * HMX_FP16_TILE_N_ELMS); + const float * src = stage + (size_t) i * 32 * Cin + cc * 32; + for (uint32_t v = 0; v < 16; v++) { + const HVX_Vector a = Q6_V_vmux_QVV(qc, hvx_vmemu(src + (size_t) (2 * v + 0) * Cin), zero); + const HVX_Vector b = Q6_V_vmux_QVV(qc, hvx_vmemu(src + (size_t) (2 * v + 1) * Cin), zero); + dst[v] = conv2d_f32_to_f16_shuff(a, b); + } + } + } + return; + } + + HVX_Vector y[16]; + for (uint32_t cc = 0; cc < n_cc; cc++) { + const uint32_t nv = MIN(32, Cin - cc * 32); + const uint32_t sv = span / VLEN_FP32; + for (uint32_t i = 0; i < nb; i++) { + // channel rows are span apart, walk them with one pointer + const HVX_Vector * p = (const HVX_Vector *) (stage + (size_t) cc * 32 * span + i * 32); + HVX_Vector * dst = (HVX_Vector *) (act + cc * pl + (size_t) (bo + i) * HMX_FP16_TILE_N_ELMS); + if (nv == 32) { + #pragma unroll + for (uint32_t k = 0; k < 16; k++) { + const HVX_Vector a = p[0]; + const HVX_Vector b = p[sv]; + p += 2 * sv; + y[k] = conv2d_f32_to_f16(a, b); + } + } else { + // partial chunk: channel pairs go to the crouton memory first, the transpose runs on the reloaded rows + uint32_t k = 0; + for (; k < nv / 2; k++) { + dst[k] = conv2d_f32_to_f16(p[0], p[sv]); + p += 2 * sv; + } + if (nv & 1) { + dst[k++] = conv2d_f32_to_f16(p[0], zero); + } + for (; k < 16; k++) { + dst[k] = zero; + } + #pragma unroll + for (uint32_t k = 0; k < 16; k++) { + y[k] = dst[k]; + } + } + conv2d_xpose_w16(y); + #pragma unroll + for (uint32_t v = 0; v < 16; v++) { + dst[v] = y[conv2d_xpose_slot(v)]; + } + } + } +} + +// Fold: one crouton channel vector (32 pixels u0..u0+31), assembled from the row pieces of the block +struct conv2d_hmx_win_fold_piece { + int32_t off; // raw offset of lane 0 for kw = 0, c = 0 + int32_t l0; // lanes [l0, l1) of this row + int32_t l1; + int32_t lb; // lane of iw = 0 for kw = 0 +}; + +// Lanes of a row piece that read inside the image for column shift sh +static inline HVX_VectorPred conv2d_hmx_win_fold_q(const struct conv2d_hmx_win_fold_piece * pc, int32_t sh, int32_t IW) { + const int32_t lo = MAX(pc->l0, pc->lb - sh); + const int32_t hi = MIN(pc->l1, pc->lb - sh + IW); + if (hi <= lo) { + return Q6_Q_vsetq_R(0); + } + return Q6_Q_and_QQn(Q6_Q_vsetq2_R(hi * sizeof(float)), Q6_Q_vsetq_R(lo * sizeof(float))); +} + +static void conv2d_hmx_win_croutons_fold(const struct htp_conv2d_win_context * wc, const float * stage, __fp16 * act, uint32_t bo, + uint32_t nb, uint32_t ua) { + const struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * input = octx->src[1]; + + const int32_t IW = input->ne[0]; + const int32_t IH = input->ne[1]; + const uint32_t Cin = input->ne[2]; + const uint32_t N = input->ne[3]; + const uint32_t KW = octx->src[0]->ne[0]; + const uint32_t nch = KW * Cin; + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const int32_t p0 = octx->op_params[2]; + const int32_t p1 = octx->op_params[3]; + const int32_t d0 = octx->op_params[4]; + const uint32_t RP = conv2d_hmx_win_fold_rplane(wc); + const float * raw = conv2d_hmx_win_fold_raw((float *) stage); + + const uint32_t vr_a = fastdiv(ua, &kp->window.div_sr); + const HVX_Vector zero = Q6_V_vzero(); + const HVX_Vector soff = *(const HVX_Vector *) conv2d_hmx_win_scat_off; + + for (uint32_t i = 0; i < nb; i++) { + const uint32_t u0 = ua + 32 * i; + + struct conv2d_hmx_win_fold_piece pc[4]; + uint32_t np = 0; + for (uint32_t vr = fastdiv(u0, &kp->window.div_sr); vr * SR < u0 + 32 && np < 4; vr++) { + const uint32_t n = fastdiv(vr, &kp->window.div_ihs); + const int32_t ih = (int32_t) (vr - n * IHS) - p1; + if (n >= N || ih < 0 || ih >= IH) { + continue; + } + const int32_t l0 = (int32_t) (MAX(u0, vr * SR) - u0); + const int32_t ow0 = (int32_t) (MAX(u0, vr * SR) - vr * SR); + pc[np].l0 = l0; + pc[np].l1 = (int32_t) (MIN(u0 + 32, (vr + 1) * SR) - u0); + pc[np].lb = l0 - ow0 + p0; + pc[np].off = (int32_t) ((vr - vr_a) * IW) + ow0 - l0 - p0; + np++; + } + + __fp16 * dst = act + (size_t) (bo + i) * HMX_FP16_TILE_N_ELMS; + if (np == 0) { + HVX_Vector * d = (HVX_Vector *) dst; + for (uint32_t v = 0; v < 16; v++) { + d[v] = zero; + } + continue; + } + + // channel ch = kw * Cin + c. Channel pairs go to the crouton memory first, the transpose runs on the reloaded rows. + // Lanes and offsets of the row pieces depend on kw only. + HVX_Vector * d = (HVX_Vector *) dst; + const bool scat = wc->n_scat != 0; + HVX_Vector pa = zero; + uint32_t ch = 0; + for (uint32_t kw = 0; kw < KW; kw++) { + const int32_t sh = (int32_t) kw * d0; + const HVX_VectorPred q0 = conv2d_hmx_win_fold_q(&pc[0], sh, IW); + const HVX_VectorPred q1 = np > 1 ? conv2d_hmx_win_fold_q(&pc[1], sh, IW) : q0; + const HVX_VectorPred q2 = np > 2 ? conv2d_hmx_win_fold_q(&pc[2], sh, IW) : q0; + const HVX_VectorPred q3 = np > 3 ? conv2d_hmx_win_fold_q(&pc[3], sh, IW) : q0; + const int32_t f0 = pc[0].off + sh; + const int32_t f1 = np > 1 ? pc[1].off + sh : f0; + const int32_t f2 = np > 2 ? pc[2].off + sh : f0; + const int32_t f3 = np > 3 ? pc[3].off + sh : f0; + + for (uint32_t c = 0; c < Cin; c++, ch++) { + const float * r = raw + (size_t) c * RP; + HVX_Vector x = Q6_V_vmux_QVV(q0, hvx_vmemu(r + f0), zero); + if (np > 1) { + x = Q6_V_vmux_QVV(q1, hvx_vmemu(r + f1), x); + } + if (np > 2) { + x = Q6_V_vmux_QVV(q2, hvx_vmemu(r + f2), x); + } + if (np > 3) { + x = Q6_V_vmux_QVV(q3, hvx_vmemu(r + f3), x); + } + if (!(ch & 1)) { + pa = x; + continue; + } + const HVX_Vector y = conv2d_f32_to_f16(pa, x); + if (scat) { + Q6_vscatter_QRMVwV(Q6_Q_vsetq2_R(VLEN), (size_t) dst, HMX_FP16_TILE_SIZE - 1, + Q6_Vw_vadd_VwVw(soff, Q6_V_vsplat_R(4 * (ch - 1))), y); + } else { + d[ch / 2] = y; + } + } + } + if (ch & 1) { + const HVX_Vector y = conv2d_f32_to_f16(pa, zero); + if (scat) { + Q6_vscatter_QRMVwV(Q6_Q_vsetq2_R(VLEN / 2), (size_t) dst, HMX_FP16_TILE_SIZE - 1, + Q6_Vw_vadd_VwVw(soff, Q6_V_vsplat_R(4 * (ch - 1))), y); + } else { + d[ch / 2] = y; + } + ch++; + } + if (!scat) { + for (uint32_t k = ch / 2; k < 16; k++) { + d[k] = zero; + } + } + if (scat) { + continue; + } + + HVX_Vector y[16]; + #pragma unroll + for (uint32_t k = 0; k < 16; k++) { + y[k] = d[k]; + } + conv2d_xpose_w16(y); + #pragma unroll + for (uint32_t v = 0; v < 16; v++) { + d[v] = y[conv2d_xpose_slot(v)]; + } + } + if (wc->n_scat && nb > 0) { + hvx_gather_sync(act + (size_t) (bo + nb - 1) * HMX_FP16_TILE_N_ELMS); + } +} + +// Fold, cwhn with d0 = 1: the KW * Cin folded channels of a pixel are contiguous in the raw row +static void conv2d_hmx_win_croutons_fold_cwhn(const struct htp_conv2d_win_context * wc, const float * stage, __fp16 * act, uint32_t bo, + uint32_t nb, uint32_t ua) { + const struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * input = octx->src[1]; + + const int32_t IW = input->ne[0]; + const int32_t IH = input->ne[1]; + const int32_t Cin = input->ne[2]; + const uint32_t N = input->ne[3]; + const int32_t KW = octx->src[0]->ne[0]; + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const int32_t p0 = octx->op_params[2]; + const int32_t p1 = octx->op_params[3]; + const float * raw = conv2d_hmx_win_fold_raw((float *) stage); + + const uint32_t vr_a = fastdiv(ua, &kp->window.div_sr); + const HVX_Vector zero = Q6_V_vzero(); + + uint32_t vr = vr_a; + uint32_t ow = ua - vr * SR; + bool ok = false; + for (uint32_t i = 0; i < nb; i++) { + HVX_Vector * dst = (HVX_Vector *) (act + (size_t) (bo + i) * HMX_FP16_TILE_N_ELMS); + HVX_Vector pa = zero; + for (uint32_t j = 0; j < 32; j++) { + if (ow == 0 || (i == 0 && j == 0)) { + const uint32_t n = fastdiv(vr, &kp->window.div_ihs); + const int32_t ih = (int32_t) (vr - n * IHS) - p1; + ok = n < N && ih >= 0 && ih < IH; + } + HVX_Vector x = zero; + if (ok) { + // folded channels kw * Cin + c read input column ow + kw - p0, valid for kw in [p0 - ow, p0 + IW - ow) + const int32_t lo = MAX(0, p0 - (int32_t) ow) * Cin; + const int32_t hi = MIN(KW, p0 + IW - (int32_t) ow) * Cin; + if (hi > lo) { + const float * src = raw + ((int32_t) ((vr - vr_a) * IW + ow) - p0) * Cin; + const HVX_VectorPred q = Q6_Q_and_QQn(Q6_Q_vsetq2_R(hi * sizeof(float)), Q6_Q_vsetq_R(lo * sizeof(float))); + x = Q6_V_vmux_QVV(q, hvx_vmemu(src), zero); + } + } + if (j & 1) { + dst[j / 2] = conv2d_f32_to_f16_shuff(pa, x); + } else { + pa = x; + } + if (++ow == SR) { + ow = 0; + vr++; + } + } + } +} + +static void conv2d_hmx_win_pack(const struct htp_conv2d_win_context * wc, unsigned int nth, unsigned int ith) { + struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + + uint32_t ts; + const uint32_t nt = conv2d_hmx_win_chunk_tiles(wc, wc->pack_chunk, &ts); + const uint32_t ncb = MIN(kp->window.n_bc, nt + (kp->window.max_off >> 5) + 1); + const uint32_t bpt = (ncb + nth - 1) / nth; + const uint32_t b0 = MIN(ith * bpt, ncb); + const uint32_t b1 = MIN(b0 + bpt, ncb); + + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * thr = wc->thr_base + (size_t) ith * kp->thr_size; + float * stages[2] = { (float *) thr, (float *) (thr + kp->stage_size) }; + __fp16 * act = wc->act[wc->pack_chunk & 1]; + + uint32_t (*stage_fn)(const struct htp_conv2d_win_context *, dma_queue *, float *, uint32_t, uint32_t) = + kp->window.fold ? conv2d_hmx_win_stage_fold : conv2d_hmx_win_stage; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + const uint32_t SB = kp->window.seg_b; + + if (b0 >= b1) { + return; + } + + // push(N), push(N + 1), pop(N), croutons(N), push(N + 2), ... + uint32_t nd[2] = { 0, 0 }; + for (uint32_t i = 0; i < 2 && b0 + i * SB < b1; i++) { + const uint32_t b = b0 + i * SB; + nd[i] += stage_fn(wc, dmaq, stages[i], (ts + b) * 32, (ts + MIN(b + SB, b1)) * 32); + } + + uint32_t si = 0; + for (uint32_t b = b0; b < b1; b += SB) { + const uint32_t nb = MIN(SB, b1 - b); + + for (uint32_t p = 0; p < nd[si]; p++) { + dma_queue_pop(dmaq); + } + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) b); + if (kp->window.fold && kp->cwhn) { + conv2d_hmx_win_croutons_fold_cwhn(wc, stages[si], act, b, nb, (ts + b) * 32); + } else if (kp->window.fold) { + conv2d_hmx_win_croutons_fold(wc, stages[si], act, b, nb, (ts + b) * 32); + } else { + conv2d_hmx_win_croutons(wc, stages[si], act, b, nb); + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) b); + + const uint32_t bn = b + 2 * SB; + nd[si] = bn < b1 ? stage_fn(wc, dmaq, stages[si], (ts + bn) * 32, (ts + MIN(bn + SB, b1)) * 32) : 0; + si ^= 1; + } +} + +static void conv2d_hmx_win_unpack(const struct htp_conv2d_win_context * wc, unsigned int nth, unsigned int ith) { + struct htp_ops_context * octx = wc->octx; + const struct htp_conv2d_kernel_params * kp = wc->kp; + const struct htp_tensor * dst = octx->dst; + + const uint32_t OW = dst->ne[0]; + const uint32_t OH = dst->ne[1]; + const uint32_t Cout = dst->ne[2]; + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const uint32_t ST = kp->window.seg_t; + const uint32_t OS = ST * 32; + + uint32_t ts; + const uint32_t nt = conv2d_hmx_win_chunk_tiles(wc, wc->unpack_chunk, &ts); + const uint32_t tpt = (nt + nth - 1) / nth; + const uint32_t i0 = MIN(ith * tpt, nt); + const uint32_t i1 = MIN(i0 + tpt, nt); + + dma_queue * dmaq = octx->ctx->dma[ith]; + uint8_t * thr = wc->thr_base + (size_t) ith * kp->thr_size + 2 * (size_t) kp->stage_size; + float * obuf = (float *) thr; + __fp16 * out = wc->out[wc->unpack_chunk & 1]; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + // nd[bi] = DMAs pushed from obuf bi, popped before it is reused HTP_CONV2D_WIN_OBUF steps later + uint32_t nd[HTP_CONV2D_WIN_OBUF] = { 0 }; + uint32_t bi = 0; + + const bool rows_contig = SR == OW && dst->nb[1] == OW * sizeof(float); + + for (uint32_t i = i0; i < i1; i += ST) { + const uint32_t ni = MIN(ST, i1 - i); + const uint32_t q_lo = (ts + i) * 32; + const uint32_t q_hi = q_lo + ni * 32; + + for (uint32_t rt = 0; rt < wc->n_rt; rt++) { + const uint32_t co0 = (wc->rt0 + rt) * 32; + const uint32_t nco = MIN(32, Cout - co0); + const uint32_t npr = (nco + 1) / 2; + const HVX_Vector restore = conv2d_hmx_rt_restore(wc->scales, rt); + + for (uint32_t p = 0; p < nd[bi]; p++) { + dma_queue_pop(dmaq); + } + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) i); + float * ob = obuf + (size_t) bi * 32 * OS; + for (uint32_t g = 0; g < ni; g++) { + HVX_Vector * tv = (HVX_Vector *) (out + ((size_t) rt * kp->ct_chunk + i + g) * HMX_FP16_TILE_N_ELMS); + HVX_Vector y[16]; + #pragma unroll + for (uint32_t v = 0; v < 16; v++) { + y[conv2d_xpose_slot(v)] = tv[v]; + } + conv2d_unxpose_w16(y); + // rows go back in place and are converted by a second loop, both in one loop spill vector registers + #pragma unroll + for (uint32_t k = 0; k < 16; k++) { + tv[k] = y[k]; + } + HVX_Vector * o = (HVX_Vector *) (ob + g * 32); + for (uint32_t k = 0; k < npr; k++) { + const HVX_VectorPair pr = hvx_vec_f16_to_f32(tv[k]); + o[(2 * k + 0) * (OS / 32)] = hvx_vec_mul_f32_f32(Q6_V_lo_W(pr), restore); + o[(2 * k + 1) * (OS / 32)] = hvx_vec_mul_f32_f32(Q6_V_hi_W(pr), restore); + } + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) i); + + // write the valid part of each virtual row in [q_lo, q_hi) + nd[bi] = 0; + uint32_t vr = fastdiv(q_lo, &kp->window.div_sr); + for (; vr * SR < q_hi; vr++) { + const uint32_t n = fastdiv(vr, &kp->window.div_ihs); + const uint32_t oh = vr - n * IHS; + if (vr < wc->vr0 || vr >= wc->vr1 || oh >= OH) { + continue; + } + const uint32_t base = vr * SR; + const uint32_t a = q_lo > base ? q_lo - base : 0; + uint32_t b = MIN(OW, q_hi - base); + if (b <= a) { + continue; + } + const dma_addr_t ddr = dst->data + (size_t) n * dst->nb[3] + (size_t) oh * dst->nb[1] + (size_t) co0 * dst->nb[2] + (size_t) a * sizeof(float); + + // no gap between rows: extend over the following rows of this image + if (rows_contig) { + uint32_t r = 1; + while (oh + r < OH && vr + r < wc->vr1 && (vr + r) * SR < q_hi) { + r++; + } + b = MIN(q_hi - base, (r - 1) * SR + OW); + vr += r - 1; + } + dma_queue_push(dmaq, dma_make_data(ddr, ob + (base + a - q_lo)), dst->nb[2], (size_t) OS * sizeof(float), + (size_t) (b - a) * sizeof(float), nco); + nd[bi]++; + } + bi = bi + 1 == HTP_CONV2D_WIN_OBUF ? 0 : bi + 1; + } + } + + for (uint32_t k = 0; k < HTP_CONV2D_WIN_OBUF; k++) { + for (uint32_t p = 0; p < nd[k]; p++) { + dma_queue_pop(dmaq); + } + } +} + +// per-thread callback for one pipeline phase +static void conv2d_hmx_win_phase_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_win_context * wc = (const struct htp_conv2d_win_context *) data; + + if (wc->unpack_chunk >= 0) { + conv2d_hmx_win_unpack(wc, nth, ith); + } + // weights of this rt block are packed before its first chunk + if (wc->pack_chunk == 0) { + const struct htp_tensor * kernel = wc->octx->src[0]; + const uint32_t n_wt = (wc->kp->window.fold ? kernel->ne[1] : kernel->ne[0] * kernel->ne[1]) * wc->kp->window.n_cc; + for (uint32_t rt = ith; rt < wc->n_rt; rt += nth) { + conv2d_hmx_rt_scale(wc->scales + rt * CONV2D_HMX_SCALES_N, wc->w_tiles + (size_t) rt * n_wt * HMX_FP16_TILE_N_ELMS, n_wt, + kernel->ne[0] * kernel->ne[1] * kernel->ne[2]); + } + } + if (wc->pack_chunk >= 0) { + conv2d_hmx_win_pack(wc, nth, ith); + } +} + +// zero out 2 act buffer regions in VTCM before packing +static void conv2d_hmx_win_zero_thread(unsigned int nth, unsigned int ith, void * data) { + const struct htp_conv2d_win_context * wc = (const struct htp_conv2d_win_context *) data; + + const size_t n = 2 * wc->layout.act_size / sizeof(float); + const size_t per = hex_round_up((n + nth - 1) / nth, VLEN_FP32); + const size_t i0 = MIN((size_t) ith * per, n); + const size_t i1 = MIN(i0 + per, n); + + struct htp_thread_trace * tr = &wc->octx->ctx->trace[ith]; + const uint16_t block = (uint16_t) (i0 / VLEN_FP32); + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_PREP, block); + if (i1 > i0) { + hvx_splat_f32_a((uint8_t *) wc->act[0] + i0 * sizeof(float), 0.0f, i1 - i0); + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_PREP, block); +} + +static void conv2d_hmx_win_run_phase(struct htp_conv2d_win_context * wc, int32_t pack, int32_t unpack) { + wc->pack_chunk = pack; + wc->unpack_chunk = unpack; + work_queue_run(wc->octx->ctx->work_queue, conv2d_hmx_win_phase_thread, wc, wc->kp->n_threads); +} + + +// live[i] = tile ts + i has a row that is written. Dead tiles lie inside the rows [OH, IHS) of an image. +static void conv2d_hmx_win_live(const struct htp_conv2d_win_context * wc, uint8_t * live, uint32_t ts, uint32_t nt) { + const struct htp_conv2d_kernel_params * kp = wc->kp; + + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const uint32_t OH = wc->octx->dst->ne[1]; + const uint32_t q0 = ts * 32; + const uint32_t q1 = (ts + nt) * 32; + + memset(live, 1, nt); + for (uint32_t n = fastdiv(fastdiv(q0, &kp->window.div_sr), &kp->window.div_ihs); n * IHS * SR < q1; n++) { + const uint32_t g0 = MAX((n * IHS + OH) * SR, q0); + const uint32_t g1 = MIN((n + 1) * IHS * SR, q1); + const uint32_t t0 = (g0 + 31) / 32; + const uint32_t t1 = g1 / 32; + if (t1 > t0) { + memset(live + (t0 - ts), 0, t1 - t0); + } + } +} + +static int conv2d_hmx_win(struct htp_ops_context * octx, const struct htp_conv2d_kernel_params * kp) { + const struct htp_tensor * kernel = octx->src[0]; + const struct htp_tensor * dst = octx->dst; + + const uint32_t KW = kernel->ne[0]; + const uint32_t KH = kernel->ne[1]; + const uint32_t OW = dst->ne[0]; + const uint32_t OH = dst->ne[1]; + const uint32_t SR = kp->window.sr; + const uint32_t IHS = kp->window.ihs; + const uint32_t d0 = octx->op_params[4]; + const uint32_t d1 = octx->op_params[5]; + + uint32_t row_base, n_rows; + conv2d_mdev_rows(octx, &row_base, &n_rows); + if (n_rows == 0) { + return HTP_STATUS_OK; + } + + const uint32_t ra = row_base; + const uint32_t rb = row_base + n_rows - 1; + const uint32_t vr0 = (ra / OH) * IHS + ra % OH; + const uint32_t vr1 = (rb / OH) * IHS + rb % OH + 1; + + const size_t tile = 2048; + const uint32_t n_wt = kp->window.fold ? KH : (KW * KH); + const size_t w_size = (size_t) kp->rt_block * n_wt * kp->window.n_cc * tile; + const size_t act_size = (size_t) kp->window.n_cc * kp->window.n_bc * tile; + const size_t out_size = (size_t) kp->rt_block * kp->ct_chunk * tile; + + struct htp_conv2d_vtcm_layout layout; + htp_conv2d_vtcm_layout_build(&layout, kp->rt_block, w_size, act_size, out_size, kp->thr_size, kp->n_threads); + + uint8_t * base = (uint8_t *) octx->ctx->vtcm_base; + + struct htp_conv2d_win_context wctx = { + .octx = octx, + .kp = kp, + .layout = layout, + .scales = VTCM_LAYOUT_PTR(__fp16, base, layout.off_scales), + .w_tiles = VTCM_LAYOUT_PTR(__fp16, base, layout.off_w), + .act = { VTCM_LAYOUT_PTR(__fp16, base, layout.off_act[0]), VTCM_LAYOUT_PTR(__fp16, base, layout.off_act[1]) }, + .out = { VTCM_LAYOUT_PTR(__fp16, base, layout.off_out[0]), VTCM_LAYOUT_PTR(__fp16, base, layout.off_out[1]) }, + .thr_base = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_thr), + .t_base = (vr0 * SR) / 32, + .t_end = ((vr1 - 1) * SR + OW + 31) / 32, + .vr0 = vr0, + .vr1 = vr1, + }; + + // small Cin: croutons are built by scattering the staged values into zeroed croutons + const uint32_t n_ch = octx->src[1]->ne[2] * (kp->window.fold ? KW : 1); + if (!kp->cwhn && n_ch <= 2 * CONV2D_WIN_SCAT_MAX) { + wctx.n_scat = (n_ch + 1) / 2; + work_queue_run(octx->ctx->work_queue, conv2d_hmx_win_zero_thread, &wctx, kp->n_threads); + } + + const int32_t n_chunks = (int32_t) ((wctx.t_end - wctx.t_base + kp->ct_chunk - 1) / kp->ct_chunk); + const uint32_t rem = n_ch - (kp->window.n_cc - 1) * 32; + + // fold: kw is in the channels, taps are kh only + const uint32_t TW = kp->window.fold ? 1 : KW; + uint32_t * taps = (uint32_t *) octx->ctx->ddr_spad_base; + for (uint32_t kh = 0; kh < KH; kh++) { + for (uint32_t kw = 0; kw < TW; kw++) { + taps[kh * TW + kw] = conv2d_hmx_win_act_off(kh * d1 * SR + kw * d0); + } + } + + wctx.live[0] = (uint8_t *) octx->ctx->ddr_spad_base + hex_round_up(KH * KW * sizeof(uint32_t), 128); + wctx.live[1] = wctx.live[0] + hex_round_up(kp->ct_chunk, 128); + + struct htp_conv2d_win_task task = { + .scales = wctx.scales, + .taps = taps, + .n_taps = TW * KH, + .out_stride = kp->ct_chunk * HMX_FP16_TILE_N_ELMS, + .n_cc = kp->window.n_cc, + .plane = kp->window.n_bc * HMX_FP16_TILE_SIZE, + .rt_last = kp->window.act_rt_last, + .wr_last = (hex_round_up(rem, 8) / 2) * VLEN - 1, + }; + + for (uint32_t rt0 = 0; rt0 < kp->n_row_tiles; rt0 += kp->rt_block) { + wctx.rt0 = rt0; + wctx.n_rt = MIN(kp->rt_block, kp->n_row_tiles - rt0); + work_queue_run(octx->ctx->work_queue, conv2d_hmx_win_wpack_thread, &wctx, kp->n_threads); + + conv2d_hmx_win_run_phase(&wctx, 0, -1); + + for (int32_t c = 0; c < n_chunks; c++) { + uint32_t ts; + const uint32_t nt = conv2d_hmx_win_chunk_tiles(&wctx, c, &ts); + conv2d_hmx_win_live(&wctx, wctx.live[c & 1], ts, nt); + task.live = wctx.live[c & 1]; + task.out = wctx.out[c & 1]; + task.w = wctx.w_tiles; + task.act = wctx.act[c & 1]; + task.n_rt = wctx.n_rt; + task.n_tiles = nt; + hmx_queue_push(octx->ctx->hmx_queue, hmx_queue_make_desc(conv2d_hmx_win_worker, &task)); + + const int32_t pack = c + 1 < n_chunks ? c + 1 : -1; + const int32_t unpack = c - 1; + if (pack >= 0 || unpack >= 0) { + conv2d_hmx_win_run_phase(&wctx, pack, unpack); + } + + hmx_queue_pop(octx->ctx->hmx_queue); + } + + conv2d_hmx_win_run_phase(&wctx, -1, n_chunks - 1); + } + + return HTP_STATUS_OK; +} + +int op_conv_2d(struct htp_ops_context * octx) { + const struct htp_conv2d_kernel_params * kparams = + (const struct htp_conv2d_kernel_params *) octx->kernel_params; + + if (kparams->total_rows == 0) { + return HTP_STATUS_OK; + } + + if (kparams->kernel_type == HTP_CONV2D_KERNEL_HMX_WINDOW) { + return conv2d_hmx_win(octx, kparams); + } + if (kparams->kernel_type == HTP_CONV2D_KERNEL_HMX_TILED) { + return conv2d_hmx_tiled(octx, kparams); + } + + return HTP_STATUS_NO_SUPPORT; +} + +struct conv2d_dw_task_slice { + dma_addr_t src_addr; + dma_addr_t dst_addr; + uint32_t src_bytes; + uint32_t dst_bytes; + uint32_t ih_count; + uint32_t top_pad; + uint32_t bot_pad; + uint32_t oh_start; + uint32_t oh_len; + int32_t ih_first; + uint32_t c; +}; + +static inline void conv2d_dw_get_slice( + struct conv2d_dw_task_slice * slice, + uint32_t task, + const struct htp_tensor * src1, + const struct htp_tensor * dst, + const struct htp_conv2d_dw_kernel_params * kp) { + + uint32_t chunk_idx; + uint32_t n; + uint32_t c = 0; + + if (kp->cwhn) { + n = fastdiv(task, &kp->div_n_chunks); + chunk_idx = task - n * kp->n_chunks; + } else { + const uint32_t plane = fastdiv(task, &kp->div_n_chunks); + chunk_idx = task - plane * kp->n_chunks; + n = fastdiv(plane, &kp->div_c); + c = plane - n * kp->c; + } + + const uint32_t oh_start = chunk_idx * kp->oh_chunk; + const uint32_t oh_len = MIN(kp->oh_chunk, kp->oh - oh_start); + + const int32_t ih_min = (int32_t)(oh_start * kp->s1) - kp->p1; + const int32_t ih_max = (int32_t)((oh_start + oh_len - 1) * kp->s1 + (kp->kh - 1) * kp->d1) - kp->p1; + const uint32_t ih_span = (uint32_t)(ih_max - ih_min + 1); + + const int32_t ih_first = MAX(0, ih_min); + const int32_t ih_last = MIN((int32_t)kp->h - 1, ih_max); + const uint32_t ih_count = (ih_first <= ih_last) ? (uint32_t)(ih_last - ih_first + 1) : 0; + const uint32_t top_pad = (ih_count > 0) ? (uint32_t)(ih_first - ih_min) : ih_span; + const uint32_t bot_pad = ih_span - top_pad - ih_count; + + slice->src_bytes = ih_count * kp->row_src_bytes; + slice->dst_bytes = oh_len * kp->row_dst_bytes; + slice->ih_count = ih_count; + slice->top_pad = top_pad; + slice->bot_pad = bot_pad; + slice->oh_start = oh_start; + slice->oh_len = oh_len; + slice->ih_first = ih_first; + slice->c = c; + + if (kp->cwhn) { + slice->src_addr = src1->data + (size_t) n * src1->nb[3] + (size_t) ih_first * src1->nb[1]; + slice->dst_addr = dst->data + (size_t) n * dst->nb[3] + (size_t) oh_start * dst->nb[1]; + } else { + slice->src_addr = src1->data + (size_t) n * src1->nb[3] + (size_t) c * src1->nb[2] + (size_t) ih_first * src1->nb[1]; + slice->dst_addr = dst->data + (size_t) n * dst->nb[3] + (size_t) c * dst->nb[2] + (size_t) oh_start * dst->nb[1]; + } +} + +static inline HVX_Vector conv2d_dw_splat_w_f32(const void * ptr) { + return hvx_vec_splat_f32(*(const float *) ptr); +} + +static inline HVX_Vector conv2d_dw_splat_w_f16(const void * ptr) { + const HVX_Vector vh = Q6_Vh_vsplat_R(*(const uint16_t *) ptr); + const HVX_Vector v1 = Q6_Vh_vsplat_R(0x3c00); + return Q6_Vsf_equals_Vqf32(Q6_V_lo_W(Q6_Wqf32_vmpy_VhfVhf(vh, v1))); +} + +static inline HVX_Vector conv2d_dw_load_w_f32(const void * ptr) { + return hvx_vmemu(ptr); +} + +static inline HVX_Vector conv2d_dw_load_w_f16(const void * ptr) { + return Q6_V_lo_W(hvx_vec_f16_to_f32(hvx_vmemu(ptr))); +} + +static inline HVX_Vector conv2d_dw_qf32_mpy_add3( + HVX_Vector acc, + HVX_Vector x0, HVX_Vector w0, + HVX_Vector x1, HVX_Vector w1, + HVX_Vector x2, HVX_Vector w2) { + const HVX_Vector p01 = Q6_Vqf32_vadd_Vqf32Vqf32(Q6_Vqf32_vmpy_VsfVsf(x0, w0), Q6_Vqf32_vmpy_VsfVsf(x1, w1)); + const HVX_Vector p2 = Q6_Vqf32_vadd_Vqf32Vqf32(acc, Q6_Vqf32_vmpy_VsfVsf(x2, w2)); + return Q6_Vqf32_vadd_Vqf32Vqf32(p01, p2); +} + +static inline void conv2d_dw_pad_vtcm_k3x3( + float * in_vtcm, + const struct conv2d_dw_task_slice * slice, + uint32_t w_in, + uint32_t extra_bot_rows) { + if (slice->top_pad > 0) { + hvx_splat_f32_a(in_vtcm, 0.0f, slice->top_pad * w_in); + } + const uint32_t tail_zero_rows = slice->bot_pad + extra_bot_rows; + if (tail_zero_rows > 0) { + hvx_splat_f32_a(in_vtcm + (size_t) (slice->top_pad + slice->ih_count) * w_in, 0.0f, tail_zero_rows * w_in); + } +} + +#define DEFINE_CONV2D_DW_WHCN_S1_K3X3(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s1_k3x3_##SUFFIX( \ + const float * restrict in_vtcm, \ + float * restrict out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + const struct htp_tensor * src0 = octx->src[0]; \ + const size_t w_nb0 = src0->nb[0]; \ + const size_t w_nb1 = src0->nb[1]; \ + const char * restrict w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const uint32_t oh_len = slice->oh_len; \ + const uint32_t w_in = kp->w; \ + \ + conv2d_dw_pad_vtcm_k3x3((float *) in_vtcm, slice, w_in, 0); \ + \ + const HVX_Vector w00 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w01 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w02 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w10 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w11 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w12 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w20 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w21 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w22 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + uint32_t ohi = 0; \ + for (; ohi + 4 <= oh_len; ohi += 4) { \ + const float * restrict r0 = in_vtcm + (size_t) ohi * w_in; \ + const float * restrict r1 = r0 + w_in; \ + const float * restrict r2 = r1 + w_in; \ + const float * restrict r3 = r2 + w_in; \ + const float * restrict r4 = r3 + w_in; \ + const float * restrict r5 = r4 + w_in; \ + \ + float * restrict out0 = out_vtcm + (size_t) (ohi + 0) * w_in; \ + float * restrict out1 = out0 + w_in; \ + float * restrict out2 = out1 + w_in; \ + float * restrict out3 = out2 + w_in; \ + \ + HVX_Vector p0 = zero, c0 = hvx_vmem(r0); \ + HVX_Vector p1 = zero, c1 = hvx_vmem(r1); \ + HVX_Vector p2 = zero, c2 = hvx_vmem(r2); \ + HVX_Vector p3 = zero, c3 = hvx_vmem(r3); \ + HVX_Vector p4 = zero, c4 = hvx_vmem(r4); \ + HVX_Vector p5 = zero, c5 = hvx_vmem(r5); \ + \ + for (uint32_t ox = 0; ox < w_in; ox += 32) { \ + const bool has_next = (ox + 32 < w_in); \ + \ + const HVX_Vector n0 = has_next ? hvx_vmem(r0 + ox + 32) : zero; \ + const HVX_Vector l0 = Q6_V_valign_VVR(c0, p0, 124); \ + const HVX_Vector rg0 = Q6_V_valign_VVR(n0, c0, 4); \ + HVX_Vector acc0 = conv2d_dw_qf32_mpy_add3(zero, l0, w00, c0, w01, rg0, w02); \ + p0 = c0; c0 = n0; \ + \ + const HVX_Vector n1 = has_next ? hvx_vmem(r1 + ox + 32) : zero; \ + const HVX_Vector l1 = Q6_V_valign_VVR(c1, p1, 124); \ + const HVX_Vector rg1 = Q6_V_valign_VVR(n1, c1, 4); \ + acc0 = conv2d_dw_qf32_mpy_add3(acc0, l1, w10, c1, w11, rg1, w12); \ + HVX_Vector acc1 = conv2d_dw_qf32_mpy_add3(zero, l1, w00, c1, w01, rg1, w02); \ + p1 = c1; c1 = n1; \ + \ + const HVX_Vector n2 = has_next ? hvx_vmem(r2 + ox + 32) : zero; \ + const HVX_Vector l2 = Q6_V_valign_VVR(c2, p2, 124); \ + const HVX_Vector rg2 = Q6_V_valign_VVR(n2, c2, 4); \ + acc0 = conv2d_dw_qf32_mpy_add3(acc0, l2, w20, c2, w21, rg2, w22); \ + hvx_vmem(out0 + ox) = Q6_Vsf_equals_Vqf32(acc0); \ + acc1 = conv2d_dw_qf32_mpy_add3(acc1, l2, w10, c2, w11, rg2, w12); \ + HVX_Vector acc2 = conv2d_dw_qf32_mpy_add3(zero, l2, w00, c2, w01, rg2, w02); \ + p2 = c2; c2 = n2; \ + \ + const HVX_Vector n3 = has_next ? hvx_vmem(r3 + ox + 32) : zero; \ + const HVX_Vector l3 = Q6_V_valign_VVR(c3, p3, 124); \ + const HVX_Vector rg3 = Q6_V_valign_VVR(n3, c3, 4); \ + acc1 = conv2d_dw_qf32_mpy_add3(acc1, l3, w20, c3, w21, rg3, w22); \ + hvx_vmem(out1 + ox) = Q6_Vsf_equals_Vqf32(acc1); \ + acc2 = conv2d_dw_qf32_mpy_add3(acc2, l3, w10, c3, w11, rg3, w12); \ + HVX_Vector acc3 = conv2d_dw_qf32_mpy_add3(zero, l3, w00, c3, w01, rg3, w02); \ + p3 = c3; c3 = n3; \ + \ + const HVX_Vector n4 = has_next ? hvx_vmem(r4 + ox + 32) : zero; \ + const HVX_Vector l4 = Q6_V_valign_VVR(c4, p4, 124); \ + const HVX_Vector rg4 = Q6_V_valign_VVR(n4, c4, 4); \ + acc2 = conv2d_dw_qf32_mpy_add3(acc2, l4, w20, c4, w21, rg4, w22); \ + hvx_vmem(out2 + ox) = Q6_Vsf_equals_Vqf32(acc2); \ + acc3 = conv2d_dw_qf32_mpy_add3(acc3, l4, w10, c4, w11, rg4, w12); \ + p4 = c4; c4 = n4; \ + \ + const HVX_Vector n5 = has_next ? hvx_vmem(r5 + ox + 32) : zero; \ + const HVX_Vector l5 = Q6_V_valign_VVR(c5, p5, 124); \ + const HVX_Vector rg5 = Q6_V_valign_VVR(n5, c5, 4); \ + acc3 = conv2d_dw_qf32_mpy_add3(acc3, l5, w20, c5, w21, rg5, w22); \ + hvx_vmem(out3 + ox) = Q6_Vsf_equals_Vqf32(acc3); \ + p5 = c5; c5 = n5; \ + } \ + } \ + \ + for (; ohi < oh_len; ++ohi) { \ + const float * restrict r0 = in_vtcm + (size_t) ohi * w_in; \ + const float * restrict r1 = r0 + w_in; \ + const float * restrict r2 = r1 + w_in; \ + float * restrict out_row = out_vtcm + (size_t) ohi * w_in; \ + \ + HVX_Vector p0 = zero, c0 = hvx_vmem(r0); \ + HVX_Vector p1 = zero, c1 = hvx_vmem(r1); \ + HVX_Vector p2 = zero, c2 = hvx_vmem(r2); \ + \ + for (uint32_t ox = 0; ox < w_in; ox += 32) { \ + const bool has_next = (ox + 32 < w_in); \ + \ + const HVX_Vector n0 = has_next ? hvx_vmem(r0 + ox + 32) : zero; \ + const HVX_Vector l0 = Q6_V_valign_VVR(c0, p0, 124); \ + const HVX_Vector rg0 = Q6_V_valign_VVR(n0, c0, 4); \ + HVX_Vector acc = conv2d_dw_qf32_mpy_add3(zero, l0, w00, c0, w01, rg0, w02); \ + p0 = c0; c0 = n0; \ + \ + const HVX_Vector n1 = has_next ? hvx_vmem(r1 + ox + 32) : zero; \ + const HVX_Vector l1 = Q6_V_valign_VVR(c1, p1, 124); \ + const HVX_Vector rg1 = Q6_V_valign_VVR(n1, c1, 4); \ + acc = conv2d_dw_qf32_mpy_add3(acc, l1, w10, c1, w11, rg1, w12); \ + p1 = c1; c1 = n1; \ + \ + const HVX_Vector n2 = has_next ? hvx_vmem(r2 + ox + 32) : zero; \ + const HVX_Vector l2 = Q6_V_valign_VVR(c2, p2, 124); \ + const HVX_Vector rg2 = Q6_V_valign_VVR(n2, c2, 4); \ + acc = conv2d_dw_qf32_mpy_add3(acc, l2, w20, c2, w21, rg2, w22); \ + p2 = c2; c2 = n2; \ + \ + hvx_vmem(out_row + ox) = Q6_Vsf_equals_Vqf32(acc); \ + } \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S1_K3X3(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S1_K3X3(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_WHCN_S2_K3X3_W32(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s2_k3x3_w32_##SUFFIX( \ + const float * restrict in_vtcm, \ + float * restrict out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + (void) kp; \ + const struct htp_tensor * src0 = octx->src[0]; \ + const size_t w_nb0 = src0->nb[0]; \ + const size_t w_nb1 = src0->nb[1]; \ + const char * restrict w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const uint32_t oh_len = slice->oh_len; \ + \ + conv2d_dw_pad_vtcm_k3x3((float *) in_vtcm, slice, 32, (oh_len & 1) ? 2 : 0); \ + \ + const HVX_Vector w00 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w01 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w02 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w10 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w11 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w12 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w20 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w21 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w22 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + const HVX_VectorPred q_not_lane16 = Q6_Q_or_QQn(Q6_Q_vsetq_R(64), Q6_Q_vsetq2_R(68)); \ + const float * restrict in_row = in_vtcm; \ + HVX_Vector v_prev_b2 = hvx_vmem(in_row); \ + in_row += 32; \ + \ + for (uint32_t ohi = 0; ohi < oh_len; ohi += 2) { \ + const HVX_Vector v_a0 = v_prev_b2; \ + const HVX_Vector v_a1 = hvx_vmem(in_row); \ + const HVX_Vector v_a2 = hvx_vmem(in_row + 32); \ + const HVX_Vector v_b0 = v_a2; \ + const HVX_Vector v_b1 = hvx_vmem(in_row + 64); \ + const HVX_Vector v_b2 = hvx_vmem(in_row + 96); \ + in_row += 128; \ + v_prev_b2 = v_b2; \ + \ + const HVX_VectorPair vp0 = Q6_W_vdeal_VVR(v_b0, v_a0, -4); \ + const HVX_Vector ev0 = Q6_V_lo_W(vp0); \ + const HVX_Vector od0 = Q6_V_hi_W(vp0); \ + const HVX_Vector lf0 = Q6_V_vand_QV(q_not_lane16, Q6_V_valign_VVR(od0, zero, 124)); \ + HVX_Vector acc = conv2d_dw_qf32_mpy_add3(zero, lf0, w00, ev0, w01, od0, w02); \ + \ + const HVX_VectorPair vp1 = Q6_W_vdeal_VVR(v_b1, v_a1, -4); \ + const HVX_Vector ev1 = Q6_V_lo_W(vp1); \ + const HVX_Vector od1 = Q6_V_hi_W(vp1); \ + const HVX_Vector lf1 = Q6_V_vand_QV(q_not_lane16, Q6_V_valign_VVR(od1, zero, 124)); \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf1, w10, ev1, w11, od1, w12); \ + \ + const HVX_VectorPair vp2 = Q6_W_vdeal_VVR(v_b2, v_a2, -4); \ + const HVX_Vector ev2 = Q6_V_lo_W(vp2); \ + const HVX_Vector od2 = Q6_V_hi_W(vp2); \ + const HVX_Vector lf2 = Q6_V_vand_QV(q_not_lane16, Q6_V_valign_VVR(od2, zero, 124)); \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf2, w20, ev2, w21, od2, w22); \ + \ + hvx_vmem(out_vtcm + (size_t) ohi * 16) = Q6_Vsf_equals_Vqf32(acc); \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S2_K3X3_W32(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S2_K3X3_W32(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_WHCN_S2_K3X3_W64(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s2_k3x3_w64_##SUFFIX( \ + const float * restrict in_vtcm, \ + float * restrict out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + (void) kp; \ + const struct htp_tensor * src0 = octx->src[0]; \ + const size_t w_nb0 = src0->nb[0]; \ + const size_t w_nb1 = src0->nb[1]; \ + const char * restrict w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const uint32_t oh_len = slice->oh_len; \ + \ + conv2d_dw_pad_vtcm_k3x3((float *) in_vtcm, slice, 64, 0); \ + \ + const HVX_Vector w00 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w01 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w02 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w10 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w11 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w12 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w20 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w21 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w22 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + const float * restrict in_row = in_vtcm; \ + const HVX_VectorPair vp0_init = Q6_W_vdeal_VVR(hvx_vmem(in_row + 32), hvx_vmem(in_row), -4); \ + in_row += 64; \ + HVX_Vector ev0 = Q6_V_lo_W(vp0_init); \ + HVX_Vector od0 = Q6_V_hi_W(vp0_init); \ + HVX_Vector lf0 = Q6_V_valign_VVR(od0, zero, 124); \ + \ + for (uint32_t ohi = 0; ohi < oh_len; ++ohi) { \ + const float * restrict r1_ptr = in_row; \ + const float * restrict r2_ptr = in_row + 64; \ + in_row += 128; \ + \ + HVX_Vector acc = conv2d_dw_qf32_mpy_add3(zero, lf0, w00, ev0, w01, od0, w02); \ + \ + const HVX_VectorPair vp1 = Q6_W_vdeal_VVR(hvx_vmem(r1_ptr + 32), hvx_vmem(r1_ptr), -4); \ + const HVX_Vector ev1 = Q6_V_lo_W(vp1); \ + const HVX_Vector od1 = Q6_V_hi_W(vp1); \ + const HVX_Vector lf1 = Q6_V_valign_VVR(od1, zero, 124); \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf1, w10, ev1, w11, od1, w12); \ + \ + const HVX_VectorPair vp2 = Q6_W_vdeal_VVR(hvx_vmem(r2_ptr + 32), hvx_vmem(r2_ptr), -4); \ + const HVX_Vector ev2 = Q6_V_lo_W(vp2); \ + const HVX_Vector od2 = Q6_V_hi_W(vp2); \ + const HVX_Vector lf2 = Q6_V_valign_VVR(od2, zero, 124); \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf2, w20, ev2, w21, od2, w22); \ + \ + hvx_vmem(out_vtcm + (size_t) ohi * 32) = Q6_Vsf_equals_Vqf32(acc); \ + \ + ev0 = ev2; \ + od0 = od2; \ + lf0 = lf2; \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S2_K3X3_W64(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S2_K3X3_W64(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_WHCN_S2_K3X3(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s2_k3x3_##SUFFIX( \ + const float * restrict in_vtcm, \ + float * restrict out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + const struct htp_tensor * src0 = octx->src[0]; \ + const size_t w_nb0 = src0->nb[0]; \ + const size_t w_nb1 = src0->nb[1]; \ + const char * restrict w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const uint32_t oh_len = slice->oh_len; \ + const uint32_t w_in = kp->w; \ + const uint32_t ow = kp->ow; \ + \ + conv2d_dw_pad_vtcm_k3x3((float *) in_vtcm, slice, w_in, 0); \ + \ + const HVX_Vector w00 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w01 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w02 = SPLAT_W_FN(w_chan + 0 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w10 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w11 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w12 = SPLAT_W_FN(w_chan + 1 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector w20 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 0 * w_nb0); \ + const HVX_Vector w21 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 1 * w_nb0); \ + const HVX_Vector w22 = SPLAT_W_FN(w_chan + 2 * w_nb1 + 2 * w_nb0); \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + for (uint32_t ohi = 0; ohi < oh_len; ++ohi) { \ + const float * restrict r0 = in_vtcm + (size_t) (2 * ohi) * w_in; \ + const float * restrict r1 = r0 + w_in; \ + const float * restrict r2 = r1 + w_in; \ + float * restrict out_row = out_vtcm + (size_t) ohi * ow; \ + \ + HVX_Vector prev_od0 = zero; \ + HVX_Vector prev_od1 = zero; \ + HVX_Vector prev_od2 = zero; \ + \ + for (uint32_t ox = 0; ox < ow; ox += 32) { \ + const uint32_t ix = 2 * ox; \ + const bool has1 = (ix + 32 < w_in); \ + \ + const HVX_VectorPair vp0 = Q6_W_vdeal_VVR(has1 ? hvx_vmem(r0 + ix + 32) : zero, hvx_vmem(r0 + ix), -4); \ + const HVX_Vector ev0 = Q6_V_lo_W(vp0); \ + const HVX_Vector od0 = Q6_V_hi_W(vp0); \ + const HVX_Vector lf0 = Q6_V_valign_VVR(od0, prev_od0, 124); \ + prev_od0 = od0; \ + HVX_Vector acc = conv2d_dw_qf32_mpy_add3(zero, lf0, w00, ev0, w01, od0, w02); \ + \ + const HVX_VectorPair vp1 = Q6_W_vdeal_VVR(has1 ? hvx_vmem(r1 + ix + 32) : zero, hvx_vmem(r1 + ix), -4); \ + const HVX_Vector ev1 = Q6_V_lo_W(vp1); \ + const HVX_Vector od1 = Q6_V_hi_W(vp1); \ + const HVX_Vector lf1 = Q6_V_valign_VVR(od1, prev_od1, 124); \ + prev_od1 = od1; \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf1, w10, ev1, w11, od1, w12); \ + \ + const HVX_VectorPair vp2 = Q6_W_vdeal_VVR(has1 ? hvx_vmem(r2 + ix + 32) : zero, hvx_vmem(r2 + ix), -4); \ + const HVX_Vector ev2 = Q6_V_lo_W(vp2); \ + const HVX_Vector od2 = Q6_V_hi_W(vp2); \ + const HVX_Vector lf2 = Q6_V_valign_VVR(od2, prev_od2, 124); \ + prev_od2 = od2; \ + acc = conv2d_dw_qf32_mpy_add3(acc, lf2, w20, ev2, w21, od2, w22); \ + \ + if (ox + 32 <= ow) { \ + hvx_vmem(out_row + ox) = Q6_Vsf_equals_Vqf32(acc); \ + } else { \ + const uint32_t rem = ow - ox; \ + const HVX_VectorPred q = Q6_Q_vsetq_R(rem * sizeof(float)); \ + hvx_vec_store_u(out_row + ox, rem * sizeof(float), Q6_V_vmux_QVV(q, Q6_Vsf_equals_Vqf32(acc), zero)); \ + } \ + } \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S2_K3X3(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S2_K3X3(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_WHCN_S1(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s1_##SUFFIX( \ + const float * in_vtcm, \ + float * out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + const struct htp_tensor * src0 = octx->src[0]; \ + const char * w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const int32_t p0 = kp->p0; \ + const int32_t p1 = kp->p1; \ + const int32_t s1 = kp->s1; \ + const int32_t d1 = kp->d1; \ + const int32_t w = (int32_t) kp->w; \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + for (uint32_t ohi = 0; ohi < slice->oh_len; ++ohi) { \ + const uint32_t oh = slice->oh_start + ohi; \ + float * out_row = out_vtcm + (size_t) ohi * kp->ow; \ + \ + for (uint32_t ox = 0; ox < kp->ow; ox += 32) { \ + const uint32_t rem = kp->ow - ox; \ + const uint32_t nbytes = (rem < 32) ? (rem * sizeof(float)) : 128; \ + HVX_Vector acc0 = zero; \ + HVX_Vector acc1 = zero; \ + HVX_Vector acc2 = zero; \ + HVX_Vector acc3 = zero; \ + \ + for (uint32_t kh = 0; kh < kp->kh; ++kh) { \ + const int32_t ih = (int32_t) (oh * s1 + kh * d1) - p1; \ + if (ih < 0 || ih >= (int32_t) kp->h) { \ + continue; \ + } \ + const float * in_row = in_vtcm + (size_t) (ih - slice->ih_first) * kp->w; \ + const char * w_row = w_chan + (size_t) kh * src0->nb[1]; \ + \ + for (uint32_t kw = 0; kw < kp->kw; ++kw) { \ + const HVX_Vector w_v = SPLAT_W_FN(w_row + (size_t) kw * src0->nb[0]); \ + const int32_t base_iw = (int32_t) ox - p0 + (int32_t) kw; \ + HVX_Vector in_v; \ + \ + if (base_iw >= 0) { \ + in_v = hvx_vmemu(in_row + base_iw); \ + } else { \ + const int32_t pad = -base_iw; \ + const HVX_Vector v = hvx_vmemu(in_row); \ + in_v = Q6_V_valign_VVR(v, zero, 128 - (uint32_t) pad * sizeof(float)); \ + } \ + if (base_iw + 31 >= w) { \ + const int32_t valid = w - base_iw; \ + const HVX_VectorPred q = Q6_Q_vsetq_R(MAX(0, valid) * sizeof(float)); \ + in_v = Q6_V_vmux_QVV(q, in_v, zero); \ + } \ + \ + const HVX_Vector prod = Q6_Vqf32_vmpy_VsfVsf(in_v, w_v); \ + switch (kw & 3) { \ + case 0: acc0 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, prod); break; \ + case 1: acc1 = Q6_Vqf32_vadd_Vqf32Vqf32(acc1, prod); break; \ + case 2: acc2 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, prod); break; \ + case 3: acc3 = Q6_Vqf32_vadd_Vqf32Vqf32(acc3, prod); break; \ + } \ + } \ + } \ + \ + const HVX_Vector acc01 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, acc1); \ + const HVX_Vector acc23 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, acc3); \ + HVX_Vector acc_out = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(acc01, acc23)); \ + if (rem < 32) { \ + const HVX_VectorPred q = Q6_Q_vsetq_R(rem * sizeof(float)); \ + acc_out = Q6_V_vmux_QVV(q, acc_out, zero); \ + } \ + \ + hvx_vec_store_u(out_row + ox, nbytes, acc_out); \ + } \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S1(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S1(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_WHCN_S2(SUFFIX, SPLAT_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_whcn_s2_##SUFFIX( \ + const float * in_vtcm, \ + float * out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + const struct htp_tensor * src0 = octx->src[0]; \ + const char * w_chan = (const char *) w_vtcm + (size_t) slice->c * src0->nb[3]; \ + const int32_t p0 = kp->p0; \ + const int32_t p1 = kp->p1; \ + const int32_t s1 = kp->s1; \ + const int32_t d1 = kp->d1; \ + const int32_t w = (int32_t) kp->w; \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + for (uint32_t ohi = 0; ohi < slice->oh_len; ++ohi) { \ + const uint32_t oh = slice->oh_start + ohi; \ + float * out_row = out_vtcm + (size_t) ohi * kp->ow; \ + \ + for (uint32_t ox = 0; ox < kp->ow; ox += 32) { \ + const uint32_t rem = kp->ow - ox; \ + const uint32_t nbytes = (rem < 32) ? (rem * sizeof(float)) : 128; \ + HVX_Vector acc0 = zero; \ + HVX_Vector acc1 = zero; \ + HVX_Vector acc2 = zero; \ + HVX_Vector acc3 = zero; \ + \ + for (uint32_t kh = 0; kh < kp->kh; ++kh) { \ + const int32_t ih = (int32_t) (oh * s1 + kh * d1) - p1; \ + if (ih < 0 || ih >= (int32_t) kp->h) { \ + continue; \ + } \ + const float * in_row = in_vtcm + (size_t) (ih - slice->ih_first) * kp->w; \ + const char * w_row = w_chan + (size_t) kh * src0->nb[1]; \ + \ + for (uint32_t kw = 0; kw < kp->kw; ++kw) { \ + const HVX_Vector w_v = SPLAT_W_FN(w_row + (size_t) kw * src0->nb[0]); \ + const int32_t base_iw = (int32_t) (2 * ox) - p0 + (int32_t) kw; \ + HVX_Vector in_v; \ + \ + if (base_iw >= 0) { \ + const HVX_Vector v0 = hvx_vmemu(in_row + base_iw); \ + const HVX_Vector v1 = hvx_vmemu(in_row + base_iw + 32); \ + in_v = Q6_V_lo_W(Q6_W_vdeal_VVR(v1, v0, -4)); \ + } else { \ + const int32_t pad = -base_iw; \ + const HVX_Vector v0 = hvx_vmemu(in_row); \ + const HVX_Vector v1 = hvx_vmemu(in_row + 32); \ + const HVX_VectorPair vp = Q6_W_vdeal_VVR(v1, v0, -4); \ + if (pad & 1) { \ + const uint32_t shift_lanes = (uint32_t) (pad + 1) / 2; \ + const HVX_Vector v_odd = Q6_V_hi_W(vp); \ + in_v = Q6_V_valign_VVR(v_odd, zero, 128 - shift_lanes * sizeof(float)); \ + } else { \ + const uint32_t shift_lanes = (uint32_t) pad / 2; \ + const HVX_Vector v_even = Q6_V_lo_W(vp); \ + in_v = Q6_V_valign_VVR(v_even, zero, 128 - shift_lanes * sizeof(float)); \ + } \ + } \ + if (base_iw + 62 >= w) { \ + const int32_t valid = (w - base_iw + 1) / 2; \ + const HVX_VectorPred q = Q6_Q_vsetq_R(MAX(0, valid) * sizeof(float)); \ + in_v = Q6_V_vmux_QVV(q, in_v, zero); \ + } \ + \ + const HVX_Vector prod = Q6_Vqf32_vmpy_VsfVsf(in_v, w_v); \ + switch (kw & 3) { \ + case 0: acc0 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, prod); break; \ + case 1: acc1 = Q6_Vqf32_vadd_Vqf32Vqf32(acc1, prod); break; \ + case 2: acc2 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, prod); break; \ + case 3: acc3 = Q6_Vqf32_vadd_Vqf32Vqf32(acc3, prod); break; \ + } \ + } \ + } \ + \ + const HVX_Vector acc01 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, acc1); \ + const HVX_Vector acc23 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, acc3); \ + HVX_Vector acc_out = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(acc01, acc23)); \ + if (rem < 32) { \ + const HVX_VectorPred q = Q6_Q_vsetq_R(rem * sizeof(float)); \ + acc_out = Q6_V_vmux_QVV(q, acc_out, zero); \ + } \ + \ + hvx_vec_store_u(out_row + ox, nbytes, acc_out); \ + } \ + } \ +} + +DEFINE_CONV2D_DW_WHCN_S2(f32, conv2d_dw_splat_w_f32) +DEFINE_CONV2D_DW_WHCN_S2(f16, conv2d_dw_splat_w_f16) + +#define DEFINE_CONV2D_DW_CWHN(SUFFIX, LOAD_W_FN) \ +__attribute__((noinline)) \ +static void conv2d_dw_cwhn_##SUFFIX( \ + const float * in_vtcm, \ + float * out_vtcm, \ + const void * w_vtcm, \ + const struct conv2d_dw_task_slice * slice, \ + const struct htp_ops_context * octx, \ + const struct htp_conv2d_dw_kernel_params * kp) { \ + \ + const struct htp_tensor * src0 = octx->src[0]; \ + const uint32_t in_row_stride = kp->w * kp->c; \ + const uint32_t out_row_stride = kp->ow * kp->c; \ + const HVX_Vector zero = Q6_V_vzero(); \ + \ + for (uint32_t cb = 0; cb < kp->c; cb += 32) { \ + const uint32_t rem = MIN(32, kp->c - cb); \ + const char * w_base = (const char *) w_vtcm + (size_t) cb * src0->nb[3]; \ + \ + for (uint32_t ohi = 0; ohi < slice->oh_len; ++ohi) { \ + const uint32_t oh = slice->oh_start + ohi; \ + float * out_row = out_vtcm + (size_t) ohi * out_row_stride + cb; \ + \ + for (uint32_t ow = 0; ow < kp->ow; ++ow) { \ + HVX_Vector acc0 = zero; \ + HVX_Vector acc1 = zero; \ + HVX_Vector acc2 = zero; \ + HVX_Vector acc3 = zero; \ + \ + for (uint32_t kh = 0; kh < kp->kh; ++kh) { \ + const int32_t ih = (int32_t)(oh * kp->s1 + kh * kp->d1) - kp->p1; \ + if (ih < 0 || ih >= (int32_t)kp->h) { \ + continue; \ + } \ + const float * in_row = in_vtcm + (size_t)(ih - slice->ih_first) * in_row_stride + cb; \ + const char * w_row = w_base + (size_t) kh * src0->nb[1]; \ + \ + for (uint32_t kw = 0; kw < kp->kw; ++kw) { \ + const int32_t iw = (int32_t)(ow * kp->s0 + kw * kp->d0) - kp->p0; \ + if (iw < 0 || iw >= (int32_t)kp->w) { \ + continue; \ + } \ + \ + const float * in_ptr = in_row + (size_t) iw * kp->c; \ + const char * w_ptr = w_row + (size_t) kw * src0->nb[0]; \ + const HVX_Vector v_in = hvx_vmemu(in_ptr); \ + const HVX_Vector v_w = LOAD_W_FN(w_ptr); \ + const HVX_Vector prod = Q6_Vqf32_vmpy_VsfVsf(v_in, v_w); \ + switch (kw & 3) { \ + case 0: acc0 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, prod); break; \ + case 1: acc1 = Q6_Vqf32_vadd_Vqf32Vqf32(acc1, prod); break; \ + case 2: acc2 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, prod); break; \ + case 3: acc3 = Q6_Vqf32_vadd_Vqf32Vqf32(acc3, prod); break; \ + } \ + } \ + } \ + \ + const HVX_Vector acc01 = Q6_Vqf32_vadd_Vqf32Vqf32(acc0, acc1); \ + const HVX_Vector acc23 = Q6_Vqf32_vadd_Vqf32Vqf32(acc2, acc3); \ + const HVX_Vector acc_out = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(acc01, acc23)); \ + \ + float * dst_ptr = out_row + (size_t) ow * kp->c; \ + if (rem == 32) { \ + hvx_vmemu(dst_ptr) = acc_out; \ + } else { \ + hvx_vec_store_u(dst_ptr, rem * sizeof(float), acc_out); \ + } \ + } \ + } \ + } \ +} + +DEFINE_CONV2D_DW_CWHN(f32, conv2d_dw_load_w_f32) +DEFINE_CONV2D_DW_CWHN(f16, conv2d_dw_load_w_f16) + +typedef void (*conv2d_dw_compute_fn_t)( + const float * in_vtcm, + float * out_vtcm, + const void * w_vtcm, + const struct conv2d_dw_task_slice * slice, + const struct htp_ops_context * octx, + const struct htp_conv2d_dw_kernel_params * kp); + +static const conv2d_dw_compute_fn_t conv2d_dw_kernels[HTP_CONV2D_DW_KERNEL_COUNT][2] = { + [HTP_CONV2D_DW_KERNEL_UNSUPPORTED] = { NULL, NULL }, + [HTP_CONV2D_DW_KERNEL_CWHN] = { conv2d_dw_cwhn_f32, conv2d_dw_cwhn_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S1] = { conv2d_dw_whcn_s1_f32, conv2d_dw_whcn_s1_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S2] = { conv2d_dw_whcn_s2_f32, conv2d_dw_whcn_s2_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S1_K3X3] = { conv2d_dw_whcn_s1_k3x3_f32, conv2d_dw_whcn_s1_k3x3_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W32] = { conv2d_dw_whcn_s2_k3x3_w32_f32, conv2d_dw_whcn_s2_k3x3_w32_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W64] = { conv2d_dw_whcn_s2_k3x3_w64_f32, conv2d_dw_whcn_s2_k3x3_w64_f16 }, + [HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3] = { conv2d_dw_whcn_s2_k3x3_f32, conv2d_dw_whcn_s2_k3x3_f16 }, +}; + +struct conv2d_dw_dma_context { + struct htp_ops_context * octx; + const struct htp_conv2d_dw_kernel_params * kp; + struct htp_conv2d_dw_vtcm_layout layout; + const void * w_vtcm; + conv2d_dw_compute_fn_t compute_fn; + uint32_t task_start; + uint32_t task_count; + uint32_t tasks_per_thread; +}; + +static void conv2d_dw_dma_thread(unsigned int nth, unsigned int ith, void * data) { + const struct conv2d_dw_dma_context * ctx = (const struct conv2d_dw_dma_context *) data; + const struct htp_ops_context * octx = ctx->octx; + const struct htp_conv2d_dw_kernel_params * kp = ctx->kp; + const struct htp_conv2d_dw_vtcm_layout * L = &ctx->layout; + const struct htp_tensor * src1 = octx->src[1]; + const struct htp_tensor * dst = octx->dst; + conv2d_dw_compute_fn_t compute_fn = ctx->compute_fn; + + const uint32_t first = ctx->task_start + ith * ctx->tasks_per_thread; + const uint32_t last = MIN(first + ctx->tasks_per_thread, ctx->task_start + ctx->task_count); + if (first >= last) { + return; + } + + (void) nth; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + dma_queue * dma_q = octx->ctx->dma[ith]; + + const uint32_t src_spad_half = (uint32_t) L->src_spad_half_size; + const uint32_t dst_spad_half = (uint32_t) L->dst_spad_half_size; + const uint32_t pad_top_stride = kp->pad_top_stride; + + uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; + uint8_t * src_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_src) + ith * L->src_bytes_per_thread; + uint8_t * dst_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_dst) + ith * L->dst_bytes_per_thread; + + float * srcb2[2] = { (float *) src_spad, (float *) (src_spad + src_spad_half) }; + float * dstb2[2] = { (float *) dst_spad, (float *) (dst_spad + dst_spad_half) }; + struct conv2d_dw_task_slice sl2[2]; + + const uint32_t total = last - first; + + for (uint32_t i = 0; i < total && i < 2; ++i) { + conv2d_dw_get_slice(&sl2[i], first + i, src1, dst, kp); + + dma_queue_push(dma_q, + dma_make_data(dst->data, dstb2[i]), + sl2[i].dst_bytes, dst_spad_half, + sl2[i].dst_bytes, 0); + + float * src_dst = srcb2[i] + (size_t) sl2[i].top_pad * pad_top_stride; + dma_queue_push(dma_q, + dma_make_data(src_dst, sl2[i].src_addr), + src_spad_half, sl2[i].src_bytes, + sl2[i].src_bytes, sl2[i].src_bytes > 0 ? 1 : 0); + } + + for (uint32_t i = 0; i < total; ++i) { + const uint32_t task = first + i; + const uint32_t buf = i & 1u; + float * srcb = srcb2[buf]; + float * dstb = dstb2[buf]; + + dma_queue_pop(dma_q); + dma_queue_pop(dma_q); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) task); + compute_fn(srcb, dstb, ctx->w_vtcm, &sl2[buf], octx, kp); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) task); + + dma_queue_push(dma_q, + dma_make_data(sl2[buf].dst_addr, dstb), + sl2[buf].dst_bytes, dst_spad_half, + sl2[buf].dst_bytes, sl2[buf].dst_bytes > 0 ? 1 : 0); + + if (i + 2 < total) { + conv2d_dw_get_slice(&sl2[buf], task + 2, src1, dst, kp); + + float * src_dst = srcb + (size_t) sl2[buf].top_pad * pad_top_stride; + dma_queue_push(dma_q, + dma_make_data(src_dst, sl2[buf].src_addr), + src_spad_half, sl2[buf].src_bytes, + sl2[buf].src_bytes, sl2[buf].src_bytes > 0 ? 1 : 0); + } + } + + dma_queue_flush(dma_q); + + FARF(HIGH, "conv2d_dw-f32-dma %d/%d: %ux%ux%ux%u -> %ux%ux%ux%u (%u:%u)\n", + ith, nth, kp->w, kp->h, kp->c, kp->n, kp->ow, kp->oh, kp->c, kp->n, first, last); +} + +int op_conv_2d_dw(struct htp_ops_context * octx) { + const struct htp_conv2d_dw_kernel_params * kp = + (const struct htp_conv2d_dw_kernel_params *) octx->kernel_params; + + if (kp->total_tasks == 0) { + return HTP_STATUS_OK; + } + + if (kp->kernel_type <= HTP_CONV2D_DW_KERNEL_UNSUPPORTED || + kp->kernel_type >= HTP_CONV2D_DW_KERNEL_COUNT) { + return HTP_STATUS_NO_SUPPORT; + } + + const uint32_t pad_rows = (kp->pad_top_stride > 0) ? 4 : 0; + const uint32_t max_ih_chunk = MIN(kp->h, (kp->oh_chunk - 1) * (uint32_t) kp->s1 + (kp->kh - 1) * (uint32_t) kp->d1 + 1); + const uint32_t max_src_bytes = (max_ih_chunk + pad_rows) * kp->row_src_bytes + 128; + const uint32_t max_dst_bytes = kp->oh_chunk * kp->row_dst_bytes + 128; + + const struct htp_tensor * src0 = octx->src[0]; + const uint32_t elem_size = kp->is_f16 ? sizeof(__fp16) : sizeof(float); + const uint32_t w_size = src0->size; + + struct htp_conv2d_dw_vtcm_layout layout; + htp_conv2d_dw_vtcm_layout_build(&layout, max_src_bytes, max_dst_bytes, w_size, kp->n_threads); + + uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; + void * w_vtcm = VTCM_LAYOUT_PTR(void, vtcm_base, layout.off_w); + + struct htp_tensor w_vtcm_tensor = *src0; + w_vtcm_tensor.data = (dma_addr_t) w_vtcm; + + if (src0->nb[0] == elem_size) { + dma_cpy_sametype_sameshape(octx->ctx->dma[0], &w_vtcm_tensor, src0, elem_size); + } else { + dma_sync_read(octx->ctx->dma[0], w_vtcm, src0->data, w_size); + } + dma_queue_flush(octx->ctx->dma[0]); + + uint32_t task_start = 0; + uint32_t task_count = kp->total_tasks; + if (octx->ctx->mdev.count > 1) { + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( + task_count, 1, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + task_start = range.start; + task_count = range.count; + } + if (task_count == 0) { + return HTP_STATUS_OK; + } + + const uint32_t nth = MIN(kp->n_threads, task_count); + const uint32_t tasks_per_thread = (task_count + nth - 1) / nth; + + struct conv2d_dw_dma_context ctx = { + .octx = octx, + .kp = kp, + .layout = layout, + .w_vtcm = w_vtcm, + .compute_fn = conv2d_dw_kernels[kp->kernel_type][kp->is_f16 ? 1 : 0], + .task_start = task_start, + .task_count = task_count, + .tasks_per_thread = tasks_per_thread, + }; + + work_queue_run(octx->ctx->work_queue, conv2d_dw_dma_thread, &ctx, nth); + return HTP_STATUS_OK; +} diff --git a/ggml/src/ggml-hexagon/htp/conv2d-ops.h b/ggml/src/ggml-hexagon/htp/conv2d-ops.h new file mode 100644 index 000000000000..a48bf3e83ffe --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/conv2d-ops.h @@ -0,0 +1,197 @@ +#ifndef HTP_CONV2D_OPS_H +#define HTP_CONV2D_OPS_H + +#include +#include + +#include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-ops.h" +#include "htp-vtcm.h" + +enum htp_conv2d_kernel_type { + HTP_CONV2D_KERNEL_UNSUPPORTED = 0, + HTP_CONV2D_KERNEL_HMX_WINDOW, // HMX convolution with sliding-window staging + HTP_CONV2D_KERNEL_HMX_TILED, // tiled implicit-GEMM convolution on HMX +}; + +// HMX_WINDOW output staging buffers per thread +#define HTP_CONV2D_WIN_OBUF 2 + +// HMX scales of one row tile at the start of VTCM: 32 (scale, bias) fp16 pairs and 128 zero bytes +#define HTP_CONV2D_HMX_SCALES_SIZE 256 + +struct htp_conv2d_tiled_params { + uint32_t w_kstride; + uint32_t k_size; + uint32_t k_group; + uint32_t k_group_pad; + uint32_t n_groups; + uint32_t n_k_tiles; + uint32_t n_ow_tiles; + uint32_t seg_tiles; + uint32_t stage_row; + uint32_t n_stage; + uint32_t wk_chunk; + struct fastdiv_values div_ow_tiles; + struct fastdiv_values div_oh; +}; + +struct htp_conv2d_window_params { + uint32_t fold; + uint32_t n_cc; + uint32_t act_rt_last; + uint32_t sr; + uint32_t ihs; + uint32_t max_off; + uint32_t n_bc; + uint32_t seg_b; + uint32_t seg_t; + uint32_t w_cs; + struct fastdiv_values div_sr; + struct fastdiv_values div_ihs; + struct fastdiv_values div_kw; + struct fastdiv_values div_tg; + struct fastdiv_values div_cc; + struct fastdiv_values div_cs; +}; + +struct htp_conv2d_kernel_params { + uint8_t kernel_type; + uint8_t n_threads; + uint8_t cwhn; + uint8_t w_kmajor; + + uint32_t total_rows; + uint32_t n_row_tiles; + uint32_t ct_chunk; + uint32_t rt_block; + uint32_t stage_size; + uint32_t thr_size; + uint32_t vtcm_size; + + union { + struct htp_conv2d_tiled_params tiled; + struct htp_conv2d_window_params window; + }; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_conv2d_kernel_params) <= 128, "htp_conv2d_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_conv2d_kernel_params) <= 128, "htp_conv2d_kernel_params is too large for kernel_params blob"); +#endif + +enum htp_conv2d_dw_kernel_type { + HTP_CONV2D_DW_KERNEL_UNSUPPORTED = 0, + HTP_CONV2D_DW_KERNEL_CWHN, // CWHN channel-contiguous layout + HTP_CONV2D_DW_KERNEL_WHCN_S1, // WHCN general stride-1 + HTP_CONV2D_DW_KERNEL_WHCN_S2, // WHCN general stride-2 + HTP_CONV2D_DW_KERNEL_WHCN_S1_K3X3, // WHCN aligned w%32==0, 3x3 s=1 p=1 d=1 + HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W32, // WHCN w=32->ow=16, 3x3 s=2 p=1 d=1 (2 rows per vector) + HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3_W64, // WHCN w=64->ow=32, 3x3 s=2 p=1 d=1 (1 vector rolling kh) + HTP_CONV2D_DW_KERNEL_WHCN_S2_K3X3, // WHCN aligned w%32==0 (w>=96), 3x3 s=2 p=1 d=1 + HTP_CONV2D_DW_KERNEL_COUNT, +}; + +struct htp_conv2d_dw_kernel_params { + uint8_t kernel_type; + uint8_t n_threads; + uint8_t cwhn; + uint8_t is_f16; + + uint32_t total_tasks; + uint32_t vtcm_size; + uint32_t w; + uint32_t h; + uint32_t c; + uint32_t n; + uint32_t kw; + uint32_t kh; + uint32_t ow; + uint32_t oh; + int32_t s0; + int32_t s1; + int32_t p0; + int32_t p1; + int32_t d0; + int32_t d1; + uint32_t oh_chunk; + uint32_t n_chunks; + uint32_t row_src_bytes; + uint32_t row_dst_bytes; + uint32_t pad_top_stride; + struct fastdiv_values div_c; + struct fastdiv_values div_n_chunks; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_conv2d_dw_kernel_params) <= 128, "htp_conv2d_dw_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_conv2d_dw_kernel_params) <= 128, "htp_conv2d_dw_kernel_params is too large for kernel_params blob"); +#endif + +struct htp_conv2d_dw_vtcm_layout { + size_t total_bytes; + size_t off_w; + size_t off_src; + size_t off_dst; + size_t src_spad_half_size; + size_t dst_spad_half_size; + size_t src_bytes_per_thread; + size_t dst_bytes_per_thread; +}; + +static inline void htp_conv2d_dw_vtcm_layout_build( + struct htp_conv2d_dw_vtcm_layout * L, + uint32_t max_src_bytes, + uint32_t max_dst_bytes, + uint32_t w_size, + uint32_t n_threads +) { + L->src_spad_half_size = hex_round_up(max_src_bytes + 256, 128); + L->dst_spad_half_size = hex_round_up(max_dst_bytes + 128, 128); + L->src_bytes_per_thread = 2 * L->src_spad_half_size; + L->dst_bytes_per_thread = 2 * L->dst_spad_half_size; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_w, hex_round_up(w_size, 128)); + VTCM_LAYOUT_ALLOC(off, off_src, L->src_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + L->total_bytes = off; +} + +struct htp_conv2d_vtcm_layout { + size_t total_bytes; + size_t off_scales; + size_t off_w; + size_t off_act[2]; + size_t off_out[2]; + size_t off_thr; + + size_t act_size; +}; + +static inline void htp_conv2d_vtcm_layout_build( + struct htp_conv2d_vtcm_layout * L, + uint32_t rt_block, + size_t w_size, + size_t act_size, + size_t out_size, + size_t thr_size, + uint32_t n_threads +) { + const size_t sc = hex_round_up((size_t) rt_block * HTP_CONV2D_HMX_SCALES_SIZE, 2048); + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_scales, sc); + VTCM_LAYOUT_ALLOC(off, off_w, w_size); + VTCM_LAYOUT_ALLOC(off, off_act[0], act_size); + VTCM_LAYOUT_ALLOC(off, off_act[1], act_size); + VTCM_LAYOUT_ALLOC(off, off_out[0], out_size); + VTCM_LAYOUT_ALLOC(off, off_out[1], out_size); + VTCM_LAYOUT_ALLOC(off, off_thr, (size_t) n_threads * thr_size); + L->act_size = act_size; + L->total_bytes = off; +} + +#endif // HTP_CONV2D_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/cpy-ops.c b/ggml/src/ggml-hexagon/htp/cpy-ops.c index 63ebb38e6800..fce45c2d4736 100644 --- a/ggml/src/ggml-hexagon/htp/cpy-ops.c +++ b/ggml/src/ggml-hexagon/htp/cpy-ops.c @@ -32,6 +32,7 @@ struct htp_copy_context { uint32_t nelem; uint32_t elem_per_thread; + struct htp_copy_convert_vtcm_layout layout; uint8_t * vtcm_src0; uint8_t * vtcm_dst; }; @@ -176,13 +177,14 @@ static void cpy_thread_##NAME##_sameshape(unsigned int nth, unsigned int ith, vo struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ \ const struct htp_copy_convert_params * cvt = &ct->kparams->u.convert; \ - const uint32_t src0_buf_size = cvt->src0_buf_size; \ - const uint32_t dst_buf_size = cvt->dst_buf_size; \ - const uint32_t src0_row_stride = cvt->src0_row_stride; \ - const uint32_t dst_row_stride = cvt->dst_row_stride; \ - const uint32_t blk_rows = cvt->blk_rows; \ - uint8_t * vtcm_src0_base = ct->vtcm_src0 + ith * cvt->spad0_size_per_thread; \ - uint8_t * vtcm_dst_base = ct->vtcm_dst + ith * cvt->spad1_size_per_thread; \ + const struct htp_copy_convert_vtcm_layout * L = &ct->layout; \ + const uint32_t src0_buf_size = L->src0_buf_size; \ + const uint32_t dst_buf_size = L->dst_buf_size; \ + const uint32_t src0_row_stride = L->src0_row_stride; \ + const uint32_t dst_row_stride = L->dst_row_stride; \ + const uint32_t blk_rows = L->blk_rows; \ + uint8_t * vtcm_src0_base = ct->vtcm_src0 + ith * L->spad0_size_per_thread; \ + uint8_t * vtcm_dst_base = ct->vtcm_dst + ith * L->spad1_size_per_thread; \ const uint32_t src0_row_size = ne00 * ct->kparams->src0_type_size; \ const uint32_t dst_row_size = ne00 * ct->kparams->dst_type_size; \ \ @@ -254,17 +256,16 @@ static int cpy_scalar(struct htp_ops_context * octx, const struct htp_copy_kerne } dma_queue * dma_q = octx->ctx->dma[0]; - dma_addr_t s_vtcm = (dma_addr_t)(uintptr_t) octx->ctx->vtcm_base; - dma_addr_t d_vtcm = s_vtcm + VLEN; + uint8_t * s_ptr = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, 0); + uint8_t * d_ptr = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, VLEN); + dma_addr_t s_vtcm = (dma_addr_t)(uintptr_t) s_ptr; + dma_addr_t d_vtcm = (dma_addr_t)(uintptr_t) d_ptr; const uint32_t s_size = kparams->src0_type_size; const uint32_t d_size = kparams->dst_type_size; dma_queue_push(dma_q, dma_make_data(s_vtcm, src0->data), s_size, s_size, s_size, 1); dma_queue_pop(dma_q); - uint8_t * s_ptr = (uint8_t *) octx->ctx->vtcm_base; - uint8_t * d_ptr = s_ptr + VLEN; - const HVX_Vector v_src = hvx_vmem(s_ptr); HVX_Vector v_dst; @@ -366,6 +367,8 @@ static int cpy_sameshape_convert(struct htp_ops_context * octx, const struct htp const struct htp_copy_convert_params * cvt = &kparams->u.convert; struct htp_copy_context ct; + htp_copy_convert_vtcm_layout_build(&ct.layout, src0->ne[0], kparams->src0_type_size, kparams->dst_type_size, cvt->blk_rows, n_threads); + ct.octx = octx; ct.kparams = kparams; ct.row_start = row_start; @@ -373,8 +376,8 @@ static int cpy_sameshape_convert(struct htp_ops_context * octx, const struct htp ct.src0_nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); uint8_t * vtcm_base = (uint8_t *) octx->ctx->vtcm_base; - ct.vtcm_src0 = vtcm_base; - ct.vtcm_dst = vtcm_base + (size_t) n_threads * cvt->spad0_size_per_thread; + ct.vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, ct.layout.off_src0); + ct.vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, ct.layout.off_dst); work_queue_func_t copy_fun = NULL; if (dst->type == HTP_TYPE_F16 && src0->type == HTP_TYPE_F32) { diff --git a/ggml/src/ggml-hexagon/htp/cpy-ops.h b/ggml/src/ggml-hexagon/htp/cpy-ops.h index 16695c2ab6a3..c3b97c0cab4b 100644 --- a/ggml/src/ggml-hexagon/htp/cpy-ops.h +++ b/ggml/src/ggml-hexagon/htp/cpy-ops.h @@ -3,6 +3,7 @@ #include "hex-common.h" #include "hex-fastdiv.h" +#include "htp-vtcm.h" #include "gather-rows.h" #include @@ -17,12 +18,6 @@ enum htp_copy_kernel_type { }; struct htp_copy_convert_params { - uint32_t src0_buf_size; - uint32_t dst_buf_size; - uint32_t spad0_size_per_thread; - uint32_t spad1_size_per_thread; - uint32_t src0_row_stride; // row pitch in the VTCM buffers - uint32_t dst_row_stride; uint32_t blk_rows; // rows moved per DMA descriptor struct fastdiv_values div_ne01; struct fastdiv_values div_ne02_ne01; @@ -60,6 +55,9 @@ struct htp_copy_kernel_params { #define HTP_COPY_VTCM_BLK_BYTES (32 * 1024) struct htp_copy_convert_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_dst; uint32_t src0_row_stride; uint32_t dst_row_stride; uint32_t blk_rows; @@ -67,11 +65,35 @@ struct htp_copy_convert_vtcm_layout { uint32_t dst_buf_size; uint32_t spad0_size_per_thread; uint32_t spad1_size_per_thread; - uint32_t total_bytes; }; -// ne01 bounds a block: rows of one block share the dim-1 stride. static inline void htp_copy_convert_vtcm_layout_build( + struct htp_copy_convert_vtcm_layout * L, + uint32_t ne00, + uint32_t src_type_size, + uint32_t dst_type_size, + uint32_t blk_rows, + uint32_t n_threads) { + + const uint32_t src0_row_stride = hex_round_up(ne00 * src_type_size, 256); + const uint32_t dst_row_stride = hex_round_up(ne00 * dst_type_size, 256); + + L->src0_row_stride = src0_row_stride; + L->dst_row_stride = dst_row_stride; + L->blk_rows = blk_rows; + L->src0_buf_size = blk_rows * src0_row_stride; + L->dst_buf_size = blk_rows * dst_row_stride; + L->spad0_size_per_thread = 2 * L->src0_buf_size; + L->spad1_size_per_thread = 2 * L->dst_buf_size; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, (size_t) n_threads * L->spad0_size_per_thread); + VTCM_LAYOUT_ALLOC(off, off_dst, (size_t) n_threads * L->spad1_size_per_thread); + L->total_bytes = off; +} + +// ne01 bounds a block: rows of one block share the dim-1 stride. +static inline void htp_copy_convert_solve_layout( struct htp_copy_convert_vtcm_layout * layout, uint32_t ne00, uint32_t ne01, @@ -79,10 +101,10 @@ static inline void htp_copy_convert_vtcm_layout_build( uint32_t dst_type_size, uint32_t n_threads) { - layout->src0_row_stride = hex_round_up(ne00 * src_type_size, 256); - layout->dst_row_stride = hex_round_up(ne00 * dst_type_size, 256); + const uint32_t src0_row_stride = hex_round_up(ne00 * src_type_size, 256); + const uint32_t dst_row_stride = hex_round_up(ne00 * dst_type_size, 256); - const uint32_t max_row = layout->src0_row_stride > layout->dst_row_stride ? layout->src0_row_stride : layout->dst_row_stride; + const uint32_t max_row = src0_row_stride > dst_row_stride ? src0_row_stride : dst_row_stride; uint32_t blk_rows = HTP_COPY_VTCM_BLK_BYTES / max_row; if (blk_rows > ne01) { blk_rows = ne01; @@ -90,13 +112,8 @@ static inline void htp_copy_convert_vtcm_layout_build( if (blk_rows == 0) { blk_rows = 1; } - layout->blk_rows = blk_rows; - layout->src0_buf_size = blk_rows * layout->src0_row_stride; - layout->dst_buf_size = blk_rows * layout->dst_row_stride; - layout->spad0_size_per_thread = 2 * layout->src0_buf_size; - layout->spad1_size_per_thread = 2 * layout->dst_buf_size; - layout->total_bytes = n_threads * (layout->spad0_size_per_thread + layout->spad1_size_per_thread); + htp_copy_convert_vtcm_layout_build(layout, ne00, src_type_size, dst_type_size, blk_rows, n_threads); } #if defined(__cplusplus) diff --git a/ggml/src/ggml-hexagon/htp/cumsum-ops.c b/ggml/src/ggml-hexagon/htp/cumsum-ops.c index eaab7d7e516c..36fc81276099 100644 --- a/ggml/src/ggml-hexagon/htp/cumsum-ops.c +++ b/ggml/src/ggml-hexagon/htp/cumsum-ops.c @@ -12,9 +12,11 @@ #include "htp-ctx.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "htp-vtcm.h" #include "hvx-types.h" #include "hvx-utils.h" #include "dma-queue.h" +#include "cumsum-ops.h" #define htp_cumsum_tensors_preamble \ const struct htp_tensor * restrict src0 = octx->src[0]; \ @@ -89,8 +91,8 @@ static inline HVX_Vector hvx_splat_last_f32(HVX_Vector v) { } static inline void hvx_cumsum_row_f32(const float * restrict src, float * restrict dst, uint32_t n) { - const uint32_t nvec = n / VLEN_FP32; - const uint32_t nloe = n % VLEN_FP32; + const uint32_t nvec = n >> 5; + const uint32_t nloe = n & (VLEN_FP32 - 1); HVX_Vector carry = Q6_V_vsplat_R(0); @@ -210,16 +212,19 @@ static void cumsum_thread_f32(unsigned int nth, unsigned int ith, void * data) { int op_cumsum_f32(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; + const struct htp_cumsum_kernel_params * kparams = + (const struct htp_cumsum_kernel_params *) octx->kernel_params; - const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const size_t dst_data_row_size = dst->ne[0] * sizeof(float); + const uint32_t total_rows = kparams->total_rows; + const size_t src_row_size = src0->nb[1]; + const size_t dst_row_size = dst->nb[1]; uint32_t row_start = 0; uint32_t nrows = total_rows; if (octx->ctx->mdev.count > 1) { uint32_t rows_per_chunk = 0; - htp_tensor_mdev_rows_per_chunk(dst, sizeof(float), (uint32_t) dst_data_row_size, &rows_per_chunk); + htp_tensor_mdev_rows_per_chunk(dst, sizeof(float), (uint32_t) dst_row_size, &rows_per_chunk); const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_rows, rows_per_chunk, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); row_start = range.start; nrows = range.count; @@ -229,43 +234,45 @@ int op_cumsum_f32(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = octx->n_threads; - - const size_t src_row_size = src0->nb[1]; - const size_t dst_row_size = dst->nb[1]; - const size_t src_row_size_aligned = hex_round_up(src_row_size, VLEN); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN); - - // 2 ping-pong buffers per thread for src and dst - const size_t spad_per_thread = 2 * (src_row_size_aligned + dst_row_size_aligned); + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, nrows))) { + return HTP_STATUS_INVAL_PARAMS; + } - octx->src0_spad.size_per_thread = src_row_size_aligned * 2; - octx->dst_spad.size_per_thread = dst_row_size_aligned * 2; + const uint32_t n_threads = octx->n_threads; - octx->src0_spad.size = n_threads * octx->src0_spad.size_per_thread; - octx->dst_spad.size = n_threads * octx->dst_spad.size_per_thread; + if (!kparams->use_dma && (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst))) { + return HTP_STATUS_NO_SUPPORT; + } - octx->src0_spad.data = octx->ctx->vtcm_base; octx->src0_spad.src = NULL; - octx->dst_spad.data = octx->src0_spad.data + octx->src0_spad.size; octx->dst_spad.src = NULL; + struct htp_cumsum_vtcm_layout layout = { 0 }; + if (kparams->use_dma) { + htp_cumsum_vtcm_layout_build(&layout, src_row_size, dst_row_size, n_threads); + + octx->src0_spad.size_per_thread = layout.src0_bytes_per_thread; + octx->dst_spad.size_per_thread = layout.dst_bytes_per_thread; + octx->src0_spad.size = n_threads * layout.src0_bytes_per_thread; + octx->dst_spad.size = n_threads * layout.dst_bytes_per_thread; + octx->src0_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_src0); + octx->dst_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_dst); + octx->src0_spad.src = NULL; + octx->dst_spad.src = NULL; + } struct htp_cumsum_context cctx = { .octx = octx, .src_row_size = src_row_size, .dst_row_size = dst_row_size, - .src_row_size_aligned = src_row_size_aligned, - .dst_row_size_aligned = dst_row_size_aligned, + .src_row_size_aligned = layout.src_row_size_aligned, + .dst_row_size_aligned = layout.dst_row_size_aligned, .rows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), .total_rows = nrows, .row_start = row_start, }; - if (octx->ctx->vtcm_size < spad_per_thread * n_threads) { - if (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst)) { - return HTP_STATUS_NO_SUPPORT; - } - work_queue_run(octx->ctx->work_queue, cumsum_thread_f32, &cctx, n_threads); - } else { + if (kparams->use_dma) { work_queue_run(octx->ctx->work_queue, cumsum_thread_f32_dma, &cctx, n_threads); + } else { + work_queue_run(octx->ctx->work_queue, cumsum_thread_f32, &cctx, n_threads); } return HTP_STATUS_OK; diff --git a/ggml/src/ggml-hexagon/htp/cumsum-ops.h b/ggml/src/ggml-hexagon/htp/cumsum-ops.h new file mode 100644 index 000000000000..6e1ac316fedd --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/cumsum-ops.h @@ -0,0 +1,49 @@ +#ifndef HTP_CUMSUM_OPS_H +#define HTP_CUMSUM_OPS_H + +#include "hex-common.h" +#include "htp-vtcm.h" +#include + +struct htp_cumsum_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_dst; + size_t src_row_size_aligned; + size_t dst_row_size_aligned; + size_t src0_bytes_per_thread; + size_t dst_bytes_per_thread; +}; + +static inline void htp_cumsum_vtcm_layout_build( + struct htp_cumsum_vtcm_layout * L, + size_t src_row_size, + size_t dst_row_size, + uint32_t n_threads +) { + L->src_row_size_aligned = hex_round_up(src_row_size, 128); + L->dst_row_size_aligned = hex_round_up(dst_row_size, 128); + L->src0_bytes_per_thread = 2 * L->src_row_size_aligned; + L->dst_bytes_per_thread = 2 * L->dst_row_size_aligned; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + + L->total_bytes = off; +} + +struct htp_cumsum_kernel_params { + uint32_t n_threads; + uint32_t total_rows; + uint32_t use_dma; + uint32_t vtcm_size; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_cumsum_kernel_params) <= 128, "htp_cumsum_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_cumsum_kernel_params) <= 128, "htp_cumsum_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_CUMSUM_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/diag-ops.c b/ggml/src/ggml-hexagon/htp/diag-ops.c index 162214d3e46f..7f03e855013f 100644 --- a/ggml/src/ggml-hexagon/htp/diag-ops.c +++ b/ggml/src/ggml-hexagon/htp/diag-ops.c @@ -10,10 +10,12 @@ #include "htp-ctx.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "htp-vtcm.h" #include "hvx-types.h" #include "hex-utils.h" #include "hvx-copy.h" #include "dma-queue.h" +#include "diag-ops.h" #define htp_diag_tensors_preamble \ const struct htp_tensor * restrict src0 = octx->src[0]; \ @@ -33,6 +35,7 @@ struct htp_diag_context { struct htp_ops_context * octx; + const struct htp_diag_kernel_params * kparams; size_t src_batch_size; size_t dst_row_size; size_t src_batch_size_aligned; @@ -83,8 +86,8 @@ static void diag_thread_f32_dma(unsigned int nth, unsigned int ith, void * data) struct htp_thread_trace * tr = &octx->ctx->trace[ith]; for (uint32_t ib = ib0; ib < ib1; ib++) { - const uint32_t i3 = ib / ne02; - const uint32_t i2 = ib % ne02; + const uint32_t i3 = fastdiv(ib, &dctx->kparams->div_ne02); + const uint32_t i2 = ib - i3 * ne02; const dma_addr_t src_batch = src_data + i3 * nb03 + i2 * nb02; @@ -134,8 +137,8 @@ static void diag_thread_f32(unsigned int nth, unsigned int ith, void * data) { htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ib0); for (uint32_t ib = ib0; ib < ib1; ib++) { - const uint32_t i3 = ib / ne02; - const uint32_t i2 = ib % ne02; + const uint32_t i3 = fastdiv(ib, &dctx->kparams->div_ne02); + const uint32_t i2 = ib - i3 * ne02; const float * restrict src_batch = (const float *)(src_data + i3 * nb03 + i2 * nb02); @@ -155,29 +158,17 @@ static void diag_thread_f32(unsigned int nth, unsigned int ith, void * data) { int op_diag_f32(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; + const struct htp_diag_kernel_params * kparams = + (const struct htp_diag_kernel_params *) octx->kernel_params; - const uint32_t total_batches = src0->ne[2] * src0->ne[3]; - const size_t dst_batch_size = dst->ne[1] * dst->nb[1]; + const uint32_t total_batches = kparams->total_batches; uint32_t batch_start = 0; uint32_t nbatches = total_batches; if (octx->ctx->mdev.count > 1) { - bool can_split = htp_tensor_mdev_data_aligned(dst) && (dst->ne[0] == 1 || dst->nb[0] == sizeof(float)) && !htp_tensor_is_permuted(dst); - uint32_t batches_per_chunk = 1; - if (can_split) { - if (dst->ne[2] > 1 && (dst->nb[2] & (HTP_TENSOR_MDEV_LINE_SIZE - 1)) == 0 && - (dst->ne[3] <= 1 || (dst->nb[3] & (HTP_TENSOR_MDEV_LINE_SIZE - 1)) == 0)) { - batches_per_chunk = 1; - } else if (dst->nb[2] == dst_batch_size && - (dst->ne[3] <= 1 || dst->nb[3] == dst->nb[2] * dst->ne[2])) { - batches_per_chunk = (dst_batch_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(dst_batch_size, HEX_L2_LINE_SIZE)) : 1; - } else { - can_split = false; - } - } - - const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_batches, can_split ? batches_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + const bool can_split = (kparams->can_split != 0) && htp_tensor_mdev_data_aligned(dst); + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_batches, can_split ? kparams->batches_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); batch_start = range.start; nbatches = range.count; } @@ -186,43 +177,49 @@ int op_diag_f32(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = octx->n_threads; - - const size_t src_batch_size = src0->ne[0] * sizeof(float); - const size_t dst_row_size = dst->ne[0] * sizeof(float); - const size_t src_batch_size_aligned = hex_round_up(src_batch_size, VLEN); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN); - - // 1 src buffer + 1 dst row buffer per thread - const size_t spad_per_thread = src_batch_size_aligned + dst_row_size_aligned; + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, nbatches))) { + return HTP_STATUS_INVAL_PARAMS; + } - octx->src0_spad.size_per_thread = src_batch_size_aligned; - octx->dst_spad.size_per_thread = dst_row_size_aligned; + const uint32_t n_threads = octx->n_threads; - octx->src0_spad.size = n_threads * octx->src0_spad.size_per_thread; - octx->dst_spad.size = n_threads * octx->dst_spad.size_per_thread; + if (!kparams->use_dma && (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst))) { + return HTP_STATUS_NO_SUPPORT; + } - octx->src0_spad.data = octx->ctx->vtcm_base; octx->src0_spad.src = NULL; - octx->dst_spad.data = octx->src0_spad.data + octx->src0_spad.size; octx->dst_spad.src = NULL; + const size_t src_batch_size = src0->ne[0] * sizeof(float); + const size_t dst_row_size = dst->ne[0] * sizeof(float); + + struct htp_diag_vtcm_layout layout = { 0 }; + if (kparams->use_dma) { + htp_diag_vtcm_layout_build(&layout, src_batch_size, dst_row_size, n_threads); + + octx->src0_spad.size_per_thread = layout.src0_bytes_per_thread; + octx->dst_spad.size_per_thread = layout.dst_bytes_per_thread; + octx->src0_spad.size = n_threads * layout.src0_bytes_per_thread; + octx->dst_spad.size = n_threads * layout.dst_bytes_per_thread; + octx->src0_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_src0); + octx->dst_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_dst); + octx->src0_spad.src = NULL; + octx->dst_spad.src = NULL; + } struct htp_diag_context dctx = { .octx = octx, + .kparams = kparams, .src_batch_size = src_batch_size, .dst_row_size = dst_row_size, - .src_batch_size_aligned = src_batch_size_aligned, - .dst_row_size_aligned = dst_row_size_aligned, + .src_batch_size_aligned = layout.src_batch_size_aligned, + .dst_row_size_aligned = layout.dst_row_size_aligned, .batches_per_thread = fastdiv(nbatches + n_threads - 1, &octx->n_threads_div), .total_batches = nbatches, .batch_start = batch_start, }; - if (octx->ctx->vtcm_size < spad_per_thread * n_threads) { - if (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst)) { - return HTP_STATUS_NO_SUPPORT; - } - work_queue_run(octx->ctx->work_queue, diag_thread_f32, &dctx, n_threads); - } else { + if (kparams->use_dma) { work_queue_run(octx->ctx->work_queue, diag_thread_f32_dma, &dctx, n_threads); + } else { + work_queue_run(octx->ctx->work_queue, diag_thread_f32, &dctx, n_threads); } return HTP_STATUS_OK; diff --git a/ggml/src/ggml-hexagon/htp/diag-ops.h b/ggml/src/ggml-hexagon/htp/diag-ops.h new file mode 100644 index 000000000000..983bc02423f2 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/diag-ops.h @@ -0,0 +1,54 @@ +#ifndef HTP_DIAG_OPS_H +#define HTP_DIAG_OPS_H + +#include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-vtcm.h" +#include + +struct htp_diag_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_dst; + size_t src_batch_size_aligned; + size_t dst_row_size_aligned; + size_t src0_bytes_per_thread; + size_t dst_bytes_per_thread; +}; + +static inline void htp_diag_vtcm_layout_build( + struct htp_diag_vtcm_layout * L, + size_t src_batch_size, + size_t dst_row_size, + uint32_t n_threads +) { + L->src_batch_size_aligned = hex_round_up(src_batch_size, 128); + L->dst_row_size_aligned = hex_round_up(dst_row_size, 128); + L->src0_bytes_per_thread = L->src_batch_size_aligned; + L->dst_bytes_per_thread = L->dst_row_size_aligned; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + + L->total_bytes = off; +} + +struct htp_diag_kernel_params { + uint32_t n_threads; + uint32_t total_batches; + uint32_t use_dma; + uint32_t can_split; + uint32_t batches_per_chunk; + uint32_t vtcm_size; + + struct fastdiv_values div_ne02; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_diag_kernel_params) <= 128, "htp_diag_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_diag_kernel_params) <= 128, "htp_diag_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_DIAG_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/dma-queue.c b/ggml/src/ggml-hexagon/htp/dma-queue.c index ef61d2d242e6..11d52a919ac5 100644 --- a/ggml/src/ggml-hexagon/htp/dma-queue.c +++ b/ggml/src/ggml-hexagon/htp/dma-queue.c @@ -141,43 +141,9 @@ bool dma_queue_push_fallback_2d(dma_queue * q, dma_data ddata, size_t dst_stride dma_ring_flush(r1); r0->tail = r1->tail; - return dma_ring_push_single_2d(r0, ddata, 0, 0, 0, /*nrows=*/ 0); -} - -bool dma_queue_push_fallback_contig(dma_queue * q, dma_data ddata, size_t total) { - dma_ring * r0 = q->ring0; - dma_ring * r1 = q->ring1; - - if (((r0->push_idx + 1) & r0->idx_mask) == r0->pop_idx) { - return false; - } - - r1->tail = r0->tail; - - size_t rem_bytes = total; - dma_addr_t cur_dst = ddata.dst; - dma_addr_t cur_src = ddata.src; - - while (rem_bytes > 0) { - const uint32_t cur_bytes = MIN(rem_bytes, DMA_SAFE_CHUNK_SIZE); - dma_data cur_data = dma_make_data(cur_dst, cur_src); - if (!dma_ring_push_single_contig(r1, cur_data, cur_bytes)) { - dma_ring_flush(r1); - dma_ring_push_single_contig(r1, cur_data, cur_bytes); - } - cur_dst += cur_bytes; - cur_src += cur_bytes; - rem_bytes -= cur_bytes; - } - - dma_ring_flush(r1); - r0->tail = r1->tail; - return dma_ring_push_single_1d(r0, ddata, /*size=*/ 0); } -#if __HVX_ARCH__ < 75 - bool dma_queue_push_fallback_1d(dma_queue * q, dma_data ddata, size_t dst_stride, size_t src_stride, size_t row_size, size_t nrows) { dma_ring * r0 = q->ring0; dma_ring * r1 = q->ring1; @@ -188,19 +154,28 @@ bool dma_queue_push_fallback_1d(dma_queue * q, dma_data ddata, size_t dst_stride r1->tail = r0->tail; - size_t rem_rows = nrows; - dma_addr_t cur_dst = ddata.dst; - dma_addr_t cur_src = ddata.src; - - while (rem_rows > 0) { - dma_data cur_data = dma_make_data(cur_dst, cur_src); - if (!dma_ring_push_single_1d(r1, cur_data, row_size)) { - dma_ring_flush(r1); - dma_ring_push_single_1d(r1, cur_data, row_size); + dma_addr_t row_dst = ddata.dst; + dma_addr_t row_src = ddata.src; + + for (size_t i = 0; i < nrows; i++) { + size_t rem_bytes = row_size; + dma_addr_t cur_dst = row_dst; + dma_addr_t cur_src = row_src; + + while (rem_bytes > 0) { + const uint32_t cur_bytes = MIN(rem_bytes, DMA_SAFE_CHUNK_SIZE); + dma_data cur_data = dma_make_data(cur_dst, cur_src); + if (!dma_ring_push_single_contig(r1, cur_data, cur_bytes)) { + dma_ring_flush(r1); + dma_ring_push_single_contig(r1, cur_data, cur_bytes); + } + cur_dst += cur_bytes; + cur_src += cur_bytes; + rem_bytes -= cur_bytes; } - cur_dst += dst_stride; - cur_src += src_stride; - rem_rows -= 1; + + row_dst += dst_stride; + row_src += src_stride; } dma_ring_flush(r1); @@ -208,5 +183,3 @@ bool dma_queue_push_fallback_1d(dma_queue * q, dma_data ddata, size_t dst_stride return dma_ring_push_single_1d(r0, ddata, /*size=*/ 0); } - -#endif diff --git a/ggml/src/ggml-hexagon/htp/dma-queue.h b/ggml/src/ggml-hexagon/htp/dma-queue.h index 9b774bdd9cff..678fc61d7e45 100644 --- a/ggml/src/ggml-hexagon/htp/dma-queue.h +++ b/ggml/src/ggml-hexagon/htp/dma-queue.h @@ -148,10 +148,7 @@ dma_queue_t dma_queue_alias_init(void * ptr, dma_queue_t main_q); void dma_queue_alias_free(dma_queue_t q); bool dma_queue_push_fallback_2d(dma_queue * q, dma_data ddata, size_t dst_stride, size_t src_stride, size_t row_size, size_t nrows); -bool dma_queue_push_fallback_contig(dma_queue * q, dma_data ddata, size_t total); -#if __HVX_ARCH__ < 75 bool dma_queue_push_fallback_1d(dma_queue * q, dma_data ddata, size_t dst_stride, size_t src_stride, size_t row_size, size_t nrows); -#endif // TODO: technically we don't need these and could use Q6_dmstart/wait/etc instead // but those do not seem to always compiler properly. @@ -400,7 +397,7 @@ static inline bool dma_queue_push(dma_queue * q, dma_data ddata, size_t dst_stri if (__builtin_expect(total <= DMA_MAX_SIZE_24B, 1)) { return dma_ring_push_single_contig(q->ring0, ddata, total); } - return dma_queue_push_fallback_contig(q, ddata, total); + return dma_queue_push_fallback_1d(q, ddata, 0, 0, total, 1); } // 2. Hot path: Standard strided 2D (10-20% of calls) @@ -410,14 +407,10 @@ static inline bool dma_queue_push(dma_queue * q, dma_data ddata, size_t dst_stri } // 3. Cold path: Descriptor chunking fallbacks (< 0.1%) -#if __HVX_ARCH__ < 75 - if (row_size <= DMA_MAX_SIZE_16B && (src_stride | dst_stride) <= DMA_MAX_STRIDE_16B) { + if ((row_size | src_stride | dst_stride) <= DMA_MAX_2D_ROW_SIZE) { return dma_queue_push_fallback_2d(q, ddata, dst_stride, src_stride, row_size, nrows); } return dma_queue_push_fallback_1d(q, ddata, dst_stride, src_stride, row_size, nrows); -#else - return dma_queue_push_fallback_2d(q, ddata, dst_stride, src_stride, row_size, nrows); -#endif } static inline void dma_sync_read(dma_queue * dma_q, void * dst, dma_addr_t src, size_t bytes) { @@ -436,10 +429,10 @@ static inline void dma_sync_write(dma_queue * dma_q, dma_addr_t dst, const void } } -#define DMA_CACHE_MAX_SIZE 256U +#define DMA_CACHE_MAX_SIZE 128U // Fully assoc LRU cache -typedef struct { +typedef struct __attribute__((aligned(128))) { uint8_t *base; uint32_t line_size; uint32_t capacity; @@ -485,7 +478,7 @@ static inline bool dma_cache_fa_push(dma_queue *q, dma_cache_fa *c, dma_addr_t s } // Direct mapped cache -typedef struct { +typedef struct __attribute__((aligned(128))) { uint8_t *base; uint32_t line_size; uint32_t capacity; diff --git a/ggml/src/ggml-hexagon/htp/fill-ops.c b/ggml/src/ggml-hexagon/htp/fill-ops.c index 212104a23bd4..2cab31b5fd0a 100644 --- a/ggml/src/ggml-hexagon/htp/fill-ops.c +++ b/ggml/src/ggml-hexagon/htp/fill-ops.c @@ -16,6 +16,7 @@ #include "htp-ctx.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "fill-ops.h" // ggml op_params layout for FILL: // op_params[0] (as float) - the scalar fill value @@ -30,21 +31,19 @@ \ const uint32_t nb1 = dst->nb[1]; \ const uint32_t nb2 = dst->nb[2]; \ - const uint32_t nb3 = dst->nb[3]; \ - \ - const uint32_t nr = ne1 * ne2 * ne3; + const uint32_t nb3 = dst->nb[3]; struct htp_fill_context { struct htp_ops_context * octx; + const struct htp_fill_kernel_params * kparams; uint32_t nrows_per_thread; uint32_t total_rows; // ne1 * ne2 * ne3 uint32_t row_start; - bool opt_path; HVX_Vector splat_vec; uint32_t elem_size; }; -static void fill_thread(unsigned int nth, unsigned int ith, void * data) { +static void fill_thread_contiguous(unsigned int nth, unsigned int ith, void * data) { const struct htp_fill_context * fctx = (const struct htp_fill_context *) data; struct htp_ops_context * octx = fctx->octx; fill_preamble; @@ -60,45 +59,59 @@ static void fill_thread(unsigned int nth, unsigned int ith, void * data) { struct htp_thread_trace * tr = &octx->ctx->trace[ith]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir0); - if (fctx->opt_path) { - // Opt path: tensor is fully contiguous, treat as flat array - const uint32_t elem_start = ir0 * ne0; - const uint32_t elem_end = ir1 * ne0; - uint8_t * dst_ptr = (uint8_t *) dst->data + elem_start * fctx->elem_size; - hvx_splat_u(dst_ptr, fctx->splat_vec, elem_end - elem_start, fctx->elem_size); - } else { - // Non-contiguous path: must respect strides - for (uint32_t ir = ir0; ir < ir1; ++ir) { - const uint32_t i1 = ir % ne1; - const uint32_t i2 = (ir / ne1) % ne2; - const uint32_t i3 = ir / (ne1 * ne2); - uint8_t * dst_ptr = (uint8_t *) dst->data + i1*nb1 + i2*nb2 + i3*nb3; - hvx_splat_u(dst_ptr, fctx->splat_vec, ne0, fctx->elem_size); - } - } + const uint32_t elem_start = ir0 * ne0; + const uint32_t elem_end = ir1 * ne0; + uint8_t * dst_ptr = (uint8_t *) dst->data + elem_start * fctx->elem_size; + hvx_splat_u(dst_ptr, fctx->splat_vec, elem_end - elem_start, fctx->elem_size); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir1); - FARF(HIGH, "fill %u/%u: rows %u:%u\n", ith, nth, ir0, ir1); + FARF(HIGH, "fill-contig %u/%u: rows %u:%u\n", ith, nth, ir0, ir1); } -int op_fill(struct htp_ops_context * octx) { +static void fill_thread_strided(unsigned int nth, unsigned int ith, void * data) { + const struct htp_fill_context * fctx = (const struct htp_fill_context *) data; + struct htp_ops_context * octx = fctx->octx; + const struct htp_fill_kernel_params * kparams = fctx->kparams; fill_preamble; - if (dst->type != HTP_TYPE_F32 && dst->type != HTP_TYPE_F16) { - return HTP_STATUS_NO_SUPPORT; + // Parallelise over the flat row index spanning ne1*ne2*ne3 + const uint32_t ir0 = fctx->row_start + fctx->nrows_per_thread * ith; + const uint32_t ir1 = MIN(ir0 + fctx->nrows_per_thread, fctx->row_start + fctx->total_rows); + + if (ir0 >= ir1) { + return; + } + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir0); + + for (uint32_t ir = ir0; ir < ir1; ++ir) { + const uint32_t i3 = fastdiv(ir, &kparams->div_ne1_ne2); + const uint32_t rem = ir - i3 * (ne1 * ne2); + const uint32_t i2 = fastdiv(rem, &kparams->div_ne1); + const uint32_t i1 = rem - i2 * ne1; + uint8_t * dst_ptr = (uint8_t *) dst->data + i1*nb1 + i2*nb2 + i3*nb3; + hvx_splat_u(dst_ptr, fctx->splat_vec, ne0, fctx->elem_size); } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir1); + FARF(HIGH, "fill-strided %u/%u: rows %u:%u\n", ith, nth, ir0, ir1); +} + +int op_fill(struct htp_ops_context * octx) { + const struct htp_tensor * dst = octx->dst; + const struct htp_fill_kernel_params * kparams = + (const struct htp_fill_kernel_params *) octx->kernel_params; + if (htp_tensor_is_extended(dst)) { return HTP_STATUS_NO_SUPPORT; } uint32_t row_start = 0; - uint32_t nrows = nr; + uint32_t nrows = kparams->total_rows; if (octx->ctx->mdev.count > 1) { - const uint32_t row_size = nb1; - const uint32_t rows_per_chunk = (row_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(row_size, HEX_L2_LINE_SIZE)) : 1; - const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(nr, htp_tensor_mdev_data_aligned(dst) ? rows_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(kparams->total_rows, htp_tensor_mdev_data_aligned(dst) ? kparams->rows_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); row_start = range.start; nrows = range.count; } @@ -107,40 +120,43 @@ int op_fill(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - // nr = ne1*ne2*ne3 (flat row count across all outer dims); parallelise over it. - const uint32_t n_threads = octx->n_threads; + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, nrows))) { + return HTP_STATUS_INVAL_PARAMS; + } - // Optimize if fully contiguous: skip stride arithmetic, treat as flat array - const bool opt_path = (nb2 == nb1 * ne1) && (nb3 == nb2 * ne2); + const uint32_t n_threads = octx->n_threads; - FARF(HIGH, "fill: (%ux%ux%ux%u) type=%u opt=%d\n", - dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], dst->type, (int) opt_path); + FARF(HIGH, "fill: (%ux%ux%ux%u) type=%u ktype=%u\n", + dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], dst->type, kparams->kernel_type); float val_f32 = 0.f; memcpy(&val_f32, &octx->op_params[0], sizeof(float)); struct htp_fill_context fctx = { .octx = octx, + .kparams = kparams, .nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), .total_rows = nrows, .row_start = row_start, - .opt_path = opt_path, + .elem_size = kparams->elem_size, }; switch (dst->type) { case HTP_TYPE_F32: fctx.splat_vec = hvx_vec_splat_f32(val_f32); - fctx.elem_size = sizeof(float); break; case HTP_TYPE_F16: fctx.splat_vec = hvx_vec_splat_f16((_Float16) val_f32); - fctx.elem_size = sizeof(_Float16); break; default: return HTP_STATUS_NO_SUPPORT; } - work_queue_run(octx->ctx->work_queue, fill_thread, &fctx, n_threads); + work_queue_func_t worker = (kparams->kernel_type == HTP_FILL_KERNEL_CONTIGUOUS) + ? fill_thread_contiguous + : fill_thread_strided; + + work_queue_run(octx->ctx->work_queue, worker, &fctx, n_threads); return HTP_STATUS_OK; } diff --git a/ggml/src/ggml-hexagon/htp/fill-ops.h b/ggml/src/ggml-hexagon/htp/fill-ops.h new file mode 100644 index 000000000000..d62f997513d5 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/fill-ops.h @@ -0,0 +1,29 @@ +#ifndef HTP_FILL_OPS_H +#define HTP_FILL_OPS_H + +#include "hex-fastdiv.h" +#include + +enum htp_fill_kernel_type { + HTP_FILL_KERNEL_CONTIGUOUS = 0, + HTP_FILL_KERNEL_STRIDED = 1, +}; + +struct htp_fill_kernel_params { + uint8_t kernel_type; + uint32_t n_threads; + uint32_t total_rows; + uint32_t elem_size; + uint32_t rows_per_chunk; + + struct fastdiv_values div_ne1; + struct fastdiv_values div_ne1_ne2; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_fill_kernel_params) <= 128, "htp_fill_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_fill_kernel_params) <= 128, "htp_fill_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_FILL_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/flash-attn-ops.c b/ggml/src/ggml-hexagon/htp/flash-attn-ops.c index 2ee55feb9aba..ee258172b1ac 100644 --- a/ggml/src/ggml-hexagon/htp/flash-attn-ops.c +++ b/ggml/src/ggml-hexagon/htp/flash-attn-ops.c @@ -39,6 +39,26 @@ // Must be multiple of 32 #define FLASH_ATTN_BLOCK_SIZE (32 * 2) +// Large scratch lives in ctx->ddr_spad to keep stack usage low. +// Ops can run on the dspqueue callback thread, which has a small stack. +struct hvx_fa_ddr_spad { + __fp16 slopes[512]; + uint16_t active_blocks[FA_MAX_KV_BLOCKS]; + uint16_t thread_active_blocks[HTP_MAX_NTHREADS][FA_MAX_KV_BLOCKS] __attribute__((aligned(128))); +}; + +struct hmx_fa_ddr_spad { + uint16_t active_blocks[FA_MAX_KV_BLOCKS]; + __fp16 slopes[] __attribute__((aligned(128))); // [g_br] +}; + +static inline void * fa_get_ddr_spad(const struct htp_ops_context * octx, size_t size) { + if (!octx->ctx->ddr_spad_base || octx->ctx->ddr_spad_size < size) { + return NULL; + } + return octx->ctx->ddr_spad_base; +} + struct htp_fa_context { const struct htp_ops_context * octx; @@ -61,9 +81,10 @@ struct htp_fa_context { uint32_t n_head_log2; float m0; float m1; - __fp16 slopes[512]; uint32_t n_blocks; + uint32_t n_active_blocks; + bool shared_active_blocks; size_t size_q_row_padded; size_t size_k_row_padded; @@ -82,12 +103,15 @@ struct htp_fa_context { size_t size_q_block; size_t size_vkq_acc; - uint8_t * spad_q; - uint8_t * spad_k; - uint8_t * spad_v; - uint8_t * spad_m; - uint8_t * spad_a; - float * spad_sinks; + uint8_t * spad_q; + uint8_t * spad_k; + uint8_t * spad_v; + uint8_t * spad_m; + uint8_t * spad_a; + float * spad_sinks; + + struct hvx_fa_ddr_spad * ddr; + dma_cache_dm * m_cache; // [n_threads] const struct htp_tensor * k; const struct htp_tensor * v; @@ -153,16 +177,89 @@ struct hmx_fa_context { __fp16 * vtcm_mask_buf; // VTCM mask buffer [Br * m_line], DMA'd per KV block __fp16 * vtcm_slopes; // ALiBi slopes [g_br] float * vtcm_sinks; // Attention sinks + __fp16 * ddr_slopes; // ALiBi slopes staging buffer in DDR [g_br] size_t row_buf_stride; // HVX vectors per row buffer (Bc/64) size_t mask_buf_row_stride; // elements (__fp16) per row in mask buffer size_t q_tile_bytes; + size_t k_tile_bytes; size_t o_tile_bytes; size_t col_vec_bytes; size_t d_tile_bytes; bool mask_broadcast; // true when mask->ne[2] == 1 (head-independent, single 2D DMA) - dma_cache_fa m_cache; + dma_cache_fa * m_cache; }; +// Scan mask rows [q_start, q_start + n_rows_q) and build compact list of KV blocks with any entry != -inf. +static uint32_t fa_scan_active_blocks( + dma_queue * dma_q, + const struct htp_tensor * mask, + uint32_t q_start, + uint32_t n_rows_q, + uint32_t im2, + uint32_t im3, + uint32_t nek1, + uint32_t Bc, + uint32_t n_kv_blocks, + void * vtcm_scratch, + size_t scratch_bytes, + uint16_t * active_blocks) { + const size_t row_bytes = (size_t) nek1 * sizeof(__fp16); + const size_t row_stride = hex_round_up(row_bytes, 128); + + if (!mask || n_kv_blocks <= 1 || n_kv_blocks > FA_MAX_KV_BLOCKS || + (size_t) n_rows_q * row_stride > scratch_bytes) { + #pragma clang loop vectorize(disable) + for (uint32_t b = 0; b < n_kv_blocks; ++b) { + active_blocks[b] = (uint16_t) b; + } + return n_kv_blocks; + } + + const dma_addr_t m_src = mask->data + q_start * mask->nb[1] + im2 * mask->nb[2] + im3 * mask->nb[3]; + dma_queue_push(dma_q, dma_make_data(vtcm_scratch, m_src), row_stride, mask->nb[1], row_bytes, n_rows_q); + const uint8_t * m_buf = (const uint8_t *) dma_queue_pop(dma_q).dst; + + const HVX_Vector v_ninf = Q6_Vh_vsplat_R(0xFC00); + uint32_t n_active = 0; + + for (uint32_t b = 0; b < n_kv_blocks; ++b) { + const uint32_t col0 = b * Bc; + const uint32_t cols = MIN(Bc, nek1 - col0); + + for (uint32_t r = 0; r < n_rows_q; ++r) { + const __fp16 * row_ptr = (const __fp16 *) (m_buf + r * row_stride) + col0; + HVX_Vector v_any = Q6_V_vzero(); + uint32_t c = 0; + for (; c + 64 <= cols; c += 64) { + const HVX_Vector v_m = *(const HVX_Vector *) (row_ptr + c); + v_any = Q6_V_vor_VV(v_any, Q6_V_vxor_VV(v_m, v_ninf)); + } + if (c < cols) { + const uint32_t rem = cols - c; + const HVX_VectorPred q_rem = Q6_Q_vsetq2_R(rem * sizeof(__fp16)); + const HVX_Vector v_m = *(const HVX_Vector *) (row_ptr + c); + const HVX_Vector v_diff = Q6_V_vand_QV(q_rem, Q6_V_vxor_VV(v_m, v_ninf)); + v_any = Q6_V_vor_VV(v_any, v_diff); + } + v_any = Q6_V_vor_VV(v_any, Q6_V_vror_VR(v_any, 64)); + v_any = Q6_V_vor_VV(v_any, Q6_V_vror_VR(v_any, 32)); + v_any = Q6_V_vor_VV(v_any, Q6_V_vror_VR(v_any, 16)); + v_any = Q6_V_vor_VV(v_any, Q6_V_vror_VR(v_any, 8)); + v_any = Q6_V_vor_VV(v_any, Q6_V_vror_VR(v_any, 4)); + if (Q6_R_vextract_VR(v_any, 0) != 0) { + active_blocks[n_active++] = (uint16_t) b; + break; + } + } + } + + if (n_active == 0 && n_kv_blocks > 0) { + active_blocks[0] = 0; + n_active = 1; + } + return n_active; +} + static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * data) { struct htp_fa_context * factx = (struct htp_fa_context *) data; const struct htp_ops_context * octx = factx->octx; @@ -233,8 +330,20 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * uint8_t * spad_m = factx->spad_m + (mask ? factx->size_m_block * HVX_FA_DMA_CACHE_SIZE : 0) * ith; uint8_t * spad_a = factx->spad_a + factx->size_vkq_acc * ith; - dma_cache_dm m_cache; - dma_cache_dm_init(&m_cache, spad_m, factx->size_m_block, HVX_FA_DMA_CACHE_SIZE); + dma_cache_dm * m_cache = &factx->m_cache[ith]; + dma_cache_dm_init(m_cache, spad_m, factx->size_m_block, HVX_FA_DMA_CACHE_SIZE); + + uint16_t * thread_active_blocks = factx->ddr->thread_active_blocks[ith]; + const uint16_t * active_blocks = factx->shared_active_blocks ? factx->ddr->active_blocks : thread_active_blocks; + uint32_t n_active_blocks = factx->n_active_blocks; + dma_addr_t prev_mp_base = 0; + + if (!factx->shared_active_blocks && !mask) { + #pragma clang loop vectorize(disable) + for (uint32_t b = 0; b < factx->n_blocks; ++b) { + thread_active_blocks[b] = (uint16_t) b; + } + } const size_t size_vkq_acc_single = hex_round_up(DV * sizeof(float), 128); @@ -271,6 +380,19 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * } } + dma_addr_t mp_base = 0; + if (mask) { + const uint32_t im2 = fastmodulo(iq2, mask->ne[2], &factx->src3_div2); + const uint32_t im3 = fastmodulo(iq3, mask->ne[3], &factx->src3_div3); + mp_base = mask->data + iq1*mask->nb[1] + im2*mask->nb[2] + im3*mask->nb[3]; + if (!factx->shared_active_blocks && mp_base != prev_mp_base) { + n_active_blocks = fa_scan_active_blocks( + dma_q, mask, iq1, 1, im2, im3, nek1, FLASH_ATTN_BLOCK_SIZE, + factx->n_blocks, spad_k, factx->size_k_block * 2, thread_active_blocks); + prev_mp_base = mp_base; + } + } + uint32_t heads[FA_HVX_G_MAX]; HVX_Vector slope_vecs[FA_HVX_G_MAX] __attribute__((aligned(128))); HVX_Vector S_vec[FA_HVX_G_MAX] __attribute__((aligned(128))); @@ -285,7 +407,7 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * const uint32_t r_iq1 = (r - r_iq3*neq2*neq1 - r_iq2 * neq1); heads[g] = r_iq2; - const __fp16 slope = factx->slopes[r_iq2]; + const __fp16 slope = factx->ddr->slopes[r_iq2]; slope_vecs[g] = hvx_vec_splat_f16(slope); S_vec[g] = hvx_vec_splat_f32(0.0f); @@ -303,32 +425,26 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * dma_queue_push(dma_q, dma_make_data(q_dst, q_row_ptr), factx->size_q_row_padded, nbq1, size_q_row, 1); } - dma_addr_t mp_base = 0; - if (mask) { - const uint32_t im2 = fastmodulo(iq2, mask->ne[2], &factx->src3_div2); - const uint32_t im3 = fastmodulo(iq3, mask->ne[3], &factx->src3_div3); - mp_base = mask->data + iq1*mask->nb[1] + im2*mask->nb[2] + im3*mask->nb[3]; - } - - // Prefetch first two blocks - for (uint32_t ib = 0; ib < MIN(factx->n_blocks, 2); ++ib) { + // Prefetch first two active blocks + for (uint32_t step = 0; step < MIN(n_active_blocks, 2); ++step) { + const uint32_t ib = active_blocks[step]; const uint32_t ic_start = ib * FLASH_ATTN_BLOCK_SIZE; const uint32_t current_block_size = MIN(FLASH_ATTN_BLOCK_SIZE, nek1 - ic_start); // K const dma_addr_t k_src = k->data + ic_start*nbk1 + ik2*nbk2 + ik3*nbk3; - uint8_t * k_dst = spad_k + (ib % 2) * factx->size_k_block; + uint8_t * k_dst = spad_k + (step % 2) * factx->size_k_block; dma_queue_push(dma_q, dma_make_data(k_dst, k_src), factx->size_k_row_padded, nbk1, size_k_row, current_block_size); // V const dma_addr_t v_src = v->data + ic_start*nbv1 + iv2*nbv2 + iv3*nbv3; - uint8_t * v_dst = spad_v + (ib % 2) * factx->size_v_block; + uint8_t * v_dst = spad_v + (step % 2) * factx->size_v_block; dma_queue_push(dma_q, dma_make_data(v_dst, v_src), factx->size_v_row_padded, nbv1, size_v_row, current_block_size); // Mask if (mask) { const dma_addr_t m_src = mp_base + ic_start * sizeof(__fp16); - dma_cache_dm_push(dma_q, &m_cache, ib, m_src, current_block_size * 2, current_block_size * 2, current_block_size * 2, 1); + dma_cache_dm_push(dma_q, m_cache, ib, m_src, current_block_size * 2, current_block_size * 2, current_block_size * 2, 1); } } @@ -348,7 +464,8 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * const HVX_Vector v_log2e = hvx_vec_splat_f16(EXP_LOG2E_F); const uint32_t stride_v2 = factx->size_v_row_padded * 2; - for (uint32_t ib = 0; ib < factx->n_blocks; ++ib) { + for (uint32_t step = 0; step < n_active_blocks; ++step) { + const uint32_t ib = active_blocks[step]; const uint32_t ic_start = ib * FLASH_ATTN_BLOCK_SIZE; const uint32_t current_block_size = MIN(FLASH_ATTN_BLOCK_SIZE, nek1 - ic_start); @@ -361,7 +478,7 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_FA_K_PREP, ir); for (uint32_t r = 0; r < current_block_size; ++r) { __fp16 * row_k = (__fp16 *)(k_base + r * factx->size_k_row_padded); - hvx_dequantize_row_q8_0_f16(row_k, row_k, DK); + hvx_dequantize_row_flat_q8_0_f16(row_k, row_k, DK); } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_FA_K_PREP, ir); } @@ -369,7 +486,7 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_FA_V_PREP, ir); for (uint32_t r = 0; r < current_block_size; ++r) { __fp16 * row_v = (__fp16 *)(v_base + r * factx->size_v_row_padded); - hvx_dequantize_row_q8_0_f16(row_v, row_v, DV); + hvx_dequantize_row_flat_q8_0_f16(row_v, row_v, DV); } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_FA_V_PREP, ir); } @@ -411,9 +528,9 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * HVX_Vector v_max = Q6_V_lo_W(hvx_vec_f16_to_f32(v_max_f16)); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_FA_QK, head_ir); - // prefetch K for block ib + 2 after last head finished QK - if (g + 1 == G_local && ib + 2 < factx->n_blocks) { - const uint32_t next_ib = ib + 2; + // prefetch K for step + 2 after last head finished QK + if (g + 1 == G_local && step + 2 < n_active_blocks) { + const uint32_t next_ib = active_blocks[step + 2]; const uint32_t next_ic_start = next_ib * FLASH_ATTN_BLOCK_SIZE; const uint32_t next_block_size = MIN(FLASH_ATTN_BLOCK_SIZE, nek1 - next_ic_start); @@ -504,6 +621,56 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * ((HVX_VectorPair *) VKQ32)[0] = vkq0; ((HVX_VectorPair *) VKQ32)[1] = vkq1; + } else if (DV == 256) { + HVX_VectorPair vkq0 = ((const HVX_VectorPair *) VKQ32)[0]; + HVX_VectorPair vkq1 = ((const HVX_VectorPair *) VKQ32)[1]; + HVX_VectorPair vkq2 = ((const HVX_VectorPair *) VKQ32)[2]; + HVX_VectorPair vkq3 = ((const HVX_VectorPair *) VKQ32)[3]; + vkq0 = Q6_W_vcombine_VV( + HVX_OP_MUL_F32(Q6_V_hi_W(vkq0), ms_vec), + HVX_OP_MUL_F32(Q6_V_lo_W(vkq0), ms_vec) + ); + vkq1 = Q6_W_vcombine_VV( + HVX_OP_MUL_F32(Q6_V_hi_W(vkq1), ms_vec), + HVX_OP_MUL_F32(Q6_V_lo_W(vkq1), ms_vec) + ); + vkq2 = Q6_W_vcombine_VV( + HVX_OP_MUL_F32(Q6_V_hi_W(vkq2), ms_vec), + HVX_OP_MUL_F32(Q6_V_lo_W(vkq2), ms_vec) + ); + vkq3 = Q6_W_vcombine_VV( + HVX_OP_MUL_F32(Q6_V_hi_W(vkq3), ms_vec), + HVX_OP_MUL_F32(Q6_V_lo_W(vkq3), ms_vec) + ); + + for (uint32_t j = 0; j < current_block_size; j += 2) { + HVX_Vector S0 = hvx_vec_repl_f16(Q6_V_vror_VR(P, j * 2)); + const HVX_Vector * vx0 = (const HVX_Vector *) v_ptr; + if (j + 1 == current_block_size) { + vkq0 = hvx_vec_mpyacc_f32_f16(vkq0, Q6_Vh_vshuff_Vh(vx0[0]), S0); + vkq1 = hvx_vec_mpyacc_f32_f16(vkq1, Q6_Vh_vshuff_Vh(vx0[1]), S0); + vkq2 = hvx_vec_mpyacc_f32_f16(vkq2, Q6_Vh_vshuff_Vh(vx0[2]), S0); + vkq3 = hvx_vec_mpyacc_f32_f16(vkq3, Q6_Vh_vshuff_Vh(vx0[3]), S0); + break; + } + + HVX_Vector S1 = hvx_vec_repl_f16(Q6_V_vror_VR(P, (j + 1) * 2)); + const HVX_Vector * vx1 = (const HVX_Vector *) (v_ptr + factx->size_v_row_padded); + vkq0 = hvx_vec_mpyacc_f32_f16(vkq0, Q6_Vh_vshuff_Vh(vx0[0]), S0); + vkq0 = hvx_vec_mpyacc_f32_f16(vkq0, Q6_Vh_vshuff_Vh(vx1[0]), S1); + vkq1 = hvx_vec_mpyacc_f32_f16(vkq1, Q6_Vh_vshuff_Vh(vx0[1]), S0); + vkq1 = hvx_vec_mpyacc_f32_f16(vkq1, Q6_Vh_vshuff_Vh(vx1[1]), S1); + vkq2 = hvx_vec_mpyacc_f32_f16(vkq2, Q6_Vh_vshuff_Vh(vx0[2]), S0); + vkq2 = hvx_vec_mpyacc_f32_f16(vkq2, Q6_Vh_vshuff_Vh(vx1[2]), S1); + vkq3 = hvx_vec_mpyacc_f32_f16(vkq3, Q6_Vh_vshuff_Vh(vx0[3]), S0); + vkq3 = hvx_vec_mpyacc_f32_f16(vkq3, Q6_Vh_vshuff_Vh(vx1[3]), S1); + v_ptr += stride_v2; + } + + ((HVX_VectorPair *) VKQ32)[0] = vkq0; + ((HVX_VectorPair *) VKQ32)[1] = vkq1; + ((HVX_VectorPair *) VKQ32)[2] = vkq2; + ((HVX_VectorPair *) VKQ32)[3] = vkq3; } else { hvx_scale_vec_f32_aa((uint8_t *) VKQ32, (const uint8_t *) VKQ32, DV, ms_vec); @@ -524,9 +691,9 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_FA_SFM, head_ir); - // prefetch V and mask for block ib + 2 after last head finished V accumulation - if (g + 1 == G_local && ib + 2 < factx->n_blocks) { - const uint32_t next_ib = ib + 2; + // prefetch V and mask for step + 2 after last head finished V accumulation + if (g + 1 == G_local && step + 2 < n_active_blocks) { + const uint32_t next_ib = active_blocks[step + 2]; const uint32_t next_ic_start = next_ib * FLASH_ATTN_BLOCK_SIZE; const uint32_t next_block_size = MIN(FLASH_ATTN_BLOCK_SIZE, nek1 - next_ic_start); @@ -537,11 +704,11 @@ static void flash_attn_ext_f16_thread(unsigned int nth, unsigned int ith, void * // Mask if (mask) { const dma_addr_t m_src = mp_base + next_ic_start * sizeof(__fp16); - dma_cache_dm_push(dma_q, &m_cache, next_ib, m_src, next_block_size * 2, next_block_size * 2, next_block_size * 2, 1); + dma_cache_dm_push(dma_q, m_cache, next_ib, m_src, next_block_size * 2, next_block_size * 2, next_block_size * 2, 1); } } } // end for g - } // end for ib + } // end for step for (uint32_t g = 0; g < G_local; ++g) { const uint32_t head_ir = ir + g; @@ -625,7 +792,7 @@ static void fa_k_interleave_thread(unsigned int n, unsigned int i, void * data) if (factx->k->type == HTP_TYPE_Q8_0) { for (uint32_t r = start; r < end; ++r) { __fp16 * row_k = (__fp16 *)((char *)args->curr_k + r * args->src_stride * sizeof(__fp16)); - hvx_dequantize_row_q8_0_f16(row_k, row_k, factx->DK); + hvx_dequantize_row_flat_q8_0_f16(row_k, row_k, factx->DK); } } hmx_interleave_rows_to_tiles(factx->vtcm_k_tiles[args->buf_idx], (const __fp16 *) args->curr_k, total_rows, factx->DK_pad, @@ -679,7 +846,7 @@ static void fa_v_interleave_thread(unsigned int n, unsigned int i, void * data) if (factx->v->type == HTP_TYPE_Q8_0) { for (uint32_t r = start; r < end; ++r) { __fp16 * row_v = (__fp16 *)((char *)args->v_src + r * args->src_stride * sizeof(__fp16)); - hvx_dequantize_row_q8_0_f16(row_v, row_v, factx->DV); + hvx_dequantize_row_flat_q8_0_f16(row_v, row_v, factx->DV); } } hmx_interleave_cols_to_tiles(v_tiles_dst, (const __fp16 *) args->v_src, total_rows, factx->DV_pad, @@ -755,40 +922,11 @@ static void fa_q_load_thread(unsigned int n, unsigned int i, void * data) { const size_t m_start = i * m_bytes_per_t; const size_t m_end = hex_smin(m_start + m_bytes_per_t, col_vec_bytes); - if (factx->sinks) { - const float * sinks_data = factx->vtcm_sinks; - float * m_vec = (float *) factx->vtcm_m_vec; - const size_t r_start = l_start / sizeof(float); - const size_t r_end = l_end / sizeof(float); - const float scale_factor = EXP_LOG2E_F; - - const HVX_Vector v_scale = hvx_vec_splat_f32(scale_factor); - - for (size_t r = r_start; r < r_end; r += 32) { - HVX_VectorAlias local_m; - for (size_t j = 0; j < 32; ++j) { - size_t curr_r = r + j; - if (curr_r < n_rows_g) { - const size_t h_idx = fastmodulo(curr_r, G, &factx->div_G); - const size_t head = args->kv_head * G + h_idx; - local_m.fp32[j] = sinks_data[head]; - } else { - local_m.fp32[j] = HTP_FA_M_INITIAL_VAL; - } - } - HVX_Vector v_scaled = HVX_OP_MUL_F32(local_m.v, v_scale); - *(HVX_Vector *) (m_vec + r) = v_scaled; - } - if (l_start < col_vec_bytes) { - hvx_splat_u8_a((char *) factx->vtcm_l_vec + l_start, 0, l_end - l_start); - } - } else { - if (l_start < col_vec_bytes) { - hvx_splat_u8_a((char *) factx->vtcm_l_vec + l_start, 0, l_end - l_start); - } - if (m_start < col_vec_bytes) { - hvx_splat_f32_a((char *) factx->vtcm_m_vec + m_start, HTP_FA_M_INITIAL_VAL, (m_end - m_start) / sizeof(float)); - } + if (l_start < col_vec_bytes) { + hvx_splat_u8_a((char *) factx->vtcm_l_vec + l_start, 0, l_end - l_start); + } + if (m_start < col_vec_bytes) { + hvx_splat_f32_a((char *) factx->vtcm_m_vec + m_start, HTP_FA_M_INITIAL_VAL, (m_end - m_start) / sizeof(float)); } // Zero the whole rescale region: vtcm_d_tiles[0], the optional vtcm_d_tiles[1] @@ -1447,21 +1585,10 @@ static inline void fa_softmax_impl( HVX_Vector v_rowsum_acc_f32_0 = Q6_V_lo_W(rowsum_acc_pair); HVX_Vector v_rowsum_acc_f32_1 = Q6_V_hi_W(rowsum_acc_pair); - HVX_Vector v_l_curr0; - HVX_Vector v_l_curr1; - if (args->kv_start == 0 && factx->sinks != NULL) { - // First KV block with sinks: m_prev holds the seeded sink value (not -inf), - // so exp_m_diff = exp2(sink - m_curr) is the sink's contribution to the - // denominator. l_prev is 0 here, so add exp_m_diff directly instead of - // multiplying the (uninitialized) l_prev term. - v_l_curr0 = HVX_OP_ADD_F32(exp_m_diff0, v_rowsum_acc_f32_0); - v_l_curr1 = HVX_OP_ADD_F32(exp_m_diff1, v_rowsum_acc_f32_1); - } else { - HVX_Vector l_prev_v0 = factx->vtcm_l_vec[r_vec_idx * 2 + 0]; - HVX_Vector l_prev_v1 = factx->vtcm_l_vec[r_vec_idx * 2 + 1]; - v_l_curr0 = HVX_OP_ADD_F32(HVX_OP_MUL_F32(l_prev_v0, exp_m_diff0), v_rowsum_acc_f32_0); - v_l_curr1 = HVX_OP_ADD_F32(HVX_OP_MUL_F32(l_prev_v1, exp_m_diff1), v_rowsum_acc_f32_1); - } + HVX_Vector l_prev_v0 = factx->vtcm_l_vec[r_vec_idx * 2 + 0]; + HVX_Vector l_prev_v1 = factx->vtcm_l_vec[r_vec_idx * 2 + 1]; + HVX_Vector v_l_curr0 = HVX_OP_ADD_F32(HVX_OP_MUL_F32(l_prev_v0, exp_m_diff0), v_rowsum_acc_f32_0); + HVX_Vector v_l_curr1 = HVX_OP_ADD_F32(HVX_OP_MUL_F32(l_prev_v1, exp_m_diff1), v_rowsum_acc_f32_1); factx->vtcm_m_vec[r_vec_idx * 2 + 0] = v_m_curr0; factx->vtcm_m_vec[r_vec_idx * 2 + 1] = v_m_curr1; @@ -1532,9 +1659,66 @@ static void fa_softmax_thread(unsigned int n, unsigned int i, void * data) { fa_softmax_impl(n, i, data, has_mask, mask_broadcast, is_g1, has_alibi, has_softcap); } +static inline HVX_Vector hvx_fa_load_sinks(const float * sinks_data, size_t idx, size_t count) { + const HVX_Vector * v_src = (const HVX_Vector *) sinks_data + (idx >> 5); + const size_t lane_off = idx & 31; + const size_t byte_off = lane_off * sizeof(float); + return (lane_off + count > 32) + ? Q6_V_valign_VVR(v_src[1], v_src[0], byte_off) + : Q6_V_vror_VR(v_src[0], byte_off); +} + static __attribute__((noinline)) void fa_build_d_diag_inv_l(struct hmx_fa_context * factx, size_t n_row_tiles, - size_t n_row_tiles_g_br) { + size_t n_row_tiles_g_br, + uint32_t kv_head, + size_t n_rows_g) { + (void) n_row_tiles_g_br; + + // sinks: l += exp(sink - m * ln2) in f32, m and l are in the log2 domain + if (factx->sinks) { + const float * sinks_data = factx->vtcm_sinks; + const size_t G = factx->G; + const size_t head_base = (size_t) kv_head * G; + const HVX_Vector v_ln2 = Q6_V_vsplat_R(EXP_LOGN2); + const HVX_Vector v_head_sinks = (G <= 32) ? hvx_fa_load_sinks(sinks_data, head_base, G) : Q6_V_vzero(); + HVX_Vector v_sink = Q6_V_vzero(); + size_t g_prev = SIZE_MAX; + + for (size_t i = 0; i < n_row_tiles; ++i) { + // the sink pattern of a tile only depends on (i * 32) % G, rebuild it when that changes + const size_t r0 = i * 32; + const size_t g0 = fastmodulo(r0, G, &factx->div_G); + if (g0 != g_prev) { + const size_t rem_g = G - g0; + if (G <= 32) { + const HVX_Vector v_lo = Q6_V_vror_VR(v_head_sinks, g0 * sizeof(float)); + const HVX_Vector v_hi = Q6_V_vror_VR(v_head_sinks, 128 - rem_g * sizeof(float)); + v_sink = Q6_V_vmux_QVV(Q6_Q_vsetq2_R(rem_g * sizeof(float)), v_lo, v_hi); + for (size_t len = G; len < 32; len <<= 1) { + const HVX_VectorPred q_keep = Q6_Q_vsetq_R(len * sizeof(float)); + const HVX_Vector v_shifted = Q6_V_vror_VR(v_sink, 128 - len * sizeof(float)); + v_sink = Q6_V_vmux_QVV(q_keep, v_sink, v_shifted); + } + } else if (rem_g >= 32) { + v_sink = hvx_fa_load_sinks(sinks_data, head_base + g0, 32); + } else { + const HVX_Vector v_lo = hvx_fa_load_sinks(sinks_data, head_base + g0, rem_g); + const HVX_Vector v_hi = hvx_fa_load_sinks(sinks_data, head_base, 32 - rem_g); + v_sink = Q6_V_vmux_QVV(Q6_Q_vsetq_R(rem_g * sizeof(float)), v_lo, Q6_V_vror_VR(v_hi, 128 - rem_g * sizeof(float))); + } + g_prev = g0; + } + + HVX_Vector v_d = HVX_OP_SUB_F32(v_sink, HVX_OP_MUL_F32(factx->vtcm_m_vec[i], v_ln2)); + if (r0 + 32 > n_rows_g) { + const HVX_VectorPred q_valid = Q6_Q_vsetq_R((n_rows_g - r0) * sizeof(float)); + v_d = Q6_V_vmux_QVV(q_valid, v_d, Q6_V_vzero()); + } + factx->vtcm_l_vec[i] = HVX_OP_ADD_F32(factx->vtcm_l_vec[i], hvx_vec_exp_f32(v_d)); + } + } + const HVX_Vector v_offsets = *(const HVX_Vector *) d_tile_scatter_offsets; const HVX_VectorPred q_32_mask = Q6_Q_vsetq_R(32 * sizeof(__fp16)); const HVX_Vector one = hvx_vec_splat_f32(1.0f); @@ -1725,7 +1909,7 @@ static __attribute__((noinline)) void fa_compute_slopes( const float m0 = factx->m0; const float m1 = factx->m1; - __fp16 temp_slopes[512] __attribute__((aligned(128))); + __fp16 * temp_slopes = factx->ddr_slopes; if (G <= 32) { // Fast path: Compute G unique slope values in vector registers HVX_Vector v_val = hvx_alibi_slopes(kv_head, G, n_head_log2, m0, m1); @@ -1743,14 +1927,13 @@ static __attribute__((noinline)) void fa_compute_slopes( } } - // Allocate stack buffer to avoid scalar writes to VTCM (which generates L2 misses) - __fp16 local_slopes[n_rows_g] __attribute__((aligned(128))); - for (size_t r = 0; r < n_rows_g; ++r) { - local_slopes[r] = temp_slopes[fastmodulo(r, G, &factx->div_G)]; + // Replicate the G values in DDR to avoid scalar writes to VTCM (which generates L2 misses) + for (size_t r = G; r < n_rows_g; ++r) { + temp_slopes[r] = temp_slopes[r - G]; } // Copy to VTCM slopes using HVX block copy (both are aligned to 128 bytes) - hvx_copy_f16_aa((uint8_t *)slopes, (const uint8_t *)local_slopes, n_rows_g); + hvx_copy_f16_aa((uint8_t *)slopes, (const uint8_t *)temp_slopes, n_rows_g); } static void fa_push_mask_dma_gqa( @@ -1796,7 +1979,7 @@ static inline void fa_prefetch_block(dma_queue * dma_q, const struct htp_tensor if (mask) { if (__builtin_expect(factx->mask_broadcast, true)) { const dma_addr_t ms_src = mask->data + q_start * mask->nb[1] + im3 * mask->nb[3] + prefetch_start * sizeof(__fp16); - dma_cache_fa_push(dma_q, &factx->m_cache, ms_src, m_line_bytes, mask->nb[1], prefetch_rows * sizeof(__fp16), n_rows_q); + dma_cache_fa_push(dma_q, factx->m_cache, ms_src, m_line_bytes, mask->nb[1], prefetch_rows * sizeof(__fp16), n_rows_q); } else { fa_push_mask_dma_gqa(dma_q, mask, q_start, im3, prefetch_start, kv_head, G, m_line_bytes, prefetch_rows, n_rows_q, factx); } @@ -1911,7 +2094,29 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { const uint32_t dst_e_size = (dst->type == HTP_TYPE_F32) ? sizeof(float) : sizeof(__fp16); const bool can_split = htp_tensor_can_row_partition(dst, dst_e_size); - if (kparams->head_split && can_split && n_kv_heads >= mdev_count && n_kv_heads % mdev_count == 0) { + if ((kparams->flags & HTP_FA_FLAG_TEAM_SPLIT) && can_split) { + // KV heads split across teams, Q-blocks split within a team + uint32_t n_teams, team_size; + htp_fa_mdev_teams(n_kv_heads, mdev_count, kparams->head_split != 0, &n_teams, &team_size); + + const uint32_t team = mdev_idx / team_size; + const uint32_t member = mdev_idx - team * team_size; + const uint32_t kv_per_team = n_kv_heads / n_teams; + kv_head_min = team * kv_per_team; + kv_head_max = kv_head_min + kv_per_team; + + const uint32_t base = n_q_blocks / team_size; + const uint32_t rem = n_q_blocks - base * team_size; + const uint32_t b0 = member * base + MIN(member, rem); + const uint32_t nblk = base + (member < rem ? 1 : 0); + + if (nblk == 0) { + return HTP_STATUS_OK; + } + + q_start_min = b0 * Br; + q_start_max = MIN((b0 + nblk) * Br, neq1); + } else if (kparams->head_split && can_split && n_kv_heads >= mdev_count && n_kv_heads % mdev_count == 0) { const uint32_t kv_per_core = n_kv_heads / mdev_count; kv_head_min = mdev_idx * kv_per_core; kv_head_max = kv_head_min + kv_per_core; @@ -1980,6 +2185,7 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { factx.vtcm_mask_buf = VTCM_LAYOUT_PTR(__fp16, base, L.off_mask_buf); factx.mask_buf_row_stride = L.mask_buf_row_stride; factx.q_tile_bytes = L.q_tile_bytes; + factx.k_tile_bytes = L.k_tile_bytes; factx.o_tile_bytes = L.o_tile_bytes; factx.col_vec_bytes = L.col_vec_bytes; factx.d_tile_bytes = L.d_tile_bytes; @@ -1988,7 +2194,14 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { const size_t m_line_bytes = L.m_line_bytes; // used by the mask DMAs in the KV loop - dma_cache_fa_init(&factx.m_cache, (uint8_t *) factx.vtcm_mask_buf, L.m_buf_slot_bytes, HMX_FA_DMA_CACHE_SIZE); + struct hmx_fa_ddr_spad * ddr = (struct hmx_fa_ddr_spad *) fa_get_ddr_spad(octx, sizeof(struct hmx_fa_ddr_spad) + factx.g_br * sizeof(__fp16)); + if (!ddr) { + return HTP_STATUS_INTERNAL_ERR; + } + + factx.ddr_slopes = ddr->slopes; + factx.m_cache = &octx->dma_cache_fa[0]; + dma_cache_fa_init(factx.m_cache, (uint8_t *) factx.vtcm_mask_buf, L.m_buf_slot_bytes, HMX_FA_DMA_CACHE_SIZE); // Head-dim padding: the K/V DMA staging buffers and the flat-Q buffer are laid out // with padded row strides (size_{k,v,q}_row_padded, covering D_pad columns) but the @@ -2010,7 +2223,10 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { // ======== Initialize HMX output scales ======== hmx_init_column_scales(factx.vtcm_hmx_scales_id, Q6_V_vsplat_R(0x3c00)); // 1.0 - hmx_init_column_scales(factx.vtcm_hmx_scales_qk, hvx_vec_splat_f16(factx.scale)); + { + union { __fp16 f; uint16_t u; } sc = { .f = factx.scale }; + hmx_init_column_scales(factx.vtcm_hmx_scales_qk, Q6_V_vsplat_R(sc.u)); + } // ======== DMA setup ======== dma_queue * const dma_q = ctx->dma[0]; @@ -2029,7 +2245,6 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { const size_t q_src_stride = q_transposed ? q->nb[2] : q->nb[1]; const size_t q_row_bytes_untransposed = factx.G * factx.DK * qo_element_size; const size_t q_row_bytes_trans_factor = factx.DK * qo_element_size; - const uint32_t kv_rows0 = hex_smin(Bc, nek1); // ======== Reusable job descriptors for pipeline ======== hmx_fa_qk_job_t qk_job; @@ -2045,34 +2260,51 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { const size_t g_br_actual = hex_align_up(n_rows_g, HMX_FP16_TILE_N_ROWS); const size_t n_row_tiles = g_br_actual / HMX_FP16_TILE_N_ROWS; + uint16_t * active_blocks = ddr->active_blocks; + uint32_t n_active_blocks = factx.n_kv_blocks; + if (mask && factx.mask_broadcast && factx.n_kv_blocks > 1) { + const size_t scratch_bytes = factx.k_tile_bytes * (factx.pipeline ? 2 : 1); + n_active_blocks = fa_scan_active_blocks( + dma_q, mask, q_start, n_rows_q, 0, im3, nek1, Bc, + factx.n_kv_blocks, factx.vtcm_k_tiles[0], scratch_bytes, active_blocks); + } else { + #pragma clang loop vectorize(disable) + for (uint32_t b = 0; b < factx.n_kv_blocks; ++b) { + active_blocks[b] = (uint16_t) b; + } + } + const uint32_t b0 = (n_active_blocks > 0) ? active_blocks[0] : 0; + const uint32_t b0_start = b0 * Bc; + const uint32_t b0_rows = hex_smin(Bc, nek1 - b0_start); + for (uint32_t kv_head = kv_head_min; kv_head < kv_head_max; ++kv_head) { const uint32_t ik2 = kv_head; const uint32_t ik3 = fastdiv(ib3, &kparams->broadcast_rk3); const uint32_t iv2 = kv_head; const uint32_t iv3 = fastdiv(ib3, &kparams->broadcast_rv3); - // 1. Push Q and KV DMAs for the very first iteration. - // Subsequent iterations are enqueued early at the end of the previous iteration. - if (ib3 == 0 && q_start == q_start_min && kv_head == kv_head_min) { + // 1. Push Q and KV DMAs for the first kv_head of this q_start block. + // Subsequent kv_head iterations are enqueued early at the end of the previous iteration. + if (kv_head == kv_head_min) { const dma_addr_t q_ptr = q->data + q_start * q->nb[1] + (kv_head * factx.G) * q->nb[2] + ib3 * q->nb[3]; const size_t q_row_bytes = q_transposed ? n_rows_q * q_row_bytes_trans_factor : q_row_bytes_untransposed; const size_t n_rows = q_transposed ? factx.G : n_rows_q; dma_queue_push(dma_q, dma_make_data(factx.vtcm_q_dma, q_ptr), q_row_bytes, hex_smax(q_src_stride, q_row_bytes), q_row_bytes, n_rows); - if (factx.n_kv_blocks > 0) { - const dma_addr_t k_src = k->data + ik2 * k->nb[2] + ik3 * k->nb[3]; - dma_queue_push(dma_q, dma_make_data(factx.vtcm_k_fp16[0], k_src), size_k_row_padded, k->nb[1], size_k_row, kv_rows0); + if (n_active_blocks > 0) { + const dma_addr_t k_src = k->data + b0_start * k->nb[1] + ik2 * k->nb[2] + ik3 * k->nb[3]; + dma_queue_push(dma_q, dma_make_data(factx.vtcm_k_fp16[0], k_src), size_k_row_padded, k->nb[1], size_k_row, b0_rows); - const dma_addr_t v_src = v->data + iv2 * v->nb[2] + iv3 * v->nb[3]; - dma_queue_push(dma_q, dma_make_data(factx.vtcm_v_fp16[0], v_src), size_v_row_padded, v->nb[1], size_v_row, kv_rows0); + const dma_addr_t v_src = v->data + b0_start * v->nb[1] + iv2 * v->nb[2] + iv3 * v->nb[3]; + dma_queue_push(dma_q, dma_make_data(factx.vtcm_v_fp16[0], v_src), size_v_row_padded, v->nb[1], size_v_row, b0_rows); if (factx.pipeline && mask) { if (__builtin_expect(factx.mask_broadcast, true)) { - const dma_addr_t ms_src = mask->data + q_start * mask->nb[1] + im3 * mask->nb[3] + 0; - dma_cache_fa_push(dma_q, &factx.m_cache, ms_src, m_line_bytes, mask->nb[1], kv_rows0 * sizeof(__fp16), n_rows_q); + const dma_addr_t ms_src = mask->data + q_start * mask->nb[1] + im3 * mask->nb[3] + b0_start * sizeof(__fp16); + dma_cache_fa_push(dma_q, factx.m_cache, ms_src, m_line_bytes, mask->nb[1], b0_rows * sizeof(__fp16), n_rows_q); } else { - fa_push_mask_dma_gqa(dma_q, mask, q_start, im3, 0, kv_head, G, m_line_bytes, kv_rows0, n_rows_q, &factx); + fa_push_mask_dma_gqa(dma_q, mask, q_start, im3, b0_start, kv_head, G, m_line_bytes, b0_rows, n_rows_q, &factx); } } } @@ -2104,27 +2336,28 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { hmx_fa_qk_job_t qk_job[2]; hmx_fa_o_update_job_t ou_job[2]; - // Prefetch block 1 early if there are multiple blocks - if (factx.n_kv_blocks > 1) { - fa_prefetch_block(dma_q, k, v, mask, 1, Bc, size_k_row_padded, size_k_row, size_v_row_padded, size_v_row, + // Prefetch second active block early if there are multiple active blocks + if (n_active_blocks > 1) { + fa_prefetch_block(dma_q, k, v, mask, active_blocks[1], Bc, size_k_row_padded, size_k_row, size_v_row_padded, size_v_row, ik2, ik3, iv2, iv3, q_start, im3, kv_head, G, m_line_bytes, n_rows_q, nek1, 1, &factx); } // Prep and start QK-dot(0) void * curr_k0 = (void *) dma_queue_pop(dma_q).dst; - fa_phase_k_interleave(&factx, kv_rows0, k_src_stride, curr_k0, 0, 0); + fa_phase_k_interleave(&factx, b0_rows, k_src_stride, curr_k0, b0_start, 0); qk_job[0].q_tiles = factx.vtcm_q_tiles; qk_job[0].k_tiles = factx.vtcm_k_tiles[0]; qk_job[0].s_tiles = factx.vtcm_s_tiles[0]; qk_job[0].n_row_tiles = n_row_tiles; - qk_job[0].n_col_tiles = hmx_ceil_div(kv_rows0, HMX_FP16_TILE_N_COLS); + qk_job[0].n_col_tiles = hmx_ceil_div(b0_rows, HMX_FP16_TILE_N_COLS); qk_job[0].n_dot_tiles = DK_pad / 32; qk_job[0].n_tiles_per_bc = n_tiles_per_bc; qk_job[0].hmx_scales = factx.vtcm_hmx_scales_qk; hmx_queue_push(hmx_q, hmx_queue_make_desc(hmx_fa_qk_dot_worker, &qk_job[0])); - for (uint32_t kv_blk = 0; kv_blk < factx.n_kv_blocks; ++kv_blk) { + for (uint32_t step = 0; step < n_active_blocks; ++step) { + const uint32_t kv_blk = active_blocks[step]; const uint32_t kv_start = kv_blk * Bc; const uint32_t kv_rows = hex_smin(Bc, nek1 - kv_start); const size_t n_col_tiles = hmx_ceil_div(kv_rows, HMX_FP16_TILE_N_COLS); @@ -2144,13 +2377,14 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { } } - // ---- 3. Start HMX O update for block kv_blk - 1 (reads P[1 - buf_idx], V[1 - buf_idx], D) ---- - // O update relys on the previous block's P and V tiles. + // ---- 3. Start HMX O update for step - 1 (reads P[1 - buf_idx], V[1 - buf_idx], D) ---- + // O update relies on the previous block's P and V tiles. // O update MUST be pushed before the next block's QK-dot: hmx_queue_pop() retires the // oldest descriptor, so push order alone decides which pop waits for which job. // If OU went in after QK(i+1), the pop below would retire QK(i+1) and leave // OU(i-1) in flight into the next iteration, where V-prep overwrites V[prev_buf]. - if (kv_blk > 0) { + if (step > 0) { + const uint32_t prev_blk = active_blocks[step - 1]; const size_t prev_buf = 1 - buf_idx; ou_job[prev_buf].o_curr = o_tile_curr; ou_job[prev_buf].o_prev = o_tile_prev; @@ -2160,16 +2394,17 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { ou_job[prev_buf].hmx_scales = factx.vtcm_hmx_scales_id; ou_job[prev_buf].n_row_tiles = n_row_tiles; ou_job[prev_buf].n_col_tiles = - hmx_ceil_div(hex_smin(Bc, nek1 - (kv_blk - 1) * Bc), HMX_FP16_TILE_N_COLS); + hmx_ceil_div(hex_smin(Bc, nek1 - prev_blk * Bc), HMX_FP16_TILE_N_COLS); ou_job[prev_buf].n_row_tiles_g_br = n_row_tiles_g_br; ou_job[prev_buf].n_tiles_per_bc = n_tiles_per_bc; ou_job[prev_buf].DV = DV_pad; hmx_queue_push(hmx_q, hmx_queue_make_desc(hmx_fa_o_update_worker, &ou_job[prev_buf])); } - // ---- 4. Pop and run K-prep for next block & push next QK-dot ---- - if (kv_blk + 1 < factx.n_kv_blocks) { - const uint32_t next_start = (kv_blk + 1) * Bc; + // ---- 4. Pop and run K-prep for next active block & push next QK-dot ---- + if (step + 1 < n_active_blocks) { + const uint32_t next_blk = active_blocks[step + 1]; + const uint32_t next_start = next_blk * Bc; const uint32_t next_rows = hex_smin(Bc, nek1 - next_start); const size_t next_buf = 1 - buf_idx; @@ -2216,15 +2451,15 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { // Run Softmax on HVX (blocking call) fa_phase_softmax_and_build_d(&factx, &sargs, n_row_tiles, n_row_tiles_g_br); - // Wait for HMX O update for block kv_blk - 1 to finish - if (kv_blk > 0) { + // Wait for HMX O update for step - 1 to finish + if (step > 0) { hmx_queue_pop(hmx_q); hex_swap_ptr((void **) &o_tile_curr, (void **) &o_tile_prev); } - // Prefetch block kv_blk + 2 - if (kv_blk + 2 < factx.n_kv_blocks) { - fa_prefetch_block(dma_q, k, v, mask, kv_blk + 2, Bc, size_k_row_padded, size_k_row, size_v_row_padded, size_v_row, + // Prefetch block step + 2 + if (step + 2 < n_active_blocks) { + fa_prefetch_block(dma_q, k, v, mask, active_blocks[step + 2], Bc, size_k_row_padded, size_k_row, size_v_row_padded, size_v_row, ik2, ik3, iv2, iv3, q_start, im3, kv_head, G, m_line_bytes, n_rows_q, nek1, buf_idx, &factx); } @@ -2232,8 +2467,8 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { } // Epilogue - if (factx.n_kv_blocks > 0) { - const uint32_t last_blk = factx.n_kv_blocks - 1; + if (n_active_blocks > 0) { + const uint32_t last_blk = active_blocks[n_active_blocks - 1]; const size_t last_cols = hmx_ceil_div(hex_smin(Bc, nek1 - last_blk * Bc), HMX_FP16_TILE_N_COLS); ou_job[0].o_curr = o_tile_curr; ou_job[0].o_prev = o_tile_prev; @@ -2250,7 +2485,7 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { // Overlapped: run HVX build diag inv L while HMX is busy executing the update htp_trace_event_start(tr_hvx, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) q_start); - fa_build_d_diag_inv_l(&factx, n_row_tiles, n_row_tiles_g_br); + fa_build_d_diag_inv_l(&factx, n_row_tiles, n_row_tiles_g_br, kv_head, n_rows_g); htp_trace_event_stop(tr_hvx, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) q_start); hmx_queue_pop(hmx_q); @@ -2259,7 +2494,8 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { } else { // Fallback path - for (uint32_t kv_blk = 0; kv_blk < factx.n_kv_blocks; ++kv_blk) { + for (uint32_t step = 0; step < n_active_blocks; ++step) { + const uint32_t kv_blk = active_blocks[step]; const uint32_t kv_start = kv_blk * Bc; const uint32_t kv_rows = hex_smin(Bc, nek1 - kv_start); const size_t n_col_tiles = hmx_ceil_div(kv_rows, HMX_FP16_TILE_N_COLS); @@ -2267,14 +2503,15 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { if (mask) { if (__builtin_expect(factx.mask_broadcast, true)) { const dma_addr_t ms_src = mask->data + q_start * mask->nb[1] + im3 * mask->nb[3] + kv_start * sizeof(__fp16); - dma_cache_fa_push(dma_q, &factx.m_cache, ms_src, m_line_bytes, mask->nb[1], kv_rows * sizeof(__fp16), n_rows_q); + dma_cache_fa_push(dma_q, factx.m_cache, ms_src, m_line_bytes, mask->nb[1], kv_rows * sizeof(__fp16), n_rows_q); } else { fa_push_mask_dma_gqa(dma_q, mask, q_start, im3, kv_start, kv_head, G, m_line_bytes, kv_rows, n_rows_q, &factx); } } - if (kv_blk + 1 < factx.n_kv_blocks) { - const uint32_t prefetch_start = (kv_blk + 1) * Bc; + if (step + 1 < n_active_blocks) { + const uint32_t prefetch_blk = active_blocks[step + 1]; + const uint32_t prefetch_start = prefetch_blk * Bc; const uint32_t prefetch_rows = hex_smin(Bc, nek1 - prefetch_start); const size_t prefetch_buf = 1 - buf_idx; const dma_addr_t k_prefetch_src = k->data + prefetch_start * k->nb[1] + ik2 * k->nb[2] + ik3 * k->nb[3]; @@ -2352,10 +2589,10 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { ou_job.DV = DV_pad; hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_fa_o_update_worker, &ou_job)); - if (kv_blk + 1 == factx.n_kv_blocks) { + if (step + 1 == n_active_blocks) { // Overlapped: run HVX build diag inv L while HMX is busy executing the update htp_trace_event_start(tr_hvx, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) q_start); - fa_build_d_diag_inv_l(&factx, n_row_tiles, n_row_tiles_g_br); + fa_build_d_diag_inv_l(&factx, n_row_tiles, n_row_tiles_g_br, kv_head, n_rows_g); htp_trace_event_stop(tr_hvx, HTP_TRACE_EVT_HVX_O_PROC, (uint16_t) q_start); } hmx_queue_pop(ctx->hmx_queue); @@ -2367,53 +2604,32 @@ int hmx_flash_attn_ext(struct htp_ops_context * octx) { } } - // Enqueue DMAs for the next iteration early so they overlap with O-PROC - uint32_t next_kv_head = kv_head + 1; - uint32_t next_q_start = q_start; - uint32_t next_ib3 = ib3; - if (next_kv_head >= kv_head_max) { - next_kv_head = kv_head_min; - next_q_start = q_start + Br; - if (next_q_start >= q_start_max) { - next_q_start = q_start_min; - next_ib3 = ib3 + 1; - } - } - bool has_next = (next_ib3 < neq3); + // Enqueue DMAs for the next kv_head early so they overlap with O-PROC + const uint32_t next_kv_head = kv_head + 1; + const bool has_next = (next_kv_head < kv_head_max); if (has_next) { - const uint32_t next_n_rows_q = hex_smin(Br, neq1 - next_q_start); - const dma_addr_t next_q_ptr = q->data + next_q_start * q->nb[1] + (next_kv_head * factx.G) * q->nb[2] + next_ib3 * q->nb[3]; - const size_t next_q_row_bytes = q_transposed ? next_n_rows_q * q_row_bytes_trans_factor : q_row_bytes_untransposed; - const size_t next_n_rows = q_transposed ? factx.G : next_n_rows_q; + const dma_addr_t next_q_ptr = q->data + q_start * q->nb[1] + (next_kv_head * factx.G) * q->nb[2] + ib3 * q->nb[3]; + const size_t next_q_row_bytes = q_transposed ? n_rows_q * q_row_bytes_trans_factor : q_row_bytes_untransposed; + const size_t next_n_rows = q_transposed ? factx.G : n_rows_q; dma_queue_push(dma_q, dma_make_data(factx.vtcm_q_dma, next_q_ptr), next_q_row_bytes, hex_smax(q_src_stride, next_q_row_bytes), next_q_row_bytes, next_n_rows); - if (factx.n_kv_blocks > 0) { + if (n_active_blocks > 0) { const uint32_t next_ik2 = next_kv_head; const uint32_t next_iv2 = next_kv_head; - uint32_t next_ik3 = ik3; - uint32_t next_iv3 = iv3; - if (next_ib3 != ib3) { - next_ik3 = fastdiv(next_ib3, &kparams->broadcast_rk3); - next_iv3 = fastdiv(next_ib3, &kparams->broadcast_rv3); - } - const dma_addr_t next_k_src = k->data + next_ik2 * k->nb[2] + next_ik3 * k->nb[3]; - dma_queue_push(dma_q, dma_make_data(factx.vtcm_k_fp16[0], next_k_src), size_k_row_padded, k->nb[1], size_k_row, kv_rows0); + const dma_addr_t next_k_src = k->data + b0_start * k->nb[1] + next_ik2 * k->nb[2] + ik3 * k->nb[3]; + dma_queue_push(dma_q, dma_make_data(factx.vtcm_k_fp16[0], next_k_src), size_k_row_padded, k->nb[1], size_k_row, b0_rows); - const dma_addr_t next_v_src = v->data + next_iv2 * v->nb[2] + next_iv3 * v->nb[3]; - dma_queue_push(dma_q, dma_make_data(factx.vtcm_v_fp16[0], next_v_src), size_v_row_padded, v->nb[1], size_v_row, kv_rows0); + const dma_addr_t next_v_src = v->data + b0_start * v->nb[1] + next_iv2 * v->nb[2] + iv3 * v->nb[3]; + dma_queue_push(dma_q, dma_make_data(factx.vtcm_v_fp16[0], next_v_src), size_v_row_padded, v->nb[1], size_v_row, b0_rows); if (factx.pipeline && mask) { - uint32_t next_im3 = im3; - if (next_ib3 != ib3) { - next_im3 = fastmodulo(next_ib3, mask->ne[3], &factx.src3_div3); - } if (__builtin_expect(factx.mask_broadcast, true)) { - const dma_addr_t ms_src = mask->data + next_q_start * mask->nb[1] + next_im3 * mask->nb[3] + 0; - dma_cache_fa_push(dma_q, &factx.m_cache, ms_src, m_line_bytes, mask->nb[1], kv_rows0 * sizeof(__fp16), next_n_rows_q); + const dma_addr_t ms_src = mask->data + q_start * mask->nb[1] + im3 * mask->nb[3] + b0_start * sizeof(__fp16); + dma_cache_fa_push(dma_q, factx.m_cache, ms_src, m_line_bytes, mask->nb[1], b0_rows * sizeof(__fp16), n_rows_q); } else { - fa_push_mask_dma_gqa(dma_q, mask, next_q_start, next_im3, 0, next_kv_head, G, m_line_bytes, kv_rows0, next_n_rows_q, &factx); + fa_push_mask_dma_gqa(dma_q, mask, q_start, im3, b0_start, next_kv_head, G, m_line_bytes, b0_rows, n_rows_q, &factx); } } } @@ -2461,7 +2677,7 @@ int op_flash_attn_ext(struct htp_ops_context * octx) { const struct htp_fa_kernel_params * kparams = (const struct htp_fa_kernel_params *) octx->kernel_params; - if (kparams->kernel_type == HTP_FA_KERNEL_UNSUPPORTED) { + if (kparams->kernel_type == HTP_FA_KERNEL_UNSUPPORTED || kparams->n_kv_blocks > FA_MAX_KV_BLOCKS) { return HTP_STATUS_NO_SUPPORT; } @@ -2514,8 +2730,15 @@ int op_flash_attn_ext(struct htp_ops_context * octx) { if (n_head > 512) { return HTP_STATUS_NO_SUPPORT; } + + factx.ddr = (struct hvx_fa_ddr_spad *) fa_get_ddr_spad(octx, sizeof(struct hvx_fa_ddr_spad)); + if (!factx.ddr) { + return HTP_STATUS_INTERNAL_ERR; + } + factx.m_cache = octx->dma_cache_dm; + for (uint32_t h = 0; h < n_head; ++h) { - factx.slopes[h] = (__fp16) ((kparams->max_bias > 0.0f) ? alibi_slope(h, factx.n_head_log2, factx.m0, factx.m1) : 1.0f); + factx.ddr->slopes[h] = (__fp16) ((kparams->max_bias > 0.0f) ? alibi_slope(h, factx.n_head_log2, factx.m0, factx.m1) : 1.0f); } // total rows in q @@ -2576,12 +2799,21 @@ int op_flash_attn_ext(struct htp_ops_context * octx) { uint8_t * const base = octx->ctx->vtcm_base; - factx.spad_q = VTCM_LAYOUT_PTR(uint8_t, base, L.off_q); - factx.spad_k = VTCM_LAYOUT_PTR(uint8_t, base, L.off_k); - factx.spad_v = VTCM_LAYOUT_PTR(uint8_t, base, L.off_v); - factx.spad_m = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, base, L.off_m, has_mask); - factx.spad_a = VTCM_LAYOUT_PTR(uint8_t, base, L.off_a); - factx.spad_sinks = VTCM_LAYOUT_PTR_OPTIONAL(float, base, L.off_sinks, has_sinks); + factx.spad_q = VTCM_LAYOUT_PTR(uint8_t, base, L.off_q); + factx.spad_k = VTCM_LAYOUT_PTR(uint8_t, base, L.off_k); + factx.spad_v = VTCM_LAYOUT_PTR(uint8_t, base, L.off_v); + factx.spad_m = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, base, L.off_m, has_mask); + factx.spad_a = VTCM_LAYOUT_PTR(uint8_t, base, L.off_a); + factx.spad_sinks = VTCM_LAYOUT_PTR_OPTIONAL(float, base, L.off_sinks, has_sinks); + factx.n_active_blocks = factx.n_blocks; + factx.shared_active_blocks = false; + + if (has_mask && neq1 == 1 && neq3 == 1 && mask->ne[2] == 1 && factx.n_blocks > 1 && factx.n_blocks <= FA_MAX_KV_BLOCKS) { + factx.n_active_blocks = fa_scan_active_blocks( + octx->ctx->dma[0], mask, 0, 1, 0, 0, k->ne[1], FLASH_ATTN_BLOCK_SIZE, + factx.n_blocks, factx.spad_k, factx.size_k_block * 2, factx.ddr->active_blocks); + factx.shared_active_blocks = true; + } if (has_sinks) { const struct htp_tensor * sinks = octx->src[4]; diff --git a/ggml/src/ggml-hexagon/htp/flash-attn-ops.h b/ggml/src/ggml-hexagon/htp/flash-attn-ops.h index 04538842c6a5..f2654f0a83dc 100644 --- a/ggml/src/ggml-hexagon/htp/flash-attn-ops.h +++ b/ggml/src/ggml-hexagon/htp/flash-attn-ops.h @@ -32,10 +32,20 @@ enum htp_fa_kernel_type { HTP_FA_KERNEL_HMX }; +// Multicore: gcd(n_kv_heads, N) teams own the KV heads, team members share the Q-blocks +#define HTP_FA_FLAG_TEAM_SPLIT 0x01 + +static inline void htp_fa_mdev_teams(uint32_t n_kv_heads, uint32_t mdev_count, bool head_split, + uint32_t * n_teams, uint32_t * team_size) { + const uint32_t t = (head_split && n_kv_heads > 0 && mdev_count > 1) ? hex_gcd_u32(n_kv_heads, mdev_count) : 1; + *n_teams = t; + *team_size = mdev_count > 1 ? mdev_count / t : 1; +} + struct htp_fa_kernel_params { uint8_t kernel_type; // enum htp_fa_kernel_type uint8_t head_split; // 1 = partition by KV heads in multicore, 0 = token partition - uint8_t flags; // reserved + uint8_t flags; // HTP_FA_FLAG_* uint8_t n_threads; // Number of threads to run // Common parameters @@ -49,9 +59,6 @@ struct htp_fa_kernel_params { float logit_softcap; uint32_t vtcm_size; - uint32_t qrows; - uint32_t qrows_per_thread; - uint32_t qrow_start; float m0; float m1; uint32_t n_head_log2; @@ -67,8 +74,6 @@ struct htp_fa_kernel_params { union { struct { uint32_t g_br; - uint32_t row_buf_stride; - uint32_t mask_buf_row_stride; int32_t mask_broadcast; int32_t pipeline; struct fastdiv_values div_G; @@ -85,6 +90,8 @@ struct htp_fa_kernel_params { #if defined(__cplusplus) static_assert(sizeof(struct htp_fa_kernel_params) <= 128, "htp_fa_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_fa_kernel_params) <= 128, "htp_fa_kernel_params is too large for kernel_params blob"); #endif // VTCM region layout for the HMX flash-attention kernel. @@ -126,6 +133,7 @@ struct hmx_fa_vtcm_layout { // Region byte sizes reused by the device at runtime (not just for allocation). size_t q_tile_bytes; size_t o_tile_bytes; + size_t k_tile_bytes; size_t s_tile_bytes; // S and P tiles (same size) size_t d_tile_bytes; // d_tiles[0..1] + d_inv_l, allocated back to back size_t m_line_bytes; // one mask row @@ -141,6 +149,8 @@ struct hmx_fa_vtcm_layout { size_t total_bytes; }; +#define FA_MAX_KV_BLOCKS 1024 + // Build the VTCM layout. static inline void hmx_fa_vtcm_layout_build(struct hmx_fa_vtcm_layout * L, @@ -224,6 +234,7 @@ static inline void hmx_fa_vtcm_layout_build(struct hmx_fa_vtcm_layout * L, L->q_tile_bytes = q_tile_size; L->o_tile_bytes = o_tile_size; + L->k_tile_bytes = k_tile_size; L->col_vec_bytes = col_vec_size; L->s_tile_bytes = s_tile_size; // Measured from the actual offsets rather than assumed to be N * d_tile_size, so @@ -321,7 +332,8 @@ static inline int hmx_fa_find_chunk_size(size_t * Br_out, size_t n_threads, bool is_q_fp32, bool has_sinks, - size_t n_heads) { + size_t n_heads, + size_t q_split) { const size_t T = HMX_FP16_TILE_N_ROWS; // 32 const size_t br_unit = hmx_ceil_div(T, gqa_factor); const size_t bc_unit = HMX_FP16_TILE_N_COLS * 2; // 64 @@ -332,8 +344,12 @@ static inline int hmx_fa_find_chunk_size(size_t * Br_out, // Pipeline constraint: cap Bc so n_kv_blocks >= FA_MIN_KV_BLOCKS. // Only relax when kv_len is too short to form enough blocks. - const size_t Bc_limit = can_pipeline ? hex_align_down(kv_len / FA_MIN_KV_BLOCKS, bc_unit) : - (kv_len >= bc_unit ? hex_align_down(kv_len, bc_unit) : bc_unit); + size_t Bc_limit = can_pipeline ? hex_align_down(kv_len / FA_MIN_KV_BLOCKS, bc_unit) : + (kv_len >= bc_unit ? hex_align_down(kv_len, bc_unit) : bc_unit); + // For small-Q SWA-sized KV caches (qo_len <= 16, kv_len <= 2048), cap Bc at 256 for block-skipping granularity + if (qo_len <= 16 && kv_len <= 2048 && Bc_limit > 256) { + Bc_limit = 256; + } // Cost coefficients calibrated from profiling const size_t c_q_fixed = 800; // per-Q-block: q_load + epilogue o_update + o_norm + o_store const size_t c_iter_base = 200; // per-KV-iter base (HMX dot/update + DMA) @@ -357,7 +373,8 @@ static inline int hmx_fa_find_chunk_size(size_t * Br_out, const size_t vecs_per_t = n_use > 0 ? (n_row_vec_cnt + n_use - 1) / n_use : 1; const size_t c_iter_actual = c_iter_base + c_softmax * vecs_per_t; - const size_t cost = q_blocks * (c_q_fixed + kv_blocks * c_iter_actual); + const size_t q_blocks_nsp = (q_blocks + q_split - 1) / (q_split ? q_split : 1); + const size_t cost = q_blocks_nsp * (c_q_fixed + kv_blocks * c_iter_actual); const size_t mn = Br * Bc; if (cost < best_cost || (cost == best_cost && mn > best_mn)) { diff --git a/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.c b/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.c index 1dd828db7b84..a70f411858c6 100644 --- a/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.c +++ b/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.c @@ -1456,9 +1456,10 @@ static inline void gdn_dma_push_chunk_gb( const dma_addr_t g_dma = g->data + (uint64_t) iv3 * g->nb[3] + (uint64_t) t_chunk * g->nb[2] + (uint64_t) iv1 * g->nb[1]; const dma_addr_t beta_dma = beta->data + (uint64_t) iv3 * beta->nb[3] + (uint64_t) t_chunk * beta->nb[2] + (uint64_t) iv1 * beta->nb[1]; const uint32_t row_bytes = n_batch * sizeof(float); + const uint32_t dst_stride = (n_batch > 1) ? row_bytes + sizeof(float) : row_bytes; - dma_queue_push(dma_q, dma_make_data(vtcm_g_raw, g_dma), row_bytes, g->nb[2], row_bytes, chunk_size); - dma_queue_push(dma_q, dma_make_data(vtcm_b_raw, beta_dma), row_bytes, beta->nb[2], row_bytes, chunk_size); + dma_queue_push(dma_q, dma_make_data(vtcm_g_raw, g_dma), dst_stride, g->nb[2], row_bytes, chunk_size); + dma_queue_push(dma_q, dma_make_data(vtcm_b_raw, beta_dma), dst_stride, beta->nb[2], row_bytes, chunk_size); } static inline void gdn_pack_s_col_tiles( @@ -1707,19 +1708,16 @@ static void gdn_hvx_phase1a_worker(unsigned int n, unsigned int i, void * data) hvx_vmem(head->b_f32[curr_buf] + 0) = hvx_vmem(bctx->vtcm_b_raw + 0); hvx_vmem(head->b_f32[curr_buf] + 32) = hvx_vmem(bctx->vtcm_b_raw + 32); } else { - int32_t offsets[32] __attribute__((aligned(128))); - for (int k = 0; k < 32; ++k) { - offsets[k] = k * n_batch * sizeof(float); - } - HVX_Vector vv = *(const HVX_Vector *) offsets; + const uint32_t vtcm_stride = (n_batch + 1) * sizeof(float); + const HVX_Vector vv = hvx_vec_gather_offsets_w(vtcm_stride); const size_t rt_g = (size_t) ((const uint8_t *) bctx->vtcm_g_raw + i * sizeof(float)); const size_t rt_b = (size_t) ((const uint8_t *) bctx->vtcm_b_raw + i * sizeof(float)); - const size_t mu = 64 * n_batch * sizeof(float); + const size_t mu = 64 * vtcm_stride; Q6_vgather_ARMVw((HVX_Vector *) (head->g_f32[curr_buf] + 0), rt_g, mu, vv); - Q6_vgather_ARMVw((HVX_Vector *) (head->g_f32[curr_buf] + 32), rt_g + 32 * n_batch * sizeof(float), mu, vv); + Q6_vgather_ARMVw((HVX_Vector *) (head->g_f32[curr_buf] + 32), rt_g + 32 * vtcm_stride, mu, vv); Q6_vgather_ARMVw((HVX_Vector *) (head->b_f32[curr_buf] + 0), rt_b, mu, vv); - Q6_vgather_ARMVw((HVX_Vector *) (head->b_f32[curr_buf] + 32), rt_b + 32 * n_batch * sizeof(float), mu, vv); + Q6_vgather_ARMVw((HVX_Vector *) (head->b_f32[curr_buf] + 32), rt_b + 32 * vtcm_stride, mu, vv); } const uint32_t t_chunk = bctx->c * 64; @@ -2270,46 +2268,9 @@ static int gated_delta_net_f32_hmx_chunked( } int op_gated_delta_net(struct htp_ops_context * octx) { - const struct htp_tensor * q = octx->src[0]; - const struct htp_tensor * k = octx->src[1]; - const struct htp_tensor * v = octx->src[2]; - const struct htp_tensor * g = octx->src[3]; - const struct htp_tensor * beta = octx->src[4]; - const struct htp_tensor * state = octx->src[5]; - const struct htp_tensor * dst = octx->dst; + const struct htp_tensor * dst = octx->dst; - if (q->type != HTP_TYPE_F32 || k->type != HTP_TYPE_F32 || v->type != HTP_TYPE_F32 || - g->type != HTP_TYPE_F32 || beta->type != HTP_TYPE_F32 || state->type != HTP_TYPE_F32 || - dst->type != HTP_TYPE_F32) { - return HTP_STATUS_NO_SUPPORT; - } - - const uint32_t S_v = v->ne[0]; - const uint32_t H = v->ne[1]; - const uint32_t n_tokens = v->ne[2]; - const uint32_t n_seqs = v->ne[3]; - const uint32_t K = octx->op_params[0]; - - if (S_v == 0 || S_v > HTP_GDN_MAX_SV || H == 0 || n_tokens == 0 || n_seqs == 0) { - return HTP_STATUS_NO_SUPPORT; - } - if ((g->ne[0] != 1 && g->ne[0] != S_v) || beta->ne[0] != 1) { - return HTP_STATUS_NO_SUPPORT; - } - if (q->ne[0] != S_v || k->ne[0] != S_v || q->ne[1] == 0 || k->ne[1] == 0 || - q->ne[2] != n_tokens || k->ne[2] != n_tokens || q->ne[3] == 0 || k->ne[3] == 0 || - (n_seqs % q->ne[3]) != 0 || (n_seqs % k->ne[3]) != 0) { - return HTP_STATUS_NO_SUPPORT; - } - // state holds s0 only: [S_v, S_v, H, n_seqs] - if (state->ne[0] != S_v || state->ne[1] != S_v || state->ne[2] != H || state->ne[3] != n_seqs) { - return HTP_STATUS_NO_SUPPORT; - } - if (dst->ne[0] != S_v * H || dst->ne[1] != n_tokens * n_seqs + S_v * n_seqs * K) { - return HTP_STATUS_NO_SUPPORT; - } - - for (int i = 0; i < 5; i++) { + for (int i = 0; i < 6; i++) { if (htp_tensor_is_extended(octx->src[i])) { return HTP_STATUS_NO_SUPPORT; } @@ -2325,68 +2286,12 @@ int op_gated_delta_net(struct htp_ops_context * octx) { } const struct htp_gdn_kernel_params * kparams = (const struct htp_gdn_kernel_params *) octx->kernel_params; - struct htp_gdn_kernel_params kparams_local; - if (!kparams || kparams->S_v == 0) { - const uint32_t rq3 = n_seqs / q->ne[3]; - const uint32_t rk3 = n_seqs / k->ne[3]; - const uint32_t total_rows = H * n_seqs; - uint32_t n_threads = (total_rows < octx->n_threads) ? total_rows : octx->n_threads; - if (n_threads == 0) { - n_threads = 1; - } - - memset(&kparams_local, 0, sizeof(kparams_local)); - kparams_local.n_threads = n_threads; - kparams_local.S_v = S_v; - kparams_local.H = H; - kparams_local.n_tokens = n_tokens; - kparams_local.n_seqs = n_seqs; - kparams_local.K = K; - kparams_local.total_rows = total_rows; - kparams_local.rows_per_thread = (total_rows + n_threads - 1) / n_threads; - const bool can_use_hmx = (octx->ctx->hmx_enabled) && - (S_v % 64 == 0) && - (n_tokens >= HTP_GDN_MIN_TOKENS) && - (g->ne[0] == 1) && - (K == 1); - - struct htp_gdn_hmx_vtcm_layout hmx_layout_local; - struct htp_gdn_vtcm_layout hvx_layout_local; - uint32_t n_heads_batch = 1; - - if (can_use_hmx && htp_gdn_hmx_solve_layout(&hmx_layout_local, S_v, HTP_GDN_CHUNK_SIZE, total_rows, octx->ctx->vtcm_size, n_threads, true, &n_heads_batch)) { - kparams_local.kernel_type = HTP_GDN_KERNEL_HMX_CHUNKED; - kparams_local.pipeline = hmx_layout_local.pipeline ? 1 : 0; - kparams_local.chunk_size = HTP_GDN_CHUNK_SIZE; - kparams_local.n_chunks = (n_tokens + HTP_GDN_CHUNK_SIZE - 1) / HTP_GDN_CHUNK_SIZE; - kparams_local.n_heads_batch = (uint16_t) n_heads_batch; - kparams_local.vtcm_size = (uint32_t) hmx_layout_local.total_bytes; - kparams_local.state_aligned = (uint32_t) hmx_layout_local.state_f32_bytes; - kparams_local.vtcm_per_thread = (uint32_t) (hmx_layout_local.total_bytes / (n_threads > 0 ? n_threads : 1)); - } else { - htp_gdn_vtcm_layout_build(&hvx_layout_local, S_v, n_threads); - kparams_local.kernel_type = HTP_GDN_KERNEL_HVX_RECURRENT; - kparams_local.pipeline = 0; - kparams_local.n_heads_batch = 1; - kparams_local.state_aligned = (uint32_t) hvx_layout_local.state_aligned; - kparams_local.vtcm_per_thread = (uint32_t) hvx_layout_local.bytes_per_thread; - kparams_local.vtcm_size = (uint32_t) hvx_layout_local.total_bytes; - } - kparams_local.kda = (g->ne[0] == S_v) ? 1 : 0; - kparams_local.scale = 1.0f / sqrtf((float) S_v); - kparams_local.state_seq_stride = (uint32_t) (state->nb[3] / sizeof(float)); - kparams_local.state_size_per_snap = S_v * S_v * H * n_seqs; - - kparams_local.div_H = init_fastdiv_values(H); - kparams_local.div_q1 = init_fastdiv_values(q->ne[1]); - kparams_local.div_k1 = init_fastdiv_values(k->ne[1]); - kparams_local.div_rq3 = init_fastdiv_values(rq3); - kparams_local.div_rk3 = init_fastdiv_values(rk3); - kparams_local.div_n_threads = init_fastdiv_values(n_threads); - - kparams = &kparams_local; + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; } + const uint32_t S_v = kparams->S_v; + const uint32_t n_tokens = kparams->n_tokens; const uint32_t total_rows = kparams->total_rows; uint32_t row_start = 0; uint32_t nrows = total_rows; @@ -2416,16 +2321,16 @@ int op_gated_delta_net(struct htp_ops_context * octx) { return gated_delta_net_f32_hmx_chunked(octx, kparams, row_start, nrows); } - const uint32_t n_threads = (nrows < kparams->n_threads) ? nrows : kparams->n_threads; + const uint32_t n_threads = (nrows < octx->n_threads) ? nrows : octx->n_threads; struct htp_gdn_context gctx; gctx.octx = octx; gctx.kparams = kparams; gctx.row_start = row_start; gctx.nrows = nrows; - gctx.vtcm_base = octx->ctx->vtcm_base; htp_gdn_vtcm_layout_build(&gctx.layout, S_v, n_threads); + gctx.vtcm_base = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, gctx.layout.off_state); if (gctx.layout.total_bytes > octx->ctx->vtcm_size) { return HTP_STATUS_VTCM_TOO_SMALL; @@ -2433,10 +2338,10 @@ int op_gated_delta_net(struct htp_ops_context * octx) { FARF(HIGH, "gated-delta-net-f32: q(%ux%ux%ux%u) k(%ux%ux%ux%u) v(%ux%ux%ux%u) state(%ux%ux%ux%u) -> (%ux%ux%ux%u) : " "vtcm-size %zu n_threads %u\n", - q->ne[0], q->ne[1], q->ne[2], q->ne[3], - k->ne[0], k->ne[1], k->ne[2], k->ne[3], - v->ne[0], v->ne[1], v->ne[2], v->ne[3], - state->ne[0], state->ne[1], state->ne[2], state->ne[3], + octx->src[0]->ne[0], octx->src[0]->ne[1], octx->src[0]->ne[2], octx->src[0]->ne[3], + octx->src[1]->ne[0], octx->src[1]->ne[1], octx->src[1]->ne[2], octx->src[1]->ne[3], + octx->src[2]->ne[0], octx->src[2]->ne[1], octx->src[2]->ne[2], octx->src[2]->ne[3], + octx->src[5]->ne[0], octx->src[5]->ne[1], octx->src[5]->ne[2], octx->src[5]->ne[3], dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], gctx.layout.total_bytes, n_threads); diff --git a/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.h b/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.h index 32fb7d24bfdd..0d88185880fe 100644 --- a/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.h +++ b/ggml/src/ggml-hexagon/htp/gated-delta-net-ops.h @@ -37,13 +37,7 @@ struct htp_gdn_kernel_params { uint32_t K; uint32_t total_rows; - uint32_t row_start; - uint32_t nrows; - uint32_t rows_per_thread; - uint32_t kda; - uint32_t state_aligned; - uint32_t vtcm_per_thread; uint32_t vtcm_size; uint32_t state_seq_stride; uint32_t state_size_per_snap; @@ -55,7 +49,6 @@ struct htp_gdn_kernel_params { struct fastdiv_values div_k1; struct fastdiv_values div_rq3; struct fastdiv_values div_rk3; - struct fastdiv_values div_n_threads; }; #if defined(__cplusplus) @@ -67,18 +60,21 @@ _Static_assert(sizeof(struct htp_gdn_kernel_params) <= 128, "htp_gdn_kernel_para struct htp_gdn_vtcm_layout { size_t state_aligned; size_t bytes_per_thread; + size_t off_state; size_t total_bytes; }; static inline void htp_gdn_vtcm_layout_build( - struct htp_gdn_vtcm_layout * layout, + struct htp_gdn_vtcm_layout * L, uint32_t S_v, uint32_t n_threads ) { size_t state_bytes = (size_t) S_v * S_v * sizeof(float); - layout->state_aligned = hex_round_up(state_bytes, 128); - layout->bytes_per_thread = 2 * layout->state_aligned; - layout->total_bytes = layout->bytes_per_thread * n_threads; + L->state_aligned = hex_round_up(state_bytes, 128); + L->bytes_per_thread = 2 * L->state_aligned; + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_state, L->bytes_per_thread * n_threads); + L->total_bytes = off; } struct htp_gdn_hmx_vtcm_layout { @@ -208,7 +204,7 @@ static inline void htp_gdn_hmx_vtcm_layout_build( VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_g_f32[1], bh * dma_scalar_sz, pipeline); VTCM_LAYOUT_ALLOC(off, off_b_f32[0], bh * dma_scalar_sz); VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_b_f32[1], bh * dma_scalar_sz, pipeline); - const size_t raw_gb_sz = hex_round_up(bh * chunk_size * sizeof(float), 128); + const size_t raw_gb_sz = hex_round_up((bh + 1) * chunk_size * sizeof(float), 128); VTCM_LAYOUT_ALLOC(off, off_g_raw[0], raw_gb_sz); VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_g_raw[1], raw_gb_sz, pipeline); VTCM_LAYOUT_ALLOC(off, off_b_raw[0], raw_gb_sz); diff --git a/ggml/src/ggml-hexagon/htp/gather-rows.c b/ggml/src/ggml-hexagon/htp/gather-rows.c index 1db48e59cdee..1e88445f1cb0 100644 --- a/ggml/src/ggml-hexagon/htp/gather-rows.c +++ b/ggml/src/ggml-hexagon/htp/gather-rows.c @@ -206,14 +206,22 @@ static void gather_rows_thread_f32(unsigned int nth, unsigned int ith, void * da struct htp_thread_trace * tr = &task->octx->ctx->trace[ith]; - uint8_t * base = task->octx->ctx->vtcm_base + ith * kparams->slice; - HVX_Vector * tab = (HVX_Vector *) base; - HVX_Vector * inc = tab + kparams->vg; - HVX_Vector * cur = inc + kparams->vg; - uint8_t * region_base = (uint8_t *) (cur + kparams->vg); - - uint8_t * region[2] = { region_base, region_base + kparams->buf_stride }; - uint8_t * out[2] = { region[0] + kparams->out_off, region[1] + kparams->out_off }; + struct htp_gather_rows_vtcm_layout layout; + htp_gather_rows_vtcm_layout_build(&layout, kparams->vg, kparams->region_size, kparams->nr_max, kparams->ne, 4); + + uint8_t * base = VTCM_LAYOUT_PTR(uint8_t, task->octx->ctx->vtcm_base, (size_t) ith * kparams->slice); + HVX_Vector * tab = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_tab); + HVX_Vector * inc = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_inc); + HVX_Vector * cur = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_cur); + + uint8_t * region[2] = { + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_region0), + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_region1), + }; + uint8_t * out[2] = { + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_out0), + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_out1), + }; htp_trace_event_start(tr, HTP_TRACE_EVT_INIT, (uint16_t) r_beg); gather_rows_init_tables_f32(tab, inc, kparams, a, b); @@ -279,14 +287,22 @@ static void gather_rows_thread_f16(unsigned int nth, unsigned int ith, void * da struct htp_thread_trace * tr = &task->octx->ctx->trace[ith]; - uint8_t * base = task->octx->ctx->vtcm_base + ith * kparams->slice; - HVX_Vector * tab = (HVX_Vector *) base; - HVX_Vector * inc = tab + kparams->vg; - HVX_Vector * cur = inc + kparams->vg; - uint8_t * region_base = (uint8_t *) (cur + kparams->vg); - - uint8_t * region[2] = { region_base, region_base + kparams->buf_stride }; - uint8_t * out[2] = { region[0] + kparams->out_off, region[1] + kparams->out_off }; + struct htp_gather_rows_vtcm_layout layout; + htp_gather_rows_vtcm_layout_build(&layout, kparams->vg, kparams->region_size, kparams->nr_max, kparams->ne, 2); + + uint8_t * base = VTCM_LAYOUT_PTR(uint8_t, task->octx->ctx->vtcm_base, (size_t) ith * kparams->slice); + HVX_Vector * tab = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_tab); + HVX_Vector * inc = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_inc); + HVX_Vector * cur = VTCM_LAYOUT_PTR(HVX_Vector, base, layout.off_cur); + + uint8_t * region[2] = { + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_region0), + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_region1), + }; + uint8_t * out[2] = { + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_out0), + VTCM_LAYOUT_PTR(uint8_t, base, layout.off_out1), + }; htp_trace_event_start(tr, HTP_TRACE_EVT_INIT, (uint16_t) r_beg); gather_rows_init_tables_f16(tab, inc, kparams, a, b); diff --git a/ggml/src/ggml-hexagon/htp/gather-rows.h b/ggml/src/ggml-hexagon/htp/gather-rows.h index 3bbb1c6357dc..c08ef4d38fce 100644 --- a/ggml/src/ggml-hexagon/htp/gather-rows.h +++ b/ggml/src/ggml-hexagon/htp/gather-rows.h @@ -2,6 +2,7 @@ #define HTP_GATHER_ROWS_H #include "hex-common.h" +#include "htp-vtcm.h" #include #include @@ -19,8 +20,6 @@ struct htp_gather_rows_params { uint32_t v1; uint32_t span1; uint32_t region_size; - uint32_t out_off; - uint32_t buf_stride; uint32_t slice; uint32_t total_rows; uint32_t rows_per_thread; @@ -28,6 +27,40 @@ struct htp_gather_rows_params { uint8_t pad[3]; }; +struct htp_gather_rows_vtcm_layout { + size_t off_tab; + size_t off_inc; + size_t off_cur; + size_t off_region0; + size_t off_out0; + size_t off_region1; + size_t off_out1; + size_t total_per_thread; +}; + +static inline void htp_gather_rows_vtcm_layout_build( + struct htp_gather_rows_vtcm_layout * L, + uint32_t vg, + uint32_t region_size, + uint32_t nr_max, + uint32_t ne, + uint32_t elem_size) { + + const size_t vec_bytes = (size_t) vg * 128; + const size_t region_aligned = hex_round_up(region_size, 128); + const size_t out_aligned = hex_round_up(region_aligned + (size_t) nr_max * ne * elem_size, 128) - region_aligned; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_tab, vec_bytes); + VTCM_LAYOUT_ALLOC(off, off_inc, vec_bytes); + VTCM_LAYOUT_ALLOC(off, off_cur, vec_bytes); + VTCM_LAYOUT_ALLOC(off, off_region0, region_aligned); + VTCM_LAYOUT_ALLOC(off, off_out0, out_aligned); + VTCM_LAYOUT_ALLOC(off, off_region1, region_aligned); + VTCM_LAYOUT_ALLOC(off, off_out1, out_aligned); + L->total_per_thread = off; +} + static inline bool htp_gather_rows_solve_layout( struct htp_gather_rows_params * kparams, uint32_t na, uint32_t a_nb1, @@ -80,8 +113,6 @@ static inline bool htp_gather_rows_solve_layout( uint32_t v1 = 0; uint32_t span1 = 0; uint32_t region_size = 0; - uint32_t out_off = 0; - uint32_t buf_stride = 0; while (nr_max > 0) { v1 = hex_round_up((nr_max - 1) * a_nb1 + na * elem_size, 128); @@ -98,10 +129,10 @@ static inline bool htp_gather_rows_solve_layout( region_size = v1; } - out_off = hex_round_up(region_size, 128); - buf_stride = hex_round_up(out_off + nr_max * ne * elem_size, 128); + struct htp_gather_rows_vtcm_layout layout; + htp_gather_rows_vtcm_layout_build(&layout, vg, region_size, nr_max, ne, elem_size); - if ((elem_size != 2 || region_size <= 32768) && fixed + 2 * buf_stride <= slice) { + if ((elem_size != 2 || region_size <= 32768) && layout.total_per_thread <= slice) { break; } @@ -121,8 +152,6 @@ static inline bool htp_gather_rows_solve_layout( kparams->v1 = v1; kparams->span1 = span1; kparams->region_size = region_size; - kparams->out_off = out_off; - kparams->buf_stride = buf_stride; kparams->slice = slice; kparams->total_rows = total_rows; kparams->rows_per_thread = rows_per_thread; diff --git a/ggml/src/ggml-hexagon/htp/get-rows-ops.c b/ggml/src/ggml-hexagon/htp/get-rows-ops.c index 90f38fa56b51..39acdfda667a 100644 --- a/ggml/src/ggml-hexagon/htp/get-rows-ops.c +++ b/ggml/src/ggml-hexagon/htp/get-rows-ops.c @@ -17,21 +17,32 @@ #include "htp-tensor.h" #include "hvx-utils.h" #include "hvx-quant.h" -#include "matmul-ops.h" #include "get-rows-ops.h" #include "work-queue.h" +struct get_rows_context; + +typedef uint32_t (*get_rows_read_index_fn_t)(const void * src1, uint32_t idx, int idx_type); +typedef void (*get_rows_flat_compute_fn_t)(float * dst_spad, const void * src_spad, uint32_t cur_elems); +typedef void (*get_rows_tiled_compute_fn_t)(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row); + struct get_rows_context { struct htp_ops_context * octx; const struct htp_get_rows_kernel_params * kparams; struct htp_get_rows_vtcm_layout vtcm_layout; - uint8_t * vtcm_base; + uint8_t * vtcm_base; + const void * src1_data; + get_rows_read_index_fn_t read_index; + get_rows_flat_compute_fn_t compute_flat; + get_rows_tiled_compute_fn_t compute_tiled; uint32_t task_start; uint32_t tasks; uint32_t tasks_per_thread; uint32_t tile_size; uint32_t tile_stride; - bool index_i32; + uint32_t src0_row_size; + uint32_t dst_row_size; + int idx_type; }; #define get_rows_preamble \ @@ -64,229 +75,169 @@ struct get_rows_context { \ const uint32_t nr = ne10 * ne11 * ne12; -#define GET_ROWS_THREAD_ST_FN(IDX_TYPE) \ -static void get_rows_thread_st_##IDX_TYPE(unsigned int nth, unsigned int ith, void *data) { \ - struct get_rows_context * grctx = (struct get_rows_context *)data; \ - struct htp_ops_context * octx = grctx->octx; \ - const struct htp_get_rows_kernel_params * kparams = grctx->kparams; \ - get_rows_preamble; \ - const uint32_t dr = grctx->tasks_per_thread; \ - const uint32_t ir0 = grctx->task_start + dr * ith; \ - if (ir0 >= grctx->task_start + grctx->tasks) { \ - return; \ - } \ - const uint32_t ir1 = MIN(ir0 + dr, grctx->task_start + grctx->tasks); \ - const uint32_t row_size_bytes = htp_tensor_get_row_size(octx->src[0]->type, ne00); \ - dma_queue * dma_q = octx->ctx->dma[ith]; \ - for (uint32_t i = ir0; i < ir1; ++i) { \ - const uint32_t i12 = fastdiv(i, &kparams->div_ne10_ne11); \ - const uint32_t rem = i - i12 * ne11 * ne10; \ - const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); \ - const uint32_t i10 = rem - i11 * ne10; \ - const IDX_TYPE * src1_ptr = (const IDX_TYPE *)(uintptr_t)(octx->src[1]->data + i10*nb10 + i11*nb11 + i12*nb12); \ - const uint32_t i01 = (uint32_t)*src1_ptr; \ - assert(i01 < ne01); \ - const uint32_t q02 = fastdiv(i11, &kparams->div_ne02); \ - const uint32_t i02 = i11 - q02 * ne02; \ - const uint32_t q03 = fastdiv(i12, &kparams->div_ne03); \ - const uint32_t i03 = i12 - q03 * ne03; \ - const dma_addr_t src0_data = octx->src[0]->data + i01*nb01 + i02*nb02 + i03*nb03; \ - const dma_addr_t dst_data = octx->dst->data + i10*nb1 + i11*nb2 + i12*nb3; \ - while (!dma_queue_push(dma_q, dma_make_data(dst_data, src0_data), nb1, nb01, \ - row_size_bytes, 1)) { \ - dma_queue_pop(dma_q); \ - } \ - } \ - dma_queue_flush(dma_q); \ +static uint32_t get_rows_read_index_ddr( + const void * src1, + uint32_t idx, + int idx_type +) { + const uint32_t off = idx * ((idx_type == HTP_TYPE_I64) ? sizeof(int64_t) : sizeof(int32_t)); + return *(const uint32_t *) ((const uint8_t *) src1 + off); } -GET_ROWS_THREAD_ST_FN(int32_t) -GET_ROWS_THREAD_ST_FN(int64_t) - -#define GET_ROWS_THREAD_DT_FN(TYPE_NAME, SRC0_SIZE_EXPR, IDX_TYPE, COMPUTE_EXPR) \ -static void get_rows_thread_##TYPE_NAME##_##IDX_TYPE(unsigned int nth, unsigned int ith, void *data) { \ - struct get_rows_context * grctx = (struct get_rows_context *)data; \ - struct htp_ops_context * octx = grctx->octx; \ - const struct htp_get_rows_kernel_params * kparams = grctx->kparams; \ - get_rows_preamble; \ - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ - const uint32_t dr = grctx->tasks_per_thread; \ - const uint32_t ir0 = grctx->task_start + dr * ith; \ - if (ir0 >= grctx->task_start + grctx->tasks) { \ - return; \ - } \ - const uint32_t ir1 = MIN(ir0 + dr, grctx->task_start + grctx->tasks); \ - const uint32_t chunks_per_row = kparams->chunks_per_row; \ - const uint32_t chunk_size = kparams->chunk_size; \ - dma_queue * dma_q = octx->ctx->dma[ith]; \ - const struct htp_get_rows_vtcm_layout * vtcm_layout = &grctx->vtcm_layout; \ - uint8_t * vtcm_src0 = grctx->vtcm_base + vtcm_layout->off_src0 + ith * vtcm_layout->src0_bytes_per_thread; \ - uint8_t * vtcm_dst = grctx->vtcm_base + vtcm_layout->off_dst + ith * vtcm_layout->dst_bytes_per_thread; \ - for (uint32_t step = 0, spad_idx = 0; step < ir1 - ir0 && spad_idx < 2; ++step, spad_idx++) { \ - const uint32_t i = ir0 + step; \ - const uint32_t row_idx = fastdiv(i, &kparams->div_chunks_per_row); \ - const uint32_t chunk_idx = i - row_idx * chunks_per_row; \ - const uint32_t i12 = fastdiv(row_idx, &kparams->div_ne10_ne11); \ - const uint32_t rem = row_idx - i12 * ne11 * ne10; \ - const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); \ - const uint32_t i10 = rem - i11 * ne10; \ - const IDX_TYPE * src1_ptr = (const IDX_TYPE *)(uintptr_t)(octx->src[1]->data + i10*nb10 + i11*nb11 + i12*nb12); \ - const uint32_t i01 = (uint32_t)*src1_ptr; \ - assert(i01 < ne01); \ - const uint32_t q02 = fastdiv(i11, &kparams->div_ne02); \ - const uint32_t i02 = i11 - q02 * ne02; \ - const uint32_t q03 = fastdiv(i12, &kparams->div_ne03); \ - const uint32_t i03 = i12 - q03 * ne03; \ - const uint32_t offset = chunk_idx * chunk_size; \ - const uint32_t cur_elems = (offset < ne00) ? MIN(chunk_size, ne00 - offset) : 0; \ - const uint32_t cur_src0_bytes = SRC0_SIZE_EXPR(cur_elems); \ - const uint32_t cur_dst_bytes = cur_elems * sizeof(float); \ - const dma_addr_t src0_data = octx->src[0]->data + i01*nb01 + i02*nb02 + i03*nb03 + SRC0_SIZE_EXPR(offset); \ - dma_queue_push(dma_q, \ - dma_make_data(octx->dst->data, \ - vtcm_dst + spad_idx * vtcm_layout->dst_spad_half_size), \ - cur_dst_bytes, vtcm_layout->dst_spad_half_size, cur_dst_bytes, 0); \ - dma_queue_push(dma_q, \ - dma_make_data(vtcm_src0 + spad_idx * vtcm_layout->src0_spad_half_size, src0_data), \ - vtcm_layout->src0_spad_half_size, cur_src0_bytes, cur_src0_bytes, 1); \ - } \ - for (uint32_t step = 0; step < ir1 - ir0; ++step) { \ - const uint32_t i = ir0 + step; \ - void * dst_spad = (void *) dma_queue_pop(dma_q).src; \ - void * src_spad = (void *) dma_queue_pop(dma_q).dst; \ - const uint32_t row_idx = fastdiv(i, &kparams->div_chunks_per_row); \ - const uint32_t chunk_idx = i - row_idx * chunks_per_row; \ - const uint32_t i12 = fastdiv(row_idx, &kparams->div_ne10_ne11); \ - const uint32_t rem = row_idx - i12 * ne11 * ne10; \ - const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); \ - const uint32_t i10 = rem - i11 * ne10; \ - const uint32_t offset = chunk_idx * chunk_size; \ - const uint32_t cur_elems = (offset < ne00) ? MIN(chunk_size, ne00 - offset) : 0; \ - const uint32_t cur_dst_bytes = cur_elems * sizeof(float); \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, i); \ - COMPUTE_EXPR; \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, i); \ - const dma_addr_t dst_data = octx->dst->data + i10*nb1 + i11*nb2 + i12*nb3 + offset * sizeof(float); \ - dma_queue_push(dma_q, \ - dma_make_data(dst_data, dst_spad), \ - cur_dst_bytes, vtcm_layout->dst_spad_half_size, cur_dst_bytes, 1); \ - const uint32_t next_step = step + 2; \ - if (next_step < ir1 - ir0) { \ - const uint32_t pi = ir0 + next_step; \ - const uint32_t prow_idx = fastdiv(pi, &kparams->div_chunks_per_row); \ - const uint32_t pchunk_idx = pi - prow_idx * chunks_per_row; \ - const uint32_t pi12 = fastdiv(prow_idx, &kparams->div_ne10_ne11); \ - const uint32_t prem = prow_idx - pi12 * ne11 * ne10; \ - const uint32_t pi11 = fastdiv(prem, &kparams->div_ne10); \ - const uint32_t pi10 = prem - pi11 * ne10; \ - const IDX_TYPE * psrc1_ptr = (const IDX_TYPE *)(uintptr_t)(octx->src[1]->data + pi10*nb10 + pi11*nb11 + pi12*nb12); \ - const uint32_t pi01 = (uint32_t)*psrc1_ptr; \ - assert(pi01 < ne01); \ - const uint32_t pq02 = fastdiv(pi11, &kparams->div_ne02); \ - const uint32_t pi02 = pi11 - pq02 * ne02; \ - const uint32_t pq03 = fastdiv(pi12, &kparams->div_ne03); \ - const uint32_t pi03 = pi12 - pq03 * ne03; \ - const uint32_t poffset = pchunk_idx * chunk_size; \ - const uint32_t pcur_elems = (poffset < ne00) ? MIN(chunk_size, ne00 - poffset) : 0; \ - const uint32_t pcur_src0_bytes = SRC0_SIZE_EXPR(pcur_elems); \ - const dma_addr_t psrc0_data = \ - octx->src[0]->data + pi01*nb01 + pi02*nb02 + pi03*nb03 + SRC0_SIZE_EXPR(poffset); \ - dma_queue_push(dma_q, \ - dma_make_data(src_spad, psrc0_data), \ - vtcm_layout->src0_spad_half_size, pcur_src0_bytes, pcur_src0_bytes, 1); \ - } \ - } \ - dma_queue_flush(dma_q); \ +static __attribute__((noinline)) uint32_t get_rows_read_index_vtcm( + const void * src1, + uint32_t idx, + int idx_type +) { + const uint32_t off = idx * ((idx_type == HTP_TYPE_I64) ? sizeof(int64_t) : sizeof(int32_t)); + const HVX_Vector v = hvx_vmem((const uint8_t *) src1 + off); // off & ~127u in HW + // vextract is normally slow, but here it avoids an HVX->L2 store and L1D miss + return (uint32_t) Q6_R_vextract_VR(v, off); } -#define F16_BYTES(n) ((n) * sizeof(__fp16)) -#define Q8_0_BYTES(n) (((n) / 32) * sizeof(block_q8_0)) +static void get_rows_thread_sametype(unsigned int nth, unsigned int ith, void * data) { + struct get_rows_context * grctx = (struct get_rows_context *) data; + struct htp_ops_context * octx = grctx->octx; + const struct htp_get_rows_kernel_params * kparams = grctx->kparams; + get_rows_preamble; -static __attribute__((noinline)) void compute_get_rows_f16(float * dst_spad, const void * src_spad, uint32_t cur_elems) { - hvx_dequantize_row_f16_f32(dst_spad, src_spad, cur_elems); -} + const uint32_t dr = grctx->tasks_per_thread; + const uint32_t ir0 = grctx->task_start + dr * ith; + if (ir0 >= grctx->task_start + grctx->tasks) { + return; + } + const uint32_t ir1 = MIN(ir0 + dr, grctx->task_start + grctx->tasks); + const uint32_t row_size_bytes = grctx->src0_row_size; + dma_queue * dma_q = octx->ctx->dma[ith]; -static __attribute__((noinline)) void compute_get_rows_q8_0(float * dst_spad, const void * src_spad, uint32_t cur_elems) { - hvx_dequantize_row_q8_0_f32(dst_spad, src_spad, cur_elems); -} + for (uint32_t i = ir0; i < ir1; ++i) { + const uint32_t i12 = fastdiv(i, &kparams->div_ne10_ne11); + const uint32_t rem = i - i12 * ne11 * ne10; + const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); + const uint32_t i10 = rem - i11 * ne10; -GET_ROWS_THREAD_DT_FN(f16, F16_BYTES, int32_t, { compute_get_rows_f16((float *)dst_spad, src_spad, cur_elems); }) -GET_ROWS_THREAD_DT_FN(f16, F16_BYTES, int64_t, { compute_get_rows_f16((float *)dst_spad, src_spad, cur_elems); }) - -GET_ROWS_THREAD_DT_FN(q8_0, Q8_0_BYTES, int32_t, { compute_get_rows_q8_0((float *)dst_spad, src_spad, cur_elems); }) -GET_ROWS_THREAD_DT_FN(q8_0, Q8_0_BYTES, int64_t, { compute_get_rows_q8_0((float *)dst_spad, src_spad, cur_elems); }) - - -static __attribute__((noinline)) void compute_get_rows_tiled(float * dst, const uint8_t * tile, uint32_t row, bool q4, bool q4_k) { - const HVX_VectorPred first2 = Q6_Q_vsetq_R(2); - const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); - HVX_Vector vq = Q6_V_vzero(); - if (q4) { - const HVX_VectorPred first1 = Q6_Q_vsetq_R(1); - const HVX_VectorPred first3 = Q6_Q_vsetq_R(3); - for (int group = 3; group >= 0; --group) { - const HVX_Vector v = Q6_V_vror_VR(hvx_vmem(tile + group * VLEN), row); - // Four planes contribute bytes at 0, 32, 64 and 96 after rotation. - HVX_Vector packed = Q6_V_vmux_QVV(first1, v, Q6_V_vror_VR(v, 31)); - packed = Q6_V_vmux_QVV(first2, packed, Q6_V_vror_VR(v, 62)); - packed = Q6_V_vmux_QVV(first3, packed, Q6_V_vror_VR(v, 93)); - vq = Q6_V_vmux_QVV(first4, packed, Q6_V_vror_VR(vq, VLEN - 4)); - } - const HVX_Vector lo = Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)); - const HVX_Vector hi = Q6_Vub_vlsr_VubR(vq, 4); - vq = Q6_V_lo_W(Q6_W_vshuff_VVR(hi, lo, -1)); - if (!q4_k) { - vq = Q6_Vb_vsub_VbVb(vq, Q6_Vb_vsplat_R(8)); - } - } else { - for (int group = 7; group >= 0; --group) { - const HVX_Vector v = Q6_V_vror_VR(hvx_vmem(tile + group * VLEN), 2 * row); - // Two planes contribute halfwords at 0 and 64 after rotation. - const HVX_Vector packed = Q6_V_vmux_QVV(first2, v, Q6_V_vror_VR(v, 62)); - vq = Q6_V_vmux_QVV(first4, packed, Q6_V_vror_VR(vq, VLEN - 4)); + const uint32_t i01 = grctx->read_index(grctx->src1_data, i, grctx->idx_type); + assert(i01 < ne01); + + const uint32_t q02 = fastdiv(i11, &kparams->div_ne02); + const uint32_t i02 = i11 - q02 * ne02; + const uint32_t q03 = fastdiv(i12, &kparams->div_ne03); + const uint32_t i03 = i12 - q03 * ne03; + + const dma_addr_t src0_data = octx->src[0]->data + i01*nb01 + i02*nb02 + i03*nb03; + const dma_addr_t dst_data = octx->dst->data + i10*nb1 + i11*nb2 + i12*nb3; + + while (!dma_queue_push(dma_q, dma_make_data(dst_data, src0_data), nb1, nb01, row_size_bytes, 1)) { + dma_queue_pop(dma_q); } } - const HVX_Vector scales = hvx_vmem(tile + (q4 ? 512 : 1024)); - const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, (q4_k ? 4 : 2) * row)); - const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); - const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); - const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); - HVX_Vector values = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); - if (q4_k) { - const HVX_Vector offset_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 4 * row + 2)); - const HVX_Vector offset = Q6_V_lo_W(hvx_vec_f16_to_f32(offset_hf)); - values = hvx_vec_add_f32_f32(values, offset); + dma_queue_flush(dma_q); +} + + + +struct get_rows_flat_task { + dma_addr_t src0_data; + dma_addr_t dst_data; +}; + +static inline struct get_rows_flat_task get_rows_flat_calc_task( + const struct htp_ops_context * octx, + const struct get_rows_context * grctx, + uint32_t i, + bool need_src0 +) { + const struct htp_get_rows_kernel_params * kparams = grctx->kparams; + get_rows_preamble; + + const uint32_t i12 = fastdiv(i, &kparams->div_ne10_ne11); + const uint32_t rem = i - i12 * ne11 * ne10; + const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); + const uint32_t i10 = rem - i11 * ne10; + + struct get_rows_flat_task task; + task.src0_data = 0; + task.dst_data = octx->dst->data + i10*nb1 + i11*nb2 + i12*nb3; + + if (need_src0) { + const uint32_t i01 = grctx->read_index(grctx->src1_data, i, grctx->idx_type); + assert(i01 < ne01); + + const uint32_t q02 = fastdiv(i11, &kparams->div_ne02); + const uint32_t i02 = i11 - q02 * ne02; + const uint32_t q03 = fastdiv(i12, &kparams->div_ne03); + const uint32_t i03 = i12 - q03 * ne03; + + task.src0_data = octx->src[0]->data + i01*nb01 + i02*nb02 + i03*nb03; } - *(HVX_Vector *) dst = values; + + return task; } -static __attribute__((noinline)) void compute_get_rows_q6_k(float * dst, const uint8_t * tile, uint32_t row) { - const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); - const HVX_VectorPred first16 = Q6_Q_vsetq_R(16 * sizeof(float)); - const HVX_Vector mask_0f = Q6_Vb_vsplat_R(0x0F); - const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); - HVX_Vector vq = Q6_V_vzero(); - - for (int group = 7; group >= 0; --group) { - const HVX_Vector lo_plane = Q6_V_vror_VR(hvx_vmem(tile + (group >> 1) * VLEN), 4 * row); - const HVX_Vector hi_plane = Q6_V_vror_VR(hvx_vmem(tile + 512 + (group >> 2) * VLEN), 4 * row); - const HVX_Vector lo = (group & 1) ? Q6_Vub_vlsr_VubR(lo_plane, 4) : Q6_V_vand_VV(lo_plane, mask_0f); - const HVX_Vector hi = Q6_Vub_vlsr_VubR(hi_plane, 2 * (group & 3)); - const HVX_Vector packed = Q6_V_vor_VV(lo, Q6_Vw_vasl_VwR(Q6_V_vand_VV(hi, mask_03), 4)); - vq = Q6_V_vmux_QVV(first4, packed, Q6_V_vror_VR(vq, VLEN - 4)); +static void get_rows_thread_flat(unsigned int nth, unsigned int ith, void * data) { + struct get_rows_context * grctx = (struct get_rows_context *) data; + struct htp_ops_context * octx = grctx->octx; + get_rows_preamble; + + const uint32_t dr = grctx->tasks_per_thread; + const uint32_t ir0 = grctx->task_start + dr * ith; + if (ir0 >= grctx->task_start + grctx->tasks) { + return; + } + const uint32_t ir1 = MIN(ir0 + dr, grctx->task_start + grctx->tasks); + + dma_queue * dma_q = octx->ctx->dma[ith]; + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + const struct htp_get_rows_vtcm_layout * vtcm_layout = &grctx->vtcm_layout; + uint8_t * vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, grctx->vtcm_base, vtcm_layout->off_src0) + ith * vtcm_layout->src0_bytes_per_thread; + uint8_t * vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, grctx->vtcm_base, vtcm_layout->off_dst) + ith * vtcm_layout->dst_bytes_per_thread; + const uint32_t src0_bytes = grctx->src0_row_size; + const uint32_t dst_bytes = grctx->dst_row_size; + get_rows_flat_compute_fn_t compute = grctx->compute_flat; + + for (uint32_t step = 0, spad_idx = 0; step < ir1 - ir0 && spad_idx < 2; ++step, spad_idx++) { + const uint32_t i = ir0 + step; + struct get_rows_flat_task task = get_rows_flat_calc_task(octx, grctx, i, true); + + dma_queue_push(dma_q, + dma_make_data(octx->dst->data, + vtcm_dst + spad_idx * vtcm_layout->dst_spad_half_size), + dst_bytes, vtcm_layout->dst_spad_half_size, dst_bytes, 0); + dma_queue_push(dma_q, + dma_make_data(vtcm_src0 + spad_idx * vtcm_layout->src0_spad_half_size, task.src0_data), + vtcm_layout->src0_spad_half_size, src0_bytes, src0_bytes, 1); + } + + for (uint32_t step = 0; step < ir1 - ir0; ++step) { + const uint32_t i = ir0 + step; + void * dst_spad = (void *) dma_queue_pop(dma_q).src; + void * src_spad = (void *) dma_queue_pop(dma_q).dst; + + struct get_rows_flat_task task = get_rows_flat_calc_task(octx, grctx, i, false); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); + compute((float *) dst_spad, src_spad, ne00); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); + + dma_queue_push(dma_q, + dma_make_data(task.dst_data, dst_spad), + dst_bytes, vtcm_layout->dst_spad_half_size, dst_bytes, 1); + + const uint32_t next_step = step + 2; + if (next_step < ir1 - ir0) { + const uint32_t pi = ir0 + next_step; + struct get_rows_flat_task next_task = get_rows_flat_calc_task(octx, grctx, pi, true); + dma_queue_push(dma_q, + dma_make_data(src_spad, next_task.src0_data), + vtcm_layout->src0_spad_half_size, src0_bytes, src0_bytes, 1); + } } - const HVX_Vector scales = hvx_vmem(tile + 768); - const HVX_Vector scale_lo_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); - const HVX_Vector scale_hi_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 64 + 2 * row)); - const HVX_Vector scale_lo = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_lo_hf)); - const HVX_Vector scale_hi = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hi_hf)); - const HVX_Vector scale = Q6_V_vmux_QVV(first16, scale_lo, scale_hi); - const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(Q6_Vb_vsub_VbVb(vq, Q6_Vb_vsplat_R(32))); - const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); - *(HVX_Vector *) dst = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + dma_queue_flush(dma_q); } + + struct get_rows_tiled_task { dma_addr_t tile_src_base; dma_addr_t dst_data; @@ -307,16 +258,15 @@ static inline struct get_rows_tiled_task get_rows_tiled_calc_task( const uint32_t rem = i - i12 * ne11 * ne10; const uint32_t i11 = fastdiv(rem, &kparams->div_ne10); const uint32_t i10 = rem - i11 * ne10; - const dma_addr_t src1_data = octx->src[1]->data + i10*nb10 + i11*nb11 + i12*nb12; - const uint32_t i01 = grctx->index_i32 ? *(const int32_t *)(uintptr_t) src1_data : (uint32_t) *(const int64_t *)(uintptr_t) src1_data; + const uint32_t i01 = grctx->read_index(grctx->src1_data, i, grctx->idx_type); assert(i01 < ne01); const uint32_t q02 = fastdiv(i11, &kparams->div_ne02); const uint32_t i02 = i11 - q02 * ne02; const uint32_t q03 = fastdiv(i12, &kparams->div_ne03); const uint32_t i03 = i12 - q03 * ne03; - const uint32_t column_tile = i01 / HTP_MM_HMX_TILE_N_ROWS; - const uint32_t row = i01 % HTP_MM_HMX_TILE_N_ROWS; + const uint32_t column_tile = i01 / HTP_TENSOR_TILE_N_ROWS; + const uint32_t row = i01 % HTP_TENSOR_TILE_N_ROWS; const dma_addr_t matrix = octx->src[0]->data + i02*nb02 + i03*nb03; struct get_rows_tiled_task task; @@ -329,7 +279,6 @@ static inline struct get_rows_tiled_task get_rows_tiled_calc_task( static void get_rows_thread_tiled(unsigned int nth, unsigned int ith, void * data) { struct get_rows_context * grctx = (struct get_rows_context *) data; struct htp_ops_context * octx = grctx->octx; - const struct htp_get_rows_kernel_params * kparams = grctx->kparams; get_rows_preamble; const uint32_t dr = grctx->tasks_per_thread; @@ -339,19 +288,17 @@ static void get_rows_thread_tiled(unsigned int nth, unsigned int ith, void * dat } const uint32_t ir1 = MIN(ir0 + dr, grctx->task_start + grctx->tasks); - const uint32_t n_k_tiles = ne00 / HTP_MM_HMX_TILE_N_COLS; + const uint32_t n_k_tiles = ne00 / htp_tensor_get_tile_k(octx->src[0]->type); const struct htp_get_rows_vtcm_layout * vtcm_layout = &grctx->vtcm_layout; - uint8_t * src_spad_base = grctx->vtcm_base + vtcm_layout->off_src0 + ith * vtcm_layout->src0_bytes_per_thread; - uint8_t * dst_spad_base = grctx->vtcm_base + vtcm_layout->off_dst + ith * vtcm_layout->dst_bytes_per_thread; + uint8_t * src_spad_base = VTCM_LAYOUT_PTR(uint8_t, grctx->vtcm_base, vtcm_layout->off_src0) + ith * vtcm_layout->src0_bytes_per_thread; + uint8_t * dst_spad_base = VTCM_LAYOUT_PTR(uint8_t, grctx->vtcm_base, vtcm_layout->off_dst) + ith * vtcm_layout->dst_bytes_per_thread; dma_queue * dma_q = octx->ctx->dma[ith]; struct htp_thread_trace * tr = &octx->ctx->trace[ith]; const uint32_t tile_size = grctx->tile_size; const uint32_t tile_stride = grctx->tile_stride; - const uint32_t dst_bytes = ne00 * sizeof(float); - const bool is_q4 = octx->src[0]->type == HTP_TYPE_Q4_0 || octx->src[0]->type == HTP_TYPE_Q4_K; - const bool is_q4_k = octx->src[0]->type == HTP_TYPE_Q4_K; - const bool is_q6_k = octx->src[0]->type == HTP_TYPE_Q6_K; + const uint32_t dst_bytes = grctx->dst_row_size; + get_rows_tiled_compute_fn_t compute_tiled = grctx->compute_tiled; for (uint32_t step = 0, spad_idx = 0; step < ir1 - ir0 && spad_idx < 2; ++step, ++spad_idx) { const uint32_t i = ir0 + step; @@ -376,15 +323,7 @@ static void get_rows_thread_tiled(unsigned int nth, unsigned int ith, void * dat struct get_rows_tiled_task task = get_rows_tiled_calc_task(octx, grctx, i, n_k_tiles, tile_size); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); - for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { - const uint8_t * tile = src_spad + k_tile * tile_stride; - float * dst_block = dst_spad + k_tile * HTP_MM_HMX_TILE_N_COLS; - if (is_q6_k) { - compute_get_rows_q6_k(dst_block, tile, task.row); - } else { - compute_get_rows_tiled(dst_block, tile, task.row, is_q4, is_q4_k); - } - } + compute_tiled(dst_spad, src_spad, n_k_tiles, tile_stride, task.row); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i); // Real writeback of dst_spad @@ -405,16 +344,40 @@ static void get_rows_thread_tiled(unsigned int nth, unsigned int ith, void * dat dma_queue_flush(dma_q); } +static __attribute__((noinline)) void get_rows_dma_src1( + struct htp_ops_context * octx, + uint8_t * vtcm_src1, + uint32_t elem_size +) { + const uint32_t ne10 = octx->src[1]->ne[0]; + const uint32_t ne11 = octx->src[1]->ne[1]; + const uint32_t ne12 = octx->src[1]->ne[2]; + const uint32_t ne13 = octx->src[1]->ne[3]; + const uint32_t nb11 = octx->src[1]->nb[1]; + const uint32_t nb12 = octx->src[1]->nb[2]; + const uint32_t nb13 = octx->src[1]->nb[3]; + + dma_queue * dma_q = octx->ctx->dma[0]; + uint8_t * cur_dst = vtcm_src1; + for (uint32_t i13 = 0; i13 < ne13; ++i13) { + for (uint32_t i12 = 0; i12 < ne12; ++i12) { + const dma_addr_t src_plane = octx->src[1]->data + i12 * nb12 + i13 * nb13; + while (!dma_queue_push(dma_q, dma_make_data(cur_dst, src_plane), + ne10 * elem_size, nb11, ne10 * elem_size, ne11)) { + dma_queue_pop(dma_q); + } + cur_dst += ne10 * ne11 * elem_size; + } + } + dma_queue_flush(dma_q); +} + int op_get_rows(struct htp_ops_context * octx) { const struct htp_get_rows_kernel_params * kparams = (const struct htp_get_rows_kernel_params *) octx->kernel_params; - if (octx->src[0]->type != HTP_TYPE_F32 && - octx->src[0]->type != HTP_TYPE_F16 && - octx->src[0]->type != HTP_TYPE_Q4_0 && - octx->src[0]->type != HTP_TYPE_Q4_K && - octx->src[0]->type != HTP_TYPE_Q6_K && - octx->src[0]->type != HTP_TYPE_Q8_0 && - octx->src[0]->type != HTP_TYPE_I32) { + const uint32_t ne00 = octx->src[0]->ne[0]; + const uint32_t src0_row_size = htp_tensor_get_row_size(octx->src[0]->type, ne00); + if (src0_row_size == 0) { return HTP_STATUS_NO_SUPPORT; } @@ -432,20 +395,16 @@ int op_get_rows(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } - if (htp_tensor_is_extended(octx->src[1])) { - return HTP_STATUS_NO_SUPPORT; - } - const struct htp_tensor * dst = octx->dst; const uint32_t total_tasks = kparams->total_tasks; - const size_t dst_row_size = htp_tensor_get_row_size(dst->type, dst->ne[0]); + const uint32_t dst_row_size = (kparams->kernel_type == HTP_GET_ROWS_KERNEL_SAMETYPE) ? src0_row_size : ne00 * sizeof(float); uint32_t task_start = 0; uint32_t tasks = total_tasks; if (octx->ctx->mdev.count > 1) { uint32_t tasks_per_chunk = 1; - htp_tensor_mdev_rows_per_chunk(dst, dst_row_size / dst->ne[0], (uint32_t) dst_row_size, &tasks_per_chunk); + htp_tensor_mdev_rows_per_chunk(dst, (uint32_t) dst->nb[0], dst_row_size, &tasks_per_chunk); const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_tasks, tasks_per_chunk, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); task_start = range.start; tasks = range.count; @@ -455,7 +414,7 @@ int op_get_rows(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - if (!htp_ops_context_set_n_threads(octx, (uint32_t) kparams->n_threads)) { + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { return HTP_STATUS_INVAL_PARAMS; } @@ -465,15 +424,18 @@ int op_get_rows(struct htp_ops_context * octx) { grctx.octx = octx; grctx.kparams = kparams; grctx.vtcm_base = (uint8_t *)octx->ctx->vtcm_base; + grctx.compute_flat = NULL; + grctx.compute_tiled = NULL; grctx.task_start = task_start; grctx.tasks = tasks; - grctx.tasks_per_thread = octx->ctx->mdev.count == 1 ? kparams->tasks_per_thread : fastdiv(tasks + n_threads - 1, &octx->n_threads_div); - grctx.tile_size = htp_mm_get_weight_tile_size(octx->src[0]->type); - grctx.tile_stride = (grctx.tile_size + 127) & ~127; - grctx.index_i32 = octx->src[1]->type == HTP_TYPE_I32; + grctx.tasks_per_thread = fastdiv(tasks + n_threads - 1, &octx->n_threads_div); + grctx.tile_size = 0; + grctx.tile_stride = 0; + grctx.src0_row_size = src0_row_size; + grctx.dst_row_size = dst_row_size; + grctx.idx_type = octx->src[1]->type; - const uint32_t ne00 = octx->src[0]->ne[0]; - htp_get_rows_vtcm_layout_build(&grctx.vtcm_layout, kparams->kernel_type, octx->src[0]->type, ne00, n_threads); + htp_get_rows_vtcm_layout_build(&grctx.vtcm_layout, kparams->kernel_type, octx->src[0]->type, ne00, total_tasks, grctx.idx_type, n_threads); if (grctx.vtcm_layout.total_bytes > octx->ctx->vtcm_size) { FARF(ERROR, "get-rows: VTCM reservation %zu is too small, needed %zu\n", @@ -481,27 +443,60 @@ int op_get_rows(struct htp_ops_context * octx) { return HTP_STATUS_INVAL_PARAMS; } - const bool is_i32 = (octx->src[1]->type == HTP_TYPE_I32); - work_queue_func_t q_func = NULL; switch (kparams->kernel_type) { case HTP_GET_ROWS_KERNEL_SAMETYPE: - q_func = (work_queue_func_t)(is_i32 ? get_rows_thread_st_int32_t : get_rows_thread_st_int64_t); + q_func = get_rows_thread_sametype; break; case HTP_GET_ROWS_KERNEL_TILED: + switch (octx->src[0]->type) { + case HTP_TYPE_F16: grctx.compute_tiled = hvx_dequantize_row_tiled_f16_f32; break; + case HTP_TYPE_Q1_0: grctx.compute_tiled = hvx_dequantize_row_tiled_q1_0_f32; break; + case HTP_TYPE_Q2_0: grctx.compute_tiled = hvx_dequantize_row_tiled_q2_0_f32; break; + case HTP_TYPE_Q8_0: grctx.compute_tiled = hvx_dequantize_row_tiled_q8_0_f32; break; + case HTP_TYPE_Q4_0: grctx.compute_tiled = hvx_dequantize_row_tiled_q4_0_f32; break; + case HTP_TYPE_Q4_K: grctx.compute_tiled = hvx_dequantize_row_tiled_q4_k_f32; break; + case HTP_TYPE_Q5_K: grctx.compute_tiled = hvx_dequantize_row_tiled_q5_k_f32; break; + case HTP_TYPE_Q6_K: grctx.compute_tiled = hvx_dequantize_row_tiled_q6_k_f32; break; + default: return HTP_STATUS_NO_SUPPORT; + } + grctx.tile_size = htp_tensor_get_tile_size(octx->src[0]->type); + grctx.tile_stride = htp_tensor_get_tile_padded_size(octx->src[0]->type); q_func = get_rows_thread_tiled; break; case HTP_GET_ROWS_KERNEL_FLAT: switch (octx->src[0]->type) { - case HTP_TYPE_F16: q_func = (work_queue_func_t)(is_i32 ? get_rows_thread_f16_int32_t : get_rows_thread_f16_int64_t); break; - case HTP_TYPE_Q8_0: q_func = (work_queue_func_t)(is_i32 ? get_rows_thread_q8_0_int32_t : get_rows_thread_q8_0_int64_t); break; + case HTP_TYPE_F16: grctx.compute_flat = hvx_dequantize_row_flat_f16_f32; break; + case HTP_TYPE_BF16: grctx.compute_flat = hvx_dequantize_row_flat_bf16_f32; break; + case HTP_TYPE_Q1_0: grctx.compute_flat = hvx_dequantize_row_flat_q1_0_f32; break; + case HTP_TYPE_Q2_0: grctx.compute_flat = hvx_dequantize_row_flat_q2_0_f32; break; + case HTP_TYPE_Q8_0: grctx.compute_flat = hvx_dequantize_row_flat_q8_0_f32; break; + case HTP_TYPE_Q4_0: grctx.compute_flat = hvx_dequantize_row_flat_q4_0_f32; break; + case HTP_TYPE_Q4_K: grctx.compute_flat = hvx_dequantize_row_flat_q4_k_f32; break; + case HTP_TYPE_Q5_K: grctx.compute_flat = hvx_dequantize_row_flat_q5_k_f32; break; + case HTP_TYPE_Q6_K: grctx.compute_flat = hvx_dequantize_row_flat_q6_k_f32; break; default: return HTP_STATUS_NO_SUPPORT; } + q_func = get_rows_thread_flat; break; default: return HTP_STATUS_NO_SUPPORT; } + const uint32_t elem_size = (grctx.idx_type == HTP_TYPE_I64) ? sizeof(int64_t) : sizeof(int32_t); + const size_t src1_bytes = (size_t) total_tasks * elem_size; + + if (!htp_tensor_is_extended(octx->src[1]) && src1_bytes <= 128 && + htp_tensor_is_contiguous(octx->src[1], elem_size)) { + grctx.src1_data = (const void *) (uintptr_t) octx->src[1]->data; + grctx.read_index = get_rows_read_index_ddr; + } else { + uint8_t * vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, grctx.vtcm_base, grctx.vtcm_layout.off_src1); + get_rows_dma_src1(octx, vtcm_src1, elem_size); + grctx.src1_data = vtcm_src1; + grctx.read_index = get_rows_read_index_vtcm; + } + FARF(HIGH, "get-rows: (%ux%ux%ux%u) x (%ux%ux%ux%u) -> (%ux%ux%ux%u) : src0-vtcm-size %zu dst-vtcm-size %zu kernel-type %d n-threads %d\n", octx->src[0]->ne[0], octx->src[0]->ne[1], octx->src[0]->ne[2], octx->src[0]->ne[3], octx->src[1]->ne[0], octx->src[1]->ne[1], octx->src[1]->ne[2], octx->src[1]->ne[3], diff --git a/ggml/src/ggml-hexagon/htp/get-rows-ops.h b/ggml/src/ggml-hexagon/htp/get-rows-ops.h index 69fa544649c3..4634be2e2ed2 100644 --- a/ggml/src/ggml-hexagon/htp/get-rows-ops.h +++ b/ggml/src/ggml-hexagon/htp/get-rows-ops.h @@ -5,7 +5,8 @@ #include #include "hex-fastdiv.h" -#include "matmul-ops.h" +#include "htp-tensor.h" +#include "htp-vtcm.h" enum htp_get_rows_kernel_type { HTP_GET_ROWS_KERNEL_SAMETYPE = 0, @@ -14,24 +15,22 @@ enum htp_get_rows_kernel_type { }; struct htp_get_rows_kernel_params { - int32_t n_threads; - int32_t kernel_type; - int32_t chunks_per_row; - int32_t chunk_size; - int32_t total_tasks; - int32_t tasks_per_thread; - int32_t vtcm_size; + uint8_t kernel_type; + uint32_t n_threads; + uint32_t total_tasks; + uint32_t vtcm_size; // Fastdiv helpers struct fastdiv_values div_ne10; struct fastdiv_values div_ne10_ne11; - struct fastdiv_values div_chunks_per_row; struct fastdiv_values div_ne02; struct fastdiv_values div_ne03; }; struct htp_get_rows_vtcm_layout { size_t total_bytes; + size_t off_src1; + size_t src1_bytes; size_t off_src0; size_t off_dst; @@ -43,57 +42,44 @@ struct htp_get_rows_vtcm_layout { }; static inline void htp_get_rows_vtcm_layout_build( - struct htp_get_rows_vtcm_layout * vtcm_layout, + struct htp_get_rows_vtcm_layout * L, int kernel_type, int type, uint32_t ne00, + uint32_t total_tasks, + int idx_type, uint32_t n_threads) { - if (kernel_type == HTP_GET_ROWS_KERNEL_SAMETYPE) { - memset(vtcm_layout, 0, sizeof(*vtcm_layout)); - return; + memset(L, 0, sizeof(*L)); + + const size_t elem_size = (idx_type == HTP_TYPE_I64) ? sizeof(int64_t) : sizeof(int32_t); + const size_t src1_raw_bytes = total_tasks * elem_size; + const size_t src1_bytes = ((src1_raw_bytes + 127) & ~127) + 128; + + L->src1_bytes = src1_bytes; + const size_t src1_alloc_bytes = (src1_bytes + 255) & ~255; + + if (kernel_type != HTP_GET_ROWS_KERNEL_SAMETYPE) { + size_t src0_row_size = 0; + if (kernel_type == HTP_GET_ROWS_KERNEL_TILED) { + const size_t tile_stride = htp_tensor_get_tile_padded_size(type); + const uint32_t n_k_tiles = ne00 / htp_tensor_get_tile_k(type); + src0_row_size = n_k_tiles > 0 ? (n_k_tiles * tile_stride) : tile_stride; + } else { + src0_row_size = htp_tensor_get_row_size(type, ne00); + } + + L->src0_spad_half_size = (src0_row_size + 255) & ~255; + L->dst_spad_half_size = (ne00 * sizeof(float) + 255) & ~255; + L->src0_bytes_per_thread = 2 * L->src0_spad_half_size; + L->dst_bytes_per_thread = 2 * L->dst_spad_half_size; } - if (kernel_type == HTP_GET_ROWS_KERNEL_TILED) { - const size_t tile_size = htp_mm_get_weight_tile_size(type); - const size_t tile_stride = (tile_size + 127) & ~127; - const uint32_t n_k_tiles = ne00 / HTP_MM_HMX_TILE_N_COLS; - const size_t row_tiles_size = n_k_tiles > 0 ? (n_k_tiles * tile_stride) : tile_stride; - vtcm_layout->src0_spad_half_size = (row_tiles_size + 255) & ~255; - vtcm_layout->dst_spad_half_size = (ne00 * sizeof(float) + 255) & ~255; - vtcm_layout->src0_bytes_per_thread = 2 * vtcm_layout->src0_spad_half_size; - vtcm_layout->dst_bytes_per_thread = 2 * vtcm_layout->dst_spad_half_size; - vtcm_layout->off_src0 = 0; - vtcm_layout->off_dst = vtcm_layout->src0_bytes_per_thread * n_threads; - vtcm_layout->total_bytes = vtcm_layout->off_dst + vtcm_layout->dst_bytes_per_thread * n_threads; - return; - } - - uint32_t src0_row_size = 0; - switch (type) { - case HTP_TYPE_F16: - src0_row_size = ne00 * 2; - break; - case HTP_TYPE_Q8_0: - src0_row_size = (ne00 / 32) * 34; - break; - default: - src0_row_size = 0; - break; - } - - size_t src0_row_size_aligned = (src0_row_size + 255) & ~255; - size_t dst_row_size_aligned = (ne00 * sizeof(float) + 255) & ~255; - - vtcm_layout->src0_spad_half_size = src0_row_size_aligned; - vtcm_layout->dst_spad_half_size = dst_row_size_aligned; - - vtcm_layout->src0_bytes_per_thread = src0_row_size_aligned * 2; - vtcm_layout->dst_bytes_per_thread = dst_row_size_aligned * 2; - - vtcm_layout->off_src0 = 0; - vtcm_layout->off_dst = vtcm_layout->off_src0 + vtcm_layout->src0_bytes_per_thread * n_threads; - vtcm_layout->total_bytes = vtcm_layout->off_dst + vtcm_layout->dst_bytes_per_thread * n_threads; + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src1, src1_alloc_bytes); + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + L->total_bytes = off; } #if defined(__cplusplus) diff --git a/ggml/src/ggml-hexagon/htp/act-ops.c b/ggml/src/ggml-hexagon/htp/glu-ops.c similarity index 69% rename from ggml/src/ggml-hexagon/htp/act-ops.c rename to ggml/src/ggml-hexagon/htp/glu-ops.c index 59a0575c4b2a..b4edddf3fe0a 100644 --- a/ggml/src/ggml-hexagon/htp/act-ops.c +++ b/ggml/src/ggml-hexagon/htp/glu-ops.c @@ -17,11 +17,12 @@ #include "hex-common.h" #include "htp-tensor.h" #include "htp-vtcm.h" +#include "glu-ops.h" -#define htp_act_preamble \ - const struct htp_tensor * src0 = actx->octx->src[0]; \ - const struct htp_tensor * src1 = actx->octx->src[1]; \ - const struct htp_tensor * dst = actx->octx->dst; \ +#define htp_glu_preamble \ + const struct htp_tensor * src0 = gctx->octx->src[0]; \ + const struct htp_tensor * src1 = gctx->octx->src[1]; \ + const struct htp_tensor * dst = gctx->octx->dst; \ \ const uint32_t ne00 = src0->ne[0]; \ const uint32_t ne01 = src0->ne[1]; \ @@ -53,21 +54,21 @@ const uint32_t nb2 = dst->nb[2]; \ const uint32_t nb3 = dst->nb[3]; -struct htp_act_context; +struct htp_glu_context; typedef void (*glu_compute_f32_fn_t)(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx); + const struct htp_glu_context * gctx); typedef void (*glu_compute_f16_fn_t)(const _Float16 * restrict src0, const _Float16 * restrict src1, _Float16 * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx); + const struct htp_glu_context * gctx); -struct htp_act_context { +struct htp_glu_context { struct htp_ops_context * octx; void * compute; @@ -108,53 +109,18 @@ struct htp_act_context { size_t vtcm_dst_size_per_thread; }; -struct htp_act_vtcm_layout { - size_t total_bytes; - size_t off_src0; - size_t off_src1; - size_t off_dst; - - size_t src0_bytes_per_thread; - size_t src1_bytes_per_thread; - size_t dst_bytes_per_thread; - - uint32_t vtcm_row_per_thread; -}; - -static inline void htp_act_vtcm_layout_build(struct htp_act_vtcm_layout * L, - size_t src0_row_size_aligned, - size_t src1_row_size_aligned, - size_t dst_row_size_aligned, - uint32_t n_threads, - size_t vtcm_size) { - const size_t spad_size_per_row = src0_row_size_aligned + src1_row_size_aligned + dst_row_size_aligned; - const uint32_t vtcm_row_per_thread = (uint32_t) (vtcm_size / (n_threads * spad_size_per_row)); - - L->vtcm_row_per_thread = vtcm_row_per_thread; - - L->src0_bytes_per_thread = src0_row_size_aligned * vtcm_row_per_thread; - L->src1_bytes_per_thread = src1_row_size_aligned * vtcm_row_per_thread; - L->dst_bytes_per_thread = dst_row_size_aligned * vtcm_row_per_thread; - - L->off_src0 = 0; - L->off_src1 = L->off_src0 + L->src0_bytes_per_thread * n_threads; - L->off_dst = L->off_src1 + L->src1_bytes_per_thread * n_threads; - - L->total_bytes = L->off_dst + L->dst_bytes_per_thread * n_threads; -} - #define htp_glu_op_preamble \ - const size_t src0_row_size_aligned = actx->src0_row_size_aligned; \ - const size_t src1_row_size_aligned = actx->src1_row_size_aligned; \ - const size_t dst_row_size_aligned = actx->dst_row_size_aligned; \ - const int nc = actx->nc; + const size_t src0_row_size_aligned = gctx->src0_row_size_aligned; \ + const size_t src1_row_size_aligned = gctx->src1_row_size_aligned; \ + const size_t dst_row_size_aligned = gctx->dst_row_size_aligned; \ + const int nc = gctx->nc; // swiglu(x) = x1 * sigmoid(x0) static void swiglu_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -172,10 +138,10 @@ static void swiglu_oai_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; - const float alpha = ((const float *) (actx->octx->op_params))[2]; - const float limit = ((const float *) (actx->octx->op_params))[3]; + const float alpha = ((const float *) (gctx->octx->op_params))[2]; + const float limit = ((const float *) (gctx->octx->op_params))[3]; for (uint32_t ib = 0; ib < num_rows; ib++) { const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); @@ -201,9 +167,9 @@ static void swiglu_clamp_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; - const float limit = ((const float *) (actx->octx->op_params))[3]; + const float limit = ((const float *) (gctx->octx->op_params))[3]; for (uint32_t ib = 0; ib < num_rows; ib++) { const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); @@ -455,7 +421,7 @@ static void geglu_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -472,7 +438,7 @@ static void geglu_quick_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -489,7 +455,7 @@ static void geglu_erf_f32(const float * restrict src0, const float * restrict src1, float * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -501,12 +467,124 @@ static void geglu_erf_f32(const float * restrict src0, } } +static inline void hvx_reglu_f32_aa(uint8_t * restrict dst, const uint8_t * restrict src0, const uint8_t * restrict src1, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src0 % 128 == 0); + assert((unsigned long) src1 % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + const HVX_Vector * restrict vsrc0 = (const HVX_Vector *) src0; + const HVX_Vector * restrict vsrc1 = (const HVX_Vector *) src1; + + const uint32_t epv = 128 / sizeof(float); + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + const HVX_Vector v_zero = Q6_V_vzero(); + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + HVX_Vector x = Q6_Vsf_vmax_VsfVsf(vsrc0[i], v_zero); + vdst[i] = hvx_vec_mul_f32_f32(x, vsrc1[i]); + } + + if (nloe) { + HVX_Vector x = Q6_Vsf_vmax_VsfVsf(vsrc0[i], v_zero); + HVX_Vector res = hvx_vec_mul_f32_f32(x, vsrc1[i]); + hvx_vec_store_a((void *) &vdst[i], nloe * sizeof(float), res); + } +} + +// reglu(x, g) = relu(x) * g +static void reglu_f32(const float * restrict src0, + const float * restrict src1, + float * restrict dst, + const uint32_t num_rows, + const struct htp_glu_context * gctx) { + htp_glu_op_preamble; + + for (uint32_t ib = 0; ib < num_rows; ib++) { + const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); + const uint8_t * restrict src1_ptr = (const uint8_t *) src1 + (ib * src1_row_size_aligned); + uint8_t * restrict dst_ptr = (uint8_t *) dst + (ib * dst_row_size_aligned); + + hvx_reglu_f32_aa(dst_ptr, src0_ptr, src1_ptr, nc); + } +} + +static __attribute__((noinline)) void hvx_sigglu_f32_vec(HVX_Vector * restrict vdst, + const HVX_Vector * restrict vsrc0, + const HVX_Vector * restrict vsrc1, + uint32_t nvec) { + const HVX_Vector v_one = hvx_vec_splat_f32(1.0f); + const HVX_Vector v_max_exp = hvx_vec_splat_f32(87.0f); + const HVX_Vector v_min_exp = hvx_vec_splat_f32(-87.0f); + + for (uint32_t i = 0; i < nvec; i++) { + HVX_Vector sig = hvx_vec_fast_sigmoid_f32_guard(vsrc0[i], v_one, v_max_exp, v_min_exp); + vdst[i] = hvx_vec_mul_f32_f32(sig, vsrc1[i]); + } +} + +static __attribute__((noinline)) void hvx_sigglu_f32_tail(HVX_Vector * restrict vdst, + const HVX_Vector * restrict vsrc0, + const HVX_Vector * restrict vsrc1, + uint32_t nloe) { + const HVX_Vector v_one = hvx_vec_splat_f32(1.0f); + const HVX_Vector v_max_exp = hvx_vec_splat_f32(87.0f); + const HVX_Vector v_min_exp = hvx_vec_splat_f32(-87.0f); + + HVX_Vector sig = hvx_vec_fast_sigmoid_f32_guard(vsrc0[0], v_one, v_max_exp, v_min_exp); + HVX_Vector res = hvx_vec_mul_f32_f32(sig, vsrc1[0]); + hvx_vec_store_a((void *) vdst, nloe * sizeof(float), res); +} + +static inline void hvx_sigglu_f32_aa(uint8_t * restrict dst, const uint8_t * restrict src0, const uint8_t * restrict src1, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src0 % 128 == 0); + assert((unsigned long) src1 % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + const HVX_Vector * restrict vsrc0 = (const HVX_Vector *) src0; + const HVX_Vector * restrict vsrc1 = (const HVX_Vector *) src1; + + const uint32_t epv = 128 / sizeof(float); + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + if (nvec) { + hvx_sigglu_f32_vec(vdst, vsrc0, vsrc1, nvec); + } + if (nloe) { + hvx_sigglu_f32_tail(vdst + nvec, vsrc0 + nvec, vsrc1 + nvec, nloe); + } +} + +// sigglu(x, g) = sigmoid(x) * g +static void sigglu_f32(const float * restrict src0, + const float * restrict src1, + float * restrict dst, + const uint32_t num_rows, + const struct htp_glu_context * gctx) { + htp_glu_op_preamble; + + for (uint32_t ib = 0; ib < num_rows; ib++) { + const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); + const uint8_t * restrict src1_ptr = (const uint8_t *) src1 + (ib * src1_row_size_aligned); + uint8_t * restrict dst_ptr = (uint8_t *) dst + (ib * dst_row_size_aligned); + + hvx_sigglu_f32_aa(dst_ptr, src0_ptr, src1_ptr, nc); + } +} + // swiglu(x) = x1 * sigmoid(x0) static void swiglu_f16(const _Float16 * restrict src0, const _Float16 * restrict src1, _Float16 * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -524,10 +602,10 @@ static void swiglu_oai_f16(const _Float16 * restrict src0, const _Float16 * restrict src1, _Float16 * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; - const _Float16 alpha = (_Float16) ((const float *) (actx->octx->op_params))[2]; - const _Float16 limit = (_Float16) ((const float *) (actx->octx->op_params))[3]; + const _Float16 alpha = (_Float16) ((const float *) (gctx->octx->op_params))[2]; + const _Float16 limit = (_Float16) ((const float *) (gctx->octx->op_params))[3]; for (uint32_t ib = 0; ib < num_rows; ib++) { const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); @@ -553,9 +631,9 @@ static void swiglu_clamp_f16(const _Float16 * restrict src0, const _Float16 * restrict src1, _Float16 * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; - const _Float16 limit = (_Float16) ((const float *) (actx->octx->op_params))[3]; + const _Float16 limit = (_Float16) ((const float *) (gctx->octx->op_params))[3]; for (uint32_t ib = 0; ib < num_rows; ib++) { const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); @@ -574,7 +652,7 @@ static void geglu_f16(const _Float16 * restrict src0, const _Float16 * restrict src1, _Float16 * restrict dst, const uint32_t num_rows, - const struct htp_act_context * actx) { + const struct htp_glu_context * gctx) { htp_glu_op_preamble; for (uint32_t ib = 0; ib < num_rows; ib++) { @@ -586,56 +664,155 @@ static void geglu_f16(const _Float16 * restrict src0, } } +static inline void hvx_reglu_f16_aa(uint8_t * restrict dst, const uint8_t * restrict src0, const uint8_t * restrict src1, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src0 % 128 == 0); + assert((unsigned long) src1 % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + const HVX_Vector * restrict vsrc0 = (const HVX_Vector *) src0; + const HVX_Vector * restrict vsrc1 = (const HVX_Vector *) src1; + + const uint32_t epv = 128 / sizeof(_Float16); + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + const HVX_Vector v_zero = Q6_V_vzero(); + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + HVX_Vector x = Q6_Vhf_vmax_VhfVhf(vsrc0[i], v_zero); + vdst[i] = hvx_vec_mul_f16_f16(x, vsrc1[i]); + } + + if (nloe) { + HVX_Vector x = Q6_Vhf_vmax_VhfVhf(vsrc0[i], v_zero); + HVX_Vector res = hvx_vec_mul_f16_f16(x, vsrc1[i]); + hvx_vec_store_a((void *) &vdst[i], nloe * sizeof(_Float16), res); + } +} + +// reglu(x, g) = relu(x) * g +static void reglu_f16(const _Float16 * restrict src0, + const _Float16 * restrict src1, + _Float16 * restrict dst, + const uint32_t num_rows, + const struct htp_glu_context * gctx) { + htp_glu_op_preamble; + + for (uint32_t ib = 0; ib < num_rows; ib++) { + const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); + const uint8_t * restrict src1_ptr = (const uint8_t *) src1 + (ib * src1_row_size_aligned); + uint8_t * restrict dst_ptr = (uint8_t *) dst + (ib * dst_row_size_aligned); + + hvx_reglu_f16_aa(dst_ptr, src0_ptr, src1_ptr, nc); + } +} + +static __attribute__((noinline)) void hvx_sigglu_f16_vec(HVX_Vector * restrict vdst, + const HVX_Vector * restrict vsrc0, + const HVX_Vector * restrict vsrc1, + uint32_t nvec) { + for (uint32_t i = 0; i < nvec; i++) { + HVX_Vector sig = hvx_vec_fast_sigmoid_f16(vsrc0[i]); + vdst[i] = hvx_vec_mul_f16_f16(sig, vsrc1[i]); + } +} + +static __attribute__((noinline)) void hvx_sigglu_f16_tail(HVX_Vector * restrict vdst, + const HVX_Vector * restrict vsrc0, + const HVX_Vector * restrict vsrc1, + uint32_t nloe) { + HVX_Vector sig = hvx_vec_fast_sigmoid_f16(vsrc0[0]); + HVX_Vector res = hvx_vec_mul_f16_f16(sig, vsrc1[0]); + hvx_vec_store_a((void *) vdst, nloe * sizeof(_Float16), res); +} + +static inline void hvx_sigglu_f16_aa(uint8_t * restrict dst, const uint8_t * restrict src0, const uint8_t * restrict src1, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src0 % 128 == 0); + assert((unsigned long) src1 % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + const HVX_Vector * restrict vsrc0 = (const HVX_Vector *) src0; + const HVX_Vector * restrict vsrc1 = (const HVX_Vector *) src1; + + const uint32_t epv = 128 / sizeof(_Float16); + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + if (nvec) { + hvx_sigglu_f16_vec(vdst, vsrc0, vsrc1, nvec); + } + if (nloe) { + hvx_sigglu_f16_tail(vdst + nvec, vsrc0 + nvec, vsrc1 + nvec, nloe); + } +} + +// sigglu(x, g) = sigmoid(x) * g +static void sigglu_f16(const _Float16 * restrict src0, + const _Float16 * restrict src1, + _Float16 * restrict dst, + const uint32_t num_rows, + const struct htp_glu_context * gctx) { + htp_glu_op_preamble; + + for (uint32_t ib = 0; ib < num_rows; ib++) { + const uint8_t * restrict src0_ptr = (const uint8_t *) src0 + (ib * src0_row_size_aligned); + const uint8_t * restrict src1_ptr = (const uint8_t *) src1 + (ib * src1_row_size_aligned); + uint8_t * restrict dst_ptr = (uint8_t *) dst + (ib * dst_row_size_aligned); + + hvx_sigglu_f16_aa(dst_ptr, src0_ptr, src1_ptr, nc); + } +} + #define DEFINE_GLU_PER_THREAD(TYPE, SUFFIX) \ static void glu_##SUFFIX##_per_thread(unsigned int nth, unsigned int ith, void * data) { \ - struct htp_act_context * actx = (struct htp_act_context *) data; \ - htp_act_preamble; \ + struct htp_glu_context * gctx = (struct htp_glu_context *) data; \ + htp_glu_preamble; \ \ - struct htp_thread_trace * tr = actx->octx->ctx ? &actx->octx->ctx->trace[ith] : NULL; \ + struct htp_thread_trace * tr = gctx->octx->ctx ? &gctx->octx->ctx->trace[ith] : NULL; \ \ - size_t src0_row_size = actx->src0_row_size; \ - size_t src1_row_size = actx->src1_row_size; \ - size_t dst_row_size = actx->dst_row_size; \ + size_t src0_row_size = gctx->src0_row_size; \ + size_t src1_row_size = gctx->src1_row_size; \ + size_t dst_row_size = gctx->dst_row_size; \ \ - size_t src0_row_stride = actx->src0_row_stride; \ - size_t src1_row_stride = actx->src1_row_stride; \ + size_t src0_row_stride = gctx->src0_row_stride; \ + size_t src1_row_stride = gctx->src1_row_stride; \ \ - const uint32_t src0_nrows = actx->src0_nrows; \ - const uint32_t src0_nrows_per_thread = actx->src0_nrows_per_thread; \ + const uint32_t src0_nrows = gctx->src0_nrows; \ + const uint32_t src0_nrows_per_thread = gctx->src0_nrows_per_thread; \ \ - const uint32_t src0_start_row = actx->row_start + src0_nrows_per_thread * ith; \ - const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, actx->row_start + src0_nrows); \ + const uint32_t src0_start_row = gctx->row_start + src0_nrows_per_thread * ith; \ + const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, gctx->row_start + src0_nrows); \ \ /* no work for this thread */ \ if (src0_start_row >= src0_end_row) { \ return; \ } \ \ - const dma_addr_t data_src0 = actx->data_src0; \ - const dma_addr_t data_src1 = actx->data_src1; \ - const dma_addr_t data_dst = actx->data_dst; \ + const dma_addr_t data_src0 = gctx->data_src0; \ + const dma_addr_t data_src1 = gctx->data_src1; \ + const dma_addr_t data_dst = gctx->data_dst; \ \ - const size_t src0_row_size_aligned = actx->src0_row_size_aligned; \ - const size_t src1_row_size_aligned = actx->src1_row_size_aligned; \ - const size_t dst_row_size_aligned = actx->dst_row_size_aligned; \ + const size_t src0_row_size_aligned = gctx->src0_row_size_aligned; \ + const size_t src1_row_size_aligned = gctx->src1_row_size_aligned; \ + const size_t dst_row_size_aligned = gctx->dst_row_size_aligned; \ \ - uint8_t * restrict src0_spad_data = actx->vtcm_src0 + (ith * actx->vtcm_src0_size_per_thread); \ - uint8_t * restrict src1_spad_data = actx->vtcm_src1 + (ith * actx->vtcm_src1_size_per_thread); \ - uint8_t * restrict dst_spad_data = actx->vtcm_dst + (ith * actx->vtcm_dst_size_per_thread); \ + uint8_t * restrict src0_spad_data = gctx->vtcm_src0 + (ith * gctx->vtcm_src0_size_per_thread); \ + uint8_t * restrict src1_spad_data = gctx->vtcm_src1 + (ith * gctx->vtcm_src1_size_per_thread); \ + uint8_t * restrict dst_spad_data = gctx->vtcm_dst + (ith * gctx->vtcm_dst_size_per_thread); \ \ - size_t src0_spad_half_size = actx->src0_spad_half_size; \ - size_t src1_spad_half_size = actx->src1_spad_half_size; \ - size_t dst_spad_half_size = actx->dst_spad_half_size; \ + size_t src0_spad_half_size = gctx->src0_spad_half_size; \ + size_t src1_spad_half_size = gctx->src1_spad_half_size; \ + size_t dst_spad_half_size = gctx->dst_spad_half_size; \ \ - const int BLOCK = actx->block; \ - if (BLOCK == 0) { \ - FARF(ERROR, "%s : VTCM reservation %zu is too small, needed %zu\n", \ - actx->op_str, actx->vtcm_src0_size_per_thread, src0_row_size_aligned); \ - return; \ - } \ + const int BLOCK = gctx->block; \ \ - dma_queue * dma_q = actx->octx->ctx->dma[ith]; \ - glu_compute_##SUFFIX##_fn_t compute = (glu_compute_##SUFFIX##_fn_t) actx->compute; \ + dma_queue * dma_q = gctx->octx->ctx->dma[ith]; \ + glu_compute_##SUFFIX##_fn_t compute = (glu_compute_##SUFFIX##_fn_t) gctx->compute; \ \ for (uint32_t ir = src0_start_row, spad_idx = 0; ir < src0_end_row && spad_idx < 2; ir += BLOCK, spad_idx++) { \ const uint32_t block_size = MIN(BLOCK, src0_end_row - ir); \ @@ -662,7 +839,7 @@ static void geglu_f16(const _Float16 * restrict src0, TYPE * src1_spad = (TYPE *) dma_queue_pop(dma_q).dst; \ \ htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ir); \ - compute(src0_spad, src1_spad, dst_spad, block_size, actx); \ + compute(src0_spad, src1_spad, dst_spad, block_size, gctx); \ htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir); \ \ dma_queue_push(dma_q, dma_make_data(data_dst + (ir * dst_row_size), dst_spad), \ @@ -685,16 +862,11 @@ static void geglu_f16(const _Float16 * restrict src0, DEFINE_GLU_PER_THREAD(float, f32) DEFINE_GLU_PER_THREAD(_Float16, f16) -static int execute_op_activations_f32(struct htp_ops_context * octx) { +static int execute_op_glu_f32(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * src1 = octx->src[1]; const struct htp_tensor * dst = octx->dst; - if ((dst->ne[0] * SIZEOF_FP32) != dst->nb[1]) { - FARF(ERROR, "Non-contiguous dst is not supported at this time \n"); - return HTP_STATUS_NO_SUPPORT; - } - glu_compute_f32_fn_t compute_fn = NULL; const char * op_type = NULL; @@ -729,11 +901,27 @@ static int execute_op_activations_f32(struct htp_ops_context * octx) { op_type = "geglu-erf-f32"; break; + case HTP_OP_GLU_REGLU: + compute_fn = reglu_f32; + op_type = "reglu-f32"; + break; + + case HTP_OP_GLU_SIGMOID: + compute_fn = sigglu_f32; + op_type = "sigglu-f32"; + break; + default: - FARF(ERROR, "Unsupported activations Op %u\n", octx->op); + FARF(ERROR, "Unsupported GLU Op %u\n", octx->op); return HTP_STATUS_NO_SUPPORT; } + const struct htp_glu_kernel_params * kparams = (const struct htp_glu_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; const size_t dst_row_size = dst->ne[0] * SIZEOF_FP32; @@ -762,17 +950,16 @@ static int execute_op_activations_f32(struct htp_ops_context * octx) { const size_t src0_row_stride = src0->nb[1]; const size_t src1_row_stride = src1 ? src1->nb[1] : src0->nb[1]; - const size_t src0_row_size_aligned = hex_round_up(src0_row_size, VLEN); - const size_t src1_row_size_aligned = hex_round_up(src1_row_size, VLEN); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN); + struct htp_glu_vtcm_layout L; + htp_glu_vtcm_layout_build(&L, dst_row_size, n_threads, kparams->vtcm_row_per_thread); - struct htp_act_vtcm_layout L; - htp_act_vtcm_layout_build(&L, src0_row_size_aligned, src1_row_size_aligned, dst_row_size_aligned, n_threads, - octx->ctx->vtcm_size); + const size_t src0_row_size_aligned = L.row_size_aligned; + const size_t src1_row_size_aligned = L.row_size_aligned; + const size_t dst_row_size_aligned = L.row_size_aligned; // Make sure the reserved vtcm size is sufficient - if (L.vtcm_row_per_thread == 0) { - FARF(ERROR, "act-%s : current VTCM reservation %zu is too small for even 1 row per thread, needed at least %zu\n", op_type, octx->ctx->vtcm_size, + if (kparams->vtcm_row_per_thread == 0 || octx->ctx->vtcm_size < kparams->vtcm_size) { + FARF(ERROR, "glu-%s : current VTCM reservation %zu is too small for even 1 row per thread, needed at least %zu\n", op_type, octx->ctx->vtcm_size, (src0_row_size_aligned + src1_row_size_aligned + dst_row_size_aligned) * n_threads); return HTP_STATUS_VTCM_TOO_SMALL; } @@ -789,58 +976,53 @@ static int execute_op_activations_f32(struct htp_ops_context * octx) { } // Prepare context - struct htp_act_context actx; - actx.octx = octx; - actx.compute = (void *) compute_fn; - actx.op_str = op_type; + struct htp_glu_context gctx; + gctx.octx = octx; + gctx.compute = (void *) compute_fn; + gctx.op_str = op_type; - actx.src0_nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); + gctx.src0_nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); - actx.src0_row_size = src0_row_size; - actx.src1_row_size = src1_row_size; - actx.dst_row_size = dst_row_size; + gctx.src0_row_size = src0_row_size; + gctx.src1_row_size = src1_row_size; + gctx.dst_row_size = dst_row_size; - actx.src0_row_size_aligned = src0_row_size_aligned; - actx.src1_row_size_aligned = src1_row_size_aligned; - actx.dst_row_size_aligned = dst_row_size_aligned; + gctx.src0_row_size_aligned = src0_row_size_aligned; + gctx.src1_row_size_aligned = src1_row_size_aligned; + gctx.dst_row_size_aligned = dst_row_size_aligned; - actx.src0_row_stride = src0_row_stride; - actx.src1_row_stride = src1_row_stride; + gctx.src0_row_stride = src0_row_stride; + gctx.src1_row_stride = src1_row_stride; uint8_t * const base = (uint8_t *) octx->ctx->vtcm_base; - actx.vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0); - actx.vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src1); - actx.vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); + gctx.vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0); + gctx.vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src1); + gctx.vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); - actx.vtcm_src0_size_per_thread = L.src0_bytes_per_thread; - actx.vtcm_src1_size_per_thread = L.src1_bytes_per_thread; - actx.vtcm_dst_size_per_thread = L.dst_bytes_per_thread; + gctx.vtcm_src0_size_per_thread = (uint32_t) L.src0_bytes_per_thread; + gctx.vtcm_src1_size_per_thread = (uint32_t) L.src1_bytes_per_thread; + gctx.vtcm_dst_size_per_thread = (uint32_t) L.dst_bytes_per_thread; - actx.src0_spad_half_size = L.src0_bytes_per_thread / 2; - actx.src1_spad_half_size = L.src1_bytes_per_thread / 2; - actx.dst_spad_half_size = L.dst_bytes_per_thread / 2; + gctx.src0_spad_half_size = gctx.vtcm_src0_size_per_thread >> 1; + gctx.src1_spad_half_size = gctx.vtcm_src1_size_per_thread >> 1; + gctx.dst_spad_half_size = gctx.vtcm_dst_size_per_thread >> 1; - actx.block = actx.src0_spad_half_size / actx.src0_row_size_aligned; - actx.src0_nrows = nrows; - actx.row_start = row_start; + gctx.block = L.block; + gctx.src0_nrows = nrows; + gctx.row_start = row_start; - actx.nc = dst->ne[0]; + gctx.nc = dst->ne[0]; // Addresses and GLU logic dma_addr_t data_src0 = src0->data; dma_addr_t data_src1 = src1 ? src1->data : 0; - if (!src1 && (octx->op == HTP_OP_GLU_SWIGLU || - octx->op == HTP_OP_GLU_SWIGLU_OAI || - octx->op == HTP_OP_GLU_SWIGLU_CLAMP || - octx->op == HTP_OP_GLU_GEGLU || - octx->op == HTP_OP_GLU_GEGLU_QUICK || - octx->op == HTP_OP_GLU_GEGLU_ERF)) { + if (!src1) { const int32_t swapped = octx->op_params[1]; data_src1 = data_src0; - actx.src1_row_size = actx.src0_row_size; + gctx.src1_row_size = gctx.src0_row_size; - size_t nc_in_bytes = actx.nc * SIZEOF_FP32; + size_t nc_in_bytes = gctx.nc * SIZEOF_FP32; if (swapped) { data_src0 += nc_in_bytes; } else { @@ -848,24 +1030,19 @@ static int execute_op_activations_f32(struct htp_ops_context * octx) { } } - actx.data_src0 = data_src0; - actx.data_src1 = data_src1; - actx.data_dst = dst->data; + gctx.data_src0 = data_src0; + gctx.data_src1 = data_src1; + gctx.data_dst = dst->data; - work_queue_run(octx->ctx->work_queue, (worker_callback_t)glu_f32_per_thread, &actx, n_threads); + work_queue_run(octx->ctx->work_queue, (worker_callback_t)glu_f32_per_thread, &gctx, n_threads); return HTP_STATUS_OK; } -static int execute_op_activations_f16(struct htp_ops_context * octx) { +static int execute_op_glu_f16(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * src1 = octx->src[1]; const struct htp_tensor * dst = octx->dst; - if ((dst->ne[0] * SIZEOF_FP16) != dst->nb[1]) { - FARF(ERROR, "Non-contiguous dst is not supported at this time \n"); - return HTP_STATUS_NO_SUPPORT; - } - glu_compute_f16_fn_t compute_fn = NULL; const char * op_type = NULL; @@ -890,11 +1067,27 @@ static int execute_op_activations_f16(struct htp_ops_context * octx) { op_type = "geglu-f16"; break; + case HTP_OP_GLU_REGLU: + compute_fn = reglu_f16; + op_type = "reglu-f16"; + break; + + case HTP_OP_GLU_SIGMOID: + compute_fn = sigglu_f16; + op_type = "sigglu-f16"; + break; + default: - FARF(ERROR, "Unsupported activations Op %u\n", octx->op); + FARF(ERROR, "Unsupported GLU Op %u\n", octx->op); return HTP_STATUS_NO_SUPPORT; } + const struct htp_glu_kernel_params * kparams = (const struct htp_glu_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; const size_t dst_row_size = dst->ne[0] * SIZEOF_FP16; @@ -923,17 +1116,16 @@ static int execute_op_activations_f16(struct htp_ops_context * octx) { const size_t src0_row_stride = src0->nb[1]; const size_t src1_row_stride = src1 ? src1->nb[1] : src0->nb[1]; - const size_t src0_row_size_aligned = hex_round_up(src0_row_size, VLEN); - const size_t src1_row_size_aligned = hex_round_up(src1_row_size, VLEN); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN); + struct htp_glu_vtcm_layout L; + htp_glu_vtcm_layout_build(&L, dst_row_size, n_threads, kparams->vtcm_row_per_thread); - struct htp_act_vtcm_layout L; - htp_act_vtcm_layout_build(&L, src0_row_size_aligned, src1_row_size_aligned, dst_row_size_aligned, n_threads, - octx->ctx->vtcm_size); + const size_t src0_row_size_aligned = L.row_size_aligned; + const size_t src1_row_size_aligned = L.row_size_aligned; + const size_t dst_row_size_aligned = L.row_size_aligned; // Make sure the reserved vtcm size is sufficient - if (L.vtcm_row_per_thread == 0) { - FARF(ERROR, "act-%s : current VTCM reservation %zu is too small for even 1 row per thread, needed at least %zu\n", op_type, octx->ctx->vtcm_size, + if (kparams->vtcm_row_per_thread == 0 || octx->ctx->vtcm_size < kparams->vtcm_size) { + FARF(ERROR, "glu-%s : current VTCM reservation %zu is too small for even 1 row per thread, needed at least %zu\n", op_type, octx->ctx->vtcm_size, (src0_row_size_aligned + src1_row_size_aligned + dst_row_size_aligned) * n_threads); return HTP_STATUS_VTCM_TOO_SMALL; } @@ -950,56 +1142,53 @@ static int execute_op_activations_f16(struct htp_ops_context * octx) { } // Prepare context - struct htp_act_context actx; - actx.octx = octx; - actx.compute = (void *) compute_fn; - actx.op_str = op_type; + struct htp_glu_context gctx; + gctx.octx = octx; + gctx.compute = (void *) compute_fn; + gctx.op_str = op_type; - actx.src0_nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); + gctx.src0_nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); - actx.src0_row_size = src0_row_size; - actx.src1_row_size = src1_row_size; - actx.dst_row_size = dst_row_size; + gctx.src0_row_size = src0_row_size; + gctx.src1_row_size = src1_row_size; + gctx.dst_row_size = dst_row_size; - actx.src0_row_size_aligned = src0_row_size_aligned; - actx.src1_row_size_aligned = src1_row_size_aligned; - actx.dst_row_size_aligned = dst_row_size_aligned; + gctx.src0_row_size_aligned = src0_row_size_aligned; + gctx.src1_row_size_aligned = src1_row_size_aligned; + gctx.dst_row_size_aligned = dst_row_size_aligned; - actx.src0_row_stride = src0_row_stride; - actx.src1_row_stride = src1_row_stride; + gctx.src0_row_stride = src0_row_stride; + gctx.src1_row_stride = src1_row_stride; uint8_t * const base = (uint8_t *) octx->ctx->vtcm_base; - actx.vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0); - actx.vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src1); - actx.vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); + gctx.vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0); + gctx.vtcm_src1 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src1); + gctx.vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); - actx.vtcm_src0_size_per_thread = L.src0_bytes_per_thread; - actx.vtcm_src1_size_per_thread = L.src1_bytes_per_thread; - actx.vtcm_dst_size_per_thread = L.dst_bytes_per_thread; + gctx.vtcm_src0_size_per_thread = (uint32_t) L.src0_bytes_per_thread; + gctx.vtcm_src1_size_per_thread = (uint32_t) L.src1_bytes_per_thread; + gctx.vtcm_dst_size_per_thread = (uint32_t) L.dst_bytes_per_thread; - actx.src0_spad_half_size = L.src0_bytes_per_thread / 2; - actx.src1_spad_half_size = L.src1_bytes_per_thread / 2; - actx.dst_spad_half_size = L.dst_bytes_per_thread / 2; + gctx.src0_spad_half_size = gctx.vtcm_src0_size_per_thread >> 1; + gctx.src1_spad_half_size = gctx.vtcm_src1_size_per_thread >> 1; + gctx.dst_spad_half_size = gctx.vtcm_dst_size_per_thread >> 1; - actx.block = actx.src0_spad_half_size / actx.src0_row_size_aligned; - actx.src0_nrows = nrows; - actx.row_start = row_start; + gctx.block = L.block; + gctx.src0_nrows = nrows; + gctx.row_start = row_start; - actx.nc = dst->ne[0]; + gctx.nc = dst->ne[0]; // Addresses and GLU logic dma_addr_t data_src0 = src0->data; dma_addr_t data_src1 = src1 ? src1->data : 0; - if (!src1 && (octx->op == HTP_OP_GLU_SWIGLU || - octx->op == HTP_OP_GLU_SWIGLU_OAI || - octx->op == HTP_OP_GLU_SWIGLU_CLAMP || - octx->op == HTP_OP_GLU_GEGLU)) { + if (!src1) { const int32_t swapped = octx->op_params[1]; data_src1 = data_src0; - actx.src1_row_size = actx.src0_row_size; + gctx.src1_row_size = gctx.src0_row_size; - size_t nc_in_bytes = actx.nc * SIZEOF_FP16; + size_t nc_in_bytes = gctx.nc * SIZEOF_FP16; if (swapped) { data_src0 += nc_in_bytes; } else { @@ -1007,22 +1196,22 @@ static int execute_op_activations_f16(struct htp_ops_context * octx) { } } - actx.data_src0 = data_src0; - actx.data_src1 = data_src1; - actx.data_dst = dst->data; + gctx.data_src0 = data_src0; + gctx.data_src1 = data_src1; + gctx.data_dst = dst->data; - work_queue_run(octx->ctx->work_queue, (worker_callback_t)glu_f16_per_thread, &actx, n_threads); + work_queue_run(octx->ctx->work_queue, (worker_callback_t)glu_f16_per_thread, &gctx, n_threads); return HTP_STATUS_OK; } -int op_activations(struct htp_ops_context * octx) { +int op_glu(struct htp_ops_context * octx) { switch (octx->src[0]->type) { case HTP_TYPE_F32: - return execute_op_activations_f32(octx); + return execute_op_glu_f32(octx); case HTP_TYPE_F16: - return execute_op_activations_f16(octx); + return execute_op_glu_f16(octx); default: return HTP_STATUS_NO_SUPPORT; diff --git a/ggml/src/ggml-hexagon/htp/glu-ops.h b/ggml/src/ggml-hexagon/htp/glu-ops.h new file mode 100644 index 000000000000..41b3857b1281 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/glu-ops.h @@ -0,0 +1,76 @@ +#ifndef HTP_GLU_OPS_H +#define HTP_GLU_OPS_H + +#include "hex-common.h" +#include "htp-ops.h" +#include "htp-vtcm.h" +#include + +struct htp_glu_kernel_params { + uint32_t n_threads; + uint32_t vtcm_row_per_thread; + uint32_t vtcm_size; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_glu_kernel_params) <= 128, "htp_glu_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_glu_kernel_params) <= 128, "htp_glu_kernel_params is too large for kernel_params blob"); +#endif + +static inline bool htp_op_is_glu(uint32_t opcode) { + switch (opcode) { + case HTP_OP_GLU_SWIGLU: + case HTP_OP_GLU_SWIGLU_OAI: + case HTP_OP_GLU_SWIGLU_CLAMP: + case HTP_OP_GLU_GEGLU: + case HTP_OP_GLU_GEGLU_QUICK: + case HTP_OP_GLU_GEGLU_ERF: + case HTP_OP_GLU_REGLU: + case HTP_OP_GLU_SIGMOID: + return true; + default: + return false; + } +} + +struct htp_glu_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_src1; + size_t off_dst; + + size_t row_size_aligned; + size_t src0_bytes_per_thread; + size_t src1_bytes_per_thread; + size_t dst_bytes_per_thread; + + uint32_t vtcm_row_per_thread; + uint32_t block; +}; + +static inline void htp_glu_vtcm_layout_build( + struct htp_glu_vtcm_layout * L, + size_t dst_row_size, + uint32_t n_threads, + uint32_t vtcm_row_per_thread +) { + const size_t row_size_aligned = hex_round_up(dst_row_size, 128); + + L->row_size_aligned = row_size_aligned; + L->vtcm_row_per_thread = vtcm_row_per_thread; + L->block = vtcm_row_per_thread >> 1; + + L->src0_bytes_per_thread = row_size_aligned * vtcm_row_per_thread; + L->src1_bytes_per_thread = row_size_aligned * vtcm_row_per_thread; + L->dst_bytes_per_thread = row_size_aligned * vtcm_row_per_thread; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_src1, L->src1_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + + L->total_bytes = off; +} + +#endif // HTP_GLU_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/hex-common.h b/ggml/src/ggml-hexagon/htp/hex-common.h index e6a52540d58b..b943453a3471 100644 --- a/ggml/src/ggml-hexagon/htp/hex-common.h +++ b/ggml/src/ggml-hexagon/htp/hex-common.h @@ -17,6 +17,10 @@ #define MIN(a, b) ((a) < (b) ? (a) : (b)) #endif +#ifndef HEX_L2_LINE_SIZE +#define HEX_L2_LINE_SIZE 128 +#endif + static inline uint32_t hex_ceil_pow2(uint32_t x) { if (x <= 1) { return 1; } int p = 2; diff --git a/ggml/src/ggml-hexagon/htp/hex-profile.h b/ggml/src/ggml-hexagon/htp/hex-profile.h index a26961fc93b8..5c7a1a488831 100644 --- a/ggml/src/ggml-hexagon/htp/hex-profile.h +++ b/ggml/src/ggml-hexagon/htp/hex-profile.h @@ -44,12 +44,14 @@ struct htp_thread_trace { }; static inline void htp_trace_event(struct htp_thread_trace * tr, uint16_t id, uint16_t info, uint32_t type) { - if (tr->count < tr->max_events) { - uint32_t i = tr->count; + if (!tr->max_events) { + return; + } + uint32_t i = tr->count++; + if (i < tr->max_events) { tr->events[i].id = id; tr->events[i].info = info | (type == HTP_TRACE_EVT_STOP ? 0x8000 : 0); tr->events[i].cycles = (uint32_t) hex_get_cycles(); - tr->count++; } } diff --git a/ggml/src/ggml-hexagon/htp/hmx-mm-kernels-tiled.h b/ggml/src/ggml-hexagon/htp/hmx-mm-kernels-tiled.h index f0a0d9de19bc..65f90c17aad0 100644 --- a/ggml/src/ggml-hexagon/htp/hmx-mm-kernels-tiled.h +++ b/ggml/src/ggml-hexagon/htp/hmx-mm-kernels-tiled.h @@ -14,14 +14,19 @@ static const __fp16 iq4_nl_to_fp16_lut[64] __attribute__((aligned(VLEN))) = { // --- tiled format dequantizers --- -typedef struct { +typedef struct tiled_dequantize_state tiled_dequantize_state_t; +typedef void (*tiled_dequant_task_fn_t)(const tiled_dequantize_state_t * state, uint32_t start_tile, uint32_t end_tile); + +struct tiled_dequantize_state { struct htp_context * ctx; struct htp_thread_trace * traces; __fp16 * dst; const uint8_t * src; + tiled_dequant_task_fn_t task_fn; struct fastdiv_values n_k_tiles_div; uint32_t n_k_tiles; + uint32_t n_weight_tiles; uint32_t n_tot_tiles; uint32_t n_tiles_per_task; uint32_t tile_size; @@ -31,7 +36,40 @@ typedef struct { uint32_t k_block; size_t row_stride; uint32_t weight_type; -} tiled_dequantize_state_t; +}; + +static void dequantize_tiled_weight_to_fp16_task_q1_0( + const tiled_dequantize_state_t *state, + uint32_t start_tile, uint32_t end_tile) { + + const HVX_Vector v_neg_one = Q6_Vb_vsplat_R(-1); + const HVX_Vector v_pos_one = Q6_Vb_vsplat_R(1); + + for (uint32_t t = start_tile; t < end_tile; t++) { + const uint8_t * tile_src = state->src + t * state->aligned_tile_size; + __fp16 * dst_ptr = state->dst + 4 * t * HTP_MM_HMX_TILE_N_ELMS; + + const HVX_Vector v_sc = hvx_vmem(tile_src + 512); + const HVX_Vector v_scale = Q6_V_lo_W(Q6_W_vshuff_VVR(v_sc, v_sc, -2)); + + for (uint32_t q = 0; q < 4; q++) { + const HVX_Vector v_plane = hvx_vmem(tile_src + q * 128); + __fp16 * quarter_dst = dst_ptr + q * HTP_MM_HMX_TILE_N_ELMS; + + #pragma unroll + for (int g = 0; g < 8; g++) { + const HVX_Vector v_q = unpack_q1_0_group(v_plane, g, v_neg_one, v_pos_one); + const HVX_VectorPair vp16 = Q6_Wh_vunpack_Vb(v_q); + const HVX_VectorPair vp_k = Q6_W_vdeal_VVR(Q6_V_hi_W(vp16), Q6_V_lo_W(vp16), -4); + + hvx_vmem(quarter_dst + (2 * g + 0) * 64) = + Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(Q6_Vhf_equals_Vh(Q6_V_lo_W(vp_k)), v_scale)); + hvx_vmem(quarter_dst + (2 * g + 1) * 64) = + Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(Q6_Vhf_equals_Vh(Q6_V_hi_W(vp_k)), v_scale)); + } + } + } +} // Dequantize a single tile from tiled weight data (already in VTCM) to tile-major FP16. static void dequantize_tiled_weight_to_fp16_task_q4_0( @@ -611,7 +649,7 @@ static void dequantize_tiled_weight_to_fp16_task_q5_k( } } -// Q6_K stores 6-bit weights and one fp16 scale per 16 k, see HTP_MM_WEIGHT_TILE_SIZE_Q6_K. +// Q6_K stores 6-bit weights and one fp16 scale per 16 k, see HTP_TENSOR_TILE_SIZE_Q6_K. // A k-group holds 4 k per row, the HMX tile holds 2, so each group is dealt into two tiles. static void dequantize_tiled_weight_to_fp16_task_q6_k( const tiled_dequantize_state_t *state, @@ -669,7 +707,7 @@ static void dequantize_tiled_weight_to_fp16_task_q6_k( } } -// Q3_K stores 3-bit weights and one fp16 scale per 16 k, see HTP_MM_WEIGHT_TILE_SIZE_Q3_K. +// Q3_K stores 3-bit weights and one fp16 scale per 16 k, see HTP_TENSOR_TILE_SIZE_Q3_K. static void dequantize_tiled_weight_to_fp16_task_q3_k( const tiled_dequantize_state_t *state, uint32_t start_tile, uint32_t end_tile) { @@ -701,7 +739,7 @@ static void dequantize_tiled_weight_to_fp16_task_q3_k( } } -// Q2_K stores 2-bit weights, the ggml scale bytes and d / -dmin per super-block, see HTP_MM_WEIGHT_TILE_SIZE_Q2_K. +// Q2_K stores 2-bit weights, the ggml scale bytes and d / -dmin per super-block, see HTP_TENSOR_TILE_SIZE_Q2_K. static void dequantize_tiled_weight_to_fp16_task_q2_k( const tiled_dequantize_state_t *state, uint32_t start_tile, uint32_t end_tile) { @@ -747,6 +785,40 @@ static void dequantize_tiled_weight_to_fp16_task_q2_k( } } +// Q2_0 stores codes 0..3 (value code - 1) and one fp16 scale per row, see HTP_MM_WEIGHT_TILE_SIZE_Q2_0. +// One packed 64-k tile expands into two consecutive 32-k fp16 tiles. +static void dequantize_tiled_weight_to_fp16_task_q2_0( + const tiled_dequantize_state_t *state, + uint32_t start_tile, uint32_t end_tile) { + + const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + const HVX_Vector i1 = Q6_Vb_vsplat_R(1); + + for (uint32_t t = start_tile; t < end_tile; t++) { + const HVX_Vector * vptr = (const HVX_Vector *) (state->src + t * state->aligned_tile_size); + __fp16 * dst_base = state->dst + 2 * t * HTP_MM_HMX_TILE_N_ELMS; + + HVX_Vector v_sc = vptr[4]; + HVX_Vector v_scale = Q6_V_lo_W(Q6_W_vshuff_VVR(v_sc, v_sc, -2)); + + for (int half = 0; half < 2; half++) { + __fp16 * dst_ptr = dst_base + half * HTP_MM_HMX_TILE_N_ELMS; + + #pragma unroll + for (int g = 0; g < 8; g++) { + HVX_Vector v_q = Q6_Vb_vsub_VbVb(unpack_q3_k_low2(vptr + 2 * half, g, mask_03), i1); + HVX_VectorPair vp16 = Q6_Wh_vunpack_Vb(v_q); + HVX_VectorPair vp_k = Q6_W_vdeal_VVR(Q6_V_hi_W(vp16), Q6_V_lo_W(vp16), -4); + + hvx_vmem(dst_ptr + (2 * g + 0) * 64) = + Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(Q6_Vhf_equals_Vh(Q6_V_lo_W(vp_k)), v_scale)); + hvx_vmem(dst_ptr + (2 * g + 1) * 64) = + Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(Q6_Vhf_equals_Vh(Q6_V_hi_W(vp_k)), v_scale)); + } + } + } +} + static __attribute__((noinline)) void convert_f16_weight_to_fp16_tiles_task( const tiled_dequantize_state_t *state, @@ -837,6 +909,56 @@ void quantize_f32_weight_to_fp16_tiles_task( } } +static __attribute__((noinline)) +void convert_bf16_weight_to_fp16_tiles_task( + const tiled_dequantize_state_t *state, + uint32_t start_tile, uint32_t end_tile) { + + const uint32_t n_k_tiles = state->n_k_tiles; + const struct fastdiv_values n_k_tiles_div = state->n_k_tiles_div; + + const HVX_Vector v_scat_base = hvx_vmem(hmx_transpose_scatter_offsets); + const HVX_Vector v_scat_step = Q6_V_vsplat_R(4); + const HVX_VectorPred q_mask64 = Q6_Q_vsetq_R(64); + + unsigned ct = fastdiv((unsigned)start_tile, &n_k_tiles_div); + unsigned kt = fastmodulo((unsigned)start_tile, n_k_tiles, &n_k_tiles_div); + + for (unsigned t = start_tile; t < (unsigned)end_tile; ) { + if (kt >= (unsigned)n_k_tiles) { kt = 0; ct++; } + + __fp16 *tile_base = state->dst + t * HTP_MM_HMX_TILE_N_ELMS; + { + uint32_t byte_off = kt * 32 * sizeof(uint16_t); + + HVX_Vector v_off = v_scat_base; + for (uint32_t r = 0; r < HTP_MM_HMX_TILE_N_ROWS; r += 2) { + uint32_t row0 = ct * HTP_MM_HMX_TILE_N_COLS + r; + uint32_t row1 = row0 + 1; + + const uint8_t *r0 = state->src + row0 * state->row_stride; + const uint8_t *r1 = state->src + row1 * state->row_stride; + + HVX_Vector v0_raw = (row0 < state->n_cols) ? hvx_vmemu((const void *)(r0 + byte_off)) : Q6_V_vzero(); + HVX_Vector v1_raw = (row1 < state->n_cols) ? hvx_vmemu((const void *)(r1 + byte_off)) : Q6_V_vzero(); + + HVX_Vector v0_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(Q6_Ww_vunpack_Vh(v0_raw)), 16); + HVX_Vector v1_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(Q6_Ww_vunpack_Vh(v1_raw)), 16); + + HVX_Vector v_out = hvx_vec_f32_to_f16(v0_f32, v1_f32); + + Q6_vscatter_QRMVwV(q_mask64, (size_t)tile_base, HTP_MM_HMX_TILE_SIZE - 1, v_off, v_out); + v_off = Q6_Vw_vadd_VwVw(v_off, v_scat_step); + + HVX_Vector v_out_hi = Q6_V_vror_VR(v_out, 64); + Q6_vscatter_QRMVwV(q_mask64, (size_t)tile_base, HTP_MM_HMX_TILE_SIZE - 1, v_off, v_out_hi); + v_off = Q6_Vw_vadd_VwVw(v_off, v_scat_step); + } + } + ++t; ++kt; + } +} + // --- End tiled dequantizers --- // dot-chunk functions require external HMX lock diff --git a/ggml/src/ggml-hexagon/htp/htp-ctx.h b/ggml/src/ggml-hexagon/htp/htp-ctx.h index b36322ae81ed..0c455141d384 100644 --- a/ggml/src/ggml-hexagon/htp/htp-ctx.h +++ b/ggml/src/ggml-hexagon/htp/htp-ctx.h @@ -3,6 +3,7 @@ #include "dma-queue.h" #include "hmx-queue.h" +#include "htp-dcache.h" #include "htp-ops.h" #include "hex-profile.h" #include "work-queue.h" @@ -11,15 +12,16 @@ #include #include #include +#include #include #include +#include #ifndef HTP_MAX_NTHREADS #define HTP_MAX_NTHREADS 10 #endif -#define HTP_MAX_MMAPS 64 -#define HTP_MAX_DIRTY_RANGES 64 +#define HTP_MAX_MMAPS 64 // Memory mapping struct htp_mmap { @@ -29,11 +31,6 @@ struct htp_mmap { uint32_t flags; }; -struct htp_dirty_range { - uint32_t start; - uint32_t end; -}; - // Scratchpad state struct htp_spad { const struct htp_tensor * src; // original src of the data (for reuse) @@ -71,14 +68,18 @@ struct htp_ops_context { // TODO convert these to an array struct htp_spad src0_spad; struct htp_spad src1_spad; - struct htp_spad src2_spad; - struct htp_spad src3_spad; struct htp_spad dst_spad; uint32_t flags; uint32_t n_threads; struct fastdiv_values n_threads_div; int status; + + // Must stay last: not cleared by htp_ops_context_reset(), ops init the caches they use + union { + dma_cache_dm dma_cache_dm[HTP_MAX_NTHREADS]; + dma_cache_fa dma_cache_fa[HTP_MAX_NTHREADS]; + } __attribute__((aligned(128))); }; // Main context for htp DSP backend @@ -123,6 +124,13 @@ struct htp_context { size_t footprint; }; +static inline void htp_ops_context_reset(struct htp_ops_context * octx, struct htp_context * ctx) { + memset(octx, 0, offsetof(struct htp_ops_context, dma_cache_dm)); + octx->ctx = ctx; + octx->n_threads = ctx->n_threads; + octx->n_threads_div = ctx->n_threads_div; +} + static inline bool htp_ops_context_set_n_threads(struct htp_ops_context * octx, uint32_t n_threads) { if (n_threads == 0 || n_threads > octx->ctx->n_threads) { return false; @@ -153,7 +161,7 @@ int op_unary(struct htp_ops_context * octx); int op_sum(struct htp_ops_context * octx); int op_sum_rows(struct htp_ops_context * octx); int op_argmax(struct htp_ops_context * octx); -int op_activations(struct htp_ops_context * octx); +int op_glu(struct htp_ops_context * octx); int op_softmax(struct htp_ops_context * octx); int op_add_id(struct htp_ops_context * octx); int op_rope(struct htp_ops_context * octx); @@ -174,9 +182,12 @@ int op_gated_delta_net(struct htp_ops_context * octx); int op_pad(struct htp_ops_context * octx); int op_im2col(struct htp_ops_context * octx); int op_im2col_3d(struct htp_ops_context * octx); +int op_conv_2d(struct htp_ops_context * octx); +int op_conv_2d_dw(struct htp_ops_context * octx); int op_pool_2d(struct htp_ops_context * octx); int op_pool_1d(struct htp_ops_context * octx); int op_allreduce(struct htp_ops_context * octx); int op_roll(struct htp_ops_context * octx); +int op_upscale(struct htp_ops_context * octx); #endif /* HTP_CTX_H */ diff --git a/ggml/src/ggml-hexagon/htp/htp-tensor.c b/ggml/src/ggml-hexagon/htp/htp-dcache.c similarity index 97% rename from ggml/src/ggml-hexagon/htp/htp-tensor.c rename to ggml/src/ggml-hexagon/htp/htp-dcache.c index 03b0070d78a7..840b1edb7a7c 100644 --- a/ggml/src/ggml-hexagon/htp/htp-tensor.c +++ b/ggml/src/ggml-hexagon/htp/htp-dcache.c @@ -1,4 +1,4 @@ -#include "htp-tensor.h" +#include "htp-dcache.h" #include #include @@ -94,7 +94,7 @@ static void merge_dirty_ranges(struct htp_context * ctx) { } } -void htp_tensor_dirty_all(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n) { +void htp_dcache_mark_dirty_tensors(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n) { const struct htp_tensor * pending[HTP_OP_MAX_OUTPUTS]; uint32_t n_pending = 0; @@ -301,7 +301,7 @@ static void flush_dirty_ranges(struct htp_context * ctx, const struct htp_dirty_ } } -void htp_flush_dirty_ranges(struct htp_context * ctx) { +void htp_dcache_flush_dirty_ranges(struct htp_context * ctx) { struct htp_dirty_range ranges[HTP_MAX_DIRTY_RANGES]; uint32_t n_ranges = 0; uint64_t total_dirty = 0; @@ -328,7 +328,7 @@ void htp_flush_dirty_ranges(struct htp_context * ctx) { memset(ctx->dirty_ranges, 0, sizeof(ctx->dirty_ranges)); } -void htp_tensor_flush_all(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n) { +void htp_dcache_flush_dirty_tensors(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n) { const struct htp_tensor * dirty_tensors[HTP_OP_MAX_INPUTS]; struct htp_dirty_range ranges[HTP_OP_MAX_INPUTS]; uint32_t n_dirty = 0; diff --git a/ggml/src/ggml-hexagon/htp/htp-dcache.h b/ggml/src/ggml-hexagon/htp/htp-dcache.h new file mode 100644 index 000000000000..1996ab258d3e --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/htp-dcache.h @@ -0,0 +1,20 @@ +#ifndef HTP_DCACHE_H +#define HTP_DCACHE_H + +#include +#include "htp-ops.h" + +#define HTP_MAX_DIRTY_RANGES 64 + +struct htp_dirty_range { + uint32_t start; + uint32_t end; +}; + +struct htp_context; + +void htp_dcache_flush_dirty_ranges(struct htp_context * ctx); +void htp_dcache_flush_dirty_tensors(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n); +void htp_dcache_mark_dirty_tensors(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n); + +#endif // HTP_DCACHE_H diff --git a/ggml/src/ggml-hexagon/htp/htp-ops.h b/ggml/src/ggml-hexagon/htp/htp-ops.h index 70d56e181a55..b8df01830b84 100644 --- a/ggml/src/ggml-hexagon/htp/htp-ops.h +++ b/ggml/src/ggml-hexagon/htp/htp-ops.h @@ -30,24 +30,14 @@ enum htp_data_type { HTP_TYPE_IQ4_NL = 20, HTP_TYPE_I32 = 26, HTP_TYPE_I64 = 27, + HTP_TYPE_BF16 = 30, HTP_TYPE_MXFP4 = 39, - - // types used internally for repack, dyn.quant, etc - HTP_TYPE_Q4_0_TILED = 200, - HTP_TYPE_Q4_1_TILED, - HTP_TYPE_Q8_0_TILED, - HTP_TYPE_MXFP4_TILED, + HTP_TYPE_Q1_0 = 41, + HTP_TYPE_Q2_0 = 42, HTP_TYPE_INVALID }; -// Constats for internal types -#define QK_Q4_0_TILED 256 // 32x32 Q4_0 tiled layout -#define QK_Q8_0_TILED 128 // 32x32 Q8_0 tiled layout -#define QK_MXFP4_TILED 256 // 32x32 MXFP4 tiled layout - - - // Do not reorder first 4 (used as an index) enum htp_op_code { HTP_OP_MUL = 0, @@ -106,6 +96,8 @@ enum htp_op_code { HTP_OP_CLAMP, HTP_OP_LEAKY_RELU, HTP_OP_IM2COL, + HTP_OP_CONV_2D, + HTP_OP_CONV_2D_DW, HTP_OP_FENCE, HTP_OP_ALLREDUCE, HTP_OP_ALLREDUCE_ADD, @@ -119,6 +111,12 @@ enum htp_op_code { HTP_OP_POOL_1D, HTP_OP_UNARY_GELU_QUICK, HTP_OP_IM2COL_3D, + HTP_OP_HADAMARD, + HTP_OP_GLU_REGLU, + HTP_OP_GLU_SIGMOID, + HTP_OP_UNARY_CEIL, + HTP_OP_UNARY_SGN, + HTP_OP_UPSCALE, HTP_OP_INVALID }; @@ -129,8 +127,8 @@ enum htp_op_code { #define HTP_OP_MAX_PARAMS 16 // aka GGML_MAX_OP_PARAMS #define HTP_OP_MAX_KERN_PARAMS 32 -#define HTP_OP_MAX_BUFS 16 -#define HTP_OP_MAX_TENSORS 8192 // must stay under 64K (uint16) +#define HTP_OP_MAX_BUFS 64 +#define HTP_OP_MAX_TENSORS 65534 // must stay under 64K (uint16) #define HTP_FENCE_TIMEOUT (1000000000ULL) #define HTP_FENCE_SLOT_SIZE 128 @@ -139,10 +137,13 @@ enum htp_op_code { #define HTP_MMAP_MAX_VMEM (2147483648u) +#define HTP_DDR_SPAD_SIZE (512 * 1024) + enum htp_tensor_flags { - HTP_TENSOR_WEIGHT = (1U << 0), // Tensor buffer model weight data (not compute) - HTP_TENSOR_REPACK = (1U << 1), // Tensor is in repacked tiled format - HTP_TENSOR_FENCE = (1U << 2) // Tensor is synchronization fence (explicitly managed) + HTP_TENSOR_WEIGHT = (1U << 0), // Tensor buffer model weight data (not compute) + HTP_TENSOR_TILED = (1U << 1), // Tensor is in tiled format + HTP_TENSOR_FENCE = (1U << 2), // Tensor is synchronization fence (explicitly managed) + HTP_TENSOR_FUSEABLE = (1U << 3), // Tensor can be fused (host-only) }; enum htp_buf_flags { diff --git a/ggml/src/ggml-hexagon/htp/htp-swiv.py b/ggml/src/ggml-hexagon/htp/htp-swiv.py new file mode 100644 index 000000000000..15d7bef274d9 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/htp-swiv.py @@ -0,0 +1,512 @@ +#!/usr/bin/env python3 + +import argparse +import logging +import os +import shutil +import struct +import sys +import tempfile +import zlib + +ELF_MAGIC = b'\x7fELF' +ELF_CLASS_INDEX = 4 +ELFCLASS32 = 1 +ELFCLASS64 = 2 +ELF_VERSION_INDEX = 6 +EV_CURRENT = 1 +MAX_PHDR_COUNT = 100 + +LOAD_TYPE = 0x1 + +SHT_NOBITS = 8 + +SWIV_MAGIC = b'SWIV' +SWIV_SEG_SIZE_MIN = 16 +# SHT_LOUSER plus ASCII "SWIV". +SWIV_SECTION_TYPE = 0xD3574956 + +logger = logging.getLogger("htp-swiv") + + +class Elf_Ehdr_common: + s = struct.Struct('16sHHI') + + def __init__(self, data): + unpacked_data = (Elf_Ehdr_common.s).unpack(data) + self.e_ident = unpacked_data[0] + self.e_type = unpacked_data[1] + self.e_machine = unpacked_data[2] + self.e_version = unpacked_data[3] + + +class Elf32_Ehdr: + s = struct.Struct('16sHHIIIIIHHHHHH') + + def __init__(self, data): + unpacked_data = (Elf32_Ehdr.s).unpack(data) + self.e_ident = unpacked_data[0] + self.e_type = unpacked_data[1] + self.e_machine = unpacked_data[2] + self.e_version = unpacked_data[3] + self.e_entry = unpacked_data[4] + self.e_phoff = unpacked_data[5] + self.e_shoff = unpacked_data[6] + self.e_flags = unpacked_data[7] + self.e_ehsize = unpacked_data[8] + self.e_phentsize = unpacked_data[9] + self.e_phnum = unpacked_data[10] + self.e_shentsize = unpacked_data[11] + self.e_shnum = unpacked_data[12] + self.e_shstrndx = unpacked_data[13] + + def get_packed_data(self): + values = [self.e_ident, + self.e_type, + self.e_machine, + self.e_version, + self.e_entry, + self.e_phoff, + self.e_shoff, + self.e_flags, + self.e_ehsize, + self.e_phentsize, + self.e_phnum, + self.e_shentsize, + self.e_shnum, + self.e_shstrndx + ] + + return (Elf32_Ehdr.s).pack(*values) + + +class Elf32_Phdr: + s = struct.Struct('I' * 8) + + def __init__(self, data): + unpacked_data = (Elf32_Phdr.s).unpack(data) + self.p_type = unpacked_data[0] + self.p_offset = unpacked_data[1] + self.p_vaddr = unpacked_data[2] + self.p_paddr = unpacked_data[3] + self.p_filesz = unpacked_data[4] + self.p_memsz = unpacked_data[5] + self.p_flags = unpacked_data[6] + self.p_align = unpacked_data[7] + + def get_packed_data(self): + values = [self.p_type, + self.p_offset, + self.p_vaddr, + self.p_paddr, + self.p_filesz, + self.p_memsz, + self.p_flags, + self.p_align + ] + + return (Elf32_Phdr.s).pack(*values) + + +class Elf32_Shdr: + s = struct.Struct('I' * 10) + + def __init__(self, data): + unpacked_data = (Elf32_Shdr.s).unpack(data) + self.sh_name = unpacked_data[0] + self.sh_type = unpacked_data[1] + self.sh_flags = unpacked_data[2] + self.sh_addr = unpacked_data[3] + self.sh_offset = unpacked_data[4] + self.sh_size = unpacked_data[5] + self.sh_link = unpacked_data[6] + self.sh_info = unpacked_data[7] + self.sh_addralign = unpacked_data[8] + self.sh_entsize = unpacked_data[9] + self.sh_name_str = "" + + def get_packed_data(self): + values = [self.sh_name, + self.sh_type, + self.sh_flags, + self.sh_addr, + self.sh_offset, + self.sh_size, + self.sh_link, + self.sh_info, + self.sh_addralign, + self.sh_entsize] + + return (Elf32_Shdr.s).pack(*values) + + +class Elf64_Ehdr: + s = struct.Struct('16sHHIQQQIHHHHHH') + + def __init__(self, data): + unpacked_data = (Elf64_Ehdr.s).unpack(data) + self.e_ident = unpacked_data[0] + self.e_type = unpacked_data[1] + self.e_machine = unpacked_data[2] + self.e_version = unpacked_data[3] + self.e_entry = unpacked_data[4] + self.e_phoff = unpacked_data[5] + self.e_shoff = unpacked_data[6] + self.e_flags = unpacked_data[7] + self.e_ehsize = unpacked_data[8] + self.e_phentsize = unpacked_data[9] + self.e_phnum = unpacked_data[10] + self.e_shentsize = unpacked_data[11] + self.e_shnum = unpacked_data[12] + self.e_shstrndx = unpacked_data[13] + + def get_packed_data(self): + values = [self.e_ident, + self.e_type, + self.e_machine, + self.e_version, + self.e_entry, + self.e_phoff, + self.e_shoff, + self.e_flags, + self.e_ehsize, + self.e_phentsize, + self.e_phnum, + self.e_shentsize, + self.e_shnum, + self.e_shstrndx + ] + + return (Elf64_Ehdr.s).pack(*values) + + +class Elf64_Phdr: + s = struct.Struct('IIQQQQQQ') + + def __init__(self, data): + unpacked_data = (Elf64_Phdr.s).unpack(data) + self.p_type = unpacked_data[0] + self.p_flags = unpacked_data[1] + self.p_offset = unpacked_data[2] + self.p_vaddr = unpacked_data[3] + self.p_paddr = unpacked_data[4] + self.p_filesz = unpacked_data[5] + self.p_memsz = unpacked_data[6] + self.p_align = unpacked_data[7] + + def get_packed_data(self): + values = [self.p_type, + self.p_flags, + self.p_offset, + self.p_vaddr, + self.p_paddr, + self.p_filesz, + self.p_memsz, + self.p_align + ] + + return (Elf64_Phdr.s).pack(*values) + + +class Elf64_Shdr: + s = struct.Struct('IIQQQQIIQQ') + + def __init__(self, data): + unpacked_data = (Elf64_Shdr.s).unpack(data) + self.sh_name = unpacked_data[0] + self.sh_type = unpacked_data[1] + self.sh_flags = unpacked_data[2] + self.sh_addr = unpacked_data[3] + self.sh_offset = unpacked_data[4] + self.sh_size = unpacked_data[5] + self.sh_link = unpacked_data[6] + self.sh_info = unpacked_data[7] + self.sh_addralign = unpacked_data[8] + self.sh_entsize = unpacked_data[9] + self.sh_name_str = "" + + def get_packed_data(self): + values = [self.sh_name, + self.sh_type, + self.sh_flags, + self.sh_addr, + self.sh_offset, + self.sh_size, + self.sh_link, + self.sh_info, + self.sh_addralign, + self.sh_entsize] + + return (Elf64_Shdr.s).pack(*values) + + +class SWIV_Seg: + s = struct.Struct('4sIQ') + + def __init__(self): + self.magic = SWIV_MAGIC + self.crc = 0 + self.padding = 0 + + def get_packed_data(self): + values = [self.magic, + self.crc, + self.padding + ] + + return (SWIV_Seg.s).pack(*values) + + +def is_elf64(elf_header): + return elf_header.e_ident[ELF_CLASS_INDEX] == ELFCLASS64 + + +def verify_elf_header(elf_header): + ident = elf_header.e_ident + return (ident.startswith(ELF_MAGIC) + and ident[ELF_CLASS_INDEX] in (ELFCLASS32, ELFCLASS64) + and ident[ELF_VERSION_INDEX] == EV_CURRENT) + + +def file_copy_offset(in_fp, in_off, out_fp, out_off, num_bytes): + in_fp.seek(in_off) + read_in = in_fp.read(num_bytes) + out_fp.seek(out_off) + out_fp.write(read_in) + + return num_bytes + + +def preprocess_elf_file(elf_file_name): + with open(elf_file_name, 'rb') as elf_fp: + elf_header = Elf_Ehdr_common(elf_fp.read(Elf_Ehdr_common.s.size)) + + if verify_elf_header(elf_header) is False: + raise RuntimeError("Input ELF verification failed : " + elf_file_name) + + elf_fp.seek(0) + + if is_elf64(elf_header): + elf_header = Elf64_Ehdr(elf_fp.read(Elf64_Ehdr.s.size)) + else: + elf_header = Elf32_Ehdr(elf_fp.read(Elf32_Ehdr.s.size)) + + phdr_table = [] + + phdr_size = elf_header.e_phentsize + + file_offset = elf_header.e_phoff + elf_fp.seek(file_offset) + + for _ in range(elf_header.e_phnum): + if is_elf64(elf_header): + phdr_table.append(Elf64_Phdr(elf_fp.read(phdr_size))) + else: + phdr_table.append(Elf32_Phdr(elf_fp.read(phdr_size))) + + return [elf_header, phdr_table] + + +def process_section_header(elf_file_name): + with open(elf_file_name, 'rb') as elf_fp: + elf_header = Elf_Ehdr_common(elf_fp.read(Elf_Ehdr_common.s.size)) + + if verify_elf_header(elf_header) is False: + raise RuntimeError("Input ELF verification failed : " + elf_file_name) + + elf_fp.seek(0) + + if is_elf64(elf_header): + elf_header = Elf64_Ehdr(elf_fp.read(Elf64_Ehdr.s.size)) + else: + elf_header = Elf32_Ehdr(elf_fp.read(Elf32_Ehdr.s.size)) + + shdr_table = [] + + shdr_size = elf_header.e_shentsize + elf_fp.seek(elf_header.e_shoff) + + for _ in range(elf_header.e_shnum): + if is_elf64(elf_header): + shdr_table.append(Elf64_Shdr(elf_fp.read(shdr_size))) + else: + shdr_table.append(Elf32_Shdr(elf_fp.read(shdr_size))) + + return shdr_table + + +def crc32_update_file(elf_fp, offset, size, crc): + elf_fp.seek(offset) + remaining = size + while remaining > 0: + chunk = elf_fp.read(min(1024 * 1024, remaining)) + if not chunk: + raise RuntimeError("Unexpected EOF while calculating CRC") + crc = zlib.crc32(chunk, crc) + remaining -= len(chunk) + return crc + + +def crc32_update_zeros(size, crc): + zero_chunk = b'\x00' * min(1024 * 1024, size) + remaining = size + while remaining > 0: + chunk = zero_chunk[:min(len(zero_chunk), remaining)] + crc = zlib.crc32(chunk, crc) + remaining -= len(chunk) + return crc + + +def crc32_calculate(elf_fp, phdr_table): + crc = 0 + + # SWIV validates loadable segment contents, including BSS as zeros. + for curr_phdr in phdr_table: + if curr_phdr.p_type != LOAD_TYPE: + continue + + crc = crc32_update_file(elf_fp, curr_phdr.p_offset, curr_phdr.p_filesz, crc) + + zero_size = curr_phdr.p_memsz - curr_phdr.p_filesz + if zero_size > 0: + crc = crc32_update_zeros(zero_size, crc) + + crc &= 0xffffffff + logger.info("calculated CRC: %#x", crc) + + return crc + + +def verify_swiv_seg(elf_in_fp, offset): + + elf_in_fp.seek(offset) + swiv_seg = SWIV_Seg() + unpacked_data = (SWIV_Seg.s).unpack(elf_in_fp.read(SWIV_SEG_SIZE_MIN)) + swiv_seg.magic = unpacked_data[0] + + return swiv_seg.magic == SWIV_MAGIC + + +def same_output_file(input_elf, output_elf): + try: + return os.path.exists(output_elf) and os.path.samefile(input_elf, output_elf) + except FileNotFoundError: + return False + + +def make_output_target(input_elf, output_elf): + if not same_output_file(input_elf, output_elf): + return output_elf, None + + output_dir = os.path.dirname(os.path.abspath(output_elf)) + output_base = os.path.basename(output_elf) + fd, temp_output = tempfile.mkstemp(prefix=output_base + ".", suffix=".tmp", dir=output_dir) + os.close(fd) + shutil.copymode(input_elf, temp_output) + return temp_output, temp_output + + +def swiv_generate(input_elf, output_elf): + output_target, temp_output = make_output_target(input_elf, output_elf) + + try: + with open(input_elf, "rb") as elf_in_fp, open(output_target, "wb+") as elf_out_fp: + [elf_header, phdr_table] = preprocess_elf_file(input_elf) + + num_phdrs = elf_header.e_phnum + num_shdrs = elf_header.e_shnum + phdr_size = elf_header.e_phentsize + + if num_phdrs == 0 or num_phdrs > MAX_PHDR_COUNT: + raise RuntimeError("Input ELF has invalid number of program headers.") + + if elf_header.e_shoff == 0 or num_shdrs == 0: + raise RuntimeError("Input ELF does not contain a section header table.") + + shdr_table_input = process_section_header(input_elf) + shdr_table_output = process_section_header(input_elf) + + last_phdr = phdr_table[num_phdrs - 1] + if last_phdr.p_memsz == SWIV_SEG_SIZE_MIN and verify_swiv_seg(elf_in_fp, last_phdr.p_offset): + raise RuntimeError("A SWIV segment is detected in the input ELF.") + + last_shdr = shdr_table_input[elf_header.e_shnum - 1] + if last_shdr.sh_size == SWIV_SEG_SIZE_MIN and verify_swiv_seg(elf_in_fp, last_shdr.sh_offset): + raise RuntimeError("A SWIV section is detected in the input ELF.") + + if is_elf64(elf_header): + swiv_shdr = Elf64_Shdr(b'\0' * Elf64_Shdr.s.size) + else: + swiv_shdr = Elf32_Shdr(b'\0' * Elf32_Shdr.s.size) + + swiv_shdr.sh_name = 0 + swiv_shdr.sh_type = SWIV_SECTION_TYPE + swiv_shdr.sh_flags = 0 + swiv_shdr.sh_addr = 0 + swiv_shdr.sh_size = SWIV_SEG_SIZE_MIN + swiv_shdr.sh_offset = elf_header.e_shoff + (elf_header.e_shnum + 1) * elf_header.e_shentsize + shdr_table_output.append(swiv_shdr) + elf_header.e_shnum += 1 + + if elf_header.e_phoff != 0: + for phdr in phdr_table: + file_copy_offset(elf_in_fp, phdr.p_offset, elf_out_fp, phdr.p_offset, phdr.p_filesz) + + elf_out_fp.seek(0) + elf_out_fp.write(elf_header.get_packed_data()) + + phdr_start = elf_header.e_phoff + for phdr in phdr_table: + elf_out_fp.seek(phdr_start) + elf_out_fp.write(phdr.get_packed_data()) + phdr_start += phdr_size + + for shdr in shdr_table_input[:num_shdrs]: + if shdr.sh_type == SHT_NOBITS or shdr.sh_size == 0: + continue + file_copy_offset(elf_in_fp, shdr.sh_offset, elf_out_fp, shdr.sh_offset, shdr.sh_size) + + shdr_start = elf_header.e_shoff + for shdr in shdr_table_output: + elf_out_fp.seek(shdr_start) + elf_out_fp.write(shdr.get_packed_data()) + shdr_start += elf_header.e_shentsize + + elf_out_fp.flush() + + swiv_seg = SWIV_Seg() + swiv_seg.crc = crc32_calculate(elf_out_fp, phdr_table) + elf_out_fp.seek(swiv_shdr.sh_offset) + elf_out_fp.write(swiv_seg.get_packed_data()) + + if temp_output is not None: + os.replace(temp_output, output_elf) + temp_output = None + + return 0 + finally: + if temp_output is not None and os.path.exists(temp_output): + os.unlink(temp_output) + + +def main(argv): + parser = argparse.ArgumentParser(description="Add a Software Image Validation (SWIV) section to an HTP ELF file.") + parser.add_argument("-i", "--input", dest="input_file", metavar="INPUT", required=True) + parser.add_argument("-o", "--output", dest="output_file", metavar="OUTPUT", required=True) + parser.add_argument("-v", "--verbose", action="store_true", help="show calculated CRC") + args = parser.parse_args(argv) + + logging.basicConfig( + level=logging.INFO if args.verbose else logging.WARNING, + format="%(message)s", + ) + + try: + return swiv_generate(args.input_file, args.output_file) + except RuntimeError as exc: + logger.error("ERROR: %s", exc) + return 2 + + +if __name__ == "__main__": + sys.exit(main(sys.argv[1:])) diff --git a/ggml/src/ggml-hexagon/htp/htp-tensor.h b/ggml/src/ggml-hexagon/htp/htp-tensor.h index f7a96683615a..a5ea0d533984 100644 --- a/ggml/src/ggml-hexagon/htp/htp-tensor.h +++ b/ggml/src/ggml-hexagon/htp/htp-tensor.h @@ -8,27 +8,40 @@ #include "hex-common.h" #include "hex-fastdiv.h" -enum { - HTP_TENSOR_MDEV_LINE_SIZE = 128, -}; +#define HTP_TENSOR_MDEV_LINE_SIZE 128 + +// Currently HMX requires 32x32 tile formats (do not change) +#define HTP_TENSOR_TILE_N_COLS 32 +#define HTP_TENSOR_TILE_N_ROWS 32 + +#define HTP_TENSOR_TILE_SIZE_F16 2048 +#define HTP_TENSOR_TILE_SIZE_Q4_0 576 +#define HTP_TENSOR_TILE_SIZE_Q4_1 640 +#define HTP_TENSOR_TILE_SIZE_Q8_0 1088 +#define HTP_TENSOR_TILE_SIZE_IQ4_NL 576 +#define HTP_TENSOR_TILE_SIZE_MXFP4 544 +#define HTP_TENSOR_TILE_SIZE_Q4_K 640 +#define HTP_TENSOR_TILE_SIZE_Q5_K 768 +#define HTP_TENSOR_TILE_SIZE_Q6_K 896 +#define HTP_TENSOR_TILE_SIZE_Q3_K 512 +#define HTP_TENSOR_TILE_SIZE_Q2_K 336 +#define HTP_TENSOR_TILE_K_Q1_0 128 +#define HTP_TENSOR_TILE_SIZE_Q1_0 576 +#define HTP_TENSOR_TILE_K_Q2_0 64 +#define HTP_TENSOR_TILE_SIZE_Q2_0 576 + +// Tiled weight tensor layouts (Q4_0, Q8_0, IQ4_NL, MXFP4, Q1_0, Q2_0, K-quants): +// See docs/backend/snapdragon/developer.md ("Tiled Weight Formats"). struct htp_tensor_mdev_range { uint32_t start; uint32_t count; }; -static inline void * htp_tensor_data(const struct htp_tensor * t) { - return (void *) (uintptr_t) t->data; -} - static inline bool htp_tensor_is_extended(const struct htp_tensor * t) { return t && (t->data >> 32) != 0; } -static inline uint32_t * htp_tensor_flags(const struct htp_tensor * t) { - return (uint32_t *) &t->flags; -} - static inline bool htp_tensor_is_contiguous(const struct htp_tensor * t, uint32_t type_size) { uint32_t next_nb = type_size; if (t->ne[0] != 1 && t->nb[0] != next_nb) { @@ -125,19 +138,62 @@ static inline struct htp_tensor_mdev_range htp_tensor_mdev_partition(uint32_t to return range; } -static inline uint32_t htp_tensor_get_row_size(int type, uint32_t ne00) { +static inline uint32_t htp_tensor_get_tile_size(int type) { + switch (type) { + case HTP_TYPE_Q4_0: return HTP_TENSOR_TILE_SIZE_Q4_0; + case HTP_TYPE_IQ4_NL: return HTP_TENSOR_TILE_SIZE_IQ4_NL; + case HTP_TYPE_Q4_1: return HTP_TENSOR_TILE_SIZE_Q4_1; + case HTP_TYPE_Q4_K: return HTP_TENSOR_TILE_SIZE_Q4_K; + case HTP_TYPE_Q8_0: return HTP_TENSOR_TILE_SIZE_Q8_0; + case HTP_TYPE_Q5_K: return HTP_TENSOR_TILE_SIZE_Q5_K; + case HTP_TYPE_Q6_K: return HTP_TENSOR_TILE_SIZE_Q6_K; + case HTP_TYPE_Q3_K: return HTP_TENSOR_TILE_SIZE_Q3_K; + case HTP_TYPE_Q2_K: return HTP_TENSOR_TILE_SIZE_Q2_K; + case HTP_TYPE_Q1_0: return HTP_TENSOR_TILE_SIZE_Q1_0; + case HTP_TYPE_Q2_0: return HTP_TENSOR_TILE_SIZE_Q2_0; + case HTP_TYPE_MXFP4: return HTP_TENSOR_TILE_SIZE_MXFP4; + case HTP_TYPE_F16: return HTP_TENSOR_TILE_SIZE_F16; + default: return 0; + } +} + +static inline uint32_t htp_tensor_get_tile_k(int type) { switch (type) { - case HTP_TYPE_F32: return ne00 * 4; - case HTP_TYPE_F16: return ne00 * 2; - case HTP_TYPE_Q8_0: return (ne00 / 32) * 34; - case HTP_TYPE_I32: return ne00 * 4; - default: return 0; + case HTP_TYPE_Q1_0: return HTP_TENSOR_TILE_K_Q1_0; + case HTP_TYPE_Q2_0: return HTP_TENSOR_TILE_K_Q2_0; + default: return 32; } } -struct htp_context; -void htp_flush_dirty_ranges(struct htp_context * ctx); -void htp_tensor_flush_all(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n); -void htp_tensor_dirty_all(struct htp_context * ctx, const struct htp_tensor * const * tensors, uint32_t n); +static inline uint32_t htp_tensor_get_tile_padded_size(int type) { + return (htp_tensor_get_tile_size(type) + 127u) & ~127u; +} + +static inline bool htp_tensor_is_tiled(const struct htp_tensor * t) { + return t && (t->flags & HTP_TENSOR_TILED) != 0; +} + +static inline uint32_t htp_tensor_get_row_size(int type, uint32_t ne00) { + switch (type) { + case HTP_TYPE_F32: return ne00 * 4; + case HTP_TYPE_F16: + case HTP_TYPE_BF16: return ne00 * 2; + case HTP_TYPE_Q8_0: return (ne00 / 32) * 34; + case HTP_TYPE_Q4_0: + case HTP_TYPE_IQ4_NL: return (ne00 / 32) * 18; + case HTP_TYPE_Q4_1: return (ne00 / 32) * 20; + case HTP_TYPE_MXFP4: return (ne00 / 32) * 17; + case HTP_TYPE_Q2_K: return (ne00 / 256) * 84; + case HTP_TYPE_Q2_0: return (ne00 / 64) * 18; + case HTP_TYPE_Q3_K: return (ne00 / 256) * 110; + case HTP_TYPE_Q4_K: return (ne00 / 256) * 144; + case HTP_TYPE_Q5_K: return (ne00 / 256) * 176; + case HTP_TYPE_Q6_K: return (ne00 / 256) * 210; + case HTP_TYPE_Q1_0: return (ne00 / HTP_TENSOR_TILE_K_Q1_0) * 18; + case HTP_TYPE_I32: return ne00 * 4; + case HTP_TYPE_I64: return ne00 * 8; + default: return 0; + } +} #endif // HTP_TENSOR_H diff --git a/ggml/src/ggml-hexagon/htp/htp_iface.idl b/ggml/src/ggml-hexagon/htp/htp_iface.idl index 303dbfb0aa3b..6e3390ba1982 100644 --- a/ggml/src/ggml-hexagon/htp/htp_iface.idl +++ b/ggml/src/ggml-hexagon/htp/htp_iface.idl @@ -11,7 +11,7 @@ struct htp_iface_pmu_conf { }; interface htp_iface : remote_handle64 { - AEEResult start(in uint32 sess_id, in uint64 dsp_queue_id, in uint32 n_hvx, in uint32 n_hmx, in uint64 max_vmem, in uint32 power_mode); + AEEResult start(in uint32 sess_id, in uint64 dsp_queue_id, in uint32 n_hvx, in uint32 n_hmx, in uint64 vtcm_size, in uint64 max_vmem, in uint32 power_mode); AEEResult stop(); AEEResult mmap(in uint32 fd, in uint64 size); AEEResult munmap(in uint32 fd); diff --git a/ggml/src/ggml-hexagon/htp/hvx-arith.h b/ggml/src/ggml-hexagon/htp/hvx-arith.h index ab2064af3bca..ec0de8e19678 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-arith.h +++ b/ggml/src/ggml-hexagon/htp/hvx-arith.h @@ -7,6 +7,7 @@ #include #include "hvx-base.h" +#include "hvx-floor.h" #include "hex-utils.h" // @@ -676,6 +677,56 @@ static inline void hvx_step_f32_aa(uint8_t * restrict dst, const uint8_t * restr } } +static inline void hvx_sgn_f32_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + HVX_Vector * restrict vsrc = (HVX_Vector *) src; + + const uint32_t elem_size = sizeof(float); + const uint32_t epv = 128 / elem_size; + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + vdst[i] = hvx_vec_sgn_f32(vsrc[i]); + } + if (nloe) { + HVX_Vector v = hvx_vec_sgn_f32(vsrc[i]); + hvx_vec_store_a((void *) &vdst[i], nloe * elem_size, v); + } +} + +static inline void hvx_sgn_f16_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + HVX_Vector * restrict vsrc = (HVX_Vector *) src; + + const uint32_t elem_size = sizeof(_Float16); + const uint32_t epv = 128 / elem_size; + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + HVX_VectorPair p = hvx_vec_f16_to_f32(vsrc[i]); + vdst[i] = hvx_vec_f32_to_f16(hvx_vec_sgn_f32(Q6_V_lo_W(p)), hvx_vec_sgn_f32(Q6_V_hi_W(p))); + } + if (nloe) { + HVX_VectorPair p = hvx_vec_f16_to_f32(vsrc[i]); + HVX_Vector v = hvx_vec_f32_to_f16(hvx_vec_sgn_f32(Q6_V_lo_W(p)), hvx_vec_sgn_f32(Q6_V_hi_W(p))); + hvx_vec_store_a((void *) &vdst[i], nloe * elem_size, v); + } +} + static inline void hvx_step_f16_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { assert((unsigned long) dst % 128 == 0); assert((unsigned long) src % 128 == 0); @@ -700,6 +751,60 @@ static inline void hvx_step_f16_aa(uint8_t * restrict dst, const uint8_t * restr } } +// +// Ceil +// + +static inline void hvx_ceil_f32_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + HVX_Vector * restrict vsrc = (HVX_Vector *) src; + + const uint32_t elem_size = sizeof(float); + const uint32_t epv = 128 / elem_size; + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + vdst[i] = hvx_vec_ceil_f32(vsrc[i]); + } + if (nloe) { + HVX_Vector v = hvx_vec_ceil_f32(vsrc[i]); + hvx_vec_store_a((void *) &vdst[i], nloe * elem_size, v); + } +} + +static inline void hvx_ceil_f16_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { + assert((unsigned long) dst % 128 == 0); + assert((unsigned long) src % 128 == 0); + + HVX_Vector * restrict vdst = (HVX_Vector *) dst; + HVX_Vector * restrict vsrc = (HVX_Vector *) src; + + const uint32_t elem_size = sizeof(_Float16); + const uint32_t epv = 128 / elem_size; + const uint32_t nvec = n / epv; + const uint32_t nloe = n % epv; + + uint32_t i = 0; + + _Pragma("unroll(4)") + for (; i < nvec; i++) { + HVX_VectorPair p = hvx_vec_f16_to_f32(vsrc[i]); + vdst[i] = hvx_vec_f32_to_f16(hvx_vec_ceil_f32(Q6_V_lo_W(p)), hvx_vec_ceil_f32(Q6_V_hi_W(p))); + } + if (nloe) { + HVX_VectorPair p = hvx_vec_f16_to_f32(vsrc[i]); + HVX_Vector v = hvx_vec_f32_to_f16(hvx_vec_ceil_f32(Q6_V_lo_W(p)), hvx_vec_ceil_f32(Q6_V_hi_W(p))); + hvx_vec_store_a((void *) &vdst[i], nloe * elem_size, v); + } +} + // // Square // diff --git a/ggml/src/ggml-hexagon/htp/hvx-base.h b/ggml/src/ggml-hexagon/htp/hvx-base.h index 20e0d6e665cf..e87a30d14e7c 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-base.h +++ b/ggml/src/ggml-hexagon/htp/hvx-base.h @@ -118,6 +118,17 @@ static inline HVX_Vector hvx_vec_step_f32(HVX_Vector v) { return Q6_V_vmux_QVV(q, one, zero); } +static inline HVX_Vector hvx_vec_sgn_f32(HVX_Vector v) { + const HVX_Vector zero = Q6_V_vzero(); + const HVX_Vector one = hvx_vec_splat_f32(1.0f); + const HVX_Vector sign_mask = Q6_V_vsplat_R(0x80000000); + const HVX_Vector mag = hvx_vec_abs_f32(v); + const HVX_Vector signed_one = Q6_V_vor_VV(one, Q6_V_vand_VV(v, sign_mask)); + // The ordered magnitude comparison maps NaN and both signed zeros to zero. + const HVX_VectorPred nonzero = Q6_Q_vcmp_gt_VsfVsf(mag, zero); + return Q6_V_vmux_QVV(nonzero, signed_one, zero); +} + static inline HVX_Vector hvx_vec_step_f16(HVX_Vector v) { const HVX_Vector zero = Q6_V_vzero(); const HVX_Vector one = hvx_vec_splat_f16((_Float16) 1.0f); diff --git a/ggml/src/ggml-hexagon/htp/hvx-floor.h b/ggml/src/ggml-hexagon/htp/hvx-floor.h index 6a1bfde56757..6757d6184e87 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-floor.h +++ b/ggml/src/ggml-hexagon/htp/hvx-floor.h @@ -97,4 +97,12 @@ static inline HVX_Vector hvx_vec_floor_f32(HVX_Vector in_vec) { return vout; } +// ceil(x) = -floor(-x); keep +-0 as is since floor(-0) returns -1 +static inline HVX_Vector hvx_vec_ceil_f32(HVX_Vector in_vec) { + HVX_Vector vout = hvx_vec_neg_f32(hvx_vec_floor_f32(hvx_vec_neg_f32(in_vec))); + HVX_Vector vabs = Q6_V_vand_VV(in_vec, Q6_V_vsplat_R(0x7fffffff)); + HVX_VectorPred q_zero = Q6_Q_vcmp_eq_VwVw(vabs, Q6_V_vzero()); + return Q6_V_vmux_QVV(q_zero, in_vec, vout); +} + #endif /* HVX_FLOOR_H */ diff --git a/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-float.h b/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-float.h index 605892aa777c..d7488976bb19 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-float.h +++ b/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-float.h @@ -76,7 +76,7 @@ static inline void quantize_f16_f16_kernel( #define HVX_OP_MUL_F32(a, b) Q6_Vsf_vmpy_VsfVsf(a, b) #endif -static inline void vec_dot_f32_f32_aa_1x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy) { +static inline void flat_vec_dot_f32_f32_aa_1x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy) { const HVX_Vector * restrict x = (const HVX_Vector *) vx; const HVX_Vector * restrict y = (const HVX_Vector *) vy; @@ -104,7 +104,7 @@ static inline void vec_dot_f32_f32_aa_1x1(const uint32_t n, float * restrict s, *s = hvx_vec_get_f32(hvx_vec_reduce_sum_f32(rsum)); } -static inline void vec_dot_f32_f32_aa_2x1(const uint32_t n, float * restrict s0, +static inline void flat_vec_dot_f32_f32_aa_2x1(const uint32_t n, float * restrict s0, const void * restrict vx0, const void * restrict vx1, const void * restrict vy0) { const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; @@ -143,7 +143,7 @@ static inline void vec_dot_f32_f32_aa_2x1(const uint32_t n, float * restrict s0, hvx_vec_store_u(s0, 8, rsum); } -static inline void vec_dot_f32_f32_aa_2x2(const uint32_t n, float * restrict s0, float * restrict s1, +static inline void flat_vec_dot_f32_f32_aa_2x2(const uint32_t n, float * restrict s0, float * restrict s1, const void * restrict vx0, const void * restrict vx1, const void * restrict vy0, const void * restrict vy1) { const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; @@ -196,10 +196,203 @@ static inline void vec_dot_f32_f32_aa_2x2(const uint32_t n, float * restrict s0, hvx_vec_store_u(s1, 8, r0_r1_c1_sum); } +static inline void flat_vec_dot_bf16_f32_aa_1x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy) { + const HVX_Vector * restrict x = (const HVX_Vector *) vx; + const HVX_Vector * restrict y = (const HVX_Vector *) vy; + + uint32_t nvec = n / 64; + uint32_t rem = n % 64; + + HVX_Vector rsum0 = Q6_V_vzero(); + HVX_Vector rsum1 = Q6_V_vzero(); + + uint32_t i = 0; + #pragma unroll(2) + for (i = 0; i < nvec; i++) { + HVX_Vector v_bf16 = x[i]; + HVX_VectorPair p = Q6_Ww_vunpack_Vh(v_bf16); + HVX_Vector w0_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p), 16); + HVX_Vector w1_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p), 16); + + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w0_f32, y[2 * i + 0])); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w1_f32, y[2 * i + 1])); + } + + if (rem) { + HVX_VectorPred bmask = Q6_Q_vsetq2_R(rem * 2); + HVX_Vector v_bf16 = Q6_V_vand_QV(bmask, x[i]); + HVX_VectorPair p = Q6_Ww_vunpack_Vh(v_bf16); + HVX_Vector w0_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p), 16); + HVX_Vector w1_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p), 16); + + if (rem <= 32) { + HVX_VectorPred a_mask = Q6_Q_vsetq2_R(rem * 4); + HVX_Vector y0 = Q6_V_vand_QV(a_mask, y[2 * i + 0]); + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w0_f32, y0)); + } else { + HVX_Vector y0 = y[2 * i + 0]; + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w0_f32, y0)); + + HVX_VectorPred a_mask = Q6_Q_vsetq2_R((rem - 32) * 4); + HVX_Vector y1 = Q6_V_vand_QV(a_mask, y[2 * i + 1]); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w1_f32, y1)); + } + } + + HVX_Vector rsum = HVX_OP_ADD_F32(rsum0, rsum1); + *s = hvx_vec_get_f32(hvx_vec_reduce_sum_f32(rsum)); +} + +static inline void flat_vec_dot_bf16_f32_aa_2x1(const uint32_t n, float * restrict s0, + const void * restrict vx0, const void * restrict vx1, + const void * restrict vy0) { + const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; + const HVX_Vector * restrict x1 = (const HVX_Vector *) vx1; + const HVX_Vector * restrict y = (const HVX_Vector *) vy0; + + uint32_t nvec = n / 64; + uint32_t rem = n % 64; + + HVX_Vector rsum0 = Q6_V_vzero(); + HVX_Vector rsum1 = Q6_V_vzero(); + + uint32_t i = 0; + #pragma unroll(2) + for (i = 0; i < nvec; i++) { + HVX_VectorPair p0 = Q6_Ww_vunpack_Vh(x0[i]); + HVX_VectorPair p1 = Q6_Ww_vunpack_Vh(x1[i]); + HVX_Vector w00_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p0), 16); + HVX_Vector w01_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p0), 16); + HVX_Vector w10_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p1), 16); + HVX_Vector w11_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p1), 16); + + HVX_Vector y0 = y[2 * i + 0]; + HVX_Vector y1 = y[2 * i + 1]; + + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w00_f32, y0)); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w10_f32, y0)); + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w01_f32, y1)); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w11_f32, y1)); + } + + if (rem) { + HVX_VectorPred bmask = Q6_Q_vsetq2_R(rem * 2); + HVX_VectorPair p0 = Q6_Ww_vunpack_Vh(Q6_V_vand_QV(bmask, x0[i])); + HVX_VectorPair p1 = Q6_Ww_vunpack_Vh(Q6_V_vand_QV(bmask, x1[i])); + HVX_Vector w00_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p0), 16); + HVX_Vector w01_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p0), 16); + HVX_Vector w10_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p1), 16); + HVX_Vector w11_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p1), 16); + + if (rem <= 32) { + HVX_VectorPred a_mask = Q6_Q_vsetq2_R(rem * 4); + HVX_Vector y0 = Q6_V_vand_QV(a_mask, y[2 * i + 0]); + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w00_f32, y0)); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w10_f32, y0)); + } else { + HVX_Vector y0 = y[2 * i + 0]; + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w00_f32, y0)); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w10_f32, y0)); + + HVX_VectorPred a_mask = Q6_Q_vsetq2_R((rem - 32) * 4); + HVX_Vector y1 = Q6_V_vand_QV(a_mask, y[2 * i + 1]); + rsum0 = HVX_OP_ADD_F32(rsum0, HVX_OP_MUL_F32(w01_f32, y1)); + rsum1 = HVX_OP_ADD_F32(rsum1, HVX_OP_MUL_F32(w11_f32, y1)); + } + } + + HVX_Vector rsum = hvx_vec_reduce_sum_f32x2(rsum0, rsum1); + hvx_vec_store_u(s0, 8, rsum); +} + +static inline void flat_vec_dot_bf16_f32_aa_2x2(const uint32_t n, float * restrict s0, float * restrict s1, + const void * restrict vx0, const void * restrict vx1, + const void * restrict vy0, const void * restrict vy1) { + const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; + const HVX_Vector * restrict x1 = (const HVX_Vector *) vx1; + const HVX_Vector * restrict y0 = (const HVX_Vector *) vy0; + const HVX_Vector * restrict y1 = (const HVX_Vector *) vy1; + + uint32_t nvec = n / 64; + uint32_t rem = n % 64; + + HVX_Vector r0_c0_sum = Q6_V_vzero(); + HVX_Vector r0_c1_sum = Q6_V_vzero(); + HVX_Vector r1_c0_sum = Q6_V_vzero(); + HVX_Vector r1_c1_sum = Q6_V_vzero(); + + uint32_t i = 0; + #pragma unroll(2) + for (i = 0; i < nvec; i++) { + HVX_VectorPair p0 = Q6_Ww_vunpack_Vh(x0[i]); + HVX_VectorPair p1 = Q6_Ww_vunpack_Vh(x1[i]); + HVX_Vector w00_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p0), 16); + HVX_Vector w01_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p0), 16); + HVX_Vector w10_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p1), 16); + HVX_Vector w11_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p1), 16); + + HVX_Vector c0_0 = y0[2 * i + 0]; + HVX_Vector c0_1 = y0[2 * i + 1]; + HVX_Vector c1_0 = y1[2 * i + 0]; + HVX_Vector c1_1 = y1[2 * i + 1]; + + r0_c0_sum = HVX_OP_ADD_F32(r0_c0_sum, HVX_OP_MUL_F32(w00_f32, c0_0)); + r0_c1_sum = HVX_OP_ADD_F32(r0_c1_sum, HVX_OP_MUL_F32(w00_f32, c1_0)); + r1_c0_sum = HVX_OP_ADD_F32(r1_c0_sum, HVX_OP_MUL_F32(w10_f32, c0_0)); + r1_c1_sum = HVX_OP_ADD_F32(r1_c1_sum, HVX_OP_MUL_F32(w10_f32, c1_0)); + + r0_c0_sum = HVX_OP_ADD_F32(r0_c0_sum, HVX_OP_MUL_F32(w01_f32, c0_1)); + r0_c1_sum = HVX_OP_ADD_F32(r0_c1_sum, HVX_OP_MUL_F32(w01_f32, c1_1)); + r1_c0_sum = HVX_OP_ADD_F32(r1_c0_sum, HVX_OP_MUL_F32(w11_f32, c0_1)); + r1_c1_sum = HVX_OP_ADD_F32(r1_c1_sum, HVX_OP_MUL_F32(w11_f32, c1_1)); + } + + if (rem) { + HVX_VectorPred bmask = Q6_Q_vsetq2_R(rem * 2); + HVX_VectorPair p0 = Q6_Ww_vunpack_Vh(Q6_V_vand_QV(bmask, x0[i])); + HVX_VectorPair p1 = Q6_Ww_vunpack_Vh(Q6_V_vand_QV(bmask, x1[i])); + HVX_Vector w00_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p0), 16); + HVX_Vector w01_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p0), 16); + HVX_Vector w10_f32 = Q6_Vw_vasl_VwR(Q6_V_lo_W(p1), 16); + HVX_Vector w11_f32 = Q6_Vw_vasl_VwR(Q6_V_hi_W(p1), 16); + + if (rem <= 32) { + HVX_VectorPred a_mask = Q6_Q_vsetq2_R(rem * 4); + HVX_Vector c0_0 = Q6_V_vand_QV(a_mask, y0[2 * i + 0]); + HVX_Vector c1_0 = Q6_V_vand_QV(a_mask, y1[2 * i + 0]); + r0_c0_sum = HVX_OP_ADD_F32(r0_c0_sum, HVX_OP_MUL_F32(w00_f32, c0_0)); + r0_c1_sum = HVX_OP_ADD_F32(r0_c1_sum, HVX_OP_MUL_F32(w00_f32, c1_0)); + r1_c0_sum = HVX_OP_ADD_F32(r1_c0_sum, HVX_OP_MUL_F32(w10_f32, c0_0)); + r1_c1_sum = HVX_OP_ADD_F32(r1_c1_sum, HVX_OP_MUL_F32(w10_f32, c1_0)); + } else { + HVX_Vector c0_0 = y0[2 * i + 0]; + HVX_Vector c1_0 = y1[2 * i + 0]; + r0_c0_sum = HVX_OP_ADD_F32(r0_c0_sum, HVX_OP_MUL_F32(w00_f32, c0_0)); + r0_c1_sum = HVX_OP_ADD_F32(r0_c1_sum, HVX_OP_MUL_F32(w00_f32, c1_0)); + r1_c0_sum = HVX_OP_ADD_F32(r1_c0_sum, HVX_OP_MUL_F32(w10_f32, c0_0)); + r1_c1_sum = HVX_OP_ADD_F32(r1_c1_sum, HVX_OP_MUL_F32(w10_f32, c1_0)); + + HVX_VectorPred a_mask = Q6_Q_vsetq2_R((rem - 32) * 4); + HVX_Vector c0_1 = Q6_V_vand_QV(a_mask, y0[2 * i + 1]); + HVX_Vector c1_1 = Q6_V_vand_QV(a_mask, y1[2 * i + 1]); + r0_c0_sum = HVX_OP_ADD_F32(r0_c0_sum, HVX_OP_MUL_F32(w01_f32, c0_1)); + r0_c1_sum = HVX_OP_ADD_F32(r0_c1_sum, HVX_OP_MUL_F32(w01_f32, c1_1)); + r1_c0_sum = HVX_OP_ADD_F32(r1_c0_sum, HVX_OP_MUL_F32(w11_f32, c0_1)); + r1_c1_sum = HVX_OP_ADD_F32(r1_c1_sum, HVX_OP_MUL_F32(w11_f32, c1_1)); + } + } + + HVX_Vector r0_r1_c0_sum = hvx_vec_reduce_sum_f32x2(r0_c0_sum, r1_c0_sum); + HVX_Vector r0_r1_c1_sum = hvx_vec_reduce_sum_f32x2(r0_c1_sum, r1_c1_sum); + + hvx_vec_store_u(s0, 8, r0_r1_c0_sum); + hvx_vec_store_u(s1, 8, r0_r1_c1_sum); +} + #undef HVX_OP_ADD_F32 #undef HVX_OP_MUL_F32 -static inline void vec_dot_f16_f16_aa_1x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy) { +static inline void flat_vec_dot_f16_f16_aa_1x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy) { const HVX_Vector * restrict x = (const HVX_Vector *) vx; const HVX_Vector * restrict y = (const HVX_Vector *) vy; @@ -226,7 +419,7 @@ static inline void vec_dot_f16_f16_aa_1x1(const uint32_t n, float * restrict s, hvx_vec_store_u(s, 4, hvx_vec_reduce_sum_f32(rsum)); } -static inline void vec_dot_f16_f16_aa_2x1(const uint32_t n, float * restrict s0, +static inline void flat_vec_dot_f16_f16_aa_2x1(const uint32_t n, float * restrict s0, const void * restrict vx0, const void * restrict vx1, const void * restrict vy0) { const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; @@ -263,7 +456,7 @@ static inline void vec_dot_f16_f16_aa_2x1(const uint32_t n, float * restrict s0, hvx_vec_store_u(s0, 8, rsum); } -static inline void vec_dot_f16_f16_aa_2x2(const uint32_t n, float * restrict s0, float * restrict s1, +static inline void flat_vec_dot_f16_f16_aa_2x2(const uint32_t n, float * restrict s0, float * restrict s1, const void * restrict vx0, const void * restrict vx1, const void * restrict vy0, const void * restrict vy1) { const HVX_Vector * restrict x0 = (const HVX_Vector *) vx0; diff --git a/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-tiled.h b/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-tiled.h index 0c86e407efe7..01c671679664 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-tiled.h +++ b/ggml/src/ggml-hexagon/htp/hvx-mm-kernels-tiled.h @@ -29,29 +29,27 @@ static inline void quantize_block_f32_q8_1_tiled_impl(float * restrict x, uint8_ HVX_Vector vx0_qf = Q6_Vqf32_vsub_VsfVsf(vx[0], zero); HVX_Vector vx1_qf = Q6_Vqf32_vsub_VsfVsf(vx[1], zero); - HVX_Vector vx2_qf = Q6_Vqf32_vsub_VsfVsf(vx[2], zero); - HVX_Vector vx3_qf = Q6_Vqf32_vsub_VsfVsf(vx[3], zero); - HVX_Vector vmax0_qf = Q6_Vqf32_vsub_VsfVsf(vmax0_sf, zero); HVX_Vector vmax1_qf = Q6_Vqf32_vsub_VsfVsf(vmax1_sf, zero); - HVX_Vector vmax2_qf = Q6_Vqf32_vsub_VsfVsf(vmax2_sf, zero); - HVX_Vector vmax3_qf = Q6_Vqf32_vsub_VsfVsf(vmax3_sf, zero); - HVX_Vector vmax01_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vmax1_qf, vmax0_qf))); - HVX_Vector vmax23_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vmax3_qf, vmax2_qf))); - - HVX_Vector vx01_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vx1_qf, vx0_qf))); - HVX_Vector vx23_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vx3_qf, vx2_qf))); + HVX_Vector vmax01_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vmax1_qf, vmax0_qf))); + HVX_Vector vx01_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vx1_qf, vx0_qf))); + HVX_Vector vd01_qf16 = Q6_Vqf16_vmpy_VhfVhf(vmax01_hf, Q6_Vh_vsplat_R(0x2008)); // 1.0 / 127.0 + HVX_Vector vd01_hf = Q6_Vhf_equals_Vqf16(vd01_qf16); + HVX_Vector vd01_inv_hf = hvx_vec_inverse_f16(vd01_hf); + vx01_hf = Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(vx01_hf, vd01_inv_hf)); - HVX_Vector vd01_qf16 = Q6_Vqf16_vmpy_VhfVhf(vmax01_hf, Q6_Vh_vsplat_R(0x2008)); // 1.0 / 127.0 - HVX_Vector vd23_qf16 = Q6_Vqf16_vmpy_VhfVhf(vmax23_hf, Q6_Vh_vsplat_R(0x2008)); // 1.0 / 127.0 - HVX_Vector vd01_hf = Q6_Vhf_equals_Vqf16(vd01_qf16); - HVX_Vector vd23_hf = Q6_Vhf_equals_Vqf16(vd23_qf16); + HVX_Vector vx2_qf = Q6_Vqf32_vsub_VsfVsf(vx[2], zero); + HVX_Vector vx3_qf = Q6_Vqf32_vsub_VsfVsf(vx[3], zero); + HVX_Vector vmax2_qf = Q6_Vqf32_vsub_VsfVsf(vmax2_sf, zero); + HVX_Vector vmax3_qf = Q6_Vqf32_vsub_VsfVsf(vmax3_sf, zero); - HVX_Vector vd01_inv_hf = hvx_vec_inverse_f16(vd01_hf); + HVX_Vector vmax23_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vmax3_qf, vmax2_qf))); + HVX_Vector vx23_hf = Q6_Vh_vdeal_Vh(Q6_Vhf_equals_Wqf32(Q6_W_vcombine_VV(vx3_qf, vx2_qf))); + HVX_Vector vd23_qf16 = Q6_Vqf16_vmpy_VhfVhf(vmax23_hf, Q6_Vh_vsplat_R(0x2008)); // 1.0 / 127.0 + HVX_Vector vd23_hf = Q6_Vhf_equals_Vqf16(vd23_qf16); HVX_Vector vd23_inv_hf = hvx_vec_inverse_f16(vd23_hf); - vx01_hf = Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(vx01_hf, vd01_inv_hf)); - vx23_hf = Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(vx23_hf, vd23_inv_hf)); + vx23_hf = Q6_Vhf_equals_Vqf16(Q6_Vqf16_vmpy_VhfVhf(vx23_hf, vd23_inv_hf)); HVX_Vector vx01_i16 = hvx_vec_i16_from_hf_rnd_sat(vx01_hf); HVX_Vector vx23_i16 = hvx_vec_i16_from_hf_rnd_sat(vx23_hf); @@ -81,25 +79,10 @@ static inline void quantize_block_f32_q8_1_tiled_impl(float * restrict x, uint8_ HVX_Vector voff01_hf = hvx_vec_f32_to_f16(voff0_sf, voff1_sf); HVX_Vector voff23_hf = hvx_vec_f32_to_f16(voff2_sf, voff3_sf); - HVX_Vector r_scale[4] = { - hvx_vec_repl_f16(vd01_hf), - hvx_vec_repl_f16(Q6_V_vror_VR(vd01_hf, 64)), - hvx_vec_repl_f16(vd23_hf), - hvx_vec_repl_f16(Q6_V_vror_VR(vd23_hf, 64)), - }; - HVX_Vector r_offset[4] = { - hvx_vec_repl_f16(voff01_hf), - hvx_vec_repl_f16(Q6_V_vror_VR(voff01_hf, 64)), - hvx_vec_repl_f16(voff23_hf), - hvx_vec_repl_f16(Q6_V_vror_VR(voff23_hf, 64)), - }; + int32_t __attribute__((aligned(128))) ws[32]; if (sums16) { // |sum of 16 int8| <= 2032 fits a halfword - int32_t __attribute__((aligned(128))) ws[32]; *(HVX_Vector *) ws = v_sums; - for (int b = 0; b < 4; b++) { - r_offset[b] = Q6_V_vsplat_R(((uint32_t) ws[8 * b + 4] << 16) | ((uint32_t) ws[8 * b] & 0xFFFF)); - } } static const uint8_t __attribute__((aligned(128))) repl[128] = { @@ -114,8 +97,15 @@ static inline void quantize_block_f32_q8_1_tiled_impl(float * restrict x, uint8_ }; HVX_Vector v_repl_ctrl = * (const HVX_Vector *) repl; + #pragma unroll for (int b = 0; b < 4; b++) { HVX_Vector v_act = Q6_V_vror_VR(vx_i8, b * 32); + HVX_Vector vd_b = (b < 2) ? vd01_hf : vd23_hf; + HVX_Vector voff_b = (b < 2) ? voff01_hf : voff23_hf; + HVX_Vector r_scale = hvx_vec_repl_f16((b & 1) ? Q6_V_vror_VR(vd_b, 64) : vd_b); + HVX_Vector r_offset = sums16 + ? Q6_V_vsplat_R(((uint32_t) ws[8 * b + 4] << 16) | ((uint32_t) ws[8 * b] & 0xFFFF)) + : hvx_vec_repl_f16((b & 1) ? Q6_V_vror_VR(voff_b, 64) : voff_b); HVX_Vector r0 = Q6_V_vdelta_VV(v_act, v_repl_ctrl); HVX_Vector r1 = Q6_V_vdelta_VV(Q6_V_vror_VR(v_act, 4), v_repl_ctrl); @@ -135,8 +125,8 @@ static inline void quantize_block_f32_q8_1_tiled_impl(float * restrict x, uint8_ dst[5] = r5; dst[6] = r6; dst[7] = r7; - dst[8] = r_scale[b]; - dst[9] = r_offset[b]; + dst[8] = r_scale; + dst[9] = r_offset; } } @@ -243,7 +233,7 @@ static inline void quantize_block_f32_q8_0_tiled(float * restrict x, uint8_t * r static void quantize_row_f32_q8_0_tiled(float * restrict x, uint8_t * restrict y, uint32_t k) { assert(k % 32 == 0); - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (k + qk - 1) / qk; for (uint32_t i = 0; i < nb; i++) { @@ -254,7 +244,7 @@ static void quantize_row_f32_q8_0_tiled(float * restrict x, uint8_t * restrict y static void quantize_row_f32_q8_1_tiled(float * restrict x, uint8_t * restrict y, uint32_t k) { assert(k % 32 == 0); - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (k + qk - 1) / qk; for (uint32_t i = 0; i < nb; i++) { @@ -265,7 +255,7 @@ static void quantize_row_f32_q8_1_tiled(float * restrict x, uint8_t * restrict y static void quantize_row_f32_q8_1_s16_tiled(float * restrict x, uint8_t * restrict y, uint32_t k) { assert(k % 32 == 0); - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (k + qk - 1) / qk; for (uint32_t i = 0; i < nb; i++) { @@ -274,6 +264,72 @@ static void quantize_row_f32_q8_1_s16_tiled(float * restrict x, uint8_t * restri } } +static inline void quantize_half_f16_tiled_splat(HVX_Vector v_src, HVX_Vector * restrict dst) { + static const uint8_t __attribute__((aligned(128))) repl[128] = { + 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x10, 0x10, 0x10, 0x10, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x20, 0x20, 0x20, 0x20, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x10, 0x10, 0x10, 0x10, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x10, 0x10, 0x10, 0x10, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x20, 0x20, 0x20, 0x20, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + 0x10, 0x10, 0x10, 0x10, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04, + }; + HVX_Vector v_repl_ctrl = *(const HVX_Vector *) repl; + + #pragma unroll(4) + for (int cp = 0; cp < 32; cp++) { + dst[cp] = Q6_V_vdelta_VV(cp == 0 ? v_src : Q6_V_vror_VR(v_src, cp * 4), v_repl_ctrl); + } +} + +static inline void quantize_block_f32_f16_tiled(const float * restrict x, uint8_t * restrict y_block) { + assert((unsigned long) x % 128 == 0); + assert((unsigned long) y_block % 128 == 0); + + const HVX_Vector * vx = (const HVX_Vector *) x; + HVX_Vector * restrict dst = (HVX_Vector *) y_block; + + HVX_Vector vx01_hf = hvx_vec_f32_to_f16(vx[0], vx[1]); + quantize_half_f16_tiled_splat(vx01_hf, dst); + + HVX_Vector vx23_hf = hvx_vec_f32_to_f16(vx[2], vx[3]); + quantize_half_f16_tiled_splat(vx23_hf, dst + 32); +} + +static inline void quantize_block_f16_f16_tiled(const __fp16 * restrict x, uint8_t * restrict y_block) { + assert((unsigned long) x % 128 == 0); + assert((unsigned long) y_block % 128 == 0); + + const HVX_Vector * vx = (const HVX_Vector *) x; + HVX_Vector * restrict dst = (HVX_Vector *) y_block; + + quantize_half_f16_tiled_splat(vx[0], dst); + quantize_half_f16_tiled_splat(vx[1], dst + 32); +} + +static void quantize_row_f32_f16_tiled(const float * restrict x, uint8_t * restrict y, uint32_t k) { + assert(k % 32 == 0); + const uint32_t qk = HTP_MM_ACT_BLOCK_K; + const uint32_t nb = (k + qk - 1) / qk; + + for (uint32_t i = 0; i < nb; i++) { + uint8_t * restrict y_block = y + i * 4 * 2048; + quantize_block_f32_f16_tiled(x + i * qk, y_block); + } +} + +static void quantize_row_f16_f16_tiled(const __fp16 * restrict x, uint8_t * restrict y, uint32_t k) { + assert(k % 32 == 0); + const uint32_t qk = HTP_MM_ACT_BLOCK_K; + const uint32_t nb = (k + qk - 1) / qk; + + for (uint32_t i = 0; i < nb; i++) { + uint8_t * restrict y_block = y + i * 4 * 2048; + quantize_block_f16_f16_tiled(x + i * qk, y_block); + } +} + // Dot kernels & helpers that consume tiled activations static inline HVX_Vector hvx_vec_mul_f16_f16_to_f32_lower32(HVX_Vector v1, HVX_Vector v2) { @@ -329,6 +385,36 @@ static inline HVX_VectorPair unpack_and_interleave_4bit_x2(HVX_Vector v_src, HVX return Q6_W_vcombine_VV(v_W1, v_W0); } +static inline HVX_Vector unpack_q1_0_group( + HVX_Vector v_plane, + int g, + HVX_Vector v_neg_one, + HVX_Vector v_pos_one +) { + HVX_VectorPred q = Q6_Q_vand_VR(v_plane, 0x01010101u << g); + return Q6_V_vmux_QVV(q, v_pos_one, v_neg_one); +} + +static inline HVX_Vector accum_q1_0_32x1( + HVX_Vector v_plane, + const HVX_Vector * restrict v_act, + HVX_Vector v_neg_one, + HVX_Vector v_pos_one +) { + HVX_Vector v_sum_lo = Q6_V_vzero(); + HVX_Vector v_sum_hi = Q6_V_vzero(); + + #pragma unroll + for (int g = 0; g < 4; g++) { + HVX_Vector v_W_lo = unpack_q1_0_group(v_plane, g, v_neg_one, v_pos_one); + HVX_Vector v_W_hi = unpack_q1_0_group(v_plane, g + 4, v_neg_one, v_pos_one); + v_sum_lo = Q6_Vw_vrmpyacc_VwVbVb(v_sum_lo, v_W_lo, v_act[g]); + v_sum_hi = Q6_Vw_vrmpyacc_VwVbVb(v_sum_hi, v_W_hi, v_act[g + 4]); + } + + return Q6_Vw_vadd_VwVw(v_sum_lo, v_sum_hi); +} + static inline HVX_Vector accum_4bit_32x1( const HVX_Vector * restrict vptr, const HVX_Vector * restrict v_act, @@ -371,6 +457,33 @@ static inline HVX_Vector accum_4bit_32x1_lut( return Q6_Vw_vadd_VwVw(v_sum0, v_sum1); } +static inline HVX_VectorPair accum_q1_0_32x2( + HVX_Vector v_plane, + const HVX_Vector * restrict v_act0, + const HVX_Vector * restrict v_act1, + HVX_Vector v_neg_one, + HVX_Vector v_pos_one +) { + HVX_Vector v_sum0_lo = Q6_V_vzero(); + HVX_Vector v_sum0_hi = Q6_V_vzero(); + HVX_Vector v_sum1_lo = Q6_V_vzero(); + HVX_Vector v_sum1_hi = Q6_V_vzero(); + + #pragma unroll + for (int g = 0; g < 4; g++) { + HVX_Vector v_W_lo = unpack_q1_0_group(v_plane, g, v_neg_one, v_pos_one); + HVX_Vector v_W_hi = unpack_q1_0_group(v_plane, g + 4, v_neg_one, v_pos_one); + v_sum0_lo = Q6_Vw_vrmpyacc_VwVbVb(v_sum0_lo, v_W_lo, v_act0[g]); + v_sum0_hi = Q6_Vw_vrmpyacc_VwVbVb(v_sum0_hi, v_W_hi, v_act0[g + 4]); + v_sum1_lo = Q6_Vw_vrmpyacc_VwVbVb(v_sum1_lo, v_W_lo, v_act1[g]); + v_sum1_hi = Q6_Vw_vrmpyacc_VwVbVb(v_sum1_hi, v_W_hi, v_act1[g + 4]); + } + + return Q6_W_vcombine_VV( + Q6_Vw_vadd_VwVw(v_sum1_lo, v_sum1_hi), + Q6_Vw_vadd_VwVw(v_sum0_lo, v_sum0_hi)); +} + static inline HVX_VectorPair accum_4bit_32x2( const HVX_Vector * restrict vptr, const HVX_Vector * restrict v_act0, @@ -454,7 +567,7 @@ static inline HVX_VectorPair accum_q8_0_32x2( return Q6_W_vcombine_VV(v_sum1, v_sum0); } -// Q5_K: OR 0x10 into every lane of v whose flag j is set in the plane (see HTP_MM_WEIGHT_TILE_SIZE_Q5_K) +// Q5_K: OR 0x10 into every lane of v whose flag j is set in the plane (see HTP_TENSOR_TILE_SIZE_Q5_K) static inline HVX_Vector hvx_q5k_or_hibit(HVX_Vector v, HVX_Vector v_plane, int j) { HVX_VectorPred q = Q6_Q_vand_VR(v_plane, 0x01010101u << j); return Q6_V_vandor_VQR(v, q, 0x10101010); @@ -526,7 +639,7 @@ static inline HVX_VectorPair accum_5bit_32x2( return Q6_W_vcombine_VV(v_sum1, v_sum0); } -// Q6_K weights are stored unsigned (0..63), see HTP_MM_WEIGHT_TILE_SIZE_Q6_K. Unpack k-group g of a tile to signed bytes (q - 32) +// Q6_K weights are stored unsigned (0..63), see HTP_TENSOR_TILE_SIZE_Q6_K. Unpack k-group g of a tile to signed bytes (q - 32) static inline HVX_Vector unpack_q6_k_group(const HVX_Vector * restrict vptr, int g, HVX_Vector mask_0f, HVX_Vector mask_03, HVX_Vector i32) { HVX_Vector v_lo = (g & 1) ? Q6_Vub_vlsr_VubR(vptr[g >> 1], 4) : Q6_V_vand_VV(vptr[g >> 1], mask_0f); HVX_Vector v_hi = (g & 3) ? Q6_Vub_vlsr_VubR(vptr[4 + (g >> 2)], 2 * (g & 3)) : vptr[4 + (g >> 2)]; @@ -593,7 +706,7 @@ static inline HVX_Vector scale_q6_k_32x1(HVX_VectorPair v_sums, HVX_Vector v_sca return hvx_vec_add_f32_f32(v_lo, v_hi); } -// Q3_K / Q2_K: low 2 bits of k-group g, see HTP_MM_WEIGHT_TILE_SIZE_Q3_K +// Q3_K / Q2_K: low 2 bits of k-group g, see HTP_TENSOR_TILE_SIZE_Q3_K static inline HVX_Vector unpack_q3_k_low2(const HVX_Vector * restrict vptr, int g, HVX_Vector mask_03) { HVX_Vector v = vptr[g >> 2]; if ((g & 3) == 3) { @@ -705,6 +818,53 @@ static inline void accum_q2_k_32x2( *v_sums1 = Q6_W_vcombine_VV(v_sum1_hi, v_sum1_lo); } +// Q2_0: unsigned codes 0..3; the -1 offset is applied via the Q8_1 block sum (v_act[9]) +static inline HVX_Vector accum_q2_0_32x1( + const HVX_Vector * restrict vptr, + const HVX_Vector * restrict v_act +) { + HVX_Vector v_sum_lo = Q6_V_vzero(); + HVX_Vector v_sum_hi = Q6_V_vzero(); + HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + + #pragma unroll + for (int g = 0; g < 4; g++) { + HVX_Vector v_W_lo = unpack_q3_k_low2(vptr, g, mask_03); + HVX_Vector v_W_hi = unpack_q3_k_low2(vptr, g + 4, mask_03); + v_sum_lo = Q6_Vw_vrmpyacc_VwVubVb(v_sum_lo, v_W_lo, v_act[g]); + v_sum_hi = Q6_Vw_vrmpyacc_VwVubVb(v_sum_hi, v_W_hi, v_act[g + 4]); + } + + return Q6_Vw_vadd_VwVw(v_sum_lo, v_sum_hi); +} + +static inline void accum_q2_0_32x2( + const HVX_Vector * restrict vptr, + const HVX_Vector * restrict v_act0, + const HVX_Vector * restrict v_act1, + HVX_Vector * v_sum0, + HVX_Vector * v_sum1 +) { + HVX_Vector v_sum0_lo = Q6_V_vzero(); + HVX_Vector v_sum0_hi = Q6_V_vzero(); + HVX_Vector v_sum1_lo = Q6_V_vzero(); + HVX_Vector v_sum1_hi = Q6_V_vzero(); + HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + + #pragma unroll + for (int g = 0; g < 4; g++) { + HVX_Vector v_W_lo = unpack_q3_k_low2(vptr, g, mask_03); + HVX_Vector v_W_hi = unpack_q3_k_low2(vptr, g + 4, mask_03); + v_sum0_lo = Q6_Vw_vrmpyacc_VwVubVb(v_sum0_lo, v_W_lo, v_act0[g]); + v_sum0_hi = Q6_Vw_vrmpyacc_VwVubVb(v_sum0_hi, v_W_hi, v_act0[g + 4]); + v_sum1_lo = Q6_Vw_vrmpyacc_VwVubVb(v_sum1_lo, v_W_lo, v_act1[g]); + v_sum1_hi = Q6_Vw_vrmpyacc_VwVubVb(v_sum1_hi, v_W_hi, v_act1[g + 4]); + } + + *v_sum0 = Q6_Vw_vadd_VwVw(v_sum0_lo, v_sum0_hi); + *v_sum1 = Q6_Vw_vadd_VwVw(v_sum1_lo, v_sum1_hi); +} + // Q2_K: fp16 d (*v_d) and -dmin (*v_m) of the 32 rows of a super-block (8 tiles, VTCM stride 384), each in both vector halves static inline void q2_k_load_dmin(const uint8_t * restrict sb, HVX_Vector * restrict v_d, HVX_Vector * restrict v_m) { HVX_Vector v_dd = Q6_V_vzero(); // lanes 0..31: d, lanes 32..63: -dmin @@ -758,6 +918,89 @@ static inline HVX_Vector q2_k_int_scale(HVX_Vector v_isum, HVX_Vector v_msum, HV return hvx_vec_mul_f32_f32(v_t, v_da32); } +static void tiled_vec_dot_q1_0_32x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy, uint32_t valid_rows, const float * restrict sz) { + const uint8_t * restrict tile_ptr = vx; + const uint8_t * restrict y_q = vy; + + HVX_Vector v_sum_qf = Q6_V_vzero(); + HVX_Vector v_neg_one = Q6_Vb_vsplat_R(-1); + HVX_Vector v_pos_one = Q6_Vb_vsplat_R(1); + + const uint32_t n_k_tiles = n / HTP_TENSOR_TILE_K_Q1_0; + for (uint32_t kt = 0; kt < n_k_tiles; kt++) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) (tile_ptr + kt * htp_tensor_get_tile_padded_size(HTP_TYPE_Q1_0)); + HVX_Vector v_tile_qf = Q6_V_vzero(); + + #pragma unroll + for (int quarter = 0; quarter < 4; quarter++) { + const HVX_Vector * restrict v_act = (const HVX_Vector *) (y_q + (4 * kt + quarter) * HTP_MM_ACT_TILE_SIZE_Q8_0); + HVX_Vector v_sum_sf = Q6_Vsf_equals_Vw(accum_q1_0_32x1(vptr[quarter], v_act, v_neg_one, v_pos_one)); + HVX_Vector v_da_sf = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act[8])); + HVX_Vector v_q_qf = Q6_Vqf32_vmpy_VsfVsf(v_sum_sf, v_da_sf); + v_tile_qf = (quarter == 0) ? v_q_qf : Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf, v_q_qf); + } + + HVX_Vector v_dw_sf = Q6_V_lo_W(hvx_vec_f16_to_f32(vptr[4])); + v_sum_qf = Q6_Vqf32_vadd_Vqf32Vqf32(v_sum_qf, Q6_Vqf32_vmpy_VsfVsf(Q6_Vsf_equals_Vqf32(v_tile_qf), v_dw_sf)); + } + + HVX_Vector v_sum_float = Q6_Vsf_equals_Vqf32(v_sum_qf); + if (sz) { + hvx_vec_store_u(s, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float, hvx_vmemu(sz))); + } else { + hvx_vec_store_u(s, valid_rows * sizeof(float), v_sum_float); + } +} + +static void tiled_vec_dot_q1_0_32x2(const uint32_t n, float * restrict s0, float * restrict s1, const void * restrict vx, const void * restrict vy0, const void * restrict vy1, uint32_t valid_rows, const float * restrict sz0, const float * restrict sz1) { + const uint8_t * restrict tile_ptr = vx; + const uint8_t * restrict y0_q = vy0; + const uint8_t * restrict y1_q = vy1; + + HVX_Vector v_sum_qf_c0 = Q6_V_vzero(); + HVX_Vector v_sum_qf_c1 = Q6_V_vzero(); + HVX_Vector v_neg_one = Q6_Vb_vsplat_R(-1); + HVX_Vector v_pos_one = Q6_Vb_vsplat_R(1); + + const uint32_t n_k_tiles = n / HTP_TENSOR_TILE_K_Q1_0; + for (uint32_t kt = 0; kt < n_k_tiles; kt++) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) (tile_ptr + kt * htp_tensor_get_tile_padded_size(HTP_TYPE_Q1_0)); + HVX_Vector v_tile_qf_c0 = Q6_V_vzero(); + HVX_Vector v_tile_qf_c1 = Q6_V_vzero(); + + for (int quarter = 0; quarter < 4; quarter++) { + const uint32_t act_tile = 4 * kt + quarter; + const HVX_Vector * restrict v_act0 = (const HVX_Vector *) (y0_q + act_tile * HTP_MM_ACT_TILE_SIZE_Q8_0); + const HVX_Vector * restrict v_act1 = (const HVX_Vector *) (y1_q + act_tile * HTP_MM_ACT_TILE_SIZE_Q8_0); + HVX_VectorPair v_sums = accum_q1_0_32x2(vptr[quarter], v_act0, v_act1, v_neg_one, v_pos_one); + HVX_Vector v_sum_sf_c0 = Q6_Vsf_equals_Vw(Q6_V_lo_W(v_sums)); + HVX_Vector v_sum_sf_c1 = Q6_Vsf_equals_Vw(Q6_V_hi_W(v_sums)); + HVX_Vector v_da_sf_c0 = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act0[8])); + HVX_Vector v_da_sf_c1 = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act1[8])); + + v_tile_qf_c0 = Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf_c0, Q6_Vqf32_vmpy_VsfVsf(v_sum_sf_c0, v_da_sf_c0)); + v_tile_qf_c1 = Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf_c1, Q6_Vqf32_vmpy_VsfVsf(v_sum_sf_c1, v_da_sf_c1)); + } + + HVX_Vector v_dw_sf = Q6_V_lo_W(hvx_vec_f16_to_f32(vptr[4])); + v_sum_qf_c0 = Q6_Vqf32_vadd_Vqf32Vqf32(v_sum_qf_c0, Q6_Vqf32_vmpy_VsfVsf(Q6_Vsf_equals_Vqf32(v_tile_qf_c0), v_dw_sf)); + v_sum_qf_c1 = Q6_Vqf32_vadd_Vqf32Vqf32(v_sum_qf_c1, Q6_Vqf32_vmpy_VsfVsf(Q6_Vsf_equals_Vqf32(v_tile_qf_c1), v_dw_sf)); + } + + HVX_Vector v_sum_float_c0 = Q6_Vsf_equals_Vqf32(v_sum_qf_c0); + HVX_Vector v_sum_float_c1 = Q6_Vsf_equals_Vqf32(v_sum_qf_c1); + if (sz0) { + hvx_vec_store_u(s0, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float_c0, hvx_vmemu(sz0))); + } else { + hvx_vec_store_u(s0, valid_rows * sizeof(float), v_sum_float_c0); + } + if (sz1) { + hvx_vec_store_u(s1, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float_c1, hvx_vmemu(sz1))); + } else { + hvx_vec_store_u(s1, valid_rows * sizeof(float), v_sum_float_c1); + } +} + static void tiled_vec_dot_q4_0_32x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy, uint32_t valid_rows, const float * restrict sz) { const uint8_t * restrict tile_ptr = vx; const uint8_t * restrict y_q = vy; @@ -1296,6 +1539,93 @@ static void tiled_vec_dot_q2_k_32x2(const uint32_t n, float * restrict s0, float } } +// One Q2_0 weight tile covers 64 k: act tiles 2 * kt and 2 * kt + 1, each 32 k wide (Q8_1) +static void tiled_vec_dot_q2_0_32x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy, uint32_t valid_rows, const float * restrict sz) { + const uint8_t * restrict tile_ptr = vx; + const uint8_t * restrict y_q = vy; + + HVX_Vector v_sum_float = Q6_V_vzero(); + HVX_Vector v_one_f16 = hvx_vec_splat_f16(1.0); + + uint32_t n_weight_tiles = n / HTP_MM_WEIGHT_TILE_K_Q2_0; + for (uint32_t kt = 0; kt < n_weight_tiles; kt++) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) (tile_ptr + kt * HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q2_0); + HVX_Vector v_tile_qf = Q6_V_vzero(); + + #pragma unroll + for (int half = 0; half < 2; half++) { + const HVX_Vector * restrict v_act = (const HVX_Vector *) (y_q + (2 * kt + half) * HTP_MM_ACT_TILE_SIZE_Q8_1); + + HVX_Vector v_sum_sf = Q6_Vsf_equals_Vw(accum_q2_0_32x1(vptr + 2 * half, v_act)); + HVX_Vector v_da_sf = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act[8])); + HVX_Vector v_sa_qf = Q6_V_lo_W(Q6_Wqf32_vmpy_VhfVhf(v_act[9], v_one_f16)); + HVX_Vector v_h_qf = Q6_Vqf32_vsub_Vqf32Vqf32(Q6_Vqf32_vmpy_VsfVsf(v_sum_sf, v_da_sf), v_sa_qf); + v_tile_qf = (half == 0) ? v_h_qf : Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf, v_h_qf); + } + + HVX_Vector v_dw_sf = Q6_V_lo_W(hvx_vec_f16_to_f32(vptr[4])); + v_sum_float = hvx_vec_add_f32_f32(v_sum_float, hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vqf32(v_tile_qf), v_dw_sf)); + } + + if (sz) { + hvx_vec_store_u(s, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float, hvx_vmemu(sz))); + } else { + hvx_vec_store_u(s, valid_rows * sizeof(float), v_sum_float); + } +} + +static void tiled_vec_dot_q2_0_32x2(const uint32_t n, float * restrict s0, float * restrict s1, const void * restrict vx, const void * restrict vy0, const void * restrict vy1, uint32_t valid_rows, const float * restrict sz0, const float * restrict sz1) { + const uint8_t * restrict tile_ptr = vx; + const uint8_t * restrict y0_q = vy0; + const uint8_t * restrict y1_q = vy1; + + HVX_Vector v_sum_float_c0 = Q6_V_vzero(); + HVX_Vector v_sum_float_c1 = Q6_V_vzero(); + HVX_Vector v_one_f16 = hvx_vec_splat_f16(1.0); + + uint32_t n_weight_tiles = n / HTP_MM_WEIGHT_TILE_K_Q2_0; + for (uint32_t kt = 0; kt < n_weight_tiles; kt++) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) (tile_ptr + kt * HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q2_0); + HVX_Vector v_tile_qf_c0 = Q6_V_vzero(); + HVX_Vector v_tile_qf_c1 = Q6_V_vzero(); + + #pragma unroll + for (int half = 0; half < 2; half++) { + const HVX_Vector * restrict v_act0 = (const HVX_Vector *) (y0_q + (2 * kt + half) * HTP_MM_ACT_TILE_SIZE_Q8_1); + const HVX_Vector * restrict v_act1 = (const HVX_Vector *) (y1_q + (2 * kt + half) * HTP_MM_ACT_TILE_SIZE_Q8_1); + + HVX_Vector v_sum_c0, v_sum_c1; + accum_q2_0_32x2(vptr + 2 * half, v_act0, v_act1, &v_sum_c0, &v_sum_c1); + + HVX_Vector v_da_sf_c0 = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act0[8])); + HVX_Vector v_da_sf_c1 = Q6_V_lo_W(hvx_vec_f16_to_f32_shuff(v_act1[8])); + HVX_Vector v_sa_qf_c0 = Q6_V_lo_W(Q6_Wqf32_vmpy_VhfVhf(v_act0[9], v_one_f16)); + HVX_Vector v_sa_qf_c1 = Q6_V_lo_W(Q6_Wqf32_vmpy_VhfVhf(v_act1[9], v_one_f16)); + + HVX_Vector v_h_qf_c0 = Q6_Vqf32_vsub_Vqf32Vqf32(Q6_Vqf32_vmpy_VsfVsf(Q6_Vsf_equals_Vw(v_sum_c0), v_da_sf_c0), v_sa_qf_c0); + HVX_Vector v_h_qf_c1 = Q6_Vqf32_vsub_Vqf32Vqf32(Q6_Vqf32_vmpy_VsfVsf(Q6_Vsf_equals_Vw(v_sum_c1), v_da_sf_c1), v_sa_qf_c1); + + v_tile_qf_c0 = (half == 0) ? v_h_qf_c0 : Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf_c0, v_h_qf_c0); + v_tile_qf_c1 = (half == 0) ? v_h_qf_c1 : Q6_Vqf32_vadd_Vqf32Vqf32(v_tile_qf_c1, v_h_qf_c1); + } + + HVX_Vector v_dw_sf = Q6_V_lo_W(hvx_vec_f16_to_f32(vptr[4])); + v_sum_float_c0 = hvx_vec_add_f32_f32(v_sum_float_c0, hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vqf32(v_tile_qf_c0), v_dw_sf)); + v_sum_float_c1 = hvx_vec_add_f32_f32(v_sum_float_c1, hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vqf32(v_tile_qf_c1), v_dw_sf)); + } + + if (sz0) { + hvx_vec_store_u(s0, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float_c0, hvx_vmemu(sz0))); + } else { + hvx_vec_store_u(s0, valid_rows * sizeof(float), v_sum_float_c0); + } + if (sz1) { + hvx_vec_store_u(s1, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum_float_c1, hvx_vmemu(sz1))); + } else { + hvx_vec_store_u(s1, valid_rows * sizeof(float), v_sum_float_c1); + } +} + static void tiled_vec_dot_iq4nl_32x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy, uint32_t valid_rows, const float * restrict sz) { const uint8_t * restrict tile_ptr = vx; const uint8_t * restrict y_q = vy; @@ -1482,6 +1812,59 @@ static void tiled_vec_dot_mxfp4_32x2(const uint32_t n, float * restrict s0, floa } } +static void tiled_vec_dot_f16_32x1(const uint32_t n, float * restrict s, const void * restrict vx, const void * restrict vy, uint32_t valid_rows, const float * restrict sz) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) vx; + const HVX_Vector * restrict v_act = (const HVX_Vector *) vy; + const uint32_t n_vecs = ((n + 31) / 32) * 16; + + HVX_VectorPair acc = Q6_W_vzero(); + + #pragma unroll(4) + for (uint32_t i = 0; i < n_vecs; i++) { + acc = hvx_vec_mpyacc_f32_f16(acc, vptr[i], v_act[i]); + } + + HVX_Vector v_sum = hvx_vec_add_f32_f32(Q6_V_lo_W(acc), Q6_V_hi_W(acc)); + + if (sz) { + hvx_vec_store_u(s, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum, hvx_vmemu(sz))); + } else { + hvx_vec_store_u(s, valid_rows * sizeof(float), v_sum); + } +} + +static void tiled_vec_dot_f16_32x2(const uint32_t n, float * restrict s0, float * restrict s1, const void * restrict vx, const void * restrict vy0, const void * restrict vy1, uint32_t valid_rows, const float * restrict sz0, const float * restrict sz1) { + const HVX_Vector * restrict vptr = (const HVX_Vector *) vx; + const HVX_Vector * restrict v_act0 = (const HVX_Vector *) vy0; + const HVX_Vector * restrict v_act1 = (const HVX_Vector *) vy1; + const uint32_t n_vecs = ((n + 31) / 32) * 16; + + HVX_VectorPair acc0 = Q6_W_vzero(); + HVX_VectorPair acc1 = Q6_W_vzero(); + + #pragma unroll(4) + for (uint32_t i = 0; i < n_vecs; i++) { + HVX_Vector v_w = vptr[i]; + acc0 = hvx_vec_mpyacc_f32_f16(acc0, v_w, v_act0[i]); + acc1 = hvx_vec_mpyacc_f32_f16(acc1, v_w, v_act1[i]); + } + + HVX_Vector v_sum0 = hvx_vec_add_f32_f32(Q6_V_lo_W(acc0), Q6_V_hi_W(acc0)); + HVX_Vector v_sum1 = hvx_vec_add_f32_f32(Q6_V_lo_W(acc1), Q6_V_hi_W(acc1)); + + if (sz0) { + hvx_vec_store_u(s0, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum0, hvx_vmemu(sz0))); + } else { + hvx_vec_store_u(s0, valid_rows * sizeof(float), v_sum0); + } + if (sz1) { + hvx_vec_store_u(s1, valid_rows * sizeof(float), hvx_vec_add_f32_f32(v_sum1, hvx_vmemu(sz1))); + } else { + hvx_vec_store_u(s1, valid_rows * sizeof(float), v_sum1); + } +} + + static inline void quantize_f32_q8_0_tiled_kernel( const uint8_t * restrict src_data, uint8_t * restrict dst_data, @@ -1533,6 +1916,40 @@ static inline void quantize_f32_q8_1_s16_tiled_kernel( } } +static inline void quantize_f32_f16_tiled_kernel( + const uint8_t * restrict src_data, + uint8_t * restrict dst_data, + uint8_t * restrict tmp_data, + uint32_t ne0, + uint32_t nrows, + size_t src_row_size, + size_t dst_row_size +) { + (void) tmp_data; + for (uint32_t i = 0; i < nrows; ++i) { + quantize_row_f32_f16_tiled((const float *) src_data, dst_data, ne0); + dst_data += dst_row_size; + src_data += src_row_size; + } +} + +static inline void quantize_f16_f16_tiled_kernel( + const uint8_t * restrict src_data, + uint8_t * restrict dst_data, + uint8_t * restrict tmp_data, + uint32_t ne0, + uint32_t nrows, + size_t src_row_size, + size_t dst_row_size +) { + (void) tmp_data; + for (uint32_t i = 0; i < nrows; ++i) { + quantize_row_f16_f16_tiled((const __fp16 *) src_data, dst_data, ne0); + dst_data += dst_row_size; + src_data += src_row_size; + } +} + static inline void quantize_f32_q8_0_tiled_block_kernel( const float * restrict src, uint8_t * restrict dst, @@ -1546,7 +1963,7 @@ static inline void quantize_f32_q8_0_tiled_block_kernel( uint32_t c ) { (void) tmp_data; - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne0 + qk - 1) / qk; for (uint32_t ib = ib_first; ib < ib_last; ++ib) { @@ -1576,7 +1993,7 @@ static inline void quantize_f32_q8_1_tiled_block_kernel( uint32_t c ) { (void) tmp_data; - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne0 + qk - 1) / qk; for (uint32_t ib = ib_first; ib < ib_last; ++ib) { @@ -1606,7 +2023,7 @@ static inline void quantize_f32_q8_1_s16_tiled_block_kernel( uint32_t c ) { (void) tmp_data; - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne0 + qk - 1) / qk; for (uint32_t ib = ib_first; ib < ib_last; ++ib) { @@ -1622,3 +2039,63 @@ static inline void quantize_f32_q8_1_s16_tiled_block_kernel( } } } + +static inline void quantize_f32_f16_tiled_block_kernel( + const float * restrict src, + uint8_t * restrict dst, + uint8_t * restrict tmp_data, + uint32_t ne0, + uint32_t ib_first, + uint32_t ib_last, + size_t src_row_size, + size_t dst_row_size, + uint32_t r, + uint32_t c +) { + (void) tmp_data; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; + const uint32_t nb = (ne0 + qk - 1) / qk; + + for (uint32_t ib = ib_first; ib < ib_last; ++ib) { + const float * restrict src_ptr = (const float *) ((const uint8_t *) src + r * src_row_size + c * qk * sizeof(float)); + uint8_t * restrict dst_ptr = dst + r * dst_row_size + c * 4 * 2048; + + quantize_block_f32_f16_tiled(src_ptr, dst_ptr); + + c++; + if (c == nb) { + c = 0; + r++; + } + } +} + +static inline void quantize_f16_f16_tiled_block_kernel( + const __fp16 * restrict src, + uint8_t * restrict dst, + uint8_t * restrict tmp_data, + uint32_t ne0, + uint32_t ib_first, + uint32_t ib_last, + size_t src_row_size, + size_t dst_row_size, + uint32_t r, + uint32_t c +) { + (void) tmp_data; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; + const uint32_t nb = (ne0 + qk - 1) / qk; + + for (uint32_t ib = ib_first; ib < ib_last; ++ib) { + const __fp16 * restrict src_ptr = (const __fp16 *) ((const uint8_t *) src + r * src_row_size + c * qk * sizeof(__fp16)); + uint8_t * restrict dst_ptr = dst + r * dst_row_size + c * 4 * 2048; + + quantize_block_f16_f16_tiled(src_ptr, dst_ptr); + + c++; + if (c == nb) { + c = 0; + r++; + } + } +} diff --git a/ggml/src/ggml-hexagon/htp/hvx-norm.h b/ggml/src/ggml-hexagon/htp/hvx-norm.h index 7ea945a339c4..145c3086e2fa 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-norm.h +++ b/ggml/src/ggml-hexagon/htp/hvx-norm.h @@ -11,7 +11,8 @@ static inline void hvx_fast_rms_norm_f32(const uint8_t * restrict src, uint8_t * restrict dst, const int num_elems, - float epsilon) { + float epsilon, + float scale) { const HVX_Vector * restrict v_src = (HVX_Vector *) src; HVX_Vector * restrict v_dst = (HVX_Vector *) dst; @@ -48,6 +49,9 @@ static inline void hvx_fast_rms_norm_f32(const uint8_t * restrict src, // Scale full vectors HVX_Vector scale_v = hvx_vec_rsqrt_f32(Q6_Vsf_equals_Vqf32(mean_epsilon_v)); + if (scale != 0.0f) { + scale_v = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vmpy_VsfVsf(scale_v, hvx_vec_splat_f32(scale))); + } #pragma unroll(4) for (int i = 0; i < nvec; i++) { @@ -72,7 +76,8 @@ static inline void hvx_fast_rms_norm_mul_f32(const uint8_t * restrict src, const uint8_t * restrict weight, uint8_t * restrict dst, const int num_elems, - float epsilon) { + float epsilon, + float scale) { const HVX_Vector * restrict v_src = (const HVX_Vector *) src; const HVX_Vector * restrict v_weight = (const HVX_Vector *) weight; HVX_Vector * restrict v_dst = (HVX_Vector *) dst; @@ -109,6 +114,9 @@ static inline void hvx_fast_rms_norm_mul_f32(const uint8_t * restrict src, // Scale and multiply HVX_Vector scale_v = hvx_vec_rsqrt_f32(Q6_Vsf_equals_Vqf32(mean_epsilon_v)); + if (scale != 0.0f) { + scale_v = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vmpy_VsfVsf(scale_v, hvx_vec_splat_f32(scale))); + } #pragma unroll(4) for (int i = 0; i < nvec; i++) { diff --git a/ggml/src/ggml-hexagon/htp/hvx-quant.h b/ggml/src/ggml-hexagon/htp/hvx-quant.h index 6b172cd63c3a..b0ca6ecf6ac8 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-quant.h +++ b/ggml/src/ggml-hexagon/htp/hvx-quant.h @@ -5,6 +5,7 @@ #include #include +#include "htp-tensor.h" #include "hvx-arith.h" #include "hvx-base.h" #include "hvx-reduce.h" @@ -96,7 +97,7 @@ static inline void hvx_quantize_row_q8_0_f32(void * restrict dst_ptr, const floa } } -static inline void hvx_dequantize_row_q8_0_f32(float * restrict dst_ptr, const void * restrict src_ptr, int n) { +static inline void hvx_dequantize_row_flat_q8_0_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { const int nb = n / QK8_0; const block_q8_0 * src = (const block_q8_0 *) src_ptr; @@ -120,7 +121,7 @@ static inline void hvx_dequantize_row_q8_0_f32(float * restrict dst_ptr, const v } } -static inline void hvx_dequantize_row_q8_0_f16(__fp16 * restrict dst_ptr, const void * restrict src_ptr, int n) { +static inline void hvx_dequantize_row_flat_q8_0_f16(__fp16 * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { const int nb = n / QK8_0; const block_q8_0 * src = (const block_q8_0 *) src_ptr; @@ -146,20 +147,580 @@ static inline void hvx_dequantize_row_q8_0_f16(__fp16 * restrict dst_ptr, const } } -static inline void hvx_dequantize_row_f16_f32(float * restrict dst_ptr, const void * restrict src_ptr, int n) { - const int nb = n / 32; +static inline void hvx_dequantize_row_flat_f16_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const uint32_t nvec = n / VLEN_FP32; + const uint32_t nloe = n % VLEN_FP32; const _Float16 * src = (const _Float16 *) src_ptr; - for (int i = 0; i < nb; i++) { - HVX_Vector v_f16 = *(const HVX_UVector *) (src + i * 32); + for (uint32_t i = 0; i < nvec; i++) { + HVX_Vector v_f16 = *(const HVX_UVector *) (src + i * VLEN_FP32); HVX_VectorPair vp_f32 = hvx_vec_f16_to_f32(v_f16); HVX_Vector res = Q6_V_lo_W(vp_f32); - float * block_dst = dst_ptr + i * 32; - hvx_vmem(block_dst) = res; + hvx_vmem(dst_ptr + i * VLEN_FP32) = res; + } + + if (nloe) { + HVX_Vector v_f16 = *(const HVX_UVector *) (src + nvec * VLEN_FP32); + HVX_VectorPair vp_f32 = hvx_vec_f16_to_f32(v_f16); + HVX_Vector res = Q6_V_lo_W(vp_f32); + + hvx_vec_store_a(dst_ptr + nvec * VLEN_FP32, nloe * sizeof(float), res); } } +static inline void hvx_dequantize_row_flat_bf16_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const uint32_t nvec = n / VLEN_FP32; + const uint32_t nloe = n % VLEN_FP32; + const uint16_t * src = (const uint16_t *) src_ptr; + + for (uint32_t i = 0; i < nvec; i++) { + HVX_Vector v_bf16 = *(const HVX_UVector *) (src + i * VLEN_FP32); + HVX_VectorPair p = Q6_Ww_vunpack_Vh(v_bf16); + HVX_Vector res = Q6_Vw_vasl_VwR(Q6_V_lo_W(p), 16); + + hvx_vmem(dst_ptr + i * VLEN_FP32) = res; + } + + if (nloe) { + HVX_Vector v_bf16 = *(const HVX_UVector *) (src + nvec * VLEN_FP32); + HVX_VectorPair p = Q6_Ww_vunpack_Vh(v_bf16); + HVX_Vector res = Q6_Vw_vasl_VwR(Q6_V_lo_W(p), 16); + + hvx_vec_store_a(dst_ptr + nvec * VLEN_FP32, nloe * sizeof(float), res); + } +} + +static inline void hvx_dequantize_row_flat_q1_0_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + static const uint32_t __attribute__((aligned(128))) bit_mask[32] = { + 1u << 0, 1u << 1, 1u << 2, 1u << 3, 1u << 4, 1u << 5, 1u << 6, 1u << 7, + 1u << 8, 1u << 9, 1u << 10, 1u << 11, 1u << 12, 1u << 13, 1u << 14, 1u << 15, + 1u << 16, 1u << 17, 1u << 18, 1u << 19, 1u << 20, 1u << 21, 1u << 22, 1u << 23, + 1u << 24, 1u << 25, 1u << 26, 1u << 27, 1u << 28, 1u << 29, 1u << 30, 1u << 31, + }; + const int nb = n / QK1_0; + const block_q1_0 * src = (const block_q1_0 *) src_ptr; + const HVX_Vector v_bit_mask = *(const HVX_Vector *) bit_mask; + const HVX_Vector v_zero = Q6_V_vzero(); + const HVX_Vector v_sign_bit = Q6_V_vsplat_R(0x80000000); + + for (int i = 0; i < nb; i++) { + HVX_Vector vd_f16 = Q6_Vh_vsplat_R(*(const int16_t *) &src[i].d); + HVX_Vector vd = Q6_V_lo_W(hvx_vec_f16_to_f32(vd_f16)); + HVX_Vector neg_vd = Q6_V_vxor_VV(vd, v_sign_bit); + HVX_Vector v_qs = *(const HVX_UVector *) src[i].qs; + + float * block_dst = dst_ptr + i * QK1_0; + #pragma unroll + for (int q = 0; q < 4; q++) { + HVX_Vector v_bits = hvx_vec_repl_u32(q == 0 ? v_qs : Q6_V_vror_VR(v_qs, 4 * q)); + HVX_VectorPred q_zero = Q6_Q_vcmp_eq_VwVw(Q6_V_vand_VV(v_bits, v_bit_mask), v_zero); + hvx_vmem(block_dst + q * 32) = Q6_V_vmux_QVV(q_zero, neg_vd, vd); + } + } +} + +static inline void hvx_dequantize_row_flat_q2_0_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const int nb = n / QK2_0; + const block_q2_0 * src = (const block_q2_0 *) src_ptr; + const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + const HVX_Vector v_one = Q6_Vb_vsplat_R(1); + + for (int i = 0; i < nb; i++) { + HVX_Vector vd_f16 = Q6_Vh_vsplat_R(*(const int16_t *) &src[i].d); + HVX_Vector vd = Q6_V_lo_W(hvx_vec_f16_to_f32(vd_f16)); + + HVX_Vector vq = *(const HVX_UVector *) src[i].qs; + HVX_Vector v0 = Q6_V_vand_VV(vq, mask_03); + HVX_Vector v1 = Q6_V_vand_VV(Q6_Vub_vlsr_VubR(vq, 2), mask_03); + HVX_Vector v2 = Q6_V_vand_VV(Q6_Vub_vlsr_VubR(vq, 4), mask_03); + HVX_Vector v3 = Q6_Vub_vlsr_VubR(vq, 6); + + HVX_Vector v01 = Q6_V_lo_W(Q6_W_vshuff_VVR(v1, v0, -1)); + HVX_Vector v23 = Q6_V_lo_W(Q6_W_vshuff_VVR(v3, v2, -1)); + HVX_Vector v64 = Q6_Vb_vsub_VbVb(Q6_V_lo_W(Q6_W_vshuff_VVR(v23, v01, -2)), v_one); + + HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(v64); + HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + + float * block_dst = dst_ptr + i * QK2_0; + hvx_vmem(block_dst + 0) = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), vd); + hvx_vmem(block_dst + 32) = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_hi_W(p32)), vd); + } +} + +static inline void hvx_dequantize_row_flat_q4_0_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const int nb = n / QK4_0; + const block_q4_0 * src = (const block_q4_0 *) src_ptr; + + const HVX_VectorPred q16 = Q6_Q_vsetq_R(16); + const HVX_Vector v_eight = Q6_Vb_vsplat_R(8); + const HVX_Vector v_zero = Q6_V_vzero(); + + for (int i = 0; i < nb; i++) { + HVX_Vector vd_f16 = Q6_Vh_vsplat_R(*(const int16_t *) &src[i].d); + HVX_VectorPair vp_f32 = hvx_vec_f16_to_f32(vd_f16); + HVX_Vector vd = Q6_V_lo_W(vp_f32); + + HVX_Vector vq = *(const HVX_UVector *) src[i].qs; + HVX_Vector v_lo = Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)); + HVX_Vector v_hi = Q6_Vub_vlsr_VubR(vq, 4); + + HVX_Vector v_lo_s8 = Q6_Vb_vsub_VbVb(v_lo, v_eight); + HVX_Vector v_hi_s8 = Q6_Vb_vsub_VbVb(v_hi, v_eight); + + HVX_Vector v32 = Q6_V_vmux_QVV(q16, v_lo_s8, Q6_V_vlalign_VVR(v_hi_s8, v_zero, 16)); + + HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(v32); + HVX_Vector v_i16 = Q6_V_lo_W(p16); + HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(v_i16); + HVX_Vector v_i32 = Q6_V_lo_W(p32); + + HVX_Vector v_f32 = Q6_Vsf_equals_Vw(v_i32); + HVX_Vector res = hvx_vec_mul_f32_f32(v_f32, vd); + + hvx_vmem(dst_ptr + i * QK4_0) = res; + } +} + +static inline void hvx_dequantize_row_flat_q4_k_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const int nb = n / QK_K; + const block_q4_K * src = (const block_q4_K *) src_ptr; + + for (int i = 0; i < nb; i++) { + const float d = GGML_FP16_TO_FP32(src[i].d); + const float min = GGML_FP16_TO_FP32(src[i].dmin); + const uint8_t * sc = src[i].scales; + + float * y = dst_ptr + i * QK_K; + + for (int step = 0; step < 4; ++step) { + uint8_t sc1, m1_u, sc2, m2_u; + if (step < 2) { + sc1 = sc[2 * step + 0] & 63; + m1_u = sc[2 * step + 4] & 63; + sc2 = sc[2 * step + 1] & 63; + m2_u = sc[2 * step + 5] & 63; + } else { + const int s = step - 2; + sc1 = (sc[8 + 2 * s + 0] & 0xF) | ((sc[2 * s + 0] >> 6) << 4); + m1_u = (sc[8 + 2 * s + 0] >> 4) | ((sc[4 + 2 * s + 0] >> 6) << 4); + sc2 = (sc[8 + 2 * s + 1] & 0xF) | ((sc[2 * s + 1] >> 6) << 4); + m2_u = (sc[8 + 2 * s + 1] >> 4) | ((sc[4 + 2 * s + 1] >> 6) << 4); + } + + HVX_Vector vq = *(const HVX_UVector *) (src[i].qs + step * 32); + HVX_Vector v_lo = Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)); + HVX_Vector v_hi = Q6_Vub_vlsr_VubR(vq, 4); + + HVX_VectorPair p16_lo = Q6_Wuh_vunpack_Vub(v_lo); + HVX_VectorPair p32_lo = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_lo)); + HVX_Vector v_i32_lo = Q6_V_lo_W(p32_lo); + HVX_Vector v_f32_lo = Q6_Vsf_equals_Vw(v_i32_lo); + + HVX_Vector vd1 = hvx_vec_splat_f32(d * sc1); + HVX_Vector vm1 = hvx_vec_splat_f32(min * m1_u); + HVX_Vector v_out1 = hvx_vec_sub_f32_f32(hvx_vec_mul_f32_f32(v_f32_lo, vd1), vm1); + hvx_vmem(y + 0) = v_out1; + + HVX_VectorPair p16_hi = Q6_Wuh_vunpack_Vub(v_hi); + HVX_VectorPair p32_hi = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_hi)); + HVX_Vector v_i32_hi = Q6_V_lo_W(p32_hi); + HVX_Vector v_f32_hi = Q6_Vsf_equals_Vw(v_i32_hi); + + HVX_Vector vd2 = hvx_vec_splat_f32(d * sc2); + HVX_Vector vm2 = hvx_vec_splat_f32(min * m2_u); + HVX_Vector v_out2 = hvx_vec_sub_f32_f32(hvx_vec_mul_f32_f32(v_f32_hi, vd2), vm2); + hvx_vmem(y + 32) = v_out2; + + y += 64; + } + } +} +static inline void hvx_dequantize_row_flat_q5_k_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const int nb = n / QK_K; + const block_q5_K * src = (const block_q5_K *) src_ptr; + + for (int i = 0; i < nb; i++) { + const float d = GGML_FP16_TO_FP32(src[i].d); + const float min = GGML_FP16_TO_FP32(src[i].dmin); + const uint8_t * sc = src[i].scales; + + HVX_Vector v_qh = *(const HVX_UVector *) src[i].qh; + float * y = dst_ptr + i * QK_K; + + for (int step = 0; step < 4; ++step) { + uint8_t sc1, m1_u, sc2, m2_u; + if (step < 2) { + sc1 = sc[2 * step + 0] & 63; + m1_u = sc[2 * step + 4] & 63; + sc2 = sc[2 * step + 1] & 63; + m2_u = sc[2 * step + 5] & 63; + } else { + const int s = step - 2; + sc1 = (sc[8 + 2 * s + 0] & 0xF) | ((sc[2 * s + 0] >> 6) << 4); + m1_u = (sc[8 + 2 * s + 0] >> 4) | ((sc[4 + 2 * s + 0] >> 6) << 4); + sc2 = (sc[8 + 2 * s + 1] & 0xF) | ((sc[2 * s + 1] >> 6) << 4); + m2_u = (sc[8 + 2 * s + 1] >> 4) | ((sc[4 + 2 * s + 1] >> 6) << 4); + } + + HVX_Vector v_ql = *(const HVX_UVector *) (src[i].qs + step * 32); + HVX_Vector v_lo = Q6_V_vand_VV(v_ql, Q6_Vb_vsplat_R(0x0F)); + HVX_Vector v_hi = Q6_Vub_vlsr_VubR(v_ql, 4); + + HVX_Vector v_h1 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_qh, 2 * step), Q6_Vb_vsplat_R(1)), 4); + HVX_Vector v_val1 = Q6_V_vor_VV(v_lo, v_h1); + + HVX_VectorPair p16_1 = Q6_Wuh_vunpack_Vub(v_val1); + HVX_VectorPair p32_1 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_1)); + HVX_Vector v_i32_1 = Q6_V_lo_W(p32_1); + HVX_Vector v_f32_1 = Q6_Vsf_equals_Vw(v_i32_1); + + HVX_Vector vd1 = hvx_vec_splat_f32(d * sc1); + HVX_Vector vm1 = hvx_vec_splat_f32(min * m1_u); + HVX_Vector v_out1 = hvx_vec_sub_f32_f32(hvx_vec_mul_f32_f32(v_f32_1, vd1), vm1); + hvx_vmem(y + 0) = v_out1; + + HVX_Vector v_h2 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_qh, 2 * step + 1), Q6_Vb_vsplat_R(1)), 4); + HVX_Vector v_val2 = Q6_V_vor_VV(v_hi, v_h2); + + HVX_VectorPair p16_2 = Q6_Wuh_vunpack_Vub(v_val2); + HVX_VectorPair p32_2 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_2)); + HVX_Vector v_i32_2 = Q6_V_lo_W(p32_2); + HVX_Vector v_f32_2 = Q6_Vsf_equals_Vw(v_i32_2); + + HVX_Vector vd2 = hvx_vec_splat_f32(d * sc2); + HVX_Vector vm2 = hvx_vec_splat_f32(min * m2_u); + HVX_Vector v_out2 = hvx_vec_sub_f32_f32(hvx_vec_mul_f32_f32(v_f32_2, vd2), vm2); + hvx_vmem(y + 32) = v_out2; + + y += 64; + } + } +} + +static inline void hvx_dequantize_row_flat_q6_k_f32(float * restrict dst_ptr, const void * restrict src_ptr, uint32_t n) { + const int nb = n / QK_K; + const block_q6_K * src = (const block_q6_K *) src_ptr; + + const HVX_VectorPred q64 = Q6_Q_vsetq_R(64); + const HVX_Vector v32_b = Q6_Vb_vsplat_R(32); + const HVX_Vector mask_0f = Q6_Vb_vsplat_R(0x0F); + const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + + for (int i = 0; i < nb; i++) { + const float d = GGML_FP16_TO_FP32(src[i].d); + + const uint8_t * restrict ql = src[i].ql; + const uint8_t * restrict qh = src[i].qh; + const int8_t * restrict sc = src[i].scales; + + float * y = dst_ptr + i * QK_K; + + for (int half = 0; half < 2; ++half) { + float s[8]; + for (int j = 0; j < 8; ++j) { + s[j] = d * sc[j]; + } + + HVX_Vector vscale1 = Q6_V_vmux_QVV(q64, hvx_vec_splat_f32(s[0]), hvx_vec_splat_f32(s[1])); + HVX_Vector vscale2 = Q6_V_vmux_QVV(q64, hvx_vec_splat_f32(s[2]), hvx_vec_splat_f32(s[3])); + HVX_Vector vscale3 = Q6_V_vmux_QVV(q64, hvx_vec_splat_f32(s[4]), hvx_vec_splat_f32(s[5])); + HVX_Vector vscale4 = Q6_V_vmux_QVV(q64, hvx_vec_splat_f32(s[6]), hvx_vec_splat_f32(s[7])); + + HVX_Vector v_ql0 = *(const HVX_UVector *) (ql); + HVX_Vector v_ql1 = *(const HVX_UVector *) (ql + 32); + HVX_Vector v_qh = *(const HVX_UVector *) (qh); + + HVX_Vector ql0_lo = Q6_V_vand_VV(v_ql0, mask_0f); + HVX_Vector qh_0 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(v_qh, mask_03), 4); + HVX_Vector v_q1 = Q6_Vb_vsub_VbVb(Q6_V_vor_VV(ql0_lo, qh_0), v32_b); + + HVX_Vector ql1_lo = Q6_V_vand_VV(v_ql1, mask_0f); + HVX_Vector qh_1 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_qh, 2), mask_03), 4); + HVX_Vector v_q2 = Q6_Vb_vsub_VbVb(Q6_V_vor_VV(ql1_lo, qh_1), v32_b); + + HVX_Vector ql0_hi = Q6_Vub_vlsr_VubR(v_ql0, 4); + HVX_Vector qh_2 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_qh, 4), mask_03), 4); + HVX_Vector v_q3 = Q6_Vb_vsub_VbVb(Q6_V_vor_VV(ql0_hi, qh_2), v32_b); + + HVX_Vector ql1_hi = Q6_Vub_vlsr_VubR(v_ql1, 4); + HVX_Vector qh_3 = Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_qh, 6), mask_03), 4); + HVX_Vector v_q4 = Q6_Vb_vsub_VbVb(Q6_V_vor_VV(ql1_hi, qh_3), v32_b); + + HVX_VectorPair p16_1 = Q6_Wh_vunpack_Vb(v_q1); + HVX_VectorPair p32_1 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_1)); + HVX_Vector v_f32_1 = Q6_Vsf_equals_Vw(Q6_V_lo_W(p32_1)); + hvx_vmem(y + 0) = hvx_vec_mul_f32_f32(v_f32_1, vscale1); + + HVX_VectorPair p16_2 = Q6_Wh_vunpack_Vb(v_q2); + HVX_VectorPair p32_2 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_2)); + HVX_Vector v_f32_2 = Q6_Vsf_equals_Vw(Q6_V_lo_W(p32_2)); + hvx_vmem(y + 32) = hvx_vec_mul_f32_f32(v_f32_2, vscale2); + + HVX_VectorPair p16_3 = Q6_Wh_vunpack_Vb(v_q3); + HVX_VectorPair p32_3 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_3)); + HVX_Vector v_f32_3 = Q6_Vsf_equals_Vw(Q6_V_lo_W(p32_3)); + hvx_vmem(y + 64) = hvx_vec_mul_f32_f32(v_f32_3, vscale3); + + HVX_VectorPair p16_4 = Q6_Wh_vunpack_Vb(v_q4); + HVX_VectorPair p32_4 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16_4)); + HVX_Vector v_f32_4 = Q6_Vsf_equals_Vw(Q6_V_lo_W(p32_4)); + hvx_vmem(y + 96) = hvx_vec_mul_f32_f32(v_f32_4, vscale4); + + y += 128; + ql += 64; + qh += 32; + sc += 8; + } + } +} + +// bytes row, row + 32, row + 64 and row + 96 of v, to bytes 0..3 +static inline HVX_Vector hvx_dequantize_gather4(HVX_Vector v, uint32_t row) { + v = Q6_V_vror_VR(v, row); + HVX_Vector packed = Q6_V_vmux_QVV(Q6_Q_vsetq_R(1), v, Q6_V_vror_VR(v, 31)); + packed = Q6_V_vmux_QVV(Q6_Q_vsetq_R(2), packed, Q6_V_vror_VR(v, 62)); + return Q6_V_vmux_QVV(Q6_Q_vsetq_R(3), packed, Q6_V_vror_VR(v, 93)); +} + +static inline void hvx_dequantize_row_tiled_q8_0_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_VectorPred first2 = Q6_Q_vsetq_R(2); + const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + HVX_Vector vq = Q6_V_vzero(); + for (int group = 7; group >= 0; --group) { + const HVX_Vector v = Q6_V_vror_VR(hvx_vmem(tile + group * VLEN), 2 * row); + const HVX_Vector packed = Q6_V_vmux_QVV(first2, v, Q6_V_vror_VR(v, 62)); + vq = Q6_V_vmux_QVV(first4, packed, Q6_V_vror_VR(vq, VLEN - 4)); + } + + const HVX_Vector scales = hvx_vmem(tile + 1024); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); + const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + HVX_Vector values = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + *(HVX_Vector *) dst = values; + } +} + +static inline void hvx_dequantize_row_tiled_q4_0_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + HVX_Vector vq = Q6_V_vzero(); + for (int group = 3; group >= 0; --group) { + vq = Q6_V_vmux_QVV(first4, hvx_dequantize_gather4(hvx_vmem(tile + group * VLEN), row), Q6_V_vror_VR(vq, VLEN - 4)); + } + + const HVX_Vector lo = Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)); + const HVX_Vector hi = Q6_Vub_vlsr_VubR(vq, 4); + vq = Q6_V_lo_W(Q6_W_vshuff_VVR(hi, lo, -1)); + vq = Q6_Vb_vsub_VbVb(vq, Q6_Vb_vsplat_R(8)); + + const HVX_Vector scales = hvx_vmem(tile + 512); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); + const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + HVX_Vector values = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + *(HVX_Vector *) dst = values; + } +} + +static inline void hvx_dequantize_row_tiled_q4_k_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + HVX_Vector vq = Q6_V_vzero(); + for (int group = 3; group >= 0; --group) { + vq = Q6_V_vmux_QVV(first4, hvx_dequantize_gather4(hvx_vmem(tile + group * VLEN), row), Q6_V_vror_VR(vq, VLEN - 4)); + } + + const HVX_Vector lo = Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)); + const HVX_Vector hi = Q6_Vub_vlsr_VubR(vq, 4); + vq = Q6_V_lo_W(Q6_W_vshuff_VVR(hi, lo, -1)); + + const HVX_Vector scales = hvx_vmem(tile + 512); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 4 * row)); + const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + const HVX_Vector offset_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 4 * row + 2)); + const HVX_Vector offset = Q6_V_lo_W(hvx_vec_f16_to_f32(offset_hf)); + + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + HVX_Vector values = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + *(HVX_Vector *) dst = hvx_vec_add_f32_f32(values, offset); + } +} + +static inline void hvx_dequantize_row_tiled_q5_k_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); + const HVX_Vector one = Q6_Vb_vsplat_R(1); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + const HVX_Vector p5 = hvx_dequantize_gather4(hvx_vmem(tile + 640), row); + HVX_Vector vq = Q6_V_vzero(); + HVX_Vector vh = Q6_V_vzero(); + for (int group = 3; group >= 0; --group) { + vq = Q6_V_vmux_QVV(first4, hvx_dequantize_gather4(hvx_vmem(tile + group * VLEN), row), Q6_V_vror_VR(vq, VLEN - 4)); + vh = Q6_V_vmux_QVV(first4, Q6_Vub_vlsr_VubR(p5, 2 * group), Q6_V_vror_VR(vh, VLEN - 4)); + } + + const HVX_Vector lo = Q6_V_vor_VV(Q6_V_vand_VV(vq, Q6_Vb_vsplat_R(0x0F)), Q6_Vw_vasl_VwR(Q6_V_vand_VV(vh, one), 4)); + const HVX_Vector hi = Q6_V_vor_VV(Q6_Vub_vlsr_VubR(vq, 4), Q6_Vw_vasl_VwR(Q6_V_vand_VV(Q6_Vub_vlsr_VubR(vh, 1), one), 4)); + vq = Q6_V_lo_W(Q6_W_vshuff_VVR(hi, lo, -1)); + + const HVX_Vector scales = hvx_vmem(tile + 512); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 4 * row)); + const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + const HVX_Vector offset_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 4 * row + 2)); + const HVX_Vector offset = Q6_V_lo_W(hvx_vec_f16_to_f32(offset_hf)); + + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + HVX_Vector values = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + *(HVX_Vector *) dst = hvx_vec_add_f32_f32(values, offset); + } +} + +static inline void hvx_dequantize_row_tiled_q6_k_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_VectorPred first4 = Q6_Q_vsetq_R(4); + const HVX_VectorPred first16 = Q6_Q_vsetq_R(16 * sizeof(float)); + const HVX_Vector mask_0f = Q6_Vb_vsplat_R(0x0F); + const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + HVX_Vector vq = Q6_V_vzero(); + for (int group = 7; group >= 0; --group) { + const HVX_Vector lo_plane = Q6_V_vror_VR(hvx_vmem(tile + (group >> 1) * VLEN), 4 * row); + const HVX_Vector hi_plane = Q6_V_vror_VR(hvx_vmem(tile + 512 + (group >> 2) * VLEN), 4 * row); + const HVX_Vector lo = (group & 1) ? Q6_Vub_vlsr_VubR(lo_plane, 4) : Q6_V_vand_VV(lo_plane, mask_0f); + const HVX_Vector hi = Q6_Vub_vlsr_VubR(hi_plane, 2 * (group & 3)); + const HVX_Vector packed = Q6_V_vor_VV(lo, Q6_Vw_vasl_VwR(Q6_V_vand_VV(hi, mask_03), 4)); + vq = Q6_V_vmux_QVV(first4, packed, Q6_V_vror_VR(vq, VLEN - 4)); + } + + const HVX_Vector scales = hvx_vmem(tile + 768); + const HVX_Vector scale_lo_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); + const HVX_Vector scale_hi_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 64 + 2 * row)); + const HVX_Vector scale_lo = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_lo_hf)); + const HVX_Vector scale_hi = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hi_hf)); + const HVX_Vector scale = Q6_V_vmux_QVV(first16, scale_lo, scale_hi); + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(Q6_Vb_vsub_VbVb(vq, Q6_Vb_vsplat_R(32))); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + *(HVX_Vector *) dst = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + } +} + +static inline HVX_Vector hvx_dequantize_tiled_f16_gather4(const uint8_t * p, uint32_t r_byte) { + HVX_Vector w0 = Q6_V_vror_VR(hvx_vmem(p + 0 * VLEN), r_byte); + HVX_Vector w1 = Q6_V_vror_VR(hvx_vmem(p + 1 * VLEN), r_byte); + HVX_Vector w01 = Q6_V_lo_W(Q6_W_vshuff_VVR(w1, w0, 4)); + HVX_Vector w2 = Q6_V_vror_VR(hvx_vmem(p + 2 * VLEN), r_byte); + HVX_Vector w3 = Q6_V_vror_VR(hvx_vmem(p + 3 * VLEN), r_byte); + HVX_Vector w23 = Q6_V_lo_W(Q6_W_vshuff_VVR(w3, w2, 4)); + return Q6_V_lo_W(Q6_W_vshuff_VVR(w23, w01, 8)); +} + +static inline void hvx_dequantize_row_tiled_f16_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const uint32_t r_byte = 4 * row; + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_N_COLS; + + HVX_Vector g0 = hvx_dequantize_tiled_f16_gather4(tile + 0 * VLEN, r_byte); + HVX_Vector g1 = hvx_dequantize_tiled_f16_gather4(tile + 4 * VLEN, r_byte); + HVX_Vector g01 = Q6_V_lo_W(Q6_W_vshuff_VVR(g1, g0, 16)); + + HVX_Vector g2 = hvx_dequantize_tiled_f16_gather4(tile + 8 * VLEN, r_byte); + HVX_Vector g3 = hvx_dequantize_tiled_f16_gather4(tile + 12 * VLEN, r_byte); + HVX_Vector g23 = Q6_V_lo_W(Q6_W_vshuff_VVR(g3, g2, 16)); + + HVX_Vector g = Q6_V_lo_W(Q6_W_vshuff_VVR(g23, g01, 32)); + *(HVX_Vector *) dst = Q6_V_lo_W(hvx_vec_f16_to_f32(g)); + } +} + +static inline void hvx_dequantize_row_tiled_q1_0_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + static const uint32_t __attribute__((aligned(128))) bit_mask[32] = { + 1u << 0, 1u << 8, 1u << 16, 1u << 24, + 1u << 1, 1u << 9, 1u << 17, 1u << 25, + 1u << 2, 1u << 10, 1u << 18, 1u << 26, + 1u << 3, 1u << 11, 1u << 19, 1u << 27, + 1u << 4, 1u << 12, 1u << 20, 1u << 28, + 1u << 5, 1u << 13, 1u << 21, 1u << 29, + 1u << 6, 1u << 14, 1u << 22, 1u << 30, + 1u << 7, 1u << 15, 1u << 23, 1u << 31, + }; + const HVX_Vector v_bit_mask = *(const HVX_Vector *) bit_mask; + const HVX_Vector v_zero = Q6_V_vzero(); + const HVX_Vector v_sign_bit = Q6_V_vsplat_R(0x80000000); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_K_Q1_0; + + const HVX_Vector scales = hvx_vmem(tile + 512); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); + const HVX_Vector vd = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + const HVX_Vector neg_vd = Q6_V_vxor_VV(vd, v_sign_bit); + + #pragma unroll + for (int q = 0; q < 4; ++q) { + const HVX_Vector v_bits = hvx_vec_repl_u32(Q6_V_vror_VR(hvx_vmem(tile + q * VLEN), 4 * row)); + const HVX_VectorPred q_zero = Q6_Q_vcmp_eq_VwVw(Q6_V_vand_VV(v_bits, v_bit_mask), v_zero); + hvx_vmem(dst + q * 32) = Q6_V_vmux_QVV(q_zero, neg_vd, vd); + } + } +} + +static inline void hvx_dequantize_row_tiled_q2_0_f32(float * dst_spad, const uint8_t * src_spad, uint32_t n_k_tiles, uint32_t tile_stride, uint32_t row) { + const HVX_Vector mask_03 = Q6_Vb_vsplat_R(0x03); + const HVX_Vector v_one = Q6_Vb_vsplat_R(1); + + for (uint32_t k_tile = 0; k_tile < n_k_tiles; ++k_tile) { + const uint8_t * tile = src_spad + k_tile * tile_stride; + float * dst = dst_spad + k_tile * HTP_TENSOR_TILE_K_Q2_0; + + const HVX_Vector v_packed = hvx_dequantize_tiled_f16_gather4(tile, 4 * row); + const HVX_Vector p0 = Q6_V_vand_VV(v_packed, mask_03); + const HVX_Vector p1 = Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_packed, 2), mask_03); + const HVX_Vector p2 = Q6_V_vand_VV(Q6_Vub_vlsr_VubR(v_packed, 4), mask_03); + const HVX_Vector p3 = Q6_Vub_vlsr_VubR(v_packed, 6); + + const HVX_Vector p01 = Q6_V_lo_W(Q6_W_vshuff_VVR(p1, p0, -4)); + const HVX_Vector p23 = Q6_V_lo_W(Q6_W_vshuff_VVR(p3, p2, -4)); + const HVX_Vector vq = Q6_Vb_vsub_VbVb(Q6_V_lo_W(Q6_W_vshuff_VVR(p23, p01, -8)), v_one); + + const HVX_Vector scales = hvx_vmem(tile + 512); + const HVX_Vector scale_hf = hvx_vec_repl_f16(Q6_V_vror_VR(scales, 2 * row)); + const HVX_Vector scale = Q6_V_lo_W(hvx_vec_f16_to_f32(scale_hf)); + + const HVX_VectorPair p16 = Q6_Wh_vunpack_Vb(vq); + const HVX_VectorPair p32 = Q6_Ww_vunpack_Vh(Q6_V_lo_W(p16)); + hvx_vmem(dst + 0) = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_lo_W(p32)), scale); + hvx_vmem(dst + 32) = hvx_vec_mul_f32_f32(Q6_Vsf_equals_Vw(Q6_V_hi_W(p32)), scale); + } +} #endif // HVX_QUANT_H diff --git a/ggml/src/ggml-hexagon/htp/hvx-sigmoid.h b/ggml/src/ggml-hexagon/htp/hvx-sigmoid.h index b7c2d7409155..d4d67ff2f07d 100644 --- a/ggml/src/ggml-hexagon/htp/hvx-sigmoid.h +++ b/ggml/src/ggml-hexagon/htp/hvx-sigmoid.h @@ -68,6 +68,14 @@ static inline HVX_Vector hvx_vec_tanh_f32(HVX_Vector x) { return Q6_Vsf_equals_Vqf32(res); } +static inline HVX_Vector hvx_vec_silu_f32(HVX_Vector x) { + HVX_Vector one = hvx_vec_splat_f32(1.0f); + HVX_Vector max_exp = hvx_vec_splat_f32(87.f); + HVX_Vector min_exp = hvx_vec_splat_f32(-87.f); + HVX_Vector sig = hvx_vec_fast_sigmoid_f32_guard(x, one, max_exp, min_exp); + return Q6_Vsf_equals_Vqf32(Q6_Vqf32_vmpy_VsfVsf(x, sig)); +} + #define hvx_sigmoid_loop_body(dst_type, src_type, vec_store) \ do { \ dst_type * restrict vdst = (dst_type *) dst; \ diff --git a/ggml/src/ggml-hexagon/htp/im2col-ops.c b/ggml/src/ggml-hexagon/htp/im2col-ops.c index ee3c7da11105..9e662694b4cf 100644 --- a/ggml/src/ggml-hexagon/htp/im2col-ops.c +++ b/ggml/src/ggml-hexagon/htp/im2col-ops.c @@ -26,6 +26,7 @@ struct htp_im2col_context { uint32_t pe_row_base; // first output row index assigned to this dev (DMA path) uint32_t pe_nrows; // number of output rows assigned to this dev (DMA path) uint32_t pe_rows_per_thread; // output rows per worker + uint32_t pe_blocks_per_thread; // output-col blocks per worker (blocked DMA path) uint32_t pe_src_row_bytes; // one output row's source, rounded 256 uint32_t pe_dst_row_bytes; // one output row's dst: OW*patch_stride*2, rounded 256 @@ -38,6 +39,7 @@ struct htp_im2col_context { uint32_t pe_owb; // output-col block size uint32_t pe_wb; // staged source window width uint32_t pe_nbpr; // blocks per row + uint32_t pe_gather_nvec; // vectors per gathered patch (KH == 1 blocked path) // Precomputed dimensions for worker threads uint32_t N; @@ -51,6 +53,7 @@ struct htp_im2col_context { uint32_t thread_in[HTP_MAX_NTHREADS]; uint32_t thread_iod[HTP_MAX_NTHREADS]; uint32_t thread_ioh[HTP_MAX_NTHREADS]; + uint32_t thread_c0[HTP_MAX_NTHREADS]; void * compute; uint32_t dst_elem; @@ -215,6 +218,109 @@ static void FNAME( IM2COL_BLOCKED_COMPUTE_BODY(im2col_blocked_compute_f16, uint16_t, hvx_copy_f16_f32_uu, hvx_splat_u16_u) IM2COL_BLOCKED_COMPUTE_BODY(im2col_blocked_compute_f32, float, hvx_copy_f32_uu, hvx_splat_f32_u) +// Offsets of one output patch in the staged window, for KH == 1: lane k reads channel k / KW at tap k % KW. +// Lanes past the patch read the first element and are not stored. +// The first vector is built lane by lane; each next one is 32 lanes further: the tap advances by 32 % KW +// and the channel by 32 / KW, plus one more when the tap wraps past KW. +static __attribute__((noinline)) void im2col_gather_table_build(const struct htp_im2col_context * ictx, + HVX_Vector * restrict table) { + const int32_t d0 = ictx->octx->op_params[4]; + const uint32_t KW = ictx->KW, Wb = ictx->pe_wb; + + int32_t tap0[32] __attribute__((aligned(128))); + int32_t off0[32] __attribute__((aligned(128))); + uint32_t iic = 0, ikw = 0; + for (uint32_t k = 0; k < 32; k++) { + tap0[k] = (int32_t) ikw; + off0[k] = (int32_t) ((iic * Wb + ikw * d0) * sizeof(float)); + if (++ikw == KW) { + ikw = 0; + iic++; + } + } + // (iic, ikw) is now (32 / KW, 32 % KW) + const HVX_Vector v_kw = Q6_V_vsplat_R(KW); + const HVX_Vector v_kw_m1 = Q6_V_vsplat_R(KW - 1); + const HVX_Vector v_tap_step = Q6_V_vsplat_R(ikw); + const HVX_Vector v_off_step = Q6_V_vsplat_R((iic * Wb + ikw * d0) * sizeof(float)); + const HVX_Vector v_off_wrap = Q6_V_vsplat_R((Wb - KW * d0) * sizeof(float)); + const HVX_Vector v_32 = Q6_V_vsplat_R(32); + const HVX_Vector v_n = Q6_V_vsplat_R(ictx->patch_stride); + + HVX_Vector lane = hvx_vec_gather_offsets_w(1); + HVX_Vector tap = *(HVX_Vector *) tap0; + HVX_Vector off = *(HVX_Vector *) off0; + for (uint32_t g = 0; g < ictx->pe_gather_nvec; g++) { + table[g] = Q6_V_vmux_QVV(Q6_Q_vcmp_gt_VwVw(v_n, lane), off, Q6_V_vzero()); + + lane = Q6_Vw_vadd_VwVw(lane, v_32); + tap = Q6_Vw_vadd_VwVw(tap, v_tap_step); + off = Q6_Vw_vadd_VwVw(off, v_off_step); + + const HVX_VectorPred wrap = Q6_Q_vcmp_gt_VwVw(tap, v_kw_m1); + tap = Q6_V_vmux_QVV(wrap, Q6_Vw_vsub_VwVw(tap, v_kw), tap); + off = Q6_V_vmux_QVV(wrap, Q6_Vw_vadd_VwVw(off, v_off_wrap), off); + } +} + +// KH == 1: each output row is one patch, gathered from the staged [IC][Wb] window with a fixed offset +// table shifted by s0 per row, then converted with a single copy. +// scratch holds the offset table followed by the gathered row (both VTCM). +#define IM2COL_GATHER_COMPUTE_BODY(FNAME, DST_CTYPE, COPY_FN) \ +static void FNAME( \ + const struct htp_im2col_context * ictx, \ + void * restrict dstb_raw, const float * restrict srcb_c, \ + float * restrict scratch, \ + uint32_t nb, uint32_t c0, uint32_t ioh) { \ + DST_CTYPE * restrict dstb = (DST_CTYPE *) dstb_raw; \ + float * restrict srcb = (float *) srcb_c; \ + const int32_t s0 = ictx->octx->op_params[0], p0 = ictx->octx->op_params[2]; \ + const int32_t s1 = ictx->octx->op_params[1], p1 = ictx->octx->op_params[3]; \ + const uint32_t IC = ictx->IC, IH = ictx->IH, IW = ictx->IW, Wb = ictx->pe_wb; \ + const uint32_t patch_stride = ictx->patch_stride; \ + const uint32_t ng = ictx->pe_gather_nvec; \ + const int32_t win0 = (int32_t) c0 * s0 - p0; \ + const int32_t iih = (int32_t) ioh * s1 - p1; \ + \ + /* the DMA stage fills only the columns inside [0, IW): zero the rest of the window */ \ + const int32_t lo = win0 < 0 ? -win0 : 0; \ + const int32_t hi = MIN((int32_t) Wb, (int32_t) IW - win0); \ + if (iih < 0 || iih >= (int32_t) IH || hi <= lo) { \ + for (uint32_t iic = 0; iic < IC; iic++) { \ + hvx_splat_f32_u(srcb + (size_t) iic * Wb, 0, Wb); \ + } \ + } else if (lo > 0 || hi < (int32_t) Wb) { \ + for (uint32_t iic = 0; iic < IC; iic++) { \ + float * row = srcb + (size_t) iic * Wb; \ + if (lo > 0) { \ + hvx_splat_f32_u(row, 0, (uint32_t) lo); \ + } \ + if (hi < (int32_t) Wb) { \ + hvx_splat_f32_u(row + hi, 0, Wb - (uint32_t) hi); \ + } \ + } \ + } \ + \ + const HVX_Vector * table = (const HVX_Vector *) scratch; \ + float * row = scratch + (size_t) ng * 32; \ + const uint32_t region = IC * Wb * sizeof(float); \ + \ + for (uint32_t j = 0; j < nb; j++) { \ + const uint32_t shift = j * (uint32_t) s0 * sizeof(float); \ + const size_t base = (size_t) ((const uint8_t *) srcb + shift); \ + const uint32_t mu = region - shift - 1; \ + for (uint32_t g = 0; g < ng; g++) { \ + Q6_vgather_ARMVw((HVX_Vector *) (row + g * 32), base, mu, table[g]); \ + } \ + hvx_gather_sync(row + (ng - 1) * 32); \ + DST_CTYPE * out = dstb + (size_t) j * patch_stride; \ + COPY_FN((uint8_t *) out, (const uint8_t *) row, patch_stride); \ + } \ +} + +IM2COL_GATHER_COMPUTE_BODY(im2col_gather_compute_f16, uint16_t, hvx_copy_f16_f32_uu) +IM2COL_GATHER_COMPUTE_BODY(im2col_gather_compute_f32, float, hvx_copy_f32_uu) + static void im2col_blocked_dma_thread(unsigned int nth, unsigned int ith, void * data) { (void) nth; struct htp_im2col_context * ictx = (struct htp_im2col_context *) data; @@ -234,24 +340,24 @@ static void im2col_blocked_dma_thread(unsigned int nth, unsigned int ith, void * float * srcb2[2] = { (float *) srcb_base, (float *) (srcb_base + ictx->pe_src_row_bytes) }; void * dstb2[2] = { dstb_base, dstb_base + ictx->pe_dst_row_bytes }; float * scratch = (float *) (srcb_base + 2 * ictx->pe_src_row_bytes); - const uint32_t row_end_max = ictx->pe_row_base + ictx->pe_nrows; - const uint32_t row_start = ictx->pe_row_base + ictx->pe_rows_per_thread * ith; - const uint32_t row_end = MIN(row_start + ictx->pe_rows_per_thread, row_end_max); - if (row_start >= row_end) { - return; - } - const uint32_t nrows_local = row_end - row_start; - const uint32_t total_blocks = nrows_local * nbpr; - if (total_blocks == 0) { + // work is split over output-col blocks, so a single output row (1D) still uses every thread + const uint32_t blk_end_max = ictx->pe_nrows * nbpr; + const uint32_t blk_start = ictx->pe_blocks_per_thread * ith; + const uint32_t blk_end = MIN(blk_start + ictx->pe_blocks_per_thread, blk_end_max); + if (blk_start >= blk_end) { return; } + const uint32_t total_blocks = blk_end - blk_start; struct im2col_cursor cur = { - .r = row_start, + .r = ictx->thread_in[ith] * ictx->OH + ictx->thread_ioh[ith], .in = ictx->thread_in[ith], .iod = 0, .ioh = ictx->thread_ioh[ith], - .c0 = 0, + .c0 = ictx->thread_c0[ith], }; + if (KH == 1) { + im2col_gather_table_build(ictx, (HVX_Vector *) scratch); + } struct im2col_cursor stage = cur; for (uint32_t i = 0; i < total_blocks && i < 2; i++) { dma_queue_push(dma_q, dma_make_data(dst_data, dstb2[i]), 0, 0, 0, 0); @@ -307,6 +413,37 @@ static void im2col_patchembed_compute_f16( const uint32_t KH = ictx->KH, KW = ictx->KW; const uint32_t OW = ictx->OW, patch_stride = ictx->patch_stride; + if (KW == 16 && (KH % 4 == 0)) { + const HVX_VectorPred q_lo = Q6_Q_vsetq_R(64); + for (uint32_t iow = 0; iow < OW; iow++) { + uint16_t * dst_patch = dstb + (size_t) iow * patch_stride; + for (uint32_t iic = 0; iic < IC; iic++) { + for (uint32_t ikh = 0; ikh < KH; ikh += 4) { + const int32_t iih0 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 0); + const int32_t iih1 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 1); + const int32_t iih2 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 2); + const int32_t iih3 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 3); + + const float * s0 = srcb + (size_t) (iic * KH + ikh + 0) * IW + (size_t) iow * 16; + const float * s1 = srcb + (size_t) (iic * KH + ikh + 1) * IW + (size_t) iow * 16; + const float * s2 = srcb + (size_t) (iic * KH + ikh + 2) * IW + (size_t) iow * 16; + const float * s3 = srcb + (size_t) (iic * KH + ikh + 3) * IW + (size_t) iow * 16; + + const HVX_Vector v0 = (iih0 >= 0 && iih0 < (int32_t) IH) ? *((const HVX_UVector *) s0) : Q6_V_vzero(); + const HVX_Vector v1 = (iih1 >= 0 && iih1 < (int32_t) IH) ? *((const HVX_UVector *) s1) : Q6_V_vzero(); + const HVX_Vector v2 = (iih2 >= 0 && iih2 < (int32_t) IH) ? *((const HVX_UVector *) s2) : Q6_V_vzero(); + const HVX_Vector v3 = (iih3 >= 0 && iih3 < (int32_t) IH) ? *((const HVX_UVector *) s3) : Q6_V_vzero(); + + const HVX_Vector w01 = Q6_V_vmux_QVV(q_lo, v0, Q6_V_vror_VR(v1, 64)); + const HVX_Vector w23 = Q6_V_vmux_QVV(q_lo, v2, Q6_V_vror_VR(v3, 64)); + + *((HVX_Vector *) (dst_patch + (size_t) (iic * KH + ikh) * 16)) = hvx_vec_f32_to_f16(w01, w23); + } + } + } + return; + } + for (uint32_t iow = 0; iow < OW; iow++) { uint16_t * dst_patch = dstb + (size_t) iow * patch_stride; for (uint32_t ikh = 0; ikh < KH; ikh++) { @@ -332,6 +469,30 @@ static void im2col_patchembed_compute_f32( const uint32_t KH = ictx->KH, KW = ictx->KW; const uint32_t OW = ictx->OW, patch_stride = ictx->patch_stride; + if (KW == 16 && (KH % 2 == 0)) { + const HVX_VectorPred q_lo = Q6_Q_vsetq_R(64); + for (uint32_t iow = 0; iow < OW; iow++) { + float * dst_patch = dstb + (size_t) iow * patch_stride; + for (uint32_t iic = 0; iic < IC; iic++) { + for (uint32_t ikh = 0; ikh < KH; ikh += 2) { + const int32_t iih0 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 0); + const int32_t iih1 = (int32_t) ioh * (int32_t) KH + (int32_t) (ikh + 1); + + const float * s0 = srcb + (size_t) (iic * KH + ikh + 0) * IW + (size_t) iow * 16; + const float * s1 = srcb + (size_t) (iic * KH + ikh + 1) * IW + (size_t) iow * 16; + + const HVX_Vector v0 = (iih0 >= 0 && iih0 < (int32_t) IH) ? *((const HVX_UVector *) s0) : Q6_V_vzero(); + const HVX_Vector v1 = (iih1 >= 0 && iih1 < (int32_t) IH) ? *((const HVX_UVector *) s1) : Q6_V_vzero(); + + const HVX_Vector w01 = Q6_V_vmux_QVV(q_lo, v0, Q6_V_vror_VR(v1, 64)); + + *((HVX_Vector *) (dst_patch + (size_t) (iic * KH + ikh) * 16)) = w01; + } + } + } + return; + } + for (uint32_t iow = 0; iow < OW; iow++) { float * dst_patch = dstb + (size_t) iow * patch_stride; for (uint32_t ikh = 0; ikh < KH; ikh++) { @@ -768,19 +929,13 @@ int op_im2col(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } - if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { - return HTP_STATUS_INVAL_PARAMS; - } - const struct htp_tensor * dst = octx->dst; uint32_t row_base = 0; uint32_t nrows = kparams->total_rows; if (octx->ctx->mdev.count > 1) { - const uint32_t row_size = dst->nb[2]; - const uint32_t rows_per_chunk = (row_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(row_size, HEX_L2_LINE_SIZE)) : 1; const struct htp_tensor_mdev_range range = - htp_tensor_mdev_partition(kparams->total_rows, htp_tensor_mdev_data_aligned(dst) ? rows_per_chunk : 0, + htp_tensor_mdev_partition(kparams->total_rows, htp_tensor_mdev_data_aligned(dst) ? kparams->rows_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); row_base = range.start; nrows = range.count; @@ -790,20 +945,32 @@ int op_im2col(struct htp_ops_context * octx) { return HTP_STATUS_OK; } + // the blocked path splits work over output-col blocks, so a single output row (1D) can use every thread + const bool blocked = kparams->kernel_type == HTP_IM2COL_KERNEL_BLOCKED_DMA; + const uint32_t nwork = blocked ? nrows * kparams->nbpr : nrows; + if (!htp_ops_context_set_n_threads(octx, MIN((uint32_t) kparams->n_threads, nwork))) { + return HTP_STATUS_INVAL_PARAMS; + } + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, kparams->src_row_bytes, kparams->dst_row_bytes, kparams->n_threads, + htp_im2col_scratch_bytes(kparams->kernel_type, kparams->KH, kparams->patch_stride)); + struct htp_im2col_context ictx = { 0 }; uint8_t * const base = octx->ctx->vtcm_base; - const uint32_t pth = MIN(octx->n_threads, nrows); + const uint32_t pth = octx->n_threads; ictx.octx = octx; ictx.pe_row_base = row_base; ictx.pe_nrows = nrows; - ictx.pe_rows_per_thread = (nrows + pth - 1) / pth; + ictx.pe_rows_per_thread = fastdiv(nrows + pth - 1, &octx->n_threads_div); + ictx.pe_blocks_per_thread = fastdiv(nwork + pth - 1, &octx->n_threads_div); ictx.pe_src_row_bytes = kparams->src_row_bytes; ictx.pe_dst_row_bytes = kparams->dst_row_bytes; - ictx.pe_vtcm_src = VTCM_LAYOUT_PTR(uint8_t, base, kparams->off_src); - ictx.pe_vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, kparams->off_dst); - ictx.pe_src_size_per_thread = kparams->src_bytes_per_thread; - ictx.pe_dst_size_per_thread = kparams->dst_bytes_per_thread; + ictx.pe_vtcm_src = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_src); + ictx.pe_vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_dst); + ictx.pe_src_size_per_thread = layout.src_bytes_per_thread; + ictx.pe_dst_size_per_thread = layout.dst_bytes_per_thread; ictx.pe_owb = kparams->owb; ictx.pe_wb = kparams->wb; ictx.pe_nbpr = kparams->nbpr; @@ -819,11 +986,22 @@ int op_im2col(struct htp_ops_context * octx) { ictx.OH = kparams->OH; ictx.OW = kparams->OW; ictx.patch_stride = kparams->patch_stride; + ictx.pe_gather_nvec = hex_round_up(kparams->patch_stride, 32) / 32; + // a thread starts at a row, or at an output-col block (possibly mid-row) on the blocked path for (uint32_t ith = 0; ith < pth; ith++) { - uint32_t r = row_base + ictx.pe_rows_per_thread * ith; - ictx.thread_ioh[ith] = r % kparams->OH; - ictx.thread_in[ith] = r / kparams->OH; + uint32_t r = row_base + ictx.pe_rows_per_thread * ith; + uint32_t c0 = 0; + if (blocked) { + const uint32_t blk = ictx.pe_blocks_per_thread * ith; + const uint32_t q = fastdiv(blk, &kparams->div_nbpr); + r = row_base + q; + c0 = (blk - q * kparams->nbpr) * kparams->owb; + } + const uint32_t in = fastdiv(r, &kparams->div_OH); + ictx.thread_ioh[ith] = r - in * kparams->OH; + ictx.thread_in[ith] = in; + ictx.thread_c0[ith] = c0; } ictx.dst_elem = dst->type == HTP_TYPE_F16 ? sizeof(__fp16) : sizeof(float); @@ -833,9 +1011,14 @@ int op_im2col(struct htp_ops_context * octx) { : (void *) im2col_patchembed_compute_f32; work_queue_run(octx->ctx->work_queue, im2col_patchembed_dma_thread, &ictx, pth); return HTP_STATUS_OK; - } else if (kparams->kernel_type == HTP_IM2COL_KERNEL_BLOCKED_DMA) { - ictx.compute = dst->type == HTP_TYPE_F16 ? (void *) im2col_blocked_compute_f16 - : (void *) im2col_blocked_compute_f32; + } else if (blocked) { + if (kparams->KH == 1) { + ictx.compute = dst->type == HTP_TYPE_F16 ? (void *) im2col_gather_compute_f16 + : (void *) im2col_gather_compute_f32; + } else { + ictx.compute = dst->type == HTP_TYPE_F16 ? (void *) im2col_blocked_compute_f16 + : (void *) im2col_blocked_compute_f32; + } work_queue_run(octx->ctx->work_queue, im2col_blocked_dma_thread, &ictx, pth); return HTP_STATUS_OK; } @@ -850,19 +1033,13 @@ int op_im2col_3d(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } - if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { - return HTP_STATUS_INVAL_PARAMS; - } - const struct htp_tensor * dst = octx->dst; uint32_t row_base = 0; uint32_t nrows = kparams->total_rows; if (octx->ctx->mdev.count > 1) { - const uint32_t row_size = dst->nb[2]; - const uint32_t rows_per_chunk = (row_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(row_size, HEX_L2_LINE_SIZE)) : 1; const struct htp_tensor_mdev_range range = - htp_tensor_mdev_partition(kparams->total_rows, htp_tensor_mdev_data_aligned(dst) ? rows_per_chunk : 0, + htp_tensor_mdev_partition(kparams->total_rows, htp_tensor_mdev_data_aligned(dst) ? kparams->rows_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); row_base = range.start; nrows = range.count; @@ -872,20 +1049,27 @@ int op_im2col_3d(struct htp_ops_context * octx) { return HTP_STATUS_OK; } + if (!htp_ops_context_set_n_threads(octx, MIN((uint32_t) kparams->n_threads, nrows))) { + return HTP_STATUS_INVAL_PARAMS; + } + + struct htp_im2col_vtcm_layout layout; + htp_im2col_vtcm_layout_build(&layout, kparams->src_row_bytes, kparams->dst_row_bytes, kparams->n_threads, 256); + struct htp_im2col_context ictx = { 0 }; uint8_t * const base = octx->ctx->vtcm_base; - const uint32_t pth = MIN(octx->n_threads, nrows); + const uint32_t pth = octx->n_threads; ictx.octx = octx; ictx.pe_row_base = row_base; ictx.pe_nrows = nrows; - ictx.pe_rows_per_thread = (nrows + pth - 1) / pth; + ictx.pe_rows_per_thread = fastdiv(nrows + pth - 1, &octx->n_threads_div); ictx.pe_src_row_bytes = kparams->src_row_bytes; ictx.pe_dst_row_bytes = kparams->dst_row_bytes; - ictx.pe_vtcm_src = VTCM_LAYOUT_PTR(uint8_t, base, kparams->off_src); - ictx.pe_vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, kparams->off_dst); - ictx.pe_src_size_per_thread = kparams->src_bytes_per_thread; - ictx.pe_dst_size_per_thread = kparams->dst_bytes_per_thread; + ictx.pe_vtcm_src = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_src); + ictx.pe_vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, layout.off_dst); + ictx.pe_src_size_per_thread = layout.src_bytes_per_thread; + ictx.pe_dst_size_per_thread = layout.dst_bytes_per_thread; ictx.pe_owb = kparams->owb; ictx.pe_wb = kparams->wb; ictx.pe_nbpr = kparams->nbpr; @@ -903,11 +1087,12 @@ int op_im2col_3d(struct htp_ops_context * octx) { ictx.patch_stride = kparams->patch_stride; for (uint32_t ith = 0; ith < pth; ith++) { - uint32_t rem = row_base + ictx.pe_rows_per_thread * ith; - ictx.thread_ioh[ith] = rem % kparams->OH; - rem /= kparams->OH; - ictx.thread_iod[ith] = rem % kparams->OD; - ictx.thread_in[ith] = rem / kparams->OD; + const uint32_t rem = row_base + ictx.pe_rows_per_thread * ith; + const uint32_t q_oh = fastdiv(rem, &kparams->div_OH); + ictx.thread_ioh[ith] = rem - q_oh * kparams->OH; + const uint32_t in = fastdiv(q_oh, &kparams->div_OD); + ictx.thread_iod[ith] = q_oh - in * kparams->OD; + ictx.thread_in[ith] = in; } ictx.dst_elem = dst->type == HTP_TYPE_F16 ? sizeof(__fp16) : sizeof(float); diff --git a/ggml/src/ggml-hexagon/htp/im2col-ops.h b/ggml/src/ggml-hexagon/htp/im2col-ops.h index 9ccc21fd761e..b34e6a09dbc1 100644 --- a/ggml/src/ggml-hexagon/htp/im2col-ops.h +++ b/ggml/src/ggml-hexagon/htp/im2col-ops.h @@ -2,6 +2,8 @@ #define HTP_IM2COL_OPS_H #include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-vtcm.h" #include enum htp_im2col_kernel_type { @@ -11,38 +13,44 @@ enum htp_im2col_kernel_type { }; struct htp_im2col_vtcm_layout { - uint32_t off_src; - uint32_t off_dst; + size_t total_bytes; + size_t off_src; + size_t off_dst; uint32_t src_bytes_per_thread; uint32_t dst_bytes_per_thread; - uint32_t total_bytes; }; +// scratch_bytes: per-thread VTCM after the two src buffers (at least 256) static inline void htp_im2col_vtcm_layout_build( - struct htp_im2col_vtcm_layout * layout, + struct htp_im2col_vtcm_layout * L, uint32_t src_row_bytes, uint32_t dst_row_bytes, - uint32_t n_threads) { + uint32_t n_threads, + uint32_t scratch_bytes) { - layout->src_bytes_per_thread = 2 * src_row_bytes + 256; - layout->dst_bytes_per_thread = 2 * dst_row_bytes; + L->src_bytes_per_thread = 2 * src_row_bytes + (scratch_bytes > 256 ? scratch_bytes : 256); + L->dst_bytes_per_thread = 2 * dst_row_bytes; - layout->off_src = 0; - layout->off_dst = layout->off_src + layout->src_bytes_per_thread * n_threads; - layout->total_bytes = layout->off_dst + layout->dst_bytes_per_thread * n_threads; + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src, (size_t) L->src_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, (size_t) L->dst_bytes_per_thread * n_threads); + L->total_bytes = off; +} + +// per-thread scratch: the KH == 1 blocked path keeps its offset table and one gathered row there, +// both padded to whole vectors +static inline uint32_t htp_im2col_scratch_bytes(uint32_t kernel_type, uint32_t KH, uint32_t patch_stride) { + if (kernel_type == HTP_IM2COL_KERNEL_BLOCKED_DMA && KH == 1) { + return 2 * hex_round_up(patch_stride, 32) * (uint32_t) sizeof(float); + } + return 256; } struct htp_im2col_kernel_params { uint8_t kernel_type; - uint8_t is_2d; - uint8_t is_3d; uint8_t n_threads; uint32_t vtcm_size; - uint32_t off_src; - uint32_t off_dst; - uint32_t src_bytes_per_thread; - uint32_t dst_bytes_per_thread; uint32_t src_row_bytes; uint32_t dst_row_bytes; @@ -57,6 +65,11 @@ struct htp_im2col_kernel_params { uint32_t OD, OH, OW; uint32_t patch_stride; uint32_t total_rows; + uint32_t rows_per_chunk; + + struct fastdiv_values div_OH; + struct fastdiv_values div_OD; + struct fastdiv_values div_nbpr; }; #if defined(__cplusplus) diff --git a/ggml/src/ggml-hexagon/htp/main.c b/ggml/src/ggml-hexagon/htp/main.c index df7c4a5bd1ff..78adc9a495d5 100644 --- a/ggml/src/ggml-hexagon/htp/main.c +++ b/ggml/src/ggml-hexagon/htp/main.c @@ -28,8 +28,8 @@ #include "ggml-common.h" #include "hex-bitmap.h" #include "htp-ctx.h" +#include "htp-dcache.h" #include "htp-ops.h" -#include "htp-tensor.h" #include "htp_iface.h" #include "work-queue.h" #include "hex-profile.h" @@ -316,9 +316,20 @@ static int vtcm_release_callback(unsigned int rctx, void * state) { return 0; } -static int vtcm_alloc(struct htp_context * ctx) { +static unsigned int vtcm_query_size(void) { unsigned int vtcm_size = 8 * 1024 * 1024; // 8MB default - HAP_compute_res_query_VTCM(0, &vtcm_size, NULL, NULL, NULL); + unsigned int vtcm_avail; + compute_res_vtcm_page_t total_layout, avail_layout; + // some images (e.g. FuSa cDSP) fail the query when the layout out-params are NULL + HAP_compute_res_query_VTCM(0, &vtcm_size, &total_layout, &vtcm_avail, &avail_layout); + return vtcm_size; +} + +static int vtcm_alloc(struct htp_context * ctx, uint64_t size_override) { + unsigned int vtcm_size = vtcm_query_size(); + if (size_override) { + vtcm_size = (unsigned int) size_override; + } compute_res_attr_t attr; HAP_compute_res_attr_init(&attr); @@ -430,7 +441,7 @@ static const struct htp_power_profile htp_power_profiles[HTP_POWER_MODE_COUNT] = #undef HTP_POWER_PROFILE_ENTRY -AEEResult htp_iface_start(remote_handle64 handle, uint32_t sess_id, uint64_t dsp_queue_id, uint32_t n_hvx, uint32_t n_hmx, uint64_t max_vmem, uint32_t power_mode) { +AEEResult htp_iface_start(remote_handle64 handle, uint32_t sess_id, uint64_t dsp_queue_id, uint32_t n_hvx, uint32_t n_hmx, uint64_t vtcm_size, uint64_t max_vmem, uint32_t power_mode) { struct htp_handle * h = (struct htp_handle *) handle; if (!h) { return AEE_EBADPARM; @@ -549,7 +560,7 @@ AEEResult htp_iface_start(remote_handle64 handle, uint32_t sess_id, uint64_t dsp ctx->max_vmem = max_vmem; ctx->dsp_queue = dsp_queue; - err = vtcm_alloc(ctx); + err = vtcm_alloc(ctx, vtcm_size); if (err != AEE_SUCCESS) { FARF(ERROR, "Unable to allocate VTCM"); htp_iface_stop(handle); @@ -666,7 +677,7 @@ AEEResult htp_iface_start(remote_handle64 handle, uint32_t sess_id, uint64_t dsp dma_ptr_curr += size_dma_q; } - ctx->ddr_spad_size = 512 * 1024; // 512 KB + ctx->ddr_spad_size = HTP_DDR_SPAD_SIZE; ctx->ddr_spad_base = memalign(128, ctx->ddr_spad_size); void * wq_ptr = (void *) ((uintptr_t) block + offset_wq); @@ -770,9 +781,7 @@ AEEResult htp_iface_hwinfo(remote_handle64 handle, uint32_t * n_threads, uint32_ *n_hvx = n_hvx_val; *n_hmx = 1; - uint32_t vtcm_sz = 8 * 1024 * 1024; // 8MB default fallback - HAP_compute_res_query_VTCM(0, (unsigned int *)&vtcm_sz, NULL, NULL, NULL); - *vtcm_size = vtcm_sz; + *vtcm_size = vtcm_query_size(); return AEE_SUCCESS; } @@ -835,7 +844,7 @@ static int op_fence(struct htp_ops_context * octx) { atomic_uint * sync_fence = (atomic_uint *) (uintptr_t) sync->data; if (mode == 1) { - htp_flush_dirty_ranges(ctx); + htp_dcache_flush_dirty_ranges(ctx); htp_mdev_group_barrier(octx); @@ -939,7 +948,10 @@ static int execute_op(struct htp_ops_context * octx) { case HTP_OP_UNARY_LOG: case HTP_OP_UNARY_RELU: case HTP_OP_UNARY_STEP: + case HTP_OP_UNARY_CEIL: + case HTP_OP_UNARY_SGN: case HTP_OP_L2_NORM: + case HTP_OP_HADAMARD: return op_unary(octx); case HTP_OP_GLU_SWIGLU: @@ -948,7 +960,9 @@ static int execute_op(struct htp_ops_context * octx) { case HTP_OP_GLU_GEGLU: case HTP_OP_GLU_GEGLU_QUICK: case HTP_OP_GLU_GEGLU_ERF: - return op_activations(octx); + case HTP_OP_GLU_REGLU: + case HTP_OP_GLU_SIGMOID: + return op_glu(octx); case HTP_OP_SOFTMAX: return op_softmax(octx); @@ -1011,6 +1025,12 @@ static int execute_op(struct htp_ops_context * octx) { case HTP_OP_IM2COL_3D: return op_im2col_3d(octx); + case HTP_OP_CONV_2D: + return op_conv_2d(octx); + + case HTP_OP_CONV_2D_DW: + return op_conv_2d_dw(octx); + case HTP_OP_ROLL: return op_roll(octx); @@ -1029,6 +1049,9 @@ static int execute_op(struct htp_ops_context * octx) { case HTP_OP_TRI: return op_unary(octx); + case HTP_OP_UPSCALE: + return op_upscale(octx); + case HTP_OP_INVALID: break; } @@ -1211,7 +1234,7 @@ static int proc_op_req(struct htp_ops_context * octx, struct htp_buf_desc * bufs src->ne[0], src->ne[1], src->ne[2], src->ne[3]); } - htp_tensor_flush_all(octx->ctx, octx->src, HTP_OP_MAX_INPUTS); + htp_dcache_flush_dirty_tensors(octx->ctx, octx->src, HTP_OP_MAX_INPUTS); // Prep output tensors for (uint32_t i = 0; i < HTP_OP_MAX_OUTPUTS; i++) { @@ -1227,7 +1250,7 @@ static int proc_op_req(struct htp_ops_context * octx, struct htp_buf_desc * bufs dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3]); } - htp_tensor_dirty_all(octx->ctx, octx->dsts, HTP_OP_MAX_OUTPUTS); + htp_dcache_mark_dirty_tensors(octx->ctx, octx->dsts, HTP_OP_MAX_OUTPUTS); htp_mdev_group_barrier(octx); @@ -1237,8 +1260,6 @@ static int proc_op_req(struct htp_ops_context * octx, struct htp_buf_desc * bufs octx->src0_spad.src = NULL; octx->src1_spad.src = NULL; - octx->src2_spad.src = NULL; - octx->src3_spad.src = NULL; octx->dst_spad.src = NULL; return octx->status; @@ -1299,10 +1320,7 @@ static void process_opbatch(struct htp_context * ctx, const struct htp_opbatch_r prep_tensors(ctx, bufs, tens, n_tens); struct htp_ops_context *octx = &ctx->octx; - memset(octx, 0, sizeof(*octx)); - octx->n_threads = ctx->n_threads; - octx->n_threads_div = ctx->n_threads_div; - octx->ctx = ctx; + htp_ops_context_reset(octx, ctx); mdev_group_init(ctx, req); diff --git a/ggml/src/ggml-hexagon/htp/matmul-ops.c b/ggml/src/ggml-hexagon/htp/matmul-ops.c index 28aed4680df4..b4b943058f18 100644 --- a/ggml/src/ggml-hexagon/htp/matmul-ops.c +++ b/ggml/src/ggml-hexagon/htp/matmul-ops.c @@ -16,6 +16,7 @@ #include "hvx-dump.h" #include "hvx-arith.h" #include "hvx-reduce.h" +#include "hvx-copy.h" #define GGML_COMMON_DECL_C #include "ggml-common.h" @@ -38,8 +39,12 @@ typedef struct { int act_stride; uint32_t act_elem_size; // 4=F32 src1, 2=F16 src1 int weight_stride; + int weight_type; int dst_stride; + int dst_cols; uint32_t bias_stride; + int tile_size; + int aligned_tile_size; int ne02; int ne03; int ne12; @@ -56,7 +61,7 @@ typedef struct { int r3; struct fastdiv_values div_r2; struct fastdiv_values div_r3; -} hmx_mm_f16_f32_batched_params_t; +} hmx_mm_batched_params_t; static bool htp_matmul_has_extended_weight(const struct htp_ops_context * octx, uint32_t n_weights) { for (uint32_t i = 0; i < n_weights; ++i) { @@ -89,6 +94,11 @@ struct htp_mm_context { const void * restrict vy, uint32_t valid_rows, const float * restrict sz); + void (*vec_dot_32x2)(const uint32_t n, float * restrict s0, float * restrict s1, + const void * restrict vx, + const void * restrict vy0, const void * restrict vy1, uint32_t valid_rows, + const float * restrict sz0, const float * restrict sz1); + // Precomputed values uint32_t src0_nrows_per_thread; uint32_t src0_row_start; @@ -238,314 +248,296 @@ static const uint8_t __attribute__((aligned(VLEN))) kvalues_mxfp4_lut[] = { #include "hvx-mm-kernels-float.h" #include "hmx-mm-kernels-tiled.h" -// Specialized repacked matmul macros -#define MATMUL_2D_REPACKED_IMPL(SUFFIX, TILE_SIZE, DOT_2X2, DOT_2X1) \ -static void hvx_mm_2d_repacked_##SUFFIX(unsigned int nth, unsigned int ith, void * data) { \ - htp_matmul_preamble; \ - \ - const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; \ - const uint32_t act_nrows = mmctx->cur_m_rows ? mmctx->cur_m_rows : (ne11 * ne12 * ne13); \ - const uint32_t cur_m_start = mmctx->cur_m_start; \ - \ - const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; \ - const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); \ - \ - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ - \ - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; \ - const uint32_t n_prefetch = kparams->n_prefetch; \ - assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); \ - \ - const size_t dst_row_size = nb1; \ - const size_t act_row_size = nb11; \ - const size_t act_stride = mmctx->vtcm_act_stride; \ - const size_t src2_stride = src2 ? ((src2->ne[1] == 1) ? 0 : src2->nb[1]) : 0; \ - \ - uint8_t * restrict vtcm_dst_ptr = mmctx->vtcm_dst + mmctx->vtcm_dst_size_per_thread * ith; \ - uint8_t * restrict vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; \ - uint8_t * restrict act_data = mmctx->vtcm_act; \ - \ - const dma_addr_t src0_row = src0->data; \ - \ - const uint32_t tile_size = TILE_SIZE; \ - const uint32_t aligned_tile_size = hex_align_up(tile_size, 128); \ - \ - uint32_t n_k_tiles_w = ne00 / 32; \ - uint32_t n_k_tiles_a = ne10 / 32; \ - uint32_t tile_row_stride = n_k_tiles_w * tile_size; \ - uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; \ - \ - uint32_t ct_start = src0_start_row / 32; \ - uint32_t ct_end = (src0_end_row + 31) / 32; \ - \ - uint32_t push_ct = ct_start; \ - if (src0_start_row < src0_end_row) { \ - for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { \ - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, \ - src0_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - } \ - } \ - \ - if (src0_start_row >= src0_end_row) { \ - return; \ - } \ - \ - for (uint32_t ct = ct_start; ct < ct_end; ct++) { \ - const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; \ - \ - int valid_rows = (int)ne0 - (int)(ct * 32); \ - valid_rows = MIN(32, MAX(0, valid_rows)); \ - \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - uint32_t ir1 = 0; \ - for (; ir1 + 1 < act_nrows; ir1 += 2) { \ - const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (ir1+0) * act_stride); \ - const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (ir1+1) * act_stride); \ - float * restrict dst_row0 = (float *) (dst->data + ((cur_m_start + ir1+0) * dst_row_size)); \ - float * restrict dst_row1 = (float *) (dst->data + ((cur_m_start + ir1+1) * dst_row_size)); \ - \ - float * dst_ptr0 = &dst_row0[ct * 32]; \ - float * dst_ptr1 = &dst_row1[ct * 32]; \ - \ - const float * src2_ptr0 = NULL; \ - const float * src2_ptr1 = NULL; \ - if (src2) { \ - const float * restrict src2_row0 = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1+0) * src2_stride)); \ - const float * restrict src2_row1 = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1+1) * src2_stride)); \ - src2_ptr0 = &src2_row0[ct * 32]; \ - src2_ptr1 = &src2_row1[ct * 32]; \ - } \ - DOT_2X2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, src2_ptr0, src2_ptr1); \ - } \ - \ - for (; ir1 < act_nrows; ++ir1) { \ - const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); \ - float * restrict dst_row = (float *) (dst->data + ((cur_m_start + ir1) * dst_row_size)); \ - float * dst_ptr = &dst_row[ct * 32]; \ - \ - const float * src2_ptr = NULL; \ - if (src2) { \ - const float * restrict src2_row = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1) * src2_stride)); \ - src2_ptr = &src2_row[ct * 32]; \ - } \ - DOT_2X1(ne10, dst_ptr, w_tile, act_col, valid_rows, src2_ptr); \ - } \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - \ - if (push_ct < ct_end) { \ - dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), \ - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - push_ct++; \ - } \ - } \ -} +static void hvx_mm_2d_tiled(unsigned int nth, unsigned int ith, void * data) { + htp_matmul_preamble; + + const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; + const uint32_t act_nrows = mmctx->cur_m_rows ? mmctx->cur_m_rows : (ne11 * ne12 * ne13); + const uint32_t cur_m_start = mmctx->cur_m_start; + + const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; + const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; + const uint32_t n_prefetch = kparams->n_prefetch; + assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); + + const size_t dst_row_size = nb1; + const size_t act_row_size = nb11; + const size_t act_stride = mmctx->vtcm_act_stride; + const size_t src2_stride = src2 ? ((src2->ne[1] == 1) ? 0 : src2->nb[1]) : 0; + + uint8_t * restrict vtcm_dst_ptr = mmctx->vtcm_dst + mmctx->vtcm_dst_size_per_thread * ith; + uint8_t * restrict vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; + uint8_t * restrict act_data = mmctx->vtcm_act; + + const dma_addr_t src0_row = src0->data; + + const uint32_t tile_size = htp_tensor_get_tile_size(src0->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src0->type); + + uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src0->type); + uint32_t tile_row_stride = n_k_tiles_w * tile_size; + uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; -#define MATVEC_2D_REPACKED_IMPL(SUFFIX, TILE_SIZE, DOT_2X1) \ -static void hvx_mv_2d_repacked_##SUFFIX(unsigned int nth, unsigned int ith, void * data) { \ - htp_matmul_preamble; \ - \ - const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; \ - \ - const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; \ - const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); \ - \ - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ - \ - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; \ - const uint32_t n_prefetch = kparams->n_prefetch; \ - assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); \ - \ - const size_t dst_row_size = nb1; \ - const size_t act_row_size = nb11; \ - const size_t act_stride = mmctx->vtcm_act_stride; \ - \ - uint8_t * vtcm_dst_ptr = mmctx->vtcm_dst + mmctx->vtcm_dst_size_per_thread * ith; \ - uint8_t * vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; \ - uint8_t * act_data = mmctx->vtcm_act; \ - \ - float * tmp = (float *) vtcm_dst_ptr; \ - \ - const dma_addr_t src0_row = src0->data; \ - \ - const uint8_t * restrict act_col = (const uint8_t *) act_data; \ - float * restrict dst_col = (float *) dst->data; \ - \ - const uint32_t tile_size = TILE_SIZE; \ - const uint32_t aligned_tile_size = hex_align_up(tile_size, 128); \ - \ - uint32_t n_k_tiles_w = ne00 / 32; \ - uint32_t n_k_tiles_a = ne10 / 32; \ - uint32_t tile_row_stride = n_k_tiles_w * tile_size; \ - uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; \ - \ - uint32_t ct_start = src0_start_row / 32; \ - uint32_t ct_end = (src0_end_row + 31) / 32; \ - \ - uint32_t push_ct = ct_start; \ - if (src0_start_row < src0_end_row) { \ - if (src2) { \ - float * vtcm_bias_ptr = (float *) mmctx->vtcm_bias + src0_start_row; \ - const dma_addr_t src2_addr = src2->data + src0_start_row * sizeof(float); \ - int slice_size = (int)MIN(src0_end_row, ne0) - (int)src0_start_row; \ - if (slice_size > 0) { \ - dma_queue_push(dma_q, dma_make_data(vtcm_bias_ptr, src2_addr), \ - slice_size * sizeof(float), slice_size * sizeof(float), slice_size * sizeof(float), 1); \ - dma_queue_pop_nowait(dma_q); \ - } \ - } \ - for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { \ - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, \ - src0_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - } \ - } \ - \ - if (src0_start_row >= src0_end_row) { \ - return; \ - } \ - \ - for (uint32_t ct = ct_start; ct < ct_end; ct++) { \ - const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; \ - \ - float * dst_ptr = &tmp[ct * 32 - src0_start_row]; \ - int valid_rows = (int)ne0 - (int)(ct * 32); \ - valid_rows = MIN(32, MAX(0, valid_rows)); \ - \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - DOT_2X1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - \ - if (push_ct < ct_end) { \ - dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), \ - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - push_ct++; \ - } \ - } \ - \ - int copy_cnt = (int)MIN(src0_end_row, ne0) - (int)src0_start_row; \ - if (copy_cnt > 0) { \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct_end); \ - if (src2) { \ - hvx_add_f32_uuu((uint8_t *) &dst_col[src0_start_row], \ - (const uint8_t *) tmp, \ - (const uint8_t *) ((const float *) mmctx->vtcm_bias + src0_start_row), \ - copy_cnt); \ - } else { \ - hvx_copy_f32_ua((uint8_t *) &dst_col[src0_start_row], (uint8_t *) tmp, copy_cnt); \ - } \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct_end); \ - } \ + uint32_t ct_start = src0_start_row / 32; + uint32_t ct_end = (src0_end_row + 31) / 32; + + uint32_t push_ct = ct_start; + if (src0_start_row < src0_end_row) { + for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { + dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, + src0_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + } + } + + if (src0_start_row >= src0_end_row) { + return; + } + + for (uint32_t ct = ct_start; ct < ct_end; ct++) { + const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; + + int valid_rows = (int)ne0 - (int)(ct * 32); + valid_rows = MIN(32, MAX(0, valid_rows)); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); + uint32_t ir1 = 0; + for (; ir1 + 1 < act_nrows; ir1 += 2) { + const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (ir1+0) * act_stride); + const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (ir1+1) * act_stride); + float * restrict dst_row0 = (float *) (dst->data + ((cur_m_start + ir1+0) * dst_row_size)); + float * restrict dst_row1 = (float *) (dst->data + ((cur_m_start + ir1+1) * dst_row_size)); + + float * dst_ptr0 = &dst_row0[ct * 32]; + float * dst_ptr1 = &dst_row1[ct * 32]; + + const float * src2_ptr0 = NULL; + const float * src2_ptr1 = NULL; + if (src2) { + const float * restrict src2_row0 = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1+0) * src2_stride)); + const float * restrict src2_row1 = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1+1) * src2_stride)); + src2_ptr0 = &src2_row0[ct * 32]; + src2_ptr1 = &src2_row1[ct * 32]; + } + mmctx->vec_dot_32x2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, src2_ptr0, src2_ptr1); + } + + for (; ir1 < act_nrows; ++ir1) { + const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); + float * restrict dst_row = (float *) (dst->data + ((cur_m_start + ir1) * dst_row_size)); + float * dst_ptr = &dst_row[ct * 32]; + + const float * src2_ptr = NULL; + if (src2) { + const float * restrict src2_row = (const float *) ((const uint8_t *) src2->data + ((cur_m_start + ir1) * src2_stride)); + src2_ptr = &src2_row[ct * 32]; + } + mmctx->vec_dot_32x1(ne10, dst_ptr, w_tile, act_col, valid_rows, src2_ptr); + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); + + if (push_ct < ct_end) { + dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + push_ct++; + } + } } -#define MATMUL_NX_2D_REPACKED_IMPL(SUFFIX, TILE_SIZE, DOT_2X2, DOT_2X1) \ -static void hvx_mm_nx_2d_repacked_##SUFFIX(unsigned int nth, unsigned int ith, void * data) { \ - struct htp_mm_context * mmctx = data; \ - struct htp_ops_context * octx = mmctx->octx; \ - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; \ - const uint32_t n_weights = kparams->n_weights; \ - \ - const struct htp_tensor * restrict act = octx->src[n_weights]; /* x */ \ - const uint32_t ne10 = act->ne[0]; \ - const uint32_t act_nrows = act->ne[1] * act->ne[2] * act->ne[3]; \ - const size_t act_stride = mmctx->vtcm_act_stride; \ - \ - uint8_t * restrict vtcm_weight_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; \ - uint8_t * restrict act_data = mmctx->vtcm_act; \ - \ - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ - const uint32_t n_prefetch = kparams->n_prefetch; \ - assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); \ - \ - const uint32_t tile_size = TILE_SIZE; \ - const uint32_t aligned_tile_size = hex_align_up(tile_size, 128); \ - uint32_t n_k_tiles_a = ne10 / 32; \ - uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; \ - \ - for (uint32_t widx = 0; widx < n_weights; widx++) { \ - const struct htp_tensor * restrict src_w = octx->src[widx]; \ - const struct htp_tensor * restrict dst = octx->dsts[widx]; \ - if (!src_w || !dst) continue; \ - dma_queue * dma_q = octx->ctx->dma[ith]; \ - \ - const uint32_t ne00 = src_w->ne[0]; \ - const uint32_t ne01 = src_w->ne[1]; \ - const size_t dst_row_size = dst->nb[1]; \ - const dma_addr_t src_w_row = src_w->data; \ - \ - uint32_t n_k_tiles_w = ne00 / 32; \ - uint32_t tile_row_stride = n_k_tiles_w * tile_size; \ - \ - uint32_t src0_start_row = 0; \ - uint32_t src0_end_row = ne01; \ - if (octx->ctx->mdev.count > 1) { \ - const bool can_split = htp_tensor_can_row_partition(dst, sizeof(float)); \ - const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(ne01, can_split ? 32 : 0, \ - octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); \ - src0_start_row = range.start; \ - src0_end_row = range.start + range.count; \ - } \ - \ - const uint32_t nrows = src0_end_row - src0_start_row; \ - uint32_t src0_nrows_per_thread = fastdiv(nrows + nth - 1, &octx->n_threads_div); \ - src0_nrows_per_thread = hex_round_up(src0_nrows_per_thread, 32); \ - \ - const uint32_t start_row = src0_start_row + src0_nrows_per_thread * ith; \ - const uint32_t end_row = MIN(start_row + src0_nrows_per_thread, src0_end_row); \ - if (start_row >= end_row) continue; \ - \ - uint32_t ct_start = start_row / 32; \ - uint32_t ct_end = (end_row + 31) / 32; \ - \ - uint32_t push_ct = ct_start; \ - for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { \ - dma_queue_push(dma_q, dma_make_data(vtcm_weight_ptr + d * tile_row_transfer_size_aligned, \ - src_w_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - } \ - \ - for (uint32_t ct = ct_start; ct < ct_end; ct++) { \ - const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; \ - int valid_rows = (int)ne01 - (int)(ct * 32); \ - valid_rows = MIN(32, MAX(0, valid_rows)); \ - \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - uint32_t ir1 = 0; \ - for (; ir1 + 1 < act_nrows; ir1 += 2) { \ - const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (ir1+0) * act_stride); \ - const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (ir1+1) * act_stride); \ - \ - float * restrict dst_row0 = (float *) (dst->data + ((ir1+0) * dst_row_size)); \ - float * restrict dst_row1 = (float *) (dst->data + ((ir1+1) * dst_row_size)); \ - float * dst_ptr0 = &dst_row0[ct * 32]; \ - float * dst_ptr1 = &dst_row1[ct * 32]; \ - \ - DOT_2X2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, NULL, NULL); \ - } \ - \ - for (; ir1 < act_nrows; ++ir1) { \ - const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); \ - float * restrict dst_row = (float *) (dst->data + (ir1 * dst_row_size)); \ - float * dst_ptr = &dst_row[ct * 32]; \ - DOT_2X1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); \ - } \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - \ - if (push_ct < ct_end) { \ - dma_queue_push(dma_q, dma_make_data(w_tile, src_w_row + push_ct * tile_row_stride), \ - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - push_ct++; \ - } \ - } \ - } \ +static void hvx_mv_2d_tiled(unsigned int nth, unsigned int ith, void * data) { + htp_matmul_preamble; + + const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; + + const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; + const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; + const uint32_t n_prefetch = kparams->n_prefetch; + assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); + + const size_t dst_row_size = nb1; + const size_t act_row_size = nb11; + const size_t act_stride = mmctx->vtcm_act_stride; + + uint8_t * vtcm_dst_ptr = mmctx->vtcm_dst + mmctx->vtcm_dst_size_per_thread * ith; + uint8_t * vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; + uint8_t * act_data = mmctx->vtcm_act; + + float * tmp = (float *) vtcm_dst_ptr; + + const dma_addr_t src0_row = src0->data; + + const uint8_t * restrict act_col = (const uint8_t *) act_data; + float * restrict dst_col = (float *) dst->data; + + const uint32_t tile_size = htp_tensor_get_tile_size(src0->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src0->type); + + uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src0->type); + uint32_t tile_row_stride = n_k_tiles_w * tile_size; + uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; + + uint32_t ct_start = src0_start_row / 32; + uint32_t ct_end = (src0_end_row + 31) / 32; + + uint32_t push_ct = ct_start; + if (src0_start_row < src0_end_row) { + if (src2) { + float * vtcm_bias_ptr = (float *) mmctx->vtcm_bias + src0_start_row; + const dma_addr_t src2_addr = src2->data + src0_start_row * sizeof(float); + int slice_size = (int)MIN(src0_end_row, ne0) - (int)src0_start_row; + if (slice_size > 0) { + dma_queue_push(dma_q, dma_make_data(vtcm_bias_ptr, src2_addr), + slice_size * sizeof(float), slice_size * sizeof(float), slice_size * sizeof(float), 1); + dma_queue_pop_nowait(dma_q); + } + } + for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { + dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, + src0_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + } + } + + if (src0_start_row >= src0_end_row) { + return; + } + + for (uint32_t ct = ct_start; ct < ct_end; ct++) { + const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; + + float * dst_ptr = &tmp[ct * 32 - src0_start_row]; + int valid_rows = (int)ne0 - (int)(ct * 32); + valid_rows = MIN(32, MAX(0, valid_rows)); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); + mmctx->vec_dot_32x1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); + + if (push_ct < ct_end) { + dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + push_ct++; + } + } + + int copy_cnt = (int)MIN(src0_end_row, ne0) - (int)src0_start_row; + if (copy_cnt > 0) { + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct_end); + if (src2) { + hvx_add_f32_uuu((uint8_t *) &dst_col[src0_start_row], + (const uint8_t *) tmp, + (const uint8_t *) ((const float *) mmctx->vtcm_bias + src0_start_row), + copy_cnt); + } else { + hvx_copy_f32_ua((uint8_t *) &dst_col[src0_start_row], (uint8_t *) tmp, copy_cnt); + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct_end); + } } -MATMUL_2D_REPACKED_IMPL(q4_0, 576, tiled_vec_dot_q4_0_32x2, tiled_vec_dot_q4_0_32x1) -MATMUL_2D_REPACKED_IMPL(q4_1, 640, tiled_vec_dot_q4_1_32x2, tiled_vec_dot_q4_1_32x1) -MATMUL_2D_REPACKED_IMPL(q8_0, 1088, tiled_vec_dot_q8_0_32x2, tiled_vec_dot_q8_0_32x1) -MATMUL_2D_REPACKED_IMPL(q6_k, 896, tiled_vec_dot_q6_k_32x2, tiled_vec_dot_q6_k_32x1) -MATMUL_2D_REPACKED_IMPL(q5_k, 768, tiled_vec_dot_q5_k_32x2, tiled_vec_dot_q5_k_32x1) -MATMUL_2D_REPACKED_IMPL(q3_k, 512, tiled_vec_dot_q3_k_32x2, tiled_vec_dot_q3_k_32x1) -MATMUL_2D_REPACKED_IMPL(q2_k, 336, tiled_vec_dot_q2_k_32x2, tiled_vec_dot_q2_k_32x1) -MATMUL_2D_REPACKED_IMPL(iq4nl, 576, tiled_vec_dot_iq4nl_32x2, tiled_vec_dot_iq4nl_32x1) -MATMUL_2D_REPACKED_IMPL(mxfp4, 544, tiled_vec_dot_mxfp4_32x2, tiled_vec_dot_mxfp4_32x1) +static void hvx_mm_nx_2d_tiled(unsigned int nth, unsigned int ith, void * data) { + struct htp_mm_context * mmctx = data; + struct htp_ops_context * octx = mmctx->octx; + const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; + const uint32_t n_weights = kparams->n_weights; + + const struct htp_tensor * restrict act = octx->src[n_weights]; /* x */ + const uint32_t ne10 = act->ne[0]; + const uint32_t act_nrows = act->ne[1] * act->ne[2] * act->ne[3]; + const size_t act_stride = mmctx->vtcm_act_stride; + + uint8_t * restrict vtcm_weight_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; + uint8_t * restrict act_data = mmctx->vtcm_act; + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + const uint32_t n_prefetch = kparams->n_prefetch; + assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); + + for (uint32_t widx = 0; widx < n_weights; widx++) { + const struct htp_tensor * restrict src_w = octx->src[widx]; + const struct htp_tensor * restrict dst = octx->dsts[widx]; + if (!src_w || !dst) continue; + dma_queue * dma_q = octx->ctx->dma[ith]; + + const uint32_t tile_size = htp_tensor_get_tile_size(src_w->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src_w->type); + const uint32_t ne00 = src_w->ne[0]; + const uint32_t ne01 = src_w->ne[1]; + const size_t dst_row_size = dst->nb[1]; + const dma_addr_t src_w_row = src_w->data; + + const uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src_w->type); + const uint32_t tile_row_stride = n_k_tiles_w * tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; + + uint32_t src0_start_row = 0; + uint32_t src0_end_row = ne01; + if (octx->ctx->mdev.count > 1) { + const bool can_split = htp_tensor_can_row_partition(dst, sizeof(float)); + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(ne01, can_split ? 32 : 0, + octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + src0_start_row = range.start; + src0_end_row = range.start + range.count; + } + + const uint32_t nrows = src0_end_row - src0_start_row; + uint32_t src0_nrows_per_thread = fastdiv(nrows + nth - 1, &octx->n_threads_div); + src0_nrows_per_thread = hex_round_up(src0_nrows_per_thread, 32); + + const uint32_t start_row = src0_start_row + src0_nrows_per_thread * ith; + const uint32_t end_row = MIN(start_row + src0_nrows_per_thread, src0_end_row); + if (start_row >= end_row) continue; + + uint32_t ct_start = start_row / 32; + uint32_t ct_end = (end_row + 31) / 32; + + uint32_t push_ct = ct_start; + for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { + dma_queue_push(dma_q, dma_make_data(vtcm_weight_ptr + d * tile_row_transfer_size_aligned, + src_w_row + push_ct * tile_row_stride), aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + } + + for (uint32_t ct = ct_start; ct < ct_end; ct++) { + const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; + int valid_rows = (int)dst->ne[0] - (int)(ct * 32); + valid_rows = MIN(32, MAX(0, valid_rows)); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); + uint32_t ir1 = 0; + for (; ir1 + 1 < act_nrows; ir1 += 2) { + const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (ir1+0) * act_stride); + const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (ir1+1) * act_stride); + + float * restrict dst_row0 = (float *) (dst->data + ((ir1+0) * dst_row_size)); + float * restrict dst_row1 = (float *) (dst->data + ((ir1+1) * dst_row_size)); + float * dst_ptr0 = &dst_row0[ct * 32]; + float * dst_ptr1 = &dst_row1[ct * 32]; + + mmctx->vec_dot_32x2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, NULL, NULL); + } + + for (; ir1 < act_nrows; ++ir1) { + const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); + float * restrict dst_row = (float *) (dst->data + (ir1 * dst_row_size)); + float * dst_ptr = &dst_row[ct * 32]; + mmctx->vec_dot_32x1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); + + if (push_ct < ct_end) { + dma_queue_push(dma_q, dma_make_data(w_tile, src_w_row + push_ct * tile_row_stride), + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + push_ct++; + } + } + } +} static void hvx_mm_transfer_act_dma( struct htp_ops_context * octx, @@ -649,12 +641,14 @@ static void name(unsigned int nth, unsigned int ith, void * data) { htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_QUANT, ir_first); \ } -QUANTIZE_IMPL(quantize_f32_q8_0_tiled, "quantize-f32-q8_0_tiled", quantize_f32_q8_0_tiled_kernel, htp_mm_q8_0_tiled_row_size(ne0)) -QUANTIZE_IMPL(quantize_f32_q8_1_tiled, "quantize-f32-q8_1_tiled", quantize_f32_q8_1_tiled_kernel, htp_mm_q8_1_tiled_row_size(ne0)) +QUANTIZE_IMPL(quantize_f32_q8_0_tiled, "quantize-f32-q8_0_tiled", quantize_f32_q8_0_tiled_kernel, htp_mm_q8_0_tiled_row_size(ne0)) +QUANTIZE_IMPL(quantize_f32_q8_1_tiled, "quantize-f32-q8_1_tiled", quantize_f32_q8_1_tiled_kernel, htp_mm_q8_1_tiled_row_size(ne0)) QUANTIZE_IMPL(quantize_f32_q8_1_s16_tiled, "quantize-f32-q8_1_s16_tiled", quantize_f32_q8_1_s16_tiled_kernel, htp_mm_q8_1_tiled_row_size(ne0)) -QUANTIZE_IMPL(quantize_f32_f32, "quantize-f32-f32", quantize_f32_f32_kernel, mmctx->vtcm_act_stride) -QUANTIZE_IMPL(quantize_f32_f16, "quantize-f32-f16", quantize_f32_f16_kernel, mmctx->vtcm_act_stride) -QUANTIZE_IMPL(quantize_f16_f16, "quantize-f16-f16", quantize_f16_f16_kernel, mmctx->vtcm_act_stride) +QUANTIZE_IMPL(quantize_f32_f16_tiled, "quantize-f32-f16_tiled", quantize_f32_f16_tiled_kernel, htp_mm_f16_tiled_row_size(ne0)) +QUANTIZE_IMPL(quantize_f16_f16_tiled, "quantize-f16-f16_tiled", quantize_f16_f16_tiled_kernel, htp_mm_f16_tiled_row_size(ne0)) +QUANTIZE_IMPL(quantize_f32_f32, "quantize-f32-f32", quantize_f32_f32_kernel, mmctx->vtcm_act_stride) +QUANTIZE_IMPL(quantize_f32_f16, "quantize-f32-f16", quantize_f32_f16_kernel, mmctx->vtcm_act_stride) +QUANTIZE_IMPL(quantize_f16_f16, "quantize-f16-f16", quantize_f16_f16_kernel, mmctx->vtcm_act_stride) static void quantize_f32_q8_0_tiled_block(unsigned int nth, unsigned int ith, void * data) { (void) nth; @@ -740,178 +734,208 @@ static void quantize_f32_q8_1_s16_tiled_block(unsigned int nth, unsigned int ith htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_QUANT, mmctx->quant_ib_first[ith]); } -// q8_1 for weight types with offsets (q8_1_s16 for Q2_K), otherwise q8_0 -static inline worker_callback_t htp_mm_act_quant_row_func(int weight_type) { +static void quantize_f32_f16_tiled_block(unsigned int nth, unsigned int ith, void * data) { + (void) nth; + struct htp_mm_context * mmctx = data; + if (mmctx->quant_ib_first[ith] >= mmctx->quant_ib_last[ith]) { + return; + } + struct htp_ops_context * octx = mmctx->octx; + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_QUANT, mmctx->quant_ib_first[ith]); + + const struct htp_tensor * src = mmctx->act; + + quantize_f32_f16_tiled_block_kernel( + (const float *) mmctx->vtcm_act_raw, + mmctx->vtcm_act, + NULL, + src->ne[0], + mmctx->quant_ib_first[ith], + mmctx->quant_ib_last[ith], + mmctx->vtcm_act_raw_stride, + htp_mm_f16_tiled_row_size(src->ne[0]), + mmctx->quant_r[ith], + mmctx->quant_c[ith] + ); + + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_QUANT, mmctx->quant_ib_first[ith]); +} + +static void quantize_f16_f16_tiled_block(unsigned int nth, unsigned int ith, void * data) { + (void) nth; + struct htp_mm_context * mmctx = data; + if (mmctx->quant_ib_first[ith] >= mmctx->quant_ib_last[ith]) { + return; + } + struct htp_ops_context * octx = mmctx->octx; + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_QUANT, mmctx->quant_ib_first[ith]); + + const struct htp_tensor * src = mmctx->act; + + quantize_f16_f16_tiled_block_kernel( + (const __fp16 *) mmctx->vtcm_act_raw, + mmctx->vtcm_act, + NULL, + src->ne[0], + mmctx->quant_ib_first[ith], + mmctx->quant_ib_last[ith], + mmctx->vtcm_act_raw_stride, + htp_mm_f16_tiled_row_size(src->ne[0]), + mmctx->quant_r[ith], + mmctx->quant_c[ith] + ); + + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_QUANT, mmctx->quant_ib_first[ith]); +} + +// q8_1 for weight types with offsets (q8_1_s16 for Q2_K), f16_tiled for F16, otherwise q8_0 +static inline worker_callback_t htp_mm_act_quant_row_func(int weight_type, int act_type) { + if (weight_type == HTP_TYPE_F16) { + return (act_type == HTP_TYPE_F16) ? quantize_f16_f16_tiled : quantize_f32_f16_tiled; + } if (weight_type == HTP_TYPE_Q2_K) { return quantize_f32_q8_1_s16_tiled; } return htp_mm_weight_has_offset(weight_type) ? quantize_f32_q8_1_tiled : quantize_f32_q8_0_tiled; } -static inline worker_callback_t htp_mm_act_quant_block_func(int weight_type) { +static inline worker_callback_t htp_mm_act_quant_block_func(int weight_type, int act_type) { + if (weight_type == HTP_TYPE_F16) { + return (act_type == HTP_TYPE_F16) ? quantize_f16_f16_tiled_block : quantize_f32_f16_tiled_block; + } if (weight_type == HTP_TYPE_Q2_K) { return quantize_f32_q8_1_s16_tiled_block; } return htp_mm_weight_has_offset(weight_type) ? quantize_f32_q8_1_tiled_block : quantize_f32_q8_0_tiled_block; } -MATVEC_2D_REPACKED_IMPL(q4_0, 576, tiled_vec_dot_q4_0_32x1) -MATVEC_2D_REPACKED_IMPL(q4_1, 640, tiled_vec_dot_q4_1_32x1) -MATVEC_2D_REPACKED_IMPL(q8_0, 1088, tiled_vec_dot_q8_0_32x1) -MATVEC_2D_REPACKED_IMPL(q5_k, 768, tiled_vec_dot_q5_k_32x1) -MATVEC_2D_REPACKED_IMPL(q6_k, 896, tiled_vec_dot_q6_k_32x1) -MATVEC_2D_REPACKED_IMPL(q3_k, 512, tiled_vec_dot_q3_k_32x1) -MATVEC_2D_REPACKED_IMPL(q2_k, 336, tiled_vec_dot_q2_k_32x1) -MATVEC_2D_REPACKED_IMPL(iq4nl, 576, tiled_vec_dot_iq4nl_32x1) -MATVEC_2D_REPACKED_IMPL(mxfp4, 544, tiled_vec_dot_mxfp4_32x1) - -MATMUL_NX_2D_REPACKED_IMPL(q4_0, 576, tiled_vec_dot_q4_0_32x2, tiled_vec_dot_q4_0_32x1) -MATMUL_NX_2D_REPACKED_IMPL(q4_1, 640, tiled_vec_dot_q4_1_32x2, tiled_vec_dot_q4_1_32x1) -MATMUL_NX_2D_REPACKED_IMPL(q8_0, 1088, tiled_vec_dot_q8_0_32x2, tiled_vec_dot_q8_0_32x1) -MATMUL_NX_2D_REPACKED_IMPL(iq4nl, 576, tiled_vec_dot_iq4nl_32x2, tiled_vec_dot_iq4nl_32x1) -MATMUL_NX_2D_REPACKED_IMPL(mxfp4, 544, tiled_vec_dot_mxfp4_32x2, tiled_vec_dot_mxfp4_32x1) -MATMUL_NX_2D_REPACKED_IMPL(q5_k, 768, tiled_vec_dot_q5_k_32x2, tiled_vec_dot_q5_k_32x1) -MATMUL_NX_2D_REPACKED_IMPL(q3_k, 512, tiled_vec_dot_q3_k_32x2, tiled_vec_dot_q3_k_32x1) -MATMUL_NX_2D_REPACKED_IMPL(q2_k, 336, tiled_vec_dot_q2_k_32x2, tiled_vec_dot_q2_k_32x1) - -#define MATMUL_4D_REPACKED_IMPL(SUFFIX, TILE_SIZE, DOT_2X2, DOT_2X1) \ -static void hvx_mm_4d_repacked_##SUFFIX(unsigned int nth, unsigned int ith, void * data) { \ - htp_matmul_preamble; \ - \ - const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; \ - const uint32_t cur_m_rows = mmctx->cur_m_rows ? mmctx->cur_m_rows : (ne11 * ne12 * ne13); \ - const uint32_t cur_m_start = mmctx->cur_m_start; \ - \ - const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; \ - const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); \ - \ - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; \ - \ - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; \ - const uint32_t n_prefetch = kparams->n_prefetch; \ - assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); \ - \ - const size_t dst_row_size = nb1; \ - const size_t act_stride = mmctx->vtcm_act_stride; \ - \ - uint8_t * restrict vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; \ - uint8_t * restrict act_data = mmctx->vtcm_act; \ - \ - const uint32_t tile_size = TILE_SIZE; \ - const uint32_t aligned_tile_size = hex_align_up(tile_size, 128); \ - \ - const uint32_t n_k_tiles_w = ne00 / 32; \ - const uint32_t n_k_tiles_a = ne10 / 32; \ - const uint32_t tile_row_stride = n_k_tiles_w * tile_size; \ - const uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; \ - const uint32_t src0_slice_stride = ((ne01 + 31) / 32) * tile_row_stride; \ - \ - const uint32_t ct_start = src0_start_row / 32; \ - const uint32_t ct_end = (src0_end_row + 31) / 32; \ - \ - \ - if (src0_start_row >= src0_end_row || cur_m_rows == 0) { \ - return; \ - } \ - \ - const uint32_t total_batches = ne12 * ne13; \ - const uint32_t b_start = fastdiv(cur_m_start, &kparams->div_ne1); \ - uint32_t b_end = fastdiv(cur_m_start + cur_m_rows + ne11 - 1, &kparams->div_ne1); \ - b_end = MIN(b_end, total_batches); \ - \ - uint32_t b_grp_start = b_start; \ - while (b_grp_start < b_end) { \ - const uint32_t b3 = fastdiv(b_grp_start, &kparams->div_ne12); \ - const uint32_t b2 = b_grp_start - b3 * ne12; \ - const uint32_t i02 = fastdiv(b2, &kparams->div_r2); \ - const uint32_t i03 = fastdiv(b3, &kparams->div_r3); \ - \ - uint32_t b_grp_end = b_grp_start + 1; \ - while (b_grp_end < b_end) { \ - const uint32_t cur_b3 = fastdiv(b_grp_end, &kparams->div_ne12); \ - const uint32_t cur_b2 = b_grp_end - cur_b3 * ne12; \ - const uint32_t cur_i02 = fastdiv(cur_b2, &kparams->div_r2); \ - const uint32_t cur_i03 = fastdiv(cur_b3, &kparams->div_r3); \ - if (cur_i02 != i02 || cur_i03 != i03) { \ - break; \ - } \ - b_grp_end++; \ - } \ - \ - const uint32_t slice_idx = i03 * ne02 + i02; \ - const dma_addr_t src0_slice = src0->data + (size_t) slice_idx * src0_slice_stride; \ - \ - uint32_t push_ct = ct_start; \ - for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { \ - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, \ - src0_slice + (size_t) push_ct * tile_row_stride), \ - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - } \ - \ - for (uint32_t ct = ct_start; ct < ct_end; ct++) { \ - const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; \ - \ - int valid_rows = (int)ne0 - (int)(ct * 32); \ - valid_rows = MIN(32, MAX(0, valid_rows)); \ - \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - for (uint32_t b = b_grp_start; b < b_grp_end; b++) { \ - const uint32_t b_m_start = b * ne11; \ - const uint32_t m_first = MAX(cur_m_start, b_m_start); \ - const uint32_t m_last = MIN(cur_m_start + cur_m_rows, b_m_start + ne11); \ - if (m_first >= m_last) continue; \ - \ - const uint32_t cur_b3 = fastdiv(b, &kparams->div_ne12); \ - const uint32_t cur_b2 = b - cur_b3 * ne12; \ - uint8_t * dst_batch_base = (uint8_t *) dst->data + (size_t) cur_b2 * nb2 + (size_t) cur_b3 * nb3; \ - \ - const uint32_t chunk_m_offset = m_first - cur_m_start; \ - const uint32_t dst_m_offset = m_first - b_m_start; \ - const uint32_t batch_nrows = m_last - m_first; \ - \ - uint32_t ir1 = 0; \ - for (; ir1 + 1 < batch_nrows; ir1 += 2) { \ - const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (chunk_m_offset + ir1 + 0) * act_stride); \ - const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (chunk_m_offset + ir1 + 1) * act_stride); \ - float * restrict dst_row0 = (float *) (dst_batch_base + (dst_m_offset + ir1 + 0) * dst_row_size); \ - float * restrict dst_row1 = (float *) (dst_batch_base + (dst_m_offset + ir1 + 1) * dst_row_size); \ - float * dst_ptr0 = &dst_row0[ct * 32]; \ - float * dst_ptr1 = &dst_row1[ct * 32]; \ - DOT_2X2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, NULL, NULL); \ - } \ - for (; ir1 < batch_nrows; ++ir1) { \ - const uint8_t * restrict act_col = (const uint8_t *) (act_data + (chunk_m_offset + ir1) * act_stride); \ - float * restrict dst_row = (float *) (dst_batch_base + (dst_m_offset + ir1) * dst_row_size); \ - float * dst_ptr = &dst_row[ct * 32]; \ - DOT_2X1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); \ - } \ - } \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); \ - \ - if (push_ct < ct_end) { \ - dma_queue_push(dma_q, dma_make_data(w_tile, src0_slice + (size_t) push_ct * tile_row_stride), \ - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); \ - push_ct++; \ - } \ - } \ - b_grp_start = b_grp_end; \ - } \ - if (src2) { \ - hvx_tensor_add_f32_grid(dst, src2, cur_m_start, cur_m_start + cur_m_rows, src0_start_row, src0_end_row, &kparams->div_ne12_ne1, &kparams->div_ne1); \ - } \ +static void hvx_mm_4d_tiled(unsigned int nth, unsigned int ith, void * data) { + htp_matmul_preamble; + + const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; + const uint32_t cur_m_rows = mmctx->cur_m_rows ? mmctx->cur_m_rows : (ne11 * ne12 * ne13); + const uint32_t cur_m_start = mmctx->cur_m_start; + + const uint32_t src0_start_row = mmctx->src0_row_start + src0_nrows_per_thread * ith; + const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, mmctx->src0_row_end); + + struct htp_thread_trace * tr = &octx->ctx->trace[ith]; + + const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; + const uint32_t n_prefetch = kparams->n_prefetch; + assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); + + const size_t dst_row_size = nb1; + const size_t act_stride = mmctx->vtcm_act_stride; + + uint8_t * restrict vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; + uint8_t * restrict act_data = mmctx->vtcm_act; + + const uint32_t tile_size = htp_tensor_get_tile_size(src0->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src0->type); + + const uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src0->type); + const uint32_t tile_row_stride = n_k_tiles_w * tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; + const uint32_t src0_slice_stride = ((ne01 + 31) / 32) * tile_row_stride; + + const uint32_t ct_start = src0_start_row / 32; + const uint32_t ct_end = (src0_end_row + 31) / 32; + + if (src0_start_row >= src0_end_row || cur_m_rows == 0) { + return; + } + + const uint32_t total_batches = ne12 * ne13; + const uint32_t b_start = fastdiv(cur_m_start, &kparams->div_ne1); + uint32_t b_end = fastdiv(cur_m_start + cur_m_rows + ne11 - 1, &kparams->div_ne1); + b_end = MIN(b_end, total_batches); + + uint32_t b_grp_start = b_start; + while (b_grp_start < b_end) { + const uint32_t b3 = fastdiv(b_grp_start, &kparams->div_ne12); + const uint32_t b2 = b_grp_start - b3 * ne12; + const uint32_t i02 = fastdiv(b2, &kparams->div_r2); + const uint32_t i03 = fastdiv(b3, &kparams->div_r3); + + uint32_t b_grp_end = b_grp_start + 1; + while (b_grp_end < b_end) { + const uint32_t cur_b3 = fastdiv(b_grp_end, &kparams->div_ne12); + const uint32_t cur_b2 = b_grp_end - cur_b3 * ne12; + const uint32_t cur_i02 = fastdiv(cur_b2, &kparams->div_r2); + const uint32_t cur_i03 = fastdiv(cur_b3, &kparams->div_r3); + if (cur_i02 != i02 || cur_i03 != i03) { + break; + } + b_grp_end++; + } + + const uint32_t slice_idx = i03 * ne02 + i02; + const dma_addr_t src0_slice = src0->data + (size_t) slice_idx * src0_slice_stride; + + uint32_t push_ct = ct_start; + for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { + dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, + src0_slice + (size_t) push_ct * tile_row_stride), + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + } + + for (uint32_t ct = ct_start; ct < ct_end; ct++) { + const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; + + int valid_rows = (int)ne0 - (int)(ct * 32); + valid_rows = MIN(32, MAX(0, valid_rows)); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); + for (uint32_t b = b_grp_start; b < b_grp_end; b++) { + const uint32_t b_m_start = b * ne11; + const uint32_t m_first = MAX(cur_m_start, b_m_start); + const uint32_t m_last = MIN(cur_m_start + cur_m_rows, b_m_start + ne11); + if (m_first >= m_last) continue; + + const uint32_t cur_b3 = fastdiv(b, &kparams->div_ne12); + const uint32_t cur_b2 = b - cur_b3 * ne12; + uint8_t * dst_batch_base = (uint8_t *) dst->data + (size_t) cur_b2 * nb2 + (size_t) cur_b3 * nb3; + + const uint32_t chunk_m_offset = m_first - cur_m_start; + const uint32_t dst_m_offset = m_first - b_m_start; + const uint32_t batch_nrows = m_last - m_first; + + uint32_t ir1 = 0; + for (; ir1 + 1 < batch_nrows; ir1 += 2) { + const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (chunk_m_offset + ir1 + 0) * act_stride); + const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (chunk_m_offset + ir1 + 1) * act_stride); + float * restrict dst_row0 = (float *) (dst_batch_base + (dst_m_offset + ir1 + 0) * dst_row_size); + float * restrict dst_row1 = (float *) (dst_batch_base + (dst_m_offset + ir1 + 1) * dst_row_size); + float * dst_ptr0 = &dst_row0[ct * 32]; + float * dst_ptr1 = &dst_row1[ct * 32]; + mmctx->vec_dot_32x2(ne10, dst_ptr0, dst_ptr1, w_tile, act_col0, act_col1, valid_rows, NULL, NULL); + } + for (; ir1 < batch_nrows; ++ir1) { + const uint8_t * restrict act_col = (const uint8_t *) (act_data + (chunk_m_offset + ir1) * act_stride); + float * restrict dst_row = (float *) (dst_batch_base + (dst_m_offset + ir1) * dst_row_size); + float * dst_ptr = &dst_row[ct * 32]; + mmctx->vec_dot_32x1(ne10, dst_ptr, w_tile, act_col, valid_rows, NULL); + } + } + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ct); + + if (push_ct < ct_end) { + dma_queue_push(dma_q, dma_make_data(w_tile, src0_slice + (size_t) push_ct * tile_row_stride), + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); + push_ct++; + } + } + b_grp_start = b_grp_end; + } + if (src2) { + hvx_tensor_add_f32_grid(dst, src2, cur_m_start, cur_m_start + cur_m_rows, src0_start_row, src0_end_row, &kparams->div_ne12_ne1, &kparams->div_ne1); + } } -MATMUL_4D_REPACKED_IMPL(q4_0, 576, tiled_vec_dot_q4_0_32x2, tiled_vec_dot_q4_0_32x1) -MATMUL_4D_REPACKED_IMPL(q4_1, 640, tiled_vec_dot_q4_1_32x2, tiled_vec_dot_q4_1_32x1) -MATMUL_4D_REPACKED_IMPL(q8_0, 1088, tiled_vec_dot_q8_0_32x2, tiled_vec_dot_q8_0_32x1) -MATMUL_4D_REPACKED_IMPL(q6_k, 896, tiled_vec_dot_q6_k_32x2, tiled_vec_dot_q6_k_32x1) -MATMUL_4D_REPACKED_IMPL(q5_k, 768, tiled_vec_dot_q5_k_32x2, tiled_vec_dot_q5_k_32x1) -MATMUL_4D_REPACKED_IMPL(q3_k, 512, tiled_vec_dot_q3_k_32x2, tiled_vec_dot_q3_k_32x1) -MATMUL_4D_REPACKED_IMPL(q2_k, 336, tiled_vec_dot_q2_k_32x2, tiled_vec_dot_q2_k_32x1) -MATMUL_4D_REPACKED_IMPL(iq4nl, 576, tiled_vec_dot_iq4nl_32x2, tiled_vec_dot_iq4nl_32x1) -MATMUL_4D_REPACKED_IMPL(mxfp4, 544, tiled_vec_dot_mxfp4_32x2, tiled_vec_dot_mxfp4_32x1) - -static void hvx_mm_2d(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mm_2d_flat(unsigned int nth, unsigned int ith, void * data) { htp_matmul_preamble; const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; @@ -1014,7 +1038,7 @@ static void hvx_mm_2d(unsigned int nth, unsigned int ith, void * data) { } } -static void hvx_mv_2d(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mv_2d_flat(unsigned int nth, unsigned int ith, void * data) { htp_matmul_preamble; const uint32_t src0_nrows = mmctx->src0_row_end - mmctx->src0_row_start; @@ -1119,7 +1143,7 @@ static void hvx_mv_2d(unsigned int nth, unsigned int ith, void * data) { } } -static void hvx_mm_4d(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mm_4d_flat(unsigned int nth, unsigned int ith, void * data) { htp_matmul_preamble; const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; @@ -1268,7 +1292,7 @@ static void hvx_mm_4d(unsigned int nth, unsigned int ith, void * data) { #define MMID_MATRIX_ROW(row_id, i1) matrix_rows[(row_id) * mmctx->mapping_stride + (i1)] -static void hvx_mm_id(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mm_id_tiled(unsigned int nth, unsigned int ith, void * data) { htp_matmul_preamble; const struct htp_tensor * restrict ids = octx->src[2]; @@ -1312,12 +1336,11 @@ static void hvx_mm_id(unsigned int nth, unsigned int ith, void * data) { const dma_addr_t src0_row = src0->data + cur_a * nb02; - const uint32_t tile_size = htp_mm_get_weight_tile_size(src0->type); - const uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(src0->type); - const uint32_t n_k_tiles_w = ne00 / 32; - const uint32_t n_k_tiles_a = ne10 / 32; + const uint32_t tile_size = htp_tensor_get_tile_size(src0->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src0->type); + const uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src0->type); const uint32_t tile_row_stride = n_k_tiles_w * tile_size; - const uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; const uint32_t ct_start = src0_start_row / 32; const uint32_t ct_end = (src0_end_row + 31) / 32; @@ -1325,13 +1348,13 @@ static void hvx_mm_id(unsigned int nth, unsigned int ith, void * data) { uint32_t push_ct = ct_start; for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); } for (uint32_t ct = ct_start; ct < ct_end; ct++) { const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; - int valid_rows = (int)ne01 - (int)(ct * 32); + int valid_rows = (int)ne0 - (int)(ct * 32); valid_rows = MIN(32, MAX(0, valid_rows)); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); @@ -1350,14 +1373,14 @@ static void hvx_mm_id(unsigned int nth, unsigned int ith, void * data) { if (push_ct < ct_end) { dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); push_ct++; } } } } -static void hvx_mv_id(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mv_id_tiled(unsigned int nth, unsigned int ith, void * data) { htp_matmul_preamble; const struct htp_tensor * restrict ids = octx->src[2]; @@ -1394,18 +1417,17 @@ static void hvx_mv_id(unsigned int nth, unsigned int ith, void * data) { if (eid < 0) { continue; } - assert(eid < (int32_t) n_ids); + assert(eid >= 0 && eid < (int32_t) n_ids); const dma_addr_t src0_row = src0->data + eid * nb02; const uint8_t * restrict act_col = (const uint8_t *) act_data; float * restrict dst_row = (float *) (dst->data + ie1 * nb1); - const uint32_t tile_size = htp_mm_get_weight_tile_size(src0->type); - const uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(src0->type); - const uint32_t n_k_tiles_w = ne00 / 32; - const uint32_t n_k_tiles_a = ne10 / 32; + const uint32_t tile_size = htp_tensor_get_tile_size(src0->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src0->type); + const uint32_t n_k_tiles_w = ne00 / htp_tensor_get_tile_k(src0->type); const uint32_t tile_row_stride = n_k_tiles_w * tile_size; - const uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; const uint32_t ct_start = src0_start_row / 32; const uint32_t ct_end = (src0_end_row + 31) / 32; @@ -1413,13 +1435,13 @@ static void hvx_mv_id(unsigned int nth, unsigned int ith, void * data) { uint32_t push_ct = ct_start; for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); } for (uint32_t ct = ct_start; ct < ct_end; ct++) { const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; - int valid_rows = (int)ne01 - (int)(ct * 32); + int valid_rows = (int)ne0 - (int)(ct * 32); valid_rows = MIN(32, MAX(0, valid_rows)); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); @@ -1428,14 +1450,14 @@ static void hvx_mv_id(unsigned int nth, unsigned int ith, void * data) { if (push_ct < ct_end) { dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); push_ct++; } } } } -static void hvx_mv_id_nx(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mv_id_nx_tiled(unsigned int nth, unsigned int ith, void * data) { struct htp_mm_context * mmctx = (struct htp_mm_context *) data; struct htp_ops_context * octx = mmctx->octx; const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; @@ -1489,12 +1511,11 @@ static void hvx_mv_id_nx(unsigned int nth, unsigned int ith, void * data) { const uint8_t * restrict act_col = (const uint8_t *) act_data; float * restrict dst_row = (float *) (dst->data + ie1 * dst->nb[1]); - const uint32_t tile_size = htp_mm_get_weight_tile_size(src_w->type); - const uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(src_w->type); - const uint32_t n_k_tiles_w = src_w->ne[0] / 32; - const uint32_t n_k_tiles_a = act->ne[0] / 32; + const uint32_t tile_size = htp_tensor_get_tile_size(src_w->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src_w->type); + const uint32_t n_k_tiles_w = src_w->ne[0] / htp_tensor_get_tile_k(src_w->type); const uint32_t tile_row_stride = n_k_tiles_w * tile_size; - const uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; const uint32_t ct_start = src0_start_row / 32; const uint32_t ct_end = (src0_end_row + 31) / 32; @@ -1502,13 +1523,13 @@ static void hvx_mv_id_nx(unsigned int nth, unsigned int ith, void * data) { uint32_t push_ct = ct_start; for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); } for (uint32_t ct = ct_start; ct < ct_end; ct++) { const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; - int valid_rows = (int)src_w->ne[1] - (int)(ct * 32); + int valid_rows = (int)dst->ne[0] - (int)(ct * 32); valid_rows = MIN(32, MAX(0, valid_rows)); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); @@ -1517,7 +1538,7 @@ static void hvx_mv_id_nx(unsigned int nth, unsigned int ith, void * data) { if (push_ct < ct_end) { dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); push_ct++; } } @@ -1525,7 +1546,7 @@ static void hvx_mv_id_nx(unsigned int nth, unsigned int ith, void * data) { } } -static void hvx_mm_id_nx(unsigned int nth, unsigned int ith, void * data) { +static void hvx_mm_id_nx_tiled(unsigned int nth, unsigned int ith, void * data) { struct htp_mm_context * mmctx = (struct htp_mm_context *) data; struct htp_ops_context * octx = mmctx->octx; const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; @@ -1580,12 +1601,11 @@ static void hvx_mm_id_nx(unsigned int nth, unsigned int ith, void * data) { const dma_addr_t src0_row = src_w->data + cur_a * src_w->nb[2]; - const uint32_t tile_size = htp_mm_get_weight_tile_size(src_w->type); - const uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(src_w->type); - const uint32_t n_k_tiles_w = src_w->ne[0] / 32; - const uint32_t n_k_tiles_a = act->ne[0] / 32; + const uint32_t tile_size = htp_tensor_get_tile_size(src_w->type); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(src_w->type); + const uint32_t n_k_tiles_w = src_w->ne[0] / htp_tensor_get_tile_k(src_w->type); const uint32_t tile_row_stride = n_k_tiles_w * tile_size; - const uint32_t tile_row_transfer_size_aligned = n_k_tiles_a * aligned_tile_size; + const uint32_t tile_row_transfer_size_aligned = n_k_tiles_w * aligned_tile_size; const uint32_t ct_start = src0_start_row / 32; const uint32_t ct_end = (src0_end_row + 31) / 32; @@ -1593,13 +1613,13 @@ static void hvx_mm_id_nx(unsigned int nth, unsigned int ith, void * data) { uint32_t push_ct = ct_start; for (uint32_t d = 0; d < n_prefetch && push_ct < ct_end; d++, push_ct++) { dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + d * tile_row_transfer_size_aligned, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); } for (uint32_t ct = ct_start; ct < ct_end; ct++) { const uint8_t * w_tile = (void *) dma_queue_pop(dma_q).dst; - int valid_rows = (int)src_w->ne[1] - (int)(ct * 32); + int valid_rows = (int)dst->ne[0] - (int)(ct * 32); valid_rows = MIN(32, MAX(0, valid_rows)); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ct); @@ -1618,7 +1638,7 @@ static void hvx_mm_id_nx(unsigned int nth, unsigned int ith, void * data) { if (push_ct < ct_end) { dma_queue_push(dma_q, dma_make_data(w_tile, src0_row + push_ct * tile_row_stride), - aligned_tile_size, tile_size, tile_size, n_k_tiles_a); + aligned_tile_size, tile_size, tile_size, n_k_tiles_w); push_ct++; } } @@ -1626,44 +1646,68 @@ static void hvx_mm_id_nx(unsigned int nth, unsigned int ith, void * data) { } } -static int hvx_mm_init_vec_dot(struct htp_mm_context * mmctx, enum htp_data_type type) { +static int hvx_mm_init_tiled_vec_dot(struct htp_mm_context * mmctx, enum htp_data_type type) { switch (type) { case HTP_TYPE_Q4_0: mmctx->type = "q4_0_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q4_0_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q4_0_32x2; return 0; case HTP_TYPE_Q4_1: case HTP_TYPE_Q4_K: mmctx->type = "q4_1_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q4_1_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q4_1_32x2; return 0; case HTP_TYPE_Q8_0: mmctx->type = "q8_0_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q8_0_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q8_0_32x2; return 0; case HTP_TYPE_Q5_K: mmctx->type = "q5_k_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q5_k_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q5_k_32x2; return 0; case HTP_TYPE_Q6_K: mmctx->type = "q6_k_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q6_k_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q6_k_32x2; return 0; case HTP_TYPE_Q3_K: mmctx->type = "q3_k_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q3_k_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q3_k_32x2; return 0; case HTP_TYPE_Q2_K: mmctx->type = "q2_k_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_q2_k_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q2_k_32x2; + return 0; + case HTP_TYPE_Q2_0: + mmctx->type = "q2_0_tiled-f32"; + mmctx->vec_dot_32x1 = tiled_vec_dot_q2_0_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q2_0_32x2; return 0; case HTP_TYPE_IQ4_NL: mmctx->type = "iq4nl_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_iq4nl_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_iq4nl_32x2; return 0; case HTP_TYPE_MXFP4: mmctx->type = "mxfp4_tiled-f32"; mmctx->vec_dot_32x1 = tiled_vec_dot_mxfp4_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_mxfp4_32x2; + return 0; + case HTP_TYPE_Q1_0: + mmctx->type = "q1_0_tiled-f32"; + mmctx->vec_dot_32x1 = tiled_vec_dot_q1_0_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_q1_0_32x2; + return 0; + case HTP_TYPE_F16: + mmctx->type = "f16_tiled-f16"; + mmctx->vec_dot_32x1 = tiled_vec_dot_f16_32x1; + mmctx->vec_dot_32x2 = tiled_vec_dot_f16_32x2; return 0; default: return -1; @@ -1705,15 +1749,11 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { mmctx->src0_row_start = src0_row_start; mmctx->src0_row_end = src0_row_end; - bool is_repacked = (src0->type == HTP_TYPE_Q4_0 || src0->type == HTP_TYPE_Q4_1 || - src0->type == HTP_TYPE_Q8_0 || src0->type == HTP_TYPE_IQ4_NL || - src0->type == HTP_TYPE_MXFP4 || src0->type == HTP_TYPE_Q6_K || - src0->type == HTP_TYPE_Q4_K || src0->type == HTP_TYPE_Q5_K || - src0->type == HTP_TYPE_Q3_K || src0->type == HTP_TYPE_Q2_K); + const bool is_tiled = htp_tensor_is_tiled(src0); // Compute src0_nrows_per_thread mmctx->src0_nrows_per_thread = fastdiv(nrows + octx->n_threads - 1, &octx->n_threads_div); - if (is_repacked) { + if (is_tiled) { mmctx->src0_nrows_per_thread = hex_round_up(mmctx->src0_nrows_per_thread, 32); } else { mmctx->src0_nrows_per_thread += (mmctx->src0_nrows_per_thread & 1); // round up to even @@ -1730,59 +1770,11 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { uint32_t n_quant_tasks = 1; const bool is_batched = (ne12 > 1 || ne13 > 1 || ne02 > 1 || ne03 > 1); if (is_batched) { - if (is_repacked) { - switch (src0->type) { - case HTP_TYPE_Q4_0: matmul_job_func = hvx_mm_4d_repacked_q4_0; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: matmul_job_func = hvx_mm_4d_repacked_q4_1; break; - case HTP_TYPE_Q8_0: matmul_job_func = hvx_mm_4d_repacked_q8_0; break; - case HTP_TYPE_Q6_K: matmul_job_func = hvx_mm_4d_repacked_q6_k; break; - case HTP_TYPE_Q5_K: matmul_job_func = hvx_mm_4d_repacked_q5_k; break; - case HTP_TYPE_Q3_K: matmul_job_func = hvx_mm_4d_repacked_q3_k; break; - case HTP_TYPE_Q2_K: matmul_job_func = hvx_mm_4d_repacked_q2_k; break; - case HTP_TYPE_IQ4_NL: matmul_job_func = hvx_mm_4d_repacked_iq4nl; break; - case HTP_TYPE_MXFP4: matmul_job_func = hvx_mm_4d_repacked_mxfp4; break; - default: return HTP_STATUS_NO_SUPPORT; - } - } else { - matmul_job_func = hvx_mm_4d; - } + matmul_job_func = is_tiled ? hvx_mm_4d_tiled : hvx_mm_4d_flat; } else if (act_nrows > 1) { - if (is_repacked) { - switch (src0->type) { - case HTP_TYPE_Q4_0: matmul_job_func = hvx_mm_2d_repacked_q4_0; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: matmul_job_func = hvx_mm_2d_repacked_q4_1; break; - case HTP_TYPE_Q8_0: matmul_job_func = hvx_mm_2d_repacked_q8_0; break; - case HTP_TYPE_Q6_K: matmul_job_func = hvx_mm_2d_repacked_q6_k; break; - case HTP_TYPE_Q5_K: matmul_job_func = hvx_mm_2d_repacked_q5_k; break; - case HTP_TYPE_Q3_K: matmul_job_func = hvx_mm_2d_repacked_q3_k; break; - case HTP_TYPE_Q2_K: matmul_job_func = hvx_mm_2d_repacked_q2_k; break; - case HTP_TYPE_IQ4_NL: matmul_job_func = hvx_mm_2d_repacked_iq4nl; break; - case HTP_TYPE_MXFP4: matmul_job_func = hvx_mm_2d_repacked_mxfp4; break; - default: return HTP_STATUS_NO_SUPPORT; - } - } else { - matmul_job_func = hvx_mm_2d; - } + matmul_job_func = is_tiled ? hvx_mm_2d_tiled : hvx_mm_2d_flat; } else { - if (is_repacked) { - switch (src0->type) { - case HTP_TYPE_Q4_0: matmul_job_func = hvx_mv_2d_repacked_q4_0; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: matmul_job_func = hvx_mv_2d_repacked_q4_1; break; - case HTP_TYPE_Q8_0: matmul_job_func = hvx_mv_2d_repacked_q8_0; break; - case HTP_TYPE_Q5_K: matmul_job_func = hvx_mv_2d_repacked_q5_k; break; - case HTP_TYPE_Q6_K: matmul_job_func = hvx_mv_2d_repacked_q6_k; break; - case HTP_TYPE_Q3_K: matmul_job_func = hvx_mv_2d_repacked_q3_k; break; - case HTP_TYPE_Q2_K: matmul_job_func = hvx_mv_2d_repacked_q2_k; break; - case HTP_TYPE_IQ4_NL: matmul_job_func = hvx_mv_2d_repacked_iq4nl; break; - case HTP_TYPE_MXFP4: matmul_job_func = hvx_mv_2d_repacked_mxfp4; break; - default: return HTP_STATUS_NO_SUPPORT; - } - } else { - matmul_job_func = hvx_mv_2d; - } + matmul_job_func = is_tiled ? hvx_mv_2d_tiled : hvx_mv_2d_flat; } bool need_quant = true; @@ -1792,9 +1784,9 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { quant_task_func = (act->type == HTP_TYPE_F32) ? quantize_f32_f16 : quantize_f16_f16; need_quant = (act->type == HTP_TYPE_F32); mmctx->type = (act->type == HTP_TYPE_F32) ? "f32-f16" : "f16-f16"; - mmctx->vec_dot_1x1 = vec_dot_f16_f16_aa_1x1; - mmctx->vec_dot_2x1 = vec_dot_f16_f16_aa_2x1; - mmctx->vec_dot_2x2 = vec_dot_f16_f16_aa_2x2; + mmctx->vec_dot_1x1 = flat_vec_dot_f16_f16_aa_1x1; + mmctx->vec_dot_2x1 = flat_vec_dot_f16_f16_aa_2x1; + mmctx->vec_dot_2x2 = flat_vec_dot_f16_f16_aa_2x2; act_row_size = kparams->act_row_size; break; @@ -1802,26 +1794,36 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { quant_task_func = NULL; need_quant = false; mmctx->type = "f32-f32"; - mmctx->vec_dot_1x1 = vec_dot_f32_f32_aa_1x1; - mmctx->vec_dot_2x1 = vec_dot_f32_f32_aa_2x1; - mmctx->vec_dot_2x2 = vec_dot_f32_f32_aa_2x2; + mmctx->vec_dot_1x1 = flat_vec_dot_f32_f32_aa_1x1; + mmctx->vec_dot_2x1 = flat_vec_dot_f32_f32_aa_2x1; + mmctx->vec_dot_2x2 = flat_vec_dot_f32_f32_aa_2x2; + act_row_size = kparams->act_row_size; + break; + + case HTP_MM_KERNEL_HVX_BF16_F32_VTCM: + quant_task_func = NULL; + need_quant = false; + mmctx->type = "bf16-f32"; + mmctx->vec_dot_1x1 = flat_vec_dot_bf16_f32_aa_1x1; + mmctx->vec_dot_2x1 = flat_vec_dot_bf16_f32_aa_2x1; + mmctx->vec_dot_2x2 = flat_vec_dot_bf16_f32_aa_2x2; act_row_size = kparams->act_row_size; break; case HTP_MM_KERNEL_HVX_QUANT_BLOCK: case HTP_MM_KERNEL_HVX_QUANT_ROW: - default: - if (hvx_mm_init_vec_dot(mmctx, src0->type) != 0) { + default: { + if (hvx_mm_init_tiled_vec_dot(mmctx, src0->type) != 0) { return HTP_STATUS_NO_SUPPORT; } - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne10 + qk - 1) / qk; const uint32_t total_nb = act_nrows * nb; if (act_nrows < octx->n_threads && !is_batched) { n_quant_tasks = MIN(total_nb, octx->n_threads); - quant_task_func = htp_mm_act_quant_block_func(src0->type); + quant_task_func = htp_mm_act_quant_block_func(src0->type, act->type); for (uint32_t ith = 0; ith < n_quant_tasks; ++ith) { uint32_t ib_first = (total_nb * ith) / n_quant_tasks; uint32_t ib_last = (total_nb * (ith + 1)) / n_quant_tasks; @@ -1832,10 +1834,11 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { } } else { n_quant_tasks = MIN(act_nrows, octx->n_threads); - quant_task_func = htp_mm_act_quant_row_func(src0->type); + quant_task_func = htp_mm_act_quant_row_func(src0->type, act->type); } act_row_size = kparams->act_row_size; break; + } } const uint32_t m_chunk = (kparams->m_chunk > 0 && (uint32_t) kparams->m_chunk < act_nrows) @@ -1848,6 +1851,7 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { if (kparams->kernel_type == HTP_MM_KERNEL_HVX_F16_F16_VTCM || kparams->kernel_type == HTP_MM_KERNEL_HVX_F32_F32_VTCM || + kparams->kernel_type == HTP_MM_KERNEL_HVX_BF16_F32_VTCM || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK) { mmctx->vtcm_act_size_per_thread = L.act_bytes; @@ -1883,7 +1887,7 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { mmctx->vtcm_src0_stride = src0_row_size_padded; mmctx->vtcm_act_stride = act_row_size; if (kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW) { - mmctx->vtcm_act_raw_stride = hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + mmctx->vtcm_act_raw_stride = htp_mm_act_raw_row_size(ne10); } else if (kparams->kernel_type == HTP_MM_KERNEL_HVX_F16_F16_VTCM) { mmctx->vtcm_act_raw_stride = hex_round_up(ne10 * sizeof(float), 128); } else { @@ -1901,14 +1905,14 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { if (need_quant) { hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act_raw, mmctx->vtcm_act_raw_stride, m_start, cur_m_rows); - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne10 + qk - 1) / qk; const uint32_t total_nb = cur_m_rows * nb; uint32_t quant_tasks; work_queue_func_t q_func; if (cur_m_rows < octx->n_threads && (kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK || kparams->kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW)) { quant_tasks = MIN(total_nb, octx->n_threads); - q_func = htp_mm_act_quant_block_func(src0->type); + q_func = htp_mm_act_quant_block_func(src0->type, act->type); for (uint32_t ith = 0; ith < quant_tasks; ++ith) { uint32_t ib_first = (total_nb * ith) / quant_tasks; uint32_t ib_last = (total_nb * (ith + 1)) / quant_tasks; @@ -1916,191 +1920,51 @@ static int hvx_mm_matmul(struct htp_ops_context * octx) { mmctx->quant_ib_last[ith] = ib_last; mmctx->quant_r[ith] = ib_first / nb; mmctx->quant_c[ith] = ib_first % nb; - } - } else { - quant_tasks = MIN(cur_m_rows, octx->n_threads); - q_func = quant_task_func; - mmctx->n_quant_rows_per_thread = (cur_m_rows + quant_tasks - 1) / quant_tasks; - } - mmctx->n_quant_tasks = quant_tasks; - work_queue_run(octx->ctx->work_queue, q_func, mmctx, quant_tasks); - } else { - hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act, mmctx->vtcm_act_stride, m_start, cur_m_rows); - } - - work_queue_run(octx->ctx->work_queue, matmul_job_func, mmctx, octx->n_threads); - } - } else { - mmctx->cur_m_start = 0; - mmctx->cur_m_rows = act_nrows; - - if (need_quant) { - hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act_raw, mmctx->vtcm_act_raw_stride, 0, act_nrows); - mmctx->n_quant_rows_per_thread = (act_nrows + n_quant_tasks - 1) / n_quant_tasks; - mmctx->n_quant_tasks = n_quant_tasks; - work_queue_run(octx->ctx->work_queue, quant_task_func, mmctx, n_quant_tasks); - } else { - hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act, mmctx->vtcm_act_stride, 0, act_nrows); - } - - work_queue_run(octx->ctx->work_queue, matmul_job_func, mmctx, octx->n_threads); - } - - return HTP_STATUS_OK; -} - -static void hvx_mm_nx_2d(unsigned int nth, unsigned int ith, void * data) { - struct htp_mm_context * mmctx = data; - struct htp_ops_context * octx = mmctx->octx; - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; - const uint32_t n_weights = kparams->n_weights; - - const struct htp_tensor * restrict act = octx->src[n_weights]; - const uint32_t act_nrows = act->ne[1] * act->ne[2] * act->ne[3]; - const size_t act_stride = mmctx->vtcm_act_stride; - - uint8_t * restrict vtcm_src0_ptr = mmctx->vtcm_src0 + mmctx->vtcm_src0_size_per_thread * ith; - uint8_t * restrict act_data = mmctx->vtcm_act; - - const uint32_t n_prefetch = kparams->n_prefetch; - assert(n_prefetch >= 2 && n_prefetch <= HTP_MM_MAX_PREFETCH && (n_prefetch & (n_prefetch - 1)) == 0); - const uint32_t prefetch_mask = n_prefetch - 1; - - struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - - - for (uint32_t widx = 0; widx < n_weights; widx++) { - const struct htp_tensor * restrict src_w = octx->src[widx]; - const struct htp_tensor * restrict dst = octx->dsts[widx]; - if (!src_w || !dst) continue; - dma_queue * dma_q = octx->ctx->dma[ith]; - - const uint32_t ne00 = src_w->ne[0]; - const uint32_t ne01 = src_w->ne[1]; - uint32_t start_row = 0; - uint32_t end_row = ne01; - if (octx->ctx->mdev.count > 1) { - const bool can_split = htp_tensor_can_row_partition(dst, sizeof(float)); - const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(ne01, can_split ? 32 : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); - start_row = range.start; - end_row = range.start + range.count; - } - - const uint32_t nrows = end_row - start_row; - uint32_t src0_nrows_per_thread = fastdiv(nrows + nth - 1, &octx->n_threads_div); - src0_nrows_per_thread += (src0_nrows_per_thread & 1); - - const uint32_t src0_start_row = start_row + src0_nrows_per_thread * ith; - const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, end_row); - const uint32_t src0_end_row_x2 = src0_start_row + ((src0_end_row - src0_start_row) & ~1U); - if (src0_start_row >= src0_end_row) continue; - - const size_t dst_row_size = dst->nb[1]; - const size_t src0_row_size = src_w->nb[1]; - const size_t src0_stride = hex_round_up(src0_row_size, 128); - - const dma_addr_t src0_row = src_w->data; - - for (uint32_t ir0 = src0_start_row; ir0 < src0_end_row_x2; ir0 += 2) { - const int is0 = (ir0 - src0_start_row); - if (is0 >= (int)n_prefetch) break; - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + is0 * src0_stride, src0_row + ir0 * src0_row_size), - src0_stride, src0_row_size, src0_row_size, 2); - } - - for (uint32_t ir0 = src0_start_row; ir0 < src0_end_row_x2; ir0 += 2) { - const uint8_t * ss0 = (void *) dma_queue_pop(dma_q).dst; - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ir0); - uint32_t ir1 = 0; - for (; ir1 + 1 < act_nrows; ir1 += 2) { - const uint8_t * restrict act_col0 = (const uint8_t *) (act_data + (ir1+0) * act_stride); - const uint8_t * restrict act_col1 = (const uint8_t *) (act_data + (ir1+1) * act_stride); - float * restrict dst_row0 = (float *) (dst->data + ((ir1+0) * dst_row_size)); - float * restrict dst_row1 = (float *) (dst->data + ((ir1+1) * dst_row_size)); - mmctx->vec_dot_2x2(ne00, &dst_row0[ir0], &dst_row1[ir0], ss0, ss0 + src0_stride, act_col0, act_col1); - } - for (; ir1 < act_nrows; ++ir1) { - const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); - float * restrict dst_row = (float *) (dst->data + (ir1 * dst_row_size)); - mmctx->vec_dot_2x1(ne00, &dst_row[ir0], ss0, ss0 + src0_stride, act_col); + } + } else { + quant_tasks = MIN(cur_m_rows, octx->n_threads); + q_func = quant_task_func; + mmctx->n_quant_rows_per_thread = (cur_m_rows + quant_tasks - 1) / quant_tasks; + } + mmctx->n_quant_tasks = quant_tasks; + work_queue_run(octx->ctx->work_queue, q_func, mmctx, quant_tasks); + } else { + hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act, mmctx->vtcm_act_stride, m_start, cur_m_rows); } - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir0); - const int pr0 = (ir0 + n_prefetch); - const int is0 = (pr0 - src0_start_row) & prefetch_mask; - if (pr0 < src0_end_row_x2) { - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + is0 * src0_stride, src0_row + pr0 * src0_row_size), - src0_stride, src0_row_size, src0_row_size, 2); - } + work_queue_run(octx->ctx->work_queue, matmul_job_func, mmctx, octx->n_threads); } + } else { + mmctx->cur_m_start = 0; + mmctx->cur_m_rows = act_nrows; - if (src0_end_row != src0_end_row_x2) { - uint32_t ir0 = src0_end_row_x2; - const int is0 = (ir0 - src0_start_row) & prefetch_mask; - dma_queue_push(dma_q, dma_make_data(vtcm_src0_ptr + is0 * src0_stride, src0_row + ir0 * src0_row_size), - src0_stride, src0_row_size, src0_row_size, 1); - const uint8_t * ss0 = (void *) dma_queue_pop(dma_q).dst; - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, ir0); - for (uint32_t ir1 = 0; ir1 < act_nrows; ++ir1) { - const uint8_t * restrict act_col = (const uint8_t *) (act_data + ir1 * act_stride); - float * restrict dst_row = (float *) (dst->data + (ir1 * dst_row_size)); - mmctx->vec_dot_1x1(ne00, &dst_row[ir0], ss0, act_col); - } - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir0); + if (need_quant) { + hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act_raw, mmctx->vtcm_act_raw_stride, 0, act_nrows); + mmctx->n_quant_rows_per_thread = (act_nrows + n_quant_tasks - 1) / n_quant_tasks; + mmctx->n_quant_tasks = n_quant_tasks; + work_queue_run(octx->ctx->work_queue, quant_task_func, mmctx, n_quant_tasks); + } else { + hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act, mmctx->vtcm_act_stride, 0, act_nrows); } + + work_queue_run(octx->ctx->work_queue, matmul_job_func, mmctx, octx->n_threads); } -} -#define DEQUANTIZE_WORKER_LOOP_IMPL(SUFFIX) \ -static void dequantize_tiled_worker_loop_##SUFFIX(unsigned int n, unsigned int i, void *data) { \ - tiled_dequantize_state_t *state = (tiled_dequantize_state_t *)data; \ - struct htp_thread_trace * tr = &state->traces[i]; \ - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_DEQUANT, i); \ - for (unsigned int task_id = i; task_id < (unsigned int)state->n_tasks; task_id += n) { \ - int start = task_id * state->n_tiles_per_task; \ - int end = hex_smin(start + state->n_tiles_per_task, state->n_tot_tiles); \ - dequantize_tiled_weight_to_fp16_task_##SUFFIX(state, start, end); \ - } \ - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_DEQUANT, i); \ + return HTP_STATUS_OK; } -DEQUANTIZE_WORKER_LOOP_IMPL(q4_0) -DEQUANTIZE_WORKER_LOOP_IMPL(q4_1) -DEQUANTIZE_WORKER_LOOP_IMPL(iq4_nl) -DEQUANTIZE_WORKER_LOOP_IMPL(mxfp4) -DEQUANTIZE_WORKER_LOOP_IMPL(q8_0) -DEQUANTIZE_WORKER_LOOP_IMPL(q6_k) -DEQUANTIZE_WORKER_LOOP_IMPL(q5_k) -DEQUANTIZE_WORKER_LOOP_IMPL(q3_k) -DEQUANTIZE_WORKER_LOOP_IMPL(q2_k) - -static void convert_f16_worker_loop(unsigned int n, unsigned int i, void *data) { - tiled_dequantize_state_t *state = (tiled_dequantize_state_t *)data; +static void dequantize_tiled_worker_loop(unsigned int n, unsigned int i, void * data) { + tiled_dequantize_state_t * state = (tiled_dequantize_state_t *) data; struct htp_thread_trace * tr = &state->traces[i]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_W_DEQUANT, i); - for (unsigned int task_id = i; task_id < (unsigned int)state->n_tasks; task_id += n) { + for (unsigned int task_id = i; task_id < (unsigned int) state->n_tasks; task_id += n) { int start = task_id * state->n_tiles_per_task; int end = hex_smin(start + state->n_tiles_per_task, state->n_tot_tiles); - convert_f16_weight_to_fp16_tiles_task(state, start, end); + state->task_fn(state, start, end); } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_W_DEQUANT, i); } -static void quantize_f32_worker_loop(unsigned int n, unsigned int i, void *data) { - tiled_dequantize_state_t *state = (tiled_dequantize_state_t *)data; - - struct htp_thread_trace * tr = &state->traces[i]; - htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_QUANT, i); - - for (unsigned int task_id = i; task_id < (unsigned int)state->n_tasks; task_id += n) { - int start = task_id * state->n_tiles_per_task; - int end = hex_smin(start + state->n_tiles_per_task, state->n_tot_tiles); - quantize_f32_weight_to_fp16_tiles_task(state, start, end); - } - - htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_QUANT, i); -} - static void transfer_output_chunk_worker_fn(unsigned int n, unsigned int i, void *data) { output_transfer_task_state_t *st = (output_transfer_task_state_t *) data; @@ -2450,18 +2314,44 @@ static void transfer_output_chunk_scattered_worker_fn(unsigned int n, unsigned i // --- HMX Dispatchers & Entry Points --- +static inline tiled_dequant_task_fn_t hmx_get_dequant_worker_fn(int weight_type, bool is_tiled) { + switch (weight_type) { + case HTP_TYPE_Q4_0: return dequantize_tiled_weight_to_fp16_task_q4_0; + case HTP_TYPE_IQ4_NL: return dequantize_tiled_weight_to_fp16_task_iq4_nl; + case HTP_TYPE_Q4_1: + case HTP_TYPE_Q4_K: return dequantize_tiled_weight_to_fp16_task_q4_1; + case HTP_TYPE_MXFP4: return dequantize_tiled_weight_to_fp16_task_mxfp4; + case HTP_TYPE_Q8_0: return dequantize_tiled_weight_to_fp16_task_q8_0; + case HTP_TYPE_Q5_K: return dequantize_tiled_weight_to_fp16_task_q5_k; + case HTP_TYPE_Q6_K: return dequantize_tiled_weight_to_fp16_task_q6_k; + case HTP_TYPE_Q3_K: return dequantize_tiled_weight_to_fp16_task_q3_k; + case HTP_TYPE_Q2_K: return dequantize_tiled_weight_to_fp16_task_q2_k; + case HTP_TYPE_Q1_0: return dequantize_tiled_weight_to_fp16_task_q1_0; + case HTP_TYPE_Q2_0: return dequantize_tiled_weight_to_fp16_task_q2_0; + case HTP_TYPE_F16: return is_tiled ? NULL : convert_f16_weight_to_fp16_tiles_task; + case HTP_TYPE_BF16: return convert_bf16_weight_to_fp16_tiles_task; + case HTP_TYPE_F32: return quantize_f32_weight_to_fp16_tiles_task; + default: return NULL; + } +} + static void dequantize_tiled_weight_chunk_to_fp16_tiles( struct htp_context *ctx, __fp16 *vtcm_dst, const void *weight_src_ddr, int n_cols, int k_block, size_t row_stride, int weight_type, int n_k_tiles, struct fastdiv_values n_k_tiles_div, - worker_callback_t dequant_worker_fn, int n_threads) { + tiled_dequant_task_fn_t dequant_worker_fn, int n_threads) { + + if (!dequant_worker_fn) { + return; + } assert(k_block % HTP_MM_HMX_TILE_N_COLS == 0); - size_t n_col_tiles = hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS); - size_t n_tot_tiles = n_col_tiles * n_k_tiles; + const size_t n_col_tiles = hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS); + const uint32_t n_weight_tiles = k_block / htp_tensor_get_tile_k(weight_type); + const size_t n_tot_tiles = n_col_tiles * n_weight_tiles; size_t n_tiles_per_task = (n_threads == 1) ? n_tot_tiles : hmx_ceil_div(n_tot_tiles, n_threads); @@ -2471,23 +2361,25 @@ static void dequantize_tiled_weight_chunk_to_fp16_tiles( state.n_tiles_per_task = n_tiles_per_task; state.dst = vtcm_dst; state.src = (const uint8_t *)weight_src_ddr; + state.task_fn = dequant_worker_fn; state.n_cols = n_cols; state.k_block = k_block; state.row_stride = row_stride; state.weight_type = weight_type; state.n_k_tiles = n_k_tiles; + state.n_weight_tiles = n_weight_tiles; state.n_k_tiles_div = n_k_tiles_div; state.traces = ctx->trace; state.ctx = ctx; - state.tile_size = htp_mm_get_weight_tile_size(weight_type); - state.aligned_tile_size = htp_mm_get_weight_aligned_tile_size(weight_type); + state.tile_size = htp_tensor_get_tile_size(weight_type); + state.aligned_tile_size = htp_tensor_get_tile_padded_size(weight_type); if (state.n_tasks == 1 || n_threads == 1) { - dequant_worker_fn(1, 0, &state); + dequantize_tiled_worker_loop(1, 0, &state); } else { int n_tasks = hex_smin((int) state.n_tasks, n_threads); - worker_pool_run_func(ctx->worker_pool, dequant_worker_fn, &state, n_tasks); + worker_pool_run_func(ctx->worker_pool, dequantize_tiled_worker_loop, &state, n_tasks); } } @@ -2764,54 +2656,35 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, struct htp_thread_trace * tr = &ctx->trace[0]; htp_trace_event_start(tr, HTP_TRACE_EVT_INIT, 0); - // Quantized weights are repacked and padded to 32, so we it has to be 32-aligned. - // Only F16/F32 weights can be non-32-aligned, they will be padded in the following kernel. - const bool wtype_is_quant = (weight_type != HTP_TYPE_F16 && weight_type != HTP_TYPE_F32); - if (k % 32 != 0 || (wtype_is_quant && n % 32 != 0)) { + const bool is_tiled = (tile_size > 0); + + if (k % 32 != 0) { return -1; } - if (!hex_is_aligned(dst, VLEN) || (act_dma_addr & (VLEN - 1)) != 0) { return -1; } + if (!hex_is_aligned(dst, sizeof(float))) { return -1; } - size_t row_stride = htp_mm_get_tiled_row_stride(weight_type, k); + size_t row_stride = htp_tensor_get_row_size(weight_type, k); if (row_stride == 0) { return -1; } - worker_callback_t dequant_worker_fn = NULL; - switch (weight_type) { - case HTP_TYPE_Q4_0: dequant_worker_fn = dequantize_tiled_worker_loop_q4_0; break; - case HTP_TYPE_IQ4_NL: dequant_worker_fn = dequantize_tiled_worker_loop_iq4_nl; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: dequant_worker_fn = dequantize_tiled_worker_loop_q4_1; break; - case HTP_TYPE_MXFP4: dequant_worker_fn = dequantize_tiled_worker_loop_mxfp4; break; - case HTP_TYPE_Q8_0: dequant_worker_fn = dequantize_tiled_worker_loop_q8_0; break; - case HTP_TYPE_Q5_K: dequant_worker_fn = dequantize_tiled_worker_loop_q5_k; break; - case HTP_TYPE_Q6_K: dequant_worker_fn = dequantize_tiled_worker_loop_q6_k; break; - case HTP_TYPE_Q3_K: dequant_worker_fn = dequantize_tiled_worker_loop_q3_k; break; - case HTP_TYPE_Q2_K: dequant_worker_fn = dequantize_tiled_worker_loop_q2_k; break; - case HTP_TYPE_F16: dequant_worker_fn = convert_f16_worker_loop; break; - case HTP_TYPE_F32: dequant_worker_fn = quantize_f32_worker_loop; break; - default: - return -1; - } + tiled_dequant_task_fn_t dequant_worker_fn = hmx_get_dequant_worker_fn(weight_type, is_tiled); const int n_k_tiles = k / HTP_MM_HMX_TILE_N_COLS; + const int n_weight_tiles = k / htp_tensor_get_tile_k(weight_type); const struct fastdiv_values n_k_tiles_div = init_fastdiv_values(n_k_tiles); - const bool is_quant = (weight_type != HTP_TYPE_F16 && weight_type != HTP_TYPE_F32); const size_t vec_dot_size = k * sizeof(__fp16); const size_t vtcm_budget = ctx->vtcm_size; - const uint32_t dma_dst_stride = is_quant ? aligned_tile_size : row_stride; - const uint32_t dma_src_stride = is_quant ? tile_size : weight_stride; - const uint32_t dma_width_bytes = is_quant ? tile_size : row_stride; + const uint32_t dma_dst_stride = is_tiled ? aligned_tile_size : row_stride; + const uint32_t dma_src_stride = is_tiled ? tile_size : weight_stride; + const uint32_t dma_width_bytes = is_tiled ? tile_size : row_stride; size_t m_chunk_n_rows = m_chunk; size_t n_chunk_n_cols = n_chunk; size_t vtcm_used = vtcm_size; - const size_t qweight_row_stride = is_quant ? (size_t)(n_k_tiles * aligned_tile_size) / 32 : 0; - struct htp_mm_hmx_vtcm_layout L; htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_2D, weight_type, k, m_chunk_n_rows, n_chunk_n_cols, 1, pipeline, act_threads, aligned_tile_size, src2_bytes); @@ -2827,7 +2700,6 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, VTCM_LAYOUT_PTR(__fp16, base, L.off_weight[0]), VTCM_LAYOUT_PTR_OPTIONAL(__fp16, base, L.off_weight[1], pipeline) }; - __fp16 *vtcm_f16_act = VTCM_LAYOUT_PTR(__fp16, base, L.off_act); float *vtcm_f32_act = VTCM_LAYOUT_PTR(float, base, L.off_act_f32); __fp16 *vtcm_output = VTCM_LAYOUT_PTR(__fp16, base, L.off_dst[0]); @@ -2855,13 +2727,23 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, if (pipeline) { // --- Asynchronous Pipelined Loop --- hmx_matmul_job_t job_slots[2]; // persistent double-buffered job descriptors + void *vtcm_raw_bufs[4] = { + vtcm_weight_raw[0], + vtcm_weight_raw[1], + dequant_worker_fn ? vtcm_weight_raw[0] : vtcm_scratch0, + dequant_worker_fn ? vtcm_weight_raw[1] : vtcm_scratch1, + }; + void *vtcm_weight_bufs[4] = { + dequant_worker_fn ? vtcm_scratch0 : vtcm_weight_raw[0], + dequant_worker_fn ? vtcm_scratch1 : vtcm_weight_raw[1], + vtcm_scratch0, + vtcm_scratch1, + }; + void *vtcm_output_bufs[2] = { vtcm_output, vtcm_scratch2 }; for (size_t mr = 0; mr < m; mr += m_chunk_n_rows) { const size_t n_rows = hex_smin(m - mr, m_chunk_n_rows); - void *vtcm_weight_bufs[2] = { vtcm_scratch0, vtcm_scratch1 }; - void *vtcm_output_bufs[2] = { vtcm_output, vtcm_scratch2 }; - struct activation_transfer_params act_params = { .ctx = ctx, .dst = vtcm_f16_act, @@ -2881,14 +2763,14 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, // Prologue: push A0 and optionally A1 (if n_chunk_cnt > 1) const size_t n_cols_A0 = hex_smin(n - 0 * n_chunk_n_cols, n_chunk_n_cols); - const uint32_t height_A0 = is_quant ? hmx_ceil_div(n_cols_A0, 32) * n_k_tiles : n_cols_A0; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[0], weight), + const uint32_t height_A0 = is_tiled ? hmx_ceil_div(n_cols_A0, 32) * n_weight_tiles : n_cols_A0; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height_A0); if (1 < n_chunk_cnt) { const size_t n_cols_A1 = hex_smin(n - 1 * n_chunk_n_cols, n_chunk_n_cols); - const uint32_t height_A1 = is_quant ? hmx_ceil_div(n_cols_A1, 32) * n_k_tiles : n_cols_A1; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[1], weight + n_chunk_n_cols * weight_stride), + const uint32_t height_A1 = is_tiled ? hmx_ceil_div(n_cols_A1, 32) * n_weight_tiles : n_cols_A1; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[1], weight + n_chunk_n_cols * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_A1); } @@ -2905,20 +2787,20 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, // 2. dequantize A_i dequantize_tiled_weight_chunk_to_fp16_tiles( - ctx, vtcm_weight_bufs[i % 2], curr_raw, + ctx, vtcm_weight_bufs[i % 4], curr_raw, n_cols, k, row_stride, weight_type, n_k_tiles, n_k_tiles_div, dequant_worker_fn, n_threads); // 3. push A_{i+2} (if i+2 < n_chunk_cnt) if (i + 2 < n_chunk_cnt) { - const uint32_t height_p2 = is_quant ? hmx_ceil_div(n_cols_p2, 32) * n_k_tiles : n_cols_p2; - dma_queue_push(weight_dma, dma_make_data(curr_raw, weight + nc_p2 * weight_stride), + const uint32_t height_p2 = is_tiled ? hmx_ceil_div(n_cols_p2, 32) * n_weight_tiles : n_cols_p2; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[(i + 2) % 4], weight + nc_p2 * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_p2); } // 4. submit C_i hmx_matmul_job_init(&job_slots[i % 2], (__fp16 *) vtcm_output_bufs[i % 2], - (__fp16 *) vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 2], + (__fp16 *) vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 4], vtcm_scales, hmx_ceil_div(n_rows, HTP_MM_HMX_TILE_N_ROWS), hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS), k / HTP_MM_HMX_TILE_N_ROWS); hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_matmul_worker_fn, &job_slots[i % 2])); @@ -2951,6 +2833,9 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, } else { // --- Synchronous loop (m <= 32 or fallback) --- hmx_matmul_job_t job; + void *vtcm_raw_bufs[2] = { vtcm_weight_raw[0], dequant_worker_fn ? vtcm_weight_raw[0] : vtcm_scratch0 }; + void *vtcm_weight_bufs[2] = { dequant_worker_fn ? vtcm_scratch0 : vtcm_weight_raw[0], vtcm_scratch0 }; + for (size_t mr = 0; mr < m; mr += m_chunk_n_rows) { const size_t n_rows = hex_smin(m - mr, m_chunk_n_rows); @@ -2974,11 +2859,12 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, // A0: Pre-fetch the first weight chunk (nc = 0) if (n > 0) { const size_t n_cols = hex_smin(n, n_chunk_n_cols); - const uint32_t height = is_quant ? hmx_ceil_div(n_cols, 32) * n_k_tiles : n_cols; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height); + const uint32_t height = is_tiled ? hmx_ceil_div(n_cols, 32) * n_weight_tiles : n_cols; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height); } - for (size_t nc = 0; nc < n; nc += n_chunk_n_cols) { + for (int i = 0; i < n_chunk_cnt; ++i) { + const size_t nc = (size_t) i * n_chunk_n_cols; const size_t n_cols = hex_smin(n - nc, n_chunk_n_cols); const size_t n_row_tiles = hmx_ceil_div(n_rows, HTP_MM_HMX_TILE_N_ROWS); const size_t n_col_tiles = hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS); @@ -2988,7 +2874,7 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, // B: Weight Dequantize (Threaded) dequantize_tiled_weight_chunk_to_fp16_tiles( - ctx, vtcm_scratch0, curr_raw, + ctx, vtcm_weight_bufs[i % 2], curr_raw, n_cols, k, row_stride, weight_type, n_k_tiles, n_k_tiles_div, dequant_worker_fn, n_threads); @@ -2996,12 +2882,12 @@ static int hmx_mm_2d_f32(struct htp_context *ctx, const size_t nc_next = nc + n_chunk_n_cols; if (nc_next < n) { const size_t n_cols_next = hex_smin(n - nc_next, n_chunk_n_cols); - const uint32_t height_next = is_quant ? hmx_ceil_div(n_cols_next, 32) * n_k_tiles : n_cols_next; - dma_queue_push(weight_dma, dma_make_data(curr_raw, weight + nc_next * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_next); + const uint32_t height_next = is_tiled ? hmx_ceil_div(n_cols_next, 32) * n_weight_tiles : n_cols_next; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[(i + 1) % 2], weight + nc_next * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_next); } // C: HMX Compute (Queue-based) - hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, vtcm_scratch0, vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); + hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 2], vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_matmul_worker_fn, &job)); hmx_queue_pop(ctx->hmx_queue); @@ -3041,35 +2927,21 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k const dma_addr_t act_dma_addr = act->data; if (k % 32 != 0) { return HTP_STATUS_NO_SUPPORT; } - if ((act_dma_addr & (VLEN - 1)) != 0) { return HTP_STATUS_NO_SUPPORT; } - size_t row_stride = htp_mm_get_tiled_row_stride(weight_type, k); + size_t row_stride = htp_tensor_get_row_size(weight_type, k); if (row_stride == 0) { return HTP_STATUS_NO_SUPPORT; } - worker_callback_t dequant_worker_fn = NULL; - switch (weight_type) { - case HTP_TYPE_Q4_0: dequant_worker_fn = dequantize_tiled_worker_loop_q4_0; break; - case HTP_TYPE_IQ4_NL: dequant_worker_fn = dequantize_tiled_worker_loop_iq4_nl; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: dequant_worker_fn = dequantize_tiled_worker_loop_q4_1; break; - case HTP_TYPE_MXFP4: dequant_worker_fn = dequantize_tiled_worker_loop_mxfp4; break; - case HTP_TYPE_Q8_0: dequant_worker_fn = dequantize_tiled_worker_loop_q8_0; break; - case HTP_TYPE_Q5_K: dequant_worker_fn = dequantize_tiled_worker_loop_q5_k; break; - case HTP_TYPE_Q6_K: dequant_worker_fn = dequantize_tiled_worker_loop_q6_k; break; - case HTP_TYPE_Q3_K: dequant_worker_fn = dequantize_tiled_worker_loop_q3_k; break; - case HTP_TYPE_Q2_K: dequant_worker_fn = dequantize_tiled_worker_loop_q2_k; break; - case HTP_TYPE_F16: dequant_worker_fn = convert_f16_worker_loop; break; - case HTP_TYPE_F32: dequant_worker_fn = quantize_f32_worker_loop; break; - default: - return HTP_STATUS_NO_SUPPORT; - } - const int n_k_tiles = k / HTP_MM_HMX_TILE_N_COLS; + const int n_weight_tiles = k / htp_tensor_get_tile_k(weight_type); const struct fastdiv_values n_k_tiles_div = init_fastdiv_values(n_k_tiles); - const bool is_quant = (weight_type != HTP_TYPE_F16 && weight_type != HTP_TYPE_F32); + const int tile_size = kparams->tile_size; + const int aligned_tile_size = kparams->aligned_tile_size; + + const bool is_tiled = (tile_size > 0); + tiled_dequant_task_fn_t dequant_worker_fn = hmx_get_dequant_worker_fn(weight_type, is_tiled); const size_t vtcm_budget = ctx->vtcm_size; const int m_chunk_n_rows = kparams->m_chunk; @@ -3079,11 +2951,9 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k const int act_threads = kparams->n_act_threads; const struct fastdiv_values * act_threads_div = &kparams->div_n_act_threads; const struct fastdiv_values * k_div = &kparams->div_ne00_padded; - const int tile_size = kparams->tile_size; - const int aligned_tile_size = kparams->aligned_tile_size; - const uint32_t dma_dst_stride = is_quant ? aligned_tile_size : row_stride; - const uint32_t dma_width_bytes = is_quant ? tile_size : row_stride; + const uint32_t dma_dst_stride = is_tiled ? aligned_tile_size : row_stride; + const uint32_t dma_width_bytes = is_tiled ? tile_size : row_stride; struct htp_mm_hmx_vtcm_layout L; htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_2D, weight_type, k, m_chunk_n_rows, n_chunk_n_cols, 1, pipeline, act_threads, aligned_tile_size, 0); @@ -3099,7 +2969,6 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k VTCM_LAYOUT_PTR(__fp16, base, L.off_weight[0]), VTCM_LAYOUT_PTR_OPTIONAL(__fp16, base, L.off_weight[1], pipeline) }; - __fp16 *vtcm_f16_act = VTCM_LAYOUT_PTR(__fp16, base, L.off_act); float *vtcm_f32_act = VTCM_LAYOUT_PTR(float, base, L.off_act_f32); __fp16 *vtcm_output = VTCM_LAYOUT_PTR(__fp16, base, L.off_dst[0]); @@ -3141,13 +3010,23 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k if (pipeline) { hmx_matmul_job_t job_slots[2]; + void *vtcm_raw_bufs[4] = { + vtcm_weight_raw[0], + vtcm_weight_raw[1], + dequant_worker_fn ? vtcm_weight_raw[0] : vtcm_scratch0, + dequant_worker_fn ? vtcm_weight_raw[1] : vtcm_scratch1, + }; + void *vtcm_weight_bufs[4] = { + dequant_worker_fn ? vtcm_scratch0 : vtcm_weight_raw[0], + dequant_worker_fn ? vtcm_scratch1 : vtcm_weight_raw[1], + vtcm_scratch0, + vtcm_scratch1, + }; + void *vtcm_output_bufs[2] = { vtcm_output, vtcm_scratch2 }; for (size_t mr = (size_t) m_start; mr < mr_end; mr += m_chunk_n_rows) { const size_t n_rows = hex_smin(mr_end - mr, m_chunk_n_rows); - void *vtcm_weight_bufs[2] = { vtcm_scratch0, vtcm_scratch1 }; - void *vtcm_output_bufs[2] = { vtcm_output, vtcm_scratch2 }; - struct activation_transfer_params act_params = { .ctx = ctx, .dst = vtcm_f16_act, @@ -3180,17 +3059,17 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k const int dst_cols = (int) dst->ne[0]; const int n_chunk_cnt = hmx_ceil_div(n, n_chunk_n_cols); - const uint32_t dma_src_stride = is_quant ? tile_size : weight_stride; + const uint32_t dma_src_stride = is_tiled ? tile_size : weight_stride; const size_t n_cols_A0 = hex_smin(n - 0 * n_chunk_n_cols, n_chunk_n_cols); - const uint32_t height_A0 = is_quant ? hmx_ceil_div(n_cols_A0, 32) * n_k_tiles : n_cols_A0; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[0], weight), + const uint32_t height_A0 = is_tiled ? hmx_ceil_div(n_cols_A0, 32) * n_weight_tiles : n_cols_A0; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height_A0); if (1 < n_chunk_cnt) { const size_t n_cols_A1 = hex_smin(n - 1 * n_chunk_n_cols, n_chunk_n_cols); - const uint32_t height_A1 = is_quant ? hmx_ceil_div(n_cols_A1, 32) * n_k_tiles : n_cols_A1; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[1], weight + n_chunk_n_cols * weight_stride), + const uint32_t height_A1 = is_tiled ? hmx_ceil_div(n_cols_A1, 32) * n_weight_tiles : n_cols_A1; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[1], weight + n_chunk_n_cols * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_A1); } @@ -3204,18 +3083,18 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k void * curr_raw = (void *) dma_queue_pop(weight_dma).dst; dequantize_tiled_weight_chunk_to_fp16_tiles( - ctx, vtcm_weight_bufs[i % 2], curr_raw, + ctx, vtcm_weight_bufs[i % 4], curr_raw, n_cols, k, row_stride, weight_type, n_k_tiles, n_k_tiles_div, dequant_worker_fn, n_threads); if (i + 2 < n_chunk_cnt) { - const uint32_t height_p2 = is_quant ? hmx_ceil_div(n_cols_p2, 32) * n_k_tiles : n_cols_p2; - dma_queue_push(weight_dma, dma_make_data(curr_raw, weight + nc_p2 * weight_stride), + const uint32_t height_p2 = is_tiled ? hmx_ceil_div(n_cols_p2, 32) * n_weight_tiles : n_cols_p2; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[(i + 2) % 4], weight + nc_p2 * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_p2); } hmx_matmul_job_init(&job_slots[i % 2], (__fp16 *) vtcm_output_bufs[i % 2], - (__fp16 *) vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 2], + (__fp16 *) vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 4], vtcm_scales, hmx_ceil_div(n_rows, HTP_MM_HMX_TILE_N_ROWS), hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS), k / HTP_MM_HMX_TILE_N_ROWS); hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_matmul_worker_fn, &job_slots[i % 2])); @@ -3244,6 +3123,9 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k } } else { hmx_matmul_job_t job; + void *vtcm_raw_bufs[2] = { vtcm_weight_raw[0], dequant_worker_fn ? vtcm_weight_raw[0] : vtcm_scratch0 }; + void *vtcm_weight_bufs[2] = { dequant_worker_fn ? vtcm_scratch0 : vtcm_weight_raw[0], vtcm_scratch0 }; + for (size_t mr = (size_t) m_start; mr < mr_end; mr += m_chunk_n_rows) { const size_t n_rows = hex_smin(mr_end - mr, m_chunk_n_rows); @@ -3277,16 +3159,18 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k const size_t weight_stride = src_w->nb[1]; const size_t dst_stride = dst->nb[1] / sizeof(float); const int dst_cols = (int) dst->ne[0]; + const int n_chunk_cnt = hmx_ceil_div(n, n_chunk_n_cols); - const uint32_t dma_src_stride = is_quant ? tile_size : weight_stride; + const uint32_t dma_src_stride = is_tiled ? tile_size : weight_stride; if (n > 0) { const size_t n_cols = hex_smin(n, n_chunk_n_cols); - const uint32_t height = is_quant ? hmx_ceil_div(n_cols, 32) * n_k_tiles : n_cols; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight_raw[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height); + const uint32_t height = is_tiled ? hmx_ceil_div(n_cols, 32) * n_weight_tiles : n_cols; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height); } - for (size_t nc = 0; nc < n; nc += n_chunk_n_cols) { + for (int i = 0; i < n_chunk_cnt; ++i) { + const size_t nc = (size_t) i * n_chunk_n_cols; const size_t n_cols = hex_smin(n - nc, n_chunk_n_cols); const size_t n_row_tiles = hmx_ceil_div(n_rows, HTP_MM_HMX_TILE_N_ROWS); const size_t n_col_tiles = hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS); @@ -3294,18 +3178,18 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k void * curr_raw = (void *) dma_queue_pop(weight_dma).dst; dequantize_tiled_weight_chunk_to_fp16_tiles( - ctx, vtcm_scratch0, curr_raw, + ctx, vtcm_weight_bufs[i % 2], curr_raw, n_cols, k, row_stride, weight_type, n_k_tiles, n_k_tiles_div, dequant_worker_fn, n_threads); const size_t nc_next = nc + n_chunk_n_cols; if (nc_next < n) { const size_t n_cols_next = hex_smin(n - nc_next, n_chunk_n_cols); - const uint32_t height_next = is_quant ? hmx_ceil_div(n_cols_next, 32) * n_k_tiles : n_cols_next; - dma_queue_push(weight_dma, dma_make_data(curr_raw, weight + nc_next * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_next); + const uint32_t height_next = is_tiled ? hmx_ceil_div(n_cols_next, 32) * n_weight_tiles : n_cols_next; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[(i + 1) % 2], weight + nc_next * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_next); } - hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, vtcm_scratch0, vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); + hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 2], vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_matmul_worker_fn, &job)); hmx_queue_pop(ctx->hmx_queue); @@ -3322,30 +3206,30 @@ static int hmx_mm_nx_2d_f32(struct htp_ops_context * octx, const struct htp_mm_k return HTP_STATUS_OK; } -static inline dma_addr_t hmx_mm_weight_batch_data(const hmx_mm_f16_f32_batched_params_t *params, +static inline dma_addr_t hmx_mm_weight_batch_data(const hmx_mm_batched_params_t *params, int dst_b2, int dst_b3) { const size_t b2_idx = (params->r2 <= 1) ? (size_t) dst_b2 : (size_t) fastdiv((uint32_t) dst_b2, ¶ms->div_r2); const size_t b3_idx = (params->r3 <= 1) ? (size_t) dst_b3 : (size_t) fastdiv((uint32_t) dst_b3, ¶ms->div_r3); return params->weight + b2_idx * params->src0_nb2 + b3_idx * params->src0_nb3; } -static inline dma_addr_t hmx_mm_act_batch_addr(const hmx_mm_f16_f32_batched_params_t *params, +static inline dma_addr_t hmx_mm_act_batch_addr(const hmx_mm_batched_params_t *params, int dst_b2, int dst_b3) { return params->act_dma_addr + dst_b2 * params->act_nb2 + dst_b3 * params->act_nb3; } -static inline float *hmx_mm_dst_batch_ptr(const hmx_mm_f16_f32_batched_params_t *params, +static inline float *hmx_mm_dst_batch_ptr(const hmx_mm_batched_params_t *params, int dst_b2, int dst_b3) { return (float *) ((uint8_t *) params->dst + (size_t) dst_b2 * params->dst_nb2 + (size_t) dst_b3 * params->dst_nb3); } -static int hmx_mm_f16_f32_batched_simple(struct htp_context *ctx, - const hmx_mm_f16_f32_batched_params_t *params, - int m_chunk, int n_chunk, int pipeline, int n_threads, int act_threads, int vtcm_size, - const struct fastdiv_values * act_threads_div, const struct fastdiv_values * k_div) { +static int hmx_mm_batched_simple(struct htp_context *ctx, + const hmx_mm_batched_params_t *params, + int m_chunk, int n_chunk, int pipeline, int n_threads, int act_threads, int vtcm_size, + const struct fastdiv_values * act_threads_div, const struct fastdiv_values * k_div) { int ret = 0; for (int b3 = 0; b3 < params->ne13 && ret == 0; ++b3) { for (int b2 = 0; b2 < params->ne12 && ret == 0; ++b2) { @@ -3357,54 +3241,53 @@ static int hmx_mm_f16_f32_batched_simple(struct htp_context *ctx, hmx_mm_act_batch_addr(params, b2, b3), hmx_mm_weight_batch_data(params, b2, b3), params->m, params->k, params->n, - params->act_stride, params->act_elem_size, params->weight_stride * (int)sizeof(__fp16), - HTP_TYPE_F16, params->k, params->dst_stride, params->bias_stride, params->n, + params->act_stride, params->act_elem_size, params->weight_stride, + params->weight_type, params->k, params->dst_stride, params->bias_stride, params->dst_cols, m_chunk, n_chunk, pipeline, n_threads, act_threads, - act_threads_div, k_div, 0, 0, vtcm_size); + act_threads_div, k_div, params->tile_size, params->aligned_tile_size, vtcm_size); } } return ret; } -static int hmx_mm_f16_f32_batched(struct htp_context *ctx, const hmx_mm_f16_f32_batched_params_t *params, - int m_chunk, int n_chunk, int pipeline, int n_threads, int act_threads, - const struct fastdiv_values * act_threads_div, - const struct fastdiv_values * k_div, - int vtcm_size) { - if (params->act_stride < params->k || params->weight_stride < params->k || params->dst_stride < params->n) { return -1; } +static int hmx_mm_batched(struct htp_context *ctx, const hmx_mm_batched_params_t *params, + int m_chunk, int n_chunk, int pipeline, int n_threads, int act_threads, + const struct fastdiv_values * act_threads_div, + const struct fastdiv_values * k_div, + int vtcm_size) { + const size_t row_stride = htp_tensor_get_row_size(params->weight_type, params->k); + if (row_stride == 0) { return -1; } + if (params->act_stride < params->k || (params->tile_size == 0 && (size_t) params->weight_stride < row_stride) || params->dst_stride < params->dst_cols) { return -1; } if (params->ne02 <= 0 || params->ne03 <= 0 || params->ne12 <= 0 || params->ne13 <= 0) { return -1; } if (params->ne12 % params->ne02 != 0 || params->ne13 % params->ne03 != 0) { return -1; } // N (the weight row count) does not have to be 32-aligned: if (params->k % 32 != 0) { return -1; } - if (!hex_is_aligned(params->dst, VLEN) || (params->act_dma_addr & (VLEN - 1)) != 0) { return -1; } + if (!hex_is_aligned(params->dst, sizeof(float))) { return -1; } const int group_size = params->r2; const size_t vtcm_budget = ctx->vtcm_size; // Check if the precomputed parameters are grouped or simple. // If simple, or if group_size <= 1, we use simple fallback loop. - // Grouped path is only valid if group_size > 1 and it fits within VTCM budget. - bool run_grouped = (group_size > 1 && (size_t)vtcm_size <= vtcm_budget); + // Grouped path is only valid for flat F16 if group_size > 1 and it fits within VTCM budget. + bool run_grouped = (params->weight_type == HTP_TYPE_F16 && params->tile_size == 0 && group_size > 1 && (size_t)vtcm_size <= vtcm_budget); if (!run_grouped) { - return hmx_mm_f16_f32_batched_simple(ctx, params, m_chunk, n_chunk, pipeline, n_threads, act_threads, vtcm_size, act_threads_div, k_div); + return hmx_mm_batched_simple(ctx, params, m_chunk, n_chunk, pipeline, n_threads, act_threads, vtcm_size, act_threads_div, k_div); } struct htp_thread_trace * tr = &ctx->trace[0]; htp_trace_event_start(tr, HTP_TRACE_EVT_INIT, 0); - const size_t vec_dot_size = params->k * sizeof(__fp16); - size_t m_chunk_n_rows = m_chunk; size_t n_chunk_n_cols = n_chunk; - size_t vtcm_used = vtcm_size; struct htp_mm_hmx_vtcm_layout L; - htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_F16_BATCHED, HTP_TYPE_F16, params->k, m_chunk_n_rows, n_chunk_n_cols, group_size, false, act_threads, 0, params->bias_bytes); + htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_BATCHED, HTP_TYPE_F16, params->k, m_chunk_n_rows, n_chunk_n_cols, group_size, false, act_threads, 0, params->bias_bytes); if (L.total_bytes > vtcm_budget) { FARF(HIGH, "%s: grouped layout overflowed VTCM, falling back to simple batched loop", __func__); htp_trace_event_stop(tr, HTP_TRACE_EVT_INIT, 0); - return hmx_mm_f16_f32_batched_simple(ctx, params, m_chunk, n_chunk, pipeline, n_threads, act_threads, vtcm_size, act_threads_div, k_div); + return hmx_mm_batched_simple(ctx, params, m_chunk, n_chunk, pipeline, n_threads, act_threads, vtcm_size, act_threads_div, k_div); } uint8_t * const base = (uint8_t *) ctx->vtcm_base; @@ -3431,7 +3314,7 @@ static int hmx_mm_f16_f32_batched(struct htp_context *ctx, const hmx_mm_f16_f32_ L.total_bytes, vtcm_budget); const size_t fp16_row_bytes = (size_t) params->k * sizeof(__fp16); - const size_t weight_row_bytes = (size_t) params->weight_stride * sizeof(__fp16); + const size_t weight_row_bytes = (size_t) params->weight_stride; htp_trace_event_stop(tr, HTP_TRACE_EVT_INIT, 0); @@ -3481,7 +3364,7 @@ static int hmx_mm_f16_f32_batched(struct htp_context *ctx, const hmx_mm_f16_f32_ } if (n_chunk_n_cols < (size_t) params->n) { const size_t n_cols_second = hex_smin((size_t) params->n - n_chunk_n_cols, n_chunk_n_cols); - const dma_addr_t second_weight_chunk = weight_group + n_chunk_n_cols * params->weight_stride * sizeof(__fp16); + const dma_addr_t second_weight_chunk = weight_group + n_chunk_n_cols * weight_row_bytes; dma_queue_push(weight_dma, dma_make_data(vtcm_scratch1, second_weight_chunk), fp16_row_bytes, weight_row_bytes, fp16_row_bytes, n_cols_second); } @@ -3500,7 +3383,7 @@ static int hmx_mm_f16_f32_batched(struct htp_context *ctx, const hmx_mm_f16_f32_ const size_t nc_next = nc + n_chunk_n_cols * 2; if (nc_next < (size_t) params->n) { const size_t n_cols_next = hex_smin((size_t) params->n - nc_next, n_chunk_n_cols); - const dma_addr_t next_weight_chunk = weight_group + nc_next * params->weight_stride * sizeof(__fp16); + const dma_addr_t next_weight_chunk = weight_group + nc_next * weight_row_bytes; dma_queue_push(weight_dma, dma_make_data(curr_raw, next_weight_chunk), fp16_row_bytes, weight_row_bytes, fp16_row_bytes, n_cols_next); @@ -3519,7 +3402,7 @@ static int hmx_mm_f16_f32_batched(struct htp_context *ctx, const hmx_mm_f16_f32_ { float *output = hmx_mm_dst_batch_ptr(params, b2_base + g, b3) + mr * params->dst_stride + nc; const float *bias_chunk = has_bias ? (vtcm_bias + mr * params->bias_stride + nc) : NULL; - int chunk_dst_cols = params->n - (int)nc; + int chunk_dst_cols = params->dst_cols - (int)nc; if (chunk_dst_cols > 0) { transfer_output_chunk_threaded(ctx, output, bias_chunk, vtcm_output, (int) n_rows, (int) n_cols, params->dst_stride, params->bias_stride, chunk_dst_cols, n_threads); @@ -3642,6 +3525,8 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, size_t dst_nb1, size_t dst_nb2, int weight_stride, int weight_type, + int tile_size, + int aligned_tile_size, const struct mmid_row_mapping *matrix_rows, int cur_a, int mapping_stride, @@ -3658,47 +3543,28 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, if (k % 32 != 0 || n % 32 != 0) { return -1; } if (!hex_is_aligned(dst, VLEN) || !hex_is_aligned(activation, VLEN)) { return -1; } - size_t row_stride = htp_mm_get_tiled_row_stride(weight_type, k); + size_t row_stride = htp_tensor_get_row_size(weight_type, k); if (row_stride == 0) { return -1; } - worker_callback_t dequant_worker_fn = NULL; - switch (weight_type) { - case HTP_TYPE_Q4_0: dequant_worker_fn = dequantize_tiled_worker_loop_q4_0; break; - case HTP_TYPE_IQ4_NL: dequant_worker_fn = dequantize_tiled_worker_loop_iq4_nl; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: dequant_worker_fn = dequantize_tiled_worker_loop_q4_1; break; - case HTP_TYPE_MXFP4: dequant_worker_fn = dequantize_tiled_worker_loop_mxfp4; break; - case HTP_TYPE_Q8_0: dequant_worker_fn = dequantize_tiled_worker_loop_q8_0; break; - case HTP_TYPE_Q5_K: dequant_worker_fn = dequantize_tiled_worker_loop_q5_k; break; - case HTP_TYPE_Q6_K: dequant_worker_fn = dequantize_tiled_worker_loop_q6_k; break; - case HTP_TYPE_Q3_K: dequant_worker_fn = dequantize_tiled_worker_loop_q3_k; break; - case HTP_TYPE_Q2_K: dequant_worker_fn = dequantize_tiled_worker_loop_q2_k; break; - case HTP_TYPE_F16: dequant_worker_fn = convert_f16_worker_loop; break; - case HTP_TYPE_F32: dequant_worker_fn = quantize_f32_worker_loop; break; - default: - return -1; - } - const int n_k_tiles = k / HTP_MM_HMX_TILE_N_COLS; + const uint32_t n_weight_tiles = k / htp_tensor_get_tile_k(weight_type); const struct fastdiv_values n_k_tiles_div = init_fastdiv_values(n_k_tiles); - const bool is_quant = (weight_type != HTP_TYPE_F16 && weight_type != HTP_TYPE_F32); - const size_t vec_dot_size = k * sizeof(__fp16); const size_t vtcm_budget = ctx->vtcm_size; size_t vtcm_used = 0; - int tile_size = htp_mm_get_weight_tile_size(weight_type); - int aligned_tile_size = htp_mm_get_weight_aligned_tile_size(weight_type); + const bool is_tiled = (tile_size > 0); + tiled_dequant_task_fn_t dequant_worker_fn = hmx_get_dequant_worker_fn(weight_type, is_tiled); - const uint32_t dma_dst_stride = is_quant ? aligned_tile_size : row_stride; - const uint32_t dma_src_stride = is_quant ? tile_size : weight_stride; - const uint32_t dma_width_bytes = is_quant ? tile_size : row_stride; + const uint32_t dma_dst_stride = is_tiled ? aligned_tile_size : row_stride; + const uint32_t dma_src_stride = is_tiled ? tile_size : weight_stride; + const uint32_t dma_width_bytes = is_tiled ? tile_size : row_stride; - const size_t qweight_row_stride = is_quant ? (size_t)(n_k_tiles * aligned_tile_size) / 32 : 0; - const size_t weight_row_stride = is_quant ? qweight_row_stride : row_stride; + const size_t qweight_row_stride = is_tiled ? (size_t)(n_weight_tiles * aligned_tile_size) / 32 : 0; + const size_t weight_row_stride = is_tiled ? qweight_row_stride : row_stride; size_t size_per_n = 0, size_per_m = 0, size_per_mn = 0; htp_mm_hmx_get_2d_chunk_costs(weight_type, k, /*pipeline=*/false, aligned_tile_size, @@ -3738,6 +3604,9 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, htp_trace_event_stop(tr, HTP_TRACE_EVT_INIT, 0); hmx_matmul_job_t job; + void *vtcm_raw_bufs[2] = { vtcm_weight, dequant_worker_fn ? vtcm_weight : vtcm_scratch0 }; + void *vtcm_weight_bufs[2] = { dequant_worker_fn ? vtcm_scratch0 : vtcm_weight, vtcm_scratch0 }; + const int n_chunk_cnt = hmx_ceil_div(n, n_chunk_n_cols); for (size_t mr = (size_t) m_start; mr < (size_t) m_end; mr += m_chunk_n_rows) { const size_t n_rows = hex_smin((size_t) m_end - mr, m_chunk_n_rows); @@ -3750,12 +3619,13 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, // A0: Pre-fetch the first weight chunk (nc = 0) if (n > 0) { const size_t n_cols = hex_smin((size_t) n, n_chunk_n_cols); - const uint32_t height = is_quant ? hmx_ceil_div(n_cols, 32) * n_k_tiles : n_cols; - dma_queue_push(weight_dma, dma_make_data(vtcm_weight, weight), + const uint32_t height = is_tiled ? hmx_ceil_div(n_cols, 32) * n_weight_tiles : n_cols; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[0], weight), dma_dst_stride, dma_src_stride, dma_width_bytes, height); } - for (size_t nc = 0; nc < (size_t) n; nc += n_chunk_n_cols) { + for (int i = 0; i < n_chunk_cnt; ++i) { + const size_t nc = (size_t) i * n_chunk_n_cols; const size_t n_cols = hex_smin((size_t) n - nc, n_chunk_n_cols); const size_t n_col_tiles = hmx_ceil_div(n_cols, HTP_MM_HMX_TILE_N_COLS); @@ -3764,7 +3634,7 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, // B: Weight Dequantize (Threaded) dequantize_tiled_weight_chunk_to_fp16_tiles( - ctx, vtcm_scratch0, curr_raw, + ctx, vtcm_weight_bufs[i % 2], curr_raw, n_cols, k, row_stride, weight_type, n_k_tiles, n_k_tiles_div, dequant_worker_fn, n_threads ); @@ -3773,13 +3643,13 @@ static int hmx_mm_id_2d_f32(struct htp_context *ctx, const size_t nc_next = nc + n_chunk_n_cols; if (nc_next < (size_t) n) { const size_t n_cols_next = hex_smin((size_t) n - nc_next, n_chunk_n_cols); - const uint32_t height_next = is_quant ? hmx_ceil_div(n_cols_next, 32) * n_k_tiles : n_cols_next; - dma_queue_push(weight_dma, dma_make_data(curr_raw, weight + nc_next * weight_stride), + const uint32_t height_next = is_tiled ? hmx_ceil_div(n_cols_next, 32) * n_weight_tiles : n_cols_next; + dma_queue_push(weight_dma, dma_make_data(vtcm_raw_bufs[(i + 1) % 2], weight + nc_next * weight_stride), dma_dst_stride, dma_src_stride, dma_width_bytes, height_next); } // C: HMX Compute (Queue-based) - hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, vtcm_scratch0, vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); + hmx_matmul_job_init(&job, vtcm_output, vtcm_f16_act, (__fp16 *) vtcm_weight_bufs[i % 2], vtcm_scales, n_row_tiles, n_col_tiles, k / HTP_MM_HMX_TILE_N_ROWS); hmx_queue_push(ctx->hmx_queue, hmx_queue_make_desc(hmx_matmul_worker_fn, &job)); hmx_queue_pop(ctx->hmx_queue); @@ -3803,7 +3673,6 @@ static int hmx_mm_op_matmul(struct htp_ops_context * octx, const struct htp_mm_k const int m_total = (int) act->ne[1]; const uint32_t act_elem_size = (act->type == HTP_TYPE_F16) ? sizeof(__fp16) : sizeof(float); const int act_stride = (int) (act->nb[1] / act_elem_size); - const int wgt_stride = (int)(src0->nb[1] / sizeof(__fp16)); int m_start = 0; int m_rows = m_total; @@ -3842,46 +3711,50 @@ static int hmx_mm_op_matmul(struct htp_ops_context * octx, const struct htp_mm_k int ret = -1; const int n_threads = kparams->n_threads; - if (kparams->kernel_type == HTP_MM_KERNEL_HMX_F16_BATCHED) { - hmx_mm_f16_f32_batched_params_t batch_params = { - .dst = dst_ptr, - .bias_addr = src2_addr, - .bias_bytes = src2_bytes, - .act_dma_addr = act_addr, - .weight = src0->data, - .weight_dma = octx->ctx->dma[0], - .m = m_rows, - .k = k, - .n = n, - .act_stride = act_stride, - .act_elem_size = act_elem_size, - .weight_stride = wgt_stride, - .dst_stride = dst_stride, - .bias_stride = src2_stride, - .ne02 = ne02, - .ne03 = ne03, - .ne12 = ne12, - .ne13 = ne13, - .src0_nb2 = src0->nb[2], - .src0_nb3 = src0->nb[3], - .act_nb2 = act->nb[2], - .act_nb3 = act->nb[3], - .dst_nb2 = dst->nb[2], - .dst_nb3 = dst->nb[3], - .bias_nb2 = src2_nb2, - .bias_nb3 = src2_nb3, - .r2 = (ne02 > 0) ? (ne12 / ne02) : 1, - .r3 = (ne03 > 0) ? (ne13 / ne03) : 1, - .div_r2 = kparams->div_r2, - .div_r3 = kparams->div_r3, + if (kparams->kernel_type == HTP_MM_KERNEL_HMX_BATCHED) { + hmx_mm_batched_params_t batch_params = { + .dst = dst_ptr, + .bias_addr = src2_addr, + .bias_bytes = src2_bytes, + .act_dma_addr = act_addr, + .weight = src0->data, + .weight_dma = octx->ctx->dma[0], + .m = m_rows, + .k = k, + .n = n, + .act_stride = act_stride, + .act_elem_size = act_elem_size, + .weight_stride = (int) src0->nb[1], + .weight_type = (int) src0->type, + .dst_stride = dst_stride, + .dst_cols = (int) dst->ne[0], + .bias_stride = src2_stride, + .tile_size = kparams->tile_size, + .aligned_tile_size = kparams->aligned_tile_size, + .ne02 = ne02, + .ne03 = ne03, + .ne12 = ne12, + .ne13 = ne13, + .src0_nb2 = src0->nb[2], + .src0_nb3 = src0->nb[3], + .act_nb2 = act->nb[2], + .act_nb3 = act->nb[3], + .dst_nb2 = dst->nb[2], + .dst_nb3 = dst->nb[3], + .bias_nb2 = src2_nb2, + .bias_nb3 = src2_nb3, + .r2 = (ne02 > 0) ? (ne12 / ne02) : 1, + .r3 = (ne03 > 0) ? (ne13 / ne03) : 1, + .div_r2 = kparams->div_r2, + .div_r3 = kparams->div_r3, }; - ret = hmx_mm_f16_f32_batched(octx->ctx, &batch_params, - kparams->m_chunk, kparams->n_chunk, - kparams->pipeline, n_threads, - kparams->n_act_threads, - &kparams->div_n_act_threads, - &kparams->div_ne00_padded, - kparams->vtcm_size); + ret = hmx_mm_batched(octx->ctx, &batch_params, + kparams->m_chunk, kparams->n_chunk, + kparams->pipeline, n_threads, + kparams->n_act_threads, + &kparams->div_n_act_threads, + &kparams->div_ne00_padded, + kparams->vtcm_size); } else { ret = hmx_mm_2d_f32( octx->ctx, octx->ctx->dma[0], dst_ptr, src2_addr, src2_bytes, @@ -3903,16 +3776,6 @@ static int hmx_mm_op_matmul(struct htp_ops_context * octx, const struct htp_mm_k return HTP_STATUS_OK; } -static inline void htp_mm_tensor_collapse_rows(struct htp_tensor * c, const struct htp_tensor * t, uint32_t stride) { - *c = *t; - c->ne[1] = t->ne[1] * t->ne[2] * t->ne[3]; - c->ne[2] = 1; - c->ne[3] = 1; - c->nb[1] = stride; - c->nb[2] = c->nb[1] * c->ne[1]; - c->nb[3] = c->nb[2]; -} - static int op_matmul_impl(struct htp_ops_context * octx) { const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; @@ -3929,36 +3792,6 @@ static int op_matmul_impl(struct htp_ops_context * octx) { } int op_matmul(struct htp_ops_context * octx) { - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; - - if (kparams->collapse) { - const struct htp_tensor * act = octx->src[1]; - const struct htp_tensor * dst = octx->dst; - const uint32_t s_act = (act->ne[1] > 1) ? act->nb[1] : ((act->ne[2] > 1) ? act->nb[2] : act->nb[3]); - const uint32_t sd = (dst->ne[1] > 1) ? dst->nb[1] : ((dst->ne[2] > 1) ? dst->nb[2] : dst->nb[3]); - struct htp_tensor act_collapsed, dst_collapsed; - htp_mm_tensor_collapse_rows(&act_collapsed, act, s_act); - htp_mm_tensor_collapse_rows(&dst_collapsed, dst, sd); - octx->src[1] = &act_collapsed; - octx->dst = &dst_collapsed; - - struct htp_tensor src2_collapsed; - const struct htp_tensor * src2 = octx->src[2]; - if (src2 && (src2->ne[1] * src2->ne[2] * src2->ne[3] > 1)) { - const uint32_t s2 = (src2->ne[1] > 1) ? src2->nb[1] : ((src2->ne[2] > 1) ? src2->nb[2] : src2->nb[3]); - htp_mm_tensor_collapse_rows(&src2_collapsed, src2, s2); - octx->src[2] = &src2_collapsed; - } - - const int status = op_matmul_impl(octx); - octx->src[1] = act; - octx->dst = dst; - if (src2) { - octx->src[2] = src2; - } - return status; - } - return op_matmul_impl(octx); } @@ -4014,6 +3847,7 @@ static int hmx_mm_op_matmul_id( nb11, nb12, nb1, nb2, (int) src0->nb[1], (int) src0->type, + kparams->tile_size, kparams->aligned_tile_size, matrix_rows, cur_a, mmctx->mapping_stride, m_start, m_end, (int) octx->n_threads); if (ret != 0) { @@ -4041,7 +3875,7 @@ static int hvx_mm_matmul_id( const struct htp_tensor * restrict ids = octx->src[2]; const size_t src0_row_size = nb01; - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (ne10 + qk - 1) / qk; const uint32_t total_nb = act_nrows * nb; @@ -4049,7 +3883,7 @@ static int hvx_mm_matmul_id( uint32_t n_quant_tasks = 1; if (act_nrows < octx->n_threads) { n_quant_tasks = MIN(total_nb, octx->n_threads); - quant_task_func = htp_mm_act_quant_block_func(src0->type); + quant_task_func = htp_mm_act_quant_block_func(src0->type, act->type); for (uint32_t ith = 0; ith < n_quant_tasks; ++ith) { uint32_t ib_first = (total_nb * ith) / n_quant_tasks; uint32_t ib_last = (total_nb * (ith + 1)) / n_quant_tasks; @@ -4060,9 +3894,9 @@ static int hvx_mm_matmul_id( } } else { n_quant_tasks = MIN(act_nrows, octx->n_threads); - quant_task_func = htp_mm_act_quant_row_func(src0->type); + quant_task_func = htp_mm_act_quant_row_func(src0->type, act->type); } - size_t act_row_size = htp_mm_weight_has_offset(src0->type) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); + size_t act_row_size = htp_mm_tiled_act_row_size(src0->type, ne10); struct htp_mm_hvx_vtcm_layout L; htp_mm_hvx_vtcm_layout_build(&L, kparams->kernel_type, src0->type, ne10, act_nrows, octx->n_threads, @@ -4093,7 +3927,7 @@ static int hvx_mm_matmul_id( mmctx->vtcm_src0_stride = src0_row_size_padded; mmctx->vtcm_act_stride = act_row_size; - mmctx->vtcm_act_raw_stride = hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + mmctx->vtcm_act_raw_stride = htp_mm_act_raw_row_size(ne10); mmctx->vtcm_src0_size_per_thread = fastdiv(L.src0_bytes, &octx->n_threads_div); mmctx->vtcm_act_size_per_thread = L.act_bytes; @@ -4177,6 +4011,7 @@ static int hmx_mm_op_matmul_id_nx( act->nb[1], act->nb[2], dst->nb[1], dst->nb[2], (int) src_w->nb[1], (int) src_w->type, + kparams->tile_size, kparams->aligned_tile_size, matrix_rows, cur_a, mmctx->mapping_stride, m_start, m_end, (int) octx->n_threads); if (ret != 0) { @@ -4207,7 +4042,7 @@ static int hvx_mm_matmul_id_nx( const struct htp_tensor * restrict ids = octx->src[n_weights + 1]; const size_t src0_row_size = src0->nb[1]; - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (act->ne[0] + qk - 1) / qk; const uint32_t total_nb = act_nrows * nb; @@ -4215,7 +4050,7 @@ static int hvx_mm_matmul_id_nx( uint32_t n_quant_tasks = 1; if (act_nrows < octx->n_threads) { n_quant_tasks = MIN(total_nb, octx->n_threads); - quant_task_func = htp_mm_act_quant_block_func(src0->type); + quant_task_func = htp_mm_act_quant_block_func(src0->type, act->type); for (uint32_t ith = 0; ith < n_quant_tasks; ++ith) { uint32_t ib_first = (total_nb * ith) / n_quant_tasks; uint32_t ib_last = (total_nb * (ith + 1)) / n_quant_tasks; @@ -4226,9 +4061,9 @@ static int hvx_mm_matmul_id_nx( } } else { n_quant_tasks = MIN(act_nrows, octx->n_threads); - quant_task_func = htp_mm_act_quant_row_func(src0->type); + quant_task_func = htp_mm_act_quant_row_func(src0->type, act->type); } - size_t act_row_size = htp_mm_weight_has_offset(src0->type) ? htp_mm_q8_1_tiled_row_size(act->ne[0]) : htp_mm_q8_0_tiled_row_size(act->ne[0]); + size_t act_row_size = htp_mm_tiled_act_row_size(src0->type, act->ne[0]); struct htp_mm_hvx_vtcm_layout L; htp_mm_hvx_vtcm_layout_build(&L, kparams->kernel_type, src0->type, act->ne[0], act_nrows, octx->n_threads, @@ -4250,7 +4085,7 @@ static int hvx_mm_matmul_id_nx( mmctx->vtcm_src0_stride = 0; mmctx->vtcm_act_stride = act_row_size; - mmctx->vtcm_act_raw_stride = hex_round_up(act->ne[0] * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + mmctx->vtcm_act_raw_stride = htp_mm_act_raw_row_size(act->ne[0]); mmctx->vtcm_src0_size_per_thread = fastdiv(L.src0_bytes, &octx->n_threads_div); mmctx->vtcm_act_size_per_thread = L.act_bytes; @@ -4277,7 +4112,7 @@ static int hvx_mm_matmul_id_nx( return HTP_STATUS_OK; } -static inline void scan_expert_ids_n( +static __attribute__((noinline)) uint32_t scan_expert_ids_n( const struct htp_tensor * ids, const uint32_t n_ids, uint32_t n_as, @@ -4287,15 +4122,17 @@ static inline void scan_expert_ids_n( ) { const size_t ids_nb1 = ids->nb[1]; const uint8_t * ids_data = (const uint8_t *) ids->data; + uint32_t n_skipped = 0; for (uint32_t iid1 = 0; iid1 < ids->ne[1]; ++iid1) { const int32_t * row_ptr = (const int32_t *) (ids_data + iid1 * ids_nb1); for (uint32_t id = 0; id < n_ids; ++id) { const int32_t i02 = row_ptr[id]; if (i02 < 0) { + n_skipped++; continue; } - assert(i02 < n_as); + assert(i02 >= 0 && i02 < (int32_t) n_as); if (matrix_rows) { matrix_rows[i02 * mapping_stride + counts[i02]] = (struct mmid_row_mapping) { id, iid1 }; @@ -4303,9 +4140,10 @@ static inline void scan_expert_ids_n( counts[i02] += 1; } } + return n_skipped; } -static inline void scan_expert_ids( +static __attribute__((noinline)) uint32_t scan_expert_ids( const struct htp_tensor * ids, uint32_t n_ids, uint32_t n_as, @@ -4317,23 +4155,25 @@ static inline void scan_expert_ids( if (ids_nb0 == 4) { switch (n_ids) { - case 8: scan_expert_ids_n(ids, 8, n_as, counts, matrix_rows, mapping_stride); break; - case 4: scan_expert_ids_n(ids, 4, n_as, counts, matrix_rows, mapping_stride); break; - case 2: scan_expert_ids_n(ids, 2, n_as, counts, matrix_rows, mapping_stride); break; - default: scan_expert_ids_n(ids, n_ids, n_as, counts, matrix_rows, mapping_stride); break; + case 8: return scan_expert_ids_n(ids, 8, n_as, counts, matrix_rows, mapping_stride); + case 4: return scan_expert_ids_n(ids, 4, n_as, counts, matrix_rows, mapping_stride); + case 2: return scan_expert_ids_n(ids, 2, n_as, counts, matrix_rows, mapping_stride); + default: return scan_expert_ids_n(ids, n_ids, n_as, counts, matrix_rows, mapping_stride); } } else { // Strided fallback const size_t ids_nb1 = ids->nb[1]; const uint8_t * ids_data = (const uint8_t *) ids->data; + uint32_t n_skipped = 0; for (uint32_t iid1 = 0; iid1 < ids->ne[1]; ++iid1) { const int32_t * row_ptr = (const int32_t *) (ids_data + iid1 * ids_nb1); for (uint32_t id = 0; id < n_ids; ++id) { const int32_t i02 = *(const int32_t *) ((const uint8_t *) row_ptr + id * ids_nb0); if (i02 < 0) { + n_skipped++; continue; } - assert(i02 < n_as); + assert(i02 >= 0 && i02 < (int32_t) n_as); if (matrix_rows) { matrix_rows[i02 * mapping_stride + counts[i02]] = (struct mmid_row_mapping) { id, iid1 }; @@ -4341,7 +4181,122 @@ static inline void scan_expert_ids( counts[i02] += 1; } } + return n_skipped; + } +} + +static __attribute__((noinline)) uint32_t count_skipped_ids_single(const struct htp_tensor * ids, uint32_t n_ids) { + const uint8_t * ids_data = (const uint8_t *) ids->data; + const size_t ids_nb0 = ids->nb[0]; + uint32_t n_skipped = 0; + for (uint32_t id = 0; id < n_ids; ++id) { + const int32_t i02 = *(const int32_t *) (ids_data + id * ids_nb0); + if (i02 < 0) { + n_skipped++; + } + } + return n_skipped; +} + +// Zero rows for skipped slots (ids < 0). Matmuls only write rows that an expert owns. +static void zero_skipped_dst_rows( + struct htp_ops_context * octx, + const struct htp_tensor * ids, + uint32_t n_ids, + const struct htp_tensor * dst +) { + const uint32_t elem_size = (dst->type == HTP_TYPE_F16) ? sizeof(__fp16) : sizeof(float); + uint32_t col_start = 0; + uint32_t col_count = dst->ne[0]; + + if (octx->ctx->mdev.count > 1) { + const bool can_split = htp_tensor_can_row_partition(dst, elem_size); + const uint32_t chunk_elems = (dst->type == HTP_TYPE_F16) ? 64 : 32; + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( + dst->ne[0], can_split ? chunk_elems : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + col_start = range.start; + col_count = range.count; + } + + if (col_count == 0) { + return; + } + + const uint8_t * ids_data = (const uint8_t *) ids->data; + const size_t ids_nb0 = ids->nb[0]; + const size_t ids_nb1 = ids->nb[1]; + const size_t dst_nb1 = dst->nb[1]; + const size_t dst_nb2 = dst->nb[2]; + const uint32_t col_offset_bytes = col_start * elem_size; + + for (uint32_t iid1 = 0; iid1 < ids->ne[1]; ++iid1) { + const uint8_t * ids_row = ids_data + iid1 * ids_nb1; + uint8_t * dst_row_group = (uint8_t *) dst->data + iid1 * dst_nb2 + col_offset_bytes; + for (uint32_t id = 0; id < n_ids; ++id) { + const int32_t i02 = *(const int32_t *) (ids_row + id * ids_nb0); + if (i02 < 0) { + hvx_splat_u(dst_row_group + id * dst_nb1, Q6_V_vzero(), col_count, elem_size); + } + } + } +} + +static int htp_mmid_prepare_mapping( + struct htp_ops_context * octx, + const struct htp_tensor * ids, + uint32_t n_ids, + uint32_t n_as, + uint32_t act_nrows, + uint8_t ** out_mapping_buf, + uint32_t ** out_matrix_row_counts, + struct mmid_row_mapping ** out_matrix_rows, + uint32_t * out_mapping_stride, + uint32_t * out_n_skipped +) { + uint8_t * mapping_buf = octx->ctx->ddr_spad_base; + uint32_t mapping_stride = 1; + uint32_t * matrix_row_counts = (uint32_t *) mapping_buf; + struct mmid_row_mapping * matrix_rows = NULL; + uint32_t n_skipped = 0; + + if (act_nrows > 1) { + const size_t matrix_row_counts_size = n_as * sizeof(uint32_t); + assert(octx->ctx->ddr_spad_size >= matrix_row_counts_size); + + hex_l2fetch_block((const void *) ids->data, ids->ne[1] * ids->nb[1]); + + hvx_splat_u(matrix_row_counts, Q6_V_vzero(), n_as, sizeof(uint32_t)); + n_skipped = scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, NULL, 0); + + uint32_t max_count = hvx_reduce_max_i32((const uint8_t *) matrix_row_counts, n_as); + mapping_stride = max_count > 0 ? max_count : 1; + + size_t matrix_row_map_size = n_as * mapping_stride * sizeof(struct mmid_row_mapping); + const size_t total_map_size = matrix_row_counts_size + matrix_row_map_size; + + if (total_map_size > octx->ctx->ddr_spad_size) { + mapping_buf = memalign(128, total_map_size); + if (!mapping_buf) { + return HTP_STATUS_INTERNAL_ERR; + } + } + + matrix_row_counts = (uint32_t *) mapping_buf; + matrix_rows = (struct mmid_row_mapping *) (mapping_buf + matrix_row_counts_size); + + hvx_splat_u(matrix_row_counts, Q6_V_vzero(), n_as, sizeof(uint32_t)); + scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, matrix_rows, mapping_stride); + } else { + n_skipped = count_skipped_ids_single(ids, n_ids); } + + *out_mapping_buf = mapping_buf; + *out_matrix_row_counts = matrix_row_counts; + *out_matrix_rows = matrix_rows; + *out_mapping_stride = mapping_stride; + *out_n_skipped = n_skipped; + + return HTP_STATUS_OK; } int op_matmul_id(struct htp_ops_context * octx) { @@ -4379,38 +4334,21 @@ int op_matmul_id(struct htp_ops_context * octx) { const int n_ids = ids->ne[0]; // n_expert_used const int n_as = ne02; // n_expert - uint8_t * mapping_buf = octx->ctx->ddr_spad_base; - uint32_t mapping_stride = 1; - uint32_t * matrix_row_counts = (uint32_t *) mapping_buf; + uint8_t * mapping_buf = NULL; + uint32_t * matrix_row_counts = NULL; struct mmid_row_mapping * matrix_rows = NULL; + uint32_t mapping_stride = 1; + uint32_t n_skipped = 0; - if (act_nrows > 1) { - const size_t matrix_row_counts_size = n_as * sizeof(uint32_t); - assert(octx->ctx->ddr_spad_size >= matrix_row_counts_size); - - hex_l2fetch_block((const void *) ids->data, ids->ne[1] * ids->nb[1]); - - memset(matrix_row_counts, 0, matrix_row_counts_size); - scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, NULL, 0); - - uint32_t max_count = hvx_reduce_max_i32((const uint8_t *) matrix_row_counts, n_as); - mapping_stride = max_count > 0 ? max_count : 1; - - size_t matrix_row_map_size = n_as * mapping_stride * sizeof(struct mmid_row_mapping); - const size_t total_map_size = matrix_row_counts_size + matrix_row_map_size; - - if (total_map_size > octx->ctx->ddr_spad_size) { - mapping_buf = memalign(128, total_map_size); - if (!mapping_buf) { - return HTP_STATUS_INTERNAL_ERR; - } - } - - matrix_row_counts = (uint32_t *) mapping_buf; - matrix_rows = (struct mmid_row_mapping *) (mapping_buf + matrix_row_counts_size); + int map_status = htp_mmid_prepare_mapping(octx, ids, n_ids, n_as, act_nrows, + &mapping_buf, &matrix_row_counts, &matrix_rows, + &mapping_stride, &n_skipped); + if (map_status != HTP_STATUS_OK) { + return map_status; + } - memset(matrix_row_counts, 0, n_as * sizeof(uint32_t)); - scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, matrix_rows, mapping_stride); + if (n_skipped > 0) { + zero_skipped_dst_rows(octx, ids, n_ids, dst); } mmctx->matrix_row_counts = matrix_row_counts; @@ -4451,8 +4389,8 @@ int op_matmul_id(struct htp_ops_context * octx) { mmctx->src0_nrows_per_thread = fastdiv(nrows + octx->n_threads - 1, &octx->n_threads_div); mmctx->src0_nrows_per_thread = hex_round_up(mmctx->src0_nrows_per_thread, 32); - if (hvx_mm_init_vec_dot(mmctx, src0->type) == 0) { - s = hvx_mm_matmul_id(octx, mmctx, act_nrows > 1 ? hvx_mm_id : hvx_mv_id); + if (hvx_mm_init_tiled_vec_dot(mmctx, src0->type) == 0) { + s = hvx_mm_matmul_id(octx, mmctx, act_nrows > 1 ? hvx_mm_id_tiled : hvx_mv_id_tiled); } else { s = HTP_STATUS_NO_SUPPORT; } @@ -4502,38 +4440,26 @@ int op_matmul_id_nx(struct htp_ops_context * octx) { const int n_ids = ids->ne[0]; const int n_as = src0->ne[2]; - uint8_t * mapping_buf = octx->ctx->ddr_spad_base; - uint32_t mapping_stride = 1; - uint32_t * matrix_row_counts = (uint32_t *) mapping_buf; + uint8_t * mapping_buf = NULL; + uint32_t * matrix_row_counts = NULL; struct mmid_row_mapping * matrix_rows = NULL; + uint32_t mapping_stride = 1; + uint32_t n_skipped = 0; - if (act_nrows > 1) { - const size_t matrix_row_counts_size = n_as * sizeof(uint32_t); - assert(octx->ctx->ddr_spad_size >= matrix_row_counts_size); - - hex_l2fetch_block((const void *) ids->data, ids->ne[1] * ids->nb[1]); - - memset(matrix_row_counts, 0, matrix_row_counts_size); - scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, NULL, 0); - - uint32_t max_count = hvx_reduce_max_i32((const uint8_t *) matrix_row_counts, n_as); - mapping_stride = max_count > 0 ? max_count : 1; - - size_t matrix_row_map_size = n_as * mapping_stride * sizeof(struct mmid_row_mapping); - const size_t total_map_size = matrix_row_counts_size + matrix_row_map_size; + int map_status = htp_mmid_prepare_mapping(octx, ids, n_ids, n_as, act_nrows, + &mapping_buf, &matrix_row_counts, &matrix_rows, + &mapping_stride, &n_skipped); + if (map_status != HTP_STATUS_OK) { + return map_status; + } - if (total_map_size > octx->ctx->ddr_spad_size) { - mapping_buf = memalign(128, total_map_size); - if (!mapping_buf) { - return HTP_STATUS_INTERNAL_ERR; + if (n_skipped > 0) { + for (uint32_t p = 0; p < n_weights; ++p) { + const struct htp_tensor * restrict d = octx->dsts[p]; + if (d) { + zero_skipped_dst_rows(octx, ids, n_ids, d); } } - - matrix_row_counts = (uint32_t *) mapping_buf; - matrix_rows = (struct mmid_row_mapping *) (mapping_buf + matrix_row_counts_size); - - memset(matrix_row_counts, 0, n_as * sizeof(uint32_t)); - scan_expert_ids(ids, n_ids, n_as, matrix_row_counts, matrix_rows, mapping_stride); } mmctx->matrix_row_counts = matrix_row_counts; @@ -4551,8 +4477,8 @@ int op_matmul_id_nx(struct htp_ops_context * octx) { if (kparams->n_hmx) { s = hmx_mm_op_matmul_id_nx(octx, mmctx); } else { - if (hvx_mm_init_vec_dot(mmctx, src0->type) == 0) { - s = hvx_mm_matmul_id_nx(octx, mmctx, act_nrows > 1 ? hvx_mm_id_nx : hvx_mv_id_nx); + if (hvx_mm_init_tiled_vec_dot(mmctx, src0->type) == 0) { + s = hvx_mm_matmul_id_nx(octx, mmctx, act_nrows > 1 ? hvx_mm_id_nx_tiled : hvx_mv_id_nx_tiled); } else { s = HTP_STATUS_NO_SUPPORT; } @@ -4584,12 +4510,6 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { const struct htp_tensor * restrict src0 = octx->src[0]; // first weight const struct htp_tensor * restrict act = octx->src[n_weights]; // activation x - bool is_repacked = (src0->type == HTP_TYPE_Q4_0 || src0->type == HTP_TYPE_Q4_1 || - src0->type == HTP_TYPE_Q8_0 || src0->type == HTP_TYPE_IQ4_NL || - src0->type == HTP_TYPE_MXFP4 || src0->type == HTP_TYPE_Q4_K || - src0->type == HTP_TYPE_Q5_K || src0->type == HTP_TYPE_Q3_K || - src0->type == HTP_TYPE_Q2_K); - struct htp_mm_context mmctx_struct = {0}; struct htp_mm_context * mmctx = &mmctx_struct; mmctx->octx = octx; @@ -4601,13 +4521,12 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { mmctx->cur_m_rows = act_nrows; const size_t src0_row_size = src0->nb[1]; - const size_t src0_row_size_padded = hex_round_up(src0_row_size, 128); - if (hvx_mm_init_vec_dot(mmctx, src0->type) != 0) { + if (hvx_mm_init_tiled_vec_dot(mmctx, src0->type) != 0) { return HTP_STATUS_NO_SUPPORT; } - const uint32_t qk = QK_Q8_0_TILED; + const uint32_t qk = HTP_MM_ACT_BLOCK_K; const uint32_t nb = (act->ne[0] + qk - 1) / qk; const uint32_t total_nb = act_nrows * nb; @@ -4615,7 +4534,7 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { uint32_t n_quant_tasks = 1; if (act_nrows < octx->n_threads) { n_quant_tasks = MIN(total_nb, octx->n_threads); - quant_task_func = htp_mm_act_quant_block_func(src0->type); + quant_task_func = htp_mm_act_quant_block_func(src0->type, act->type); for (uint32_t ith = 0; ith < n_quant_tasks; ++ith) { uint32_t ib_first = (total_nb * ith) / n_quant_tasks; uint32_t ib_last = (total_nb * (ith + 1)) / n_quant_tasks; @@ -4626,12 +4545,10 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { } } else { n_quant_tasks = MIN(act_nrows, octx->n_threads); - quant_task_func = htp_mm_act_quant_row_func(src0->type); + quant_task_func = htp_mm_act_quant_row_func(src0->type, act->type); } - const size_t act_row_size = htp_mm_weight_has_offset(src0->type) - ? htp_mm_q8_1_tiled_row_size(act->ne[0]) - : htp_mm_q8_0_tiled_row_size(act->ne[0]); + const size_t act_row_size = htp_mm_tiled_act_row_size(src0->type, act->ne[0]); struct htp_mm_hvx_vtcm_layout L; htp_mm_hvx_vtcm_layout_build(&L, kparams->kernel_type, src0->type, act->ne[0], act_nrows, octx->n_threads, @@ -4651,36 +4568,14 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { mmctx->vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); mmctx->vtcm_act_raw = VTCM_LAYOUT_PTR(uint8_t, base, L.off_act_raw); - mmctx->vtcm_src0_stride = is_repacked ? 0 : src0_row_size_padded; + mmctx->vtcm_src0_stride = 0; mmctx->vtcm_act_stride = act_row_size; - mmctx->vtcm_act_raw_stride = hex_round_up(act->ne[0] * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + mmctx->vtcm_act_raw_stride = htp_mm_act_raw_row_size(act->ne[0]); mmctx->vtcm_src0_size_per_thread = fastdiv(L.src0_bytes, &octx->n_threads_div); mmctx->vtcm_act_size_per_thread = L.act_bytes; mmctx->vtcm_dst_size_per_thread = fastdiv(L.dst_bytes, &octx->n_threads_div); - // Run fused matmul - const uint32_t n_matmul_jobs = octx->n_threads; - worker_callback_t matmul_job_func; - if (is_repacked) { - switch (src0->type) { - case HTP_TYPE_Q4_0: matmul_job_func = hvx_mm_nx_2d_repacked_q4_0; break; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: matmul_job_func = hvx_mm_nx_2d_repacked_q4_1; break; - case HTP_TYPE_Q5_K: matmul_job_func = hvx_mm_nx_2d_repacked_q5_k; break; - case HTP_TYPE_Q3_K: matmul_job_func = hvx_mm_nx_2d_repacked_q3_k; break; - case HTP_TYPE_Q2_K: matmul_job_func = hvx_mm_nx_2d_repacked_q2_k; break; - case HTP_TYPE_Q8_0: matmul_job_func = hvx_mm_nx_2d_repacked_q8_0; break; - case HTP_TYPE_IQ4_NL: matmul_job_func = hvx_mm_nx_2d_repacked_iq4nl; break; - case HTP_TYPE_MXFP4: matmul_job_func = hvx_mm_nx_2d_repacked_mxfp4; break; - default: - htp_trace_event_stop(tr, HTP_TRACE_EVT_INIT, 0); - return HTP_STATUS_NO_SUPPORT; - } - } else { - matmul_job_func = hvx_mm_nx_2d; - } - htp_trace_event_stop(tr, HTP_TRACE_EVT_INIT, 0); hvx_mm_transfer_act_dma(octx, kparams, act, mmctx->vtcm_act_raw, mmctx->vtcm_act_raw_stride, 0, act_nrows); @@ -4689,41 +4584,11 @@ static int op_matmul_nx_impl(struct htp_ops_context * octx) { mmctx->n_quant_tasks = n_quant_tasks; work_queue_run(octx->ctx->work_queue, quant_task_func, mmctx, n_quant_tasks); - work_queue_run(octx->ctx->work_queue, matmul_job_func, mmctx, n_matmul_jobs); + work_queue_run(octx->ctx->work_queue, hvx_mm_nx_2d_tiled, mmctx, octx->n_threads); return HTP_STATUS_OK; } int op_matmul_nx(struct htp_ops_context * octx) { - const struct htp_mm_kernel_params * kparams = (const struct htp_mm_kernel_params *) octx->kernel_params; - - if (kparams->collapse) { - const uint32_t n_weights = kparams->n_weights; - const struct htp_tensor * act = octx->src[n_weights]; - const uint32_t s1 = (act->ne[1] > 1) ? act->nb[1] : ((act->ne[2] > 1) ? act->nb[2] : act->nb[3]); - struct htp_tensor act_collapsed; - struct htp_tensor dsts_collapsed[HTP_OP_MAX_OUTPUTS]; - const struct htp_tensor * orig_dsts[HTP_OP_MAX_OUTPUTS]; - - htp_mm_tensor_collapse_rows(&act_collapsed, act, s1); - octx->src[n_weights] = &act_collapsed; - - for (uint32_t p = 0; p < n_weights; p++) { - orig_dsts[p] = octx->dsts[p]; - const struct htp_tensor * d = octx->dsts[p]; - const uint32_t sd = (d->ne[1] > 1) ? d->nb[1] : ((d->ne[2] > 1) ? d->nb[2] : d->nb[3]); - htp_mm_tensor_collapse_rows(&dsts_collapsed[p], d, sd); - octx->dsts[p] = &dsts_collapsed[p]; - } - - const int status = op_matmul_nx_impl(octx); - - octx->src[n_weights] = act; - for (uint32_t p = 0; p < n_weights; p++) { - octx->dsts[p] = orig_dsts[p]; - } - return status; - } - return op_matmul_nx_impl(octx); } diff --git a/ggml/src/ggml-hexagon/htp/matmul-ops.h b/ggml/src/ggml-hexagon/htp/matmul-ops.h index 522d8779feb6..4971ed958b75 100644 --- a/ggml/src/ggml-hexagon/htp/matmul-ops.h +++ b/ggml/src/ggml-hexagon/htp/matmul-ops.h @@ -4,6 +4,7 @@ #include #include #include "htp-ops.h" +#include "htp-tensor.h" #include "hex-fastdiv.h" #include "hex-common.h" #include "htp-vtcm.h" @@ -19,45 +20,15 @@ extern "C" { #define HTP_MM_HMX_TILE_N_ELMS 1024 #define HTP_MM_HMX_MIN_NROWS 4 -// --- Weight Repacked Tile Sizes --- -#define HTP_MM_WEIGHT_TILE_SIZE_Q4_0 576 -#define HTP_MM_WEIGHT_TILE_SIZE_Q4_1 640 -#define HTP_MM_WEIGHT_TILE_SIZE_Q8_0 1088 -#define HTP_MM_WEIGHT_TILE_SIZE_IQ4_NL 576 -#define HTP_MM_WEIGHT_TILE_SIZE_MXFP4 544 -// Q5_K: the Q4_1 tile (640) followed by a 128-byte plane with the 5th bit of every quant, transposed so that -// plane byte l holds the eight flags of lane l: bit 2i = low nibble of nibble vector i, bit 2i+1 = high nibble -#define HTP_MM_WEIGHT_TILE_SIZE_Q5_K 768 -// Q6_K native 6-bit tile (32 rows x 32 k), vrmpy-ready: byte 4*row+b of a vector holds k = 4*group+b -// vectors 0..3: low nibbles, vector i holds group 2i (low nibble) and group 2i+1 (high nibble) -// vectors 4..5: high 2 bits, vector m holds groups 4m..4m+3 at bit offsets 0,2,4,6 -// vector 6: fp16 scales per row, d * scales[]: k 0..15 in lanes 0..31, k 16..31 in lanes 32..63 -#define HTP_MM_WEIGHT_TILE_SIZE_Q6_K 896 -// Q3_K native 3-bit tile, vrmpy-ready like Q6_K -// vectors 0..1: low 2 bits, vector m holds groups 4m..4m+3 at bit offsets 0,2,4,6 -// vector 2: bit g set where the hmask bit of group g is clear (quant = low 2 bits - 4) -// vector 3: fp16 scales per row, d * (scales[] - 32): k 0..15 in lanes 0..31, k 16..31 in lanes 32..63 -#define HTP_MM_WEIGHT_TILE_SIZE_Q3_K 512 -// Q2_K native 2-bit tile with the ggml scale bytes, vrmpy-ready like Q6_K (same bits per weight as block_q2_K) -// bytes 0..255: unsigned 2-bit quants, vector m holds groups 4m..4m+3 at bit offsets 0,2,4,6 -// bytes 256..319: scales[] bytes (min << 4 | scale), sub-block s of row r at 32 * s + r -// bytes 320..335: 8 fp16, tile j of a super-block: d (j < 4) or -dmin (j >= 4) of rows 8 * (j % 4) .. 8 * (j % 4) + 7 -#define HTP_MM_WEIGHT_TILE_SIZE_Q2_K 336 - -// --- Weight Repacked Aligned Tile Sizes --- -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q4_0 640 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q4_1 640 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q8_0 1152 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_IQ4_NL 640 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_MXFP4 640 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q5_K 768 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q6_K 896 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q3_K 512 -#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q2_K 384 +#define HTP_MM_WEIGHT_TILE_K_Q2_0 64 +#define HTP_MM_WEIGHT_TILE_SIZE_Q2_0 HTP_TENSOR_TILE_SIZE_Q2_0 +#define HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q2_0 640 // --- Activation Tiled Block Sizes (including padding) --- +#define HTP_MM_ACT_BLOCK_K 128 #define HTP_MM_ACT_TILE_SIZE_Q8_0 1152 #define HTP_MM_ACT_TILE_SIZE_Q8_1 1280 +#define HTP_MM_ACT_TILE_SIZE_F16 2048 #define HTP_MM_MAX_PREFETCH 16 @@ -74,11 +45,12 @@ enum htp_mm_kernel_type { // HMX paths HTP_MM_KERNEL_HMX_2D, - HTP_MM_KERNEL_HMX_F16_BATCHED, + HTP_MM_KERNEL_HMX_BATCHED, // HVX floating-point paths HTP_MM_KERNEL_HVX_F16_F16_VTCM, HTP_MM_KERNEL_HVX_F32_F32_VTCM, + HTP_MM_KERNEL_HVX_BF16_F32_VTCM, // HVX quantized paths HTP_MM_KERNEL_HVX_QUANT_ROW, // standard row-wise parallel quantization @@ -89,7 +61,7 @@ enum htp_mm_kernel_type { struct htp_mm_kernel_params { uint8_t kernel_type; // enum htp_mm_kernel_type uint8_t pipeline; // 1 = pipelined execution, 0 = standard - uint8_t collapse; // 1 = collapse outer dims into 2D, 0 = standard + uint8_t unused; // reserved uint8_t n_hmx; // 1 = use HMX, 0 = use HVX uint8_t n_threads; // Number of threads to spawn @@ -103,10 +75,7 @@ struct htp_mm_kernel_params { int32_t aligned_tile_size; // Aligned weight tile size (padded to 128) int32_t act_row_size; // Row size for activation scratchpad int32_t vtcm_size; // Total required scratchpad size in VTCM - int32_t vtcm_src0_size; // src0 scratchpad size in VTCM - int32_t vtcm_act_size; // activation scratchpad size in VTCM int32_t vtcm_bias_size; // bias scratchpad size in VTCM (fused only) - int32_t vtcm_dst_size; // dst scratchpad size in VTCM // Precomputed division values struct fastdiv_values div_ne12_ne1; @@ -212,98 +181,41 @@ static inline int htp_mm_hmx_compute_chunks(size_t vtcm_total, return 0; } -// --- Tile Size Helpers --- -static inline uint32_t htp_mm_get_weight_tile_size(int weight_type) { - switch (weight_type) { - case HTP_TYPE_Q4_0: - case HTP_TYPE_IQ4_NL: - return HTP_MM_WEIGHT_TILE_SIZE_Q4_0; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: - return HTP_MM_WEIGHT_TILE_SIZE_Q4_1; - case HTP_TYPE_Q8_0: - return HTP_MM_WEIGHT_TILE_SIZE_Q8_0; - case HTP_TYPE_Q5_K: - return HTP_MM_WEIGHT_TILE_SIZE_Q5_K; - case HTP_TYPE_Q6_K: - return HTP_MM_WEIGHT_TILE_SIZE_Q6_K; - case HTP_TYPE_Q3_K: - return HTP_MM_WEIGHT_TILE_SIZE_Q3_K; - case HTP_TYPE_Q2_K: - return HTP_MM_WEIGHT_TILE_SIZE_Q2_K; - case HTP_TYPE_MXFP4: - return HTP_MM_WEIGHT_TILE_SIZE_MXFP4; - default: - return 0; - } -} - -static inline uint32_t htp_mm_get_weight_aligned_tile_size(int weight_type) { - switch (weight_type) { - case HTP_TYPE_Q4_0: - case HTP_TYPE_IQ4_NL: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q4_0; - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q4_1; - case HTP_TYPE_Q8_0: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q8_0; - case HTP_TYPE_Q5_K: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q5_K; - case HTP_TYPE_Q6_K: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q6_K; - case HTP_TYPE_Q3_K: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q3_K; - case HTP_TYPE_Q2_K: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_Q2_K; - case HTP_TYPE_MXFP4: - return HTP_MM_WEIGHT_ALIGNED_TILE_SIZE_MXFP4; - default: - return 0; - } -} - // weight types whose tiles carry a per-block offset (x = d * q + m): the activations need block sums (q8_1) // (Q2_K: per-16 k sums, q8_1_s16) static inline bool htp_mm_weight_has_offset(int weight_type) { return weight_type == HTP_TYPE_Q4_1 || weight_type == HTP_TYPE_Q4_K || weight_type == HTP_TYPE_Q5_K || - weight_type == HTP_TYPE_Q2_K; + weight_type == HTP_TYPE_Q2_K || weight_type == HTP_TYPE_Q2_0; } // --- Activation/Row Size Helpers --- static inline size_t htp_mm_q8_0_tiled_row_size(uint32_t ne) { - const uint32_t ne_padded = ((ne + 127) / 128) * 128; + const uint32_t ne_padded = hex_round_up(ne, HTP_MM_ACT_BLOCK_K); const uint32_t nb_32 = ne_padded / 32; return nb_32 * HTP_MM_ACT_TILE_SIZE_Q8_0; } static inline size_t htp_mm_q8_1_tiled_row_size(uint32_t ne) { - const uint32_t ne_padded = ((ne + 127) / 128) * 128; + const uint32_t ne_padded = hex_round_up(ne, HTP_MM_ACT_BLOCK_K); const uint32_t nb_32 = ne_padded / 32; return nb_32 * HTP_MM_ACT_TILE_SIZE_Q8_1; } -static inline size_t htp_mm_get_tiled_row_stride(int weight_type, uint32_t k) { - uint32_t nb = (k + QK_Q4_0_TILED - 1) / QK_Q4_0_TILED; - switch (weight_type) { - case HTP_TYPE_Q4_0: - case HTP_TYPE_IQ4_NL: - case HTP_TYPE_Q4_1: - case HTP_TYPE_Q4_K: - case HTP_TYPE_Q8_0: - case HTP_TYPE_Q5_K: - case HTP_TYPE_Q6_K: - case HTP_TYPE_Q3_K: - case HTP_TYPE_Q2_K: - case HTP_TYPE_MXFP4: - return (size_t) nb * htp_mm_get_weight_tile_size(weight_type); - case HTP_TYPE_F16: - return (size_t) k * sizeof(__fp16); - case HTP_TYPE_F32: - return (size_t) k * sizeof(float); - default: - return 0; +static inline size_t htp_mm_f16_tiled_row_size(uint32_t ne) { + const uint32_t ne_padded = hex_round_up(ne, HTP_MM_ACT_BLOCK_K); + const uint32_t nb_32 = ne_padded / 32; + return nb_32 * HTP_MM_ACT_TILE_SIZE_F16; +} + +static inline size_t htp_mm_tiled_act_row_size(int weight_type, uint32_t ne) { + if (weight_type == HTP_TYPE_F16) { + return htp_mm_f16_tiled_row_size(ne); } + return htp_mm_weight_has_offset(weight_type) ? htp_mm_q8_1_tiled_row_size(ne) : htp_mm_q8_0_tiled_row_size(ne); +} + +static inline size_t htp_mm_act_raw_row_size(uint32_t ne) { + return hex_round_up(ne, HTP_MM_ACT_BLOCK_K) * sizeof(float); } static inline size_t htp_mm_round_up(size_t n, size_t m) { @@ -318,11 +230,11 @@ static inline void htp_mm_hmx_get_2d_chunk_costs( int wtype, uint32_t k, bool pipeline, uint32_t aligned_tile_size, size_t * size_per_n_out, size_t * size_per_m_out, size_t * size_per_mn_out ) { - const bool is_quant = (wtype != HTP_TYPE_F16 && wtype != HTP_TYPE_F32); - const size_t row_stride = htp_mm_get_tiled_row_stride(wtype, k); + const bool is_quant = (wtype != HTP_TYPE_F16 && wtype != HTP_TYPE_F32 && wtype != HTP_TYPE_BF16); + const size_t row_stride = htp_tensor_get_row_size(wtype, k); const size_t vec_dot_size = k * sizeof(uint16_t); - const uint32_t n_k_tiles = k / HTP_MM_HMX_TILE_N_COLS; - const size_t qweight_row_stride = is_quant ? (size_t)(n_k_tiles * aligned_tile_size) / 32 : 0; + const uint32_t n_weight_tiles = k / htp_tensor_get_tile_k(wtype); + const size_t qweight_row_stride = is_quant ? (size_t)(n_weight_tiles * aligned_tile_size) / 32 : 0; *size_per_n_out = (pipeline ? 2 : 1) * (is_quant ? qweight_row_stride : row_stride) + (pipeline ? 2 * vec_dot_size : vec_dot_size); @@ -404,7 +316,7 @@ static inline void htp_mm_hmx_vtcm_layout_build( ) { size_t off = 0; - if (kernel_type == HTP_MM_KERNEL_HMX_F16_BATCHED) { + if (kernel_type == HTP_MM_KERNEL_HMX_BATCHED) { const size_t vec_dot_size = k * sizeof(uint16_t); const size_t act_head_stride = mc * k; const size_t weight_area_size = hex_align_up(nc * vec_dot_size, HTP_MM_HMX_TILE_SIZE); @@ -450,14 +362,14 @@ static inline void htp_mm_hmx_vtcm_layout_build( off = off_group_a + hex_smax(group_b_size, group_c_size); } else { // HTP_MM_KERNEL_HMX_2D - const bool is_quant = (wtype != HTP_TYPE_F16 && wtype != HTP_TYPE_F32); - const size_t row_stride = htp_mm_get_tiled_row_stride(wtype, k); + const bool is_quant = (wtype != HTP_TYPE_F16 && wtype != HTP_TYPE_F32 && wtype != HTP_TYPE_BF16); + const size_t row_stride = htp_tensor_get_row_size(wtype, k); const size_t vec_dot_size = k * sizeof(uint16_t); - const uint32_t n_k_tiles = k / HTP_MM_HMX_TILE_N_COLS; + const uint32_t n_weight_tiles = k / htp_tensor_get_tile_k(wtype); const size_t min_f32_size = hex_align_up(act_threads * HTP_MM_DMA_ACT_MULTIPLIER * k * sizeof(float), 128); const size_t weight_area_size = is_quant - ? hex_align_up((nc / 32) * n_k_tiles * aligned_tile_size, HTP_MM_HMX_TILE_SIZE) + ? hex_align_up((nc / 32) * n_weight_tiles * aligned_tile_size, HTP_MM_HMX_TILE_SIZE) : hex_align_up(nc * row_stride, HTP_MM_HMX_TILE_SIZE); const size_t act_area_size = hex_align_up(mc * vec_dot_size, HTP_MM_HMX_TILE_SIZE); const size_t output_area_size = hex_align_up(mc * nc * sizeof(__fp16), HTP_MM_HMX_TILE_SIZE); @@ -527,30 +439,15 @@ static inline void htp_mm_hvx_vtcm_layout_build( size_t dst_sz = 0; size_t act_raw_sz = 0; - const bool is_repack = (wtype == HTP_TYPE_Q4_0 || wtype == HTP_TYPE_Q4_1 || - wtype == HTP_TYPE_Q8_0 || wtype == HTP_TYPE_IQ4_NL || - wtype == HTP_TYPE_MXFP4 || wtype == HTP_TYPE_Q6_K || - wtype == HTP_TYPE_Q4_K || wtype == HTP_TYPE_Q5_K || - wtype == HTP_TYPE_Q3_K || wtype == HTP_TYPE_Q2_K); - if (is_fused_nx) { - const size_t src0_row_size_padded = hex_round_up(src0_row_size, 128); + uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(wtype); + uint32_t n_k_tiles = (ne10 + htp_tensor_get_tile_k(wtype) - 1) / htp_tensor_get_tile_k(wtype); + uint32_t tile_row_size = n_k_tiles * aligned_tile_size; + size_t weight_sz_per_thread = hex_round_up(n_prefetch * tile_row_size, 128); - size_t weight_sz_per_thread = 0; - - if (is_repack) { - uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(wtype); - uint32_t n_k_tiles = hex_round_up(ne10, 32) / 32; - uint32_t tile_row_size = n_k_tiles * aligned_tile_size; - - weight_sz_per_thread = hex_round_up(n_prefetch * tile_row_size, 128); - } else { - weight_sz_per_thread = hex_round_up(n_prefetch * src0_row_size_padded, 128); - } - - size_t tiled_act_row_size = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); + size_t tiled_act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); size_t q_act_sz = hex_round_up(tiled_act_row_size * act_nrows, 128); - size_t raw_row_size = hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + size_t raw_row_size = htp_mm_act_raw_row_size(ne10); src0_sz = weight_sz_per_thread * n_threads; // shared single-weight prefetch buffer act_sz = q_act_sz; // quantized activation buffer @@ -558,22 +455,15 @@ static inline void htp_mm_hvx_vtcm_layout_build( dst_sz = 0; act_raw_sz = hex_round_up(raw_row_size * act_nrows, 128); } else if (is_matmul_id) { - const size_t src0_row_size_padded = htp_mm_round_up(src0_row_size, 128); - const size_t act_row_size_tiled = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) - : htp_mm_q8_0_tiled_row_size(ne10); - - size_t src0_sz_per_thread = htp_mm_round_up(n_prefetch * src0_row_size_padded, 256); - act_sz = htp_mm_round_up(act_row_size_tiled * act_nrows, 256); - - if (is_repack) { - const uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(wtype); - const uint32_t n_k_tiles = ne10 / 32; - const uint32_t tile_row_size = n_k_tiles * aligned_tile_size; - size_t repacked_vtcm_size = htp_mm_round_up(n_prefetch * tile_row_size, 256); - src0_sz_per_thread = repacked_vtcm_size; - } + const size_t act_row_size_tiled = htp_mm_tiled_act_row_size(wtype, ne10); + const uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(wtype); + const uint32_t n_k_tiles = (ne10 + htp_tensor_get_tile_k(wtype) - 1) / htp_tensor_get_tile_k(wtype); + const uint32_t tile_row_size = n_k_tiles * aligned_tile_size; + size_t src0_sz_per_thread = htp_mm_round_up(n_prefetch * tile_row_size, 256); + + act_sz = htp_mm_round_up(act_row_size_tiled * act_nrows, 256); - size_t raw_row_size = hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + size_t raw_row_size = htp_mm_act_raw_row_size(ne10); src0_sz = src0_sz_per_thread * n_threads; dst_sz = 0; @@ -592,7 +482,8 @@ static inline void htp_mm_hvx_vtcm_layout_build( act_raw_sz = hex_round_up(hex_round_up(ne10 * sizeof(float), 128) * act_nrows, 128); break; } - case HTP_MM_KERNEL_HVX_F32_F32_VTCM: { + case HTP_MM_KERNEL_HVX_F32_F32_VTCM: + case HTP_MM_KERNEL_HVX_BF16_F32_VTCM: { size_t f32_act_row_size = htp_mm_round_up(ne10 * 4, 128); act_sz = htp_mm_round_up(f32_act_row_size * act_nrows, 256); src0_sz = htp_mm_round_up(n_prefetch * src0_row_size_padded, 256) * n_threads; @@ -602,24 +493,18 @@ static inline void htp_mm_hvx_vtcm_layout_build( } case HTP_MM_KERNEL_HVX_QUANT_BLOCK: case HTP_MM_KERNEL_HVX_QUANT_ROW: { - size_t q_act_row_size = htp_mm_weight_has_offset(wtype) ? htp_mm_q8_1_tiled_row_size(ne10) : htp_mm_q8_0_tiled_row_size(ne10); + size_t q_act_row_size = htp_mm_tiled_act_row_size(wtype, ne10); + uint32_t aligned_tile_size = htp_tensor_get_tile_padded_size(wtype); + uint32_t n_weight_tiles = (ne10 + htp_tensor_get_tile_k(wtype) - 1) / htp_tensor_get_tile_k(wtype); + uint32_t tile_row_size = n_weight_tiles * aligned_tile_size; + size_t tiled_vtcm_size = htp_mm_round_up(n_prefetch * tile_row_size, 256); - src0_sz = htp_mm_round_up(n_prefetch * src0_row_size_padded, 256); + src0_sz = tiled_vtcm_size * n_threads; act_sz = htp_mm_round_up(q_act_row_size * act_nrows, 256); - src0_sz = src0_sz * n_threads; - - if (is_repack) { - uint32_t aligned_tile_size = htp_mm_get_weight_aligned_tile_size(wtype); - uint32_t n_k_tiles = ne10 / 32; - uint32_t tile_row_size = n_k_tiles * aligned_tile_size; - size_t repacked_vtcm_size = htp_mm_round_up(n_prefetch * tile_row_size, 256); - src0_sz = repacked_vtcm_size * n_threads; - } - size_t dst_slice_per_thread = (dst_nrows > 0 && act_nrows == 1) ? htp_mm_round_up((dst_row_size + n_threads - 1) / n_threads, 128) : 0; dst_sz = dst_slice_per_thread * n_threads; - size_t raw_row_size = hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + size_t raw_row_size = htp_mm_act_raw_row_size(ne10); act_raw_sz = hex_round_up(raw_row_size * act_nrows, 128); break; } @@ -687,9 +572,7 @@ static inline bool htp_mm_hvx_solve_vtcm_params( const size_t avail_act = vtcm_budget - fixed_bytes; size_t row_size = 0; if (kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW || kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK) { - row_size = htp_mm_weight_has_offset(wtype) - ? htp_mm_q8_1_tiled_row_size(ne10) - : htp_mm_q8_0_tiled_row_size(ne10); + row_size = htp_mm_tiled_act_row_size(wtype, ne10); } else if (kernel_type == HTP_MM_KERNEL_HVX_F16_F16_VTCM) { row_size = hex_round_up(ne10 * 2, 128); } else { @@ -701,7 +584,7 @@ static inline bool htp_mm_hvx_solve_vtcm_params( size_t eff_row_size = row_size; if (kernel_type == HTP_MM_KERNEL_HVX_QUANT_ROW || kernel_type == HTP_MM_KERNEL_HVX_QUANT_BLOCK) { - eff_row_size += hex_round_up(ne10 * sizeof(float), QK_Q8_0_TILED * sizeof(float)); + eff_row_size += htp_mm_act_raw_row_size(ne10); } uint32_t m_chunk = (uint32_t) (avail_act / eff_row_size); @@ -749,7 +632,7 @@ static inline size_t htp_mm_hmx_get_batched_vtcm_size( int wtype, uint32_t k, size_t mc, size_t nc, uint32_t group_size, bool pipeline, uint32_t act_threads, size_t bias_size) { (void)pipeline; struct htp_mm_hmx_vtcm_layout L; - htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_F16_BATCHED, wtype, k, mc, nc, group_size, false, act_threads, 0, bias_size); + htp_mm_hmx_vtcm_layout_build(&L, HTP_MM_KERNEL_HMX_BATCHED, wtype, k, mc, nc, group_size, false, act_threads, 0, bias_size); return L.total_bytes; } diff --git a/ggml/src/ggml-hexagon/htp/pad-ops.c b/ggml/src/ggml-hexagon/htp/pad-ops.c index 85f25a8eb760..cda6df318c21 100644 --- a/ggml/src/ggml-hexagon/htp/pad-ops.c +++ b/ggml/src/ggml-hexagon/htp/pad-ops.c @@ -17,18 +17,28 @@ #include "htp-ctx.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "htp-vtcm.h" +#include "pad-ops.h" /* Circular wrap: maps any integer x into [0, n) */ -static inline uint32_t wrap_around(int32_t x, uint32_t n) { - return (uint32_t)(((x % (int32_t)n) + (int32_t)n) % (int32_t)n); +static inline uint32_t wrap_around(int32_t x, uint32_t n, const struct fastdiv_values * div_n) { + if (x >= 0) { + const uint32_t ux = (uint32_t) x; + return ux < n ? ux : fastmodulo(ux, n, div_n); + } + const uint32_t ux = (uint32_t) (-x); + const uint32_t rem = ux < n ? ux : fastmodulo(ux, n, div_n); + return rem ? (n - rem) : 0; } /* Decompose a flat dst row index into (i1, i2, i3) */ static inline void pad_decompose_row(uint32_t ir, uint32_t ne1, uint32_t ne2, + const struct htp_pad_kernel_params * kparams, uint32_t *i1, uint32_t *i2, uint32_t *i3) { - *i1 = ir % ne1; - *i2 = (ir / ne1) % ne2; - *i3 = ir / (ne1 * ne2); + *i3 = fastdiv(ir, &kparams->div_ne1_ne2); + const uint32_t rem = ir - (*i3) * (ne1 * ne2); + *i2 = fastdiv(rem, &kparams->div_ne1); + *i1 = rem - (*i2) * ne1; } /* Return non-zero if row (i1,i2,i3) falls in the non-padded interior */ @@ -62,25 +72,28 @@ static inline dma_addr_t pad_src_row_data(const struct htp_tensor * src, /* Compute the DDR src row pointer for a circular row (wrap-around indexing) */ static inline const uint8_t * pad_circ_src_row_ptr(const struct htp_tensor * src, + const struct htp_pad_kernel_params * kparams, uint32_t i1, uint32_t i2, uint32_t i3, int32_t lp1, int32_t lp2, int32_t lp3) { return (const uint8_t *) src->data - + wrap_around((int32_t)i1 - lp1, src->ne[1]) * src->nb[1] - + wrap_around((int32_t)i2 - lp2, src->ne[2]) * src->nb[2] - + wrap_around((int32_t)i3 - lp3, src->ne[3]) * src->nb[3]; + + wrap_around((int32_t)i1 - lp1, src->ne[1], &kparams->div_ne01) * src->nb[1] + + wrap_around((int32_t)i2 - lp2, src->ne[2], &kparams->div_ne02) * src->nb[2] + + wrap_around((int32_t)i3 - lp3, src->ne[3], &kparams->div_ne03) * src->nb[3]; } static inline dma_addr_t pad_circ_src_row_data(const struct htp_tensor * src, + const struct htp_pad_kernel_params * kparams, uint32_t i1, uint32_t i2, uint32_t i3, int32_t lp1, int32_t lp2, int32_t lp3) { return src->data - + wrap_around((int32_t)i1 - lp1, src->ne[1]) * src->nb[1] - + wrap_around((int32_t)i2 - lp2, src->ne[2]) * src->nb[2] - + wrap_around((int32_t)i3 - lp3, src->ne[3]) * src->nb[3]; + + wrap_around((int32_t)i1 - lp1, src->ne[1], &kparams->div_ne01) * src->nb[1] + + wrap_around((int32_t)i2 - lp2, src->ne[2], &kparams->div_ne02) * src->nb[2] + + wrap_around((int32_t)i3 - lp3, src->ne[3], &kparams->div_ne03) * src->nb[3]; } struct htp_pad_context { struct htp_ops_context * octx; + const struct htp_pad_kernel_params * kparams; int32_t lp0, rp0; int32_t lp1, rp1; @@ -152,7 +165,7 @@ static void pad_job_per_thread_hvx(unsigned int nth, unsigned int ith, void * da for (uint32_t dst_row = row_start; dst_row < row_end; dst_row++) { uint32_t i1, i2, i3; - pad_decompose_row(dst_row, ne1, ne2, &i1, &i2, &i3); + pad_decompose_row(dst_row, ne1, ne2, pctx->kparams, &i1, &i2, &i3); uint8_t * dst_ptr = (uint8_t *) dst->data + i1 * nb1 + i2 * nb2 + i3 * nb3; @@ -219,7 +232,7 @@ static void pad_job_per_thread_hvx_dma(unsigned int nth, unsigned int ith, void dst_row_size, dst_row_size_aligned, dst_row_size, 0); uint32_t i1, i2, i3; - pad_decompose_row(ir, ne1, ne2, &i1, &i2, &i3); + pad_decompose_row(ir, ne1, ne2, pctx->kparams, &i1, &i2, &i3); const int interior = pad_is_interior(i1, i2, i3, lp1, rp1, ne1, lp2, rp2, ne2, @@ -246,7 +259,7 @@ static void pad_job_per_thread_hvx_dma(unsigned int nth, unsigned int ith, void uint8_t * src_spad_cur = (uint8_t *) dma_queue_pop(dma_q).dst; uint32_t i1, i2, i3; - pad_decompose_row(ir, ne1, ne2, &i1, &i2, &i3); + pad_decompose_row(ir, ne1, ne2, pctx->kparams, &i1, &i2, &i3); const dma_addr_t dst_data = dst->data + i1 * nb1 + i2 * nb2 + i3 * nb3; @@ -278,7 +291,7 @@ static void pad_job_per_thread_hvx_dma(unsigned int nth, unsigned int ith, void const uint32_t next_row = ir + 2; if (next_row < row_end) { uint32_t ni1, ni2, ni3; - pad_decompose_row(next_row, ne1, ne2, &ni1, &ni2, &ni3); + pad_decompose_row(next_row, ne1, ne2, pctx->kparams, &ni1, &ni2, &ni3); const int next_interior = pad_is_interior(ni1, ni2, ni3, lp1, rp1, ne1, lp2, rp2, ne2, @@ -315,10 +328,10 @@ static void pad_job_per_thread_hvx_circular(unsigned int nth, unsigned int ith, for (uint32_t dst_row = row_start; dst_row < row_end; dst_row++) { uint32_t i1, i2, i3; - pad_decompose_row(dst_row, ne1, ne2, &i1, &i2, &i3); + pad_decompose_row(dst_row, ne1, ne2, pctx->kparams, &i1, &i2, &i3); uint8_t * dst_ptr = (uint8_t *) dst->data + i1 * nb1 + i2 * nb2 + i3 * nb3; - const uint8_t * src_row = pad_circ_src_row_ptr(src, i1, i2, i3, lp1, lp2, lp3); + const uint8_t * src_row = pad_circ_src_row_ptr(src, pctx->kparams, i1, i2, i3, lp1, lp2, lp3); if (nb00 == type_size) { @@ -393,8 +406,8 @@ static void pad_job_per_thread_hvx_circular_dma(unsigned int nth, unsigned int i dst_row_size, dst_row_size_aligned, dst_row_size, 0); uint32_t pi1, pi2, pi3; - pad_decompose_row(ir, ne1, ne2, &pi1, &pi2, &pi3); - const dma_addr_t src_data = pad_circ_src_row_data(src, pi1, pi2, pi3, lp1, lp2, lp3); + pad_decompose_row(ir, ne1, ne2, pctx->kparams, &pi1, &pi2, &pi3); + const dma_addr_t src_data = pad_circ_src_row_data(src, pctx->kparams, pi1, pi2, pi3, lp1, lp2, lp3); dma_queue_push(dma_q, dma_make_data(src_spad_cur, src_data), src_row_size_aligned, src_row_size, src_row_size, 1); @@ -411,7 +424,7 @@ static void pad_job_per_thread_hvx_circular_dma(unsigned int nth, unsigned int i uint8_t * src_spad_cur = (uint8_t *) dma_queue_pop(dma_q).dst; uint32_t i1, i2, i3; - pad_decompose_row(ir, ne1, ne2, &i1, &i2, &i3); + pad_decompose_row(ir, ne1, ne2, pctx->kparams, &i1, &i2, &i3); const dma_addr_t dst_data = dst->data + i1 * nb1 + i2 * nb2 + i3 * nb3; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) ir); @@ -455,8 +468,8 @@ static void pad_job_per_thread_hvx_circular_dma(unsigned int nth, unsigned int i const uint32_t next_row = ir + 2; if (next_row < row_end) { uint32_t nri1, nri2, nri3; - pad_decompose_row(next_row, ne1, ne2, &nri1, &nri2, &nri3); - const dma_addr_t next_src_data = pad_circ_src_row_data(src, nri1, nri2, nri3, lp1, lp2, lp3); + pad_decompose_row(next_row, ne1, ne2, pctx->kparams, &nri1, &nri2, &nri3); + const dma_addr_t next_src_data = pad_circ_src_row_data(src, pctx->kparams, nri1, nri2, nri3, lp1, lp2, lp3); dma_queue_push(dma_q, dma_make_data(src_spad_cur, next_src_data), src_row_size_aligned, src_row_size, src_row_size, 1); @@ -475,15 +488,8 @@ static void pad_job_per_thread_hvx_circular_dma(unsigned int nth, unsigned int i int op_pad(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; - - // Only F32 supported - size_t type_size; - switch (src0->type) { - case HTP_TYPE_F32: type_size = 4; break; - default: - FARF(ERROR, "pad-hvx: unsupported type %u\n", src0->type); - return HTP_STATUS_NO_SUPPORT; - } + const struct htp_pad_kernel_params * kparams = + (const struct htp_pad_kernel_params *) octx->kernel_params; const int32_t lp0 = octx->op_params[0]; const int32_t rp0 = octx->op_params[1]; @@ -495,11 +501,10 @@ int op_pad(struct htp_ops_context * octx) { const int32_t rp3 = octx->op_params[7]; const int32_t circular = octx->op_params[8]; - const uint32_t ne0 = dst->ne[0]; - const uint32_t ne00 = src0->ne[0]; - - const uint32_t total_dst_rows = dst->ne[1] * dst->ne[2] * dst->ne[3]; - const size_t dst_row_size = (size_t)ne0 * type_size; + const uint32_t total_dst_rows = kparams->total_rows; + const size_t type_size = kparams->elem_size; + const size_t src_row_size = src0->ne[0] * type_size; + const size_t dst_row_size = dst->ne[0] * type_size; uint32_t row_start = 0; uint32_t nrows = total_dst_rows; @@ -516,60 +521,68 @@ int op_pad(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = octx->n_threads; - - const size_t src_row_size = (size_t)ne00 * type_size; - const size_t src_row_size_aligned = hex_round_up(src_row_size, VLEN); - const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN); - - // Total VTCM needed: 2 buffers (ping+pong) for src and dst, per thread - const size_t vtcm_needed = (size_t)n_threads * 2 * (src_row_size_aligned + dst_row_size_aligned); + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, nrows))) { + return HTP_STATUS_INVAL_PARAMS; + } - const int use_dma = (src0->nb[0] == (uint32_t)type_size) && (ne00 >= 512) && - (octx->ctx->vtcm_size >= vtcm_needed); + const uint32_t n_threads = octx->n_threads; - if (!use_dma && (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst))) { + if (!kparams->use_dma && (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst))) { return HTP_STATUS_NO_SUPPORT; } - if (use_dma) { - octx->src0_spad.size_per_thread = 2 * src_row_size_aligned; - octx->dst_spad.size_per_thread = 2 * dst_row_size_aligned; - octx->src0_spad.size = n_threads * octx->src0_spad.size_per_thread; - octx->dst_spad.size = n_threads * octx->dst_spad.size_per_thread; - octx->src0_spad.data = octx->ctx->vtcm_base; - octx->dst_spad.data = octx->src0_spad.data + octx->src0_spad.size; + struct htp_pad_vtcm_layout layout = { 0 }; + if (kparams->use_dma) { + htp_pad_vtcm_layout_build(&layout, src_row_size, dst_row_size, n_threads); + + octx->src0_spad.size_per_thread = layout.src0_bytes_per_thread; + octx->dst_spad.size_per_thread = layout.dst_bytes_per_thread; + octx->src0_spad.size = n_threads * layout.src0_bytes_per_thread; + octx->dst_spad.size = n_threads * layout.dst_bytes_per_thread; + octx->src0_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_src0); + octx->dst_spad.data = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_dst); octx->src0_spad.src = NULL; octx->dst_spad.src = NULL; } struct htp_pad_context pctx = { - .octx = octx, + .octx = octx, + .kparams = kparams, .lp0 = lp0, .rp0 = rp0, .lp1 = lp1, .rp1 = rp1, .lp2 = lp2, .rp2 = rp2, .lp3 = lp3, .rp3 = rp3, - .nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), - .total_dst_rows = nrows, - .row_start = row_start, - .type_size = type_size, + .nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), + .total_dst_rows = nrows, + .row_start = row_start, + .type_size = type_size, .src_row_size = src_row_size, - .src_row_size_aligned = src_row_size_aligned, + .src_row_size_aligned = layout.src_row_size_aligned, .dst_row_size = dst_row_size, - .dst_row_size_aligned = dst_row_size_aligned, + .dst_row_size_aligned = layout.dst_row_size_aligned, }; FARF(HIGH, "pad-hvx%s%s: (%ux%ux%ux%u) -> (%ux%ux%ux%u) pads=(%d,%d,%d,%d,%d,%d,%d,%d)\n", - circular ? "-circ" : "", - use_dma ? "-dma" : "", + circular ? "-circ" : "", + kparams->use_dma ? "-dma" : "", src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3); - if (circular && use_dma) { work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_circular_dma, &pctx, n_threads); } - else if (circular) { work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_circular, &pctx, n_threads); } - else if (use_dma) { work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_dma, &pctx, n_threads); } - else { work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx, &pctx, n_threads); } + switch (kparams->kernel_type) { + case HTP_PAD_KERNEL_HVX_CIRCULAR_DMA: + work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_circular_dma, &pctx, n_threads); + break; + case HTP_PAD_KERNEL_HVX_CIRCULAR: + work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_circular, &pctx, n_threads); + break; + case HTP_PAD_KERNEL_HVX_DMA: + work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx_dma, &pctx, n_threads); + break; + default: + work_queue_run(octx->ctx->work_queue, pad_job_per_thread_hvx, &pctx, n_threads); + break; + } return HTP_STATUS_OK; } diff --git a/ggml/src/ggml-hexagon/htp/pad-ops.h b/ggml/src/ggml-hexagon/htp/pad-ops.h new file mode 100644 index 000000000000..5b8557538c60 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/pad-ops.h @@ -0,0 +1,65 @@ +#ifndef HTP_PAD_OPS_H +#define HTP_PAD_OPS_H + +#include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-vtcm.h" +#include + +enum htp_pad_kernel_type { + HTP_PAD_KERNEL_HVX = 0, + HTP_PAD_KERNEL_HVX_DMA = 1, + HTP_PAD_KERNEL_HVX_CIRCULAR = 2, + HTP_PAD_KERNEL_HVX_CIRCULAR_DMA = 3, +}; + +struct htp_pad_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_dst; + size_t src_row_size_aligned; + size_t dst_row_size_aligned; + size_t src0_bytes_per_thread; + size_t dst_bytes_per_thread; +}; + +static inline void htp_pad_vtcm_layout_build( + struct htp_pad_vtcm_layout * L, + size_t src_row_size, + size_t dst_row_size, + uint32_t n_threads +) { + L->src_row_size_aligned = hex_round_up(src_row_size, 128); + L->dst_row_size_aligned = hex_round_up(dst_row_size, 128); + L->src0_bytes_per_thread = 2 * L->src_row_size_aligned; + L->dst_bytes_per_thread = 2 * L->dst_row_size_aligned; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + + L->total_bytes = off; +} + +struct htp_pad_kernel_params { + uint8_t kernel_type; + uint32_t n_threads; + uint32_t total_rows; + uint32_t use_dma; + uint32_t elem_size; + uint32_t vtcm_size; + + struct fastdiv_values div_ne1; + struct fastdiv_values div_ne1_ne2; + struct fastdiv_values div_ne01; + struct fastdiv_values div_ne02; + struct fastdiv_values div_ne03; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_pad_kernel_params) <= 128, "htp_pad_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_pad_kernel_params) <= 128, "htp_pad_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_PAD_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/pool-ops.c b/ggml/src/ggml-hexagon/htp/pool-ops.c index ea1f1a597945..b41c7bed23c7 100644 --- a/ggml/src/ggml-hexagon/htp/pool-ops.c +++ b/ggml/src/ggml-hexagon/htp/pool-ops.c @@ -247,6 +247,7 @@ typedef void (*pool_plane_fn_t)(const float * src, float * dst, const struct htp struct pool_2d_context { struct htp_ops_context * octx; const struct htp_pool_2d_kernel_params * kparams; + struct htp_pool_vtcm_layout layout; pool_plane_fn_t pool_plane; uint32_t n_threads; uint32_t plane_start; @@ -257,6 +258,7 @@ struct pool_2d_context { static void pool_2d_thread(unsigned int nth, unsigned int ith, void * data) { struct pool_2d_context * ctx = (struct pool_2d_context *) data; const struct htp_pool_2d_kernel_params * p = ctx->kparams; + const struct htp_pool_vtcm_layout * L = &ctx->layout; const struct htp_tensor * src0 = ctx->octx->src[0]; const struct htp_tensor * dst = ctx->octx->dst; pool_plane_fn_t pool_plane = ctx->pool_plane; @@ -271,15 +273,14 @@ static void pool_2d_thread(unsigned int nth, unsigned int ith, void * data) { struct htp_thread_trace * tr = &ctx->octx->ctx->trace[ith]; dma_queue * dma_queue = ctx->octx->ctx->dma[ith]; - const uint32_t src_spad_half = p->src_plane_bytes_aligned; - const uint32_t dst_spad_half = p->dst_plane_bytes_aligned; - const uint32_t src_bytes_per_thread = 2 * src_spad_half; - const uint32_t dst_bytes_per_thread = 2 * dst_spad_half; - const size_t off_dst = (size_t) ctx->n_threads * src_bytes_per_thread; + const uint32_t src_plane_bytes = L->src_plane_bytes; + const uint32_t dst_plane_bytes = L->dst_plane_bytes; + const uint32_t src_spad_half = (uint32_t) L->src_spad_half_size; + const uint32_t dst_spad_half = (uint32_t) L->dst_spad_half_size; uint8_t * vtcm_base = (uint8_t *) ctx->octx->ctx->vtcm_base; - uint8_t * src_spad = vtcm_base + ith * src_bytes_per_thread; - uint8_t * dst_spad = vtcm_base + off_dst + ith * dst_bytes_per_thread; + uint8_t * src_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_src) + ith * L->src_bytes_per_thread; + uint8_t * dst_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_dst) + ith * L->dst_bytes_per_thread; float * srcb2[2] = { (float *) src_spad, (float *) (src_spad + src_spad_half) }; float * dstb2[2] = { (float *) dst_spad, (float *) (dst_spad + dst_spad_half) }; @@ -290,14 +291,14 @@ static void pool_2d_thread(unsigned int nth, unsigned int ith, void * data) { for (uint32_t i = 0; i < total && i < 2; ++i) { dma_queue_push(dma_queue, dma_make_data(dst->data, dstb2[i]), - p->dst_plane_bytes, dst_spad_half, - p->dst_plane_bytes, 0); + dst_plane_bytes, dst_spad_half, + dst_plane_bytes, 0); - const dma_addr_t src_addr = src0->data + (first + i) * p->src_plane_bytes; + const dma_addr_t src_addr = src0->data + (first + i) * src_plane_bytes; dma_queue_push(dma_queue, dma_make_data(srcb2[i], src_addr), - src_spad_half, p->src_plane_bytes, - p->src_plane_bytes, 1); + src_spad_half, src_plane_bytes, + src_plane_bytes, 1); } for (uint32_t i = 0; i < total; ++i) { @@ -313,18 +314,18 @@ static void pool_2d_thread(unsigned int nth, unsigned int ith, void * data) { pool_plane(srcb, dstb, p); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) plane); - const dma_addr_t dst_addr = dst->data + plane * p->dst_plane_bytes; + const dma_addr_t dst_addr = dst->data + plane * dst_plane_bytes; dma_queue_push(dma_queue, dma_make_data(dst_addr, dstb), - p->dst_plane_bytes, dst_spad_half, - p->dst_plane_bytes, 1); + dst_plane_bytes, dst_spad_half, + dst_plane_bytes, 1); if (i + 2 < total) { - const dma_addr_t next_src_addr = src0->data + (plane + 2) * p->src_plane_bytes; + const dma_addr_t next_src_addr = src0->data + (plane + 2) * src_plane_bytes; dma_queue_push(dma_queue, dma_make_data(srcb, next_src_addr), - src_spad_half, p->src_plane_bytes, - p->src_plane_bytes, 1); + src_spad_half, src_plane_bytes, + src_plane_bytes, 1); } } @@ -337,22 +338,15 @@ static void pool_2d_thread(unsigned int nth, unsigned int ith, void * data) { } int op_pool_2d(struct htp_ops_context * octx) { - const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; const struct htp_pool_2d_kernel_params * p = (const struct htp_pool_2d_kernel_params *) octx->kernel_params; - if (src0->type != HTP_TYPE_F32 || dst->type != HTP_TYPE_F32 || - (p->pool_op != HTP_POOL_AVG && p->pool_op != HTP_POOL_MAX)) { - return HTP_STATUS_NO_SUPPORT; - } - uint32_t plane_start = 0; uint32_t plane_count = p->planes; if (octx->ctx->mdev.count > 1) { - const uint32_t planes_per_chunk = (p->dst_plane_bytes > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(p->dst_plane_bytes, HEX_L2_LINE_SIZE)) : 1; const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( - plane_count, htp_tensor_mdev_data_aligned(dst) ? planes_per_chunk : 0, + plane_count, htp_tensor_mdev_data_aligned(dst) ? p->planes_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); plane_start = range.start; plane_count = range.count; @@ -369,16 +363,12 @@ int op_pool_2d(struct htp_ops_context * octx) { const uint32_t planes_per_thread = fastdiv(plane_count + n_threads - 1, &octx->n_threads_div); pool_plane_fn_t pool_plane; - if (p->global_path) { - pool_plane = pool_plane_global; - } else if (p->block_path) { - pool_plane = pool_plane_block; - } else if (p->narrow_path) { - pool_plane = pool_plane_hvx_narrow; - } else if (p->fast_path) { - pool_plane = pool_plane_hvx; - } else { - pool_plane = pool_plane_general; + switch (p->kernel_type) { + case HTP_POOL_KERNEL_GLOBAL: pool_plane = pool_plane_global; break; + case HTP_POOL_KERNEL_BLOCK: pool_plane = pool_plane_block; break; + case HTP_POOL_KERNEL_HVX_NARROW: pool_plane = pool_plane_hvx_narrow; break; + case HTP_POOL_KERNEL_HVX: pool_plane = pool_plane_hvx; break; + default: pool_plane = pool_plane_general; break; } struct pool_2d_context ctx = { @@ -390,6 +380,7 @@ int op_pool_2d(struct htp_ops_context * octx) { .plane_count = plane_count, .planes_per_thread = planes_per_thread, }; + htp_pool_vtcm_layout_build(&ctx.layout, p->src_x, p->src_y, p->dst_x, p->dst_y, n_threads); work_queue_run(octx->ctx->work_queue, pool_2d_thread, &ctx, n_threads); return HTP_STATUS_OK; } diff --git a/ggml/src/ggml-hexagon/htp/pool-ops.h b/ggml/src/ggml-hexagon/htp/pool-ops.h index 66b405a8b378..178e5d00fc41 100644 --- a/ggml/src/ggml-hexagon/htp/pool-ops.h +++ b/ggml/src/ggml-hexagon/htp/pool-ops.h @@ -7,8 +7,18 @@ #include #include "hex-common.h" +#include "htp-vtcm.h" + +enum htp_pool_kernel_type { + HTP_POOL_KERNEL_GENERAL = 0, + HTP_POOL_KERNEL_HVX, + HTP_POOL_KERNEL_HVX_NARROW, + HTP_POOL_KERNEL_GLOBAL, + HTP_POOL_KERNEL_BLOCK, +}; struct htp_pool_2d_kernel_params { + uint8_t kernel_type; uint32_t src_x; uint32_t src_y; uint32_t dst_x; @@ -19,17 +29,10 @@ struct htp_pool_2d_kernel_params { uint32_t stride_y; int32_t pad_x; int32_t pad_y; - uint32_t src_plane_bytes; - uint32_t dst_plane_bytes; - uint32_t src_plane_bytes_aligned; - uint32_t dst_plane_bytes_aligned; uint32_t n_threads; uint32_t planes; + uint32_t planes_per_chunk; uint32_t pool_op; - uint32_t fast_path; - uint32_t narrow_path; - uint32_t global_path; - uint32_t block_path; uint32_t avg_divide_count; uint32_t ox_lo; uint32_t ox_hi; @@ -46,12 +49,36 @@ struct htp_pool_vtcm_layout { size_t total_bytes; size_t off_src; size_t off_dst; + uint32_t src_plane_bytes; + uint32_t dst_plane_bytes; size_t src_bytes_per_thread; size_t dst_bytes_per_thread; size_t src_spad_half_size; size_t dst_spad_half_size; }; +static inline void htp_pool_vtcm_layout_build( + struct htp_pool_vtcm_layout * L, + uint32_t src_x, + uint32_t src_y, + uint32_t dst_x, + uint32_t dst_y, + uint32_t n_threads +) { + // Full-plane double buffering (256 bytes guard space for vector loads) + L->src_plane_bytes = src_x * src_y * sizeof(float); + L->dst_plane_bytes = dst_x * dst_y * sizeof(float); + L->src_spad_half_size = hex_round_up(L->src_plane_bytes + 256, 128); + L->dst_spad_half_size = hex_round_up(L->dst_plane_bytes, 128); + L->src_bytes_per_thread = 2 * L->src_spad_half_size; + L->dst_bytes_per_thread = 2 * L->dst_spad_half_size; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src, L->src_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + L->total_bytes = off; +} + static inline bool htp_pool_solve_layout( struct htp_pool_vtcm_layout * layout, uint32_t src_x, @@ -61,25 +88,8 @@ static inline bool htp_pool_solve_layout( uint32_t n_threads, size_t vtcm_budget ) { - // Full-plane double buffering (256 bytes guard space for vector loads) - const size_t src_plane_bytes = (size_t) src_x * src_y * sizeof(float); - const size_t dst_plane_bytes = (size_t) dst_x * dst_y * sizeof(float); - const size_t src_plane_aligned = hex_round_up((uint32_t) src_plane_bytes + 256, 128); - const size_t dst_plane_aligned = hex_round_up((uint32_t) dst_plane_bytes, 128); - - const size_t spad_per_thread = 2 * (src_plane_aligned + dst_plane_aligned); - if (spad_per_thread * n_threads > vtcm_budget) { - return false; - } - - layout->src_spad_half_size = src_plane_aligned; - layout->dst_spad_half_size = dst_plane_aligned; - layout->src_bytes_per_thread = 2 * src_plane_aligned; - layout->dst_bytes_per_thread = 2 * dst_plane_aligned; - layout->off_src = 0; - layout->off_dst = layout->src_bytes_per_thread * n_threads; - layout->total_bytes = layout->off_dst + layout->dst_bytes_per_thread * n_threads; - return true; + htp_pool_vtcm_layout_build(layout, src_x, src_y, dst_x, dst_y, n_threads); + return layout->total_bytes <= vtcm_budget; } #endif // HTP_POOL_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/repeat-ops.c b/ggml/src/ggml-hexagon/htp/repeat-ops.c index 2551be225b84..827ef24c575b 100644 --- a/ggml/src/ggml-hexagon/htp/repeat-ops.c +++ b/ggml/src/ggml-hexagon/htp/repeat-ops.c @@ -16,14 +16,11 @@ #include "hex-profile.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "repeat-ops.h" struct htp_repeat_context { - struct htp_ops_context * octx; - - uint32_t nr0; - uint32_t nr1; - uint32_t nr2; - uint32_t nr3; + struct htp_ops_context * octx; + const struct htp_repeat_kernel_params * kparams; uint32_t nrows_per_thread; uint32_t total_dst_rows; // ne1 * ne2 * ne3 @@ -35,6 +32,7 @@ struct htp_repeat_context { static void repeat_job_per_thread(unsigned int nth, unsigned int ith, void * data) { const struct htp_repeat_context * rctx = (const struct htp_repeat_context *) data; struct htp_ops_context * octx = rctx->octx; + const struct htp_repeat_kernel_params * kparams = rctx->kparams; const struct htp_tensor * src = octx->src[0]; const struct htp_tensor * dst = octx->dst; @@ -58,29 +56,30 @@ static void repeat_job_per_thread(unsigned int nth, unsigned int ith, void * dat const uint32_t nb2 = dst->nb[2]; const uint32_t nb3 = dst->nb[3]; - const uint32_t nr0 = rctx->nr0; - const uint32_t nr1 = rctx->nr1; - const uint32_t nr2 = rctx->nr2; - const uint32_t nr3 = rctx->nr3; + const uint32_t nr0 = kparams->nr0; const size_t row_bytes = ne00 * rctx->type_size; const uint32_t row_start = rctx->row_start + rctx->nrows_per_thread * ith; const uint32_t row_end = MIN(row_start + rctx->nrows_per_thread, rctx->row_start + rctx->total_dst_rows); + if (row_start >= row_end) { + return; + } struct htp_thread_trace * tr = &octx->ctx->trace[ith]; htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, row_start); for (uint32_t dst_row = row_start; dst_row < row_end; dst_row++) { // Decompose flat dst row index into (i1, i2, i3) - const uint32_t i1 = dst_row % ne1; - const uint32_t i2 = (dst_row / ne1) % ne2; - const uint32_t i3 = dst_row / (ne1 * ne2); + const uint32_t dst_row_div_ne1 = fastdiv(dst_row, &kparams->div_ne1); + const uint32_t i1 = dst_row - dst_row_div_ne1 * ne1; + const uint32_t i3 = fastdiv(dst_row, &kparams->div_ne12); + const uint32_t i2 = dst_row_div_ne1 - i3 * ne2; // Map to source indices (tiling) - const uint32_t k1 = i1 % ne01; - const uint32_t k2 = i2 % ne02; - const uint32_t k3 = i3 % ne03; + const uint32_t k1 = fastmodulo(i1, ne01, &kparams->div_ne01); + const uint32_t k2 = fastmodulo(i2, ne02, &kparams->div_ne02); + const uint32_t k3 = fastmodulo(i3, ne03, &kparams->div_ne03); const uint8_t * src_row = (const uint8_t *) src->data + k1 * nb01 + k2 * nb02 + k3 * nb03; uint8_t * dst_base = (uint8_t *) dst->data + i1 * nb1 + i2 * nb2 + i3 * nb3; @@ -104,15 +103,6 @@ int op_repeat(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; const struct htp_tensor * dst = octx->dst; - // Validate that dst dims are multiples of src dims - if (dst->ne[0] % src0->ne[0] != 0 || - dst->ne[1] % src0->ne[1] != 0 || - dst->ne[2] % src0->ne[2] != 0 || - dst->ne[3] % src0->ne[3] != 0) { - FARF(ERROR, "repeat: dst dims must be multiples of src dims\n"); - return HTP_STATUS_INVAL_PARAMS; - } - size_t type_size; switch (src0->type) { case HTP_TYPE_F32: type_size = 4; break; @@ -126,6 +116,13 @@ int op_repeat(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } + const struct htp_repeat_kernel_params * kparams = + (const struct htp_repeat_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t total_dst_rows = dst->ne[1] * dst->ne[2] * dst->ne[3]; const size_t dst_row_size = dst->ne[0] * type_size; @@ -148,10 +145,7 @@ int op_repeat(struct htp_ops_context * octx) { struct htp_repeat_context rctx = { .octx = octx, - .nr0 = dst->ne[0] / src0->ne[0], - .nr1 = dst->ne[1] / src0->ne[1], - .nr2 = dst->ne[2] / src0->ne[2], - .nr3 = dst->ne[3] / src0->ne[3], + .kparams = kparams, .nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), .total_dst_rows = nrows, .row_start = row_start, @@ -161,7 +155,7 @@ int op_repeat(struct htp_ops_context * octx) { FARF(HIGH, "repeat: (%ux%ux%ux%u) -> (%ux%ux%ux%u) nr=(%u,%u,%u,%u)\n", src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], - rctx.nr0, rctx.nr1, rctx.nr2, rctx.nr3); + kparams->nr0, kparams->nr1, kparams->nr2, kparams->nr3); work_queue_run(octx->ctx->work_queue, repeat_job_per_thread, &rctx, n_threads); diff --git a/ggml/src/ggml-hexagon/htp/repeat-ops.h b/ggml/src/ggml-hexagon/htp/repeat-ops.h new file mode 100644 index 000000000000..47759e037d08 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/repeat-ops.h @@ -0,0 +1,27 @@ +#ifndef HTP_REPEAT_OPS_H +#define HTP_REPEAT_OPS_H + +#include "hex-fastdiv.h" +#include + +struct htp_repeat_kernel_params { + uint32_t n_threads; + uint32_t nr0; + uint32_t nr1; + uint32_t nr2; + uint32_t nr3; + + struct fastdiv_values div_ne1; + struct fastdiv_values div_ne12; + struct fastdiv_values div_ne01; + struct fastdiv_values div_ne02; + struct fastdiv_values div_ne03; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_repeat_kernel_params) <= 128, "htp_repeat_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_repeat_kernel_params) <= 128, "htp_repeat_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_REPEAT_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/roll-ops.c b/ggml/src/ggml-hexagon/htp/roll-ops.c index 9c373f56d3c9..77ded0fe9022 100644 --- a/ggml/src/ggml-hexagon/htp/roll-ops.c +++ b/ggml/src/ggml-hexagon/htp/roll-ops.c @@ -17,16 +17,15 @@ #include "hex-profile.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "roll-ops.h" struct htp_roll_context { struct htp_ops_context * octx; + const struct htp_roll_kernel_params * kparams; uint32_t row_start; uint32_t nrows; uint32_t nrows_per_thread; - - struct fastdiv_values div_ne1; - struct fastdiv_values div_ne2_ne1; }; static inline uint32_t htp_roll_wrap(int32_t i, uint32_t ne) { @@ -39,30 +38,32 @@ static inline uint32_t htp_roll_wrap(int32_t i, uint32_t ne) { return (uint32_t) i; } -#define htp_roll_preamble \ - const struct htp_tensor * src0 = octx->src[0]; \ - const struct htp_tensor * dst = octx->dst; \ - \ - const uint32_t ne0 = dst->ne[0]; \ - const uint32_t ne1 = dst->ne[1]; \ - const uint32_t ne2 = dst->ne[2]; \ - const uint32_t ne3 = dst->ne[3]; \ - \ - const uint32_t nb01 = src0->nb[1]; \ - const uint32_t nb02 = src0->nb[2]; \ - const uint32_t nb03 = src0->nb[3]; \ - \ - const uint32_t nb1 = dst->nb[1]; \ - const uint32_t nb2 = dst->nb[2]; \ - const uint32_t nb3 = dst->nb[3]; \ - \ - const int32_t s0 = octx->op_params[0]; \ - const int32_t s1 = octx->op_params[1]; \ - const int32_t s2 = octx->op_params[2]; \ - const int32_t s3 = octx->op_params[3]; \ - \ - const uint32_t i0_src0 = htp_roll_wrap(-s0, ne0); \ - const uint32_t n0 = ne0 - i0_src0; +#define htp_roll_preamble \ + const struct htp_tensor * src0 = octx->src[0]; \ + const struct htp_tensor * dst = octx->dst; \ + const struct htp_roll_kernel_params * kparams = \ + (const struct htp_roll_kernel_params *) octx->kernel_params; \ + \ + const uint32_t ne0 = dst->ne[0]; \ + const uint32_t ne1 = dst->ne[1]; \ + const uint32_t ne2 = dst->ne[2]; \ + const uint32_t ne3 = dst->ne[3]; \ + \ + const uint32_t nb01 = src0->nb[1]; \ + const uint32_t nb02 = src0->nb[2]; \ + const uint32_t nb03 = src0->nb[3]; \ + \ + const uint32_t nb1 = dst->nb[1]; \ + const uint32_t nb2 = dst->nb[2]; \ + const uint32_t nb3 = dst->nb[3]; \ + \ + const int32_t s0 = octx->op_params[0]; \ + const int32_t s1 = octx->op_params[1]; \ + const int32_t s2 = octx->op_params[2]; \ + const int32_t s3 = octx->op_params[3]; \ + \ + const uint32_t i0_src0 = kparams->i0_src0; \ + const uint32_t n0 = kparams->n0; #define htp_roll_dma_preamble dma_queue * q = octx->ctx->dma[0]; @@ -91,10 +92,10 @@ static inline void roll_dma_push_rows(dma_queue * q, uint32_t src_row, uint32_t nrows, uint32_t row_size, - uint32_t i0_src0) { + uint32_t i0_src0, + uint32_t n0) { const dma_addr_t dst_base = dst->data + (size_t) dst_row * row_size; const dma_addr_t src_base = src0->data + (size_t) src_row * row_size; - const uint32_t n0 = src0->ne[0] - i0_src0; roll_dma_push(q, dst_base, src_base + (size_t) i0_src0 * sizeof(float), row_size, row_size, n0 * sizeof(float), nrows); @@ -125,7 +126,7 @@ static int roll_dma_f32_contiguous(struct htp_ops_context * octx) { const uint32_t row_size = ne0 * sizeof(float); if (s1 == 0 && s2 == 0 && s3 == 0) { - roll_dma_push_rows(q, dst, src0, 0, 0, ne1 * ne2 * ne3, row_size, i0_src0); + roll_dma_push_rows(q, dst, src0, 0, 0, ne1 * ne2 * ne3, row_size, i0_src0, n0); dma_queue_flush(q); return HTP_STATUS_OK; } @@ -139,9 +140,9 @@ static int roll_dma_f32_contiguous(struct htp_ops_context * octx) { const uint32_t n2_first = ne2 - i2_src0; roll_dma_push_rows(q, dst, src0, dst_row0, src_row0, n2_first * ne1, - row_size, i0_src0); + row_size, i0_src0, n0); roll_dma_push_rows(q, dst, src0, dst_row0 + n2_first * ne1, i03 * ne2 * ne1, - i2_src0 * ne1, row_size, i0_src0); + i2_src0 * ne1, row_size, i0_src0, n0); } dma_queue_flush(q); @@ -159,9 +160,9 @@ static int roll_dma_f32_contiguous(struct htp_ops_context * octx) { const uint32_t src_row0 = (i03 * ne2 + i02) * ne1; roll_dma_push_rows(q, dst, src0, dst_row0, src_row0 + i1_src0, - n1_first, row_size, i0_src0); + n1_first, row_size, i0_src0, n0); roll_dma_push_rows(q, dst, src0, dst_row0 + n1_first, src_row0, - i1_src0, row_size, i0_src0); + i1_src0, row_size, i0_src0, n0); } } @@ -214,9 +215,9 @@ static void roll_thread_f32(unsigned int nth, unsigned int ith, void * data) { htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, row_start); for (uint32_t row = row_start; row < row_end; row++) { - const uint32_t i3 = fastdiv(row, &rctx->div_ne2_ne1); + const uint32_t i3 = fastdiv(row, &kparams->div_ne2_ne1); const uint32_t rem = row - i3 * ne2 * ne1; - const uint32_t i2 = fastdiv(rem, &rctx->div_ne1); + const uint32_t i2 = fastdiv(rem, &kparams->div_ne1); const uint32_t i1 = rem - i2 * ne1; const uint32_t i01 = htp_roll_wrap((int32_t) i1 - s1, ne1); @@ -245,23 +246,14 @@ static void roll_thread_f32(unsigned int nth, unsigned int ith, void * data) { int execute_op_roll_f32(struct htp_ops_context * octx) { htp_roll_preamble; - if (src0->type != HTP_TYPE_F32 || dst->type != HTP_TYPE_F32) { - FARF(ERROR, "roll: unsupported type %u -> %u\n", src0->type, dst->type); - return HTP_STATUS_NO_SUPPORT; - } - - if (src0->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float)) { - FARF(ERROR, "roll: unsupported nb0 %u -> %u\n", src0->nb[0], dst->nb[0]); - return HTP_STATUS_NO_SUPPORT; + if (kparams->kernel_type == HTP_ROLL_KERNEL_DMA_CONTIGUOUS) { + return roll_dma_f32_contiguous(octx); } - - if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || - src0->ne[2] != ne2 || src0->ne[3] != ne3) { - FARF(ERROR, "roll: shape mismatch\n"); - return HTP_STATUS_INVAL_PARAMS; + if (kparams->kernel_type == HTP_ROLL_KERNEL_DMA_STRIDED) { + return roll_dma_f32_strided(octx); } - const uint32_t total_rows = ne1 * ne2 * ne3; + const uint32_t total_rows = kparams->total_rows; const size_t dst_row_size = ne0 * sizeof(float); uint32_t row_start = 0; @@ -279,25 +271,21 @@ int execute_op_roll_f32(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - if (octx->ctx->mdev.count <= 1) { - if (htp_tensor_is_contiguous(src0, sizeof(float)) && htp_tensor_is_contiguous(dst, sizeof(float))) { - return roll_dma_f32_contiguous(octx); - } - return roll_dma_f32_strided(octx); - } - if (htp_tensor_is_extended(src0) || htp_tensor_is_extended(dst)) { return HTP_STATUS_NO_SUPPORT; } + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, nrows))) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t n_threads = octx->n_threads; struct htp_roll_context rctx = { .octx = octx, + .kparams = kparams, .row_start = row_start, .nrows = nrows, .nrows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div), - .div_ne1 = init_fastdiv_values(dst->ne[1]), - .div_ne2_ne1 = init_fastdiv_values(dst->ne[2] * dst->ne[1]), }; work_queue_run(octx->ctx->work_queue, roll_thread_f32, &rctx, n_threads); diff --git a/ggml/src/ggml-hexagon/htp/roll-ops.h b/ggml/src/ggml-hexagon/htp/roll-ops.h new file mode 100644 index 000000000000..2646aaa4c99c --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/roll-ops.h @@ -0,0 +1,30 @@ +#ifndef HTP_ROLL_OPS_H +#define HTP_ROLL_OPS_H + +#include "hex-fastdiv.h" +#include + +enum htp_roll_kernel_type { + HTP_ROLL_KERNEL_DMA_CONTIGUOUS = 1, + HTP_ROLL_KERNEL_DMA_STRIDED = 2, + HTP_ROLL_KERNEL_HVX = 3, +}; + +struct htp_roll_kernel_params { + uint8_t kernel_type; + uint32_t n_threads; + uint32_t total_rows; + uint32_t i0_src0; + uint32_t n0; + + struct fastdiv_values div_ne1; + struct fastdiv_values div_ne2_ne1; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_roll_kernel_params) <= 128, "htp_roll_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_roll_kernel_params) <= 128, "htp_roll_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_ROLL_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/rope-ops.c b/ggml/src/ggml-hexagon/htp/rope-ops.c index f6b4d383ce4c..8c55ac3af49e 100644 --- a/ggml/src/ggml-hexagon/htp/rope-ops.c +++ b/ggml/src/ggml-hexagon/htp/rope-ops.c @@ -700,15 +700,6 @@ static int execute_op_rope_f32(struct htp_ops_context * octx) { const struct htp_tensor * src2 = octx->src[2]; const struct htp_tensor * dst = octx->dst; - switch (octx->op) { - case HTP_OP_ROPE: - break; - - default: - FARF(ERROR, "Unsupported Op %u\n", octx->op); - return HTP_STATUS_NO_SUPPORT; - } - const struct htp_rope_kernel_params * kparams = (const struct htp_rope_kernel_params *) octx->kernel_params; if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { return HTP_STATUS_INVAL_PARAMS; @@ -746,20 +737,23 @@ static int execute_op_rope_f32(struct htp_ops_context * octx) { const size_t dst_row_size = dst->ne[0] * sizeof(float); const size_t dst_row_stride = dst->nb[1]; + struct htp_rope_vtcm_layout layout; + htp_rope_vtcm_layout_build(&layout, src0->ne[0], kparams->n_threads, src2 ? src2->ne[0] : 0); + struct htp_rope_context rctx; memset(&rctx, 0, sizeof(struct htp_rope_context)); rctx.octx = octx; - rctx.vtcm_base = (uint8_t *) octx->ctx->vtcm_base; - rctx.spad_per_thread = kparams->spad_per_thread; - rctx.theta_cache_offset = kparams->theta_cache_offset; + rctx.vtcm_base = VTCM_LAYOUT_PTR(uint8_t, octx->ctx->vtcm_base, layout.off_spad); + rctx.spad_per_thread = layout.bytes_per_thread; + rctx.theta_cache_offset = layout.theta_cache_size_aligned; if (src2) { dma_queue * dma_q = octx->ctx->dma[0]; const size_t ff_size = src2->ne[0] * sizeof(float); - float * vtcm_freq_factors = (float *) (rctx.vtcm_base + kparams->freq_factors_offset); + float * vtcm_freq_factors = VTCM_LAYOUT_PTR(float, octx->ctx->vtcm_base, layout.off_freq_factors); dma_queue_push(dma_q, dma_make_data(vtcm_freq_factors, src2->data), - kparams->freq_factors_size, 0, ff_size, 1); + layout.freq_factors_size_aligned, 0, ff_size, 1); dma_queue_pop(dma_q); rctx.freq_factors = vtcm_freq_factors; } @@ -791,7 +785,7 @@ static int execute_op_rope_f32(struct htp_ops_context * octx) { rctx.src0_row_stride = src0_row_stride; rctx.dst_row_size = dst_row_size; rctx.dst_row_stride = dst_row_stride; - rctx.src0_row_size_aligned = kparams->src0_row_size_aligned; + rctx.src0_row_size_aligned = layout.src0_row_size_aligned; rctx.src0_nrows = nrows; rctx.nrows = nrows; diff --git a/ggml/src/ggml-hexagon/htp/rope-ops.h b/ggml/src/ggml-hexagon/htp/rope-ops.h index ee055ccbc19f..0c28ef826d5f 100644 --- a/ggml/src/ggml-hexagon/htp/rope-ops.h +++ b/ggml/src/ggml-hexagon/htp/rope-ops.h @@ -3,6 +3,7 @@ #include "hex-common.h" #include "hex-fastdiv.h" +#include "htp-vtcm.h" #define HTP_ROPE_SPAD_BLOCK 8 #define HTP_ROPE_SPAD_NSLOTS 4 @@ -10,14 +11,7 @@ struct htp_rope_kernel_params { uint32_t n_threads; - uint32_t src0_nrows; - uint32_t src0_nrows_per_thread; uint32_t vtcm_size; - uint32_t spad_per_thread; - uint32_t theta_cache_offset; - uint32_t src0_row_size_aligned; - uint32_t freq_factors_offset; - uint32_t freq_factors_size; struct fastdiv_values div_ne2_ne1; struct fastdiv_values div_ne1; @@ -31,6 +25,8 @@ _Static_assert(sizeof(struct htp_rope_kernel_params) <= 128, "htp_rope_kernel_pa struct htp_rope_vtcm_layout { size_t total_bytes; + size_t off_spad; + size_t off_freq_factors; size_t bytes_per_thread; size_t theta_cache_size_aligned; size_t src0_row_size_aligned; @@ -38,7 +34,7 @@ struct htp_rope_vtcm_layout { }; static inline void htp_rope_vtcm_layout_build( - struct htp_rope_vtcm_layout * layout, + struct htp_rope_vtcm_layout * L, uint32_t ne00, uint32_t n_threads, uint32_t n_freq_factors @@ -48,11 +44,15 @@ static inline void htp_rope_vtcm_layout_build( const size_t theta_cache_size_aligned = hex_round_up((uint32_t) src0_row_size, 256); const size_t freq_factors_size_aligned = hex_round_up(n_freq_factors * sizeof(float), 256); - layout->src0_row_size_aligned = src0_row_size_aligned; - layout->theta_cache_size_aligned = theta_cache_size_aligned; - layout->freq_factors_size_aligned = freq_factors_size_aligned; - layout->bytes_per_thread = theta_cache_size_aligned + HTP_ROPE_SPAD_NROWS * src0_row_size_aligned; - layout->total_bytes = layout->bytes_per_thread * n_threads + freq_factors_size_aligned; + L->src0_row_size_aligned = src0_row_size_aligned; + L->theta_cache_size_aligned = theta_cache_size_aligned; + L->freq_factors_size_aligned = freq_factors_size_aligned; + L->bytes_per_thread = theta_cache_size_aligned + HTP_ROPE_SPAD_NROWS * src0_row_size_aligned; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_spad, L->bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_freq_factors, freq_factors_size_aligned, n_freq_factors > 0); + L->total_bytes = off; } static inline uint8_t * rope_spad_slot(uint8_t * base, uint32_t slot, size_t row_size_aligned) { diff --git a/ggml/src/ggml-hexagon/htp/set-rows-ops.c b/ggml/src/ggml-hexagon/htp/set-rows-ops.c index 1d72538f176f..191cf0c6afba 100644 --- a/ggml/src/ggml-hexagon/htp/set-rows-ops.c +++ b/ggml/src/ggml-hexagon/htp/set-rows-ops.c @@ -79,8 +79,10 @@ static void set_rows_thread_dma_##TYPE_NAME##_##IDX_TYPE(unsigned int nth, unsig const uint32_t ir1 = MIN(ir0 + dr, srctx->task_start + srctx->tasks); \ dma_queue * dma_q = octx->ctx->dma[ith]; \ const struct htp_set_rows_vtcm_layout * vtcm_layout = &srctx->vtcm_layout; \ - uint8_t * vtcm_src0 = srctx->vtcm_base + vtcm_layout->off_src0 + ith * vtcm_layout->src0_bytes_per_thread; \ - uint8_t * vtcm_dst = srctx->vtcm_base + vtcm_layout->off_dst + ith * vtcm_layout->dst_bytes_per_thread; \ + uint8_t * vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, srctx->vtcm_base, vtcm_layout->off_src0) + \ + ith * vtcm_layout->src0_bytes_per_thread; \ + uint8_t * vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, srctx->vtcm_base, vtcm_layout->off_dst) + \ + ith * vtcm_layout->dst_bytes_per_thread; \ const uint32_t src0_row_size = ne00 * sizeof(float); \ const uint32_t dst_row_size = htp_tensor_get_row_size(octx->dst->type, ne00); \ const uint32_t nrows_per_thread = ir1 - ir0; \ @@ -188,14 +190,6 @@ int op_set_rows(struct htp_ops_context * octx) { const struct htp_set_rows_kernel_params * kparams = (const struct htp_set_rows_kernel_params *)octx->kernel_params; set_rows_preamble; - if (octx->src[0]->type != HTP_TYPE_F32) { - return HTP_STATUS_NO_SUPPORT; - } - - if (octx->dst->type != HTP_TYPE_F32 && octx->dst->type != HTP_TYPE_F16 && octx->dst->type != HTP_TYPE_Q8_0) { - return HTP_STATUS_NO_SUPPORT; - } - if (htp_tensor_is_extended(octx->src[1])) { return HTP_STATUS_NO_SUPPORT; } diff --git a/ggml/src/ggml-hexagon/htp/set-rows-ops.h b/ggml/src/ggml-hexagon/htp/set-rows-ops.h index 5e98d2cb55c5..b9cb6cc90a56 100644 --- a/ggml/src/ggml-hexagon/htp/set-rows-ops.h +++ b/ggml/src/ggml-hexagon/htp/set-rows-ops.h @@ -2,18 +2,13 @@ #define HTP_SET_ROWS_OPS_H #include "hex-fastdiv.h" +#include "htp-tensor.h" +#include "htp-vtcm.h" struct htp_set_rows_kernel_params { - int32_t n_threads; - int32_t total_tasks; - int32_t tasks_per_thread; - int32_t vtcm_size; - - // Fastdiv helpers - struct fastdiv_values div_ne11; - struct fastdiv_values div_ne12; - struct fastdiv_values div_tasks_per_thread; - struct fastdiv_values div_ne02; + uint32_t n_threads; + uint32_t total_tasks; + uint32_t vtcm_size; }; struct htp_set_rows_vtcm_layout { @@ -29,40 +24,27 @@ struct htp_set_rows_vtcm_layout { }; static inline void htp_set_rows_vtcm_layout_build( - struct htp_set_rows_vtcm_layout * vtcm_layout, + struct htp_set_rows_vtcm_layout * L, int dst_type, uint32_t ne00, uint32_t n_threads) { - size_t src0_row_size = ne00 * 4; - size_t dst_row_size = 0; - switch (dst_type) { - case 0: // HTP_TYPE_F32 - dst_row_size = ne00 * 4; - break; - case 1: // HTP_TYPE_F16 - dst_row_size = ne00 * 2; - break; - case 8: // HTP_TYPE_Q8_0 - dst_row_size = (ne00 / 32) * 34; - break; - default: - dst_row_size = 0; - break; - } + size_t src0_row_size = ne00 * sizeof(float); + size_t dst_row_size = htp_tensor_get_row_size(dst_type, ne00); size_t src0_row_size_aligned = (src0_row_size + 255) & ~255; size_t dst_row_size_aligned = (dst_row_size + 255) & ~255; - vtcm_layout->src0_spad_half_size = src0_row_size_aligned; - vtcm_layout->dst_spad_half_size = dst_row_size_aligned; + L->src0_spad_half_size = src0_row_size_aligned; + L->dst_spad_half_size = dst_row_size_aligned; - vtcm_layout->src0_bytes_per_thread = src0_row_size_aligned * 2; - vtcm_layout->dst_bytes_per_thread = dst_row_size_aligned * 2; + L->src0_bytes_per_thread = src0_row_size_aligned * 2; + L->dst_bytes_per_thread = dst_row_size_aligned * 2; - vtcm_layout->off_src0 = 0; - vtcm_layout->off_dst = vtcm_layout->off_src0 + vtcm_layout->src0_bytes_per_thread * n_threads; - vtcm_layout->total_bytes = vtcm_layout->off_dst + vtcm_layout->dst_bytes_per_thread * n_threads; + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + L->total_bytes = off; } #if defined(__cplusplus) diff --git a/ggml/src/ggml-hexagon/htp/softmax-ops.c b/ggml/src/ggml-hexagon/htp/softmax-ops.c index 48be5d725aab..d65c3fae33a6 100644 --- a/ggml/src/ggml-hexagon/htp/softmax-ops.c +++ b/ggml/src/ggml-hexagon/htp/softmax-ops.c @@ -496,7 +496,7 @@ static int execute_op_softmax_f32(struct htp_ops_context * octx) { return HTP_STATUS_INVAL_PARAMS; } - if (kparams->kernel_id >= HTP_SOFTMAX_KERNEL_COUNT) { + if (kparams->kernel_type >= HTP_SOFTMAX_KERNEL_COUNT) { return HTP_STATUS_INVAL_PARAMS; } @@ -532,34 +532,38 @@ static int execute_op_softmax_f32(struct htp_ops_context * octx) { const uint32_t n_threads = octx->n_threads; uint8_t * const vtcm_base = (uint8_t *) octx->ctx->vtcm_base; - const uint32_t off_src0 = 0; - const uint32_t off_dst = off_src0 + kparams->vtcm_src0_size_per_thread * kparams->n_threads; - const uint32_t off_src1 = off_dst + kparams->vtcm_dst_size_per_thread * kparams->n_threads; + struct htp_softmax_vtcm_layout layout; + htp_softmax_vtcm_layout_build(&layout, + src0->ne[0], + kparams->use_src1 ? octx->src[1]->ne[0] : 0, + kparams->use_src1 != 0, + kparams->use_f16 != 0, + kparams->n_threads); struct htp_softmax_context smctx = { .octx = octx, .kparams = kparams, - .compute = (void *) softmax_kernels[kparams->kernel_id], + .compute = (void *) softmax_kernels[kparams->kernel_type], .data_src0 = src0->data, .data_src1 = kparams->use_src1 ? octx->src[1]->data : 0, .data_dst = dst->data, - .vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, off_src0), - .vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, off_dst), - .vtcm_src1 = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, vtcm_base, off_src1, kparams->use_src1), + .vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, layout.off_src0), + .vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, layout.off_dst), + .vtcm_src1 = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, vtcm_base, layout.off_src1, kparams->use_src1), - .vtcm_src0_size_per_thread = kparams->vtcm_src0_size_per_thread, - .vtcm_src1_size_per_thread = kparams->vtcm_src1_size_per_thread, - .vtcm_dst_size_per_thread = kparams->vtcm_dst_size_per_thread, + .vtcm_src0_size_per_thread = (uint32_t) layout.src0_bytes_per_thread, + .vtcm_src1_size_per_thread = (uint32_t) layout.src1_bytes_per_thread, + .vtcm_dst_size_per_thread = (uint32_t) layout.dst_bytes_per_thread, - .src0_spad_half_size = kparams->src0_spad_half_size, - .src1_spad_half_size = kparams->src1_spad_half_size, - .dst_spad_half_size = kparams->dst_spad_half_size, + .src0_spad_half_size = (uint32_t) layout.src0_spad_half_size, + .src1_spad_half_size = (uint32_t) layout.src1_spad_half_size, + .dst_spad_half_size = (uint32_t) layout.dst_spad_half_size, - .src0_row_size_aligned = kparams->src0_row_size_aligned, - .src1_row_size_aligned = kparams->src1_row_size_aligned, - .dst_row_size_aligned = kparams->dst_row_size_aligned, + .src0_row_size_aligned = (uint32_t) layout.src0_spad_half_size, + .src1_row_size_aligned = (uint32_t) layout.src1_spad_half_size, + .dst_row_size_aligned = (uint32_t) layout.dst_spad_half_size, .use_f16 = kparams->use_f16 != 0, diff --git a/ggml/src/ggml-hexagon/htp/softmax-ops.h b/ggml/src/ggml-hexagon/htp/softmax-ops.h index 8d976adb83ea..ef6567306d42 100644 --- a/ggml/src/ggml-hexagon/htp/softmax-ops.h +++ b/ggml/src/ggml-hexagon/htp/softmax-ops.h @@ -7,8 +7,9 @@ #include #include "hex-fastdiv.h" #include "hex-common.h" +#include "htp-vtcm.h" -enum htp_softmax_kernel_id { +enum htp_softmax_kernel_type { HTP_SOFTMAX_KERNEL_NOMASK = 0, HTP_SOFTMAX_KERNEL_MASK_F32, HTP_SOFTMAX_KERNEL_MASK_F16, @@ -16,28 +17,14 @@ enum htp_softmax_kernel_id { }; struct htp_softmax_kernel_params { + uint8_t kernel_type; uint32_t n_threads; - uint32_t src0_nrows; - uint32_t src0_nrows_per_thread; uint32_t vtcm_size; - uint32_t vtcm_src0_size_per_thread; - uint32_t vtcm_src1_size_per_thread; - uint32_t vtcm_dst_size_per_thread; - - uint32_t src0_row_size_aligned; - uint32_t src1_row_size_aligned; - uint32_t dst_row_size_aligned; - - uint32_t src0_spad_half_size; - uint32_t src1_spad_half_size; - uint32_t dst_spad_half_size; - uint32_t n_head; uint32_t n_head_log2; uint32_t use_src1; uint32_t use_f16; - uint32_t kernel_id; float scale; float max_bias; @@ -72,7 +59,7 @@ struct htp_softmax_vtcm_layout { }; static inline void htp_softmax_vtcm_layout_build( - struct htp_softmax_vtcm_layout * layout, + struct htp_softmax_vtcm_layout * L, uint32_t ne00, uint32_t ne10, bool use_src1, @@ -87,20 +74,21 @@ static inline void htp_softmax_vtcm_layout_build( size_t dst_row_size_aligned = hex_round_up(dst_row_size, 128); size_t src1_row_size_aligned = use_src1 ? hex_round_up(src1_row_size, 128) : 0; - layout->src0_spad_half_size = src0_row_size_aligned; - layout->dst_spad_half_size = dst_row_size_aligned; - layout->src1_spad_half_size = src1_row_size_aligned; + L->src0_spad_half_size = src0_row_size_aligned; + L->dst_spad_half_size = dst_row_size_aligned; + L->src1_spad_half_size = src1_row_size_aligned; // Double buffering: 2 half-buffers per thread - layout->src0_bytes_per_thread = src0_row_size_aligned * 2; - layout->dst_bytes_per_thread = dst_row_size_aligned * 2; - layout->src1_bytes_per_thread = src1_row_size_aligned * 2; + L->src0_bytes_per_thread = src0_row_size_aligned * 2; + L->dst_bytes_per_thread = dst_row_size_aligned * 2; + L->src1_bytes_per_thread = src1_row_size_aligned * 2; - layout->off_src0 = 0; - layout->off_dst = layout->off_src0 + layout->src0_bytes_per_thread * n_threads; - layout->off_src1 = layout->off_dst + layout->dst_bytes_per_thread * n_threads; + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_src1, L->src1_bytes_per_thread * n_threads, use_src1); - layout->total_bytes = layout->off_src1 + layout->src1_bytes_per_thread * n_threads; + L->total_bytes = off; } #endif // HTP_SOFTMAX_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/solve-tri-ops.c b/ggml/src/ggml-hexagon/htp/solve-tri-ops.c index 182982fcda66..628ca65e8451 100644 --- a/ggml/src/ggml-hexagon/htp/solve-tri-ops.c +++ b/ggml/src/ggml-hexagon/htp/solve-tri-ops.c @@ -13,14 +13,16 @@ #include "htp-tensor.h" #include "hvx-types.h" #include "hvx-utils.h" +#include "solve-tri-ops.h" struct htp_solve_tri_context { - struct htp_ops_context * octx; - uint32_t jobs_per_thread; - uint32_t total_jobs; - uint32_t job_start; - uint32_t k_chunks; - uint32_t col_block; + struct htp_ops_context * octx; + const struct htp_solve_tri_kernel_params * kparams; + uint32_t jobs_per_thread; + uint32_t total_jobs; + uint32_t job_start; + uint32_t k_chunks; + uint32_t col_block; }; static inline void solve_tri_row_scalar(const float * A_row, @@ -80,6 +82,7 @@ static inline void solve_tri_row_hvx(const float * A_row, static void solve_tri_batch_thread_f32(unsigned int nth, unsigned int ith, void * data) { struct htp_solve_tri_context * sctx = (struct htp_solve_tri_context *) data; struct htp_ops_context * octx = sctx->octx; + const struct htp_solve_tri_kernel_params * kparams = sctx->kparams; const struct htp_tensor * src0 = octx->src[0]; // A const struct htp_tensor * src1 = octx->src[1]; // B @@ -91,7 +94,7 @@ static void solve_tri_batch_thread_f32(unsigned int nth, unsigned int ith, void const uint32_t ne02 = src0->ne[2]; const uint32_t col_block = VLEN_FP32; - const uint32_t k_full = (k / col_block) * col_block; + const uint32_t k_full = k & ~(col_block - 1); const uint32_t start_batch = sctx->job_start + sctx->jobs_per_thread * ith; const uint32_t end_batch = MIN(start_batch + sctx->jobs_per_thread, sctx->job_start + sctx->total_jobs); @@ -100,7 +103,7 @@ static void solve_tri_batch_thread_f32(unsigned int nth, unsigned int ith, void htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) start_batch); for (uint32_t batch = start_batch; batch < end_batch; ++batch) { - const uint32_t i03 = batch / ne02; + const uint32_t i03 = fastdiv(batch, &kparams->div_ne02); const uint32_t i02 = batch - i03 * ne02; const float * A_batch = @@ -141,6 +144,7 @@ static void solve_tri_batch_thread_f32(unsigned int nth, unsigned int ith, void static void solve_tri_chunk_thread_f32(unsigned int nth, unsigned int ith, void * data) { struct htp_solve_tri_context * sctx = (struct htp_solve_tri_context *) data; struct htp_ops_context * octx = sctx->octx; + const struct htp_solve_tri_kernel_params * kparams = sctx->kparams; const struct htp_tensor * src0 = octx->src[0]; // A const struct htp_tensor * src1 = octx->src[1]; // B @@ -158,10 +162,10 @@ static void solve_tri_chunk_thread_f32(unsigned int nth, unsigned int ith, void htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) start_job); for (uint32_t job = start_job; job < end_job; ++job) { - const uint32_t batch = job / sctx->k_chunks; + const uint32_t batch = fastdiv(job, &kparams->div_k_chunks); const uint32_t chunk = job - batch * sctx->k_chunks; - const uint32_t i03 = batch / ne02; + const uint32_t i03 = fastdiv(batch, &kparams->div_ne02); const uint32_t i02 = batch - i03 * ne02; const float * A_batch = @@ -198,36 +202,17 @@ int op_solve_tri(struct htp_ops_context * octx) { const struct htp_tensor * src0 = octx->src[0]; // A const struct htp_tensor * src1 = octx->src[1]; // B const struct htp_tensor * dst = octx->dst; // X - - if (src0->type != HTP_TYPE_F32 || src1->type != HTP_TYPE_F32 || dst->type != HTP_TYPE_F32) { - return HTP_STATUS_NO_SUPPORT; - } - - // left=true, lower=true, uni=false only - if (src0->ne[0] != src0->ne[1]) { - return HTP_STATUS_INVAL_PARAMS; - } - if (src0->ne[1] != src1->ne[1]) { - return HTP_STATUS_INVAL_PARAMS; - } - if (src0->ne[2] != src1->ne[2] || src0->ne[3] != src1->ne[3]) { - return HTP_STATUS_INVAL_PARAMS; - } - if (dst->ne[0] != src1->ne[0] || dst->ne[1] != src1->ne[1] || dst->ne[2] != src1->ne[2] || - dst->ne[3] != src1->ne[3]) { - return HTP_STATUS_INVAL_PARAMS; - } + const struct htp_solve_tri_kernel_params * kparams = + (const struct htp_solve_tri_kernel_params *) octx->kernel_params; if (htp_tensor_is_extended(src0) || htp_tensor_is_extended(src1) || htp_tensor_is_extended(dst)) { return HTP_STATUS_NO_SUPPORT; } - const uint32_t k = src1->ne[0]; - - const uint32_t col_block = VLEN_FP32; - const uint32_t k_chunks = (k + col_block - 1) / col_block; - const uint32_t total_batches = src0->ne[2] * src0->ne[3]; - const bool batched = total_batches >= (uint32_t) octx->n_threads; + const uint32_t col_block = kparams->col_block; + const uint32_t k_chunks = kparams->k_chunks; + const uint32_t total_batches = kparams->total_batches; + const bool batched = (kparams->batched != 0); FARF(HIGH, "solve-tri: (%ux%ux%ux%u) x (%ux%ux%ux%u) -> (%ux%ux%ux%u) : batched %d\n", src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], @@ -239,9 +224,7 @@ int op_solve_tri(struct htp_ops_context * octx) { uint32_t njobs = total_batches; if (octx->ctx->mdev.count > 1) { - const uint32_t batch_size = dst->nb[2]; - const uint32_t batches_per_chunk = (batch_size > 0) ? (HEX_L2_LINE_SIZE / hex_gcd_u32(batch_size, HEX_L2_LINE_SIZE)) : 1; - const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_batches, htp_tensor_mdev_data_aligned(dst) ? batches_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(total_batches, htp_tensor_mdev_data_aligned(dst) ? kparams->batches_per_chunk : 0, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); job_start = range.start; njobs = range.count; } @@ -250,11 +233,15 @@ int op_solve_tri(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - // Batch-level parallelism + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, njobs))) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t n_threads = octx->n_threads; struct htp_solve_tri_context sctx = { .octx = octx, + .kparams = kparams, .jobs_per_thread = fastdiv(njobs + n_threads - 1, &octx->n_threads_div), .total_jobs = njobs, .job_start = job_start, @@ -264,8 +251,7 @@ int op_solve_tri(struct htp_ops_context * octx) { work_queue_run(octx->ctx->work_queue, solve_tri_batch_thread_f32, &sctx, n_threads); } else { - // Chunk-level parallelism - const uint32_t total_jobs = total_batches * k_chunks; + const uint32_t total_jobs = kparams->total_jobs; uint32_t job_start = 0; uint32_t njobs = total_jobs; @@ -281,10 +267,15 @@ int op_solve_tri(struct htp_ops_context * octx) { return HTP_STATUS_OK; } + if (!htp_ops_context_set_n_threads(octx, MIN(kparams->n_threads, njobs))) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t n_threads = octx->n_threads; struct htp_solve_tri_context sctx = { .octx = octx, + .kparams = kparams, .jobs_per_thread = fastdiv(njobs + n_threads - 1, &octx->n_threads_div), .total_jobs = njobs, .job_start = job_start, diff --git a/ggml/src/ggml-hexagon/htp/solve-tri-ops.h b/ggml/src/ggml-hexagon/htp/solve-tri-ops.h new file mode 100644 index 000000000000..327415814bf4 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/solve-tri-ops.h @@ -0,0 +1,26 @@ +#ifndef HTP_SOLVE_TRI_OPS_H +#define HTP_SOLVE_TRI_OPS_H + +#include "hex-fastdiv.h" +#include + +struct htp_solve_tri_kernel_params { + uint32_t n_threads; + uint32_t total_batches; + uint32_t total_jobs; + uint32_t k_chunks; + uint32_t col_block; + uint32_t batched; + uint32_t batches_per_chunk; + + struct fastdiv_values div_ne02; + struct fastdiv_values div_k_chunks; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_solve_tri_kernel_params) <= 128, "htp_solve_tri_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_solve_tri_kernel_params) <= 128, "htp_solve_tri_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_SOLVE_TRI_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/ssm-conv.c b/ggml/src/ggml-hexagon/htp/ssm-conv.c index 0d28c8990480..4b06b18f2cd2 100644 --- a/ggml/src/ggml-hexagon/htp/ssm-conv.c +++ b/ggml/src/ggml-hexagon/htp/ssm-conv.c @@ -135,6 +135,13 @@ static inline void hvx_ssm_conv_unpack_to_T(const float * raw, float * T, uint32 } } +static __attribute__((noinline)) void hvx_ssm_conv_silu_vtcm(float * restrict buf, uint32_t n_vecs) { + HVX_Vector * restrict vbuf = (HVX_Vector *) buf; + for (uint32_t i = 0; i < n_vecs; ++i) { + vbuf[i] = hvx_vec_silu_f32(vbuf[i]); + } +} + // Decode dot product specialization for d_conv == 4: multiply in the raw channel-major layout, // then deinterleave the products so each vector holds one tap of 32 channels, and sum. // Keeps both operands in DMA layout - no transpose, no scratch. @@ -166,11 +173,12 @@ static inline void hvx_ssm_conv_decode_4(const float * x, const float * w, float // the lanes past the channel tail. static inline void hvx_ssm_conv_transpose_block(const float * raw_block, float * T, + uint32_t raw_stride_bytes, uint32_t ncs, uint32_t cb_n, HVX_Vector vv) { const size_t base = (size_t) raw_block; - const uint32_t mu = cb_n * ncs * sizeof(float) - 1; + const uint32_t mu = cb_n * raw_stride_bytes - 1; for (uint32_t t = 0; t < ncs; ++t) { Q6_vgather_ARMVw((HVX_Vector *) (T + (size_t) t * VLEN_FP32), base + t * sizeof(float), mu, vv); @@ -189,9 +197,10 @@ static void ssm_conv_thread_f32_decode(unsigned int nth, unsigned int ith, void dma_queue * dma_q = octx->ctx->dma[ith]; - const uint32_t d_conv = kparams->d_conv; - const uint32_t d_inner = kparams->d_inner; - const uint32_t n_s = kparams->n_s; + const uint32_t d_conv = kparams->d_conv; + const uint32_t d_inner = kparams->d_inner; + const uint32_t n_s = kparams->n_s; + const bool apply_silu = kparams->silu != 0; const uint32_t dr = scctx->nrows_per_thread; const uint32_t ir0 = scctx->row_start + dr * ith; @@ -232,7 +241,7 @@ static void ssm_conv_thread_f32_decode(unsigned int nth, unsigned int ith, void // raw_dot keeps both operands in the DMA layout, so src1 needs no prep pass const bool raw_dot = (d_conv == 4) && (d_inner_per_thread % VLEN_FP32 == 0); - const uint32_t n_tiles = (d_inner_per_thread + d_inner_tile - 1) / d_inner_tile; + const uint32_t n_tiles = fastdiv(d_inner_per_thread + d_inner_tile - 1, &kparams->div_d_inner_tile); const uint32_t n_chunks = n_s * n_tiles; const size_t row_bytes = d_conv * sizeof(float); @@ -295,21 +304,18 @@ static void ssm_conv_thread_f32_decode(unsigned int nth, unsigned int ith, void hvx_ssm_conv_unpack_to_T(src0_tile_raw[c & 1], src0_T, tile_n, tile_stride, d_conv); for (uint32_t cb = 0; cb < tile_n; cb += VLEN_FP32) { - const uint32_t cb_n = MIN(VLEN_FP32, tile_n - cb); HVX_Vector acc = hvx_vec_splat_f32(0.0f); for (uint32_t j = 0; j < d_conv; ++j) { HVX_Vector x = *(const HVX_Vector *)(src0_T + j * tile_stride + cb); HVX_Vector w = *(const HVX_Vector *)(src1_T + j * d_inner_stride + tile_off + cb); acc = Q6_Vqf32_vadd_Vqf32Vqf32(acc, Q6_Vqf32_vmpy_VsfVsf(x, w)); } - HVX_Vector y = Q6_Vsf_equals_Vqf32(acc); - if (cb_n == VLEN_FP32) { - *(HVX_Vector *)(out + cb) = y; - } else { - hvx_vec_store_u(out + cb, cb_n * sizeof(float), y); - } + *(HVX_Vector *)(out + cb) = Q6_Vsf_equals_Vqf32(acc); } } + if (apply_silu) { + hvx_ssm_conv_silu_vtcm(out, hex_round_up(tile_n, VLEN_FP32) / VLEN_FP32); + } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) i3); const dma_addr_t dst_ddr = dst->data + i3 * dst_stride_seq_bytes + (ir0 + tile_off) * sizeof(float); @@ -352,11 +358,12 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void dma_queue * dma_q = octx->ctx->dma[ith]; - const uint32_t d_conv = kparams->d_conv; - const uint32_t d_inner = kparams->d_inner; - const uint32_t n_t = kparams->n_t; - const uint32_t n_s = kparams->n_s; - const uint32_t ncs = src0->ne[0]; + const uint32_t d_conv = kparams->d_conv; + const uint32_t d_inner = kparams->d_inner; + const uint32_t n_t = kparams->n_t; + const uint32_t n_s = kparams->n_s; + const uint32_t ncs = src0->ne[0]; + const bool apply_silu = kparams->silu != 0; const uint32_t dr = scctx->nrows_per_thread; const uint32_t ir0 = scctx->row_start + dr * ith; @@ -387,7 +394,8 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void // src0 spad holds two raw tiles (fetch of tile n+1 overlaps compute of tile n) plus // the transposed block. dst spad holds two tiles so a writeback can stay in flight. - const size_t src0_tile_raw_bytes = hex_round_up(d_inner_tile * ncs * sizeof(float), 128); + const size_t raw_stride_bytes = ncs * sizeof(float) + sizeof(float); + const size_t src0_tile_raw_bytes = hex_round_up(d_inner_tile * raw_stride_bytes, 128); const size_t dst_tile_bytes = hex_round_up(d_inner_tile * n_t * sizeof(float), 128); float * src0_tile_raw[2] = { (float *) src0_spad_base, (float *) (src0_spad_base + src0_tile_raw_bytes) }; @@ -397,7 +405,7 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void struct htp_thread_trace * tr = &octx->ctx->trace[ith]; - const uint32_t n_tiles = (d_inner_per_thread + d_inner_tile - 1) / d_inner_tile; + const uint32_t n_tiles = fastdiv(d_inner_per_thread + d_inner_tile - 1, &kparams->div_d_inner_tile); const uint32_t n_chunks = n_s * n_tiles; const size_t row_bytes = ncs * sizeof(float); @@ -413,7 +421,7 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void (ir0 + tile_off_fetch) * src0_stride_inner_bytes; \ dma_queue_push(dma_q, \ dma_make_data((uint8_t *) src0_tile_raw[(c) & 1], fetch_ddr), \ - row_bytes, src0_stride_inner_bytes, row_bytes, cur_tile_n); \ + raw_stride_bytes, src0_stride_inner_bytes, row_bytes, cur_tile_n); \ tile_off_fetch += d_inner_tile; \ if (tile_off_fetch >= d_inner_per_thread) { \ tile_off_fetch = 0; \ @@ -440,11 +448,7 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void const uint32_t C_TILE = VLEN_FP32; // gather offsets: lane r reads channel r of the raw tile block - uint32_t __attribute__((aligned(VLEN))) gather_off[VLEN_FP32]; - for (uint32_t r = 0; r < VLEN_FP32; ++r) { - gather_off[r] = r * ncs * sizeof(float); - } - const HVX_Vector vv = *(const HVX_Vector *) gather_off; + const HVX_Vector vv = hvx_vec_gather_offsets_w(raw_stride_bytes); uint32_t i3 = 0; uint32_t tile_off = 0; @@ -468,7 +472,8 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void const uint32_t cb_n = MIN(C_TILE, tile_n - cb); htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) tile_off); - hvx_ssm_conv_transpose_block(raw + (size_t) cb * ncs, src0_T, ncs, cb_n, vv); + const float * raw_ch = (const float *) ((const uint8_t *) raw + (size_t) cb * raw_stride_bytes); + hvx_ssm_conv_transpose_block(raw_ch, src0_T, raw_stride_bytes, ncs, cb_n, vv); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_A_PREP, (uint16_t) tile_off); const float * restrict wp = src1_T + tile_off + cb; @@ -513,10 +518,14 @@ static void ssm_conv_thread_f32_prefill(unsigned int nth, unsigned int ith, void htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) tile_off); } + if (apply_silu) { + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) tile_off); + hvx_ssm_conv_silu_vtcm(out, n_t * (dst_tile_stride / C_TILE)); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) tile_off); + } + // Writeback dst_tile VTCM -> DDR via 2D DMA - dma_queue_push(dma_q, - dma_make_data(dst->data + i3 * dst_stride_seq_bytes + (ir0 + tile_off) * sizeof(float), - (uint8_t *) out), + dma_queue_push(dma_q, dma_make_data(dst->data + i3 * dst_stride_seq_bytes + (ir0 + tile_off) * sizeof(float), (uint8_t *) out), dst_stride_token_bytes, dst_tile_stride * sizeof(float), tile_n * sizeof(float), n_t); if (c + 2 < n_chunks) { @@ -547,13 +556,8 @@ int op_ssm_conv_f32(struct htp_ops_context * octx) { const struct htp_tensor * src1 = octx->src[1]; const struct htp_tensor * dst = octx->dst; - if (src0->type != HTP_TYPE_F32 || src1->type != HTP_TYPE_F32 || dst->type != HTP_TYPE_F32) { - return HTP_STATUS_NO_SUPPORT; - } - const struct htp_ssm_conv_kernel_params * kparams = (const struct htp_ssm_conv_kernel_params *) octx->kernel_params; - if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { return HTP_STATUS_INVAL_PARAMS; } @@ -582,26 +586,30 @@ int op_ssm_conv_f32(struct htp_ops_context * octx) { return HTP_STATUS_VTCM_TOO_SMALL; } - const uint32_t n_threads = octx->n_threads; + const uint32_t n_threads = octx->n_threads; + const uint32_t raw_rpt = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); + const uint32_t d_inner_per_thread = hex_round_up(raw_rpt, VLEN_FP32); + + struct htp_ssm_conv_vtcm_layout L; + htp_ssm_conv_vtcm_layout_build(&L, d_inner_per_thread, kparams->d_conv, kparams->n_t, kparams->d_inner_tile, n_threads); + + uint8_t * const base = (uint8_t *) octx->ctx->vtcm_base; - octx->src0_spad.size_per_thread = kparams->vtcm_src0_size_per_thread; - octx->src1_spad.size_per_thread = kparams->vtcm_src1_size_per_thread; - octx->dst_spad.size_per_thread = kparams->vtcm_dst_size_per_thread; + octx->src0_spad.size_per_thread = L.src0_bytes_per_thread; + octx->src1_spad.size_per_thread = L.src1_bytes_per_thread; + octx->dst_spad.size_per_thread = L.dst_bytes_per_thread; - octx->src0_spad.size = kparams->vtcm_src0_size; - octx->src1_spad.size = kparams->vtcm_src1_size; - octx->dst_spad.size = kparams->vtcm_dst_size; + octx->src0_spad.size = L.src0_bytes; + octx->src1_spad.size = L.src1_bytes; + octx->dst_spad.size = L.dst_bytes; - octx->src0_spad.data = octx->ctx->vtcm_base; - octx->src1_spad.data = octx->src0_spad.data + octx->src0_spad.size; - octx->dst_spad.data = octx->src1_spad.data + octx->src1_spad.size; + octx->src0_spad.data = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0); + octx->src1_spad.data = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src1); + octx->dst_spad.data = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst); octx->src0_spad.src = NULL; octx->src1_spad.src = NULL; octx->dst_spad.src = NULL; - const uint32_t raw_rpt = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); - const uint32_t d_inner_per_thread = hex_round_up(raw_rpt, VLEN_FP32); - struct htp_ssm_conv_context scctx = { .octx = octx, .kparams = kparams, diff --git a/ggml/src/ggml-hexagon/htp/ssm-conv.h b/ggml/src/ggml-hexagon/htp/ssm-conv.h index a071d74b0402..cd4180857294 100644 --- a/ggml/src/ggml-hexagon/htp/ssm-conv.h +++ b/ggml/src/ggml-hexagon/htp/ssm-conv.h @@ -3,8 +3,10 @@ #include +#include "hex-common.h" #include "hex-fastdiv.h" #include "htp-ops.h" +#include "htp-vtcm.h" struct htp_ssm_conv_kernel_params { uint32_t n_threads; @@ -14,16 +16,63 @@ struct htp_ssm_conv_kernel_params { uint32_t n_s; uint32_t d_inner_tile; - uint32_t vtcm_src0_size_per_thread; - uint32_t vtcm_src1_size_per_thread; - uint32_t vtcm_dst_size_per_thread; - - uint32_t vtcm_src0_size; - uint32_t vtcm_src1_size; - uint32_t vtcm_dst_size; uint32_t vtcm_size; + uint32_t silu; + + struct fastdiv_values div_d_inner_tile; }; +struct htp_ssm_conv_vtcm_layout { + size_t total_bytes; + size_t off_src0; + size_t off_src1; + size_t off_dst; + size_t src0_bytes_per_thread; + size_t src1_bytes_per_thread; + size_t dst_bytes_per_thread; + size_t src0_bytes; + size_t src1_bytes; + size_t dst_bytes; +}; + +static inline void htp_ssm_conv_vtcm_layout_build( + struct htp_ssm_conv_vtcm_layout * L, + uint32_t d_inner_per_thread, + uint32_t d_conv, + uint32_t n_t, + uint32_t d_inner_tile, + uint32_t n_threads +) { + const size_t src1_raw_bytes = hex_round_up((size_t) d_inner_per_thread * d_conv * sizeof(float), 128) + 128; + const size_t src1_T_bytes = hex_round_up((size_t) d_conv * d_inner_per_thread * sizeof(float), 128); + + L->src1_bytes_per_thread = src1_raw_bytes + src1_T_bytes; + + if (n_t == 1) { + const size_t src0_tile_raw_bytes = hex_round_up((size_t) d_inner_tile * d_conv * sizeof(float), 128); + const size_t src0_T_bytes = hex_round_up((size_t) d_conv * d_inner_tile * sizeof(float), 128); + L->src0_bytes_per_thread = 2 * src0_tile_raw_bytes + src0_T_bytes; + L->dst_bytes_per_thread = 2 * hex_round_up((size_t) d_inner_tile * sizeof(float), 128); + } else { + const uint32_t ncs = d_conv - 1 + n_t; + const size_t raw_stride_bytes = ncs * sizeof(float) + sizeof(float); + const size_t src0_block_T = hex_round_up((size_t) ncs * 32 * sizeof(float), 128); + const size_t src0_tile_raw = hex_round_up((size_t) d_inner_tile * raw_stride_bytes, 128); + L->src0_bytes_per_thread = 2 * src0_tile_raw + src0_block_T; + L->dst_bytes_per_thread = 2 * hex_round_up((size_t) d_inner_tile * n_t * sizeof(float), 128); + } + + L->src0_bytes = L->src0_bytes_per_thread * n_threads; + L->src1_bytes = L->src1_bytes_per_thread * n_threads; + L->dst_bytes = L->dst_bytes_per_thread * n_threads; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes); + VTCM_LAYOUT_ALLOC(off, off_src1, L->src1_bytes); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes); + L->total_bytes = off; +} + #if defined(__cplusplus) static_assert(sizeof(struct htp_ssm_conv_kernel_params) <= 128, "htp_ssm_conv_kernel_params is too large for kernel_params blob"); #else diff --git a/ggml/src/ggml-hexagon/htp/sum-rows-ops.c b/ggml/src/ggml-hexagon/htp/sum-rows-ops.c index 177c74b33a7b..3d931ed19305 100644 --- a/ggml/src/ggml-hexagon/htp/sum-rows-ops.c +++ b/ggml/src/ggml-hexagon/htp/sum-rows-ops.c @@ -18,6 +18,7 @@ #include "htp-ctx.h" #include "htp-ops.h" #include "htp-tensor.h" +#include "sum-rows-ops.h" #define sum_rows_preamble \ const struct htp_tensor *src0 = octx->src[0]; \ @@ -52,7 +53,6 @@ struct sum_rows_context { size_t dst_stride; uint32_t rows_per_thread; uint32_t total_rows; - bool opt_path; }; static void sum_rows_thread_f32(unsigned int nth, unsigned int ith, void *data) { @@ -71,7 +71,6 @@ static void sum_rows_thread_f32(unsigned int nth, unsigned int ith, void *data) const size_t src_stride = smctx->src_stride; const size_t dst_stride = smctx->dst_stride; const uint32_t ne00 = smctx->ne00; - const bool opt_path = smctx->opt_path; const float * restrict src_th = (const float *) (smctx->src_data + (start_row * src_stride)); float * restrict dst_th = (float *) (smctx->dst_data + (start_row * dst_stride)); @@ -90,11 +89,7 @@ static void sum_rows_thread_f32(unsigned int nth, unsigned int ith, void *data) hex_l2fetch((const uint8_t *) src_local + src_stride, src_stride, src_stride, 1); } - if (opt_path) { - *dst_local = hvx_reduce_sum_f32_a((const uint8_t *) src_local, ne00); - } else { - *dst_local = hvx_reduce_sum_f32((const uint8_t *) src_local, ne00); - } + *dst_local = hvx_reduce_sum_f32((const uint8_t *) src_local, ne00); } htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) start_row); @@ -111,6 +106,13 @@ int op_sum_rows(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } + const struct htp_sum_rows_kernel_params * kparams = + (const struct htp_sum_rows_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t src0_nrows = ne01 * ne02 * ne03; const size_t dst_data_row_size = dst->ne[0] * sizeof(float); @@ -129,14 +131,9 @@ int op_sum_rows(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = octx->n_threads; + const uint32_t n_threads = octx->n_threads; const uint32_t rows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); - bool opt_path = false; - if ((0 == hex_is_aligned((void *) src0->data, VLEN)) && !(nb01 & (VLEN - 1))) { - opt_path = true; - } - struct sum_rows_context smctx = { .octx = octx, .src_data = (const uint8_t *) src0->data + row_start * nb01, @@ -146,7 +143,6 @@ int op_sum_rows(struct htp_ops_context * octx) { .dst_stride = nb1, .rows_per_thread = rows_per_thread, .total_rows = nrows, - .opt_path = opt_path, }; work_queue_run(octx->ctx->work_queue, sum_rows_thread_f32, &smctx, n_threads); @@ -197,6 +193,13 @@ int op_sum(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } + const struct htp_sum_rows_kernel_params * kparams = + (const struct htp_sum_rows_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + if (octx->ctx->mdev.count > 1 && octx->ctx->mdev.idx > 0) { return HTP_STATUS_OK; } @@ -207,9 +210,8 @@ int op_sum(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = (total_elems >= 1024) ? MIN(octx->n_threads, HTP_MAX_NTHREADS) : 1; - const uint32_t raw_chunk = (total_elems + n_threads - 1) / n_threads; - const uint32_t elems_per_thread = hex_round_up(raw_chunk, 32); + const uint32_t n_threads = octx->n_threads; + const uint32_t elems_per_thread = kparams->elems_per_thread; struct sum_context sctx = { .octx = octx, @@ -324,6 +326,13 @@ int op_argmax(struct htp_ops_context * octx) { return HTP_STATUS_NO_SUPPORT; } + const struct htp_sum_rows_kernel_params * kparams = + (const struct htp_sum_rows_kernel_params *) octx->kernel_params; + + if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + const uint32_t ne00 = src0->ne[0]; const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; @@ -341,9 +350,8 @@ int op_argmax(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = (ne00 >= 1024) ? MIN(octx->n_threads, HTP_MAX_NTHREADS) : 1; - const uint32_t raw_chunk = (ne00 + n_threads - 1) / n_threads; - const uint32_t elems_per_thread = hex_round_up(raw_chunk, 32); + const uint32_t n_threads = octx->n_threads; + const uint32_t elems_per_thread = kparams->elems_per_thread; struct argmax_context actx = { .octx = octx, @@ -389,8 +397,8 @@ int op_argmax(struct htp_ops_context * octx) { return HTP_STATUS_OK; } - const uint32_t n_threads = MIN(octx->n_threads, nrows); - const uint32_t rows_per_thread = (nrows + n_threads - 1) / n_threads; + const uint32_t n_threads = octx->n_threads; + const uint32_t rows_per_thread = fastdiv(nrows + n_threads - 1, &octx->n_threads_div); struct argmax_context actx = { .octx = octx, diff --git a/ggml/src/ggml-hexagon/htp/sum-rows-ops.h b/ggml/src/ggml-hexagon/htp/sum-rows-ops.h new file mode 100644 index 000000000000..cc9ddd483913 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/sum-rows-ops.h @@ -0,0 +1,17 @@ +#ifndef HTP_SUM_ROWS_OPS_H +#define HTP_SUM_ROWS_OPS_H + +#include + +struct htp_sum_rows_kernel_params { + uint32_t n_threads; + uint32_t elems_per_thread; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_sum_rows_kernel_params) <= 128, "htp_sum_rows_kernel_params is too large for kernel_params blob"); +#else +_Static_assert(sizeof(struct htp_sum_rows_kernel_params) <= 128, "htp_sum_rows_kernel_params is too large for kernel_params blob"); +#endif + +#endif // HTP_SUM_ROWS_OPS_H diff --git a/ggml/src/ggml-hexagon/htp/unary-ops.c b/ggml/src/ggml-hexagon/htp/unary-ops.c index c557b0907daa..3b63ac674d73 100644 --- a/ggml/src/ggml-hexagon/htp/unary-ops.c +++ b/ggml/src/ggml-hexagon/htp/unary-ops.c @@ -109,18 +109,17 @@ static inline size_t unary_row_offset(uint32_t ir, return i1 * nb1 + i2 * nb2 + i3 * nb3; } -// Safe DMA block size from row `ir`: clamp to the tighter dim-1 slice -// boundary of src and dst so the nb1 stride stays valid for all rows. +// Safe DMA block size from row `ir`: clamp to the dim-1 slice boundary +// when non-contiguous so the nb1 stride stays valid for all rows. static inline uint32_t unary_block_size(uint32_t ir, uint32_t end_row, uint32_t block, - bool src_contig, - bool dst_contig, + bool contig, uint32_t ne1, const struct fastdiv_values * div_ne1) { uint32_t limit = MIN(block, end_row - ir); - if (!src_contig || !dst_contig) { + if (!contig) { const uint32_t slice_end = (fastdiv(ir, div_ne1) + 1) * ne1; limit = MIN(limit, slice_end - ir); } @@ -213,13 +212,15 @@ static void rms_norm_f32(const void * restrict src, const struct htp_unary_context * uctx) { htp_unary_op_preamble; float epsilon = 0.f; - memcpy(&epsilon, op_params, sizeof(float)); + float scale = 0.f; + memcpy(&epsilon, &op_params[0], sizeof(float)); + memcpy(&scale, &op_params[1], sizeof(float)); for (uint32_t ir = 0; ir < num_rows; ir++) { const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); - hvx_fast_rms_norm_f32((const uint8_t *) src_local, (uint8_t *) dst_local, ne0, epsilon); + hvx_fast_rms_norm_f32((const uint8_t *) src_local, (uint8_t *) dst_local, ne0, epsilon, scale); } } @@ -230,14 +231,16 @@ static void rms_norm_mul_f32(const void * restrict src, const struct htp_unary_context * uctx) { htp_unary_op_preamble; float epsilon = 0.f; - memcpy(&epsilon, op_params, sizeof(float)); + float scale = 0.f; + memcpy(&epsilon, &op_params[0], sizeof(float)); + memcpy(&scale, &op_params[1], sizeof(float)); for (uint32_t ir = 0; ir < num_rows; ir++) { const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); const uint8_t * restrict w_local = (const uint8_t *)weight + (uctx->broadcast_weight ? 0 : ir * uctx->src1_row_size_aligned); uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); - hvx_fast_rms_norm_mul_f32(src_local, w_local, dst_local, ne0, epsilon); + hvx_fast_rms_norm_mul_f32(src_local, w_local, dst_local, ne0, epsilon, scale); } } @@ -423,6 +426,34 @@ static void step_f16(const void * restrict src, } } +static void ceil_f16(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); + + hvx_ceil_f16_aa((uint8_t *) dst_local, (const uint8_t *) src_local, ne0); + } +} + +static void sgn_f16(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); + + hvx_sgn_f16_aa((uint8_t *) dst_local, (const uint8_t *) src_local, ne0); + } +} + static void l2_norm_f16(const void * restrict src, void * restrict dst, const uint32_t num_rows, @@ -617,10 +648,11 @@ static void tri_f32(const void * restrict src, const uint32_t nloe = ne0 % VLEN_FP32; const uint32_t ne01 = uctx->octx->src[0]->ne[1]; + const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; for (uint32_t b = 0; b < num_rows; b++) { const uint32_t abs_row = ir + b; - const uint32_t i01 = abs_row % ne01; + const uint32_t i01 = fastmodulo(abs_row, ne01, div_ne01); const HVX_Vector * restrict v_src = (const HVX_Vector *) ((const uint8_t *) src + b * src0_row_size_aligned); HVX_Vector * restrict v_dst = (HVX_Vector *) ((uint8_t *) dst + b * dst_row_size_aligned); @@ -690,22 +722,48 @@ static void tri_f32(const void * restrict src, } } +// softplus(x) = log(1 + exp(x)) +// Match CPU reference: return x for x > 20 to avoid overflow. +static inline void hvx_softplus_f32_aa(uint8_t * restrict dst, const uint8_t * restrict src, uint32_t n) { + const HVX_Vector * restrict v_src = (const HVX_Vector *) src; + HVX_Vector * restrict v_dst = (HVX_Vector *) dst; + + const HVX_Vector twenty = hvx_vec_splat_f32(20.0f); + const HVX_Vector one = hvx_vec_splat_f32(1.0f); + + const uint32_t nvec = n / VLEN_FP32; + const uint32_t nloe = n % VLEN_FP32; + + #pragma unroll(4) + for (uint32_t i = 0; i < nvec; i++) { + HVX_Vector x = v_src[i]; + HVX_VectorPred pred_gt20 = Q6_Q_vcmp_gt_VsfVsf(x, twenty); + HVX_Vector expx = hvx_vec_exp_f32(x); + HVX_Vector logv = hvx_vec_log_f32(hvx_vec_add_f32_f32(one, expx)); + v_dst[i] = Q6_V_vmux_QVV(pred_gt20, x, logv); + } + + if (nloe > 0) { + HVX_Vector x = v_src[nvec]; + HVX_VectorPred pred_gt20 = Q6_Q_vcmp_gt_VsfVsf(x, twenty); + HVX_Vector expx = hvx_vec_exp_f32(x); + HVX_Vector logv = hvx_vec_log_f32(hvx_vec_add_f32_f32(one, expx)); + HVX_Vector sp = Q6_V_vmux_QVV(pred_gt20, x, logv); + hvx_vec_store_a((void *) &v_dst[nvec], nloe * sizeof(float), sp); + } +} + static void softplus_f32(const void * restrict src, void * restrict dst, const uint32_t num_rows, const struct htp_unary_context * uctx) { htp_unary_op_preamble; - // softplus(x) = log(1 + exp(x)) - // Match CPU reference: ggml_compute_softplus_f32() in ggml-impl.h + for (uint32_t ir = 0; ir < num_rows; ir++) { - const float * restrict src_f = (const float *)((const uint8_t *)src + (ir * src0_row_size_aligned)); - float * restrict dst_f = (float *)((uint8_t *)dst + (ir * dst_row_size_aligned)); + const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); - for (uint32_t i = 0; i < ne0; i++) { - float x = src_f[i]; - // For x > 20: softplus(x) ~ x (avoids exp overflow) - dst_f[i] = (x > 20.0f) ? x : logf(1.0f + expf(x)); - } + hvx_softplus_f32_aa(dst_local, src_local, ne0); } } @@ -725,6 +783,143 @@ static void l2_norm_f32(const void * restrict src, } } +static inline HVX_VectorPair hvx_fwht_stage_pair(HVX_Vector v0, HVX_Vector v1, int32_t b) { + HVX_VectorPair p = Q6_W_vshuff_VVR(v1, v0, b); + HVX_Vector s = Q6_Vqf32_vadd_Vqf32Vqf32(Q6_V_lo_W(p), Q6_V_hi_W(p)); + HVX_Vector d = Q6_Vqf32_vsub_Vqf32Vqf32(Q6_V_lo_W(p), Q6_V_hi_W(p)); + return Q6_W_vshuff_VVR(d, s, b); +} + +static inline HVX_VectorPair hvx_fwht32_pair(HVX_Vector v0_sf, HVX_Vector v1_sf, HVX_Vector v_scale) { + HVX_Vector v0 = Q6_Vqf32_vmpy_VsfVsf(v0_sf, v_scale); + HVX_Vector v1 = Q6_Vqf32_vmpy_VsfVsf(v1_sf, v_scale); + HVX_VectorPair p; + p = hvx_fwht_stage_pair(v0, v1, 4); + p = hvx_fwht_stage_pair(Q6_V_lo_W(p), Q6_V_hi_W(p), 8); + p = hvx_fwht_stage_pair(Q6_V_lo_W(p), Q6_V_hi_W(p), 16); + p = hvx_fwht_stage_pair(Q6_V_lo_W(p), Q6_V_hi_W(p), 32); + p = hvx_fwht_stage_pair(Q6_V_lo_W(p), Q6_V_hi_W(p), 64); + return p; +} + +static inline void hvx_fwht_store32(HVX_Vector * restrict v_dst, HVX_VectorPair p) { + v_dst[0] = Q6_Vsf_equals_Vqf32(Q6_V_lo_W(p)); +} + +static inline void hvx_fwht_store64(HVX_Vector * restrict v_dst, HVX_VectorPair p) { + HVX_Vector u = Q6_V_lo_W(p); + HVX_Vector v = Q6_V_hi_W(p); + v_dst[0] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(u, v)); + v_dst[1] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vsub_Vqf32Vqf32(u, v)); +} + +static inline void hvx_fwht_tail_f32(HVX_Vector * restrict v_dst, uint32_t nvec) { + uint32_t len_vec = 2; + for (; len_vec * 2 < nvec; len_vec <<= 2) { + const uint32_t step = len_vec * 4; + for (uint32_t i = 0; i < nvec; i += step) { + for (uint32_t j = 0; j < len_vec; j++) { + HVX_Vector a0 = v_dst[i + j]; + HVX_Vector a1 = v_dst[i + j + len_vec]; + HVX_Vector a2 = v_dst[i + j + 2 * len_vec]; + HVX_Vector a3 = v_dst[i + j + 3 * len_vec]; + + HVX_Vector t0 = Q6_Vqf32_vadd_VsfVsf(a0, a1); + HVX_Vector t1 = Q6_Vqf32_vsub_VsfVsf(a0, a1); + HVX_Vector t2 = Q6_Vqf32_vadd_VsfVsf(a2, a3); + HVX_Vector t3 = Q6_Vqf32_vsub_VsfVsf(a2, a3); + + v_dst[i + j] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(t0, t2)); + v_dst[i + j + len_vec] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_Vqf32Vqf32(t1, t3)); + v_dst[i + j + 2 * len_vec] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vsub_Vqf32Vqf32(t0, t2)); + v_dst[i + j + 3 * len_vec] = Q6_Vsf_equals_Vqf32(Q6_Vqf32_vsub_Vqf32Vqf32(t1, t3)); + } + } + } + + if (len_vec < nvec) { + for (uint32_t i = 0; i < nvec; i += 2 * len_vec) { + for (uint32_t j = 0; j < len_vec; j++) { + HVX_Vector u = v_dst[i + j]; + HVX_Vector v = v_dst[i + len_vec + j]; + v_dst[i + j] = hvx_vec_add_f32_f32(u, v); + v_dst[i + len_vec + j] = hvx_vec_sub_f32_f32(u, v); + } + } + } +} + +static inline void hvx_fwht_row_f32(const uint8_t * restrict src, uint8_t * restrict dst, uint32_t n, HVX_Vector v_scale) { + const HVX_Vector * restrict v_src = (const HVX_Vector *) src; + HVX_Vector * restrict v_dst = (HVX_Vector *) dst; + const uint32_t nvec = n / VLEN_FP32; + + if (nvec == 1) { + HVX_VectorPair p = hvx_fwht32_pair(v_src[0], v_src[0], v_scale); + hvx_fwht_store32(v_dst, p); + return; + } + + for (uint32_t i = 0; i < nvec; i += 2) { + HVX_VectorPair p = hvx_fwht32_pair(v_src[i], v_src[i + 1], v_scale); + hvx_fwht_store64(&v_dst[i], p); + } + + hvx_fwht_tail_f32(v_dst, nvec); +} + +static inline void hvx_fwht_row_f16(const uint8_t * restrict src, uint8_t * restrict dst, uint32_t n, HVX_Vector v_scale) { + const HVX_Vector * restrict v_src = (const HVX_Vector *) src; + HVX_Vector * restrict v_dst = (HVX_Vector *) dst; + const uint32_t nvec = n / VLEN_FP32; + + if (nvec == 1) { + HVX_Vector v0 = Q6_V_lo_W(hvx_vec_f16_to_f32(v_src[0])); + HVX_VectorPair p = hvx_fwht32_pair(v0, v0, v_scale); + hvx_fwht_store32(v_dst, p); + return; + } + + const uint32_t nvec_f16 = n / VLEN_FP16; + for (uint32_t i = 0; i < nvec_f16; i++) { + HVX_VectorPair f32p = hvx_vec_f16_to_f32(v_src[i]); + HVX_VectorPair p = hvx_fwht32_pair(Q6_V_lo_W(f32p), Q6_V_hi_W(f32p), v_scale); + hvx_fwht_store64(&v_dst[2 * i], p); + } + + hvx_fwht_tail_f32(v_dst, nvec); +} + +static void hadamard_f32(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + const HVX_Vector v_scale = hvx_vec_splat_f32(1.0f / sqrtf((float) ne0)); + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_row = (const uint8_t *) src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_row = (uint8_t *) dst + (ir * dst_row_size_aligned); + + hvx_fwht_row_f32(src_row, dst_row, ne0, v_scale); + } +} + +static void hadamard_f16(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + const HVX_Vector v_scale = hvx_vec_splat_f32(1.0f / sqrtf((float) ne0)); + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_row = (const uint8_t *) src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_row = (uint8_t *) dst + (ir * dst_row_size_aligned); + + hvx_fwht_row_f16(src_row, dst_row, ne0, v_scale); + } +} + static void tanh_f32(const void * restrict src, void * restrict dst, const uint32_t num_rows, @@ -781,6 +976,34 @@ static void step_f32(const void * restrict src, } } +static void ceil_f32(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); + + hvx_ceil_f32_aa(dst_local, src_local, ne0); + } +} + +static void sgn_f32(const void * restrict src, + void * restrict dst, + const uint32_t num_rows, + const struct htp_unary_context * uctx) { + htp_unary_op_preamble; + + for (uint32_t ir = 0; ir < num_rows; ir++) { + const uint8_t * restrict src_local = (const uint8_t *)src + (ir * src0_row_size_aligned); + uint8_t * restrict dst_local = (uint8_t *)dst + (ir * dst_row_size_aligned); + + hvx_sgn_f32_aa(dst_local, src_local, ne0); + } +} + static void log_f32(const void * restrict src, void * restrict dst, const uint32_t num_rows, @@ -866,12 +1089,7 @@ static void tile_gelu_erf_f32(void * restrict dst, const void * restrict src, ui static void tile_softplus_f32(void * restrict dst, const void * restrict src, uint32_t tw, const struct htp_unary_context * uctx) { (void) uctx; - const float * restrict sf = (const float *) src; - float * restrict df = (float *) dst; - for (uint32_t i = 0; i < tw; i++) { - float x = sf[i]; - df[i] = (x > 20.0f) ? x : logf(1.0f + expf(x)); - } + hvx_softplus_f32_aa((uint8_t *) dst, (const uint8_t *) src, tw); } static void tile_tanh_f32(void * restrict dst, const void * restrict src, uint32_t tw, const struct htp_unary_context * uctx) { @@ -899,6 +1117,16 @@ static void tile_step_f32(void * restrict dst, const void * restrict src, uint32 hvx_step_f32_aa((uint8_t *) dst, (const uint8_t *) src, tw); } +static void tile_ceil_f32(void * restrict dst, const void * restrict src, uint32_t tw, const struct htp_unary_context * uctx) { + (void) uctx; + hvx_ceil_f32_aa((uint8_t *) dst, (const uint8_t *) src, tw); +} + +static void tile_sgn_f32(void * restrict dst, const void * restrict src, uint32_t tw, const struct htp_unary_context * uctx) { + (void) uctx; + hvx_sgn_f32_aa((uint8_t *) dst, (const uint8_t *) src, tw); +} + static void tri_apply_tile_f32(const void * restrict src, void * restrict dst, uint32_t tile_elems, uint32_t col_start, uint32_t i01, uint32_t ne0, int32_t ttype) { @@ -1005,35 +1233,23 @@ static void unary_thread_row_block(unsigned int nth, unsigned int ith, void * da const size_t src0_vtcm_half_size = uctx->src0_vtcm_half_size; const size_t dst_vtcm_half_size = uctx->dst_vtcm_half_size; - const bool src0_contig = (nb02 == (size_t)ne01 * nb01) && - (nb03 == (size_t)ne02 * nb02); - const bool dst_contig = (nb2 == (size_t)ne1 * nb1) && - (nb3 == (size_t)ne2 * nb2); + const bool src0_contig = uctx->kparams->src0_contig; + const uint32_t BLOCK = uctx->block; const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; const struct fastdiv_values * div_ne02 = &uctx->kparams->div_ne02; const struct fastdiv_values * div_ne012 = &uctx->kparams->div_ne012; - const uint32_t src0_max_block = src0_contig ? uctx->block : MIN((uint32_t)uctx->block, ne01); - const uint32_t dst_max_block = dst_contig ? uctx->block : MIN((uint32_t)uctx->block, ne1); - const uint32_t BLOCK = MIN(src0_max_block, dst_max_block); - if (BLOCK == 0) { - FARF(ERROR, "unary-row-block : current VTCM reservation %zu is too small, needed at least %zu\n", - uctx->vtcm_src0_size_per_thread, src0_row_size_aligned); - return; - } - dma_queue * dma_q = octx->ctx->dma[ith]; for (uint32_t ir = src0_start_row, vtcm_idx = 0; ir < src0_end_row && vtcm_idx < 2; vtcm_idx++) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, dst_contig, - ne01, div_ne01); + const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, ne01, div_ne01); dma_queue_push(dma_q, dma_make_data(data_dst, dst_vtcm_data + (vtcm_idx * dst_vtcm_half_size)), nb1, dst_row_size_aligned, dst_data_row_size, 0); - const size_t src0_off = src0_contig ? (ir * nb01) : + const size_t src0_off = src0_contig ? ((size_t) ir * nb01) : unary_row_offset(ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); dma_queue_push(dma_q, dma_make_data(src0_vtcm_data + (vtcm_idx * src0_vtcm_half_size), data_src + src0_off), @@ -1045,8 +1261,7 @@ static void unary_thread_row_block(unsigned int nth, unsigned int ith, void * da unary_compute_fn_t compute = (unary_compute_fn_t) uctx->compute; for (uint32_t ir = src0_start_row; ir < src0_end_row; ) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, dst_contig, - ne01, div_ne01); + const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, ne01, div_ne01); void * dst_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).src; void * src0_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).dst; @@ -1055,8 +1270,7 @@ static void unary_thread_row_block(unsigned int nth, unsigned int ith, void * da compute(src0_vtcm, dst_vtcm, block_size, uctx); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir); - const size_t dst_off = dst_contig ? (ir * nb1) : - unary_row_offset(ir, ne1, ne2, div_ne01, div_ne02, div_ne012, nb1, nb2, nb3); + const size_t dst_off = (size_t) ir * nb1; dma_queue_push(dma_q, dma_make_data(data_dst + dst_off, dst_vtcm), nb1, dst_row_size_aligned, dst_data_row_size, block_size); @@ -1064,12 +1278,12 @@ static void unary_thread_row_block(unsigned int nth, unsigned int ith, void * da const uint32_t next_ir = ir + block_size; if (next_ir < src0_end_row) { const uint32_t next_block_size = unary_block_size(next_ir, src0_end_row, BLOCK, src0_contig, - dst_contig, ne01, div_ne01); + ne01, div_ne01); const uint32_t pref_ir = next_ir + next_block_size; if (pref_ir < src0_end_row) { const uint32_t pref_block_size = unary_block_size(pref_ir, src0_end_row, BLOCK, src0_contig, - dst_contig, ne01, div_ne01); - const size_t src0_pref_off = src0_contig ? (pref_ir * nb01) : + ne01, div_ne01); + const size_t src0_pref_off = src0_contig ? ((size_t) pref_ir * nb01) : unary_row_offset(pref_ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); dma_queue_push(dma_q, dma_make_data(src0_vtcm, data_src + src0_pref_off), @@ -1115,10 +1329,6 @@ static void unary_thread_rms_norm_mul_f32(unsigned int nth, unsigned int ith, vo const uint32_t nb11 = src1->nb[1]; const uint32_t nb12 = src1->nb[2]; const uint32_t nb13 = src1->nb[3]; - const uint32_t nb11_bc = (src1->ne[1] > 1) ? nb11 : 0; - const uint32_t nb12_bc = (src1->ne[2] > 1) ? nb12 : 0; - const uint32_t nb13_bc = (src1->ne[3] > 1) ? nb13 : 0; - const bool src1_contig = ((nb12 == (size_t)ne01 * nb11) && (nb13 == (size_t)ne02 * nb12)); uint8_t * src0_vtcm_data = uctx->vtcm_src0 + (ith * uctx->vtcm_src0_size_per_thread); uint8_t * src1_vtcm_data = uctx->vtcm_src1 ? (uctx->vtcm_src1 + (ith * uctx->vtcm_src1_size_per_thread)) : NULL; @@ -1128,28 +1338,15 @@ static void unary_thread_rms_norm_mul_f32(unsigned int nth, unsigned int ith, vo const size_t src1_vtcm_half_size = uctx->src1_vtcm_half_size; const size_t dst_vtcm_half_size = uctx->dst_vtcm_half_size; - const bool src0_contig = (nb02 == (size_t)ne01 * nb01) && - (nb03 == (size_t)ne02 * nb02); - const bool dst_contig = (nb2 == (size_t)ne1 * nb1) && - (nb3 == (size_t)ne2 * nb2); + const bool src0_contig = uctx->kparams->src0_contig; + const bool src1_contig = uctx->kparams->src1_contig; + const bool block_contig = src0_contig && src1_contig; + const uint32_t BLOCK = uctx->block; const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; const struct fastdiv_values * div_ne02 = &uctx->kparams->div_ne02; const struct fastdiv_values * div_ne012 = &uctx->kparams->div_ne012; - const bool src1_needs_row_clip = !uctx->broadcast_weight && !src1_contig; - const bool block_src0_contig = src0_contig && !src1_needs_row_clip; - const bool block_dst_contig = dst_contig && !src1_needs_row_clip; - - const uint32_t src0_max_block = block_src0_contig ? uctx->block : MIN((uint32_t)uctx->block, ne01); - const uint32_t dst_max_block = block_dst_contig ? uctx->block : MIN((uint32_t)uctx->block, ne1); - const uint32_t BLOCK = MIN(src0_max_block, dst_max_block); - if (BLOCK == 0) { - FARF(ERROR, "unary-rms-norm-mul : current VTCM reservation %zu is too small, needed at least %zu\n", - uctx->vtcm_src0_size_per_thread, src0_row_size_aligned); - return; - } - dma_queue * dma_q = octx->ctx->dma[ith]; if (uctx->broadcast_weight) { @@ -1159,22 +1356,21 @@ static void unary_thread_rms_norm_mul_f32(unsigned int nth, unsigned int ith, vo } for (uint32_t ir = src0_start_row, vtcm_idx = 0; ir < src0_end_row && vtcm_idx < 2; vtcm_idx++) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, block_src0_contig, block_dst_contig, - ne01, div_ne01); + const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, block_contig, ne01, div_ne01); dma_queue_push(dma_q, dma_make_data(data_dst, dst_vtcm_data + (vtcm_idx * dst_vtcm_half_size)), nb1, dst_row_size_aligned, dst_data_row_size, 0); - const size_t src0_off = src0_contig ? (ir * nb01) : + const size_t src0_off = src0_contig ? ((size_t) ir * nb01) : unary_row_offset(ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); dma_queue_push(dma_q, dma_make_data(src0_vtcm_data + (vtcm_idx * src0_vtcm_half_size), data_src + src0_off), src0_row_size_aligned, nb01, src0_data_row_size, block_size); if (!uctx->broadcast_weight) { - const size_t src1_off = src1_contig ? (ir * nb11) : - unary_row_offset(ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb11_bc, nb12_bc, nb13_bc); + const size_t src1_off = src1_contig ? ((size_t) ir * nb11) : + unary_row_offset(ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb11, nb12, nb13); dma_queue_push(dma_q, dma_make_data(src1_vtcm_data + (vtcm_idx * src1_vtcm_half_size), data_src1 + src1_off), uctx->src1_row_size_aligned, nb11, uctx->src1_data_row_size, block_size); @@ -1186,8 +1382,7 @@ static void unary_thread_rms_norm_mul_f32(unsigned int nth, unsigned int ith, vo unary_rms_norm_mul_compute_fn_t compute = (unary_rms_norm_mul_compute_fn_t) uctx->compute; for (uint32_t ir = src0_start_row; ir < src0_end_row; ) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, block_src0_contig, block_dst_contig, - ne01, div_ne01); + const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, block_contig, ne01, div_ne01); void * dst_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).src; void * src0_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).dst; @@ -1201,30 +1396,28 @@ static void unary_thread_rms_norm_mul_f32(unsigned int nth, unsigned int ith, vo compute(src0_vtcm, w, dst_vtcm, block_size, uctx); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir); - const size_t dst_off = dst_contig ? (ir * nb1) : - unary_row_offset(ir, ne1, ne2, div_ne01, div_ne02, div_ne012, nb1, nb2, nb3); + const size_t dst_off = (size_t) ir * nb1; dma_queue_push(dma_q, dma_make_data(data_dst + dst_off, dst_vtcm), nb1, dst_row_size_aligned, dst_data_row_size, block_size); const uint32_t next_ir = ir + block_size; if (next_ir < src0_end_row) { - const uint32_t next_block_size = unary_block_size(next_ir, src0_end_row, BLOCK, block_src0_contig, - block_dst_contig, ne01, div_ne01); + const uint32_t next_block_size = unary_block_size(next_ir, src0_end_row, BLOCK, block_contig, + ne01, div_ne01); const uint32_t pref_ir = next_ir + next_block_size; if (pref_ir < src0_end_row) { - const uint32_t pref_block_size = unary_block_size(pref_ir, src0_end_row, BLOCK, block_src0_contig, - block_dst_contig, ne01, div_ne01); - const size_t src0_pref_off = src0_contig ? (pref_ir * nb01) : + const uint32_t pref_block_size = unary_block_size(pref_ir, src0_end_row, BLOCK, block_contig, + ne01, div_ne01); + const size_t src0_pref_off = src0_contig ? ((size_t) pref_ir * nb01) : unary_row_offset(pref_ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); dma_queue_push(dma_q, dma_make_data(src0_vtcm, data_src + src0_pref_off), src0_row_size_aligned, nb01, src0_data_row_size, pref_block_size); if (!uctx->broadcast_weight) { - const size_t src1_pref_off = src1_contig ? (pref_ir * nb11) : - unary_row_offset(pref_ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb11_bc, nb12_bc, - nb13_bc); + const size_t src1_pref_off = src1_contig ? ((size_t) pref_ir * nb11) : + unary_row_offset(pref_ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb11, nb12, nb13); dma_queue_push(dma_q, dma_make_data(src1_vtcm, data_src1 + src1_pref_off), uctx->src1_row_size_aligned, nb11, uctx->src1_data_row_size, pref_block_size); @@ -1270,37 +1463,18 @@ static void unary_thread_tri_f32(unsigned int nth, unsigned int ith, void * data const size_t src0_vtcm_half_size = uctx->src0_vtcm_half_size; const size_t dst_vtcm_half_size = uctx->dst_vtcm_half_size; - - const bool src0_contig = (nb02 == (size_t)ne01 * nb01) && - (nb03 == (size_t)ne02 * nb02); - const bool dst_contig = (nb2 == (size_t)ne1 * nb1) && - (nb3 == (size_t)ne2 * nb2); - - const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; - const struct fastdiv_values * div_ne02 = &uctx->kparams->div_ne02; - const struct fastdiv_values * div_ne012 = &uctx->kparams->div_ne012; - - const uint32_t src0_max_block = src0_contig ? uctx->block : MIN((uint32_t)uctx->block, ne01); - const uint32_t dst_max_block = dst_contig ? uctx->block : MIN((uint32_t)uctx->block, ne1); - const uint32_t BLOCK = MIN(src0_max_block, dst_max_block); - if (BLOCK == 0) { - FARF(ERROR, "unary-tri : current VTCM reservation %zu is too small, needed at least %zu\n", - uctx->vtcm_src0_size_per_thread, src0_row_size_aligned); - return; - } + const uint32_t BLOCK = uctx->block; dma_queue * dma_q = octx->ctx->dma[ith]; for (uint32_t ir = src0_start_row, vtcm_idx = 0; ir < src0_end_row && vtcm_idx < 2; vtcm_idx++) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, dst_contig, - ne01, div_ne01); + const uint32_t block_size = MIN(BLOCK, src0_end_row - ir); dma_queue_push(dma_q, dma_make_data(data_dst, dst_vtcm_data + (vtcm_idx * dst_vtcm_half_size)), nb1, dst_row_size_aligned, dst_data_row_size, 0); - const size_t src0_off = src0_contig ? (ir * nb01) : - unary_row_offset(ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); + const size_t src0_off = (size_t) ir * nb01; dma_queue_push(dma_q, dma_make_data(src0_vtcm_data + (vtcm_idx * src0_vtcm_half_size), data_src + src0_off), src0_row_size_aligned, nb01, src0_data_row_size, block_size); @@ -1311,8 +1485,7 @@ static void unary_thread_tri_f32(unsigned int nth, unsigned int ith, void * data unary_tri_compute_fn_t compute = (unary_tri_compute_fn_t) uctx->compute; for (uint32_t ir = src0_start_row; ir < src0_end_row; ) { - const uint32_t block_size = unary_block_size(ir, src0_end_row, BLOCK, src0_contig, dst_contig, - ne01, div_ne01); + const uint32_t block_size = MIN(BLOCK, src0_end_row - ir); void * dst_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).src; void * src0_vtcm = (void *) (uintptr_t) dma_queue_pop(dma_q).dst; @@ -1321,22 +1494,18 @@ static void unary_thread_tri_f32(unsigned int nth, unsigned int ith, void * data compute(src0_vtcm, dst_vtcm, block_size, ir, uctx); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, ir); - const size_t dst_off = dst_contig ? (ir * nb1) : - unary_row_offset(ir, ne1, ne2, div_ne01, div_ne02, div_ne012, nb1, nb2, nb3); + const size_t dst_off = (size_t) ir * nb1; dma_queue_push(dma_q, dma_make_data(data_dst + dst_off, dst_vtcm), nb1, dst_row_size_aligned, dst_data_row_size, block_size); const uint32_t next_ir = ir + block_size; if (next_ir < src0_end_row) { - const uint32_t next_block_size = unary_block_size(next_ir, src0_end_row, BLOCK, src0_contig, - dst_contig, ne01, div_ne01); + const uint32_t next_block_size = MIN(BLOCK, src0_end_row - next_ir); const uint32_t pref_ir = next_ir + next_block_size; if (pref_ir < src0_end_row) { - const uint32_t pref_block_size = unary_block_size(pref_ir, src0_end_row, BLOCK, src0_contig, - dst_contig, ne01, div_ne01); - const size_t src0_pref_off = src0_contig ? (pref_ir * nb01) : - unary_row_offset(pref_ir, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03); + const uint32_t pref_block_size = MIN(BLOCK, src0_end_row - pref_ir); + const size_t src0_pref_off = (size_t) pref_ir * nb01; dma_queue_push(dma_q, dma_make_data(src0_vtcm, data_src + src0_pref_off), src0_row_size_aligned, nb01, src0_data_row_size, pref_block_size); @@ -1386,21 +1555,17 @@ static void unary_thread_tiled(unsigned int nth, unsigned int ith, void * data) const struct fastdiv_values * div_ne012 = &uctx->kparams->div_ne012; const struct fastdiv_values * div_tpr = &uctx->kparams->div_tpr; - const uint32_t tiles_per_row = (ne0 + col_tile - 1) / col_tile; - - const bool src0_contig = (nb02 == (size_t)ne01 * nb01) && - (nb03 == (size_t)ne02 * nb02); - const bool dst_contig = (nb2 == (size_t)ne1 * nb1) && - (nb3 == (size_t)ne2 * nb2); + const uint32_t tiles_per_row = uctx->kparams->tiles_per_row; + const bool src0_contig = uctx->kparams->src0_contig; const uint32_t total_tiles = (src0_end_row - src0_start_row) * tiles_per_row; for (uint32_t t = 0, vtcm_idx = 0; t < total_tiles && vtcm_idx < 2; t++, vtcm_idx++) { - const uint32_t row = src0_start_row + t / tiles_per_row; - const uint32_t col = (t % tiles_per_row) * col_tile; + const uint32_t row = src0_start_row + fastdiv(t, div_tpr); + const uint32_t col = fastmodulo(t, tiles_per_row, div_tpr) * col_tile; const uint32_t tw = MIN(col_tile, ne0 - col); const size_t tb = (size_t) tw * sizeof(float); - const size_t soff = (src0_contig ? (row * nb01) : + const size_t soff = (src0_contig ? ((size_t) row * nb01) : unary_row_offset(row, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03)) + (size_t) col * sizeof(float); @@ -1428,9 +1593,7 @@ static void unary_thread_tiled(unsigned int nth, unsigned int ith, void * data) compute(dst_vtcm, src_vtcm, tw, uctx); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, t); - const size_t doff = (dst_contig ? (row * nb1) : - unary_row_offset(row, ne1, ne2, div_ne01, div_ne02, div_ne012, nb1, nb2, nb3)) + - (size_t) col * sizeof(float); + const size_t doff = (size_t) row * nb1 + (size_t) col * sizeof(float); const size_t tb = (size_t) tw * sizeof(float); dma_queue_push(dma_q, dma_make_data(data_dst + doff, dst_vtcm), tb, tb, tb, 1); @@ -1438,7 +1601,7 @@ static void unary_thread_tiled(unsigned int nth, unsigned int ith, void * data) if (pt < total_tiles) { const uint32_t ptw = MIN(col_tile, ne0 - pcol); const size_t ptb = (size_t) ptw * sizeof(float); - const size_t psoff = (src0_contig ? (prow * nb01) : + const size_t psoff = (src0_contig ? ((size_t) prow * nb01) : unary_row_offset(prow, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03)) + (size_t) pcol * sizeof(float); @@ -1499,29 +1662,20 @@ static void unary_thread_tiled_tri_f32(unsigned int nth, unsigned int ith, void dma_queue * dma_q = octx->ctx->dma[ith]; - const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; - const struct fastdiv_values * div_ne02 = &uctx->kparams->div_ne02; - const struct fastdiv_values * div_ne012 = &uctx->kparams->div_ne012; - const struct fastdiv_values * div_tpr = &uctx->kparams->div_tpr; + const struct fastdiv_values * div_ne01 = &uctx->kparams->div_ne01; + const struct fastdiv_values * div_tpr = &uctx->kparams->div_tpr; - const uint32_t tiles_per_row = (ne0 + col_tile - 1) / col_tile; + const uint32_t tiles_per_row = uctx->kparams->tiles_per_row; const int32_t tri_ttype = op_params[0]; - const bool src0_contig = (nb02 == (size_t)ne01 * nb01) && - (nb03 == (size_t)ne02 * nb02); - const bool dst_contig = (nb2 == (size_t)ne1 * nb1) && - (nb3 == (size_t)ne2 * nb2); - const uint32_t total_tiles = (src0_end_row - src0_start_row) * tiles_per_row; for (uint32_t t = 0, vtcm_idx = 0; t < total_tiles && vtcm_idx < 2; t++, vtcm_idx++) { - const uint32_t row = src0_start_row + t / tiles_per_row; - const uint32_t col = (t % tiles_per_row) * col_tile; + const uint32_t row = src0_start_row + fastdiv(t, div_tpr); + const uint32_t col = fastmodulo(t, tiles_per_row, div_tpr) * col_tile; const uint32_t tw = MIN(col_tile, ne0 - col); const size_t tb = (size_t) tw * sizeof(float); - const size_t soff = (src0_contig ? (row * nb01) : - unary_row_offset(row, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, nb03)) + - (size_t) col * sizeof(float); + const size_t soff = (size_t) row * nb01 + (size_t) col * sizeof(float); dma_queue_push(dma_q, dma_make_data(data_dst, dst_vtcm_data + (vtcm_idx * dst_half)), 0, 0, 0, 0); dma_queue_push(dma_q, dma_make_data(src0_vtcm_data + (vtcm_idx * src0_half), data_src + soff), tb, tb, tb, 1); @@ -1548,20 +1702,15 @@ static void unary_thread_tiled_tri_f32(unsigned int nth, unsigned int ith, void compute(src_vtcm, dst_vtcm, tw, col, i01, ne0, tri_ttype); htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, t); - const size_t doff = (dst_contig ? (row * nb1) : - unary_row_offset(row, ne1, ne2, div_ne01, div_ne02, div_ne012, nb1, nb2, nb3)) + - (size_t) col * sizeof(float); + const size_t doff = (size_t) row * nb1 + (size_t) col * sizeof(float); const size_t tb = (size_t) tw * sizeof(float); dma_queue_push(dma_q, dma_make_data(data_dst + doff, dst_vtcm), tb, tb, tb, 1); const uint32_t pt = t + 2; if (pt < total_tiles) { - const uint32_t ptw = MIN(col_tile, ne0 - pcol); - const size_t ptb = (size_t) ptw * sizeof(float); - const size_t psoff = (src0_contig ? (prow * nb01) : - unary_row_offset(prow, ne01, ne02, div_ne01, div_ne02, div_ne012, nb01, nb02, - nb03)) + - (size_t) pcol * sizeof(float); + const uint32_t ptw = MIN(col_tile, ne0 - pcol); + const size_t ptb = (size_t) ptw * sizeof(float); + const size_t psoff = (size_t) prow * nb01 + (size_t) pcol * sizeof(float); dma_queue_push(dma_q, dma_make_data(src_vtcm, data_src + psoff), ptb, ptb, ptb, 1); } @@ -1621,51 +1770,34 @@ static int execute_op_unary(struct htp_ops_context * octx) { case HTP_OP_UNARY_LOG: op_type = is_f16 ? "log-f16" : "log-f32"; break; case HTP_OP_UNARY_RELU: op_type = "relu-f32"; break; case HTP_OP_UNARY_STEP: op_type = is_f16 ? "step-f16" : "step-f32"; break; + case HTP_OP_UNARY_CEIL: op_type = is_f16 ? "ceil-f16" : "ceil-f32"; break; + case HTP_OP_UNARY_SGN: op_type = is_f16 ? "sgn-f16" : "sgn-f32"; break; case HTP_OP_L2_NORM: op_type = is_f16 ? "l2norm-f16" : "l2norm-f32"; break; case HTP_OP_TRI: op_type = "tri-f32"; break; + case HTP_OP_HADAMARD: op_type = is_f16 ? "hadamard-f16" : "hadamard-f32"; break; default: FARF(ERROR, "Unsupported unary Op %u\n", octx->op); return HTP_STATUS_NO_SUPPORT; } - // F16 only has row-block kernels for this subset of ops (see the dispatch switch - // below) - reject everything else up front, before touching kparams/VTCM. - if (is_f16) { - switch (octx->op) { - case HTP_OP_NORM: - case HTP_OP_RMS_NORM: - case HTP_OP_SCALE: - case HTP_OP_CLAMP: - case HTP_OP_SQR: - case HTP_OP_SQRT: - case HTP_OP_L2_NORM: - case HTP_OP_UNARY_ABS: - case HTP_OP_UNARY_LOG: - case HTP_OP_UNARY_STEP: - break; - default: - FARF(ERROR, "unary-%s: not supported for F16\n", op_type); - return HTP_STATUS_NO_SUPPORT; - } - } - const struct htp_unary_kernel_params * kparams = (const struct htp_unary_kernel_params *) octx->kernel_params; if (!htp_ops_context_set_n_threads(octx, kparams->n_threads)) { return HTP_STATUS_INVAL_PARAMS; } + const size_t src0_elem_size = is_f16 ? sizeof(_Float16) : sizeof(float); + const size_t dst_elem_size = (dst->type == HTP_TYPE_F16) ? sizeof(_Float16) : sizeof(float); const uint32_t src0_nrows = src0->ne[1] * src0->ne[2] * src0->ne[3]; - const size_t elem_size = is_f16 ? sizeof(_Float16) : sizeof(float); - const size_t src0_data_row_size = src0->ne[0] * elem_size; - const size_t dst_data_row_size = dst->ne[0] * elem_size; + const size_t src0_data_row_size = src0->ne[0] * src0_elem_size; + const size_t dst_data_row_size = dst->ne[0] * dst_elem_size; uint32_t row_start = 0; uint32_t nrows = src0_nrows; if (octx->ctx->mdev.count > 1) { uint32_t rows_per_chunk = 0; - htp_tensor_mdev_rows_per_chunk(dst, (uint32_t) elem_size, (uint32_t) dst_data_row_size, &rows_per_chunk); + htp_tensor_mdev_rows_per_chunk(dst, (uint32_t) dst_elem_size, (uint32_t) dst_data_row_size, &rows_per_chunk); const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition(src0_nrows, rows_per_chunk, octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); row_start = range.start; nrows = range.count; @@ -1677,15 +1809,11 @@ static int execute_op_unary(struct htp_ops_context * octx) { const uint32_t n_threads = octx->n_threads; - const size_t src0_row_size_aligned = kparams->src0_row_size_aligned; - const size_t dst_row_size_aligned = kparams->dst_row_size_aligned; - - // Always 0 for F16 - htp_unary_vtcm_layout_build() keeps F16 on the row-block path, + // Always 0 for F16 - htp_unary_solve_layout() keeps F16 on the row-block path, // since only F32 has unary_task_f32_tiled_* kernels. const uint32_t col_tile = kparams->col_tile; size_t src1_data_row_size = 0; - size_t src1_row_size_aligned = kparams->src1_row_size_aligned; bool broadcast_weight = kparams->broadcast_weight; const struct htp_tensor * src1 = NULL; @@ -1696,8 +1824,8 @@ static int execute_op_unary(struct htp_ops_context * octx) { src1_data_row_size = src1->ne[0] * sizeof(float); } - if (octx->ctx->vtcm_size < (size_t)kparams->vtcm_size) { - FARF(ERROR, "unary-%s : current VTCM reservation %zu is too small, needed %zu\n", op_type, octx->ctx->vtcm_size, (size_t)kparams->vtcm_size); + if ((!col_tile && kparams->block == 0) || octx->ctx->vtcm_size < (size_t) kparams->vtcm_size) { + FARF(ERROR, "unary-%s : current VTCM reservation %zu is too small, needed %zu\n", op_type, octx->ctx->vtcm_size, (size_t) kparams->vtcm_size); return HTP_STATUS_VTCM_TOO_SMALL; } @@ -1705,9 +1833,13 @@ static int execute_op_unary(struct htp_ops_context * octx) { octx->src1_spad.src = NULL; octx->dst_spad.src = NULL; - FARF(HIGH, "%s: (%ux%ux%ux%u) -> (%ux%ux%ux%u) : src0-vtcm-size %u src1-vtcm-size %u dst-vtcm-size %u\n", op_type, + struct htp_unary_vtcm_layout L; + htp_unary_vtcm_layout_build(&L, octx->op, src0_data_row_size, dst_data_row_size, src1_data_row_size, + src0_elem_size, col_tile, kparams->block, broadcast_weight, kparams->n_threads); + + FARF(HIGH, "%s: (%ux%ux%ux%u) -> (%ux%ux%ux%u) : src0-vtcm-size %zu src1-vtcm-size %zu dst-vtcm-size %zu\n", op_type, src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], - kparams->vtcm_src0_size, kparams->vtcm_src1_size, kparams->vtcm_dst_size); + L.src0_bytes * n_threads, L.src1_bytes * n_threads, L.dst_bytes * n_threads); uint8_t * const base = (uint8_t *) octx->ctx->vtcm_base; struct htp_unary_context uctx = { @@ -1725,26 +1857,26 @@ static int execute_op_unary(struct htp_ops_context * octx) { .src1_data_row_size = src1_data_row_size, .dst_data_row_size = dst_data_row_size, - .src0_row_size_aligned = src0_row_size_aligned, - .src1_row_size_aligned = src1_row_size_aligned, - .dst_row_size_aligned = dst_row_size_aligned, + .src0_row_size_aligned = L.src0_row_size_aligned, + .src1_row_size_aligned = L.src1_row_size_aligned, + .dst_row_size_aligned = L.dst_row_size_aligned, - .src0_vtcm_half_size = kparams->vtcm_src0_size_per_thread / 2, - .src1_vtcm_half_size = (octx->op == HTP_OP_RMS_NORM_MUL) ? (kparams->vtcm_src1_size_per_thread / (broadcast_weight ? 1 : 2)) : 0, - .dst_vtcm_half_size = kparams->vtcm_dst_size_per_thread / 2, + .src0_vtcm_half_size = L.src0_bytes >> 1, + .src1_vtcm_half_size = (octx->op == HTP_OP_RMS_NORM_MUL) ? (L.src1_bytes >> (broadcast_weight ? 0 : 1)) : 0, + .dst_vtcm_half_size = L.dst_bytes >> 1, .block = kparams->block, .nc = src0->ne[0], .col_tile = col_tile, .broadcast_weight = broadcast_weight, - .vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, 0), - .vtcm_src1 = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, base, kparams->vtcm_src0_size, kparams->vtcm_src1_size > 0), - .vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, kparams->vtcm_src0_size + kparams->vtcm_src1_size), + .vtcm_src0 = VTCM_LAYOUT_PTR(uint8_t, base, L.off_src0), + .vtcm_src1 = VTCM_LAYOUT_PTR_OPTIONAL(uint8_t, base, L.off_src1, L.src1_bytes > 0), + .vtcm_dst = VTCM_LAYOUT_PTR(uint8_t, base, L.off_dst), - .vtcm_src0_size_per_thread = kparams->vtcm_src0_size_per_thread, - .vtcm_src1_size_per_thread = kparams->vtcm_src1_size_per_thread, - .vtcm_dst_size_per_thread = kparams->vtcm_dst_size_per_thread, + .vtcm_src0_size_per_thread = L.src0_bytes, + .vtcm_src1_size_per_thread = L.src1_bytes, + .vtcm_dst_size_per_thread = L.dst_bytes, }; FARF(HIGH, "%s: %s mode (col_tile %u)\n", op_type, col_tile ? "tiled" : "row-block", col_tile); @@ -1773,6 +1905,8 @@ static int execute_op_unary(struct htp_ops_context * octx) { case HTP_OP_UNARY_LOG: compute_func = (void *) tile_log_f32; break; case HTP_OP_UNARY_RELU: compute_func = (void *) tile_relu_f32; break; case HTP_OP_UNARY_STEP: compute_func = (void *) tile_step_f32; break; + case HTP_OP_UNARY_CEIL: compute_func = (void *) tile_ceil_f32; break; + case HTP_OP_UNARY_SGN: compute_func = (void *) tile_sgn_f32; break; case HTP_OP_TRI: task_func = unary_thread_tiled_tri_f32; compute_func = (void *) tri_apply_tile_f32; @@ -1792,6 +1926,9 @@ static int execute_op_unary(struct htp_ops_context * octx) { case HTP_OP_UNARY_ABS: compute_func = (void *) abs_f16; break; case HTP_OP_UNARY_LOG: compute_func = (void *) log_f16; break; case HTP_OP_UNARY_STEP: compute_func = (void *) step_f16; break; + case HTP_OP_UNARY_CEIL: compute_func = (void *) ceil_f16; break; + case HTP_OP_UNARY_SGN: compute_func = (void *) sgn_f16; break; + case HTP_OP_HADAMARD: compute_func = (void *) hadamard_f16; break; default: break; } } else { @@ -1821,7 +1958,10 @@ static int execute_op_unary(struct htp_ops_context * octx) { case HTP_OP_UNARY_LOG: compute_func = (void *) log_f32; break; case HTP_OP_UNARY_RELU: compute_func = (void *) relu_f32; break; case HTP_OP_UNARY_STEP: compute_func = (void *) step_f32; break; + case HTP_OP_UNARY_CEIL: compute_func = (void *) ceil_f32; break; + case HTP_OP_UNARY_SGN: compute_func = (void *) sgn_f32; break; case HTP_OP_L2_NORM: compute_func = (void *) l2_norm_f32; break; + case HTP_OP_HADAMARD: compute_func = (void *) hadamard_f32; break; case HTP_OP_TRI: task_func = unary_thread_tri_f32; compute_func = (void *) tri_f32; diff --git a/ggml/src/ggml-hexagon/htp/unary-ops.h b/ggml/src/ggml-hexagon/htp/unary-ops.h index 7e5779e5afb7..713e40d50b75 100644 --- a/ggml/src/ggml-hexagon/htp/unary-ops.h +++ b/ggml/src/ggml-hexagon/htp/unary-ops.h @@ -2,29 +2,22 @@ #define HTP_UNARY_OPS_H #include "hex-common.h" +#include "hex-fastdiv.h" #include "htp-ops.h" +#include "htp-vtcm.h" // Op-specific struct for precomputed unary params struct htp_unary_kernel_params { uint32_t n_threads; uint32_t col_tile; - uint32_t vtcm_row_per_thread; uint32_t block; uint32_t broadcast_weight; - uint32_t vtcm_src0_size_per_thread; - uint32_t vtcm_src1_size_per_thread; - uint32_t vtcm_dst_size_per_thread; - - uint32_t vtcm_src0_size; - uint32_t vtcm_src1_size; - uint32_t vtcm_dst_size; - - uint32_t src0_row_size_aligned; - uint32_t src1_row_size_aligned; - uint32_t dst_row_size_aligned; + uint32_t src0_contig; + uint32_t src1_contig; uint32_t vtcm_size; + uint32_t tiles_per_row; // Fastdiv helpers struct fastdiv_values div_ne01; @@ -62,31 +55,94 @@ static inline bool htp_op_is_unary(uint32_t opcode) { case HTP_OP_UNARY_LOG: case HTP_OP_UNARY_RELU: case HTP_OP_UNARY_STEP: + case HTP_OP_UNARY_CEIL: + case HTP_OP_UNARY_SGN: case HTP_OP_L2_NORM: case HTP_OP_TRI: + case HTP_OP_HADAMARD: return true; default: return false; } } +static inline bool htp_unary_is_elementwise(uint32_t opcode) { + if (!htp_op_is_unary(opcode)) { + return false; + } + switch (opcode) { + case HTP_OP_NORM: + case HTP_OP_RMS_NORM: + case HTP_OP_RMS_NORM_MUL: + case HTP_OP_L2_NORM: + case HTP_OP_HADAMARD: + case HTP_OP_TRI: + return false; + default: + return true; + } +} + struct htp_unary_vtcm_layout { size_t total_bytes; size_t off_src0; size_t off_src1; size_t off_dst; + size_t src0_row_size_aligned; + size_t src1_row_size_aligned; + size_t dst_row_size_aligned; + size_t src0_bytes; size_t src1_bytes; size_t dst_bytes; }; static inline void htp_unary_vtcm_layout_build( + struct htp_unary_vtcm_layout * L, + uint32_t op, + size_t src0_data_row_size, + size_t dst_data_row_size, + size_t src1_data_row_size, + size_t elem_size, + uint32_t col_tile, + uint32_t block, + bool broadcast_weight, + uint32_t n_threads +) { + L->src0_row_size_aligned = hex_round_up(src0_data_row_size, 128); + L->dst_row_size_aligned = hex_round_up(dst_data_row_size, 128); + L->src1_row_size_aligned = (op == HTP_OP_RMS_NORM_MUL) ? hex_round_up(src1_data_row_size, 128) : 0; + + if (col_tile > 0) { + const size_t col_tile_bytes = col_tile * elem_size; + L->src0_bytes = col_tile_bytes * 2; + L->dst_bytes = col_tile_bytes * 2; + L->src1_bytes = 0; + } else { + L->src0_bytes = L->src0_row_size_aligned * block * 2; + L->dst_bytes = L->dst_row_size_aligned * block * 2; + if (op == HTP_OP_RMS_NORM_MUL) { + L->src1_bytes = broadcast_weight ? L->src1_row_size_aligned : (L->src1_row_size_aligned * block * 2); + } else { + L->src1_bytes = 0; + } + } + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src0, L->src0_bytes * n_threads); + VTCM_LAYOUT_ALLOC_OPTIONAL(off, off_src1, L->src1_bytes * n_threads, L->src1_bytes > 0); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes * n_threads); + L->total_bytes = off; +} + +static inline void htp_unary_solve_layout( struct htp_unary_vtcm_layout * L, uint32_t op, uint32_t ne00, uint32_t ne10, uint32_t ne11, + uint32_t max_block, bool broadcast_weight, uint32_t n_threads, size_t vtcm_size, @@ -94,18 +150,14 @@ static inline void htp_unary_vtcm_layout_build( uint32_t * out_col_tile, uint32_t * out_vtcm_row_per_thread ) { + const size_t dst_elem_size = (op == HTP_OP_HADAMARD) ? sizeof(float) : elem_size; const size_t src0_data_row_size = ne00 * elem_size; - const size_t dst_data_row_size = ne10 * elem_size; + const size_t dst_data_row_size = ne10 * dst_elem_size; + const size_t src1_data_row_size = (op == HTP_OP_RMS_NORM_MUL) ? (ne11 * sizeof(float)) : 0; const size_t src0_row_size_aligned = hex_round_up(src0_data_row_size, 128); const size_t dst_row_size_aligned = hex_round_up(dst_data_row_size, 128); - - size_t src1_row_size_aligned = 0; - if (op == HTP_OP_RMS_NORM_MUL) { - // RMS_NORM_MUL fusion is F32-only; its weight tensor is always F32. - const size_t src1_data_row_size = ne11 * sizeof(float); - src1_row_size_aligned = hex_round_up(src1_data_row_size, 128); - } + const size_t src1_row_size_aligned = (op == HTP_OP_RMS_NORM_MUL) ? hex_round_up(src1_data_row_size, 128) : 0; size_t vtcm_size_per_row = 0; size_t vtcm_row_per_thread = 0; @@ -130,8 +182,13 @@ static inline void htp_unary_vtcm_layout_build( vtcm_row_per_thread = vtcm_size / (n_threads * vtcm_size_per_row); } + if (max_block > 0 && vtcm_row_per_thread > max_block) { + vtcm_row_per_thread = max_block; + } + const bool is_reduction = (op == HTP_OP_NORM || op == HTP_OP_RMS_NORM || - op == HTP_OP_RMS_NORM_MUL || op == HTP_OP_L2_NORM); + op == HTP_OP_RMS_NORM_MUL || op == HTP_OP_L2_NORM || + op == HTP_OP_HADAMARD); // The tiled fallback path below only has F32 task functions (unary_task_f32_tiled_*); // F16 has no tiled kernels, so it must stay on the row-block path like reduction ops. // NOTE: if F16 ends up with vtcm_row_per_thread == 0 here (row too large for the VTCM @@ -145,37 +202,14 @@ static inline void htp_unary_vtcm_layout_build( const size_t per_thread_budget = vtcm_size / n_threads; const size_t col_tile_bytes = hex_align_down(per_thread_budget / 4, 128); col_tile = (uint32_t) (col_tile_bytes / elem_size); - - L->src0_bytes = col_tile_bytes * 2; - L->dst_bytes = col_tile_bytes * 2; - L->src1_bytes = 0; - } else { - L->src0_bytes = src0_row_size_aligned * vtcm_row_per_thread * 2; - L->dst_bytes = dst_row_size_aligned * vtcm_row_per_thread * 2; - if (op == HTP_OP_RMS_NORM_MUL) { - if (broadcast_weight) { - L->src1_bytes = src1_row_size_aligned; - } else { - L->src1_bytes = src1_row_size_aligned * vtcm_row_per_thread * 2; - } - } else { - L->src1_bytes = 0; - } - } - - L->off_src0 = 0; - if (op == HTP_OP_RMS_NORM_MUL) { - L->off_src1 = L->off_src0 + L->src0_bytes * n_threads; - L->off_dst = L->off_src1 + L->src1_bytes * n_threads; - } else { - L->off_src1 = 0; - L->off_dst = L->off_src0 + L->src0_bytes * n_threads; } - L->total_bytes = L->off_dst + L->dst_bytes * n_threads; + const uint32_t block = col_tile ? 0 : (uint32_t) vtcm_row_per_thread; + htp_unary_vtcm_layout_build(L, op, src0_data_row_size, dst_data_row_size, src1_data_row_size, + elem_size, col_tile, block, broadcast_weight, n_threads); *out_col_tile = col_tile; - *out_vtcm_row_per_thread = vtcm_row_per_thread; + *out_vtcm_row_per_thread = (uint32_t) vtcm_row_per_thread; } #endif /* HTP_UNARY_OPS_H */ diff --git a/ggml/src/ggml-hexagon/htp/upscale-ops.c b/ggml/src/ggml-hexagon/htp/upscale-ops.c new file mode 100644 index 000000000000..62070cf5d7cd --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/upscale-ops.c @@ -0,0 +1,958 @@ +#pragma clang diagnostic ignored "-Wunused-variable" + +#include +#include +#include + +#include "hex-common.h" +#include "dma-queue.h" +#include "hex-profile.h" +#include "htp-ctx.h" +#include "htp-ops.h" +#include "htp-tensor.h" +#include "hvx-types.h" +#include "hvx-base.h" +#include "hvx-utils.h" +#include "upscale-ops.h" + +static inline int32_t clamp_i32(int32_t v, int32_t lo, int32_t hi) { + return v < lo ? lo : (v > hi ? hi : v); +} + +static inline float clamp_f32(float v, float lo, float hi) { + return v < lo ? lo : (v > hi ? hi : v); +} + +static inline float bicubic_weight1(float x) { + const float a = -0.75f; + return ((a + 2.0f) * x - (a + 3.0f)) * x * x + 1.0f; +} + +static inline float bicubic_weight2(float x) { + const float a = -0.75f; + return ((a * x - 5.0f * a) * x + 8.0f * a) * x - 4.0f * a; +} + +static inline void bicubic_weights(float x, float w[4]) { + w[0] = bicubic_weight2(x + 1.0f); + w[1] = bicubic_weight1(x); + w[2] = bicubic_weight1(1.0f - x); + w[3] = bicubic_weight2(2.0f - x); +} + +static void upscale_init_luts_nearest( + uint32_t * lut_x, + uint32_t * lut_y, + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p +) { + const uint32_t src_x = src0->ne[0]; + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_x = dst->ne[0]; + const uint32_t dst_y = dst->ne[1]; + const uint32_t dst_x_aligned = (dst_x + VLEN_FP32 - 1) & ~(VLEN_FP32 - 1); + + for (uint32_t ox = 0; ox < dst_x_aligned; ++ox) { + if (ox < dst_x) { + uint32_t x0 = (uint32_t) ((float) ox * p->inv_sf0); + lut_x[ox] = MIN(x0, src_x - 1) * sizeof(float); + } else { + lut_x[ox] = 0; + } + } + for (uint32_t oy = 0; oy < dst_y; ++oy) { + uint32_t y0 = (uint32_t) ((float) oy * p->inv_sf1); + lut_y[oy] = MIN(y0, src_y - 1); + } +} + +static void upscale_init_luts_bilinear( + struct upscale_bilinear_x_chunk * lut_x, + struct upscale_bilinear_y * lut_y, + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p +) { + const uint32_t src_x = src0->ne[0]; + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_x = dst->ne[0]; + const uint32_t dst_y = dst->ne[1]; + const uint32_t n_chunks = (dst_x + VLEN_FP32 - 1) / VLEN_FP32; + + for (uint32_t c = 0; c < n_chunks; ++c) { + struct upscale_bilinear_x_chunk * chunk = &lut_x[c]; + const uint32_t ox_start = c * VLEN_FP32; + for (uint32_t l = 0; l < VLEN_FP32; ++l) { + const uint32_t ox = ox_start + l; + if (ox < dst_x) { + float xf = ((float) ox + p->pixel_offset) * p->inv_sf0 - p->pixel_offset; + int32_t x0 = (int32_t) floorf(xf); + int32_t x1 = x0 + 1; + x0 = clamp_i32(x0, 0, (int32_t) src_x - 1); + x1 = clamp_i32(x1, 0, (int32_t) src_x - 1); + float dx = clamp_f32(xf - (float) x0, 0.0f, 1.0f); + + chunk->off0[l] = x0 * (int32_t) sizeof(float); + chunk->off1[l] = x1 * (int32_t) sizeof(float); + chunk->w0[l] = 1.0f - dx; + chunk->dx[l] = dx; + } else { + chunk->off0[l] = 0; + chunk->off1[l] = 0; + chunk->w0[l] = 0.0f; + chunk->dx[l] = 0.0f; + } + } + } + for (uint32_t oy = 0; oy < dst_y; ++oy) { + float yf = ((float) oy + p->pixel_offset) * p->inv_sf1 - p->pixel_offset; + int32_t y0 = (int32_t) floorf(yf); + int32_t y1 = y0 + 1; + y0 = clamp_i32(y0, 0, (int32_t) src_y - 1); + y1 = clamp_i32(y1, 0, (int32_t) src_y - 1); + float dy = clamp_f32(yf - (float) y0, 0.0f, 1.0f); + + lut_y[oy].y0 = (uint32_t) y0; + lut_y[oy].y1 = (uint32_t) y1; + lut_y[oy].wy1 = dy; + lut_y[oy].wy0 = 1.0f - dy; + } +} + +static void upscale_init_luts_bicubic( + struct upscale_bicubic_x * lut_x, + struct upscale_bicubic_y * lut_y, + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p +) { + const uint32_t src_x = src0->ne[0]; + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_x = dst->ne[0]; + const uint32_t dst_y = dst->ne[1]; + + for (uint32_t ox = 0; ox < dst_x; ++ox) { + float xf = ((float) ox + p->pixel_offset) * p->inv_sf0 - p->pixel_offset; + int32_t x0 = (int32_t) floorf(xf); + float dx = xf - (float) x0; + bicubic_weights(dx, lut_x[ox].w); + + lut_x[ox].x[0] = clamp_i32(x0 - 1, 0, (int32_t) src_x - 1); + lut_x[ox].x[1] = clamp_i32(x0 + 0, 0, (int32_t) src_x - 1); + lut_x[ox].x[2] = clamp_i32(x0 + 1, 0, (int32_t) src_x - 1); + lut_x[ox].x[3] = clamp_i32(x0 + 2, 0, (int32_t) src_x - 1); + } + for (uint32_t oy = 0; oy < dst_y; ++oy) { + float yf = ((float) oy + p->pixel_offset) * p->inv_sf1 - p->pixel_offset; + int32_t y0 = (int32_t) floorf(yf); + float dy = yf - (float) y0; + bicubic_weights(dy, lut_y[oy].w); + + lut_y[oy].y[0] = clamp_i32(y0 - 1, 0, (int32_t) src_y - 1); + lut_y[oy].y[1] = clamp_i32(y0 + 0, 0, (int32_t) src_y - 1); + lut_y[oy].y[2] = clamp_i32(y0 + 1, 0, (int32_t) src_y - 1); + lut_y[oy].y[3] = clamp_i32(y0 + 2, 0, (int32_t) src_y - 1); + } +} + +static void upscale_init_luts_antialias( + struct upscale_antialias_x * lut_x, + struct upscale_antialias_y * lut_y, + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p +) { + const uint32_t src_x = src0->ne[0]; + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_x = dst->ne[0]; + const uint32_t dst_y = dst->ne[1]; + + const float filter_radius0 = p->filter_radius0; + const float filter_radius1 = p->filter_radius1; + + for (uint32_t ox = 0; ox < dst_x; ++ox) { + const float xf = ((float) ox + p->pixel_offset) * p->inv_sf0; + int32_t x_min = (int32_t) MAX(xf - filter_radius0 + p->pixel_offset, 0.0f); + int32_t x_max = (int32_t) MIN(xf + filter_radius0 + p->pixel_offset, (float) src_x); + lut_x[ox].x_min = clamp_i32(x_min, 0, (int32_t) src_x); + lut_x[ox].x_max = clamp_i32(x_max, 0, (int32_t) src_x); + lut_x[ox].xf = xf; + } + for (uint32_t oy = 0; oy < dst_y; ++oy) { + const float yf = ((float) oy + p->pixel_offset) * p->inv_sf1; + int32_t y_min = (int32_t) MAX(yf - filter_radius1 + p->pixel_offset, 0.0f); + int32_t y_max = (int32_t) MIN(yf + filter_radius1 + p->pixel_offset, (float) src_y); + lut_y[oy].y_min = clamp_i32(y_min, 0, (int32_t) src_y); + lut_y[oy].y_max = clamp_i32(y_max, 0, (int32_t) src_y); + lut_y[oy].yf = yf; + } +} + +static inline void get_src_y_window( + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p, + const void * lut_y, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t * out_src_y_start, + uint32_t * out_src_y_count +) { + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_y = dst->ne[1]; + + if (dst_y_count == dst_y) { + *out_src_y_start = 0; + *out_src_y_count = src_y; + return; + } + + const uint32_t last_oy = dst_y_start + dst_y_count - 1; + + if (p->mode == HTP_UPSCALE_MODE_NEAREST) { + const uint32_t * ly = (const uint32_t *) lut_y; + const uint32_t y0 = ly[dst_y_start]; + const uint32_t y1 = ly[last_oy]; + *out_src_y_start = y0; + *out_src_y_count = y1 - y0 + 1; + } else if (p->mode == HTP_UPSCALE_MODE_BICUBIC) { + const struct upscale_bicubic_y * ly = (const struct upscale_bicubic_y *) lut_y; + const int32_t y0 = ly[dst_y_start].y[0]; + const int32_t y1 = ly[last_oy].y[3]; + *out_src_y_start = (uint32_t) y0; + *out_src_y_count = (uint32_t) (y1 - y0 + 1); + } else if (p->antialias) { + const struct upscale_antialias_y * ly = (const struct upscale_antialias_y *) lut_y; + const int32_t y0 = ly[dst_y_start].y_min; + const int32_t y1 = ly[last_oy].y_max; + *out_src_y_start = (uint32_t) y0; + *out_src_y_count = (uint32_t) (y1 - y0); + } else { + const struct upscale_bilinear_y * ly = (const struct upscale_bilinear_y *) lut_y; + const uint32_t y0 = ly[dst_y_start].y0; + const uint32_t y1 = ly[last_oy].y1; + *out_src_y_start = y0; + *out_src_y_count = y1 - y0 + 1; + } +} + +static inline void resolve_dst_slice( + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p, + uint32_t chunk_idx, + dma_addr_t * out_slice_dst_off, + uint32_t * out_dst_ys, + uint32_t * out_dst_yc +) { + const uint32_t s_idx = fastdiv(chunk_idx, &p->div_chunks_per_slice); + const uint32_t c_idx = chunk_idx - s_idx * p->chunks_per_slice; + const uint32_t d_ys = c_idx * p->dst_nrows_per_chunk; + const uint32_t d_yc = MIN(p->dst_nrows_per_chunk, dst->ne[1] - d_ys); + const uint32_t i3 = fastdiv(s_idx, &p->div_dst_z); + const uint32_t i2 = s_idx - i3 * dst->ne[2]; + + *out_slice_dst_off = (dma_addr_t) i2 * dst->nb[2] + (dma_addr_t) i3 * dst->nb[3]; + *out_dst_ys = d_ys; + *out_dst_yc = d_yc; +} + +static inline void resolve_src_slice( + const struct htp_tensor * src0, + const struct htp_tensor * dst, + const struct htp_upscale_kernel_params * p, + const void * lut_y, + uint32_t chunk_idx, + dma_addr_t * out_slice_src_off, + uint32_t * out_src_ys, + uint32_t * out_src_yc +) { + const uint32_t s_idx = fastdiv(chunk_idx, &p->div_chunks_per_slice); + const uint32_t c_idx = chunk_idx - s_idx * p->chunks_per_slice; + const uint32_t d_ys = c_idx * p->dst_nrows_per_chunk; + const uint32_t d_yc = MIN(p->dst_nrows_per_chunk, dst->ne[1] - d_ys); + uint32_t s_ys, s_yc; + get_src_y_window(src0, dst, p, lut_y, d_ys, d_yc, &s_ys, &s_yc); + + const uint32_t i3 = fastdiv(s_idx, &p->div_dst_z); + const uint32_t i2 = s_idx - i3 * dst->ne[2]; + const uint32_t i03 = (uint32_t) ((float) i3 * p->inv_sf3); + const uint32_t i02 = (uint32_t) ((float) i2 * p->inv_sf2); + + *out_slice_src_off = (dma_addr_t) i02 * src0->nb[2] + (dma_addr_t) i03 * src0->nb[3]; + *out_src_ys = s_ys; + *out_src_yc = s_yc; +} + +struct upscale_context; + +typedef void (*upscale_chunk_fn_t)( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +); + +struct upscale_context { + struct htp_ops_context * octx; + const struct htp_upscale_kernel_params * kparams; + struct htp_upscale_vtcm_layout layout; + upscale_chunk_fn_t compute_chunk; + const void * lut_x; + const void * lut_y; + uint32_t chunk_start; + uint32_t chunk_count; + uint32_t chunks_per_thread; +}; + +static void compute_nearest_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + const uint32_t * lut_x = (const uint32_t *) ctx->lut_x; + const uint32_t * lut_y = (const uint32_t *) ctx->lut_y; + const uint32_t region_size = hex_round_up(src_x * sizeof(float), 128); + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const uint32_t y0 = lut_y[oy]; + const float * r0 = srcb + (y0 - src_y_start) * src_x; + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + *(HVX_Vector *) (R_buf + ix) = hvx_vmemu(r0 + ix); + } + + for (uint32_t ox = 0; ox < dst_x; ox += VLEN_FP32) { + const uint32_t rem = dst_x - ox; + const uint32_t nbytes = (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN; + const HVX_Vector voff = hvx_vmem(lut_x + ox); + Q6_vgather_ARMVw((HVX_Vector *) gather_tmp, (size_t) R_buf, region_size, voff); + hvx_gather_sync(gather_tmp); + hvx_vec_store_u(dst_row + ox, nbytes, hvx_vmem(gather_tmp)); + } + } +} + +static void compute_nearest_2x_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + (void) R_buf; + (void) gather_tmp; + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const uint32_t sy = oy >> 1; + const float * r0 = srcb + (sy - src_y_start) * src_x; + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + const HVX_Vector vin = hvx_vmemu(r0 + ix); + + const HVX_VectorPair p = Q6_W_vshuff_VVR(vin, vin, -4); + const HVX_Vector v_lo = Q6_V_lo_W(p); + const HVX_Vector v_hi = Q6_V_hi_W(p); + + const uint32_t ox0 = 2 * ix; + const uint32_t rem_out0 = (dst_x > ox0) ? (dst_x - ox0) : 0; + const uint32_t nbytes_out0 = (rem_out0 < VLEN_FP32) ? (rem_out0 * sizeof(float)) : VLEN; + hvx_vec_store_u(dst_row + ox0, nbytes_out0, v_lo); + + const uint32_t ox1 = ox0 + VLEN_FP32; + if (dst_x > ox1) { + const uint32_t rem_out1 = dst_x - ox1; + const uint32_t nbytes_out1 = (rem_out1 < VLEN_FP32) ? (rem_out1 * sizeof(float)) : VLEN; + hvx_vec_store_u(dst_row + ox1, nbytes_out1, v_hi); + } + } + } +} + +static void compute_nearest_4x_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + (void) R_buf; + (void) gather_tmp; + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const uint32_t sy = oy >> 2; + const float * r0 = srcb + (sy - src_y_start) * src_x; + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + const HVX_Vector vin = hvx_vmemu(r0 + ix); + + const HVX_VectorPair p = Q6_W_vshuff_VVR(vin, vin, -4); + const HVX_Vector v_lo = Q6_V_lo_W(p); + const HVX_Vector v_hi = Q6_V_hi_W(p); + + const HVX_VectorPair p0 = Q6_W_vshuff_VVR(v_lo, v_lo, -4); + const HVX_VectorPair p1 = Q6_W_vshuff_VVR(v_hi, v_hi, -4); + + const HVX_Vector out0 = Q6_V_lo_W(p0); + const HVX_Vector out1 = Q6_V_hi_W(p0); + const HVX_Vector out2 = Q6_V_lo_W(p1); + const HVX_Vector out3 = Q6_V_hi_W(p1); + + const uint32_t ox = 4 * ix; + if (dst_x > ox) { + const uint32_t rem = dst_x - ox; + hvx_vec_store_u(dst_row + ox, (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN, out0); + } + if (dst_x > ox + VLEN_FP32) { + const uint32_t rem = dst_x - (ox + VLEN_FP32); + hvx_vec_store_u(dst_row + ox + VLEN_FP32, (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN, out1); + } + if (dst_x > ox + 2 * VLEN_FP32) { + const uint32_t rem = dst_x - (ox + 2 * VLEN_FP32); + hvx_vec_store_u(dst_row + ox + 2 * VLEN_FP32, (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN, out2); + } + if (dst_x > ox + 3 * VLEN_FP32) { + const uint32_t rem = dst_x - (ox + 3 * VLEN_FP32); + hvx_vec_store_u(dst_row + ox + 3 * VLEN_FP32, (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN, out3); + } + } + } +} + +static inline void compute_bilinear_chunk_32( + float * restrict dst_chunk, + const float * restrict R_buf, + float * restrict tmp_a, + float * restrict tmp_b, + uint32_t region_size, + const struct upscale_bilinear_x_chunk * restrict chunk, + uint32_t nbytes +) { + const HVX_Vector voff0 = hvx_vmem(chunk->off0); + const HVX_Vector voff1 = hvx_vmem(chunk->off1); + const HVX_Vector vw0 = hvx_vmem(chunk->w0); + const HVX_Vector vdx = hvx_vmem(chunk->dx); + + Q6_vgather_ARMVw((HVX_Vector *) tmp_a, (size_t) R_buf, region_size, voff0); + Q6_vgather_ARMVw((HVX_Vector *) tmp_b, (size_t) R_buf, region_size, voff1); + hvx_gather_sync(tmp_b); + + const HVX_Vector va = hvx_vmem(tmp_a); + const HVX_Vector vb = hvx_vmem(tmp_b); + + const HVX_Vector val = hvx_vec_add_f32_f32( + hvx_vec_mul_f32_f32(vw0, va), + hvx_vec_mul_f32_f32(vdx, vb) + ); + + hvx_vec_store_u(dst_chunk, nbytes, val); +} + +static void compute_bilinear_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + const struct upscale_bilinear_x_chunk * lut_x = (const struct upscale_bilinear_x_chunk *) ctx->lut_x; + const struct upscale_bilinear_y * lut_y = (const struct upscale_bilinear_y *) ctx->lut_y; + const uint32_t n_chunks = (dst_x + VLEN_FP32 - 1) / VLEN_FP32; + const uint32_t region_size = hex_round_up(src_x * sizeof(float), 128); + float * tmp_a = gather_tmp; + float * tmp_b = gather_tmp + VLEN_FP32; + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const struct upscale_bilinear_y * ey = &lut_y[oy]; + const float * r0 = srcb + (ey->y0 - src_y_start) * src_x; + const float * r1 = srcb + (ey->y1 - src_y_start) * src_x; + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + if (ey->y0 == ey->y1) { + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + *(HVX_Vector *) (R_buf + ix) = hvx_vmemu(r0 + ix); + } + } else { + const HVX_Vector vwy0 = hvx_vec_splat_f32(ey->wy0); + const HVX_Vector vwy1 = hvx_vec_splat_f32(ey->wy1); + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + const HVX_Vector vr0 = hvx_vmemu(r0 + ix); + const HVX_Vector vr1 = hvx_vmemu(r1 + ix); + *(HVX_Vector *) (R_buf + ix) = hvx_vec_add_f32_f32( + hvx_vec_mul_f32_f32(vwy0, vr0), + hvx_vec_mul_f32_f32(vwy1, vr1) + ); + } + } + + for (uint32_t c = 0; c < n_chunks; ++c) { + const uint32_t ox = c * VLEN_FP32; + const uint32_t rem = dst_x - ox; + const uint32_t nbytes = (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN; + compute_bilinear_chunk_32(dst_row + ox, R_buf, tmp_a, tmp_b, region_size, &lut_x[c], nbytes); + } + } +} + +static void compute_bilinear_2x_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + (void) R_buf; + (void) gather_tmp; + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + const struct upscale_bilinear_y * lut_y = (const struct upscale_bilinear_y *) ctx->lut_y; + const HVX_Vector c_075 = hvx_vec_splat_f32(0.75f); + const HVX_Vector c_025 = hvx_vec_splat_f32(0.25f); + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const struct upscale_bilinear_y * ey = &lut_y[oy]; + const float * r0 = srcb + (ey->y0 - src_y_start) * src_x; + const float * r1 = srcb + (ey->y1 - src_y_start) * src_x; + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + const bool same_row = (ey->y0 == ey->y1); + const HVX_Vector vwy0 = hvx_vec_splat_f32(ey->wy0); + const HVX_Vector vwy1 = hvx_vec_splat_f32(ey->wy1); + + HVX_Vector v_curr = hvx_vmem(r0); + if (!same_row) { + const HVX_Vector v1 = hvx_vmem(r1); + v_curr = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(vwy0, v_curr), hvx_vec_mul_f32_f32(vwy1, v1)); + } + + HVX_Vector v_prev = Q6_V_vror_VR(v_curr, 4); + + for (uint32_t ix = 0; ix < src_x; ix += VLEN_FP32) { + HVX_Vector v_next_chunk; + const uint32_t next_ix = ix + VLEN_FP32; + if (next_ix < src_x) { + v_next_chunk = hvx_vmem(r0 + next_ix); + if (!same_row) { + const HVX_Vector v1 = hvx_vmem(r1 + next_ix); + v_next_chunk = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(vwy0, v_next_chunk), hvx_vec_mul_f32_f32(vwy1, v1)); + } + } else { + v_next_chunk = Q6_V_vror_VR(v_curr, 124); + } + + const HVX_Vector v_shl = Q6_V_valign_VVR(v_curr, v_prev, 124); + const HVX_Vector v_shr = Q6_V_valign_VVR(v_next_chunk, v_curr, 4); + + const HVX_Vector ve = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(c_075, v_curr), hvx_vec_mul_f32_f32(c_025, v_shl)); + const HVX_Vector vo = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(c_075, v_curr), hvx_vec_mul_f32_f32(c_025, v_shr)); + + const HVX_VectorPair p = Q6_W_vshuff_VVR(vo, ve, -4); + const HVX_Vector out0 = Q6_V_lo_W(p); + const HVX_Vector out1 = Q6_V_hi_W(p); + + const uint32_t ox0 = 2 * ix; + hvx_vmem(dst_row + ox0) = out0; + hvx_vmem(dst_row + ox0 + VLEN_FP32) = out1; + + v_prev = v_curr; + v_curr = v_next_chunk; + } + } +} + +static void compute_bilinear_antialias_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + (void) R_buf; + (void) gather_tmp; + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + const struct htp_upscale_kernel_params * p = ctx->kparams; + const struct upscale_antialias_x * lut_x = (const struct upscale_antialias_x *) ctx->lut_x; + const struct upscale_antialias_y * lut_y = (const struct upscale_antialias_y *) ctx->lut_y; + + const float invscale1 = p->invscale1; + const float invscale0 = p->invscale0; + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const struct upscale_antialias_y * ey = &lut_y[oy]; + const float yf = ey->yf; + const int32_t y_min = ey->y_min; + const int32_t y_max = ey->y_max; + + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + for (uint32_t ox = 0; ox < dst_x; ox += VLEN_FP32) { + const uint32_t rem = dst_x - ox; + const uint32_t nbytes = (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN; + float tmp[VLEN_FP32] __attribute__((aligned(128))); + const uint32_t cnt = rem < VLEN_FP32 ? rem : VLEN_FP32; + + for (uint32_t l = 0; l < cnt; ++l) { + const uint32_t cur_ox = ox + l; + const struct upscale_antialias_x * ex = &lut_x[cur_ox]; + const float xf = ex->xf; + const int32_t x_min = ex->x_min; + const int32_t x_max = ex->x_max; + + float val = 0.0f; + float total_weight = 0.0f; + + for (int32_t sy = y_min; sy < y_max; ++sy) { + const float diff_y = fabsf((float) sy - yf + p->pixel_offset) * invscale1; + const float weight_y = MAX(1.0f - diff_y, 0.0f); + if (weight_y <= 0.0f) { + continue; + } + const float * r = srcb + (uint32_t) (sy - (int32_t) src_y_start) * src_x; + + for (int32_t sx = x_min; sx < x_max; ++sx) { + const float diff_x = fabsf((float) sx - xf + p->pixel_offset) * invscale0; + const float weight_x = MAX(1.0f - diff_x, 0.0f); + const float weight = weight_x * weight_y; + if (weight <= 0.0f) { + continue; + } + val += r[sx] * weight; + total_weight += weight; + } + } + + tmp[l] = (total_weight > 0.0f) ? (val / total_weight) : 0.0f; + } + + hvx_vec_store_u(dst_row + ox, nbytes, *(const HVX_Vector *) tmp); + } + } +} + +static void compute_bicubic_chunk( + const struct upscale_context * ctx, + const float * srcb, + float * dstb, + float * R_buf, + float * gather_tmp, + uint32_t dst_y_start, + uint32_t dst_y_count, + uint32_t src_y_start +) { + (void) R_buf; + (void) gather_tmp; + const uint32_t src_x = ctx->octx->src[0]->ne[0]; + const uint32_t dst_x = ctx->octx->dst->ne[0]; + const struct upscale_bicubic_x * lut_x = (const struct upscale_bicubic_x *) ctx->lut_x; + const struct upscale_bicubic_y * lut_y = (const struct upscale_bicubic_y *) ctx->lut_y; + + for (uint32_t oy = dst_y_start; oy < dst_y_start + dst_y_count; ++oy) { + const struct upscale_bicubic_y * ey = &lut_y[oy]; + const float * r0 = srcb + (uint32_t) (ey->y[0] - (int32_t) src_y_start) * src_x; + const float * r1 = srcb + (uint32_t) (ey->y[1] - (int32_t) src_y_start) * src_x; + const float * r2 = srcb + (uint32_t) (ey->y[2] - (int32_t) src_y_start) * src_x; + const float * r3 = srcb + (uint32_t) (ey->y[3] - (int32_t) src_y_start) * src_x; + + float * dst_row = dstb + (oy - dst_y_start) * dst_x; + + const HVX_Vector vwy0 = hvx_vec_splat_f32(ey->w[0]); + const HVX_Vector vwy1 = hvx_vec_splat_f32(ey->w[1]); + const HVX_Vector vwy2 = hvx_vec_splat_f32(ey->w[2]); + const HVX_Vector vwy3 = hvx_vec_splat_f32(ey->w[3]); + + for (uint32_t ox = 0; ox < dst_x; ox += VLEN_FP32) { + const uint32_t rem = dst_x - ox; + const uint32_t nbytes = (rem < VLEN_FP32) ? (rem * sizeof(float)) : VLEN; + + float v0[VLEN_FP32] __attribute__((aligned(128))); + float v1[VLEN_FP32] __attribute__((aligned(128))); + float v2[VLEN_FP32] __attribute__((aligned(128))); + float v3[VLEN_FP32] __attribute__((aligned(128))); + + const uint32_t cnt = rem < VLEN_FP32 ? rem : VLEN_FP32; + for (uint32_t l = 0; l < cnt; ++l) { + const struct upscale_bicubic_x * e = &lut_x[ox + l]; + v0[l] = r0[e->x[0]] * e->w[0] + r0[e->x[1]] * e->w[1] + r0[e->x[2]] * e->w[2] + r0[e->x[3]] * e->w[3]; + v1[l] = r1[e->x[0]] * e->w[0] + r1[e->x[1]] * e->w[1] + r1[e->x[2]] * e->w[2] + r1[e->x[3]] * e->w[3]; + v2[l] = r2[e->x[0]] * e->w[0] + r2[e->x[1]] * e->w[1] + r2[e->x[2]] * e->w[2] + r2[e->x[3]] * e->w[3]; + v3[l] = r3[e->x[0]] * e->w[0] + r3[e->x[1]] * e->w[1] + r3[e->x[2]] * e->w[2] + r3[e->x[3]] * e->w[3]; + } + for (uint32_t l = cnt; l < VLEN_FP32; ++l) { + v0[l] = v1[l] = v2[l] = v3[l] = 0.0f; + } + + const HVX_Vector vv0 = *(const HVX_Vector *) v0; + const HVX_Vector vv1 = *(const HVX_Vector *) v1; + const HVX_Vector vv2 = *(const HVX_Vector *) v2; + const HVX_Vector vv3 = *(const HVX_Vector *) v3; + + const HVX_Vector acc0 = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(vwy0, vv0), hvx_vec_mul_f32_f32(vwy1, vv1)); + const HVX_Vector acc1 = hvx_vec_add_f32_f32(hvx_vec_mul_f32_f32(vwy2, vv2), hvx_vec_mul_f32_f32(vwy3, vv3)); + const HVX_Vector val = hvx_vec_add_f32_f32(acc0, acc1); + + hvx_vec_store_u(dst_row + ox, nbytes, val); + } + } +} + +static inline void dma_push_src_chunk( + dma_queue * dma_q, + float * spad, + const struct htp_tensor * src0, + dma_addr_t slice_src_off, + uint32_t src_ys, + uint32_t src_yc +) { + const uint32_t src_x = src0->ne[0]; + const dma_addr_t src_addr = src0->data + slice_src_off + (dma_addr_t) src_ys * src0->nb[1]; + + if (src0->nb[0] == sizeof(float)) { + const uint32_t row_size = src_x * sizeof(float); + const uint32_t dst_stride = row_size; + const uint32_t src_stride = src0->nb[1]; + dma_queue_push(dma_q, dma_make_data(spad, src_addr), dst_stride, src_stride, row_size, src_yc); + } else { + const uint32_t row_size = sizeof(float); + const uint32_t dst_stride = sizeof(float); + const uint32_t src_stride = src0->nb[0]; + const uint32_t nrows = src_x * src_yc; + dma_queue_push(dma_q, dma_make_data(spad, src_addr), dst_stride, src_stride, row_size, nrows); + } +} + +static void upscale_worker(unsigned int nth, unsigned int ith, void * data) { + struct upscale_context * ctx = (struct upscale_context *) data; + const struct htp_upscale_kernel_params * p = ctx->kparams; + const struct htp_upscale_vtcm_layout * L = &ctx->layout; + const struct htp_tensor * src0 = ctx->octx->src[0]; + const struct htp_tensor * dst = ctx->octx->dst; + + const uint32_t first = ctx->chunk_start + ith * ctx->chunks_per_thread; + const uint32_t last = MIN(first + ctx->chunks_per_thread, ctx->chunk_start + ctx->chunk_count); + + if (first >= last) { + return; + } + + struct htp_thread_trace * tr = &ctx->octx->ctx->trace[ith]; + dma_queue * dma_q = ctx->octx->ctx->dma[ith]; + + const uint32_t src_spad_half = (uint32_t) L->src_spad_half_size; + const uint32_t dst_spad_half = (uint32_t) L->dst_spad_half_size; + + uint8_t * vtcm_base = (uint8_t *) ctx->octx->ctx->vtcm_base; + uint8_t * src_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_src) + ith * L->src_bytes_per_thread; + uint8_t * dst_spad = VTCM_LAYOUT_PTR(uint8_t, vtcm_base, L->off_dst) + ith * L->dst_bytes_per_thread; + float * R_buf = VTCM_LAYOUT_PTR(float, vtcm_base, L->off_r) + ith * (L->r_bytes_per_thread / sizeof(float)); + float * gather_tmp = VTCM_LAYOUT_PTR(float, vtcm_base, L->off_gather) + ith * (L->gather_bytes_per_thread / sizeof(float)); + const void * lut_y = ctx->lut_y; + + float * srcb2[2] = { (float *) src_spad, (float *) (src_spad + src_spad_half) }; + float * dstb2[2] = { (float *) dst_spad, (float *) (dst_spad + dst_spad_half) }; + + const uint32_t dst_row_size = dst->ne[0] * sizeof(float); + const uint32_t dst_stride = dst->nb[1]; + + const uint32_t total = last - first; + + // Warmup: prime pipeline with initial transfers + for (uint32_t i = 0; i < total && i < 2; ++i) { + dma_queue_push(dma_q, dma_make_data(dst->data, dstb2[i]), dst_stride, dst_row_size, dst_row_size, 0); + + dma_addr_t slice_src_off; + uint32_t src_ys, src_yc; + resolve_src_slice(src0, dst, p, lut_y, first + i, &slice_src_off, &src_ys, &src_yc); + + dma_push_src_chunk(dma_q, srcb2[i], src0, slice_src_off, src_ys, src_yc); + } + + // Steady state loop + for (uint32_t i = 0; i < total; ++i) { + const uint32_t buf = i & 1u; + float * srcb = srcb2[buf]; + float * dstb = dstb2[buf]; + + dma_queue_pop(dma_q); + dma_queue_pop(dma_q); + + dma_addr_t slice_dst_off; + uint32_t dst_ys, dst_yc; + resolve_dst_slice(dst, p, first + i, &slice_dst_off, &dst_ys, &dst_yc); + + uint32_t src_ys, src_yc; + get_src_y_window(src0, dst, p, lut_y, dst_ys, dst_yc, &src_ys, &src_yc); + + htp_trace_event_start(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) (first + i)); + ctx->compute_chunk(ctx, srcb, dstb, R_buf, gather_tmp, dst_ys, dst_yc, src_ys); + htp_trace_event_stop(tr, HTP_TRACE_EVT_HVX_COMP, (uint16_t) (first + i)); + + const dma_addr_t dst_addr = dst->data + slice_dst_off + (dma_addr_t) dst_ys * dst_stride; + dma_queue_push(dma_q, dma_make_data(dst_addr, dstb), dst_stride, dst_row_size, dst_row_size, dst_yc); + + const uint32_t next = i + 2; + if (next < total) { + dma_addr_t next_src_off; + uint32_t next_src_ys, next_src_yc; + resolve_src_slice(src0, dst, p, lut_y, first + next, &next_src_off, &next_src_ys, &next_src_yc); + + dma_push_src_chunk(dma_q, srcb, src0, next_src_off, next_src_ys, next_src_yc); + } + } + + dma_queue_flush(dma_q); + + (void) nth; +} + +int op_upscale(struct htp_ops_context * octx) { + const struct htp_tensor * src0 = octx->src[0]; + const struct htp_tensor * dst = octx->dst; + const struct htp_upscale_kernel_params * p = + (const struct htp_upscale_kernel_params *) octx->kernel_params; + + const uint32_t src_x = src0->ne[0]; + const uint32_t src_y = src0->ne[1]; + const uint32_t dst_x = dst->ne[0]; + const uint32_t dst_y = dst->ne[1]; + + uint32_t chunk_start = 0; + uint32_t chunk_count = p->total_chunks; + + if (octx->ctx->mdev.count > 1) { + const struct htp_tensor_mdev_range range = htp_tensor_mdev_partition( + chunk_count, htp_tensor_mdev_data_aligned(dst) ? p->chunks_per_group : 0, + octx->ctx->mdev.idx, octx->ctx->mdev.count, &octx->ctx->mdev.count_div); + chunk_start = range.start; + chunk_count = range.count; + } + + if (chunk_count == 0) { + return HTP_STATUS_OK; + } + + const uint32_t n_threads = MIN(p->n_threads, chunk_count); + if (!htp_ops_context_set_n_threads(octx, n_threads)) { + return HTP_STATUS_INVAL_PARAMS; + } + + const uint32_t chunks_per_thread = fastdiv(chunk_count + n_threads - 1, &octx->n_threads_div); + + size_t lut_x_size = 0; + size_t elem_y_sz = sizeof(uint32_t); + + if (p->mode == HTP_UPSCALE_MODE_BICUBIC) { + lut_x_size = hex_round_up(dst_x * sizeof(struct upscale_bicubic_x), 128); + elem_y_sz = sizeof(struct upscale_bicubic_y); + } else if (p->antialias) { + lut_x_size = hex_round_up(dst_x * sizeof(struct upscale_antialias_x), 128); + elem_y_sz = sizeof(struct upscale_antialias_y); + } else if (p->mode == HTP_UPSCALE_MODE_BILINEAR) { + const uint32_t n_chunks = (dst_x + VLEN_FP32 - 1) / VLEN_FP32; + lut_x_size = hex_round_up(n_chunks * sizeof(struct upscale_bilinear_x_chunk), 128); + elem_y_sz = sizeof(struct upscale_bilinear_y); + } else { + lut_x_size = hex_round_up(dst_x * sizeof(uint32_t), 128); + } + + const size_t lut_y_size = hex_round_up(dst_y * elem_y_sz, 128); + const size_t total_lut_size = lut_x_size + lut_y_size; + + if (total_lut_size > octx->ctx->ddr_spad_size) { + return HTP_STATUS_NO_SUPPORT; + } + + void * base_scratch = octx->ctx->ddr_spad_base; + void * lut_x = base_scratch; + void * lut_y = (uint8_t *) base_scratch + lut_x_size; + + if (p->mode == HTP_UPSCALE_MODE_NEAREST) { + upscale_init_luts_nearest((uint32_t *) lut_x, (uint32_t *) lut_y, src0, dst, p); + } else if (p->mode == HTP_UPSCALE_MODE_BICUBIC) { + upscale_init_luts_bicubic((struct upscale_bicubic_x *) lut_x, (struct upscale_bicubic_y *) lut_y, src0, dst, p); + } else if (p->antialias) { + upscale_init_luts_antialias((struct upscale_antialias_x *) lut_x, (struct upscale_antialias_y *) lut_y, src0, dst, p); + } else { + upscale_init_luts_bilinear((struct upscale_bilinear_x_chunk *) lut_x, (struct upscale_bilinear_y *) lut_y, src0, dst, p); + } + + upscale_chunk_fn_t compute_chunk; + switch (p->kernel_type) { + case HTP_UPSCALE_KERNEL_NEAREST: + compute_chunk = compute_nearest_chunk; + break; + case HTP_UPSCALE_KERNEL_NEAREST_2X: + compute_chunk = compute_nearest_2x_chunk; + break; + case HTP_UPSCALE_KERNEL_NEAREST_4X: + compute_chunk = compute_nearest_4x_chunk; + break; + case HTP_UPSCALE_KERNEL_BILINEAR: + compute_chunk = compute_bilinear_chunk; + break; + case HTP_UPSCALE_KERNEL_BILINEAR_2X: + compute_chunk = compute_bilinear_2x_chunk; + break; + case HTP_UPSCALE_KERNEL_BILINEAR_AA: + compute_chunk = compute_bilinear_antialias_chunk; + break; + case HTP_UPSCALE_KERNEL_BICUBIC: + compute_chunk = compute_bicubic_chunk; + break; + default: + return HTP_STATUS_INVAL_PARAMS; + } + + struct upscale_context ctx = { + .octx = octx, + .kparams = p, + .compute_chunk = compute_chunk, + .lut_x = lut_x, + .lut_y = lut_y, + .chunk_start = chunk_start, + .chunk_count = chunk_count, + .chunks_per_thread = chunks_per_thread, + }; + + htp_upscale_vtcm_layout_build(&ctx.layout, src_x, src_y, dst_x, dst_y, + p->dst_nrows_per_chunk, p->inv_sf1, p->filter_radius1, n_threads); + + work_queue_run(octx->ctx->work_queue, upscale_worker, &ctx, n_threads); + + return HTP_STATUS_OK; +} diff --git a/ggml/src/ggml-hexagon/htp/upscale-ops.h b/ggml/src/ggml-hexagon/htp/upscale-ops.h new file mode 100644 index 000000000000..aff7854b50f3 --- /dev/null +++ b/ggml/src/ggml-hexagon/htp/upscale-ops.h @@ -0,0 +1,204 @@ +#ifndef HTP_UPSCALE_OPS_H +#define HTP_UPSCALE_OPS_H + +#include +#include +#include +#include + +#include "hex-common.h" +#include "hex-fastdiv.h" +#include "htp-vtcm.h" + +enum htp_upscale_mode { + HTP_UPSCALE_MODE_NEAREST = 0, + HTP_UPSCALE_MODE_BILINEAR = 1, + HTP_UPSCALE_MODE_BICUBIC = 2, +}; + +enum htp_upscale_kernel_type { + HTP_UPSCALE_KERNEL_NEAREST = 0, + HTP_UPSCALE_KERNEL_NEAREST_2X = 1, + HTP_UPSCALE_KERNEL_NEAREST_4X = 2, + HTP_UPSCALE_KERNEL_BILINEAR = 3, + HTP_UPSCALE_KERNEL_BILINEAR_2X = 4, + HTP_UPSCALE_KERNEL_BILINEAR_AA = 5, + HTP_UPSCALE_KERNEL_BICUBIC = 6, +}; + +struct htp_upscale_kernel_params { + uint8_t kernel_type; + uint8_t mode; + uint8_t align_corners; + uint8_t antialias; + + float inv_sf0; + float inv_sf1; + float inv_sf2; + float inv_sf3; + float pixel_offset; + + float filter_radius0; + float filter_radius1; + float invscale0; + float invscale1; + + uint32_t n_threads; + uint32_t chunks_per_group; + + uint32_t dst_nrows_per_chunk; + uint32_t chunks_per_slice; + uint32_t total_chunks; + uint32_t vtcm_size; + + struct fastdiv_values div_chunks_per_slice; + struct fastdiv_values div_dst_z; +}; + +#if defined(__cplusplus) +static_assert(sizeof(struct htp_upscale_kernel_params) <= 128, "htp_upscale_kernel_params is too large"); +#else +_Static_assert(sizeof(struct htp_upscale_kernel_params) <= 128, "htp_upscale_kernel_params is too large"); +#endif + +struct __attribute__((aligned(128))) upscale_bilinear_x_chunk { + int32_t off0[32]; + int32_t off1[32]; + float w0[32]; + float dx[32]; +}; + +struct upscale_bilinear_y { + uint32_t y0; + uint32_t y1; + float wy0; + float wy1; +}; + +struct upscale_bicubic_x { + int32_t x[4]; + float w[4]; +}; + +struct upscale_bicubic_y { + int32_t y[4]; + float w[4]; +}; + +struct upscale_antialias_x { + int32_t x_min; + int32_t x_max; + float xf; +}; + +struct upscale_antialias_y { + int32_t y_min; + int32_t y_max; + float yf; +}; + +struct htp_upscale_vtcm_layout { + size_t total_bytes; + size_t off_src; + size_t off_dst; + size_t off_r; + size_t off_gather; + size_t src_bytes_per_thread; + size_t dst_bytes_per_thread; + size_t r_bytes_per_thread; + size_t gather_bytes_per_thread; + size_t src_spad_half_size; + size_t dst_spad_half_size; + uint32_t max_src_chunk_rows; + uint32_t dst_chunk_rows; +}; + +static inline void htp_upscale_vtcm_layout_build( + struct htp_upscale_vtcm_layout * L, + uint32_t src_x, + uint32_t src_y, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_chunk_rows, + float inv_sf1, + float filter_radius1, + uint32_t n_threads +) { + uint32_t max_src_rows; + if (dst_chunk_rows >= dst_y) { + max_src_rows = src_y; + } else { + const float est = (float) dst_chunk_rows * inv_sf1 + 2.0f * filter_radius1; + max_src_rows = (uint32_t) ceilf(est) + 4; + if (max_src_rows > src_y) { + max_src_rows = src_y; + } + } + + const uint32_t src_chunk_bytes = src_x * max_src_rows * sizeof(float); + const uint32_t dst_chunk_bytes = dst_x * dst_chunk_rows * sizeof(float); + + L->max_src_chunk_rows = max_src_rows; + L->dst_chunk_rows = dst_chunk_rows; + L->src_spad_half_size = hex_round_up(src_chunk_bytes + 256, 128); + L->dst_spad_half_size = hex_round_up(dst_chunk_bytes, 128); + L->src_bytes_per_thread = 2 * L->src_spad_half_size; + L->dst_bytes_per_thread = 2 * L->dst_spad_half_size; + L->r_bytes_per_thread = hex_round_up(src_x * sizeof(float), 128); + L->gather_bytes_per_thread = 256; + + size_t off = 0; + VTCM_LAYOUT_ALLOC(off, off_src, L->src_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_dst, L->dst_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_r, L->r_bytes_per_thread * n_threads); + VTCM_LAYOUT_ALLOC(off, off_gather, L->gather_bytes_per_thread * n_threads); + L->total_bytes = off; +} + +static inline bool htp_upscale_solve_layout( + struct htp_upscale_vtcm_layout * layout, + uint32_t src_x, + uint32_t src_y, + uint32_t dst_x, + uint32_t dst_y, + float inv_sf1, + float filter_radius1, + uint32_t n_threads, + size_t vtcm_budget, + uint32_t * out_dst_chunk_rows +) { + // 1. Try full plane + uint32_t chunk_rows = dst_y; + htp_upscale_vtcm_layout_build(layout, src_x, src_y, dst_x, dst_y, chunk_rows, inv_sf1, filter_radius1, n_threads); + if (layout->total_bytes <= vtcm_budget) { + *out_dst_chunk_rows = chunk_rows; + return true; + } + + // 2. Try smaller chunk bands: 64, 32, 16, 8, 4, 2, 1 + chunk_rows = 64; + while (chunk_rows > 1) { + if (chunk_rows < dst_y) { + htp_upscale_vtcm_layout_build(layout, src_x, src_y, dst_x, dst_y, chunk_rows, inv_sf1, filter_radius1, n_threads); + if (layout->total_bytes <= vtcm_budget) { + *out_dst_chunk_rows = chunk_rows; + return true; + } + } + chunk_rows /= 2; + } + + // 3. Fallback to 1 row + chunk_rows = 1; + htp_upscale_vtcm_layout_build(layout, src_x, src_y, dst_x, dst_y, chunk_rows, inv_sf1, filter_radius1, n_threads); + if (layout->total_bytes <= vtcm_budget) { + *out_dst_chunk_rows = chunk_rows; + return true; + } + + return false; +} + +int op_upscale(struct htp_ops_context * octx); + +#endif // HTP_UPSCALE_OPS_H diff --git a/ggml/src/ggml-hexagon/libggml-htp.inf b/ggml/src/ggml-hexagon/libggml-htp.inf index 874dde1b8878..ff6ac27cdbeb 100644 --- a/ggml/src/ggml-hexagon/libggml-htp.inf +++ b/ggml/src/ggml-hexagon/libggml-htp.inf @@ -18,6 +18,7 @@ libggml-htp-v73.so = 1 libggml-htp-v75.so = 1 libggml-htp-v79.so = 1 libggml-htp-v81.so = 1 +libggml-htp-v85.so = 1 [ControlFlags] ExcludeFromSelect = * @@ -30,6 +31,7 @@ libggml-htp-v73.so,,,0x10 ;COPYFLG_NO_OVERWRITE libggml-htp-v75.so,,,0x10 ;COPYFLG_NO_OVERWRITE libggml-htp-v79.so,,,0x10 ;COPYFLG_NO_OVERWRITE libggml-htp-v81.so,,,0x10 ;COPYFLG_NO_OVERWRITE +libggml-htp-v85.so,,,0x10 ;COPYFLG_NO_OVERWRITE [Strings] GGML = 'GGML' diff --git a/ggml/src/ggml-impl.h b/ggml/src/ggml-impl.h index ae26e0c23b46..4dc55e78e218 100644 --- a/ggml/src/ggml-impl.h +++ b/ggml/src/ggml-impl.h @@ -512,6 +512,7 @@ static inline float ggml_e8m0_to_fp32_half(uint8_t x) { // UE4M3: unsigned, 4 exp bits (bias=7), 3 mantissa bits // Returns value * 0.5 to match kvalues_mxfp4 convention (kvalues = 2 * E2M1_float) static inline float ggml_ue4m3_to_fp32(uint8_t x) { + // TODO: reject invalid unsigned E4M3 scales instead of decoding NaN as zero or ignoring the sign bit. if (x == 0 || x == 0x7F) { return 0.0f; } @@ -527,6 +528,7 @@ static inline float ggml_ue4m3_to_fp32(uint8_t x) { } static inline uint8_t ggml_fp32_to_ue4m3(float x) { + // TODO: use ties-to-even rounding, allow subnormal carry, and preserve finite values with exponent field 15. if (!(x > 0.0f)) { return 0; } @@ -564,6 +566,62 @@ static inline uint8_t ggml_fp32_to_ue4m3(float x) { return (uint8_t) ((ue4m3_exp << 3) | ue4m3_man); } +static inline float ggml_f8_e4m3_to_fp32(uint8_t x) { + const uint8_t ax = x & 0x7F; + if (ax == 0x7F) { + // OCP FP8 defines both 0x7F and 0xFF as NaN; the sign need not be preserved. + return NAN; + } + + const int exp = (ax >> 3) & 0xF; + const int man = ax & 0x7; + // OCP FP8 rev. 1.1, section 5.1: subnormal magnitude = M * 2^-9; normal magnitude = (1 + M / 8) * 2^(E - 7). + const float value = exp == 0 + ? ldexpf((float) man, -9) + : ldexpf(1.0f + (float) man / 8.0f, exp - 7); + return x & 0x80 ? -value : value; +} + +static inline int ggml_round_to_nearest_even(float x) { + const int value = (int) floorf(x); + const float fraction = x - value; + return fraction > 0.5f || (fraction == 0.5f && (value & 1)) ? value + 1 : value; +} + +// Supports saturating conversion only; infinities and overflow clamp to +/-448. +static inline uint8_t ggml_fp32_to_f8_e4m3(float x) { + const uint8_t sign = signbit(x) ? 0x80 : 0; + x = fabsf(x); + + if (isnan(x)) { + // OCP FP8 leaves NaN sign handling to the implementation; use canonical 0x7F. + return 0x7F; + } + if (x == 0.0f) { + return sign; + } + if (isinf(x) || x >= 448.0f) { + return sign | 0x7E; + } + if (x < 0.015625f) { + // OCP FP8 rev. 1.1, section 5.1: subnormal magnitude = M * 2^(1 - bias - m) = M / 512. + return sign | (uint8_t) ggml_round_to_nearest_even(x * 512.0f); + } + + int exp; + const float mantissa = frexpf(x, &exp) * 2.0f; + int encoded_exp = exp + 6; + int encoded_man = ggml_round_to_nearest_even((mantissa - 1.0f) * 8.0f); + if (encoded_man == 8) { + encoded_man = 0; + encoded_exp++; + } + if (encoded_exp > 15 || (encoded_exp == 15 && encoded_man > 6)) { + return sign | 0x7E; + } + return sign | (uint8_t) (encoded_exp << 3) | (uint8_t) encoded_man; +} + /** * Converts brain16 to float32. * diff --git a/ggml/src/ggml-metal/CMakeLists.txt b/ggml/src/ggml-metal/CMakeLists.txt index 05cdea156316..91691b223669 100644 --- a/ggml/src/ggml-metal/CMakeLists.txt +++ b/ggml/src/ggml-metal/CMakeLists.txt @@ -45,6 +45,7 @@ set(METALLIB_KERNEL_SOURCES kernels/fa_q5_0.metal kernels/fa_q5_1.metal kernels/fa_q8_0.metal + kernels/fa_tensor.metal kernels/fa_vec_f16.metal kernels/fa_vec_f32.metal kernels/fa_vec_q4_0.metal @@ -233,12 +234,12 @@ else() VERBATIM ) - set(AIR_FA_TENSOR "${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/fa_f16_tensor.air") + set(AIR_FA_TENSOR "${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/fa_tensor_tensor.air") add_custom_command( OUTPUT ${AIR_FA_TENSOR} - COMMAND xcrun -sdk ${METAL_SDK} metal ${XC_FLAGS_TENSOR} -DGGML_METAL_HAS_TENSOR -I ${CMAKE_RUNTIME_OUTPUT_DIRECTORY} -c ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/kernels/fa_f16.metal -o ${AIR_FA_TENSOR} - DEPENDS kernels/fa_f16.metal ${METALLIB_KERNELS_FA_SHARED} kernels/common.h kernels/dequantize.h ${METALLIB_COMMON} ggml-metal-impl.h - COMMENT "Compiling kernels/fa_f16.metal (tensor API)" + COMMAND xcrun -sdk ${METAL_SDK} metal ${XC_FLAGS_TENSOR} -DGGML_METAL_HAS_TENSOR -I ${CMAKE_RUNTIME_OUTPUT_DIRECTORY} -c ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/kernels/fa_tensor.metal -o ${AIR_FA_TENSOR} + DEPENDS kernels/fa_tensor.metal kernels/common.h ${METALLIB_COMMON} ggml-metal-impl.h + COMMENT "Compiling kernels/fa_tensor.metal (tensor API)" VERBATIM ) diff --git a/ggml/src/ggml-metal/ggml-metal-context.m b/ggml/src/ggml-metal/ggml-metal-context.m index e9064666f628..597c126ca3f7 100644 --- a/ggml/src/ggml-metal/ggml-metal-context.m +++ b/ggml/src/ggml-metal/ggml-metal-context.m @@ -539,8 +539,14 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * descriptor.outputURL = [NSURL fileURLWithPath:path]; NSError * error = nil; - if (![[MTLCaptureManager sharedCaptureManager] startCaptureWithDescriptor:descriptor error:&error]) { + const bool ok = [[MTLCaptureManager sharedCaptureManager] startCaptureWithDescriptor:descriptor error:&error]; + + [descriptor release]; + + if (!ok) { GGML_LOG_ERROR("%s: error: unable to start capture '%s' (did you set METAL_CAPTURE_ENABLED=1 ?)\n", __func__, [[error localizedDescription] UTF8String]); + [ctx->capture_scope release]; + ctx->capture_scope = nil; } else { [ctx->capture_scope beginScope]; ctx->capture_started = true; @@ -600,6 +606,8 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * // enter here only when capturing in order to wait for all computation to finish // otherwise, we leave the graph to compute asynchronously if (use_capture && ctx->capture_started) { + enum ggml_status res = GGML_STATUS_SUCCESS; + // wait for completion and check status of each command buffer // needed to detect if the device ran out-of-memory for example (#1881) { @@ -613,11 +621,11 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); } - return GGML_STATUS_FAILED; + res = GGML_STATUS_FAILED; } } - for (int i = 0; i < n_cb; ++i) { + for (int i = 0; i < n_cb && res == GGML_STATUS_SUCCESS; ++i) { id cmd_buf = ctx->cmd_bufs[i].obj; [cmd_buf waitUntilCompleted]; @@ -627,8 +635,8 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * if (status == MTLCommandBufferStatusError) { GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); } - - return GGML_STATUS_FAILED; + res = GGML_STATUS_FAILED; + break; } id next_buffer = (i + 1 < n_cb ? ctx->cmd_bufs[i + 1].obj : nil); @@ -643,7 +651,8 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * if (ctx->abort_callback && ctx->abort_callback(ctx->abort_callback_data)) { GGML_LOG_INFO("%s: command buffer %d aborted", __func__, i); - return GGML_STATUS_ABORTED; + res = GGML_STATUS_ABORTED; + break; } [next_buffer commit]; @@ -652,7 +661,14 @@ enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * [ctx->capture_scope endScope]; [[MTLCaptureManager sharedCaptureManager] stopCapture]; + [ctx->capture_scope release]; + ctx->capture_scope = nil; + ctx->capture_started = false; + + if (res != GGML_STATUS_SUCCESS) { + return res; + } } } diff --git a/ggml/src/ggml-metal/ggml-metal-device.cpp b/ggml/src/ggml-metal/ggml-metal-device.cpp index b70129de8f19..463d57c7b111 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.cpp +++ b/ggml/src/ggml-metal/ggml-metal-device.cpp @@ -507,6 +507,47 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_lightning_indexe return res; } +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_top_k_mask( + ggml_metal_library_t lib, + const ggml_tensor * op, + bool fill, + bool has_score, + bool has_blocks, + bool has_extra, + bool vec) { + GGML_ASSERT(op->op == GGML_OP_TOP_K_MASK); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_top_k_mask%s_%s", fill ? "_fill" : "", ggml_type_name(op->type)); + + ggml_metal_pipeline_with_params res; + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + if (fill) { + snprintf(name, 256, "%s_vec=%d", base, vec ? 1 : 0); + + ggml_metal_cv_set_bool(cv, vec, FC_TOP_K_MASK + 3); + } else { + snprintf(name, 256, "%s_sc=%d_bl=%d_ex=%d", base, has_score ? 1 : 0, has_blocks ? 1 : 0, has_extra ? 1 : 0); + + ggml_metal_cv_set_bool(cv, has_score, FC_TOP_K_MASK + 0); + ggml_metal_cv_set_bool(cv, has_blocks, FC_TOP_K_MASK + 1); + ggml_metal_cv_set_bool(cv, has_extra, FC_TOP_K_MASK + 2); + } + + res = ggml_metal_library_get_pipeline(lib, name); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + } + + ggml_metal_cv_free(cv); + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_dsv4_hc(ggml_metal_library_t lib, const ggml_tensor * op) { char name[256]; const char * base = nullptr; @@ -1062,7 +1103,6 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv(ggml_meta { nsg = N_SG_MXFP4; nr0 = N_R0_MXFP4; - smem = 32*sizeof(float); } break; case GGML_TYPE_Q2_K: { @@ -1225,40 +1265,6 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv(ggml_meta return res; } -ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_amax_part(ggml_metal_library_t lib) { - char base[256]; - char name[256]; - - snprintf(base, 256, "kernel_mul_mm_id_amax_part_f32"); - snprintf(name, 256, "%s", base); - - ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); - if (!res.pipeline) { - res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); - } - - res.smem = 32*sizeof(float); - - return res; -} - -ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_amax(ggml_metal_library_t lib) { - char base[256]; - char name[256]; - - snprintf(base, 256, "kernel_mul_mm_id_amax_f32"); - snprintf(name, 256, "%s", base); - - ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); - if (!res.pipeline) { - res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); - } - - res.smem = 32*sizeof(float); - - return res; -} - ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_map0(ggml_metal_library_t lib, int ne02, int ne20) { char base[256]; char name[256]; @@ -1283,6 +1289,15 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_map0(g return res; } +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_zero(ggml_metal_library_t lib) { + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, "kernel_mul_mm_id_zero"); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, "kernel_mul_mm_id_zero", "kernel_mul_mm_id_zero", nullptr); + } + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id(ggml_metal_library_t lib, const ggml_tensor * op) { char base[256]; char name[256]; @@ -1292,18 +1307,14 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id(ggml_m const bool bc_inp = op->src[0]->ne[0] % 32 != 0; - // src1 prec [TAG_GGML_PREC] - const bool amax = ggml_get_op_params_i32(op, 3) == GGML_PREC_F32; - snprintf(base, 256, "kernel_mul_mm_id_%s_%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1)); - snprintf(name, 256, "%s_bci=%d_amax=%d", base, bc_inp, amax); + snprintf(name, 256, "%s_bci=%d", base, bc_inp); ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); if (!res.pipeline) { ggml_metal_cv_t cv = ggml_metal_cv_init(); ggml_metal_cv_set_bool(cv, bc_inp, FC_MUL_MM + 0); - ggml_metal_cv_set_bool(cv, amax, FC_MUL_MM + 6); res = ggml_metal_library_compile_pipeline(lib, base, name, cv); @@ -1387,7 +1398,6 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_id(ggml_m { nsg = N_SG_MXFP4; nr0 = N_R0_MXFP4; - smem = 32*sizeof(float); } break; case GGML_TYPE_Q2_K: { @@ -1567,6 +1577,28 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax(ggml_meta return res; } +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax_part(ggml_metal_library_t lib) { + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, "kernel_argmax_part_f32"); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, "kernel_argmax_part_f32", "kernel_argmax_part_f32", nullptr); + } + + res.smem = 32*(sizeof(float) + sizeof(int32_t)); + + return res; +} + +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax_final(ggml_metal_library_t lib) { + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, "kernel_argmax_final_f32"); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, "kernel_argmax_final_f32", "kernel_argmax_final_f32", nullptr); + } + + res.smem = 32*(sizeof(float) + sizeof(int32_t)); + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argsort(ggml_metal_library_t lib, const ggml_tensor * op) { assert(op->op == GGML_OP_ARGSORT); @@ -1866,7 +1898,9 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_t const int32_t dk = (int32_t) op->src[1]->ne[0]; const int32_t dv = (int32_t) op->src[2]->ne[0]; - snprintf(base, 256, "kernel_flash_attn_ext_tensor_f16_dk%d_dv%d", dk, dv); + const char * type = op->src[1]->type == GGML_TYPE_BF16 ? "bf16" : "f16"; + + snprintf(base, 256, "kernel_flash_attn_ext_tensor_%s_dk%d_dv%d", type, dk, dv); snprintf(name, 256, "%s_mask=%d_sinks=%d_bias=%d_scap=%d", base, has_mask, has_sinks, has_bias, has_scap); ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); @@ -1953,6 +1987,23 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext( return res; } +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_rows( + ggml_metal_library_t lib, + const ggml_tensor * op) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + const char * base = "kernel_flash_attn_ext_rows"; + + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, base); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, base, base, nullptr); + } + + GGML_UNUSED(op); + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_vec_idx( ggml_metal_library_t lib, const ggml_tensor * op) { @@ -1982,6 +2033,7 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_v bool has_scap, bool has_kvpad, bool has_sparse, + bool has_rows, int32_t nqpsg, int32_t ne, int32_t nsg, @@ -2011,7 +2063,7 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_v dv, qne_suffix); - snprintf(name, 256, "%s_mask=%d_sink=%d_bias=%d_scap=%d_kvpad=%d_sparse=%d_ns10=%d_ns20=%d_nsg=%d_nwg=%d", + snprintf(name, 256, "%s_mask=%d_sink=%d_bias=%d_scap=%d_kvpad=%d_sparse=%d_rows=%d_ns10=%d_ns20=%d_nsg=%d_nwg=%d", base, has_mask, has_sinks, @@ -2019,6 +2071,7 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_v has_scap, has_kvpad, has_sparse, + has_rows, ns10, ns20, nsg, nwg); @@ -2033,6 +2086,7 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_v ggml_metal_cv_set_bool(cv, has_scap, FC_FLASH_ATTN_EXT_VEC + 3); ggml_metal_cv_set_bool(cv, has_kvpad, FC_FLASH_ATTN_EXT_VEC + 4); ggml_metal_cv_set_bool(cv, has_sparse, FC_FLASH_ATTN_EXT_VEC + 5); + ggml_metal_cv_set_bool(cv, has_rows, FC_FLASH_ATTN_EXT_VEC + 6); ggml_metal_cv_set_int32(cv, ns10, FC_FLASH_ATTN_EXT_VEC + 20); ggml_metal_cv_set_int32(cv, ns20, FC_FLASH_ATTN_EXT_VEC + 21); diff --git a/ggml/src/ggml-metal/ggml-metal-device.h b/ggml/src/ggml-metal/ggml-metal-device.h index 4012b9d5f69b..e096d611be95 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.h +++ b/ggml/src/ggml-metal/ggml-metal-device.h @@ -126,6 +126,7 @@ struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_cumsum_ad struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_tri (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_soft_max (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_lightning_indexer (ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_top_k_mask (ggml_metal_library_t lib, const struct ggml_tensor * op, bool fill, bool has_score, bool has_blocks, bool has_extra, bool vec); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_dsv4_hc (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_ssm_conv (ggml_metal_library_t lib, const struct ggml_tensor * op, int32_t nc, bool use_silu); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_ssm_conv_batched (ggml_metal_library_t lib, const struct ggml_tensor * op, int ssm_conv_bs, int32_t nc, bool use_silu); @@ -140,11 +141,12 @@ struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_mm struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_map0 (ggml_metal_library_t lib, int ne02, int ne20); -struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_amax(ggml_metal_library_t lib); -struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_amax_part(ggml_metal_library_t lib); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_zero (ggml_metal_library_t lib); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_id (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax (ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax_part (ggml_metal_library_t lib); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argmax_final (ggml_metal_library_t lib); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argsort (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_argsort_merge (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_fwht (ggml_metal_library_t lib, int n, enum ggml_type tsrc); @@ -217,6 +219,10 @@ struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_att int32_t ns10, int32_t ns20); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_rows( + ggml_metal_library_t lib, + const struct ggml_tensor * op); + struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_vec_idx( ggml_metal_library_t lib, const struct ggml_tensor * op); @@ -230,6 +236,7 @@ struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_att bool has_scap, bool has_kvpad, bool has_sparse, + bool has_rows, int32_t nqpsg, int32_t ne, int32_t nsg, @@ -360,7 +367,10 @@ bool ggml_metal_buffer_is_shared(ggml_metal_buffer_t buf); void ggml_metal_buffer_memset_tensor(ggml_metal_buffer_t buf, struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size); void ggml_metal_buffer_set_tensor (ggml_metal_buffer_t buf, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size); void ggml_metal_buffer_get_tensor (ggml_metal_buffer_t buf, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size); +void ggml_metal_buffer_set_tensor_n (ggml_metal_buffer_t buf, struct ggml_tensor * const * tensors, const void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors); +void ggml_metal_buffer_get_tensor_n (ggml_metal_buffer_t buf, const struct ggml_tensor * const * tensors, void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors); bool ggml_metal_buffer_cpy_tensor (ggml_metal_buffer_t buf, const struct ggml_tensor * src, struct ggml_tensor * dst); +bool ggml_metal_buffer_cpy_tensor_n (ggml_metal_buffer_t buf, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors); void ggml_metal_buffer_clear (ggml_metal_buffer_t buf, uint8_t value); // finds the Metal buffer that contains the tensor data on the GPU device diff --git a/ggml/src/ggml-metal/ggml-metal-device.m b/ggml/src/ggml-metal/ggml-metal-device.m index 9fe0c2540c85..c8e02b10668e 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.m +++ b/ggml/src/ggml-metal/ggml-metal-device.m @@ -118,6 +118,7 @@ int ggml_metal_pipeline_max_theads_per_threadgroup(struct ggml_metal_pipeline_wi X(FA_Q5_0, fa_q5_0) \ X(FA_Q5_1, fa_q5_1) \ X(FA_Q8_0, fa_q8_0) \ + X(FA_TENSOR, fa_tensor) \ X(FA_VEC_F16, fa_vec_f16) \ X(FA_VEC_F32, fa_vec_f32) \ X(FA_VEC_Q4_0, fa_vec_q4_0) \ @@ -1515,6 +1516,7 @@ static bool ggml_metal_supports_mul_mat_op( bool src0_f16_has_mv, bool mm_path) { if (!has_simdgroup_reduction || + op->src[0]->type == GGML_TYPE_F8_E4M3 || op->src[0]->type == GGML_TYPE_NVFP4 || op->src[0]->type == GGML_TYPE_TQ1_0) { return false; @@ -1554,6 +1556,7 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te switch (op->op) { case GGML_OP_SCALE: + return ggml_is_contiguous_rows(op->src[0]) && (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_BF16); case GGML_OP_FILL: case GGML_OP_CLAMP: case GGML_OP_SQR: @@ -1724,6 +1727,39 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te case GGML_OP_ROLL: return ggml_is_contiguous(op->src[0]); case GGML_OP_FLASH_ATTN_EXT: + // K/V row lists (ggml_flash_attn_ext_rows): one list of cache rows per q slice + if (op->src[5] != NULL) { + const struct ggml_tensor * kv_rows = op->src[5]; + + if (kv_rows->type != GGML_TYPE_I32 || + !ggml_is_contiguous(kv_rows) || + kv_rows->ne[2] != 1 || kv_rows->ne[3] != 1 || + kv_rows->ne[1] != op->src[0]->ne[3] || + !op->src[3] || op->src[1]->ne[3] != 1 || op->src[2]->ne[3] != 1) { + return false; + } + + // the non-vec kernels attend over a contiguous F16 copy of the referenced rows: + // - F16 K/V is gathered directly + // - quantized K/V is first dequantized with kernel_flash_attn_ext_kv_*_f16 + // - other types keep attending to the whole cache (dense mask) + switch (op->src[1]->type) { + case GGML_TYPE_F16: + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: + case GGML_TYPE_Q8_0: + break; + default: + return false; + } + + // the row gather copies F16 values in groups of 4 + if (op->src[2]->ne[0] % 4 != 0) { + return false; + } + } // for new head sizes, add checks here if (op->src[0]->ne[0] != 32 && op->src[0]->ne[0] != 40 && @@ -1833,6 +1869,15 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te ggml_is_contiguous_rows(op->src[1]) && ggml_is_contiguous_rows(op->src[2]) && (op->src[3] == NULL || ggml_is_contiguous_rows(op->src[3])); + case GGML_OP_TOP_K_MASK: + return (op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32) && + op->src[0]->type == op->type && + op->src[0]->nb[0] == ggml_type_size(op->src[0]->type) && + op->nb[0] == ggml_type_size(op->type) && + op->src[1]->type == GGML_TYPE_I32 && + (op->src[2] == NULL || op->src[2]->type == GGML_TYPE_F32) && + (op->src[3] == NULL || op->src[3]->type == GGML_TYPE_I32) && + (op->src[4] == NULL || op->src[4]->type == GGML_TYPE_I32); case GGML_OP_SSM_CONV: // the channels-major input layout is only implemented on CPU/CUDA return has_simdgroup_reduction && ggml_ssm_conv_get_layout(op) == GGML_SSM_CONV_LAYOUT_TIME_MAJOR; @@ -1923,7 +1968,8 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te } case GGML_OP_GET_ROWS: return op->src[0]->type != GGML_TYPE_NVFP4 && - op->src[0]->type != GGML_TYPE_TQ1_0; + op->src[0]->type != GGML_TYPE_TQ1_0 && + op->src[0]->type != GGML_TYPE_F8_E4M3; case GGML_OP_SET_ROWS: { if (op->src[0]->type == GGML_TYPE_F16) { @@ -2090,19 +2136,11 @@ static void ggml_metal_buffer_rset_free(ggml_metal_buffer_t buf) { static void * ggml_metal_host_malloc(size_t n) { void * data = NULL; -#if TARGET_OS_OSX kern_return_t err = vm_allocate((vm_map_t) mach_task_self(), (void *) &data, n, VM_FLAGS_ANYWHERE); if (err != KERN_SUCCESS) { GGML_LOG_ERROR("%s: error: vm_allocate failed\n", __func__); return NULL; } -#else - const int result = posix_memalign((void **) &data, sysconf(_SC_PAGESIZE), n); - if (result != 0) { - GGML_LOG_ERROR("%s: error: posix_memalign failed\n", __func__); - return NULL; - } -#endif return data; } @@ -2284,11 +2322,7 @@ void ggml_metal_buffer_free(ggml_metal_buffer_t buf) { } if (buf->is_shared && buf->owned) { -#if TARGET_OS_OSX vm_deallocate((vm_map_t)mach_task_self(), (vm_address_t)buf->all_data, buf->all_size); -#else - free(buf->all_data); -#endif } free(buf); @@ -2426,6 +2460,148 @@ void ggml_metal_buffer_get_tensor(ggml_metal_buffer_t buf, const struct ggml_ten } } +static bool ggml_metal_buffer_data_span(const void * const * data, const size_t * sizes, size_t n_tensors, uintptr_t * min_data, uintptr_t * max_data) { + bool found = false; + + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + + const uintptr_t start = (uintptr_t) data[i]; + const uintptr_t end = start + sizes[i]; + if (!found) { + *min_data = start; + *max_data = end; + found = true; + } else { + if (start < *min_data) { + *min_data = start; + } + if (end > *max_data) { + *max_data = end; + } + } + } + + return found; +} + +void ggml_metal_buffer_set_tensor_n(ggml_metal_buffer_t buf, struct ggml_tensor * const * tensors, const void * const * data, + const size_t * offsets, const size_t * sizes, size_t n_tensors) { + if (buf->is_shared) { + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + memcpy((char *) tensors[i]->data + offsets[i], data[i], sizes[i]); + } + return; + } + + uintptr_t min_data = 0, max_data = 0; + if (!ggml_metal_buffer_data_span(data, sizes, n_tensors, &min_data, &max_data)) { + return; + } + + @autoreleasepool { + void * data_ptr = (void *) min_data; + id buf_src = [buf->dev->mtl_device newBufferWithBytesNoCopy:data_ptr + length:max_data - min_data + options:MTLResourceStorageModeShared + deallocator:nil]; + + GGML_ASSERT(buf_src); + + id cmd_buf = [buf->dev->mtl_queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + + ggml_backend_buffer_t tensor_buf_ggml = tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + ggml_metal_buffer_t tensor_buf = (ggml_metal_buffer_t) tensor_buf_ggml->context; + struct ggml_metal_buffer_id bid_dst = ggml_metal_buffer_get_id(tensor_buf, tensors[i]); + bid_dst.offs += offsets[i]; + + [encoder copyFromBuffer:buf_src + sourceOffset:(uintptr_t) data[i] - min_data + toBuffer:bid_dst.metal + destinationOffset:bid_dst.offs + size:sizes[i]]; + } + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + + [buf_src release]; + } +} + +void ggml_metal_buffer_get_tensor_n(ggml_metal_buffer_t buf, const struct ggml_tensor * const * tensors, void * const * data, + const size_t * offsets, const size_t * sizes, size_t n_tensors) { + if (buf->is_shared) { + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + memcpy(data[i], (const char *) tensors[i]->data + offsets[i], sizes[i]); + } + return; + } + + uintptr_t min_data = 0, max_data = 0; + if (!ggml_metal_buffer_data_span((const void * const *) data, sizes, n_tensors, &min_data, &max_data)) { + return; + } + + @autoreleasepool { + id buf_dst = [buf->dev->mtl_device newBufferWithBytesNoCopy:(void *) min_data + length:max_data - min_data + options:MTLResourceStorageModeShared + deallocator:nil]; + + GGML_ASSERT(buf_dst); + + id cmd_buf = [buf->dev->mtl_queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + for (size_t i = 0; i < n_tensors; i++) { + if (sizes[i] == 0) { + continue; + } + + ggml_backend_buffer_t tensor_buf_ggml = tensors[i]->view_src ? tensors[i]->view_src->buffer : tensors[i]->buffer; + ggml_metal_buffer_t tensor_buf = (ggml_metal_buffer_t) tensor_buf_ggml->context; + struct ggml_metal_buffer_id bid_src = ggml_metal_buffer_get_id(tensor_buf, tensors[i]); + bid_src.offs += offsets[i]; + + [encoder copyFromBuffer:bid_src.metal + sourceOffset:bid_src.offs + toBuffer:buf_dst + destinationOffset:(uintptr_t) data[i] - min_data + size:sizes[i]]; + } + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + + [buf_dst release]; + } +} + bool ggml_metal_buffer_cpy_tensor(ggml_metal_buffer_t buf_dst, const struct ggml_tensor * src, struct ggml_tensor * dst) { ggml_metal_buffer_t buf_src = (ggml_metal_buffer_t)src->buffer->context; @@ -2467,6 +2643,74 @@ bool ggml_metal_buffer_cpy_tensor(ggml_metal_buffer_t buf_dst, const struct ggml return true; } +bool ggml_metal_buffer_cpy_tensor_n(ggml_metal_buffer_t buf_dst, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors) { + if (n_tensors == 0) { + return true; + } + + bool all_shared = true; + for (size_t i = 0; i < n_tensors; ++i) { + ggml_backend_buffer_t src_buf = srcs[i]->view_src ? srcs[i]->view_src->buffer : srcs[i]->buffer; + ggml_metal_buffer_t buf_src = (ggml_metal_buffer_t) src_buf->context; + if (!buf_dst->is_shared || !buf_src->is_shared) { + all_shared = false; + break; + } + } + + if (all_shared) { + for (size_t i = 0; i < n_tensors; ++i) { + memcpy(dsts[i]->data, srcs[i]->data, ggml_nbytes(srcs[i])); + } + return true; + } + + // for private buffers, we need to use Metal blit commands + @autoreleasepool { + struct ggml_metal_buffer_id * bid_srcs = malloc(n_tensors * sizeof(struct ggml_metal_buffer_id)); + struct ggml_metal_buffer_id * bid_dsts = malloc(n_tensors * sizeof(struct ggml_metal_buffer_id)); + + for (size_t i = 0; i < n_tensors; ++i) { + ggml_backend_buffer_t src_buf = srcs[i]->view_src ? srcs[i]->view_src->buffer : srcs[i]->buffer; + ggml_backend_buffer_t dst_buf = dsts[i]->view_src ? dsts[i]->view_src->buffer : dsts[i]->buffer; + ggml_metal_buffer_t buf_src = (ggml_metal_buffer_t) src_buf->context; + ggml_metal_buffer_t buf_dst_i = (ggml_metal_buffer_t) dst_buf->context; + bid_srcs[i] = ggml_metal_buffer_get_id(buf_src, srcs[i]); + bid_dsts[i] = ggml_metal_buffer_get_id(buf_dst_i, dsts[i]); + + if (bid_srcs[i].metal == nil || bid_dsts[i].metal == nil) { + free(bid_srcs); + free(bid_dsts); + return false; + } + } + + id cmd_buf = [buf_dst->dev->mtl_queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + for (size_t i = 0; i < n_tensors; ++i) { + [encoder copyFromBuffer:bid_srcs[i].metal + sourceOffset:bid_srcs[i].offs + toBuffer:bid_dsts[i].metal + destinationOffset:bid_dsts[i].offs + size:ggml_nbytes(srcs[i])]; + } + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + + free(bid_srcs); + free(bid_dsts); + } + + return true; +} + void ggml_metal_buffer_clear(ggml_metal_buffer_t buf, uint8_t value) { if (buf->is_shared) { memset(buf->all_data, value, buf->all_size); diff --git a/ggml/src/ggml-metal/ggml-metal-fusion.cpp b/ggml/src/ggml-metal/ggml-metal-fusion.cpp index d78ca7c4b7fd..020cad29d198 100644 --- a/ggml/src/ggml-metal/ggml-metal-fusion.cpp +++ b/ggml/src/ggml-metal/ggml-metal-fusion.cpp @@ -636,6 +636,11 @@ static bool ggml_metal_fusion_check_moe_reduce( if (!match.experts->data || !match.weights->data || !match.dst->data) { return false; } + + // the fused kernel reads experts and weights while writing dst, so dst must not overlap either input + if (ggml_metal_fusion_overlap(match.dst, match.experts) || ggml_metal_fusion_overlap(match.dst, match.weights)) { + return false; + } } return true; diff --git a/ggml/src/ggml-metal/ggml-metal-impl.h b/ggml/src/ggml-metal/ggml-metal-impl.h index 4ffb5a77ddfb..11c15feffe06 100644 --- a/ggml/src/ggml-metal/ggml-metal-impl.h +++ b/ggml/src/ggml-metal/ggml-metal-impl.h @@ -14,7 +14,8 @@ #define N_MM_SIMD_GROUP_X 2 #define N_MM_SIMD_GROUP_Y 2 -#define N_MM_NPART_AMAX 256 +#define N_ARGMAX_NPART_MAX 256 +#define N_ARGMAX_CHUNK 4096 // kernel parameters for mat-vec threadgroups // @@ -124,6 +125,7 @@ #define FC_FLASH_ATTN_EXT_TENSOR 2200 #define FC_LIGHTNING_INDEXER 2200 #define FC_MUL_MV_MMA 2300 +#define FC_TOP_K_MASK 2400 // op-specific constants #define OP_FLASH_ATTN_EXT_NQPSG 8 @@ -383,6 +385,19 @@ typedef struct { int32_t nblocks; } ggml_metal_kargs_flash_attn_ext_kv_f16; +// gather the K/V cache rows referenced by the kv_rows lists into contiguous F16 buffers +typedef struct { + int32_t ne11; // number of rows per list (n_kv_rows) + int32_t ne_12_2; // number of K/V heads + int32_t ne10; // DK + int32_t ne20; // DV, set to 0 to skip gathering V (V is a view of K) + uint64_t v_off; // byte offset of the gathered V region in dst + uint64_t nb11; // K source strides (ne13 = 1: the cache is shared by all streams) + uint64_t nb12; + uint64_t nb21; // V source strides (ne23 = 1) + uint64_t nb22; +} ggml_metal_kargs_flash_attn_ext_rows; + typedef struct { int32_t ne11; int32_t ne_12_2; // assume K and V are same shape @@ -570,12 +585,11 @@ typedef struct { } ggml_metal_kargs_mul_mm_id_map0; typedef struct { - int32_t ne00; - int32_t ne01; - int32_t ne02; - uint64_t nb01; - uint64_t nb02; -} ggml_metal_kargs_mul_mm_id_amax; + int32_t ne0; + uint64_t nb1; + uint64_t nb2; + uint64_t nb21; +} ggml_metal_kargs_mul_mm_id_zero; typedef struct { int32_t ne00; @@ -1295,6 +1309,38 @@ typedef struct { uint64_t nbm3; } ggml_metal_kargs_lightning_indexer; +typedef struct { + int32_t n_kv; + int32_t m1; + int32_t m2; + int32_t m3; + int32_t n_top; + int32_t n_pick; + int32_t n_blk; + int32_t n_extra; + int64_t n_elems; + uint64_t nb1; + uint64_t nb2; + uint64_t nb3; + uint64_t nbm1; + uint64_t nbm2; + uint64_t nbm3; + uint64_t nbk0; + uint64_t nbk1; + uint64_t nbk2; + uint64_t nbk3; + uint64_t nbs0; + uint64_t nbs1; + uint64_t nbs2; + uint64_t nbs3; + uint64_t nbb0; + uint64_t nbb1; + uint64_t nbe0; + uint64_t nbe1; + uint64_t nbe2; + uint64_t nbe3; +} ggml_metal_kargs_top_k_mask; + typedef struct { int32_t n_tokens; int32_t n_iter; @@ -1379,8 +1425,10 @@ typedef struct { } ggml_metal_kargs_pool_1d; typedef struct { - int64_t ne00; + int64_t ne00; uint64_t nb01; + int64_t npart; + int64_t ne01; } ggml_metal_kargs_argmax; typedef struct { diff --git a/ggml/src/ggml-metal/ggml-metal-ops.cpp b/ggml/src/ggml-metal/ggml-metal-ops.cpp index 115d73695a0b..cace34bd4578 100644 --- a/ggml/src/ggml-metal/ggml-metal-ops.cpp +++ b/ggml/src/ggml-metal/ggml-metal-ops.cpp @@ -345,6 +345,10 @@ static int ggml_metal_op_encode_impl(ggml_metal_op_t ctx, int idx) { { n_fuse = ggml_metal_op_lightning_indexer(ctx, idx); } break; + case GGML_OP_TOP_K_MASK: + { + n_fuse = ggml_metal_op_top_k_mask(ctx, idx); + } break; case GGML_OP_DSV4_HC_COMB: case GGML_OP_DSV4_HC_PRE: case GGML_OP_DSV4_HC_POST: @@ -895,7 +899,9 @@ int ggml_metal_op_unary(ggml_metal_op_t ctx, int idx) { if (pipeline.cnt) { const int n = pipeline.c4 ? ggml_nelements(op)/4 : ggml_nelements(op); - ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + const int nth = MIN(256, n); + + ggml_metal_encoder_dispatch_threadgroups(enc, (n + nth - 1)/nth, 1, 1, nth, 1, 1); } else { const int nth_max = MIN(256, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); const int nth = MIN(args.ne00, nth_max); @@ -948,7 +954,9 @@ int ggml_metal_op_glu(ggml_metal_op_t ctx, int idx) { const int64_t nrows = ggml_nrows(op->src[0]); - const int32_t nth = std::max(1, std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne00/2)); + // split each row over several threadgroups: with a single row (decode) one threadgroup would run on one GPU core + const int32_t nth = std::max(1, std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), std::min(256, ne0))); + const int32_t nk = (ne0 + nth - 1)/nth; ggml_metal_encoder_set_pipeline(enc, pipeline); ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); @@ -960,7 +968,7 @@ int ggml_metal_op_glu(ggml_metal_op_t ctx, int idx) { } ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); - ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, nth, 1, 1); + ggml_metal_encoder_dispatch_threadgroups(enc, nk, nrows, 1, nth, 1, 1); return 1; } @@ -1424,6 +1432,124 @@ int ggml_metal_op_lightning_indexer(ggml_metal_op_t ctx, int idx) { return 1; } +int ggml_metal_op_top_k_mask(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const ggml_tensor * mask = op->src[0]; + const ggml_tensor * top_k = op->src[1]; + const ggml_tensor * score = op->src[2]; + const ggml_tensor * blocks = op->src[3]; + const ggml_tensor * extra = op->src[4]; + + GGML_ASSERT(op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32); + GGML_ASSERT(mask->type == op->type); + GGML_ASSERT(top_k->type == GGML_TYPE_I32); + GGML_ASSERT(!score || score->type == GGML_TYPE_F32); + GGML_ASSERT(!blocks || blocks->type == GGML_TYPE_I32); + GGML_ASSERT(!extra || extra->type == GGML_TYPE_I32); + + const int32_t n_kv = mask->ne[0]; + const int32_t n_top = (int32_t) top_k->ne[0]; + const int32_t n_pick = blocks ? blocks->ne[1] : score ? score->ne[0] : n_kv; + const int32_t n_blk = blocks ? blocks->ne[0] : 0; + const int32_t n_extra = extra ? extra->ne[0] : 0; + + const ggml_metal_buffer_id bid = ggml_metal_get_buffer_id(op); + + // the vector fill stores 4 elements at a time + const int32_t ts = ggml_type_size(op->type); + const int64_t n_elems = ggml_nelements(op); + + const bool has_score = score != NULL; + const bool has_blocks = blocks != NULL; + const bool has_extra = extra != NULL; + + const bool vec = n_elems % 4 == 0 && bid.offs % (4*ts) == 0; + + ggml_metal_kargs_top_k_mask args = { + /*.n_kv =*/ n_kv, + /*.m1 =*/ (int32_t) mask->ne[1], + /*.m2 =*/ (int32_t) mask->ne[2], + /*.m3 =*/ (int32_t) mask->ne[3], + /*.n_top =*/ n_top, + /*.n_pick =*/ n_pick, + /*.n_blk =*/ n_blk, + /*.n_extra =*/ n_extra, + /*.n_elems =*/ n_elems, + /*.nb1 =*/ op->nb[1], + /*.nb2 =*/ op->nb[2], + /*.nb3 =*/ op->nb[3], + /*.nbm1 =*/ mask->nb[1], + /*.nbm2 =*/ mask->nb[2], + /*.nbm3 =*/ mask->nb[3], + /*.nbk0 =*/ top_k->nb[0], + /*.nbk1 =*/ top_k->nb[1], + /*.nbk2 =*/ top_k->nb[2], + /*.nbk3 =*/ top_k->nb[3], + /*.nbs0 =*/ score ? score->nb[0] : 0, + /*.nbs1 =*/ score ? score->nb[1] : 0, + /*.nbs2 =*/ score ? score->nb[2] : 0, + /*.nbs3 =*/ score ? score->nb[3] : 0, + /*.nbb0 =*/ blocks ? blocks->nb[0] : 0, + /*.nbb1 =*/ blocks ? blocks->nb[1] : 0, + /*.nbe0 =*/ extra ? extra->nb[0] : 0, + /*.nbe1 =*/ extra ? extra->nb[1] : 0, + /*.nbe2 =*/ extra ? extra->nb[2] : 0, + /*.nbe3 =*/ extra ? extra->nb[3] : 0, + }; + + // the fill covers the whole dst, the scatter overwrites the kept cells with the mask values + { + auto pipeline_fill = ggml_metal_library_get_pipeline_top_k_mask(lib, op, true, false, false, false, vec); + + const int64_t n_fill = n_elems/(vec ? 4 : 1); + const int32_t nth_max = ggml_metal_pipeline_max_theads_per_threadgroup(pipeline_fill); + + int nth = 32; // SIMD width + + while (nth < nth_max && nth < n_fill) { + nth *= 2; + } + + ggml_metal_encoder_set_pipeline(enc, pipeline_fill); + ggml_metal_encoder_set_bytes(enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer(enc, bid, 1); + + ggml_metal_encoder_dispatch_threadgroups(enc, (n_fill + nth - 1)/nth, 1, 1, nth, 1, 1); + + ggml_metal_op_concurrency_reset(ctx); + } + + { + auto pipeline = ggml_metal_library_get_pipeline_top_k_mask(lib, op, false, has_score, has_blocks, has_extra, false); + + const int32_t n_max = n_top + n_extra; + const int32_t nth_max = ggml_metal_pipeline_max_theads_per_threadgroup(pipeline); + + int nth = 32; // SIMD width + + while (nth < nth_max && nth < n_max) { + nth *= 2; + } + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes(enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(mask), 1); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(top_k), 2); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(score ? score : mask), 3); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(blocks ? blocks : mask), 4); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(extra ? extra : mask), 5); + ggml_metal_encoder_set_buffer(enc, bid, 6); + + ggml_metal_encoder_dispatch_threadgroups(enc, op->ne[1], op->ne[2], op->ne[3], nth, 1, 1); + } + + return 1; +} + int ggml_metal_op_dsv4_hc(ggml_metal_op_t ctx, int idx) { ggml_tensor * op = ctx->node(idx); @@ -2319,13 +2445,18 @@ int ggml_metal_op_pool_1d(ggml_metal_op_t ctx, int idx) { auto pipeline = ggml_metal_library_get_pipeline_pool_1d(lib, op, op_pool); - const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), (int) np); - const int ntg = (np + nth - 1) / nth; + const int nth = std::min(256, std::max(1, k0)); + const int ntg = (int) np; + + const size_t smem = op_pool == GGML_OP_POOL_AVG ? + 2*32*sizeof(float) : + 32*sizeof(float); ggml_metal_encoder_set_pipeline(enc, pipeline); ggml_metal_encoder_set_bytes (enc, &args_pool_1d, sizeof(args_pool_1d), 0); ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); ggml_metal_encoder_dispatch_threadgroups(enc, ntg, 1, 1, nth, 1, 1); @@ -2807,15 +2938,6 @@ size_t ggml_metal_op_mul_mat_id_extra_ids(const ggml_tensor * op) { return ggml_type_size(GGML_TYPE_I32)*(ne20*ne21 + ne02); } -size_t ggml_metal_op_mul_mat_id_extra_amax(const ggml_tensor * op) { - assert(op->op == GGML_OP_MUL_MAT_ID); - - GGML_UNUSED(op); - - // 2 scaling factors (8 bytes) + N_MM_NPART_AMAX per-threadgroup scales for stage-1 - return 8 + N_MM_NPART_AMAX*sizeof(float); -} - int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { ggml_tensor * op = ctx->node(idx); @@ -2867,39 +2989,6 @@ int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { ggml_metal_buffer_id bid_ids = bid_tpe; bid_ids.offs += ggml_metal_op_mul_mat_id_extra_tpe(op); - ggml_metal_buffer_id bid_amax = bid_ids; - bid_amax.offs += ggml_metal_op_mul_mat_id_extra_ids(op); - - // src1 prec [TAG_GGML_PREC] - const bool use_amax = ggml_get_op_params_i32(op, 3) == GGML_PREC_F32; - - // src1 rescale factors, computed before the matmul - // ref: https://github.com/ggml-org/llama.cpp/pull/26223 - if (use_amax) { - ggml_metal_kargs_mul_mm_id_amax args = { - /*.ne00 =*/ ne10, - /*.ne01 =*/ ne11, - /*.ne02 =*/ ne12, - /*.nb01 =*/ nb11, - /*.nb02 =*/ nb12, - }; - - auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id_amax_part(lib); - - const size_t smem = pipeline.smem; - - GGML_ASSERT(smem <= props_dev->max_theadgroup_memory_size); - - ggml_metal_encoder_set_pipeline(enc, pipeline); - ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); - ggml_metal_encoder_set_buffer (enc, bid_src1, 1); - ggml_metal_encoder_set_buffer (enc, bid_amax, 2); - - ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); - - ggml_metal_encoder_dispatch_threadgroups(enc, N_MM_NPART_AMAX, 1, 1, 256, 1, 1); - } - { ggml_metal_kargs_mul_mm_id_map0 args = { ne10, @@ -2930,20 +3019,28 @@ int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { ggml_metal_encoder_dispatch_threadgroups(enc, 1, 1, 1, ne02, 1, 1); } - ggml_metal_op_concurrency_reset(ctx); + // zero the rows that no expert owns - disjoint from what kernel_mul_mm_id writes + { + ggml_metal_kargs_mul_mm_id_zero args = { + /*.ne0 =*/ ne0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb21 =*/ nb21, + }; - if (use_amax) { - auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id_amax(lib); + auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id_zero(lib); ggml_metal_encoder_set_pipeline(enc, pipeline); - ggml_metal_encoder_set_buffer (enc, bid_amax, 0); - - ggml_metal_encoder_dispatch_threadgroups(enc, 1, 1, 1, 32, 1, 1); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src2, 1); + ggml_metal_encoder_set_buffer (enc, bid_dst, 2); - // the next kernel has to wait for the amax data - ggml_metal_op_concurrency_reset(ctx); + ggml_metal_encoder_dispatch_threadgroups(enc, ne20, ne21, 1, 32, 1, 1); } + // this barrier is always needed because the next kernel has to wait for the id maps to be computed + ggml_metal_op_concurrency_reset(ctx); + { auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id(lib, op); @@ -2972,7 +3069,6 @@ int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { ggml_metal_encoder_set_buffer (enc, bid_tpe, 3); ggml_metal_encoder_set_buffer (enc, bid_ids, 4); ggml_metal_encoder_set_buffer (enc, bid_dst, 5); - ggml_metal_encoder_set_buffer (enc, bid_amax, 6); const size_t smem = pipeline.smem; @@ -3161,11 +3257,14 @@ static bool ggml_metal_op_flash_attn_ext_use_tensor(const ggml_tensor * op, bool return false; } - if (op->src[1]->type != GGML_TYPE_F16 && !ggml_metal_op_flash_attn_ext_use_kv_f16(op)) { + if (op->src[1]->type != GGML_TYPE_F16 && op->src[1]->type != GGML_TYPE_BF16 && !ggml_metal_op_flash_attn_ext_use_kv_f16(op)) { return false; } - return op->src[1]->ne[1] % OP_FLASH_ATTN_EXT_TENSOR_NCPSG == 0; + // with kv_rows, the attention runs over the compacted row lists (padded to 256), not over the cache + const int64_t ne11_attn = op->src[5] ? op->src[5]->ne[0] : op->src[1]->ne[1]; + + return ne11_attn % OP_FLASH_ATTN_EXT_TENSOR_NCPSG == 0; } // returns the n_kv_max hint if the sparse path is available for this op, or 0 otherwise @@ -3174,6 +3273,11 @@ static bool ggml_metal_op_flash_attn_ext_use_tensor(const ggml_tensor * op, bool static int ggml_metal_op_flash_attn_ext_n_kv_max_sparse(const ggml_tensor * op) { assert(op->op == GGML_OP_FLASH_ATTN_EXT); + // K/V row lists are handled by the dense kernels, not by the sparse path + if (op->src[5] != nullptr) { + return 0; + } + int32_t n_kv_max = 0; memcpy(&n_kv_max, ((const int32_t *) op->op_params) + 4, sizeof(n_kv_max)); @@ -3417,6 +3521,32 @@ size_t ggml_metal_op_flash_attn_ext_extra_idx(const ggml_tensor * op) { return GGML_PAD(sizeof(int32_t)*(size_t) n_kv_max_padded*ne31*ne32*ne33, 16); } +// size of the contiguous F16 buffers holding the K/V rows referenced by the kv_rows lists +// the attention over these buffers is a standard dense op (no per-tile gather in the main kernel) +size_t ggml_metal_op_flash_attn_ext_extra_rows(const ggml_tensor * op) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + const ggml_tensor * kv_rows = op->src[5]; + + if (!kv_rows) { + return 0; + } + + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + + const int64_t n_rows = kv_rows->ne[0]; + const int64_t n_slices = kv_rows->ne[1]; + + // note: when V is a view of K, the gathered V is read from the gathered K, so only K is gathered + const bool v_is_view_of_k = ggml_metal_op_flash_attn_ext_v_is_view_of_k(op); + + const size_t k_size = GGML_PAD(sizeof(ggml_fp16_t)*(size_t) ne10*n_rows*ne12*n_slices, 16); + const size_t v_size = v_is_view_of_k ? 0 : GGML_PAD(sizeof(ggml_fp16_t)*(size_t) ne20*n_rows*ne22*n_slices, 16); + + return k_size + v_size; +} + int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { ggml_tensor * op = ctx->node(idx); @@ -3449,6 +3579,22 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { GGML_ASSERT(!op->src[3] || op->src[3]->ne[1] >= op->src[0]->ne[1] && "the Flash-Attention Metal kernel requires the mask to be at least n_queries big"); + // K/V row lists (ggml_flash_attn_ext_rows): src[5] holds one list of cache rows per q slice + // the attention loops then run over the mask columns and read K/V rows through the lists + const ggml_tensor * kv_rows = op->src[5]; + const bool has_rows = kv_rows != nullptr; + + GGML_ASSERT(!has_rows || (kv_rows->type == GGML_TYPE_I32 && ggml_is_contiguous(kv_rows))); + GGML_ASSERT(!has_rows || (kv_rows->ne[1] == ne03 && kv_rows->ne[2] == 1 && kv_rows->ne[3] == 1)); + GGML_ASSERT(!has_rows || op->src[3]); + + // the loop bound over the mask columns / K/V row lists + const int64_t ne11_attn = has_rows ? kv_rows->ne[0] : ne11; + + // the row lists are padded by the KV cache to a multiple of 256, so the pad path never triggers + GGML_ASSERT(!has_rows || ne11_attn % OP_FLASH_ATTN_EXT_NCPSG == 0); + GGML_ASSERT(!has_rows || ne11_attn % OP_FLASH_ATTN_EXT_VEC_NCPSG == 0); + float scale; float max_bias; float logit_softcap; @@ -3463,6 +3609,8 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { const bool has_mask = op->src[3] != NULL; const bool has_sinks = op->src[4] != NULL; + + GGML_ASSERT(!has_rows || has_mask); const bool has_bias = max_bias != 0.0f; const bool has_scap = logit_softcap != 0.0f; @@ -3499,12 +3647,25 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { const bool use_sparse = n_kv_max_sparse > 0; const int n_kv_max_padded = use_sparse ? GGML_PAD(n_kv_max_sparse, OP_FLASH_ATTN_EXT_VEC_NCPSG) : 0; + const bool use_vec = ggml_metal_op_flash_attn_ext_use_vec(op); + + // with kv_rows, the non-vec path gathers the referenced rows into a contiguous F16 buffer and + // attends over it with the F16 kernel - quantized KV is first dequantized with the F16 pass + const bool rows_gather = has_rows && !use_vec; + // the vec kernels dequantize the KV inline; no need for the F16 dequant pass in the sparse path - const bool use_kv_f16 = !use_sparse && ggml_metal_op_flash_attn_ext_use_kv_f16(op); + const bool dequant_kv = !use_sparse && (rows_gather ? + ggml_is_quantized(op->src[1]->type) : ggml_metal_op_flash_attn_ext_use_kv_f16(op)); + + const bool use_kv_f16 = !use_sparse && (rows_gather ? true : dequant_kv); ggml_metal_buffer_id bid_idx = bid_kv_f16; bid_idx.offs += ggml_metal_op_flash_attn_ext_extra_kv_f16(op); + // contiguous K/V buffers holding the rows referenced by the kv_rows lists + ggml_metal_buffer_id bid_rows = bid_idx; + bid_rows.offs += ggml_metal_op_flash_attn_ext_extra_idx(op); + ggml_metal_buffer_id bid_k = bid_src1; ggml_metal_buffer_id bid_v = bid_src2; @@ -3517,7 +3678,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { uint64_t nb22_attn = nb22; uint64_t nb23_attn = nb23; - if (use_kv_f16) { + if (dequant_kv) { assert(ggml_metal_op_flash_attn_ext_extra_kv_f16(op) != 0); const bool v_is_view_of_k = ggml_metal_op_flash_attn_ext_v_is_view_of_k(op); @@ -3605,6 +3766,70 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { } } + // with kv_rows, gather the cache rows referenced by the lists into contiguous F16 buffers + // the attention then runs as a standard dense op over the gathered rows (tensor or half8x8 kernel) + if (rows_gather) { + assert(ggml_metal_op_flash_attn_ext_extra_rows(op) != 0); + + const bool v_is_view_of_k = ggml_metal_op_flash_attn_ext_v_is_view_of_k(op); + + GGML_ASSERT(ne20 % 4 == 0); + + const size_t k_size = GGML_PAD(sizeof(ggml_fp16_t)*(size_t) ne10*ne11_attn*ne12*ne03, 16); + + ggml_metal_kargs_flash_attn_ext_rows args0 = { + /*.ne11 =*/ (int32_t) ne11_attn, + /*.ne_12_2 =*/ ne12, + /*.ne10 =*/ ne10, + /*.ne20 =*/ v_is_view_of_k ? 0 : ne20, // the gathered V is a view of the gathered K + /*.v_off =*/ k_size, + /*.nb11 =*/ nb11_attn, + /*.nb12 =*/ nb12_attn, + /*.nb21 =*/ nb21_attn, + /*.nb22 =*/ nb22_attn, + }; + + auto pipeline0 = ggml_metal_library_get_pipeline_flash_attn_ext_rows(lib, op); + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline0), 64); + + ggml_metal_encoder_set_pipeline(enc, pipeline0); + ggml_metal_encoder_set_bytes (enc, &args0, sizeof(args0), 0); + ggml_metal_encoder_set_buffer (enc, bid_k, 1); + ggml_metal_encoder_set_buffer (enc, bid_v, 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(kv_rows), 3); + ggml_metal_encoder_set_buffer (enc, bid_rows, 4); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne11_attn, ne03, 1, nth, 1, 1); + + ggml_metal_op_concurrency_reset(ctx); + + // contiguous F16 layout of the gathered rows: [DK, n_rows, n_head_kv, n_streams] + bid_k = bid_rows; + + nb10_attn = sizeof(ggml_fp16_t); + nb11_attn = nb10_attn*ne10; + nb12_attn = nb11_attn*ne11_attn; + nb13_attn = nb12_attn*ne12; + + // if V is a view of K, the gathered V is read from the gathered K with K's strides + if (v_is_view_of_k) { + bid_v = bid_k; + + nb20_attn = nb10_attn; + nb21_attn = nb11_attn; + nb22_attn = nb12_attn; + nb23_attn = nb13_attn; + } else { + bid_v = bid_rows; + bid_v.offs += k_size; + + nb20_attn = sizeof(ggml_fp16_t); + nb21_attn = nb20_attn*ne20; + nb22_attn = nb21_attn*ne11_attn; + nb23_attn = nb22_attn*ne22; + } + } + if (!use_sparse && ggml_metal_op_flash_attn_ext_use_tensor(op, props_dev->has_tensor)) { // tensor API kernel const int nqptg = ne00 >= 512 ? OP_FLASH_ATTN_EXT_TENSOR_NQPSG_LARGE : OP_FLASH_ATTN_EXT_TENSOR_NQPSG; // queries per threadgroup @@ -3650,9 +3875,9 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { /*.nb01 =*/ nb01, /*.nb02 =*/ nb02, /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, + /*.ne11 =*/ (int32_t) ne11_attn, /*.ne_12_2 =*/ ne12, - /*.ne_12_3 =*/ ne13, + /*.ne_12_3 =*/ has_rows ? ne03 : ne13, // the gathered K/V holds one copy per stream /*.ns10 =*/ ns10, /*.nb11 =*/ nb11_attn, /*.nb12 =*/ nb12_attn, @@ -3678,7 +3903,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { /*.logit_softcap =*/ logit_softcap, }; - // shared memory layout: queries (half), scores (float), probabilities (half), row scale (float), rescale flag (int) + // shared memory layout: queries (16-bit), scores (float), probabilities (16-bit), row scale (float), rescale flag (int) const size_t smem = GGML_PAD(nqptg*ne00*sizeof(ggml_fp16_t) + nqptg*ncpsg*(sizeof(float) + sizeof(ggml_fp16_t)) + nqptg*sizeof(float) + sizeof(int32_t), 16); auto pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_tensor(lib, op, has_mask, has_sinks, has_bias, has_scap); @@ -3710,7 +3935,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { bool need_sync = false; - const bool has_kvpad = ne11 % ncpsg != 0; + const bool has_kvpad = ne11_attn % ncpsg != 0; if (has_kvpad) { assert(ggml_metal_op_flash_attn_ext_extra_pad(op) != 0); @@ -3810,9 +4035,9 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { /*.nb01 =*/ nb01, /*.nb02 =*/ nb02, /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, + /*.ne11 =*/ (int32_t) ne11_attn, /*.ne_12_2 =*/ ne12, - /*.ne_12_3 =*/ ne13, + /*.ne_12_3 =*/ has_rows ? ne03 : ne13, // the gathered K/V holds one copy per stream /*.ns10 =*/ ns10, /*.nb11 =*/ nb11_attn, /*.nb12 =*/ nb12_attn, @@ -3878,7 +4103,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { bool need_sync = false; - const bool has_kvpad = !use_sparse && ne11 % ncpsg != 0; + const bool has_kvpad = !use_sparse && ne11_attn % ncpsg != 0; if (use_sparse) { assert(ggml_metal_op_flash_attn_ext_extra_idx(op) != 0); @@ -3961,13 +4186,13 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { // queries: Q*NSG*PAD2(ne00, 128) // attn + mask: NSG*4*Q*C // results: 2*NSG*Q*PAD2(ne20, 128) - // sparse idx: NSG*C ints (only when use_sparse) + // sparse idx: NSG*C ints (when use_sparse, or when gathering K/V rows) const int64_t dk_pad = GGML_PAD(ne00, 128); const int64_t dv_pad = GGML_PAD(ne20, 128); auto fa_vec_smem = [&](int64_t nsg, int32_t nqptg) -> size_t { const size_t smem_half = (size_t) (dk_pad + 4*ncpsg + 2*dv_pad)*nqptg*nsg; - return GGML_PAD(smem_half*sizeof(ggml_fp16_t) + (use_sparse ? (size_t) nsg*ncpsg*sizeof(int) : 0), 16); + return GGML_PAD(smem_half*sizeof(ggml_fp16_t) + ((use_sparse || has_rows) ? (size_t) nsg*ncpsg*sizeof(int) : 0), 16); }; int64_t nsg = 1; @@ -3998,7 +4223,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { } else { nwg = 32; nsg = 1; - while (2*nwg*nsg*ncpsg < ne11 && nsg < 4) { + while (2*nwg*nsg*ncpsg < ne11_attn && nsg < 4) { nsg *= 2; } } @@ -4019,7 +4244,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { /*.nb01 =*/ nb01, /*.nb02 =*/ nb02, /*.nb03 =*/ nb03, - /*.ne11 =*/ use_sparse ? n_kv_max_padded : ne11, + /*.ne11 =*/ use_sparse ? n_kv_max_padded : (int32_t) ne11_attn, /*.ne_12_2 =*/ ne12, /*.ne_12_3 =*/ ne13, /*.ns10 =*/ ns10, @@ -4048,7 +4273,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { /*.n_kv_max_padded =*/ n_kv_max_padded, }; - auto pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_vec(lib, op, has_mask, has_sinks, has_bias, has_scap, has_kvpad, use_sparse, nqptg, cfg.NE, nsg, nwg, use_kv_f16, ns10, ns20); + auto pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_vec(lib, op, has_mask, has_sinks, has_bias, has_scap, has_kvpad, use_sparse, has_rows, nqptg, cfg.NE, nsg, nwg, use_kv_f16, ns10, ns20); GGML_ASSERT(nsg*32 <= ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); @@ -4059,7 +4284,7 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { ggml_metal_encoder_set_buffer (enc, bid_v, 3); ggml_metal_encoder_set_buffer (enc, bid_src3, 4); ggml_metal_encoder_set_buffer (enc, bid_src4, 5); - ggml_metal_encoder_set_buffer (enc, use_sparse ? bid_idx : bid_src0, 8); + ggml_metal_encoder_set_buffer (enc, use_sparse ? bid_idx : (has_rows ? ggml_metal_get_buffer_id(kv_rows) : bid_src0), 8); const size_t smem = fa_vec_smem(nsg, nqptg); @@ -4236,7 +4461,9 @@ int ggml_metal_op_bin(ggml_metal_op_t ctx, int idx) { ggml_metal_encoder_set_buffer (enc, bid_dst, 3); if (pipeline.cnt) { - ggml_metal_encoder_dispatch_threadgroups(enc, args.ne0, ggml_nrows(op), 1, 1, 1, 1); + const int nth = MIN(256, args.ne0); + + ggml_metal_encoder_dispatch_threadgroups(enc, (args.ne0 + nth - 1)/nth, ggml_nrows(op), 1, nth, 1, 1); } else { const int nth_max = MIN(256, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); @@ -5421,6 +5648,25 @@ int ggml_metal_op_timestep_embedding(ggml_metal_op_t ctx, int idx) { return 1; } +size_t ggml_metal_op_argmax_extra(const ggml_tensor * op) { + assert(op->op == GGML_OP_ARGMAX); + + const int64_t ne00 = op->src[0]->ne[0]; + const int64_t ne01 = op->src[0]->ne[1]; + + int npart = 1; + if (ne00 > N_ARGMAX_CHUNK) { + npart = (int) std::min(N_ARGMAX_NPART_MAX, (ne00 + N_ARGMAX_CHUNK - 1)/N_ARGMAX_CHUNK); + } + + if (npart == 1) { + return 0; + } + + // partial max + partial argmax for every row + return (sizeof(float) + sizeof(int32_t)) * npart * ne01; +} + int ggml_metal_op_argmax(ggml_metal_op_t ctx, int idx) { ggml_tensor * op = ctx->node(idx); @@ -5432,22 +5678,61 @@ int ggml_metal_op_argmax(ggml_metal_op_t ctx, int idx) { GGML_TENSOR_LOCALS( int32_t, ne, op, ne); GGML_TENSOR_LOCALS(uint64_t, nb, op, nb); + const int64_t nrows = ggml_nrows(op->src[0]); + + int npart = 1; + if (ne00 > N_ARGMAX_CHUNK) { + npart = (int) std::min(N_ARGMAX_NPART_MAX, (ne00 + N_ARGMAX_CHUNK - 1)/N_ARGMAX_CHUNK); + } + ggml_metal_kargs_argmax args = { - /*.ne00 = */ ne00, - /*.nb01 = */ nb01, + /*.ne00 = */ ne00, + /*.nb01 = */ nb01, + /*.npart = */ npart, + /*.ne01 = */ ne01, }; - auto pipeline = ggml_metal_library_get_pipeline_argmax(lib, op); + const size_t smem = 32*(sizeof(float) + sizeof(int32_t)); - const int64_t nrows = ggml_nrows(op->src[0]); + if (npart > 1) { + auto pipeline_part = ggml_metal_library_get_pipeline_argmax_part(lib); + auto pipeline_final = ggml_metal_library_get_pipeline_argmax_final(lib); + + ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(op); + ggml_metal_buffer_id bid_tmp = bid_dst; + bid_tmp.offs += ggml_nbytes(op); + + ggml_metal_encoder_set_pipeline(enc, pipeline_part); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, bid_tmp, 2); + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, npart, nrows, 1, 256, 1, 1); + + ggml_metal_op_concurrency_reset(ctx); + + int nth = 32; // SIMD width + while (nth < npart && nth < 256) { + nth *= 2; + } + + ggml_metal_encoder_set_pipeline(enc, pipeline_final); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_tmp, 1); + ggml_metal_encoder_set_buffer (enc, bid_dst, 2); + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, nth, 1, 1); + + return 1; + } + + auto pipeline = ggml_metal_library_get_pipeline_argmax(lib, op); int nth = 32; // SIMD width while (nth < ne00 && nth*ne01*ne02*ne03 < 256) { nth *= 2; } - const size_t smem = pipeline.smem; - ggml_metal_encoder_set_pipeline(enc, pipeline); ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); diff --git a/ggml/src/ggml-metal/ggml-metal-ops.h b/ggml/src/ggml-metal/ggml-metal-ops.h index 583d1156bf27..47889fa8490a 100644 --- a/ggml/src/ggml-metal/ggml-metal-ops.h +++ b/ggml/src/ggml-metal/ggml-metal-ops.h @@ -36,7 +36,6 @@ size_t ggml_metal_op_mul_mat_id_extra_tpe(const struct ggml_tensor * op); // id map [n_tokens, n_expert] size_t ggml_metal_op_mul_mat_id_extra_ids(const struct ggml_tensor * op); -size_t ggml_metal_op_mul_mat_id_extra_amax(const struct ggml_tensor * op); // return true if we should use the FA vector kernel for this op bool ggml_metal_op_flash_attn_ext_use_vec(const struct ggml_tensor * op); @@ -46,6 +45,9 @@ size_t ggml_metal_op_flash_attn_ext_extra_blk(const struct ggml_tensor * op); size_t ggml_metal_op_flash_attn_ext_extra_tmp(const struct ggml_tensor * op); size_t ggml_metal_op_flash_attn_ext_extra_kv_f16(const struct ggml_tensor * op); size_t ggml_metal_op_flash_attn_ext_extra_idx(const struct ggml_tensor * op); +size_t ggml_metal_op_flash_attn_ext_extra_rows(const struct ggml_tensor * op); + +size_t ggml_metal_op_argmax_extra(const struct ggml_tensor * op); int ggml_metal_op_concat (ggml_metal_op_t ctx, int idx); int ggml_metal_op_repeat (ggml_metal_op_t ctx, int idx); @@ -59,6 +61,7 @@ int ggml_metal_op_get_rows (ggml_metal_op_t ctx, int idx); int ggml_metal_op_set_rows (ggml_metal_op_t ctx, int idx); int ggml_metal_op_diag (ggml_metal_op_t ctx, int idx); int ggml_metal_op_lightning_indexer (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_top_k_mask (ggml_metal_op_t ctx, int idx); int ggml_metal_op_dsv4_hc (ggml_metal_op_t ctx, int idx); int ggml_metal_op_soft_max (ggml_metal_op_t ctx, int idx); int ggml_metal_op_ssm_conv (ggml_metal_op_t ctx, int idx); diff --git a/ggml/src/ggml-metal/ggml-metal.cpp b/ggml/src/ggml-metal/ggml-metal.cpp index 344882e044f3..9bed6421bbdd 100644 --- a/ggml/src/ggml-metal/ggml-metal.cpp +++ b/ggml/src/ggml-metal/ggml-metal.cpp @@ -68,6 +68,22 @@ static void ggml_backend_metal_buffer_shared_get_tensor(ggml_backend_buffer_t bu ggml_metal_buffer_get_tensor(ctx, tensor, data, offset, size); } +static void ggml_backend_metal_buffer_shared_set_tensor_n(ggml_backend_buffer_t buffer, struct ggml_tensor * const * tensors, const void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_set_tensor_n(ctx, tensors, data, offsets, sizes, n_tensors); +} + +static void ggml_backend_metal_buffer_shared_get_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * tensors, void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_get_tensor_n(ctx, tensors, data, offsets, sizes, n_tensors); +} + static bool ggml_backend_metal_buffer_shared_cpy_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * src, ggml_tensor * dst) { ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; @@ -80,6 +96,20 @@ static bool ggml_backend_metal_buffer_shared_cpy_tensor(ggml_backend_buffer_t bu return ggml_metal_buffer_cpy_tensor(ctx, src, dst); } +static bool ggml_backend_metal_buffer_shared_cpy_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + for (size_t i = 0; i < n_tensors; ++i) { + if (!ggml_backend_buffer_is_metal(srcs[i]->buffer)) { + return false; + } + } + + return ggml_metal_buffer_cpy_tensor_n(ctx, srcs, dsts, n_tensors); +} + static void ggml_backend_metal_buffer_shared_clear(ggml_backend_buffer_t buffer, uint8_t value) { ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; @@ -100,6 +130,9 @@ static ggml_backend_buffer_i ggml_backend_metal_buffer_shared_i = { /* .cpy_tensor = */ ggml_backend_metal_buffer_shared_cpy_tensor, /* .clear = */ ggml_backend_metal_buffer_shared_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ ggml_backend_metal_buffer_shared_set_tensor_n, + /* .get_tensor_n = */ ggml_backend_metal_buffer_shared_get_tensor_n, + /* .cpy_tensor_n = */ ggml_backend_metal_buffer_shared_cpy_tensor_n, }; // private buffer @@ -144,6 +177,22 @@ static void ggml_backend_metal_buffer_private_get_tensor(ggml_backend_buffer_t b ggml_metal_buffer_get_tensor(ctx, tensor, data, offset, size); } +static void ggml_backend_metal_buffer_private_set_tensor_n(ggml_backend_buffer_t buffer, struct ggml_tensor * const * tensors, const void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_set_tensor_n(ctx, tensors, data, offsets, sizes, n_tensors); +} + +static void ggml_backend_metal_buffer_private_get_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * tensors, void * const * data, const size_t * offsets, const size_t * sizes, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_get_tensor_n(ctx, tensors, data, offsets, sizes, n_tensors); +} + static bool ggml_backend_metal_buffer_private_cpy_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * src, ggml_tensor * dst) { ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; @@ -156,6 +205,20 @@ static bool ggml_backend_metal_buffer_private_cpy_tensor(ggml_backend_buffer_t b return ggml_metal_buffer_cpy_tensor(ctx, src, dst); } +static bool ggml_backend_metal_buffer_private_cpy_tensor_n(ggml_backend_buffer_t buffer, const struct ggml_tensor * const * srcs, struct ggml_tensor * const * dsts, size_t n_tensors) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + for (size_t i = 0; i < n_tensors; ++i) { + if (!ggml_backend_buffer_is_metal(srcs[i]->buffer)) { + return false; + } + } + + return ggml_metal_buffer_cpy_tensor_n(ctx, srcs, dsts, n_tensors); +} + static void ggml_backend_metal_buffer_private_clear(ggml_backend_buffer_t buffer, uint8_t value) { ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; @@ -176,6 +239,9 @@ static ggml_backend_buffer_i ggml_backend_metal_buffer_private_i = { /* .cpy_tensor = */ ggml_backend_metal_buffer_private_cpy_tensor, /* .clear = */ ggml_backend_metal_buffer_private_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ ggml_backend_metal_buffer_private_set_tensor_n, + /* .get_tensor_n = */ ggml_backend_metal_buffer_private_get_tensor_n, + /* .cpy_tensor_n = */ ggml_backend_metal_buffer_private_cpy_tensor_n, }; static bool ggml_backend_buffer_is_metal(ggml_backend_buffer_t buffer) { @@ -226,7 +292,6 @@ static size_t ggml_backend_metal_buffer_type_get_alloc_size(ggml_backend_buffer_ { res += ggml_metal_op_mul_mat_id_extra_tpe(tensor); res += ggml_metal_op_mul_mat_id_extra_ids(tensor); - res += ggml_metal_op_mul_mat_id_extra_amax(tensor); } break; case GGML_OP_FLASH_ATTN_EXT: { @@ -235,6 +300,7 @@ static size_t ggml_backend_metal_buffer_type_get_alloc_size(ggml_backend_buffer_ res += ggml_metal_op_flash_attn_ext_extra_tmp(tensor); res += ggml_metal_op_flash_attn_ext_extra_kv_f16(tensor); res += ggml_metal_op_flash_attn_ext_extra_idx(tensor); + res += ggml_metal_op_flash_attn_ext_extra_rows(tensor); } break; case GGML_OP_CUMSUM: case GGML_OP_ARGSORT: @@ -245,6 +311,10 @@ static size_t ggml_backend_metal_buffer_type_get_alloc_size(ggml_backend_buffer_ { res = 2*sizeof(int32_t)*ggml_nelements(tensor->src[0]); } break; + case GGML_OP_ARGMAX: + { + res += ggml_metal_op_argmax_extra(tensor); + } break; default: break; } diff --git a/ggml/src/ggml-metal/kernels/binbcast.metal b/ggml/src/ggml-metal/kernels/binbcast.metal index 7c7ab9b5eb94..e125b7a03cfc 100644 --- a/ggml/src/ggml-metal/kernels/binbcast.metal +++ b/ggml/src/ggml-metal/kernels/binbcast.metal @@ -22,8 +22,13 @@ kernel void kernel_bin_fuse_impl( if (FC_RB) { // row broadcast - const uint i0 = tgpig.y*args.ne00 + tgpig.x; - const uint i1 = FC_CB ? tgpig.x%args.ne10 : tgpig.x; + const uint i = tgpig.x*ntg.x + tpitg.x; + if (i >= (uint) args.ne0) { + return; + } + + const uint i0 = tgpig.y*args.ne00 + i; + const uint i1 = FC_CB ? i%args.ne10 : i; device const T0 * src0_row = (device const T0 *) (src0); device T * dst_row = (device T *) (dst); @@ -185,6 +190,14 @@ kernel void kernel_add_id( device float * dst_row = (device float *)((device char *)dst + i1*nb1 + i2*nb2); device const float * src0_row = (device const float *)((device char *)src0 + i1*args.nb01 + i2*args.nb02); + + if (i11 == -1) { + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + dst_row[i0] = src0_row[i0]; + } + return; + } + device const float * src1_row = (device const float *)((device char *)src1 + i11*args.nb11); for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { diff --git a/ggml/src/ggml-metal/kernels/fa_aux.metal b/ggml/src/ggml-metal/kernels/fa_aux.metal index ebee1becd284..6fe47470fb2d 100644 --- a/ggml/src/ggml-metal/kernels/fa_aux.metal +++ b/ggml/src/ggml-metal/kernels/fa_aux.metal @@ -48,6 +48,80 @@ template [[host_name("kernel_flash_attn_ext_kv_q5_0_f16")]] kernel kernel_flash_ template [[host_name("kernel_flash_attn_ext_kv_q5_1_f16")]] kernel kernel_flash_attn_ext_kv_f16_t kernel_flash_attn_ext_kv_f16; template [[host_name("kernel_flash_attn_ext_kv_q8_0_f16")]] kernel kernel_flash_attn_ext_kv_f16_t kernel_flash_attn_ext_kv_f16; +// gather the K/V cache rows referenced by the kv_rows lists into contiguous F16 buffers +// - one threadgroup per (row, stream); the attention is then run as a standard dense op over the +// gathered rows, which avoids the per-tile K/V gather in the main kernels +// - negative rows are padding: filled with zeros, their mask entries are -INF so they contribute nothing +kernel void kernel_flash_attn_ext_rows( + constant ggml_metal_kargs_flash_attn_ext_rows & args, + device const char * k_src, + device const char * v_src, + device const int * rows, + device char * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiitg[[thread_index_in_threadgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { + const int64_t i1 = tgpig[0]; // row index + const int64_t i3 = tgpig[1]; // stream + + const int64_t row = rows[i1 + i3*args.ne11]; + + // gathered layout: [DK, n_rows, n_head_kv, n_streams] and [DV, n_rows, n_head_kv, n_streams] F16 + device half4 * k_dst = (device half4 *) (dst + i3*args.ne_12_2*args.ne11*args.ne10*sizeof(half)); + device half4 * v_dst = (device half4 *) (dst + args.v_off + i3*args.ne_12_2*args.ne11*args.ne20*sizeof(half)); + + // note: the K/V cache is shared by all streams (ne13 = ne23 = 1), the row list selects the rows + // each thread copies up to 4 half4 values (32 bytes) to keep the memory transactions large + + // K: all heads of this row + { + const int64_t per_head = args.ne10/4; + + for (int64_t i = 4*tiitg; i < args.ne_12_2*per_head; i += 4*ntg.x) { + const int64_t i2 = i/per_head; + const int64_t i0 = i%per_head; + const int n = (int) min((int64_t) 4, per_head - i0); + + device half4 * dst4 = k_dst + (i2*args.ne11 + i1)*per_head + i0; + + if (row >= 0) { + device const half4 * src4 = (device const half4 *) (k_src + row*args.nb11 + i2*args.nb12) + i0; + for (int j = 0; j < n; ++j) { + dst4[j] = src4[j]; + } + } else { + for (int j = 0; j < n; ++j) { + dst4[j] = half4(0.0h); + } + } + } + } + + // V: all heads of this row + { + const int64_t per_head = args.ne20/4; + + for (int64_t i = 4*tiitg; i < args.ne_12_2*per_head; i += 4*ntg.x) { + const int64_t i2 = i/per_head; + const int64_t i0 = i%per_head; + const int n = (int) min((int64_t) 4, per_head - i0); + + device half4 * dst4 = v_dst + (i2*args.ne11 + i1)*per_head + i0; + + if (row >= 0) { + device const half4 * src4 = (device const half4 *) (v_src + row*args.nb21 + i2*args.nb22) + i0; + for (int j = 0; j < n; ++j) { + dst4[j] = src4[j]; + } + } else { + for (int j = 0; j < n; ++j) { + dst4[j] = half4(0.0h); + } + } + } + } +} + constant bool FC_flash_attn_ext_pad_has_mask [[function_constant(FC_FLASH_ATTN_EXT_PAD + 0)]]; constant int32_t FC_flash_attn_ext_pad_ncpsg [[function_constant(FC_FLASH_ATTN_EXT_PAD + 25)]]; diff --git a/ggml/src/ggml-metal/kernels/fa_f16.metal b/ggml/src/ggml-metal/kernels/fa_f16.metal index 0f44b419bdea..6e30b09e3a5a 100644 --- a/ggml/src/ggml-metal/kernels/fa_f16.metal +++ b/ggml/src/ggml-metal/kernels/fa_f16.metal @@ -75,291 +75,3 @@ template [[host_name("kernel_flash_attn_ext_bf16_dk576_dv512")]] kernel flash_at #undef FA_TYPES #undef FA_TYPES_BF #undef FA_TYPES_F32 - -#ifdef GGML_METAL_HAS_TENSOR - -constant bool FC_flash_attn_ext_tensor_has_mask [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 0)]]; -constant bool FC_flash_attn_ext_tensor_has_sinks [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 1)]]; -constant bool FC_flash_attn_ext_tensor_has_bias [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 2)]]; -constant bool FC_flash_attn_ext_tensor_has_scap [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 3)]]; - -// ref: https://arxiv.org/pdf/2307.08691.pdf -template< - short DK, // K head size - short DV, // V head size - short Q = OP_FLASH_ATTN_EXT_TENSOR_NQPSG, // queries per threadgroup - short C = OP_FLASH_ATTN_EXT_TENSOR_NCPSG, // cache items per threadgroup - short NSG = OP_FLASH_ATTN_EXT_TENSOR_NSG> // number of simd groups -kernel void kernel_flash_attn_ext_tensor( - constant ggml_metal_kargs_flash_attn_ext & args, - device const char * q, - device const char * k, - device const char * v, - device const char * mask, - device const char * sinks, - device const char * blk, - device char * dst, - threadgroup char * shmem [[threadgroup(0)]], - uint3 tgpig [[threadgroup_position_in_grid]], - ushort tiisg [[thread_index_in_simdgroup]], - ushort sgitg [[simdgroup_index_in_threadgroup]]) { - constexpr short NW = N_SIMDWIDTH; - constexpr short NT = NW*NSG; - constexpr short NQ = Q/NSG; - constexpr short NC = C/NW; // columns per thread - - static_assert(DK % 4 == 0, "DK must be divisible by 4"); - static_assert(Q % NSG == 0, "Q must be divisible by NSG"); - static_assert(C % NW == 0, "C must be divisible by NW"); - - const int iq3 = tgpig[2]; - const int iq2 = tgpig[1]; - const int iq1 = tgpig[0]*Q; - - const short tiitg = sgitg*NW + tiisg; - - threadgroup half * sq = (threadgroup half *) shmem; // [Q, DK] queries - threadgroup float * ss = (threadgroup float *) (sq + Q*DK); // [Q, C] scores - threadgroup half * sp = (threadgroup half *) (ss + Q*C); // [Q, C] probabilities - threadgroup float * sr = (threadgroup float *) (sp + Q*C); // [Q] per-row scale of O - threadgroup int * sf = (threadgroup int *) (sr + Q); // [1] last iteration (ic0 + 1) that rescaled O - - q += iq1*args.nb01 + iq2*args.nb02 + iq3*args.nb03; - - { - const int ikv2 = iq2/(args.ne02/args.ne_12_2); - const int ikv3 = iq3/(args.ne03/args.ne_12_3); - - k += ikv2*args.nb12 + ikv3*args.nb13; - v += ikv2*args.nb22 + ikv3*args.nb23; - } - - // with softcap the scale is small (scale/softcap), so it is applied to the scores to keep the precision of Q - const float qscale = FC_flash_attn_ext_tensor_has_scap ? 1.0f : args.scale; - - // load the queries, with the scale folded in - for (int i = tiitg; i < Q*DK/4; i += NT) { - const int j = i/(DK/4); - - float4 q4 = 0.0f; - if (iq1 + j < args.ne01) { - q4 = ((device const float4 *) (q + j*args.nb01))[i%(DK/4)]; - } - - ((threadgroup half4 *) sq)[i] = (half4) (q4*qscale); - } - - device const half * pm[NQ]; - - FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { - const short j = jj*NSG + sgitg; - - pm[jj] = (device const half *) (mask + (iq1 + j)*args.nb31 + (iq2%args.ne32)*args.nb32 + (iq3%args.ne33)*args.nb33); - } - - { - const int nblk1 = (args.ne01 + Q - 1)/Q; - const int nblk0 = (args.ne11 + C - 1)/C; - - blk += (((iq3%args.ne33)*args.ne32 + (iq2%args.ne32))*nblk1 + iq1/Q)*nblk0; - } - - float M[NQ]; - float S[NQ]; - - FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { - M[jj] = -FLT_MAX/2; - S[jj] = 0.0f; - } - - float slope = 1.0f; - - // ALiBi - if (FC_flash_attn_ext_tensor_has_bias) { - const short h = iq2; - - const float base = h < args.n_head_log2 ? args.m0 : args.m1; - const short exph = h < args.n_head_log2 ? h + 1 : 2*(h - args.n_head_log2) + 1; - - slope = pow(base, exph); - } - - const int sk = args.ns10; - const int sv = args.ns20; - - auto tq = tensor(sq, dextents(DK, Q)); - auto ts = tensor(ss, dextents(C, Q)); - auto tp = tensor(sp, dextents(C, Q)); - - mpp::tensor_ops::matmul2d< - mpp::tensor_ops::matmul2d_descriptor(Q, C, DK, false, true, false, mpp::tensor_ops::matmul2d_descriptor::mode::multiply), - execution_simdgroups> mm_qk; - - mpp::tensor_ops::matmul2d< - mpp::tensor_ops::matmul2d_descriptor(Q, DV, C, false, false, false, mpp::tensor_ops::matmul2d_descriptor::mode::multiply_accumulate), - execution_simdgroups> mm_pv; - - auto tv0 = tensor((device half *) v, dextents(DV, C), array({1, sv})); - - // the O matrix from the paper - auto co = mm_pv.template get_destination_cooperative_tensor(); - - FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { - if (co.is_valid_element(i)) { - co[i] = 0.0f; - } - } - - if (tiitg == 0) { - sf[0] = 0; - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - // the host guarantees ne11 % C == 0 - for (int ic0 = 0, ic = 0; ic < args.ne11; ++ic0, ic += C) { - char blk_cur = 1; - - if (FC_flash_attn_ext_tensor_has_mask) { - blk_cur = blk[ic0]; - - if (blk_cur == 0) { - continue; - } - } - - // Q*K^T - { - auto tk = tensor((device half *) (k + (uint64_t) ic*args.nb11), dextents(DK, C), array({1, sk})); - - mm_qk.run(tq, tk, ts); - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - // online softmax - FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { - const short j = jj*NSG + sgitg; - - float s[NC]; - - FOR_UNROLL (short ii = 0; ii < NC; ++ii) { - s[ii] = ss[j*C + ii*NW + tiisg]; - } - - if (FC_flash_attn_ext_tensor_has_scap) { - FOR_UNROLL (short ii = 0; ii < NC; ++ii) { - s[ii] = args.logit_softcap*precise::tanh(s[ii]*args.scale); - } - } - - if (FC_flash_attn_ext_tensor_has_mask && blk_cur != 2 && iq1 + j < args.ne31) { - FOR_UNROLL (short ii = 0; ii < NC; ++ii) { - s[ii] += slope*(float) pm[jj][ic + ii*NW + tiisg]; - } - } - - float m = M[jj]; - - FOR_UNROLL (short ii = 0; ii < NC; ++ii) { - m = max(m, s[ii]); - } - - m = simd_max(m); - - // lazy rescaling: move the running max only when it grows by more than 8 (e^8 fits in half) - float ms = 1.0f; - - if (m > M[jj] + 8.0f) { - ms = exp(M[jj] - m); - M[jj] = m; - - if (tiisg == 0) { - sf[0] = ic0 + 1; - } - } - - float sum = 0.0f; - - FOR_UNROLL (short ii = 0; ii < NC; ++ii) { - // the sum uses the same rounded values as P*V - const half p = (half) exp(s[ii] - M[jj]); - - sp[j*C + ii*NW + tiisg] = p; - - sum += (float) p; - } - - S[jj] = S[jj]*ms + simd_sum(sum); - - if (tiisg == 0) { - sr[j] = ms; - } - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - // O = diag(ms)*O + P*V - if (sf[0] == ic0 + 1) { - FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { - if (co.is_valid_element(i)) { - co[i] *= sr[co.get_multidimensional_index(i)[1]]; - } - } - } - - { - auto tv = tensor((device half *) (v + (uint64_t) ic*args.nb21), dextents(DV, C), array({1, sv})); - - mm_pv.run(tp, tv, co); - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - } - - FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { - const short j = jj*NSG + sgitg; - - // the sink only adds to the denominator - its rescale of O is folded into the final scale - float ms = 1.0f; - - if (FC_flash_attn_ext_tensor_has_sinks) { - const float s = ((device const float *) sinks)[iq2]; - const float m = max(M[jj], s); - - ms = exp(M[jj] - m); - - S[jj] = S[jj]*ms + exp(s - m); - } - - if (tiisg == 0) { - sr[j] = S[jj] == 0.0f ? 0.0f : ms/S[jj]; - } - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { - if (co.is_valid_element(i)) { - co[i] *= sr[co.get_multidimensional_index(i)[1]]; - } - } - - // store to global memory - rows past ne01 are clipped by the tensor extents - device float * pdst = (device float *) dst + ((uint64_t) iq3*args.ne2*args.ne1 + iq2 + (uint64_t) iq1*args.ne1)*DV; - - auto td = tensor(pdst, dextents(DV, args.ne01 - iq1), array({1, args.ne1*DV})); - - co.store(td); -} - -typedef decltype(kernel_flash_attn_ext_tensor<64, 64>) flash_attn_ext_tensor_t; - -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk64_dv64" )]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<64, 64>; -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk128_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<128, 128>; -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk192_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<192, 128>; -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk256_dv256")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<256, 256>; -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk512_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<512, 512, OP_FLASH_ATTN_EXT_TENSOR_NQPSG_LARGE>; -template [[host_name("kernel_flash_attn_ext_tensor_f16_dk576_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor<576, 512, OP_FLASH_ATTN_EXT_TENSOR_NQPSG_LARGE>; - -#endif // GGML_METAL_HAS_TENSOR diff --git a/ggml/src/ggml-metal/kernels/fa_tensor.metal b/ggml/src/ggml-metal/kernels/fa_tensor.metal new file mode 100644 index 000000000000..4a9ed30e3b25 --- /dev/null +++ b/ggml/src/ggml-metal/kernels/fa_tensor.metal @@ -0,0 +1,298 @@ +#include "common.h" + +#ifdef GGML_METAL_HAS_TENSOR + +constant bool FC_flash_attn_ext_tensor_has_mask [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 0)]]; +constant bool FC_flash_attn_ext_tensor_has_sinks [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 1)]]; +constant bool FC_flash_attn_ext_tensor_has_bias [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 2)]]; +constant bool FC_flash_attn_ext_tensor_has_scap [[function_constant(FC_FLASH_ATTN_EXT_TENSOR + 3)]]; + +// ref: https://arxiv.org/pdf/2307.08691.pdf +template< + typename T, // Q, K, V and P types + typename T4, + short DK, // K head size + short DV, // V head size + short Q = OP_FLASH_ATTN_EXT_TENSOR_NQPSG, // queries per threadgroup + short C = OP_FLASH_ATTN_EXT_TENSOR_NCPSG, // cache items per threadgroup + short NSG = OP_FLASH_ATTN_EXT_TENSOR_NSG> // number of simd groups +kernel void kernel_flash_attn_ext_tensor( + constant ggml_metal_kargs_flash_attn_ext & args, + device const char * q, + device const char * k, + device const char * v, + device const char * mask, + device const char * sinks, + device const char * blk, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig [[threadgroup_position_in_grid]], + ushort tiisg [[thread_index_in_simdgroup]], + ushort sgitg [[simdgroup_index_in_threadgroup]]) { + constexpr short NW = N_SIMDWIDTH; + constexpr short NT = NW*NSG; + constexpr short NQ = Q/NSG; + constexpr short NC = C/NW; // columns per thread + + static_assert(DK % 4 == 0, "DK must be divisible by 4"); + static_assert(Q % NSG == 0, "Q must be divisible by NSG"); + static_assert(C % NW == 0, "C must be divisible by NW"); + + const int iq3 = tgpig[2]; + const int iq2 = tgpig[1]; + const int iq1 = tgpig[0]*Q; + + const short tiitg = sgitg*NW + tiisg; + + threadgroup T * sq = (threadgroup T *) shmem; // [Q, DK] queries + threadgroup float * ss = (threadgroup float *) (sq + Q*DK); // [Q, C] scores + threadgroup T * sp = (threadgroup T *) (ss + Q*C); // [Q, C] probabilities + threadgroup float * sr = (threadgroup float *) (sp + Q*C); // [Q] per-row scale of O + threadgroup int * sf = (threadgroup int *) (sr + Q); // [1] last iteration (ic0 + 1) that rescaled O + + q += iq1*args.nb01 + iq2*args.nb02 + iq3*args.nb03; + + { + const int ikv2 = iq2/(args.ne02/args.ne_12_2); + const int ikv3 = iq3/(args.ne03/args.ne_12_3); + + k += ikv2*args.nb12 + ikv3*args.nb13; + v += ikv2*args.nb22 + ikv3*args.nb23; + } + + // with softcap the scale is small (scale/softcap), so it is applied to the scores to keep the precision of Q + const float qscale = FC_flash_attn_ext_tensor_has_scap ? 1.0f : args.scale; + + // load the queries, with the scale folded in + for (int i = tiitg; i < Q*DK/4; i += NT) { + const int j = i/(DK/4); + + float4 q4 = 0.0f; + if (iq1 + j < args.ne01) { + q4 = ((device const float4 *) (q + j*args.nb01))[i%(DK/4)]; + } + + ((threadgroup T4 *) sq)[i] = (T4) (q4*qscale); + } + + device const half * pm[NQ]; + + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + pm[jj] = (device const half *) (mask + (iq1 + j)*args.nb31 + (iq2%args.ne32)*args.nb32 + (iq3%args.ne33)*args.nb33); + } + + { + const int nblk1 = (args.ne01 + Q - 1)/Q; + const int nblk0 = (args.ne11 + C - 1)/C; + + blk += (((iq3%args.ne33)*args.ne32 + (iq2%args.ne32))*nblk1 + iq1/Q)*nblk0; + } + + float M[NQ]; + float S[NQ]; + + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + M[jj] = -FLT_MAX/2; + S[jj] = 0.0f; + } + + float slope = 1.0f; + + // ALiBi + if (FC_flash_attn_ext_tensor_has_bias) { + const short h = iq2; + + const float base = h < args.n_head_log2 ? args.m0 : args.m1; + const short exph = h < args.n_head_log2 ? h + 1 : 2*(h - args.n_head_log2) + 1; + + slope = pow(base, exph); + } + + const int sk = args.ns10; + const int sv = args.ns20; + + auto tq = tensor(sq, dextents(DK, Q)); + auto ts = tensor(ss, dextents(C, Q)); + auto tp = tensor(sp, dextents(C, Q)); + + mpp::tensor_ops::matmul2d< + mpp::tensor_ops::matmul2d_descriptor(Q, C, DK, false, true, false, mpp::tensor_ops::matmul2d_descriptor::mode::multiply), + execution_simdgroups> mm_qk; + + mpp::tensor_ops::matmul2d< + mpp::tensor_ops::matmul2d_descriptor(Q, DV, C, false, false, false, mpp::tensor_ops::matmul2d_descriptor::mode::multiply_accumulate), + execution_simdgroups> mm_pv; + + auto tv0 = tensor((device T *) v, dextents(DV, C), array({1, sv})); + + // the O matrix from the paper + auto co = mm_pv.template get_destination_cooperative_tensor(); + + FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { + if (co.is_valid_element(i)) { + co[i] = 0.0f; + } + } + + if (tiitg == 0) { + sf[0] = 0; + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + // the host guarantees ne11 % C == 0 + for (int ic0 = 0, ic = 0; ic < args.ne11; ++ic0, ic += C) { + char blk_cur = 1; + + if (FC_flash_attn_ext_tensor_has_mask) { + blk_cur = blk[ic0]; + + if (blk_cur == 0) { + continue; + } + } + + // Q*K^T + { + auto tk = tensor((device T *) (k + (uint64_t) ic*args.nb11), dextents(DK, C), array({1, sk})); + + mm_qk.run(tq, tk, ts); + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + // online softmax + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + float s[NC]; + + FOR_UNROLL (short ii = 0; ii < NC; ++ii) { + s[ii] = ss[j*C + ii*NW + tiisg]; + } + + if (FC_flash_attn_ext_tensor_has_scap) { + FOR_UNROLL (short ii = 0; ii < NC; ++ii) { + s[ii] = args.logit_softcap*precise::tanh(s[ii]*args.scale); + } + } + + if (FC_flash_attn_ext_tensor_has_mask && blk_cur != 2 && iq1 + j < args.ne31) { + FOR_UNROLL (short ii = 0; ii < NC; ++ii) { + s[ii] += slope*(float) pm[jj][ic + ii*NW + tiisg]; + } + } + + float m = M[jj]; + + FOR_UNROLL (short ii = 0; ii < NC; ++ii) { + m = max(m, s[ii]); + } + + m = simd_max(m); + + // lazy rescaling: move the running max only when it grows by more than 8 (e^8 fits in half) + float ms = 1.0f; + + if (m > M[jj] + 8.0f) { + ms = exp(M[jj] - m); + M[jj] = m; + + if (tiisg == 0) { + sf[0] = ic0 + 1; + } + } + + float sum = 0.0f; + + FOR_UNROLL (short ii = 0; ii < NC; ++ii) { + // the sum uses the same rounded values as P*V + const T p = (T) exp(s[ii] - M[jj]); + + sp[j*C + ii*NW + tiisg] = p; + + sum += (float) p; + } + + S[jj] = S[jj]*ms + simd_sum(sum); + + if (tiisg == 0) { + sr[j] = ms; + } + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + // O = diag(ms)*O + P*V + if (sf[0] == ic0 + 1) { + FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { + if (co.is_valid_element(i)) { + co[i] *= sr[co.get_multidimensional_index(i)[1]]; + } + } + } + + { + auto tv = tensor((device T *) (v + (uint64_t) ic*args.nb21), dextents(DV, C), array({1, sv})); + + mm_pv.run(tp, tv, co); + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + } + + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + // the sink only adds to the denominator - its rescale of O is folded into the final scale + float ms = 1.0f; + + if (FC_flash_attn_ext_tensor_has_sinks) { + const float s = ((device const float *) sinks)[iq2]; + const float m = max(M[jj], s); + + ms = exp(M[jj] - m); + + S[jj] = S[jj]*ms + exp(s - m); + } + + if (tiisg == 0) { + sr[j] = S[jj] == 0.0f ? 0.0f : ms/S[jj]; + } + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + FOR_UNROLL (short i = 0; i < co.get_capacity(); ++i) { + if (co.is_valid_element(i)) { + co[i] *= sr[co.get_multidimensional_index(i)[1]]; + } + } + + // store to global memory - rows past ne01 are clipped by the tensor extents + device float * pdst = (device float *) dst + ((uint64_t) iq3*args.ne2*args.ne1 + iq2 + (uint64_t) iq1*args.ne1)*DV; + + auto td = tensor(pdst, dextents(DV, args.ne01 - iq1), array({1, args.ne1*DV})); + + co.store(td); +} + +typedef decltype(kernel_flash_attn_ext_tensor) flash_attn_ext_tensor_t; + +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk64_dv64" )]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk128_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk192_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk256_dv256")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk512_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_f16_dk576_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; + +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk64_dv64" )]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk128_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk192_dv128")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk256_dv256")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk512_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; +template [[host_name("kernel_flash_attn_ext_tensor_bf16_dk576_dv512")]] kernel flash_attn_ext_tensor_t kernel_flash_attn_ext_tensor; + +#endif // GGML_METAL_HAS_TENSOR diff --git a/ggml/src/ggml-metal/kernels/fa_vec_common.metal b/ggml/src/ggml-metal/kernels/fa_vec_common.metal index 46270ba4b271..c81e4d09bb75 100644 --- a/ggml/src/ggml-metal/kernels/fa_vec_common.metal +++ b/ggml/src/ggml-metal/kernels/fa_vec_common.metal @@ -13,6 +13,7 @@ constant int32_t FC_flash_attn_ext_vec_ns20 [[function_constant(FC_FLASH_ATTN_EX constant int32_t FC_flash_attn_ext_vec_nsg [[function_constant(FC_FLASH_ATTN_EXT_VEC + 22)]]; constant int32_t FC_flash_attn_ext_vec_nwg [[function_constant(FC_FLASH_ATTN_EXT_VEC + 23)]]; constant bool FC_flash_attn_ext_vec_has_sparse [[function_constant(FC_FLASH_ATTN_EXT_VEC + 5)]]; +constant bool FC_flash_attn_ext_vec_has_rows [[function_constant(FC_FLASH_ATTN_EXT_VEC + 6)]]; template< typename q4_t, // query types in shared memory typename k4_t, // key types in shared memory @@ -90,7 +91,8 @@ kernel void kernel_flash_attn_ext_vec( threadgroup o4_t * so4 = (threadgroup o4_t *) (shmem_f16 + SMEM_Q + SMEM_S + 2*sgitg*Q*PV); // scratch buffer for the results // sparse indices for the current block - threadgroup int * spidx = FC_flash_attn_ext_vec_has_sparse + // note: with kv_rows, the buffer holds the row list of the current slice instead + threadgroup int * spidx = (FC_flash_attn_ext_vec_has_sparse || FC_flash_attn_ext_vec_has_rows) ? (threadgroup int *) (shmem_f16 + SMEM) + sgitg*C : nullptr; @@ -165,6 +167,12 @@ kernel void kernel_flash_attn_ext_vec( ((int64_t)(iq3%args.ne33)*args.ne32 + (iq2%args.ne32))*args.ne31*args.n_kv_max_padded + (iq1%args.ne31)*args.n_kv_max_padded; } + // K/V row list of the current slice (ggml_flash_attn_ext_rows) + // with kv_rows, the loop below runs over the mask columns (args.ne11) and the K/V cache rows + // are read indirectly through the list. negative entries are padding, their mask is -INF + device const int * rows_list = FC_flash_attn_ext_vec_has_rows ? + (device const int *) idx + (int64_t)(iq3%args.ne33)*args.ne11 : nullptr; + float slope = 1.0f; // ALiBi @@ -222,12 +230,12 @@ kernel void kernel_flash_attn_ext_vec( ic = 0; } - // load the sparse KV indices for the current block into shared memory - if (FC_flash_attn_ext_vec_has_sparse) { + // load the KV row indices for the current block into shared memory + if (FC_flash_attn_ext_vec_has_sparse || FC_flash_attn_ext_vec_has_rows) { FOR_UNROLL (short ii = 0; ii < C/NW; ++ii) { const short i = ii*NW + tiisg; - spidx[i] = pidx[ic + i]; + spidx[i] = FC_flash_attn_ext_vec_has_rows ? rows_list[ic + i] : pidx[ic + i]; } simdgroup_barrier(mem_flags::mem_threadgroup); } @@ -242,6 +250,15 @@ kernel void kernel_flash_attn_ext_vec( sm[qq*C + tiisg] = -MAXHALF; } } + } else if (FC_flash_attn_ext_vec_has_rows) { + // the mask is compact: column ic maps to cache row spidx[tiisg] + FOR_UNROLL (short qq = 0; qq < Q; ++qq) { + if ((iq1*Q + qq) < args.ne01) { + sm[qq*C + tiisg] = pm[qq][ic + tiisg]; + } else { + sm[qq*C + tiisg] = -MAXHALF; + } + } } else { FOR_UNROLL (short qq = 0; qq < Q; ++qq) { if ((iq1*Q + qq) < args.ne01) { @@ -276,7 +293,7 @@ kernel void kernel_flash_attn_ext_vec( { device const k4_t * pk4 = nullptr; - if (!FC_flash_attn_ext_vec_has_sparse) { + if (!FC_flash_attn_ext_vec_has_sparse && !FC_flash_attn_ext_vec_has_rows) { pk4 = (device const k4_t *) (k + ic*args.nb11); pk4 += ty*NS10/4 + tx; @@ -291,7 +308,7 @@ kernel void kernel_flash_attn_ext_vec( // each simdgroup processes Q queries and NE (NW/NL) cache elements FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { - if (FC_flash_attn_ext_vec_has_sparse) { + if (FC_flash_attn_ext_vec_has_sparse || FC_flash_attn_ext_vec_has_rows) { // the KV rows are gathered from the index list; -1 entries are padding const int i11 = spidx[NE*cc + ty]; if (i11 >= 0) { @@ -434,7 +451,7 @@ kernel void kernel_flash_attn_ext_vec( } } - if (FC_flash_attn_ext_vec_has_sparse) { + if (FC_flash_attn_ext_vec_has_sparse || FC_flash_attn_ext_vec_has_rows) { FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { // the KV rows are gathered from the index list; -1 entries are padding const int i11 = spidx[NE*cc + ty]; diff --git a/ggml/src/ggml-metal/kernels/misc.metal b/ggml/src/ggml-metal/kernels/misc.metal index fb27983db3e6..5dfd4a60c3ab 100644 --- a/ggml/src/ggml-metal/kernels/misc.metal +++ b/ggml/src/ggml-metal/kernels/misc.metal @@ -60,6 +60,140 @@ kernel void kernel_argmax_f32( dst_i32[tgpig] = arg_val; } +kernel void kernel_argmax_part_f32( + constant ggml_metal_kargs_argmax & args, + device const char * src0, + device char * tmp, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + uint sgitg[[simdgroup_index_in_threadgroup]], + uint tiisg[[thread_index_in_simdgroup]], + uint3 ntg[[threads_per_threadgroup]]) { + const int row = tgpig.y; + const int part = tgpig.x; + const int ne00 = (int) args.ne00; + const int npart = (int) args.npart; + const int chunk = (ne00 + npart - 1) / npart; + const int start = part * chunk; + const int end = min(start + chunk, ne00); + + device const float * x_row = (device const float *) ((device const char *) src0 + row * args.nb01); + + float lmax = -INFINITY; + int32_t larg = -1; + + for (int i00 = start + tpitg.x; i00 < end; i00 += ntg.x) { + if (x_row[i00] > lmax) { + lmax = x_row[i00]; + larg = i00; + } + } + + // find the argmax value in the block + float max_val = simd_max(lmax); + int32_t arg_val = simd_max(select(-1, larg, lmax == max_val)); + + threadgroup float * shared_maxval = (threadgroup float *) shmem; + threadgroup int32_t * shared_argmax = (threadgroup int32_t *) shmem + N_SIMDWIDTH; + + if (ntg.x > N_SIMDWIDTH) { + if (sgitg == 0) { + shared_maxval[tiisg] = -INFINITY; + shared_argmax[tiisg] = -1; + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + if (tiisg == 0) { + shared_maxval[sgitg] = max_val; + shared_argmax[sgitg] = arg_val; + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + max_val = shared_maxval[tiisg]; + arg_val = shared_argmax[tiisg]; + + float max_val_reduced = simd_max(max_val); + int32_t arg_val_reduced = simd_max(select(-1, arg_val, max_val == max_val_reduced)); + + max_val = max_val_reduced; + arg_val = arg_val_reduced; + } + + if (tpitg.x == 0) { + device float * tmp_max = (device float *) tmp; + device int32_t * tmp_arg = (device int32_t *) tmp + npart * (int) args.ne01; + + tmp_max[row*npart + part] = max_val; + tmp_arg[row*npart + part] = arg_val; + } +} + +kernel void kernel_argmax_final_f32( + constant ggml_metal_kargs_argmax & args, + device const char * tmp, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + uint sgitg[[simdgroup_index_in_threadgroup]], + uint tiisg[[thread_index_in_simdgroup]], + uint3 ntg[[threads_per_threadgroup]]) { + const int row = tgpig.x; + const int npart = (int) args.npart; + + device const float * tmp_max = (device const float *) tmp; + device const int32_t * tmp_arg = (device const int32_t *) tmp + npart * (int) args.ne01; + + float lmax = -INFINITY; + int32_t larg = -1; + + for (int i = tpitg.x; i < npart; i += ntg.x) { + if (tmp_max[row*npart + i] > lmax) { + lmax = tmp_max[row*npart + i]; + larg = tmp_arg[row*npart + i]; + } + } + + // find the argmax value in the block + float max_val = simd_max(lmax); + int32_t arg_val = simd_max(select(-1, larg, lmax == max_val)); + + threadgroup float * shared_maxval = (threadgroup float *) shmem; + threadgroup int32_t * shared_argmax = (threadgroup int32_t *) shmem + N_SIMDWIDTH; + + if (ntg.x > N_SIMDWIDTH) { + if (sgitg == 0) { + shared_maxval[tiisg] = -INFINITY; + shared_argmax[tiisg] = -1; + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + if (tiisg == 0) { + shared_maxval[sgitg] = max_val; + shared_argmax[sgitg] = arg_val; + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + max_val = shared_maxval[tiisg]; + arg_val = shared_argmax[tiisg]; + + float max_val_reduced = simd_max(max_val); + int32_t arg_val_reduced = simd_max(select(-1, arg_val, max_val == max_val_reduced)); + + max_val = max_val_reduced; + arg_val = arg_val_reduced; + } + + if (tpitg.x == 0) { + ((device int32_t *) dst)[row] = arg_val; + } +} + kernel void kernel_diag_f32( constant ggml_metal_kargs_diag & args, device const char * src0, @@ -772,3 +906,99 @@ kernel void kernel_dsv4_hc_post_f32( *(device float *) (dst + i0*args.nb_d0 + idst*args.nb_d1 + it*args.nb_d2) = result[idst]; } } + +constant bool FC_top_k_mask_has_score [[function_constant(FC_TOP_K_MASK + 0)]]; +constant bool FC_top_k_mask_has_blocks [[function_constant(FC_TOP_K_MASK + 1)]]; +constant bool FC_top_k_mask_has_extra [[function_constant(FC_TOP_K_MASK + 2)]]; +constant bool FC_top_k_mask_vec [[function_constant(FC_TOP_K_MASK + 3)]]; + +// the fill runs before the scatter, both are fully parallel over the whole dst and over the picks of one row +template +kernel void kernel_top_k_mask_fill( + constant ggml_metal_kargs_top_k_mask & args, + device char * dst, + uint tid[[thread_position_in_grid]], + uint ntot[[threads_per_grid]]) { + const T ninf = T(-INFINITY); + + if (FC_top_k_mask_vec) { + device T4 * dst_4 = (device T4 *) dst; + for (int64_t i = tid; i < args.n_elems/4; i += ntot) { + dst_4[i] = T4(ninf); + } + } else { + device T * dst_t = (device T *) dst; + for (int64_t i = tid; i < args.n_elems; i += ntot) { + dst_t[i] = ninf; + } + } +} + +typedef decltype(kernel_top_k_mask_fill) kernel_top_k_mask_fill_h_t; +typedef decltype(kernel_top_k_mask_fill) kernel_top_k_mask_fill_f_t; + +template [[host_name("kernel_top_k_mask_fill_f16")]] kernel kernel_top_k_mask_fill_h_t kernel_top_k_mask_fill; +template [[host_name("kernel_top_k_mask_fill_f32")]] kernel kernel_top_k_mask_fill_f_t kernel_top_k_mask_fill; + +// one threadgroup per row: copy the mask cells of the live picks and of the extra cells over the fill +template +kernel void kernel_top_k_mask( + constant ggml_metal_kargs_top_k_mask & args, + device const char * mask, + device const char * top_k, + device const char * score, + device const char * blocks, + device const char * extra, + device char * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + uint3 ntg_max[[threads_per_threadgroup]]) { + const int i1 = tgpig.x; + const int i2 = tgpig.y; + const int i3 = tgpig.z; + + const int tiitg = tpitg.x; + const int ntg = ntg_max.x; + + device const char * mask_row = mask + (i1 % args.m1)*args.nbm1 + (i2 % args.m2)*args.nbm2 + (i3 % args.m3)*args.nbm3; + device char * dst_row = dst + i1*args.nb1 + i2*args.nb2 + i3*args.nb3; + device const char * top_k_row = top_k + i1*args.nbk1 + i2*args.nbk2 + i3*args.nbk3; + + device const T * mask_row_t = (device const T *) mask_row; + device T * dst_row_t = (device T *) dst_row; + + for (int i = tiitg; i < args.n_top; i += ntg) { + const int32_t p = *(device const int32_t *) (top_k_row + i*args.nbk0); + if (p < 0 || p >= args.n_pick) { + continue; + } + if (FC_top_k_mask_has_score && !(*(device const float *) (score + p*args.nbs0 + i1*args.nbs1 + i2*args.nbs2 + i3*args.nbs3) > -INFINITY)) { + continue; + } + if (FC_top_k_mask_has_blocks) { + FOR_UNROLL (int k = 0; k < args.n_blk; ++k) { + const int32_t c = *(device const int32_t *) (blocks + k*args.nbb0 + p*args.nbb1); + if (c >= 0 && c < args.n_kv) { + dst_row_t[c] = mask_row_t[c]; + } + } + } else if (p < args.n_kv) { + dst_row_t[p] = mask_row_t[p]; + } + } + + if (FC_top_k_mask_has_extra) { + for (int i = tiitg; i < args.n_extra; i += ntg) { + const int32_t c = *(device const int32_t *) (extra + i*args.nbe0 + i1*args.nbe1 + i2*args.nbe2 + i3*args.nbe3); + if (c >= 0 && c < args.n_kv) { + dst_row_t[c] = mask_row_t[c]; + } + } + } +} + +typedef decltype(kernel_top_k_mask) kernel_top_k_mask_h_t; +typedef decltype(kernel_top_k_mask) kernel_top_k_mask_f_t; + +template [[host_name("kernel_top_k_mask_f16")]] kernel kernel_top_k_mask_h_t kernel_top_k_mask; +template [[host_name("kernel_top_k_mask_f32")]] kernel kernel_top_k_mask_f_t kernel_top_k_mask; diff --git a/ggml/src/ggml-metal/kernels/mul_mm.metal b/ggml/src/ggml-metal/kernels/mul_mm.metal index dfa5102c56f8..edcc061d516e 100644 --- a/ggml/src/ggml-metal/kernels/mul_mm.metal +++ b/ggml/src/ggml-metal/kernels/mul_mm.metal @@ -7,7 +7,6 @@ constant short FC_mul_mm_ne12 [[function_constant(FC_MUL_MM + 2)]]; constant short FC_mul_mm_ne13 [[function_constant(FC_MUL_MM + 3)]]; constant short FC_mul_mm_r2 [[function_constant(FC_MUL_MM + 4)]]; constant short FC_mul_mm_r3 [[function_constant(FC_MUL_MM + 5)]]; -constant bool FC_mul_mm_id_amax [[function_constant(FC_MUL_MM + 6)]]; constant int32_t FC_mul_mm_id_map0_ne02 [[function_constant(FC_MUL_MM + 7)]]; // each block_q contains 16*nl weights @@ -324,10 +323,10 @@ kernel void kernel_mul_mm( // if no bounds checks on the output are needed, we can directly write to device memory device float * C = (device float *) dst + (r0 + 32*(sgitg & 1)) + \ - (r1 + 16*(sgitg >> 1)) * args.ne0 + im*args.ne1*args.ne0; + (uint64_t) (r1 + 16*(sgitg >> 1))*args.ne0 + (uint64_t) im*args.ne1*args.ne0; for (short i = 0; i < 8; i++) { - simdgroup_store(mc[i], C + 8*(i%4) + 8*args.ne0*(i/4), args.ne0, 0, false); + simdgroup_store(mc[i], C + 8*(i%4) + (uint64_t) 8*args.ne0*(i/4), args.ne0, 0, false); } } else { // block is smaller than 64x32, we should avoid writing data outside of the matrix @@ -343,7 +342,7 @@ kernel void kernel_mul_mm( if (sgitg == 0) { for (int j = tiitg; j < nr1; j += NR1) { - device float * D = (device float *) dst + r0 + (r1 + j)*args.ne0 + im*args.ne1*args.ne0; + device float * D = (device float *) dst + r0 + (uint64_t) (r1 + j)*args.ne0 + (uint64_t) im*args.ne1*args.ne0; device float4 * D4 = (device float4 *) D; threadgroup float * C = temp_str + (j*NR0); @@ -391,8 +390,10 @@ kernel void kernel_mul_mm_id_map0( if (i21 + tpitg < args.ne21) { device const int32_t * src2_i32 = (device const int32_t *) (src2 + (i21 + tpitg)*args.nb21); + // 0xFFFF marks a skipped slot, it never matches an expert since ne02 fits in a threadgroup FOR_UNROLL (short i20 = 0; i20 < ne20; i20++) { - sids[tpitg*ne20 + i20] = src2_i32[i20]; + const int32_t id = src2_i32[i20]; + sids[tpitg*ne20 + i20] = id == -1 ? 0xFFFF : (uint16_t) id; } } @@ -506,82 +507,27 @@ kernel void kernel_mul_mm_id_map0( } } -kernel void kernel_mul_mm_id_amax_part_f32( - constant ggml_metal_kargs_mul_mm_id_amax & args, - device const char * src1, - device char * dst, - threadgroup char * shmem [[threadgroup(0)]], - uint tgpig[[threadgroup_position_in_grid]], - ushort tiitg[[thread_index_in_threadgroup]], - ushort tiisg[[thread_index_in_simdgroup]], - ushort sgitg[[simdgroup_index_in_threadgroup]], - ushort ntg[[threads_per_threadgroup]]) { - const int nrow = args.ne01*args.ne02; - - float lmax = 0.0f; - - for (int ir = tgpig; ir < nrow; ir += N_MM_NPART_AMAX) { - const int i01 = ir % args.ne01; - const int i02 = ir / args.ne01; - - device const float * row = (device const float *) (src1 + i02*args.nb02 + i01*args.nb01); - - for (int i00 = tiitg; i00 < args.ne00; i00 += ntg) { - lmax = max(lmax, fabs(row[i00])); - } - } - - float amax = simd_max(lmax); - - threadgroup float * shared_amax = (threadgroup float *) shmem; - - if (ntg > N_SIMDWIDTH) { - if (sgitg == 0) { - shared_amax[tiisg] = 0.0f; - } - threadgroup_barrier(mem_flags::mem_threadgroup); - - if (tiisg == 0) { - shared_amax[sgitg] = amax; - } - threadgroup_barrier(mem_flags::mem_threadgroup); - - amax = shared_amax[tiisg]; - amax = simd_max(amax); - } - - if (tiitg == 0) { - ((device float *) (dst + 8))[tgpig] = amax; - } -} - -kernel void kernel_mul_mm_id_amax_f32( - device char * dst, - ushort tiitg[[thread_index_in_threadgroup]]) { - device const float * part = (device const float *) (dst + 8); +// kernel_mul_mm_id only writes the rows that an expert owns, so the skipped rows are zeroed here +kernel void kernel_mul_mm_id_zero( + constant ggml_metal_kargs_mul_mm_id_zero & args, + device const char * src2, + device char * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + ushort3 tpitg[[thread_position_in_threadgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { + const int i20 = tgpig.x; // slot + const int i21 = tgpig.y; // token - float amax = 0.0f; + const int32_t id = ((device const int32_t *) (src2 + i21*args.nb21))[i20]; - for (int i = tiitg; i < N_MM_NPART_AMAX; i += N_SIMDWIDTH) { - amax = max(amax, part[i]); + if (id != -1) { + return; } - amax = simd_max(amax); - - if (tiitg == 0) { - // leave a comfortable margin below the f16 max of 65504 - float scale = 1.0f; - - // isfinite: src1 already inf/nan is not ours to fix - keep the - // scale at 1.0 instead of turning it into a different failure - if (isfinite(amax) && amax > 32768.0f) { - scale = exp2(ceil(log2(amax)) - 15.0f); - } - - device float * d = (device float *) dst; + device float * dst_row = (device float *) (dst + i20*args.nb1 + i21*args.nb2); - d[0] = 1.0f/scale; // exact: scale is a power of two - d[1] = scale; + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + dst_row[i0] = 0.0f; } } @@ -593,6 +539,7 @@ template [[host_name("kernel_mul_mm_id_map0_ne20_4" )]] kernel kernel_mul_mm_id_ template [[host_name("kernel_mul_mm_id_map0_ne20_5" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<5>; template [[host_name("kernel_mul_mm_id_map0_ne20_6" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<6>; template [[host_name("kernel_mul_mm_id_map0_ne20_8" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<8>; +template [[host_name("kernel_mul_mm_id_map0_ne20_9" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<9>; template [[host_name("kernel_mul_mm_id_map0_ne20_10")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<10>; template [[host_name("kernel_mul_mm_id_map0_ne20_16")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<16>; template [[host_name("kernel_mul_mm_id_map0_ne20_22")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<22>; @@ -606,7 +553,6 @@ kernel void kernel_mul_mm_id( device const char * htpe, device const char * hids, device char * dst, - device const char * amax, threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiitg[[thread_index_in_threadgroup]], @@ -662,10 +608,6 @@ kernel void kernel_mul_mm_id( // skip the upper half of the token tile when the expert did not fill it constexpr short NR1H = NR1/2; - // power-of-two rescaling - const float s1_inv = FC_mul_mm_id_amax ? ((device const float *) amax)[0] : 1.0f; - const float s1_scale = FC_mul_mm_id_amax ? ((device const float *) amax)[1] : 1.0f; - #ifndef GGML_METAL_HAS_TENSOR S0_8x8 ma[4]; S1_8x8 mb[2]; @@ -691,7 +633,7 @@ kernel void kernel_mul_mm_id( const int id = ids_i32[idb + lr1]; const short i11 = (id % args.ne20) % args.ne11; - const short i12 = (id / args.ne20); + const int i12 = (id / args.ne20); device const block_q * x = (device const block_q *)(src0 + args.nb01*(r0 + lr0) + offset0) + offset1; @@ -771,7 +713,7 @@ kernel void kernel_mul_mm_id( const short ib = 4*sx + sy; - *(sb + 64*ib + 8*ly + lx) = loop_k + iy + i < args.ne00 ? (S1) (*((device T1 *) y + i) * (T1) s1_inv) : 0; + *(sb + 64*ib + 8*ly + lx) = loop_k + iy + i < args.ne00 ? (S1) *((device T1 *) y + i) : 0; } } else { const short sx = (tiitg%NL1); @@ -784,7 +726,7 @@ kernel void kernel_mul_mm_id( const short ib = 4*sx + sy; - *(threadgroup S1_2x4 *)(sb + 64*ib + 8*ly) = (S1_2x4)((*((device T1_2x4 *) y)) * (T1) s1_inv); + *(threadgroup S1_2x4 *)(sb + 64*ib + 8*ly) = (S1_2x4)(*((device T1_2x4 *) y)); } #else // load data and store to threadgroup memory @@ -832,7 +774,7 @@ kernel void kernel_mul_mm_id( //const short lx = (tiitg/NL1)%8; //const short ly = i; - *(sb + NK*(8*sy + ly) + 8*sx + lx) = loop_k + iy + i < args.ne00 ? (S1) (*((device T1 *) y + i) * (T1) s1_inv) : 0; + *(sb + NK*(8*sy + ly) + 8*sx + lx) = loop_k + iy + i < args.ne00 ? (S1) *((device T1 *) y + i) : 0; } } else { const short sx = (tiitg%NL1); @@ -843,7 +785,7 @@ kernel void kernel_mul_mm_id( //const short lx = (tiitg/NL1)%8; //const short ly = i; - *(threadgroup S1_2x4 *)(sb + NK*(8*sy + ly) + 8*sx) = (S1_2x4)((*((device T1_2x4 *) y)) * (T1) s1_inv); + *(threadgroup S1_2x4 *)(sb + NK*(8*sy + ly) + 8*sx) = (S1_2x4)(*((device T1_2x4 *) y)); } #endif @@ -924,9 +866,9 @@ kernel void kernel_mul_mm_id( const int id = ids_i32[idb + j]; const short ide = id % args.ne20; - const short idt = id / args.ne20; + const int idt = id / args.ne20; - device float * D = (device float *) dst + r0 + ide*args.ne0 + idt*args.ne1*args.ne0; + device float * D = (device float *) dst + r0 + (uint64_t) ide*args.ne0 + (uint64_t) idt*args.ne1*args.ne0; device float4 * D4 = (device float4 *) D; threadgroup float * C = (threadgroup float *) shmem + j*NR0; @@ -934,12 +876,12 @@ kernel void kernel_mul_mm_id( int i = tiisg; for (; i < nr0/4; i += 32) { - *(D4 + i) = *(C4 + i) * s1_scale; + *(D4 + i) = *(C4 + i); } i = (4*(nr0/4)) + tiisg; for (; i < nr0; i += 32) { - *(D + i) = *(C + i) * s1_scale; + *(D + i) = *(C + i); } } } diff --git a/ggml/src/ggml-metal/kernels/mul_mv.metal b/ggml/src/ggml-metal/kernels/mul_mv.metal index 0d1069f2c88a..5d012e484944 100644 --- a/ggml/src/ggml-metal/kernels/mul_mv.metal +++ b/ggml/src/ggml-metal/kernels/mul_mv.metal @@ -3030,6 +3030,22 @@ kernel void kernel_mul_mv_iq4_xs_f32( kernel_mul_mv_iq4_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } +// decode the E2M1 value in the low nibble of n, scaled by 2^-14, without a lookup table: the 3 magnitude bits +// land in the fp16 exponent/mantissa (e=0 gives the 0.5 subnormal). same decode as MLX's fp4_e2m1 +static inline half mxfp4_dq1(uint32_t n) { + const half c = as_type(ushort((n & 7) << 9)); + return (n & 8) ? -c : c; +} + +// low / high nibbles of the 4 bytes of w, in byte order, scaled by 2^-14 +static inline float4 mxfp4_lo4(uint32_t w) { + return float4(mxfp4_dq1(w), mxfp4_dq1(w >> 8), mxfp4_dq1(w >> 16), mxfp4_dq1(w >> 24)); +} + +static inline float4 mxfp4_hi4(uint32_t w) { + return float4(mxfp4_dq1(w >> 4), mxfp4_dq1(w >> 12), mxfp4_dq1(w >> 20), mxfp4_dq1(w >> 28)); +} + template void kernel_mul_mv_mxfp4_f32_impl( args_t args, @@ -3042,8 +3058,6 @@ void kernel_mul_mv_mxfp4_f32_impl( ushort sgitg) { const short NSG = FC_mul_mv_nsg; - threadgroup float * shmem_f32 = (threadgroup float *) shmem; - const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; @@ -3065,9 +3079,6 @@ void kernel_mul_mv_mxfp4_f32_impl( const short ix = tiisg/2; // 0...15 const short it = tiisg%2; // 0 or 1 - shmem_f32[tiisg] = kvalues_mxfp4_f[tiisg%16]; - threadgroup_barrier(mem_flags::mem_threadgroup); - float4 yl[4]; float sumf[NR0]={0.f}; @@ -3087,14 +3098,25 @@ void kernel_mul_mv_mxfp4_f32_impl( device const block_mxfp4 & xb = x[row*ns01 + ib]; device const uint8_t * q2 = (device const uint8_t *)(xb.qs + 8*it); - float4 acc1 = yl[0]*float4(shmem_f32[q2[0] & 0x0F], shmem_f32[q2[1] & 0x0F], shmem_f32[q2[2] & 0x0F], shmem_f32[q2[3] & 0x0F]); - float4 acc2 = yl[1]*float4(shmem_f32[q2[0] >> 4 ], shmem_f32[q2[1] >> 4 ], shmem_f32[q2[2] >> 4 ], shmem_f32[q2[3] >> 4 ]); - float4 acc3 = yl[2]*float4(shmem_f32[q2[4] & 0x0F], shmem_f32[q2[5] & 0x0F], shmem_f32[q2[6] & 0x0F], shmem_f32[q2[7] & 0x0F]); - float4 acc4 = yl[3]*float4(shmem_f32[q2[4] >> 4 ], shmem_f32[q2[5] >> 4 ], shmem_f32[q2[6] >> 4 ], shmem_f32[q2[7] >> 4 ]); + // blocks are 17 bytes, so the 8 quant bytes are only byte aligned: read the aligned words that cover them + // and funnel-shift. the third word is read only when needed so no word past the block end is touched + device const uint32_t * pw = (device const uint32_t *)((ulong) q2 & ~3ul); + const uint sh = ((uint)(ulong) q2 & 3u)*8; + const uint32_t a = pw[0]; + const uint32_t b = pw[1]; + const uint32_t c = pw[sh ? 2 : 1]; + const uint32_t w0 = (a >> sh) | ((b << 1) << (31 - sh)); + const uint32_t w1 = (b >> sh) | ((c << 1) << (31 - sh)); + + float4 acc1 = yl[0]*mxfp4_lo4(w0); + float4 acc2 = yl[1]*mxfp4_hi4(w0); + float4 acc3 = yl[2]*mxfp4_lo4(w1); + float4 acc4 = yl[3]*mxfp4_hi4(w1); acc1 = (acc1 + acc3) + (acc2 + acc4); - sumf[row] += e8m0_to_fp32(xb.e) * ((acc1[0] + acc1[1]) + (acc1[2] + acc1[3])); + // 16384 undoes the 2^-14 of the decode + sumf[row] += (e8m0_to_fp32(xb.e)*16384.0f) * ((acc1[0] + acc1[1]) + (acc1[2] + acc1[3])); } yb += 16 * QK_MXFP4; @@ -3302,7 +3324,8 @@ kernel void kernel_mul_mv_id( uint3 tgpig[[threadgroup_position_in_grid]], ushort tiitg[[thread_index_in_threadgroup]], ushort tiisg[[thread_index_in_simdgroup]], - ushort sgitg[[simdgroup_index_in_threadgroup]]) { + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort3 ntg [[threads_per_threadgroup]]) { const int iid1 = tgpig.z/args.nei0; const int idx = tgpig.z%args.nei0; @@ -3316,11 +3339,20 @@ kernel void kernel_mul_mv_id( const int64_t i1 = idx; const int64_t i2 = i12; + device char * dst_cur = dst + (i1*args.ne0 + i2*args.ne1*args.ne0)*sizeof(float); + + if (i02 == -1) { + device float * dst_f32 = (device float *) dst_cur; + const ushort nth = ntg.x*ntg.y*ntg.z; + for (int i0 = tiitg; i0 < args.ne0; i0 += nth) { + dst_f32[i0] = 0.0f; + } + return; + } + device const char * src0_cur = src0s + i02*args.nb02; device const char * src1_cur = src1 + i11*args.nb11 + i12*args.nb12; - device char * dst_cur = dst + (i1*args.ne0 + i2*args.ne1*args.ne0)*sizeof(float); - ggml_metal_kargs_mul_mv args0 = { /*.ne00 =*/ args.ne00, /*.ne01 =*/ args.ne01, diff --git a/ggml/src/ggml-metal/kernels/pool.metal b/ggml/src/ggml-metal/kernels/pool.metal index 13d355b9deb3..3dc0261c3376 100644 --- a/ggml/src/ggml-metal/kernels/pool.metal +++ b/ggml/src/ggml-metal/kernels/pool.metal @@ -84,65 +84,117 @@ kernel void kernel_pool_1d_max_f32( constant ggml_metal_kargs_pool_1d & args, device const float * src, device float * dst, - uint gid [[thread_position_in_grid]] -) { - - if (gid >= args.np) { + threadgroup char * shmem [[threadgroup(0)]], + uint tgpig[[threadgroup_position_in_grid]], + uint tpitg[[thread_position_in_threadgroup]], + uint sgitg[[simdgroup_index_in_threadgroup]], + uint tiisg[[thread_index_in_simdgroup]], + uint ntg[[threads_per_threadgroup]]) { + if (tgpig >= args.np) { return; } - const int ow = (int)gid % args.OW; - const int row = (int)gid / args.OW; + const int out = (int) tgpig; + const int ow = out % (int) args.OW; + const int row = out / (int) args.OW; + + const int base = ow * args.s0 - args.p0; + const int src_off = row * args.IW; + const int dst_off = row * args.OW; + + float lmax = -INFINITY; + + for (int ki = tpitg; ki < args.k0; ki += ntg) { + const int j = base + ki; + if (j >= 0 && j < args.IW) { + lmax = max(lmax, src[src_off + j]); + } + } - const int base = ow * args.s0 - args.p0; + float max_val = simd_max(lmax); - float acc = -INFINITY; + threadgroup float * shared_max = (threadgroup float *) shmem; - const int src_off = row * args.IW; - const int dst_off = row * args.OW; + if (ntg > N_SIMDWIDTH) { + if (sgitg == 0) { + shared_max[tiisg] = -INFINITY; + } + threadgroup_barrier(mem_flags::mem_threadgroup); - for (int ki = 0; ki < args.k0; ++ki) { - int j = base + ki; - if (j < 0 || j >= args.IW){ - continue; + if (tiisg == 0) { + shared_max[sgitg] = max_val; } - float v = src[src_off + j]; - acc = max(acc, v); + threadgroup_barrier(mem_flags::mem_threadgroup); + + max_val = shared_max[tiisg]; + max_val = simd_max(max_val); } - dst[dst_off + ow] = acc; + if (tpitg == 0) { + dst[dst_off + ow] = max_val; + } } kernel void kernel_pool_1d_avg_f32( constant ggml_metal_kargs_pool_1d & args, device const float * src, device float * dst, - uint gid [[thread_position_in_grid]] -) { - - if (gid >= args.np) { + threadgroup char * shmem [[threadgroup(0)]], + uint tgpig[[threadgroup_position_in_grid]], + uint tpitg[[thread_position_in_threadgroup]], + uint sgitg[[simdgroup_index_in_threadgroup]], + uint tiisg[[thread_index_in_simdgroup]], + uint ntg[[threads_per_threadgroup]]) { + if (tgpig >= args.np) { return; } - const int ow = (int)gid % args.OW; - const int row = (int)gid / args.OW; - - const int base = ow * args.s0 - args.p0; + const int out = (int) tgpig; + const int ow = out % (int) args.OW; + const int row = out / (int) args.OW; - float acc = 0.0f; - int cnt = 0; + const int base = ow * args.s0 - args.p0; + const int src_off = row * args.IW; + const int dst_off = row * args.OW; - const int src_off = row * args.IW; - const int dst_off = row * args.OW; + float lsum = 0.0f; + int lcnt = 0; - for (int ki = 0; ki < args.k0; ++ki) { + for (int ki = tpitg; ki < args.k0; ki += ntg) { const int j = base + ki; - if (j < 0 || j >= args.IW) { - continue; + if (j >= 0 && j < args.IW) { + lsum += src[src_off + j]; + lcnt += 1; + } + } + + float sum = simd_sum(lsum); + float cnt = simd_sum((float) lcnt); + + threadgroup float * shared_sum = (threadgroup float *) shmem; + threadgroup float * shared_cnt = (threadgroup float *) shmem + N_SIMDWIDTH; + + if (ntg > N_SIMDWIDTH) { + if (sgitg == 0) { + shared_sum[tiisg] = 0.0f; + shared_cnt[tiisg] = 0.0f; + } + threadgroup_barrier(mem_flags::mem_threadgroup); + + if (tiisg == 0) { + shared_sum[sgitg] = sum; + shared_cnt[sgitg] = cnt; } - acc += src[src_off + j]; - cnt += 1; + threadgroup_barrier(mem_flags::mem_threadgroup); + + sum = shared_sum[tiisg]; + cnt = shared_cnt[tiisg]; + + sum = simd_sum(sum); + cnt = simd_sum(cnt); } - dst[dst_off + ow] = (cnt > 0) ? (acc / (float)cnt) : 0.0f; + if (tpitg == 0) { + dst[dst_off + ow] = (cnt > 0.0f) ? (sum / cnt) : 0.0f; + } } diff --git a/ggml/src/ggml-metal/kernels/quantize.h b/ggml/src/ggml-metal/kernels/quantize.h index 0741b22253ed..d3ba8884a521 100644 --- a/ggml/src/ggml-metal/kernels/quantize.h +++ b/ggml/src/ggml-metal/kernels/quantize.h @@ -20,6 +20,7 @@ void quantize_q1_0(device const float * src, device block_q1_0 & dst) { } void quantize_q2_0(device const float * src, device block_q2_0 & dst) { +#pragma METAL fp math_mode(safe) float amax = 0.0f; for (int j = 0; j < QK2_0; j++) { float a = fabs(src[j]); diff --git a/ggml/src/ggml-metal/kernels/unary.metal b/ggml/src/ggml-metal/kernels/unary.metal index e50a6486394c..b361da996ffa 100644 --- a/ggml/src/ggml-metal/kernels/unary.metal +++ b/ggml/src/ggml-metal/kernels/unary.metal @@ -3,6 +3,24 @@ constant short FC_unary_op [[function_constant(FC_UNARY + 0)]]; constant bool FC_unary_cnt[[function_constant(FC_UNARY + 1)]]; +template +inline constexpr T ggml_metal_unary_cast(U x) { + return (T) x; +} + +#if defined(GGML_METAL_HAS_BF16) +// MSL has no C-style cast from float vectors to bfloat vectors +template <> +inline bfloat4 ggml_metal_unary_cast(float4 x) { + return bfloat4(bfloat(x[0]), bfloat(x[1]), bfloat(x[2]), bfloat(x[3])); +} + +template <> +inline bfloat4 ggml_metal_unary_cast(float x) { + return bfloat4(bfloat(x), bfloat(x), bfloat(x), bfloat(x)); +} +#endif + template kernel void kernel_unary_impl( constant ggml_metal_kargs_unary & args, @@ -20,7 +38,7 @@ kernel void kernel_unary_impl( int i0; if (FC_CNT) { - i0 = tgpig.x; + i0 = tgpig.x*ntg.x + tpitg.x; src0_ptr = (device const T0 *) (src0); dst_ptr = (device T *) (dst); @@ -43,84 +61,88 @@ kernel void kernel_unary_impl( if (i0 >= args.ne0) { return; } + } else { + if (i0 >= args.ne00*args.ne01*args.ne02*args.ne03) { + return; + } } const TC x = (TC) src0_ptr[i0]; if (FC_OP == OP_UNARY_NUM_SCALE) { - dst_ptr[i0] = (T) (args.scale * x + args.bias); + dst_ptr[i0] = ggml_metal_unary_cast(args.scale * x + args.bias); } if (FC_OP == OP_UNARY_NUM_FILL) { - dst_ptr[i0] = (T) args.val; + dst_ptr[i0] = ggml_metal_unary_cast(args.val); } if (FC_OP == OP_UNARY_NUM_CLAMP) { - dst_ptr[i0] = (T) clamp(x, args.min, args.max); + dst_ptr[i0] = ggml_metal_unary_cast(clamp(x, args.min, args.max)); } if (FC_OP == OP_UNARY_NUM_SQR) { - dst_ptr[i0] = (T) (x * x); + dst_ptr[i0] = ggml_metal_unary_cast(x * x); } if (FC_OP == OP_UNARY_NUM_SQRT) { - dst_ptr[i0] = (T) sqrt(x); + dst_ptr[i0] = ggml_metal_unary_cast(sqrt(x)); } if (FC_OP == OP_UNARY_NUM_SIN) { - dst_ptr[i0] = (T) sin(x); + dst_ptr[i0] = ggml_metal_unary_cast(sin(x)); } if (FC_OP == OP_UNARY_NUM_COS) { - dst_ptr[i0] = (T) cos(x); + dst_ptr[i0] = ggml_metal_unary_cast(cos(x)); } if (FC_OP == OP_UNARY_NUM_LOG) { - dst_ptr[i0] = (T) log(x); + dst_ptr[i0] = ggml_metal_unary_cast(log(x)); } if (FC_OP == OP_UNARY_NUM_LEAKY_RELU) { - dst_ptr[i0] = (T) (TC(x > 0)*x + TC(x <= 0)*(x * args.slope)); + dst_ptr[i0] = ggml_metal_unary_cast(TC(x > 0)*x + TC(x <= 0)*(x * args.slope)); } if (FC_OP == OP_UNARY_NUM_TANH) { - dst_ptr[i0] = (T) precise::tanh(x); + dst_ptr[i0] = ggml_metal_unary_cast(precise::tanh(x)); } if (FC_OP == OP_UNARY_NUM_RELU) { - dst_ptr[i0] = (T) fmax(0, x); + dst_ptr[i0] = ggml_metal_unary_cast(fmax(0, x)); } if (FC_OP == OP_UNARY_NUM_SIGMOID) { - dst_ptr[i0] = (T) (1 / (1 + exp(-x))); + dst_ptr[i0] = ggml_metal_unary_cast(1 / (1 + exp(-x))); } if (FC_OP == OP_UNARY_NUM_GELU) { - dst_ptr[i0] = (T) (0.5*x*(1 + precise::tanh(SQRT_2_OVER_PI*x*(1 + GELU_COEF_A*x*x)))); + dst_ptr[i0] = ggml_metal_unary_cast(0.5*x*(1 + precise::tanh(SQRT_2_OVER_PI*x*(1 + GELU_COEF_A*x*x)))); } if (FC_OP == OP_UNARY_NUM_GELU_ERF) { - dst_ptr[i0] = (T) (0.5*x*(1 + erf_approx(SQRT_2_INV*x))); + dst_ptr[i0] = ggml_metal_unary_cast(0.5*x*(1 + erf_approx(SQRT_2_INV*x))); } if (FC_OP == OP_UNARY_NUM_GELU_QUICK) { - dst_ptr[i0] = (T) (x * (1/(1 + exp(GELU_QUICK_COEF*x)))); + dst_ptr[i0] = ggml_metal_unary_cast(x * (1/(1 + exp(GELU_QUICK_COEF*x)))); } if (FC_OP == OP_UNARY_NUM_SILU) { - dst_ptr[i0] = (T) (x / (1 + exp(-x))); + dst_ptr[i0] = ggml_metal_unary_cast(x / (1 + exp(-x))); } if (FC_OP == OP_UNARY_NUM_ELU) { - dst_ptr[i0] = (T) elu_approx(x); + dst_ptr[i0] = ggml_metal_unary_cast(elu_approx(x)); } if (FC_OP == OP_UNARY_NUM_NEG) { - dst_ptr[i0] = (T) -x; + dst_ptr[i0] = ggml_metal_unary_cast(-x); } if (FC_OP == OP_UNARY_NUM_ABS) { - dst_ptr[i0] = (T) fabs(x); + dst_ptr[i0] = ggml_metal_unary_cast(fabs(x)); } if (FC_OP == OP_UNARY_NUM_SGN) { @@ -132,40 +154,40 @@ kernel void kernel_unary_impl( } if (FC_OP == OP_UNARY_NUM_HARDSWISH) { - dst_ptr[i0] = (T) (x * fmax(0, fmin(1, x/6 + 0.5))); + dst_ptr[i0] = ggml_metal_unary_cast(x * fmax(0, fmin(1, x/6 + 0.5))); } if (FC_OP == OP_UNARY_NUM_HARDSIGMOID) { - dst_ptr[i0] = (T) fmax(0, fmin(1, x/6 + 0.5)); + dst_ptr[i0] = ggml_metal_unary_cast(fmax(0, fmin(1, x/6 + 0.5))); } if (FC_OP == OP_UNARY_NUM_EXP) { - dst_ptr[i0] = (T) exp(x); + dst_ptr[i0] = ggml_metal_unary_cast(exp(x)); } if (FC_OP == OP_UNARY_NUM_SOFTPLUS) { - dst_ptr[i0] = (T) select(log(1 + exp(x)), x, x > 20); + dst_ptr[i0] = ggml_metal_unary_cast(select(log(1 + exp(x)), x, x > 20)); } if (FC_OP == OP_UNARY_NUM_EXPM1) { // TODO: precise implementation - dst_ptr[i0] = (T) (exp(x) - 1); + dst_ptr[i0] = ggml_metal_unary_cast(exp(x) - 1); } if (FC_OP == OP_UNARY_NUM_FLOOR) { - dst_ptr[i0] = (T) floor(x); + dst_ptr[i0] = ggml_metal_unary_cast(floor(x)); } if (FC_OP == OP_UNARY_NUM_CEIL) { - dst_ptr[i0] = (T) ceil(x); + dst_ptr[i0] = ggml_metal_unary_cast(ceil(x)); } if (FC_OP == OP_UNARY_NUM_ROUND) { - dst_ptr[i0] = (T) round(x); + dst_ptr[i0] = ggml_metal_unary_cast(round(x)); } if (FC_OP == OP_UNARY_NUM_TRUNC) { - dst_ptr[i0] = (T) trunc(x); + dst_ptr[i0] = ggml_metal_unary_cast(trunc(x)); } if (FC_OP == OP_UNARY_NUM_XIELU) { @@ -174,7 +196,7 @@ kernel void kernel_unary_impl( const TC clamped = fmin(xi, TC(args.val)); const TC y_pos = TC(args.scale) * xi * xi + TC(args.bias) * xi; const TC y_neg = (exp(clamped) - TC(1.0f) - xi) * TC(args.slope) + TC(args.bias) * xi; - dst_ptr[i0] = (T) (gate * y_pos + (TC(1.0f) - gate) * y_neg); + dst_ptr[i0] = ggml_metal_unary_cast(gate * y_pos + (TC(1.0f) - gate) * y_neg); } } @@ -188,6 +210,10 @@ template [[host_name("kernel_unary_f32_f32")]] kernel kernel_unary_t kernel_un template [[host_name("kernel_unary_f32_f32_4")]] kernel kernel_unary_t kernel_unary_impl; template [[host_name("kernel_unary_f16_f16")]] kernel kernel_unary_t kernel_unary_impl; template [[host_name("kernel_unary_f16_f16_4")]] kernel kernel_unary_t kernel_unary_impl; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_unary_bf16_bf16")]] kernel kernel_unary_t kernel_unary_impl; +template [[host_name("kernel_unary_bf16_bf16_4")]] kernel kernel_unary_t kernel_unary_impl; +#endif kernel void kernel_silu_back_f32( constant ggml_metal_kargs_silu_back & args, @@ -209,14 +235,15 @@ kernel void kernel_reglu( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float x0 = src0_row[i0]; const float x1 = src1_row[i0]; @@ -235,14 +262,15 @@ kernel void kernel_geglu( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float x0 = src0_row[i0]; const float x1 = src1_row[i0]; @@ -263,14 +291,15 @@ kernel void kernel_swiglu( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float x0 = src0_row[i0]; const float x1 = src1_row[i0]; @@ -291,14 +320,15 @@ kernel void kernel_swiglu_oai( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { float x0 = src0_row[i0]; float x1 = src1_row[i0]; @@ -323,14 +353,15 @@ kernel void kernel_swiglu_clamp( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float gate = min((float) src0_row[i0], args.limit); const float up = clamp((float) src1_row[i0], -args.limit, args.limit); @@ -349,14 +380,15 @@ kernel void kernel_geglu_erf( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float x0 = src0_row[i0]; const float x1 = src1_row[i0]; @@ -377,14 +409,15 @@ kernel void kernel_geglu_quick( device const char * src0, device const char * src1, device char * dst, - uint tgpig[[threadgroup_position_in_grid]], - uint tpitg[[thread_position_in_threadgroup]], - uint ntg[[threads_per_threadgroup]]) { - device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; - device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; - device T * dst_row = (device T *) ((device char *) dst + tgpig*args.nb1); - - for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + uint2 tgpig[[threadgroup_position_in_grid]], + uint2 tpitg[[thread_position_in_threadgroup]], + uint2 ntg[[threads_per_threadgroup]], + uint2 ntgs[[threadgroups_per_grid]]) { + device const T * src0_row = (device const T *) ((device const char *) src0 + tgpig.y*args.nb01) + args.i00; + device const T * src1_row = (device const T *) ((device const char *) src1 + tgpig.y*args.nb11) + args.i10; + device T * dst_row = (device T *) ((device char *) dst + tgpig.y*args.nb1); + + for (int i0 = tgpig.x*ntg.x + tpitg.x; i0 < args.ne0; i0 += ntg.x*ntgs.x) { const float x0 = src0_row[i0]; const float x1 = src1_row[i0]; diff --git a/ggml/src/ggml-opencl/CMakeLists.txt b/ggml/src/ggml-opencl/CMakeLists.txt index 97b862afffd8..79fc37b60990 100644 --- a/ggml/src/ggml-opencl/CMakeLists.txt +++ b/ggml/src/ggml-opencl/CMakeLists.txt @@ -64,9 +64,14 @@ set(GGML_OPENCL_KERNELS add add_id moe_add_id_glu + argmax argsort + top_k + top_k_mask + lightning_indexer tri fill + fwht clamp cpy cvt @@ -80,6 +85,8 @@ set(GGML_OPENCL_KERNELS solve_tri im2col_f32 im2col_f16 + im2col_3d_f32 + im2col_3d_f16 mean mul_mv_f16_f16 mul_mv_f16_f32_1row @@ -96,6 +103,72 @@ set(GGML_OPENCL_KERNELS mul_mv_q4_0_f32_1d_16x_flat mul_mv_q4_1_f32 mul_mv_q4_1_f32_flat + gemm_noshuffle_q2_k_q8_1_dp4a + gemv_noshuffle_q2_k_f32 + gemm_noshuffle_q2_k_f32 + gemm_noshuffle_q3_k_f32 + gemm_noshuffle_iq2_s_f32 + gemm_noshuffle_iq2_xs_f32 + gemm_noshuffle_iq2_xxs_f32 + gemm_noshuffle_iq2_xxs_q8_1_dp4a + gemv_noshuffle_iq2_xxs_f32 + gemm_noshuffle_iq2_xs_q8_1_dp4a + gemv_noshuffle_iq2_xs_f32 + gemm_noshuffle_iq2_s_q8_1_dp4a + gemv_noshuffle_iq2_s_f32 + gemm_noshuffle_q2_0_f32 + gemm_noshuffle_q2_0_q8_1_dp4a + gemv_noshuffle_q2_0_f32 + gemm_noshuffle_iq1_m_f32 + gemm_noshuffle_iq1_m_q8_1_dp4a + gemv_noshuffle_iq1_m_f32 + gemm_noshuffle_iq1_s_f32 + gemm_noshuffle_iq1_s_q8_1_dp4a + gemv_noshuffle_iq1_s_f32 + gemm_noshuffle_iq3_s_f32 + gemm_noshuffle_iq3_s_q8_1_dp4a + gemv_noshuffle_iq3_s_f32 + gemm_noshuffle_iq3_xxs_f32 + gemm_noshuffle_iq3_xxs_q8_1_dp4a + gemv_noshuffle_iq3_xxs_f32 + gemm_noshuffle_q3_k_q8_1_dp4a + gemv_noshuffle_q3_k_f32 + mul_mv_q2_k_f32 + mul_mv_q3_k_f32 + iq2_s_grid + mul_mv_iq2_s_f32 + iq2_xs_grid + mul_mv_iq2_xs_f32 + iq2_xxs_grid + mul_mv_iq2_xxs_f32 + mul_mv_iq2_xxs_f32_flat + mul_mm_iq2_xxs_f32_l4_lm + mul_mv_iq2_xs_f32_flat + mul_mm_iq2_xs_f32_l4_lm + mul_mv_iq2_s_f32_flat + mul_mm_iq2_s_f32_l4_lm + mul_mv_q2_0_f32 + mul_mv_q2_0_f32_flat + mul_mm_q2_0_f32_l4_lm + mul_mv_iq1_m_f32 + mul_mv_iq1_m_f32_flat + mul_mm_iq1_m_f32_l4_lm + iq1_s_grid + mul_mv_iq1_s_f32 + mul_mv_iq1_s_f32_flat + mul_mm_iq1_s_f32_l4_lm + iq3_xxs_grid + mul_mv_iq3_xxs_f32 + mul_mv_iq3_xxs_f32_flat + mul_mm_iq3_xxs_f32_l4_lm + iq3_s_grid + mul_mv_iq3_s_f32 + mul_mv_iq3_s_f32_flat + mul_mm_iq3_s_f32_l4_lm + mul_mv_q3_k_f32_flat + mul_mm_q3_k_f32_l4_lm + mul_mv_q2_k_f32_flat + mul_mm_q2_k_f32_l4_lm mul_mv_q4_k_f32 mul_mv_q4_k_f32_flat mul_mv_q5_0_f32 @@ -117,6 +190,7 @@ set(GGML_OPENCL_KERNELS mul_mv_id_q8_0_f32_flat mul_mv_id_mxfp4_f32 mul_mv_id_mxfp4_f32_flat + mul_mat_id_utils gemm_moe_q4_0_f32_ns gemm_moe_q4_0_q8_1_dp4a gemv_moe_q4_0_f32_ns @@ -132,6 +206,7 @@ set(GGML_OPENCL_KERNELS gemm_moe_q6_k_q8_1_dp4a gemm_moe_q8_1_dp4a moe_reorder_quant_a_q8_1 + transpose_activation_q8 gemm_noshuffle_q4_k_q8_1_dp4a gemm_noshuffle_q5_k_q8_1_dp4a gemm_noshuffle_q6_k_q8_1_dp4a @@ -139,6 +214,9 @@ set(GGML_OPENCL_KERNELS gemm_noshuffle_q5_0_q8_1_dp4a gemm_noshuffle_iq4_nl_q8_1_dp4a gemm_noshuffle_q4_0_q8_1_dp4a + gemm_coopk_q4_0_q8_1_dp4a + gemm_coopk_q4_k_q8_1_dp4a + gemm_coopk_q6_k_q8_1_dp4a quant_a_q8_1 gemv_moe_q4_k_f32_ns gemm_moe_q5_k_f32_ns @@ -184,6 +262,7 @@ set(GGML_OPENCL_KERNELS gemv_noshuffle_q4_k_f32 gemv_noshuffle_q4_k_f32_o4 gemv_noshuffle_q4_k_f32_tiled + gemm_noshuffle_q4_K_f32_tiled_dp4a gemm_noshuffle_q4_k_f32 gemv_noshuffle_q4_k_f32_32b_trans gemv_noshuffle_q6_k_f32 @@ -234,6 +313,7 @@ set(GGML_OPENCL_KERNELS mul_mm_f16_f32_kq_kqv conv2d conv2d_f16_f32 + conv2_dw flash_attn_repack flash_attn_pre_f16 flash_attn_f32_f16 diff --git a/ggml/src/ggml-opencl/ggml-opencl.cpp b/ggml/src/ggml-opencl/ggml-opencl.cpp index 2b8e8271df5d..6f0e4499e057 100644 --- a/ggml/src/ggml-opencl/ggml-opencl.cpp +++ b/ggml/src/ggml-opencl/ggml-opencl.cpp @@ -646,8 +646,8 @@ struct ggml_backend_opencl_context { ggml_cl_version platform_version; ggml_cl_version opencl_c_version; - // argsort is loaded in supports_op because its availability depends on how - // many workgroups are allowed, which requires kernel compilation. + // argmax and argsort are loaded in supports_op; argsort availability depends on the compiled kernel's workgroup limit. + bool kernels_loaded_argmax = false; bool kernels_loaded_argsort = false; // rest of the kernels are currently always loaded in alloc_buffer. bool kernels_loaded = false; @@ -661,8 +661,10 @@ struct ggml_backend_opencl_context { size_t global_mem_size; size_t max_alloc_size; size_t max_workgroup_size; + cl_ulong local_mem_size; bool fp16_support; bool has_vector_subgroup_broadcast; + bool has_khr_subgroup_shuffle = false; bool has_subgroup_shuffle = false; // cl_khr_subgroup_shuffle or cl_qcom_subgroup_shuffle bool has_integer_dot = false; // cl_khr_integer_dot_product or cl_qcom_dot_product8 bool has_qcom_subgroup_shuffle = false; // specifically cl_qcom_subgroup_shuffle @@ -720,6 +722,10 @@ struct ggml_backend_opencl_context { ggml_cl_buffer prealloc_moe_qa; // int8 quants [tok_slots * ne00] ggml_cl_buffer prealloc_moe_da; // per-block d [tok_slots * ne00/32] (half) ggml_cl_buffer prealloc_moe_sa; // per-block s [tok_slots * ne00/32] (half) + // per-tile transposed qa/da and on-chip scratch for the ldck dp4a MoE GEMM + ggml_cl_buffer prealloc_moe_qa_trans; // int8 quants [tok_slots * ne00] + ggml_cl_buffer prealloc_moe_da_trans; // per-block d [tok_slots * ne00/32] (float) + ggml_cl_buffer prealloc_moe_qda_on_chip; // scratch copy of the router weights to avoid dst aliasing ggml_cl_buffer prealloc_moe_combine_w; ggml_cl_buffer prealloc_splitk_partial; // [ksplit * M] partials for split-K GEMV @@ -751,6 +757,7 @@ struct ggml_backend_opencl_context { // prealloc buffers for src0 and src1 ggml_cl_buffer prealloc_src0; ggml_cl_buffer prealloc_src1; + ggml_cl_buffer prealloc_top_k; #ifdef GGML_OPENCL_USE_ADRENO_KERNELS ggml_cl_buffer prealloc_adreno_xmem_const; @@ -827,6 +834,7 @@ struct ggml_backend_opencl_context { cl_program program_mul_mv_id_mxfp4_f32_flat; cl_program program_mul_mm_f32_f32_l4_lm; cl_program program_mul_mm_f16_f32_l4_lm; + cl_program program_mul_mm_f16_f32_l4_lm_n8; cl_program program_mul_mm_q8_0_f32_l4_lm; cl_kernel kernel_add, kernel_add_row, kernel_add_f16, kernel_add_row_f16; @@ -864,7 +872,10 @@ struct ggml_backend_opencl_context { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS ggml_cl_adreno_xmem_attn_state adreno_xmem_attn; #endif - cl_kernel kernel_get_rows_f32, kernel_get_rows_f16, kernel_get_rows_q4_0; + cl_kernel kernel_top_k_f32, kernel_top_k_merge_f32; + cl_kernel kernel_top_k_mask[2], kernel_top_k_mask_fill[2]; + cl_kernel kernel_lightning_indexer; + cl_kernel kernel_get_rows_f32, kernel_get_rows_f16, kernel_get_rows_i32, kernel_get_rows_q4_0; cl_kernel kernel_set_rows_f32_i64, kernel_set_rows_f32_i32, kernel_set_rows_f16_i64, kernel_set_rows_f16_i32; cl_kernel kernel_set_rows_q8_0_i64, kernel_set_rows_q8_0_i32; cl_kernel kernel_set_rows_q8_0_soa_i64, kernel_set_rows_q8_0_soa_i32; @@ -872,10 +883,12 @@ struct ggml_backend_opencl_context { cl_kernel kernel_set_rows_q4_0_soa_i64, kernel_set_rows_q4_0_soa_i32; cl_kernel kernel_rope_norm_f32, kernel_rope_norm_f16, kernel_rope_neox_f32, kernel_rope_neox_f16; cl_kernel kernel_rope_multi_f32, kernel_rope_multi_f16, kernel_rope_vision_f32, kernel_rope_vision_f16; - cl_kernel kernel_cpy_f16_f16, kernel_cpy_f16_f32, kernel_cpy_f32_f16, kernel_cpy_f32_f32, kernel_cpy_i32_i32; + cl_kernel kernel_cpy_f16_f16, kernel_cpy_f16_f32, kernel_cpy_f32_f16, kernel_cpy_f32_f32, kernel_cpy_i32_i32, kernel_cpy_i32_f32, kernel_cpy_f32_i32; cl_kernel kernel_cpy_f32_f32_pack = nullptr; cl_kernel kernel_cpy_f32_f32_flat = nullptr; cl_kernel kernel_mul_mat_f32_f32; + cl_kernel kernel_fwht[2] = {}; + size_t fwht_workgroup_size[2] = {}; cl_kernel kernel_mul_mat_f16_f16; cl_kernel kernel_mul_mat_f16_f32_1row; cl_program program_mul_mv_f16_f32_mrow; @@ -954,6 +967,113 @@ struct ggml_backend_opencl_context { cl_kernel kernel_mul_mv_q5_0_f32_flat; cl_kernel kernel_mul_mv_q5_1_f32; cl_kernel kernel_mul_mv_q5_1_f32_flat; + cl_kernel kernel_convert_block_q2_K, kernel_restore_block_q2_K; + cl_kernel kernel_mul_mv_q2_K_f32_flat; + cl_kernel kernel_mul_mm_q2_k_f32_l4_lm; + cl_kernel kernel_convert_block_q2_k_noshuffle; + cl_kernel kernel_restore_block_q2_k_noshuffle; + cl_kernel kernel_gemv_noshuffle_q2_k_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_k_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_k_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_k_q8_1_dp4a_narrow = nullptr; + int q2_k_mv_rows = 4; + int q2_k_mv_nsg = 4; + cl_kernel kernel_mul_mv_q2_K_f32; + cl_kernel kernel_convert_block_q3_K, kernel_restore_block_q3_K; + cl_kernel kernel_mul_mv_q3_K_f32_flat; + cl_kernel kernel_mul_mm_q3_k_f32_l4_lm; + cl_kernel kernel_convert_block_q3_k_noshuffle, kernel_restore_block_q3_k_noshuffle; + cl_kernel kernel_gemv_noshuffle_q3_k_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q3_k_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q3_k_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_q3_k_q8_1_dp4a_narrow = nullptr; + int q3_k_mv_rows = 2; + int q3_k_mv_nsg = 8; + cl_kernel kernel_mul_mv_q3_K_f32; + cl_kernel kernel_convert_block_iq2_s, kernel_restore_block_iq2_s; + cl_kernel kernel_mul_mv_iq2_s_f32_flat; + cl_kernel kernel_mul_mm_iq2_s_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq2_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_s_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_s_q8_1_dp4a_narrow = nullptr; + int iq2_s_mv_nsg = 8; + ggml_cl_buffer iq2_s_grid_buffer; + cl_mem iq2_s_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq2_s_f32; + cl_kernel kernel_convert_block_iq2_xs, kernel_restore_block_iq2_xs; + cl_kernel kernel_mul_mv_iq2_xs_f32_flat; + cl_kernel kernel_mul_mm_iq2_xs_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq2_xs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a_narrow = nullptr; + int iq2_xs_mv_nsg = 4; + ggml_cl_buffer iq2_xs_grid_buffer; + cl_mem iq2_xs_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq2_xs_f32; + cl_kernel kernel_convert_block_iq2_xxs, kernel_restore_block_iq2_xxs; + cl_kernel kernel_mul_mv_iq2_xxs_f32_flat; + cl_kernel kernel_mul_mm_iq2_xxs_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq2_xxs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xxs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a_narrow = nullptr; + int iq2_xxs_mv_nsg = 4; + ggml_cl_buffer iq2_xxs_grid_buffer; + cl_mem iq2_xxs_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq2_xxs_f32; + cl_kernel kernel_convert_block_q2_0, kernel_restore_block_q2_0; + cl_kernel kernel_mul_mv_q2_0_f32_flat; + cl_kernel kernel_mul_mm_q2_0_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_q2_0_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_0_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_0_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_q2_0_q8_1_dp4a_narrow = nullptr; + int q2_0_mv_nsg = 8; + cl_kernel kernel_mul_mv_q2_0_f32; + cl_kernel kernel_convert_block_iq1_m, kernel_restore_block_iq1_m; + cl_kernel kernel_mul_mv_iq1_m_f32_flat; + cl_kernel kernel_mul_mm_iq1_m_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq1_m_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_m_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_m_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_m_q8_1_dp4a_narrow = nullptr; + int iq1_m_mv_nsg = 4; + cl_kernel kernel_mul_mv_iq1_m_f32; + cl_kernel kernel_convert_block_iq1_s, kernel_restore_block_iq1_s; + cl_kernel kernel_mul_mv_iq1_s_f32_flat; + cl_kernel kernel_mul_mm_iq1_s_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq1_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_s_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq1_s_q8_1_dp4a_narrow = nullptr; + int iq1_s_mv_nsg = 4; + ggml_cl_buffer iq1_s_grid_buffer; + cl_mem iq1_s_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq1_s_f32; + cl_kernel kernel_convert_block_iq3_xxs, kernel_restore_block_iq3_xxs; + cl_kernel kernel_mul_mv_iq3_xxs_f32_flat; + cl_kernel kernel_mul_mm_iq3_xxs_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq3_xxs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_xxs_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a_narrow = nullptr; + int iq3_xxs_mv_nsg = 4; + ggml_cl_buffer iq3_xxs_grid_buffer; + cl_mem iq3_xxs_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq3_xxs_f32; + cl_kernel kernel_convert_block_iq3_s, kernel_restore_block_iq3_s; + cl_kernel kernel_mul_mv_iq3_s_f32_flat; + cl_kernel kernel_mul_mm_iq3_s_f32_l4_lm; + cl_kernel kernel_gemv_noshuffle_iq3_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_s_f32 = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_s_q8_1_dp4a = nullptr; + cl_kernel kernel_gemm_noshuffle_iq3_s_q8_1_dp4a_narrow = nullptr; + int iq3_s_mv_nsg = 4; + ggml_cl_buffer iq3_s_grid_buffer; + cl_mem iq3_s_grid_image = nullptr; + cl_kernel kernel_mul_mv_iq3_s_f32; cl_kernel kernel_mul_mv_q4_K_f32; cl_kernel kernel_mul_mv_q4_K_f32_flat; cl_kernel kernel_mul_mv_q5_K_f32; @@ -966,6 +1086,8 @@ struct ggml_backend_opencl_context { cl_kernel kernel_mul_mv_iq4_nl_f32_flat; cl_kernel kernel_solve_tri_f32; cl_kernel kernel_im2col_f32, kernel_im2col_f16; + cl_kernel kernel_im2col_3d_f32, kernel_im2col_3d_f16; + cl_kernel kernel_argmax_f32_i32; cl_kernel kernel_argsort_f32_i32; cl_kernel kernel_sum_rows_f32, kernel_sum_rows_f32_4; cl_kernel kernel_cumsum_blk, kernel_cumsum_add; @@ -998,6 +1120,7 @@ struct ggml_backend_opencl_context { cl_kernel kernel_conv_2d_f16; cl_kernel kernel_conv_2d_f32; cl_kernel kernel_conv_2d_f16_f32; + cl_kernel kernel_conv2d_dw_f32_f32, kernel_conv2d_dwf16_f32; cl_kernel kernel_ssm_conv_f32_f32, kernel_ssm_conv_f32_f32_4; // [size_idx][kda][tgpp] where size_idx: 0=S_V=16, 1=32, 2=64, 3=128; kda: 0 or 1. // tgpp 0 = TG variant (COLS_PER_LANE_GROUP=1), tgpp 1 = prefill variant (COLS_PER_LANE_GROUP=4). @@ -1016,6 +1139,7 @@ struct ggml_backend_opencl_context { cl_kernel kernel_gemv_moe_q4_k_f32_ns_wimg = nullptr; // weight-as-texture MoE decode GEMV (opt-in) cl_kernel kernel_gemm_moe_q4_k_q8_1_dp4a = nullptr; // dp4a (int8) prefill GEMM variant cl_kernel kernel_moe_reorder_quant_a_q8_1; // fused reorder + q8_1 quant for the dp4a GEMM + cl_kernel kernel_transpose_activation_q8; // per-tile transpose of q8_1 activations for the ldck dp4a GEMM cl_kernel kernel_gemm_moe_q8_1_dp4a_q80 = nullptr; // generic dp4a MoE GEMM (MOE_QT=80), opt-in cl_kernel kernel_moe_expand_scale_q8_0 = nullptr; // q8_0 per-block d -> uniform scale[16] cl_kernel kernel_gemm_moe_q8_1_dp4a_q50 = nullptr; // generic dp4a MoE GEMM (MOE_QT=50, q5_0), opt-in @@ -1031,12 +1155,14 @@ struct ggml_backend_opencl_context { cl_kernel kernel_gemm_moe_mxfp4_q8_1_dp4a = nullptr; // dp4a (int8) mxfp4 MoE prefill GEMM cl_kernel kernel_gemm_moe_q4_0_q8_1_dp4a = nullptr; // dp4a (int8) q4_0 MoE prefill GEMM cl_kernel kernel_gemm_moe_mxfp4_q8_1_dp4a_bin = nullptr; // binary dp4a (int8) mxfp4 MoE prefill GEMM + cl_kernel kernel_gemm_moe_mxfp4_q8_1_dp4a_ldck_bin = nullptr; // binary dp4a (int8) mxfp4 MoE prefill GEMM using ldck cl_kernel kernel_gemm_moe_q4_0_q8_1_dp4a_bin = nullptr; // binary dp4a (int8) q4_0 MoE prefill GEMM cl_kernel kernel_gemm_moe_q4_k_q8_1_dp4a_bin = nullptr; // binary dp4a (int8) q4_k MoE prefill GEMM cl_kernel kernel_gemm_moe_q6_k_q8_1_dp4a_bin = nullptr; // binary dp4a (int8) q6_k MoE prefill GEMM cl_kernel kernel_moe_reorder_b; cl_kernel kernel_moe_histogram, kernel_moe_scan, kernel_moe_fill, kernel_moe_scatter; cl_kernel kernel_moe_scatter_stable = nullptr; // deterministic slot assignment + cl_kernel kernel_moe_zero_dst; cl_kernel kernel_moe_combine_f32 = nullptr; // fused router-weight mul + cross-expert sum cl_kernel kernel_moe_combine_bias_f32 = nullptr; // same, with the down-projection bias add folded in cl_kernel kernel_mul_mv_id_q4_0_f32_8x_flat; @@ -1046,6 +1172,7 @@ struct ggml_backend_opencl_context { cl_kernel kernel_mul_mm_f32_f32_l4_lm; cl_kernel kernel_gemv_f32_f32_mc; // multi-column (small-N) f32 GEMV for spec/MTP verify cl_kernel kernel_mul_mm_f16_f32_l4_lm; + cl_kernel kernel_mul_mm_f16_f32_l4_lm_n8; cl_kernel kernel_mul_mm_q1_0_f32_l4_lm; cl_kernel kernel_mul_mm_q4_0_f32_l4_lm; cl_kernel kernel_mul_mm_q4_1_f32_l4_lm; @@ -1235,15 +1362,19 @@ struct ggml_backend_opencl_context { cl_kernel kernel_gemm_noshuffle_q4_1_f32; cl_kernel kernel_gemm_noshuffle_q8_0_f32, kernel_gemm_noshuffle_q8_0_f32_bin; cl_kernel kernel_gemm_noshuffle_q8_0_q8_1_dp4a = nullptr; // dp4a (int8) dense q8_0 prefill GEMM (opt-in) + cl_kernel kernel_gemm_noshuffle_q8_0_q8_1_dp4a_act_vload4 = nullptr; cl_kernel kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg = nullptr; // q8_0 dense dp4a, weights via texture (opt-in) cl_kernel kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin = nullptr; cl_kernel kernel_gemv_noshuffle_q8_0_f32; cl_kernel kernel_gemv_noshuffle_q8_0_f32_splitk; // split-K across WGs (small-M decode) cl_kernel kernel_gemm_noshuffle_q1_0_f32; cl_kernel kernel_gemv_noshuffle_q1_0_f32; + cl_kernel kernel_gemv_noshuffle_q1_0_f32_nsg1 = nullptr; + int min_m_gemv_nsg1_q1_0 = 0; cl_kernel kernel_gemv_noshuffle_q4_k_f32; cl_kernel kernel_gemv_noshuffle_q4_k_f32_o4; // 4-output-per-WI, long-vocab lm_head cl_kernel kernel_gemv_noshuffle_q4_k_f32_tiled; // tiled-wide layout (opt-in) + cl_kernel kernel_gemm_noshuffle_q4_K_f32_tiled_dp4a = nullptr; cl_kernel kernel_gemv_noshuffle_q4_k_f32_splitk; // split-K across WGs (small-M decode) cl_kernel kernel_gemv_splitk_reduce_f32; // sums split-K per-slice partials cl_kernel kernel_gemv_noshuffle_q4_k_f32_glu; // fused gate+up GEMV + GLU (FFN) @@ -1254,9 +1385,17 @@ struct ggml_backend_opencl_context { cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin; cl_kernel kernel_gemv_noshuffle_q4_k_f32_32b_trans; cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a = nullptr; // dp4a (int8) dense prefill GEMM + cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_act_vload4 = nullptr; cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg = nullptr; // dp4a dense prefill GEMM, weights via texture (X1 opt-in) + cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow = nullptr; + cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow_wimg = nullptr; + int tile_n_dp4a_q4_k = 32; + int tile_n_dp4a_narrow_q4_k = 32; + int max_n_dp4a_narrow_q4_k = 16; cl_kernel kernel_gemm_noshuffle_q5_k_q8_1_dp4a = nullptr; // dp4a (int8) dense q5_K prefill GEMM + cl_kernel kernel_gemm_noshuffle_q5_k_q8_1_dp4a_act_vload4 = nullptr; cl_kernel kernel_gemm_noshuffle_q6_k_q8_1_dp4a = nullptr; // dp4a (int8) dense q6_K prefill GEMM + cl_kernel kernel_gemm_noshuffle_q6_k_q8_1_dp4a_act_vload4 = nullptr; cl_kernel kernel_quant_a_q8_1; // plain activation q8_1 pre-pass cl_kernel kernel_gemm_noshuffle_q4_k_f32_r1; cl_kernel kernel_gemm_noshuffle_q4_k_f32_kimg; @@ -1290,8 +1429,46 @@ struct ggml_backend_opencl_context { cl_kernel kernel_gemm_noshuffle_iq4_nl_f32; cl_kernel kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a = nullptr; // dp4a (int8) dense IQ4_NL prefill GEMM cl_kernel kernel_gemm_noshuffle_q4_0_q8_1_dp4a = nullptr; // dp4a (int8) dense q4_0 prefill GEMM + cl_kernel kernel_gemm_noshuffle_q4_0_q8_1_dp4a_act_vload4 = nullptr; + cl_kernel kernel_gemm_coopk_q4_0_q8_1_dp4a_c4 = nullptr; + cl_kernel kernel_gemm_coopk_q4_0_q8_1_dp4a_c2 = nullptr; + int nsg_coopk_dp4a_q4_0 = 8; + int rows_coopk_dp4a_q4_0 = 4; + cl_kernel kernel_gemm_coopk_q4_k_q8_1_dp4a_c4 = nullptr; + cl_kernel kernel_gemm_coopk_q4_k_q8_1_dp4a_c2 = nullptr; + int nsg_coopk_dp4a_q4_k = 8; + int rows_coopk_dp4a_q4_k = 4; + cl_kernel kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c4 = nullptr; + cl_kernel kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c2 = nullptr; + int nsg_coopk_dp4a_q4_k_bin_c4 = 8; + int nsg_coopk_dp4a_q4_k_bin_c2 = 8; + cl_kernel kernel_gemm_coopk_q6_k_q8_1_dp4a_c4 = nullptr; + cl_kernel kernel_gemm_coopk_q6_k_q8_1_dp4a_c2 = nullptr; + int nsg_coopk_dp4a_q6_k = 8; + int rows_coopk_dp4a_q6_k = 4; #endif // GGML_OPENCL_USE_ADRENO_KERNELS + ~ggml_backend_opencl_context() { + if (iq1_s_grid_image) { + CL_CHECK(clReleaseMemObject(iq1_s_grid_image)); + } + if (iq3_xxs_grid_image) { + CL_CHECK(clReleaseMemObject(iq3_xxs_grid_image)); + } + if (iq3_s_grid_image) { + CL_CHECK(clReleaseMemObject(iq3_s_grid_image)); + } + if (iq2_xxs_grid_image) { + CL_CHECK(clReleaseMemObject(iq2_xxs_grid_image)); + } + if (iq2_xs_grid_image) { + CL_CHECK(clReleaseMemObject(iq2_xs_grid_image)); + } + if (iq2_s_grid_image) { + CL_CHECK(clReleaseMemObject(iq2_s_grid_image)); + } + } + void free() { clFinish(queue); @@ -1448,6 +1625,61 @@ static cl_program build_program_from_binary(cl_context ctx, cl_device_id dev, co return p; } +static void load_cl_kernels_argmax(ggml_backend_opencl_context *backend_ctx) { + auto opencl_c_std = + std::string("CL") + std::to_string(backend_ctx->opencl_c_version.major) + "." + std::to_string(backend_ctx->opencl_c_version.minor); + std::string compile_opts = std::string("-cl-std=") + opencl_c_std; + + if (!backend_ctx->kernels_loaded_argmax) { + cl_int err; +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "argmax.cl.h" + }; +#else + const std::string kernel_src = read_file("argmax.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_argmax_f32_i32 = clCreateKernel(prog, "kernel_argmax_f32_i32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + backend_ctx->kernels_loaded_argmax = true; + } +} + +static std::string ggml_cl_q2_k_mm_options(const ggml_backend_opencl_context * backend_ctx) { + const bool x2 = backend_ctx->gpu_family == ADRENO && + (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A8X || backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + int bk = x2 ? 16 : 32; + bool half = x2; + if (const char * env = getenv("GGML_OPENCL_LM_BK")) { + const int value = atoi(env); + if (value == 16 || value == 32) { + bk = value; + } + } + if (const char * env = getenv("GGML_OPENCL_LM_HALF")) { + half = atoi(env) != 0; + } + return " -DBK=" + std::to_string(bk) + " -DLM_HALF=" + std::to_string(half ? 1 : 0); +} + +static std::string ggml_cl_q3_k_mm_options(const ggml_backend_opencl_context * backend_ctx) { + const bool x2 = backend_ctx->gpu_family == ADRENO && + (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A8X || backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + int bk = x2 ? 16 : 32; + bool half = x2; + if (const char * env = getenv("GGML_OPENCL_LM_BK")) { + const int value = atoi(env); + if (value == 16 || value == 32) { + bk = value; + } + } + if (const char * env = getenv("GGML_OPENCL_LM_HALF")) { + half = atoi(env) != 0; + } + return " -DBK=" + std::to_string(bk) + " -DLM_HALF=" + std::to_string(half ? 1 : 0); +} + static void load_cl_kernels_argsort(ggml_backend_opencl_context *backend_ctx) { // compiler options for general kernels auto opencl_c_std = @@ -1486,6 +1718,180 @@ static bool use_adreno_bin_kernels(ggml_backend_opencl_context * backend_ctx) { #endif // GGML_OPENCL_USE_ADRENO_BIN_KERNELS } +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static bool ggml_cl_coopk_dp4a_enabled(const ggml_backend_opencl_context * backend_ctx) { + static const char * const env = getenv("GGML_OPENCL_COOPK_DP4A"); + if (env && *env && atoi(env) == 0) { + return false; + } + if (!backend_ctx->has_integer_dot) { + return false; + } + if (backend_ctx->gpu_family == GPU_FAMILY::ADRENO) { + if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::ADRENO_UNKNOWN || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X) { + return false; + } + if (backend_ctx->adreno_cl_compiler_version.type == ADRENO_CL_COMPILER_TYPE::E17) { + return false; + } + } + return true; +} + +static bool ggml_cl_coopk_dp4a_narrow_on(const ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * op, int rows) { + if (!ggml_cl_coopk_dp4a_enabled(backend_ctx)) { + return false; + } + // Each lane handles rows output rows; subgroups split K for the same rows. + // Full row groups and 32-value K blocks avoid tail checks in the kernels. + return op->ne[1] >= 2 && op->ne[1] <= 4 + && rows > 0 && (op->src[0]->ne[1] % (64 * rows)) == 0 + && (op->src[0]->ne[0] % 32) == 0; +} + +// COOPK_NSG sizes the local reduction buffer, so a smaller workgroup requires a rebuild. +static cl_program ggml_cl_build_program_coopk(ggml_backend_opencl_context * backend_ctx, + const char * kernel_src, const char * kernel_name, + const std::string & opts_base, int & nsg) { + while (nsg >= 2) { + const std::string opts = opts_base + " -DCOOPK_NSG=" + std::to_string(nsg); + cl_program program = build_program_from_source(backend_ctx, kernel_src, opts); + cl_int err; + cl_kernel kernel = clCreateKernel(program, kernel_name, &err); + CL_CHECK(err); + size_t max_workgroup_size = 0; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, + sizeof(max_workgroup_size), &max_workgroup_size, NULL)); + CL_CHECK(clReleaseKernel(kernel)); + if ((size_t) 64 * nsg <= max_workgroup_size) { + return program; + } + CL_CHECK(clReleaseProgram(program)); + nsg /= 2; + } + return nullptr; +} + +static void ggml_cl_coopk_build_narrow(ggml_backend_opencl_context * backend_ctx, + const std::string & kernel_src, const char * kernel_name, + int rows, int & nsg, cl_kernel & kernel_c4, cl_kernel & kernel_c2) { + const std::string base_opts = backend_ctx->kernel_compile_opts + + " -DCOOPK_ROWS=" + std::to_string(rows); + for (int cols = 4; cols >= 2; cols -= 2) { + int nsg_eff = nsg; + cl_program program = ggml_cl_build_program_coopk( + backend_ctx, kernel_src.c_str(), kernel_name, + base_opts + " -DCOOPK_COLS=" + std::to_string(cols), nsg_eff); + if (program == nullptr) { + return; + } + cl_int err; + cl_kernel kernel = clCreateKernel(program, kernel_name, &err); + if (err != CL_SUCCESS) { kernel = nullptr; } + CL_CHECK(clReleaseProgram(program)); + if (cols == 4) { + kernel_c4 = kernel; + nsg = nsg_eff; + if (kernel == nullptr) { + return; + } + } else { + // Both widths share one stored subgroup count for launch. + if (kernel != nullptr && nsg_eff != nsg) { + CL_CHECK(clReleaseKernel(kernel)); + kernel = nullptr; + } + kernel_c2 = kernel; + } + } +} + +static void load_cl_kernels_gemm_coopk(ggml_backend_opencl_context * backend_ctx) { + if (backend_ctx->gpu_family != GPU_FAMILY::ADRENO || !ggml_cl_coopk_dp4a_enabled(backend_ctx)) { + return; + } + + // Q4_0 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_coopk_q4_0_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_coopk_q4_0_q8_1_dp4a.cl"); +#endif + ggml_cl_coopk_build_narrow(backend_ctx, kernel_src, "kernel_gemm_coopk_q4_0_q8_1_dp4a", + backend_ctx->rows_coopk_dp4a_q4_0, backend_ctx->nsg_coopk_dp4a_q4_0, + backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c4, + backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c2); + GGML_LOG_CONT("."); + } + + // Q4_K + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_coopk_q4_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_coopk_q4_k_q8_1_dp4a.cl"); +#endif + ggml_cl_coopk_build_narrow(backend_ctx, kernel_src, "kernel_gemm_coopk_q4_k_q8_1_dp4a", + backend_ctx->rows_coopk_dp4a_q4_k, backend_ctx->nsg_coopk_dp4a_q4_k, + backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c4, + backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c2); + + const char * env = getenv("GGML_OPENCL_COOPK_Q4_K_BIN"); + if (use_adreno_bin_kernels(backend_ctx) && (!env || !*env || atoi(env) != 0)) { + const std::string base_opts = backend_ctx->kernel_compile_opts + + " -DCOOPK_Q_BIN=1 -DCOOPK_ROWS=" + std::to_string(backend_ctx->rows_coopk_dp4a_q4_k); + for (int cols = 4; cols >= 2; cols -= 2) { + int & nsg = (cols == 4) ? backend_ctx->nsg_coopk_dp4a_q4_k_bin_c4 + : backend_ctx->nsg_coopk_dp4a_q4_k_bin_c2; + int nsg_eff = nsg; + cl_program program = ggml_cl_build_program_coopk( + backend_ctx, kernel_src.c_str(), "kernel_gemm_coopk_q4_k_q8_1_dp4a", + base_opts + " -DCOOPK_COLS=" + std::to_string(cols), nsg_eff); + if (program == nullptr) { + continue; + } + cl_int err; + cl_kernel kernel = clCreateKernel(program, "kernel_gemm_coopk_q4_k_q8_1_dp4a", &err); + if (err != CL_SUCCESS) { kernel = nullptr; } + CL_CHECK(clReleaseProgram(program)); + if (cols == 4) { + backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c4 = kernel; + } else { + backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c2 = kernel; + } + nsg = nsg_eff; + } + } + GGML_LOG_CONT("."); + } + + // Q6_K + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_coopk_q6_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_coopk_q6_k_q8_1_dp4a.cl"); +#endif + ggml_cl_coopk_build_narrow(backend_ctx, kernel_src, "kernel_gemm_coopk_q6_k_q8_1_dp4a", + backend_ctx->rows_coopk_dp4a_q6_k, backend_ctx->nsg_coopk_dp4a_q6_k, + backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c4, + backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c2); + GGML_LOG_CONT("."); + } +} + +#endif + static std::string ggml_opencl_make_compile_opts(const ggml_backend_opencl_context * backend_ctx) { auto opencl_c_std = std::string("CL") + std::to_string(backend_ctx->opencl_c_version.major) + "." + std::to_string(backend_ctx->opencl_c_version.minor); @@ -1547,6 +1953,21 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { GGML_LOG_CONT("."); } + // mul_mat_id_utils + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mat_id_utils.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mat_id_utils.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_moe_zero_dst = clCreateKernel(prog, "kernel_moe_zero_dst", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + // moe_add_id_glu { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1646,6 +2067,8 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { } } CL_CHECK((backend_ctx->kernel_cpy_i32_i32 = clCreateKernel(prog, "kernel_cpy_i32_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_cpy_i32_f32 = clCreateKernel(prog, "kernel_cpy_i32_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_cpy_f32_i32 = clCreateKernel(prog, "kernel_cpy_f32_i32", &err), err)); GGML_LOG_CONT("."); } @@ -1720,6 +2143,30 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { CL_CHECK((backend_ctx->kernel_restore_block_q5_K = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q5_K", &err), err)); CL_CHECK((backend_ctx->kernel_convert_block_q5_K_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q5_K_noshuffle", &err), err)); CL_CHECK((backend_ctx->kernel_restore_block_q5_K_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q5_K_noshuffle", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q2_k_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q2_k_noshuffle", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q2_k_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q2_k_noshuffle", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q3_k_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q3_k_noshuffle", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q3_k_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q3_k_noshuffle", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq2_xxs = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq2_xxs", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq2_xxs = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq2_xxs", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq2_xs = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq2_xs", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq2_xs = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq2_xs", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq2_s = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq2_s", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq2_s = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq2_s", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q2_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q2_0", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q2_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q2_0", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq1_s = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq1_s", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq1_s = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq1_s", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq1_m = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq1_m", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq1_m = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq1_m", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq3_xxs = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq3_xxs", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq3_xxs = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq3_xxs", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_iq3_s = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_iq3_s", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_iq3_s = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_iq3_s", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q3_K = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q3_K", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q3_K = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q3_K", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q2_K = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q2_K", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q2_K = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q2_K", &err), err)); CL_CHECK((backend_ctx->kernel_convert_block_q6_K = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q6_K", &err), err)); CL_CHECK((backend_ctx->kernel_restore_block_q6_K = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q6_K", &err), err)); CL_CHECK((backend_ctx->kernel_convert_block_q6_K_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q6_K_noshuffle", &err), err)); @@ -1821,6 +2268,58 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { GGML_LOG_CONT("."); } + // lightning_indexer + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "lightning_indexer.cl.h" + }; +#else + const std::string kernel_src = read_file("lightning_indexer.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_lightning_indexer = clCreateKernel(prog, "kernel_lightning_indexer", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // top_k + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "top_k.cl.h" + }; +#else + const std::string kernel_src = read_file("top_k.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_top_k_f32 = clCreateKernel(prog, "kernel_top_k_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_top_k_merge_f32 = clCreateKernel(prog, "kernel_top_k_merge_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // top_k_mask + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "top_k_mask.cl.h" + }; +#else + const std::string kernel_src = read_file("top_k_mask.cl"); +#endif + // Scores can contain NaN and -inf, so do not use the default fast-math options. + const std::string opts = "-cl-std=" + opencl_c_std + + (backend_ctx->adreno_use_large_buffer ? " -qcom-enable-large-buffer" : ""); + for (int i = 0; i < 2; ++i) { + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts + " -DMASK_F16=" + std::to_string(i == 0)); + CL_CHECK((backend_ctx->kernel_top_k_mask[i] = clCreateKernel(prog, "kernel_top_k_mask", &err), err)); + CL_CHECK((backend_ctx->kernel_top_k_mask_fill[i] = clCreateKernel(prog, "kernel_top_k_mask_fill", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + } + GGML_LOG_CONT("."); + } + // get_rows { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1834,6 +2333,7 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); CL_CHECK((backend_ctx->kernel_get_rows_f32 = clCreateKernel(backend_ctx->program_get_rows, "kernel_get_rows_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_get_rows_i32 = clCreateKernel(backend_ctx->program_get_rows, "kernel_get_rows_i32", &err), err)); CL_CHECK((backend_ctx->kernel_get_rows_f16 = clCreateKernel(backend_ctx->program_get_rows, "kernel_get_rows_f16", &err), err)); CL_CHECK((backend_ctx->kernel_get_rows_q4_0 = clCreateKernel(backend_ctx->program_get_rows, "kernel_get_rows_q4_0", &err), err)); GGML_LOG_CONT("."); @@ -1888,6 +2388,40 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { GGML_LOG_CONT("."); } + // im2col_3d_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "im2col_3d_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("im2col_3d_f32.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_im2col_3d_f32 = clCreateKernel(prog, "kernel_im2col_3d_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // im2col_3d_f16 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "im2col_3d_f16.cl.h" + }; +#else + const std::string kernel_src = read_file("im2col_3d_f16.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_im2col_3d_f16 = clCreateKernel(prog, "kernel_im2col_3d_f16", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + // mul_mv_q4_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -2011,4192 +2545,5629 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) { GGML_LOG_CONT("."); } - // mul_mv_q4_k_f32 + // mul_mv_q2_k_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q4_k_f32.cl.h" + #include "mul_mv_q2_k_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q4_k_f32.cl"); + const std::string kernel_src = read_file("mul_mv_q2_k_f32_flat.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q4_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q4_K_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_q2_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q2_K_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q4_k_f32_flat + // mul_mm_q2_k_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q4_k_f32_flat.cl.h" + #include "mul_mm_q2_k_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q4_k_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mm_q2_k_f32_l4_lm.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q4_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q4_K_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts + ggml_cl_q2_k_mm_options(backend_ctx)); + CL_CHECK((backend_ctx->kernel_mul_mm_q2_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q2_k_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_0_f32 + // mul_mv_q2_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_0_f32.cl.h" + #include "mul_mv_q2_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_0_f32.cl"); + const std::string kernel_src = read_file("mul_mv_q2_k_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_q5_0_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_0_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q2_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q2_K_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_0_f32_flat + // mul_mv_q3_k_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_0_f32_flat.cl.h" + #include "mul_mv_q3_k_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_0_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_q3_k_f32_flat.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q5_0_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_0_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_q3_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q3_K_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_1_f32 + // mul_mm_q3_k_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_1_f32.cl.h" + #include "mul_mm_q3_k_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_1_f32.cl"); + const std::string kernel_src = read_file("mul_mm_q3_k_f32_l4_lm.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q5_1_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_1_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts + ggml_cl_q3_k_mm_options(backend_ctx)); + CL_CHECK((backend_ctx->kernel_mul_mm_q3_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q3_k_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_1_f32_flat +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq2_s_grid_src { + #include "iq2_s_grid.cl.h" + }; +#else + const std::string iq2_s_grid_src = read_file("iq2_s_grid.cl"); +#endif + + // mul_mv_iq2_s_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_1_f32_flat.cl.h" + #include "mul_mv_iq2_s_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_1_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_s_f32_flat.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q5_1_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_1_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_s_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq2_s_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_k_f32 + // mul_mm_iq2_s_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_k_f32.cl.h" + #include "mul_mm_iq2_s_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_k_f32.cl"); + const std::string kernel_src = read_file("mul_mm_iq2_s_f32_l4_lm.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q5_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_K_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq2_s_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq2_s_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q5_k_f32_flat +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq2_xs_grid_src { + #include "iq2_xs_grid.cl.h" + }; +#else + const std::string iq2_xs_grid_src = read_file("iq2_xs_grid.cl"); +#endif + + // mul_mv_iq2_xs_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q5_k_f32_flat.cl.h" + #include "mul_mv_iq2_xs_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q5_k_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_xs_f32_flat.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q5_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_K_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_xs_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq2_xs_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // mul_mv_q6_k_f32 + // mul_mm_iq2_xs_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q6_k_f32.cl.h" + #include "mul_mm_iq2_xs_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q6_k_f32.cl"); + const std::string kernel_src = read_file("mul_mm_iq2_xs_f32_l4_lm.cl"); #endif - backend_ctx->program_mul_mv_q6_K = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q6_K_f32 = clCreateKernel(backend_ctx->program_mul_mv_q6_K, "kernel_mul_mv_q6_K_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq2_xs_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq2_xs_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q6_k_f32_flat - { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq2_xxs_grid_src { + #include "iq2_xxs_grid.cl.h" + }; +#else + const std::string iq2_xxs_grid_src = read_file("iq2_xxs_grid.cl"); +#endif + + // mul_mv_iq2_xxs_f32_flat + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q6_k_f32_flat.cl.h" + #include "mul_mv_iq2_xxs_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q6_k_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_xxs_f32_flat.cl"); #endif - // The codegen workarounds in this kernel are a measured 13-20% loss on - // compilers that do not need them, so only the affected ones build them; - // everyone else gets the original source. - const std::string q6k_opts = backend_ctx->q6_k_flat_old_compiler - ? compile_opts + " -DADRENO_OLD_COMPILER=1" - : compile_opts; - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), q6k_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q6_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q6_K_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_xxs_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq2_xxs_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q8_0_f32 + // mul_mm_iq2_xxs_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q8_0_f32.cl.h" + #include "mul_mm_iq2_xxs_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q8_0_f32.cl"); + const std::string kernel_src = read_file("mul_mm_iq2_xxs_f32_l4_lm.cl"); #endif - backend_ctx->program_mul_mv_q8_0_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32, "kernel_mul_mv_q8_0_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq2_xxs_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq2_xxs_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q8_0_f32_flat + // mul_mv_iq2_xxs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q8_0_f32_flat.cl.h" + #include "mul_mv_iq2_xxs_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q8_0_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_xxs_f32.cl"); #endif - backend_ctx->program_mul_mv_q8_0_f32_flat = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32_flat, "kernel_mul_mv_q8_0_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_xxs_f32 = clCreateKernel(prog, "kernel_mul_mv_iq2_xxs_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q1_0_f32 + // mul_mv_iq2_xs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q1_0_f32.cl.h" + #include "mul_mv_iq2_xs_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q1_0_f32.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_xs_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q1_0_f32 = clCreateKernel(prog, "kernel_mul_mv_q1_0_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_xs_f32 = clCreateKernel(prog, "kernel_mul_mv_iq2_xs_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_q1_0_f32_flat + // mul_mv_iq2_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_q1_0_f32_flat.cl.h" + #include "mul_mv_iq2_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_q1_0_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq2_s_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_q1_0_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q1_0_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq2_s_f32 = clCreateKernel(prog, "kernel_mul_mv_iq2_s_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_iq4_nl_f32 + // fwht { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_iq4_nl_f32.cl.h" + #include "fwht.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_iq4_nl_f32.cl"); + const std::string kernel_src = read_file("fwht.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + for (int i = 0; i < 2; ++i) { + const std::string opts = compile_opts + (i == 0 ? " -DSRC_TYPE=float" : " -DSRC_TYPE=half"); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + CL_CHECK((backend_ctx->kernel_fwht[i] = clCreateKernel(prog, "kernel_fwht", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + size_t nth = 128; + const size_t max_workgroup = backend_ctx->get_kernel_workgroup_size(backend_ctx->kernel_fwht[i]); + while (nth > max_workgroup) { + nth /= 2; + } + backend_ctx->fwht_workgroup_size[i] = nth; + } + GGML_LOG_CONT("."); + } - CL_CHECK((backend_ctx->kernel_mul_mv_iq4_nl_f32 = clCreateKernel(prog, "kernel_mul_mv_iq4_nl_f32", &err), err)); + // mul_mv_q2_0_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_q2_0_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_q2_0_f32_flat.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_q2_0_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q2_0_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_iq4_nl_f32_flat + // mul_mm_q2_0_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_iq4_nl_f32_flat.cl.h" + #include "mul_mm_q2_0_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_iq4_nl_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mm_q2_0_f32_l4_lm.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_iq4_nl_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq4_nl_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_q2_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q2_0_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_mxfp4_f32 + // mul_mv_q2_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_mxfp4_f32.cl.h" + #include "mul_mv_q2_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_mxfp4_f32.cl"); + const std::string kernel_src = read_file("mul_mv_q2_0_f32.cl"); #endif - backend_ctx->program_mul_mv_mxfp4_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32, "kernel_mul_mv_mxfp4_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_q2_0_f32 = clCreateKernel(prog, "kernel_mul_mv_q2_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_mxfp4_f32_flat +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq1_s_grid_src { + #include "iq1_s_grid.cl.h" + }; +#else + const std::string iq1_s_grid_src = read_file("iq1_s_grid.cl"); +#endif + + // mul_mv_iq1_s_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_mxfp4_f32_flat.cl.h" + #include "mul_mv_iq1_s_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_mxfp4_f32_flat.cl"); + const std::string kernel_src = read_file("mul_mv_iq1_s_f32_flat.cl"); #endif - backend_ctx->program_mul_mv_mxfp4_f32_flat = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32_flat, "kernel_mul_mv_mxfp4_f32_flat", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq1_s_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq1_s_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f16_f16 + // mul_mm_iq1_s_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f16_f16.cl.h" + #include "mul_mm_iq1_s_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f16_f16.cl"); + const std::string kernel_src = read_file("mul_mm_iq1_s_f32_l4_lm.cl"); #endif - backend_ctx->program_mul_mv_f16_f16 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f16 = clCreateKernel(backend_ctx->program_mul_mv_f16_f16, "kernel_mul_mat_f16_f16", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq1_s_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq1_s_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f16_f32_1row + // mul_mv_iq1_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f16_f32_1row.cl.h" + #include "mul_mv_iq1_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f16_f32_1row.cl"); + const std::string kernel_src = read_file("mul_mv_iq1_s_f32.cl"); #endif - backend_ctx->program_mul_mv_f16_f32_1row = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_1row = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_1row, "kernel_mul_mat_f16_f32_1row", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq1_s_f32 = clCreateKernel(prog, "kernel_mul_mv_iq1_s_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f16_f32_mrow (multi-row decode GEMV) + // mul_mv_iq1_m_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f16_f32_mrow.cl.h" + #include "mul_mv_iq1_m_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f16_f32_mrow.cl"); + const std::string kernel_src = read_file("mul_mv_iq1_m_f32_flat.cl"); #endif - backend_ctx->program_mul_mv_f16_f32_mrow = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_r2 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_r2", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_r4 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_r4", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_h8 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_h8", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_h8r2", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq1_m_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq1_m_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f16_f32_l4 + // mul_mm_iq1_m_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f16_f32_l4.cl.h" + #include "mul_mm_iq1_m_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f16_f32_l4.cl"); + const std::string kernel_src = read_file("mul_mm_iq1_m_f32_l4_lm.cl"); #endif - backend_ctx->program_mul_mv_f16_f32_l4 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr", &err), err)); - if (backend_ctx->gpu_family == ADRENO) { - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr_ls = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr_ls", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr_lq = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr_lq", &err), err)); - } - - cl_int err_x8 = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8 = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8", &err_x8); - if (err_x8 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8 = nullptr; } - - cl_int err_x8p = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_pair", &err_x8p); - if (err_x8p != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair = nullptr; } - - cl_int err_x8g = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa4", &err_x8g); - if (err_x8g != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 = nullptr; } - - cl_int err_x8gi = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa4_img", &err_x8gi); - if (err_x8gi != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img = nullptr; } - - cl_int err_x8gi_r4 = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img", &err_x8gi_r4); - if (err_x8gi_r4 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img = nullptr; } - - cl_int err_r2dk256 = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img", &err_r2dk256); - if (err_r2dk256 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img = nullptr; } + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq1_m_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq1_m_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } - cl_int err_y8 = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_y8 = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8", &err_y8); - if (err_y8 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8 = nullptr; } + // mul_mv_iq1_m_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_iq1_m_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_iq1_m_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq1_m_f32 = clCreateKernel(prog, "kernel_mul_mv_iq1_m_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } - cl_int err_y8g = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8_gqa", &err_y8g); - if (err_y8g != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa = nullptr; } +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq3_s_grid_src { + #include "iq3_s_grid.cl.h" + }; +#else + const std::string iq3_s_grid_src = read_file("iq3_s_grid.cl"); +#endif - cl_int err_y8gi = CL_SUCCESS; - backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img = - clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8_gqa_img", &err_y8gi); - if (err_y8gi != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img = nullptr; } + // mul_mv_iq3_s_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_iq3_s_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_iq3_s_f32_flat.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq3_s_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq3_s_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f16_f32 + // mul_mm_iq3_s_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f16_f32.cl.h" + #include "mul_mm_iq3_s_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f16_f32.cl"); + const std::string kernel_src = read_file("mul_mm_iq3_s_f32_l4_lm.cl"); #endif - backend_ctx->program_mul_mv_f16_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32, "kernel_mul_mat_f16_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq3_s_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq3_s_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_f32_f32 + // mul_mv_iq3_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_f32_f32.cl.h" + #include "mul_mv_iq3_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_f32_f32.cl"); + const std::string kernel_src = read_file("mul_mv_iq3_s_f32.cl"); #endif - backend_ctx->program_mul_mv_f32_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f32_f32 = clCreateKernel(backend_ctx->program_mul_mv_f32_f32, "kernel_mul_mat_f32_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq3_s_f32 = clCreateKernel(prog, "kernel_mul_mv_iq3_s_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mat_f16_f32_tiled +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string iq3_xxs_grid_src { + #include "iq3_xxs_grid.cl.h" + }; +#else + const std::string iq3_xxs_grid_src = read_file("iq3_xxs_grid.cl"); +#endif + + // mul_mv_iq3_xxs_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mat_f16_f32.cl.h" + #include "mul_mv_iq3_xxs_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mat_f16_f32.cl"); + const std::string kernel_src = read_file("mul_mv_iq3_xxs_f32_flat.cl"); #endif - backend_ctx->program_mul_mat_f16_f32_tiled = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_tiled = clCreateKernel(backend_ctx->program_mul_mat_f16_f32_tiled, "mul_mat_f16_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq3_xxs_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq3_xxs_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // gemm_xmem_f16_f32_os8 + // mul_mm_iq3_xxs_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_xmem_f16_f32_os8.cl.h" + #include "mul_mm_iq3_xxs_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("gemm_xmem_f16_f32_os8.cl"); + const std::string kernel_src = read_file("mul_mm_iq3_xxs_f32_l4_lm.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_adreno_xmem_pack_src_f32 = - clCreateKernel(prog, "adreno_xmem_pack_src_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_adreno_xmem_prepack_weight_f16 = - clCreateKernel(prog, "adreno_xmem_prepack_weight_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_xmem_f16_f32_os8 = - clCreateKernel(prog, "kernel_gemm_xmem_f16_f32_os8", &err), err)); - CL_CHECK((backend_ctx->kernel_adreno_xmem_store_dst_f32 = - clCreateKernel(prog, "adreno_xmem_store_dst_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_iq3_xxs_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq3_xxs_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // Adreno xmem SDPA - if (backend_ctx->gpu_family == GPU_FAMILY::ADRENO) { + // mul_mv_iq3_xxs_f32 + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sdpa_xmem_f32_f16_os8.cl.h" + #include "mul_mv_iq3_xxs_f32.cl.h" }; #else - const std::string kernel_src = read_file("sdpa_xmem_f32_f16_os8.cl"); + const std::string kernel_src = read_file("mul_mv_iq3_xxs_f32.cl"); #endif - cl_program program = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - auto & xmem_attn = backend_ctx->adreno_xmem_attn; - CL_CHECK((xmem_attn.kernel_q_f32_to_img_scaled = - clCreateKernel(program, "adreno_xmem_attn_q_f32_to_img_scaled", &err), err)); - CL_CHECK((xmem_attn.kernel_kv_f32_to_img_gqa = - clCreateKernel(program, "adreno_xmem_attn_kv_f32_to_img_gqa", &err), err)); - CL_CHECK((xmem_attn.kernel_kv_f16_to_img_gqa = - clCreateKernel(program, "adreno_xmem_attn_kv_f16_to_img_gqa", &err), err)); - CL_CHECK((xmem_attn.kernel_img_to_f32 = - clCreateKernel(program, "adreno_xmem_attn_img_to_f32", &err), err)); - CL_CHECK((xmem_attn.kernel_k_gather = - clCreateKernel(program, "adreno_xmem_attn_k_gather", &err), err)); - CL_CHECK((xmem_attn.kernel_pack_k = - clCreateKernel(program, "adreno_xmem_attn_pack_k", &err), err)); - CL_CHECK((xmem_attn.kernel_qk_gemm = - clCreateKernel(program, "adreno_xmem_attn_qk_gemm", &err), err)); - CL_CHECK((xmem_attn.kernel_softmax_reduce_basic = - clCreateKernel(program, "adreno_xmem_attn_softmax_reduce_basic", &err), err)); - CL_CHECK((xmem_attn.kernel_softmax_apply_basic = - clCreateKernel(program, "adreno_xmem_attn_softmax_apply_basic", &err), err)); - CL_CHECK((xmem_attn.kernel_mask_scores = - clCreateKernel(program, "adreno_xmem_attn_mask_scores", &err), err)); - CL_CHECK((xmem_attn.kernel_pack_v = - clCreateKernel(program, "adreno_xmem_attn_pack_v", &err), err)); - CL_CHECK((xmem_attn.kernel_pv_gemm = - clCreateKernel(program, "adreno_xmem_attn_pv_gemm", &err), err)); - CL_CHECK(clReleaseProgram(program)); - xmem_attn.compiled = true; + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_mul_mv_iq3_xxs_f32 = clCreateKernel(prog, "kernel_mul_mv_iq3_xxs_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS - // mul_mm_f32_f32_l4_lm + // mul_mv_q3_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_f32_f32_l4_lm.cl.h" + #include "mul_mv_q3_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_f32_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q3_k_f32.cl"); #endif - backend_ctx->program_mul_mm_f32_f32_l4_lm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_f32_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_mul_mm_f32_f32_l4_lm", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_f32_f32_mc = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_gemv_f32_f32_mc", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q3_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q3_K_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_f16_f32_l4_lm + // mul_mv_q4_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_f16_f32_l4_lm.cl.h" + #include "mul_mv_q4_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_f16_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q4_k_f32.cl"); #endif - backend_ctx->program_mul_mm_f16_f32_l4_lm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_l4_lm, "kernel_mul_mm_f16_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q4_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q4_K_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q4_0_f32_l4_lm + // mul_mv_q4_k_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q4_0_f32_l4_lm.cl.h" + #include "mul_mv_q4_k_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q4_0_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q4_k_f32_flat.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q4_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_0_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q4_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q4_K_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q4_1_f32_l4_lm + // mul_mv_q5_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q4_1_f32_l4_lm.cl.h" + #include "mul_mv_q5_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q4_1_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_0_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q4_1_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_1_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_0_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q5_0_f32_l4_lm + // mul_mv_q5_0_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q5_0_f32_l4_lm.cl.h" + #include "mul_mv_q5_0_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q5_0_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_0_f32_flat.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q5_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_0_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_0_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_0_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q5_1_f32_l4_lm + // mul_mv_q5_1_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q5_1_f32_l4_lm.cl.h" + #include "mul_mv_q5_1_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q5_1_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_1_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q5_1_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_1_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_1_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_1_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q8_0_f32_l4_lm + // mul_mv_q5_1_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q8_0_f32_l4_lm.cl.h" + #include "mul_mv_q5_1_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q8_0_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_1_f32_flat.cl"); #endif - backend_ctx->program_mul_mm_q8_0_f32_l4_lm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q8_0_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_q8_0_f32_l4_lm, "kernel_mul_mm_q8_0_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_1_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_1_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q1_0_f32_l4_lm + // mul_mv_q5_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q1_0_f32_l4_lm.cl.h" + #include "mul_mv_q5_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q1_0_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_k_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q1_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q1_0_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_K_f32 = clCreateKernel(prog, "kernel_mul_mv_q5_K_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_iq4_nl_f32_l4_lm + // mul_mv_q5_k_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_iq4_nl_f32_l4_lm.cl.h" + #include "mul_mv_q5_k_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_iq4_nl_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q5_k_f32_flat.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_iq4_nl_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq4_nl_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q5_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q5_K_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); } - // mul_mm_q4_k_f32_l4_lm + // mul_mv_q6_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q4_k_f32_l4_lm.cl.h" + #include "mul_mv_q6_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q4_k_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q6_k_f32.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mv_q6_K = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q4_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_k_f32_l4_lm", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mv_q6_K_f32 = clCreateKernel(backend_ctx->program_mul_mv_q6_K, "kernel_mul_mv_q6_K_f32", &err), err)); GGML_LOG_CONT("."); } - // mul_mm_q6_k_f32_l4_lm + // mul_mv_q6_k_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q6_k_f32_l4_lm.cl.h" + #include "mul_mv_q6_k_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q6_k_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q6_k_f32_flat.cl"); #endif + // The codegen workarounds in this kernel are a measured 13-20% loss on + // compilers that do not need them, so only the affected ones build them; + // everyone else gets the original source. + const std::string q6k_opts = backend_ctx->q6_k_flat_old_compiler + ? compile_opts + " -DADRENO_OLD_COMPILER=1" + : compile_opts; cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + build_program_from_source(backend_ctx, kernel_src.c_str(), q6k_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q6_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q6_k_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q6_K_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q6_K_f32_flat", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mm_q5_k_f32_l4_lm + // mul_mv_q8_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_q5_k_f32_l4_lm.cl.h" + #include "mul_mv_q8_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_q5_k_f32_l4_lm.cl"); + const std::string kernel_src = read_file("mul_mv_q8_0_f32.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mv_q8_0_f32 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_q5_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_k_f32_l4_lm", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32, "kernel_mul_mv_q8_0_f32", &err), err)); GGML_LOG_CONT("."); } - // mul_mm_f16_f32_kq_kqv + // mul_mv_q8_0_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mm_f16_f32_kq_kqv.cl.h" + #include "mul_mv_q8_0_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("mul_mm_f16_f32_kq_kqv.cl"); + const std::string kernel_src = read_file("mul_mv_q8_0_f32_flat.cl"); #endif - backend_ctx->program_mul_mm_f16_f32_kqv = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts+" -DKQV "); - backend_ctx->program_mul_mm_f16_f32_kq = + backend_ctx->program_mul_mv_q8_0_f32_flat = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_kqv = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_kqv, "mul_mm_f16_f32_kqv", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_kq = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_kq, "mul_mm_f16_f32_kq", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32_flat, "kernel_mul_mv_q8_0_f32_flat", &err), err)); GGML_LOG_CONT("."); } - // mul + // mul_mv_q1_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul.cl.h" + #include "mul_mv_q1_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul.cl"); + const std::string kernel_src = read_file("mul_mv_q1_0_f32.cl"); #endif - backend_ctx->program_mul = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_row_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q1_0_f32 = clCreateKernel(prog, "kernel_mul_mv_q1_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // norm + // mul_mv_q1_0_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "norm.cl.h" + #include "mul_mv_q1_0_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("norm.cl"); + const std::string kernel_src = read_file("mul_mv_q1_0_f32_flat.cl"); #endif - backend_ctx->program_norm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_norm = clCreateKernel(backend_ctx->program_norm, "kernel_norm", &err), err)); - CL_CHECK((backend_ctx->kernel_norm_mul_add = clCreateKernel(backend_ctx->program_norm, "kernel_norm_mul_add", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_q1_0_f32_flat = clCreateKernel(prog, "kernel_mul_mv_q1_0_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // relu + // mul_mv_iq4_nl_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "relu.cl.h" + #include "mul_mv_iq4_nl_f32.cl.h" }; #else - const std::string kernel_src = read_file("relu.cl"); + const std::string kernel_src = read_file("mul_mv_iq4_nl_f32.cl"); #endif - backend_ctx->program_relu = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_relu = clCreateKernel(backend_ctx->program_relu, "kernel_relu", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_iq4_nl_f32 = clCreateKernel(prog, "kernel_mul_mv_iq4_nl_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // rms_norm + // mul_mv_iq4_nl_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "rms_norm.cl.h" + #include "mul_mv_iq4_nl_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("rms_norm.cl"); + const std::string kernel_src = read_file("mul_mv_iq4_nl_f32_flat.cl"); #endif - backend_ctx->program_rms_norm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); - CL_CHECK((backend_ctx->kernel_rms_norm_mul = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul", &err), err)); - CL_CHECK((backend_ctx->kernel_rms_norm_mul_add = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul_add", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_iq4_nl_f32_flat = clCreateKernel(prog, "kernel_mul_mv_iq4_nl_f32_flat", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // l2_norm + // mul_mv_mxfp4_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "l2_norm.cl.h" + #include "mul_mv_mxfp4_f32.cl.h" }; #else - const std::string kernel_src = read_file("l2_norm.cl"); + const std::string kernel_src = read_file("mul_mv_mxfp4_f32.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mv_mxfp4_f32 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_l2_norm_f32 = clCreateKernel(prog, "kernel_l2_norm_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32, "kernel_mul_mv_mxfp4_f32", &err), err)); GGML_LOG_CONT("."); } - // rope + // mul_mv_mxfp4_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "rope.cl.h" + #include "mul_mv_mxfp4_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("rope.cl"); + const std::string kernel_src = read_file("mul_mv_mxfp4_f32_flat.cl"); #endif - backend_ctx->program_rope = + backend_ctx->program_mul_mv_mxfp4_f32_flat = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_rope_norm_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_norm_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_norm_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_norm_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_neox_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_neox_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_neox_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_neox_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_multi_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_multi_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_multi_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_multi_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_vision_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_vision_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_rope_vision_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_vision_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32_flat, "kernel_mul_mv_mxfp4_f32_flat", &err), err)); GGML_LOG_CONT("."); } - // scale + // mul_mv_f16_f16 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "scale.cl.h" + #include "mul_mv_f16_f16.cl.h" }; #else - const std::string kernel_src = read_file("scale.cl"); + const std::string kernel_src = read_file("mul_mv_f16_f16.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mv_f16_f16 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_scale_f32 = clCreateKernel(prog, "kernel_scale_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_scale_f32_4 = clCreateKernel(prog, "kernel_scale_f32_4", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f16 = clCreateKernel(backend_ctx->program_mul_mv_f16_f16, "kernel_mul_mat_f16_f16", &err), err)); GGML_LOG_CONT("."); } - // silu + // mul_mv_f16_f32_1row { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "silu.cl.h" + #include "mul_mv_f16_f32_1row.cl.h" }; #else - const std::string kernel_src = read_file("silu.cl"); + const std::string kernel_src = read_file("mul_mv_f16_f32_1row.cl"); #endif - backend_ctx->program_silu = + backend_ctx->program_mul_mv_f16_f32_1row = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_silu = clCreateKernel(backend_ctx->program_silu, "kernel_silu", &err), err)); - CL_CHECK((backend_ctx->kernel_silu_4 = clCreateKernel(backend_ctx->program_silu, "kernel_silu_4", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_1row = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_1row, "kernel_mul_mat_f16_f32_1row", &err), err)); GGML_LOG_CONT("."); } - // softmax_f32 + // mul_mv_f16_f32_mrow (multi-row decode GEMV) { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "softmax_f32.cl.h" + #include "mul_mv_f16_f32_mrow.cl.h" }; #else - const std::string kernel_src = read_file("softmax_f32.cl"); + const std::string kernel_src = read_file("mul_mv_f16_f32_mrow.cl"); #endif - backend_ctx->program_softmax_f32 = + backend_ctx->program_mul_mv_f16_f32_mrow = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_soft_max = clCreateKernel(backend_ctx->program_softmax_f32, "kernel_soft_max", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_r2 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_r2", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_r4 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_r4", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_h8 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_h8", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_mrow, "kernel_mul_mat_f16_f32_mrow_h8r2", &err), err)); GGML_LOG_CONT("."); } - // softmax_f16 + // mul_mv_f16_f32_l4 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "softmax_f16.cl.h" + #include "mul_mv_f16_f32_l4.cl.h" }; #else - const std::string kernel_src = read_file("softmax_f16.cl"); + const std::string kernel_src = read_file("mul_mv_f16_f32_l4.cl"); #endif - backend_ctx->program_softmax_f16 = + backend_ctx->program_mul_mv_f16_f32_l4 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_soft_max_f16 = clCreateKernel(backend_ctx->program_softmax_f16, "kernel_soft_max_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr", &err), err)); + if (backend_ctx->gpu_family == ADRENO) { + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr_ls = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr_ls", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_l4_dr_lq = clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_dr_lq", &err), err)); + } + + cl_int err_x8 = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8 = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8", &err_x8); + if (err_x8 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8 = nullptr; } + + cl_int err_x8p = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_pair", &err_x8p); + if (err_x8p != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair = nullptr; } + + cl_int err_x8g = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa4", &err_x8g); + if (err_x8g != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 = nullptr; } + + cl_int err_x8gi = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa4_img", &err_x8gi); + if (err_x8gi != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img = nullptr; } + + cl_int err_x8gi_r4 = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img", &err_x8gi_r4); + if (err_x8gi_r4 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img = nullptr; } + + cl_int err_r2dk256 = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img", &err_r2dk256); + if (err_r2dk256 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img = nullptr; } + + cl_int err_y8 = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_y8 = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8", &err_y8); + if (err_y8 != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8 = nullptr; } + + cl_int err_y8g = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8_gqa", &err_y8g); + if (err_y8g != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa = nullptr; } + + cl_int err_y8gi = CL_SUCCESS; + backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img = + clCreateKernel(backend_ctx->program_mul_mv_f16_f32_l4, "kernel_mul_mat_f16_f32_l4_y8_gqa_img", &err_y8gi); + if (err_y8gi != CL_SUCCESS) { backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img = nullptr; } GGML_LOG_CONT("."); } - // softmax_4_f32 + // mul_mv_f16_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "softmax_4_f32.cl.h" + #include "mul_mv_f16_f32.cl.h" }; #else - const std::string kernel_src = read_file("softmax_4_f32.cl"); + const std::string kernel_src = read_file("mul_mv_f16_f32.cl"); #endif - backend_ctx->program_softmax_4_f32 = + backend_ctx->program_mul_mv_f16_f32 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_soft_max_4 = clCreateKernel(backend_ctx->program_softmax_4_f32, "kernel_soft_max_4", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32 = clCreateKernel(backend_ctx->program_mul_mv_f16_f32, "kernel_mul_mat_f16_f32", &err), err)); GGML_LOG_CONT("."); } - // softmax_4_f16 + // mul_mv_f32_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "softmax_4_f16.cl.h" + #include "mul_mv_f32_f32.cl.h" }; #else - const std::string kernel_src = read_file("softmax_4_f16.cl"); + const std::string kernel_src = read_file("mul_mv_f32_f32.cl"); #endif - backend_ctx->program_softmax_4_f16 = + backend_ctx->program_mul_mv_f32_f32 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_soft_max_4_f16 = clCreateKernel(backend_ctx->program_softmax_4_f16, "kernel_soft_max_4_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f32_f32 = clCreateKernel(backend_ctx->program_mul_mv_f32_f32, "kernel_mul_mat_f32_f32", &err), err)); GGML_LOG_CONT("."); } - // div + // mul_mat_f16_f32_tiled { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "div.cl.h" + #include "mul_mat_f16_f32.cl.h" }; #else - const std::string kernel_src = read_file("div.cl"); + const std::string kernel_src = read_file("mul_mat_f16_f32.cl"); #endif - std::string compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable -cl-finite-math-only "; - - backend_ctx->program_div = + backend_ctx->program_mul_mat_f16_f32_tiled = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); - CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); - CL_CHECK((backend_ctx->kernel_div_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_div_row_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_row_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mat_f16_f32_tiled = clCreateKernel(backend_ctx->program_mul_mat_f16_f32_tiled, "mul_mat_f16_f32", &err), err)); GGML_LOG_CONT("."); } - // sqr +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // gemm_xmem_f16_f32_os8 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sqr.cl.h" + #include "gemm_xmem_f16_f32_os8.cl.h" }; #else - const std::string kernel_src = read_file("sqr.cl"); + const std::string kernel_src = read_file("gemm_xmem_f16_f32_os8.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sqr_cont_f32 = clCreateKernel(prog, "kernel_sqr_cont_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_sqr_cont_f32_4 = clCreateKernel(prog, "kernel_sqr_cont_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_sqr_cont_f16 = clCreateKernel(prog, "kernel_sqr_cont_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_sqr_cont_f16_4 = clCreateKernel(prog, "kernel_sqr_cont_f16_4", &err), err)); - + CL_CHECK((backend_ctx->kernel_adreno_xmem_pack_src_f32 = + clCreateKernel(prog, "adreno_xmem_pack_src_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_adreno_xmem_prepack_weight_f16 = + clCreateKernel(prog, "adreno_xmem_prepack_weight_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_xmem_f16_f32_os8 = + clCreateKernel(prog, "kernel_gemm_xmem_f16_f32_os8", &err), err)); + CL_CHECK((backend_ctx->kernel_adreno_xmem_store_dst_f32 = + clCreateKernel(prog, "adreno_xmem_store_dst_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - // sqrt - { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // Adreno xmem SDPA + if (backend_ctx->gpu_family == GPU_FAMILY::ADRENO) { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sqrt.cl.h" + #include "sdpa_xmem_f32_f16_os8.cl.h" }; #else - const std::string kernel_src = read_file("sqrt.cl"); + const std::string kernel_src = read_file("sdpa_xmem_f32_f16_os8.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - - CL_CHECK((backend_ctx->kernel_sqrt_cont_f32 = clCreateKernel(prog, "kernel_sqrt_cont_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_sqrt_cont_f32_4 = clCreateKernel(prog, "kernel_sqrt_cont_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_sqrt_cont_f16 = clCreateKernel(prog, "kernel_sqrt_cont_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_sqrt_cont_f16_4 = clCreateKernel(prog, "kernel_sqrt_cont_f16_4", &err), err)); + cl_program program = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK(clReleaseProgram(prog)); + auto & xmem_attn = backend_ctx->adreno_xmem_attn; + CL_CHECK((xmem_attn.kernel_q_f32_to_img_scaled = + clCreateKernel(program, "adreno_xmem_attn_q_f32_to_img_scaled", &err), err)); + CL_CHECK((xmem_attn.kernel_kv_f32_to_img_gqa = + clCreateKernel(program, "adreno_xmem_attn_kv_f32_to_img_gqa", &err), err)); + CL_CHECK((xmem_attn.kernel_kv_f16_to_img_gqa = + clCreateKernel(program, "adreno_xmem_attn_kv_f16_to_img_gqa", &err), err)); + CL_CHECK((xmem_attn.kernel_img_to_f32 = + clCreateKernel(program, "adreno_xmem_attn_img_to_f32", &err), err)); + CL_CHECK((xmem_attn.kernel_k_gather = + clCreateKernel(program, "adreno_xmem_attn_k_gather", &err), err)); + CL_CHECK((xmem_attn.kernel_pack_k = + clCreateKernel(program, "adreno_xmem_attn_pack_k", &err), err)); + CL_CHECK((xmem_attn.kernel_qk_gemm = + clCreateKernel(program, "adreno_xmem_attn_qk_gemm", &err), err)); + CL_CHECK((xmem_attn.kernel_softmax_reduce_basic = + clCreateKernel(program, "adreno_xmem_attn_softmax_reduce_basic", &err), err)); + CL_CHECK((xmem_attn.kernel_softmax_apply_basic = + clCreateKernel(program, "adreno_xmem_attn_softmax_apply_basic", &err), err)); + CL_CHECK((xmem_attn.kernel_mask_scores = + clCreateKernel(program, "adreno_xmem_attn_mask_scores", &err), err)); + CL_CHECK((xmem_attn.kernel_pack_v = + clCreateKernel(program, "adreno_xmem_attn_pack_v", &err), err)); + CL_CHECK((xmem_attn.kernel_pv_gemm = + clCreateKernel(program, "adreno_xmem_attn_pv_gemm", &err), err)); + CL_CHECK(clReleaseProgram(program)); + xmem_attn.compiled = true; GGML_LOG_CONT("."); } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - // mean + // mul_mm_f32_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mean.cl.h" + #include "mul_mm_f32_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("mean.cl"); + const std::string kernel_src = read_file("mul_mm_f32_f32_l4_lm.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mm_f32_f32_l4_lm = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mean_f32 = clCreateKernel(prog, "kernel_mean_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_mean_f32_4 = clCreateKernel(prog, "kernel_mean_f32_4", &err), err)); - - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mm_f32_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_mul_mm_f32_f32_l4_lm", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_f32_f32_mc = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_gemv_f32_f32_mc", &err), err)); GGML_LOG_CONT("."); } - // sub + // mul_mm_f16_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sub.cl.h" + #include "mul_mm_f16_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("sub.cl"); + const std::string kernel_src = read_file("mul_mm_f16_f32_l4_lm.cl"); #endif - backend_ctx->program_sub = + backend_ctx->program_mul_mm_f16_f32_l4_lm = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); - CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); - CL_CHECK((backend_ctx->kernel_sub_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_sub_row_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_l4_lm, "kernel_mul_mm_f16_f32_l4_lm", &err), err)); + + const std::string narrow_opts = compile_opts + " -DBN=8 -DTN=1 -DKERNEL_NAME_LM=kernel_mul_mm_f16_f32_l4_lm_n8"; + backend_ctx->program_mul_mm_f16_f32_l4_lm_n8 = + build_program_from_source(backend_ctx, kernel_src.c_str(), narrow_opts); + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_l4_lm_n8 = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_l4_lm_n8, "kernel_mul_mm_f16_f32_l4_lm_n8", &err), err)); GGML_LOG_CONT("."); } - // sum_rows + // mul_mm_q4_0_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sum_rows.cl.h" + #include "mul_mm_q4_0_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("sum_rows.cl"); + const std::string kernel_src = read_file("mul_mm_q4_0_f32_l4_lm.cl"); #endif - backend_ctx->program_sum_rows_f32 = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sum_rows_f32 = clCreateKernel(backend_ctx->program_sum_rows_f32, "kernel_sum_rows_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_sum_rows_f32_4 = clCreateKernel(backend_ctx->program_sum_rows_f32, "kernel_sum_rows_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_q4_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_0_f32_l4_lm", &err), err)); GGML_LOG_CONT("."); } - // cumsum + // mul_mm_q4_1_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "cumsum.cl.h" + #include "mul_mm_q4_1_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("cumsum.cl"); + const std::string kernel_src = read_file("mul_mm_q4_1_f32_l4_lm.cl"); #endif - cl_program prog; - prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_cumsum_blk = clCreateKernel(prog, "kernel_cumsum_blk", &err), err)); - CL_CHECK((backend_ctx->kernel_cumsum_add = clCreateKernel(prog, "kernel_cumsum_add", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_q4_1_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_1_f32_l4_lm", &err), err)); GGML_LOG_CONT("."); - CL_CHECK(clReleaseProgram(prog)); } - // sigmoid + // mul_mm_q5_0_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "sigmoid.cl.h" + #include "mul_mm_q5_0_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("sigmoid.cl"); + const std::string kernel_src = read_file("mul_mm_q5_0_f32_l4_lm.cl"); #endif - backend_ctx->program_sigmoid = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sigmoid_f32 = clCreateKernel(backend_ctx->program_sigmoid, "kernel_sigmoid_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_sigmoid_f16 = clCreateKernel(backend_ctx->program_sigmoid, "kernel_sigmoid_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_q5_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_0_f32_l4_lm", &err), err)); GGML_LOG_CONT("."); } - // group_norm + // mul_mm_q5_1_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "group_norm.cl.h" + #include "mul_mm_q5_1_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("group_norm.cl"); + const std::string kernel_src = read_file("mul_mm_q5_1_f32_l4_lm.cl"); #endif - backend_ctx->program_group_norm = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_group_norm = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm", &err), err)); - CL_CHECK((backend_ctx->kernel_group_norm_mul_add = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm_mul_add", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_q5_1_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_1_f32_l4_lm", &err), err)); GGML_LOG_CONT("."); } - // repeat + // mul_mm_q8_0_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "repeat.cl.h" + #include "mul_mm_q8_0_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("repeat.cl"); + const std::string kernel_src = read_file("mul_mm_q8_0_f32_l4_lm.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mm_q8_0_f32_l4_lm = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_repeat_f32 = clCreateKernel(prog, "kernel_repeat_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_mul_mm_q8_0_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_q8_0_f32_l4_lm, "kernel_mul_mm_q8_0_f32_l4_lm", &err), err)); GGML_LOG_CONT("."); } - // pad + // mul_mm_q1_0_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "pad.cl.h" + #include "mul_mm_q1_0_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("pad.cl"); + const std::string kernel_src = read_file("mul_mm_q1_0_f32_l4_lm.cl"); #endif - if (!kernel_src.empty()) { - backend_ctx->program_pad = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_pad = clCreateKernel(backend_ctx->program_pad, "kernel_pad", &err), err)); - GGML_LOG_CONT("."); - } else { - GGML_LOG_WARN("ggml_opencl: pad kernel source not found or empty. Pad operations will not be available.\n"); - backend_ctx->program_pad = nullptr; - backend_ctx->kernel_pad = nullptr; - } + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mm_q1_0_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q1_0_f32_l4_lm", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // tanh + // mul_mm_iq4_nl_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "tanh.cl.h" + #include "mul_mm_iq4_nl_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("tanh.cl"); + const std::string kernel_src = read_file("mul_mm_iq4_nl_f32_l4_lm.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_tanh_f32 = clCreateKernel(prog, "kernel_tanh_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_tanh_f32_4 = clCreateKernel(prog, "kernel_tanh_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_tanh_f32_nc = clCreateKernel(prog, "kernel_tanh_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_tanh_f16 = clCreateKernel(prog, "kernel_tanh_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_tanh_f16_4 = clCreateKernel(prog, "kernel_tanh_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_tanh_f16_nc = clCreateKernel(prog, "kernel_tanh_f16_nc", &err), err)); + + CL_CHECK((backend_ctx->kernel_mul_mm_iq4_nl_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_iq4_nl_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // neg + // mul_mm_q4_k_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "neg.cl.h" + #include "mul_mm_q4_k_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("neg.cl"); + const std::string kernel_src = read_file("mul_mm_q4_k_f32_l4_lm.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_neg_f32 = clCreateKernel(prog, "kernel_neg_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_neg_f32_4 = clCreateKernel(prog, "kernel_neg_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_neg_f32_nc = clCreateKernel(prog, "kernel_neg_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_neg_f16 = clCreateKernel(prog, "kernel_neg_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_neg_f16_4 = clCreateKernel(prog, "kernel_neg_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_neg_f16_nc = clCreateKernel(prog, "kernel_neg_f16_nc", &err), err)); + + CL_CHECK((backend_ctx->kernel_mul_mm_q4_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q4_k_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // exp + // mul_mm_q6_k_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "exp.cl.h" + #include "mul_mm_q6_k_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("exp.cl"); + const std::string kernel_src = read_file("mul_mm_q6_k_f32_l4_lm.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_exp_f32 = clCreateKernel(prog, "kernel_exp_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_exp_f32_4 = clCreateKernel(prog, "kernel_exp_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_exp_f32_nc = clCreateKernel(prog, "kernel_exp_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_exp_f16 = clCreateKernel(prog, "kernel_exp_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_exp_f16_4 = clCreateKernel(prog, "kernel_exp_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_exp_f16_nc = clCreateKernel(prog, "kernel_exp_f16_nc", &err), err)); + + CL_CHECK((backend_ctx->kernel_mul_mm_q6_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q6_k_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // expm1 + // mul_mm_q5_k_f32_l4_lm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "expm1.cl.h" + #include "mul_mm_q5_k_f32_l4_lm.cl.h" }; #else - const std::string kernel_src = read_file("expm1.cl"); + const std::string kernel_src = read_file("mul_mm_q5_k_f32_l4_lm.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_expm1_f32 = clCreateKernel(prog, "kernel_expm1_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_expm1_f32_4 = clCreateKernel(prog, "kernel_expm1_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_expm1_f32_nc = clCreateKernel(prog, "kernel_expm1_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_expm1_f16 = clCreateKernel(prog, "kernel_expm1_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_expm1_f16_4 = clCreateKernel(prog, "kernel_expm1_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_expm1_f16_nc = clCreateKernel(prog, "kernel_expm1_f16_nc", &err), err)); + + CL_CHECK((backend_ctx->kernel_mul_mm_q5_k_f32_l4_lm = clCreateKernel(prog, "kernel_mul_mm_q5_k_f32_l4_lm", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // abs + // mul_mm_f16_f32_kq_kqv { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "abs.cl.h" + #include "mul_mm_f16_f32_kq_kqv.cl.h" }; #else - const std::string kernel_src = read_file("abs.cl"); + const std::string kernel_src = read_file("mul_mm_f16_f32_kq_kqv.cl"); #endif - cl_program prog = + backend_ctx->program_mul_mm_f16_f32_kqv = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts+" -DKQV "); + backend_ctx->program_mul_mm_f16_f32_kq = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_abs_f32 = clCreateKernel(prog, "kernel_abs_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_abs_f32_4 = clCreateKernel(prog, "kernel_abs_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_abs_f32_nc = clCreateKernel(prog, "kernel_abs_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_abs_f16 = clCreateKernel(prog, "kernel_abs_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_abs_f16_4 = clCreateKernel(prog, "kernel_abs_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_abs_f16_nc = clCreateKernel(prog, "kernel_abs_f16_nc", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_kqv = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_kqv, "mul_mm_f16_f32_kqv", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_kq = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_kq, "mul_mm_f16_f32_kq", &err), err)); GGML_LOG_CONT("."); } - // unary_ext (sgn, step, elu, hardswish, hardsigmoid, floor, ceil, round, trunc) + // mul { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "unary_ext.cl.h" + #include "mul.cl.h" }; #else - const std::string kernel_src = read_file("unary_ext.cl"); + const std::string kernel_src = read_file("mul.cl"); #endif - cl_program prog = + backend_ctx->program_mul = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); -#define CL_UNARY_EXT_K(op) \ - CL_CHECK((backend_ctx->kernel_##op##_f32 = clCreateKernel(prog, "kernel_" #op "_f32", &err), err)); \ - CL_CHECK((backend_ctx->kernel_##op##_f32_4 = clCreateKernel(prog, "kernel_" #op "_f32_4", &err), err)); \ - CL_CHECK((backend_ctx->kernel_##op##_f32_nc = clCreateKernel(prog, "kernel_" #op "_f32_nc", &err), err)); \ - CL_CHECK((backend_ctx->kernel_##op##_f16 = clCreateKernel(prog, "kernel_" #op "_f16", &err), err)); \ - CL_CHECK((backend_ctx->kernel_##op##_f16_4 = clCreateKernel(prog, "kernel_" #op "_f16_4", &err), err)); \ - CL_CHECK((backend_ctx->kernel_##op##_f16_nc = clCreateKernel(prog, "kernel_" #op "_f16_nc", &err), err)); - CL_UNARY_EXT_K(sgn) - CL_UNARY_EXT_K(step) - CL_UNARY_EXT_K(elu) - CL_UNARY_EXT_K(hardswish) - CL_UNARY_EXT_K(hardsigmoid) - CL_UNARY_EXT_K(floor) - CL_UNARY_EXT_K(ceil) - CL_UNARY_EXT_K(round) - CL_UNARY_EXT_K(trunc) -#undef CL_UNARY_EXT_K - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row_f16", &err), err)); GGML_LOG_CONT("."); } - // softplus + // norm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "softplus.cl.h" + #include "norm.cl.h" }; #else - const std::string kernel_src = read_file("softplus.cl"); + const std::string kernel_src = read_file("norm.cl"); #endif - cl_program prog = + backend_ctx->program_norm = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_softplus_f32 = clCreateKernel(prog, "kernel_softplus_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_softplus_f32_4 = clCreateKernel(prog, "kernel_softplus_f32_4", &err), err)); - CL_CHECK((backend_ctx->kernel_softplus_f32_nc = clCreateKernel(prog, "kernel_softplus_f32_nc", &err), err)); - CL_CHECK((backend_ctx->kernel_softplus_f16 = clCreateKernel(prog, "kernel_softplus_f16", &err), err)); - CL_CHECK((backend_ctx->kernel_softplus_f16_4 = clCreateKernel(prog, "kernel_softplus_f16_4", &err), err)); - CL_CHECK((backend_ctx->kernel_softplus_f16_nc = clCreateKernel(prog, "kernel_softplus_f16_nc", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_norm = clCreateKernel(backend_ctx->program_norm, "kernel_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_norm_mul_add = clCreateKernel(backend_ctx->program_norm, "kernel_norm_mul_add", &err), err)); GGML_LOG_CONT("."); } - // upscale + // relu { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "upscale.cl.h" + #include "relu.cl.h" }; #else - const std::string kernel_src = read_file("upscale.cl"); + const std::string kernel_src = read_file("relu.cl"); #endif - if (!kernel_src.empty()) { - backend_ctx->program_upscale = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_upscale = clCreateKernel(backend_ctx->program_upscale, "kernel_upscale", &err), err)); - if (backend_ctx->program_upscale) { - cl_int err_bilinear; - backend_ctx->kernel_upscale_bilinear = clCreateKernel(backend_ctx->program_upscale, "kernel_upscale_bilinear", &err_bilinear); - if (err_bilinear != CL_SUCCESS) { - GGML_LOG_WARN("ggml_opencl: kernel_upscale_bilinear not found in upscale.cl. Bilinear upscale will not be available. Error: %d\n", err_bilinear); - backend_ctx->kernel_upscale_bilinear = nullptr; - } - } else { - backend_ctx->kernel_upscale_bilinear = nullptr; - } - GGML_LOG_CONT("."); - } else { - GGML_LOG_WARN("ggml_opencl: upscale kernel source not found or empty. Upscale operations will not be available.\n"); - backend_ctx->program_upscale = nullptr; - backend_ctx->kernel_upscale = nullptr; - backend_ctx->kernel_upscale_bilinear = nullptr; - } + backend_ctx->program_relu = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_relu = clCreateKernel(backend_ctx->program_relu, "kernel_relu", &err), err)); + GGML_LOG_CONT("."); } - // concat + // rms_norm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "concat.cl.h" + #include "rms_norm.cl.h" }; #else - const std::string kernel_src = read_file("concat.cl"); + const std::string kernel_src = read_file("rms_norm.cl"); #endif - cl_program prog = + backend_ctx->program_rms_norm = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_concat_b1 = clCreateKernel(prog, "kernel_concat_b1", &err), err)); - CL_CHECK((backend_ctx->kernel_concat_b2 = clCreateKernel(prog, "kernel_concat_b2", &err), err)); - CL_CHECK((backend_ctx->kernel_concat_b4 = clCreateKernel(prog, "kernel_concat_b4", &err), err)); - CL_CHECK((backend_ctx->kernel_concat_b8 = clCreateKernel(prog, "kernel_concat_b8", &err), err)); - CL_CHECK((backend_ctx->kernel_concat_b4_pack = clCreateKernel(prog, "kernel_concat_b4_pack", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm_mul = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm_mul_add = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul_add", &err), err)); GGML_LOG_CONT("."); } - // timestep_embedding + // l2_norm { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "tsembd.cl.h" + #include "l2_norm.cl.h" }; #else - - const std::string kernel_src = read_file("tsembd.cl"); + const std::string kernel_src = read_file("l2_norm.cl"); #endif - if (!kernel_src.empty()) { - backend_ctx->program_tsembd = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_timestep_embedding = clCreateKernel(backend_ctx->program_tsembd, "kernel_timestep_embedding", &err), err)); - GGML_LOG_CONT("."); - } else { - GGML_LOG_WARN("ggml_opencl: timestep_embedding kernel source not found or empty. This op will not be available.\n"); - backend_ctx->program_tsembd = nullptr; - backend_ctx->kernel_timestep_embedding = nullptr; - } + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_l2_norm_f32 = clCreateKernel(prog, "kernel_l2_norm_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // set_rows + // rope { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "set_rows.cl.h" + #include "rope.cl.h" }; #else - const std::string kernel_src = read_file("set_rows.cl"); + const std::string kernel_src = read_file("rope.cl"); #endif - backend_ctx->program_set_rows = + backend_ctx->program_rope = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_set_rows_f32_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_f32_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_f16_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_f16_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q8_0_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q8_0_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_i32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q8_0_soa_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_soa_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q8_0_soa_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_soa_i32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q4_0_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q4_0_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_i32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q4_0_soa_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_soa_i64", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_q4_0_soa_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_soa_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_norm_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_norm_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_norm_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_norm_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_neox_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_neox_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_neox_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_neox_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_multi_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_multi_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_multi_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_multi_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_vision_f32 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_vision_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_rope_vision_f16 = clCreateKernel(backend_ctx->program_rope, "kernel_rope_vision_f16", &err), err)); GGML_LOG_CONT("."); } - // conv2d - { - #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "conv2d.cl.h" - }; - const std::string kernel_src_f16_f32 { - #include "conv2d_f16_f32.cl.h" - }; - #else - const std::string kernel_src = read_file("conv2d.cl"); - const std::string kernel_src_f16_f32 = read_file("conv2d_f16_f32.cl"); - #endif - if (!kernel_src.empty()) { - backend_ctx->program_conv_2d_f16 = - build_program_from_source(backend_ctx, kernel_src.c_str(), (std::string(compile_opts) + " -DUSE_FP16=1").c_str()); - CL_CHECK((backend_ctx->kernel_conv_2d_f16 = clCreateKernel(backend_ctx->program_conv_2d_f16, "kernel_conv_2d", &err), err)); - GGML_LOG_CONT("."); - backend_ctx->program_conv_2d_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_conv_2d_f32 = clCreateKernel(backend_ctx->program_conv_2d_f32, "kernel_conv_2d", &err), err)); - GGML_LOG_CONT("."); - } else { - GGML_LOG_WARN("ggml_opencl: conv2d kernel source not found or empty. This op will not be available.\n"); - backend_ctx->program_conv_2d_f16 = nullptr; - backend_ctx->kernel_conv_2d_f16 = nullptr; - backend_ctx->program_conv_2d_f32 = nullptr; - backend_ctx->kernel_conv_2d_f32 = nullptr; - } - if (!kernel_src_f16_f32.empty()) { - backend_ctx->program_conv_2d_f16_f32 = - build_program_from_source(backend_ctx, kernel_src_f16_f32.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_conv_2d_f16_f32 = clCreateKernel(backend_ctx->program_conv_2d_f16_f32, "kernel_conv_2d", &err), err)); - GGML_LOG_CONT("."); - } else { - GGML_LOG_WARN("ggml_opencl: conv2d_f16_f32 kernel source not found or empty. This op will not be available.\n"); - backend_ctx->program_conv_2d_f16_f32 = nullptr; - backend_ctx->kernel_conv_2d_f16_f32 = nullptr; - } - } - - // ssm_conv + // scale { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "ssm_conv.cl.h" + #include "scale.cl.h" }; #else - const std::string kernel_src = read_file("ssm_conv.cl"); + const std::string kernel_src = read_file("scale.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_ssm_conv_f32_f32 = clCreateKernel(prog, "kernel_ssm_conv_f32_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_ssm_conv_f32_f32_4 = clCreateKernel(prog, "kernel_ssm_conv_f32_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_scale_f32 = clCreateKernel(prog, "kernel_scale_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_scale_f32_4 = clCreateKernel(prog, "kernel_scale_f32_4", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // ssm_scan + // silu { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "ssm_scan.cl.h" + #include "silu.cl.h" }; #else - const std::string kernel_src = read_file("ssm_scan.cl"); + const std::string kernel_src = read_file("silu.cl"); #endif - cl_program prog = + backend_ctx->program_silu = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_ssm_scan_f32 = clCreateKernel(prog, "kernel_ssm_scan_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_ssm_scan_f32_mamba2_d128 = clCreateKernel(prog, "kernel_ssm_scan_f32_mamba2_d128", &err), err)); - CL_CHECK((backend_ctx->kernel_ssm_scan_f32_mamba2_d256 = clCreateKernel(prog, "kernel_ssm_scan_f32_mamba2_d256", &err), err)); - - cl_kernel * kernels[] = { - &backend_ctx->kernel_ssm_scan_f32_mamba2_d128, - &backend_ctx->kernel_ssm_scan_f32_mamba2_d256 - }; - - // specialized kernels use subgroups and assume subgroup size is 64, - // if device does not support subgroups or subgroup size is not 64, - // release these kernels - for (int i = 0; i < 2; ++i) { - size_t subgroup_size = 0; -#if CL_TARGET_OPENCL_VERSION >= 210 - const size_t local_work_size[] = { 64, 1 }; - const cl_int subgroup_err = clGetKernelSubGroupInfo(*kernels[i], backend_ctx->device, CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE, - sizeof(local_work_size), local_work_size, sizeof(subgroup_size), &subgroup_size, nullptr); - if (subgroup_err != CL_SUCCESS) { - subgroup_size = 0; - } -#endif - // The specialized kernels reduce over one 64-lane subgroup. - if (subgroup_size != 64) { - CL_CHECK(clReleaseKernel(*kernels[i])); - *kernels[i] = nullptr; - } - } - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_silu = clCreateKernel(backend_ctx->program_silu, "kernel_silu", &err), err)); + CL_CHECK((backend_ctx->kernel_silu_4 = clCreateKernel(backend_ctx->program_silu, "kernel_silu_4", &err), err)); GGML_LOG_CONT("."); } - // gated_delta_net: one kernel per (S_V, KDA, tgpp) triple. + // softmax_f32 { - #ifdef GGML_OPENCL_EMBED_KERNELS +#ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gated_delta_net.cl.h" + #include "softmax_f32.cl.h" }; - #else - const std::string kernel_src = read_file("gated_delta_net.cl"); - #endif - - const int gdn_sizes[4] = { 16, 32, 64, 128 }; - const int sg_size = backend_ctx->gpu_family == GPU_FAMILY::ADRENO ? 64 : backend_ctx->gpu_family == GPU_FAMILY::INTEL ? 32 : -1; - if (sg_size < 0) { - GGML_LOG_ERROR("Unsupported GPU Family: only Adreno and Intel are supported.\n"); - exit(1); - } - - for (int si = 0; si < 4; si++) { - const int S_V = gdn_sizes[si]; - - // MUST match the dispatcher heuristic in ggml_cl_gated_delta_net exactly. - int lanes_per_column; - if (S_V >= 128) { - lanes_per_column = 8; - } else { - lanes_per_column = std::min(S_V, sg_size); - } - - // Round LANES_PER_COLUMN down until it is: - // * power-of-two - // * divides both S_V and sg_size - while (lanes_per_column > 1 && - (((lanes_per_column & (lanes_per_column - 1)) != 0) || - (S_V % lanes_per_column) != 0 || - (sg_size % lanes_per_column) != 0)) { - lanes_per_column >>= 1; - } - - GGML_ASSERT(lanes_per_column >= 1); - GGML_ASSERT(((lanes_per_column & (lanes_per_column - 1)) == 0)); - GGML_ASSERT((S_V % lanes_per_column) == 0); - GGML_ASSERT((sg_size % lanes_per_column) == 0); - - const bool is_partial_reduce = (lanes_per_column != 1) && (lanes_per_column < sg_size); - int use_qcom_shuffle = 0; - if (is_partial_reduce) { - if (backend_ctx->has_qcom_subgroup_shuffle) { - use_qcom_shuffle = 1; - } - } - for (int kda = 0; kda < 2; kda++) { - for (int tgpp = 0; tgpp < 2; tgpp++) { - const int cpl = (tgpp == 0) ? 1 : 4; - const int spw = (tgpp == 0) ? 1 : 1; - - std::string opts = compile_opts; - opts += " -DS_V=" + std::to_string(S_V); - opts += " -DKDA=" + std::to_string(kda); - opts += " -DSUBGROUP_SIZE=" + std::to_string(sg_size); - opts += " -DLANES_PER_COLUMN=" + std::to_string(lanes_per_column); - opts += " -DCOLS_PER_LANE_GROUP=" + std::to_string(cpl); - opts += " -DUSE_QCOM_SUBGROUP_SHUFFLE=" + std::to_string(use_qcom_shuffle); - - // Since spw=1 is found to be optimal, SUBGROUPS_PER_WG > 1 code in - // the kernel is removed. If you want to experiment with spw > 1, - // Please remember to implement code to handle it. - opts += " -DSUBGROUPS_PER_WG=" + std::to_string(spw); - - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); +#else + const std::string kernel_src = read_file("softmax_f32.cl"); +#endif + backend_ctx->program_softmax_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gated_delta_net_f32[si][kda][tgpp] = - clCreateKernel(prog, "kernel_gated_delta_net", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - } - } - } + CL_CHECK((backend_ctx->kernel_soft_max = clCreateKernel(backend_ctx->program_softmax_f32, "kernel_soft_max", &err), err)); GGML_LOG_CONT("."); } - // moe_combine (fused router-weight mul + cross-expert sum) + // softmax_f16 { - #ifdef GGML_OPENCL_EMBED_KERNELS +#ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "moe_combine.cl.h" + #include "softmax_f16.cl.h" }; - #else - const std::string kernel_src = read_file("moe_combine.cl"); - #endif - cl_program prog = build_program_from_source( - backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_moe_combine_f32 = - clCreateKernel(prog, "kernel_moe_combine_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_moe_combine_bias_f32 = - clCreateKernel(prog, "kernel_moe_combine_bias_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); +#else + const std::string kernel_src = read_file("softmax_f16.cl"); +#endif + backend_ctx->program_softmax_f16 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_soft_max_f16 = clCreateKernel(backend_ctx->program_softmax_f16, "kernel_soft_max_f16", &err), err)); GGML_LOG_CONT("."); } - // mul_mv_id_q4_0_f32_8x_flat + // softmax_4_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_id_q4_0_f32_8x_flat.cl.h" + #include "softmax_4_f32.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_id_q4_0_f32_8x_flat.cl"); + const std::string kernel_src = read_file("softmax_4_f32.cl"); #endif - backend_ctx->program_mul_mv_id_q4_0_f32_8x_flat = + backend_ctx->program_softmax_4_f32 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_id_q4_0_f32_8x_flat = clCreateKernel(backend_ctx->program_mul_mv_id_q4_0_f32_8x_flat, "kernel_mul_mv_id_q4_0_f32_8x_flat", &err), err)); + CL_CHECK((backend_ctx->kernel_soft_max_4 = clCreateKernel(backend_ctx->program_softmax_4_f32, "kernel_soft_max_4", &err), err)); GGML_LOG_CONT("."); } - // mul_mv_id_q8_0_f32 + // softmax_4_f16 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_id_q8_0_f32.cl.h" + #include "softmax_4_f16.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_id_q8_0_f32.cl"); + const std::string kernel_src = read_file("softmax_4_f16.cl"); #endif - backend_ctx->program_mul_mv_id_q8_0_f32 = + backend_ctx->program_softmax_4_f16 = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32, "kernel_mul_mv_id_q8_0_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_soft_max_4_f16 = clCreateKernel(backend_ctx->program_softmax_4_f16, "kernel_soft_max_4_f16", &err), err)); GGML_LOG_CONT("."); } - // mul_mv_id_q8_0_f32_flat + // div { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_id_q8_0_f32_flat.cl.h" + #include "div.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_id_q8_0_f32_flat.cl"); + const std::string kernel_src = read_file("div.cl"); #endif - backend_ctx->program_mul_mv_id_q8_0_f32_flat = + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable -cl-finite-math-only "; + + backend_ctx->program_div = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32_flat, "kernel_mul_mv_id_q8_0_f32_flat", &err), err)); + CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); + CL_CHECK((backend_ctx->kernel_div_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_row_f16", &err), err)); GGML_LOG_CONT("."); } - // mul_mv_id_mxfp4_f32 + // sqr { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_id_mxfp4_f32.cl.h" + #include "sqr.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32.cl"); + const std::string kernel_src = read_file("sqr.cl"); #endif - backend_ctx->program_mul_mv_id_mxfp4_f32 = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32, "kernel_mul_mv_id_mxfp4_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_sqr_cont_f32 = clCreateKernel(prog, "kernel_sqr_cont_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_sqr_cont_f32_4 = clCreateKernel(prog, "kernel_sqr_cont_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_sqr_cont_f16 = clCreateKernel(prog, "kernel_sqr_cont_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_sqr_cont_f16_4 = clCreateKernel(prog, "kernel_sqr_cont_f16_4", &err), err)); + + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // mul_mv_id_mxfp4_f32_flat + // sqrt { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "mul_mv_id_mxfp4_f32_flat.cl.h" + #include "sqrt.cl.h" }; #else - const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32_flat.cl"); + const std::string kernel_src = read_file("sqrt.cl"); #endif - backend_ctx->program_mul_mv_id_mxfp4_f32_flat = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32_flat, "kernel_mul_mv_id_mxfp4_f32_flat", &err), err)); + CL_CHECK((backend_ctx->kernel_sqrt_cont_f32 = clCreateKernel(prog, "kernel_sqrt_cont_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_sqrt_cont_f32_4 = clCreateKernel(prog, "kernel_sqrt_cont_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_sqrt_cont_f16 = clCreateKernel(prog, "kernel_sqrt_cont_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_sqrt_cont_f16_4 = clCreateKernel(prog, "kernel_sqrt_cont_f16_4", &err), err)); + + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // Adreno kernels -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // transpose + // mean { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "transpose.cl.h" + #include "mean.cl.h" }; #else - const std::string kernel_src = read_file("transpose.cl"); + const std::string kernel_src = read_file("mean.cl"); #endif - backend_ctx->program_transpose = + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_transpose_32_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32_16", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_32 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_8_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_8_buf", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_16_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16_buf", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_32_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32_buf", &err), err)); - CL_CHECK((backend_ctx->kernel_transpose_16_4x1 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16_4x1", &err), err)); + CL_CHECK((backend_ctx->kernel_mean_f32 = clCreateKernel(prog, "kernel_mean_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_mean_f32_4 = clCreateKernel(prog, "kernel_mean_f32_4", &err), err)); + + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q1_0_f32 + // sub { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q1_0_f32.cl.h" + #include "sub.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q1_0_f32.cl"); + const std::string kernel_src = read_file("sub.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q1_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q1_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + backend_ctx->program_sub = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row_f16", &err), err)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q1_0_f32 + // sum_rows { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src_CL_gemv_general { - #include "gemv_noshuffle_q1_0_f32.cl.h" + const std::string kernel_src { + #include "sum_rows.cl.h" }; #else - const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q1_0_f32.cl"); + const std::string kernel_src = read_file("sum_rows.cl"); #endif + backend_ctx->program_sum_rows_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q1_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q1_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_sum_rows_f32 = clCreateKernel(backend_ctx->program_sum_rows_f32, "kernel_sum_rows_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_sum_rows_f32_4 = clCreateKernel(backend_ctx->program_sum_rows_f32, "kernel_sum_rows_f32_4", &err), err)); GGML_LOG_CONT("."); } - // gemv_noshuffle_general + // cumsum { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X) { - CL_gemv_compile_opts += " -DGGML_CL_A6X_CONSTFOLD_FIX"; - } - #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src_CL_gemv_general { - #include "gemv_noshuffle_q4_0_f32.cl.h" + const std::string kernel_src { + #include "cumsum.cl.h" }; #else - const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q4_0_f32.cl"); + const std::string kernel_src = read_file("cumsum.cl"); #endif + cl_program prog; + prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32_mc3", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_cumsum_blk = clCreateKernel(prog, "kernel_cumsum_blk", &err), err)); + CL_CHECK((backend_ctx->kernel_cumsum_add = clCreateKernel(prog, "kernel_cumsum_add", &err), err)); GGML_LOG_CONT("."); + CL_CHECK(clReleaseProgram(prog)); } - // gemv_noshuffle + // sigmoid { - // Gemv 2048, 16384 - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DLINE_STRIDE_A=2048 " - " -DBLOCK_STRIDE_A=16384 " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src_CL_gemv { - #include "gemv_noshuffle_q4_0_f32_spec.cl.h" + const std::string kernel_src { + #include "sigmoid.cl.h" }; #else - const std::string kernel_src_CL_gemv = read_file("gemv_noshuffle_q4_0_f32_spec.cl"); + const std::string kernel_src = read_file("sigmoid.cl"); #endif + backend_ctx->program_sigmoid = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - - // Gemv 2048, 16384 - CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DLINE_STRIDE_A=2048 " - " -DBLOCK_STRIDE_A=16384 " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - - prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_11008 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - - // Gemv 5504, 44032 - CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DLINE_STRIDE_A=5504 " - " -DBLOCK_STRIDE_A=44032 " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - - prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_11008_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_sigmoid_f32 = clCreateKernel(backend_ctx->program_sigmoid, "kernel_sigmoid_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_sigmoid_f16 = clCreateKernel(backend_ctx->program_sigmoid, "kernel_sigmoid_f16", &err), err)); GGML_LOG_CONT("."); + } - // Gemv 16000, 128000 - CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DLINE_STRIDE_A=16000 " - " -DBLOCK_STRIDE_A=128000 " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } + // group_norm + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "group_norm.cl.h" + }; +#else + const std::string kernel_src = read_file("group_norm.cl"); +#endif + backend_ctx->program_group_norm = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32000_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_group_norm = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_group_norm_mul_add = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm_mul_add", &err), err)); GGML_LOG_CONT("."); } - // mul_mat_Ab_Bi_8x4 + // repeat { #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src_CL_gemm { - #include "gemm_noshuffle_q4_0_f32.cl.h" + const std::string kernel_src { + #include "repeat.cl.h" }; #else - const std::string kernel_src_CL_gemm = read_file("gemm_noshuffle_q4_0_f32.cl"); + const std::string kernel_src = read_file("repeat.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemm.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_0_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_repeat_f32 = clCreateKernel(prog, "kernel_repeat_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans = nullptr; - backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin = nullptr; - backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin = nullptr; + // pad { - { - std::string opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q4_0_f32_32b_trans.cl.h" - }; + const std::string kernel_src { + #include "pad.cl.h" + }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q4_0_f32_32b_trans.cl"); + const std::string kernel_src = read_file("pad.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans = - clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32_32b_trans", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + if (!kernel_src.empty()) { + backend_ctx->program_pad = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_pad = clCreateKernel(backend_ctx->program_pad, "kernel_pad", &err), err)); GGML_LOG_CONT("."); - } - - if (use_adreno_bin_kernels(backend_ctx)) { - size_t bin_size = 0; - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_0_f32_32b_trans_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - - kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } + } else { + GGML_LOG_WARN("ggml_opencl: pad kernel source not found or empty. Pad operations will not be available.\n"); + backend_ctx->program_pad = nullptr; + backend_ctx->kernel_pad = nullptr; } } - // gemm_noshuffle_q4_1_f32 + // tanh { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q4_1_f32.cl.h" + #include "tanh.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q4_1_f32.cl"); + const std::string kernel_src = read_file("tanh.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_1_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_1_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_tanh_f32 = clCreateKernel(prog, "kernel_tanh_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_tanh_f32_4 = clCreateKernel(prog, "kernel_tanh_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_tanh_f32_nc = clCreateKernel(prog, "kernel_tanh_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_tanh_f16 = clCreateKernel(prog, "kernel_tanh_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_tanh_f16_4 = clCreateKernel(prog, "kernel_tanh_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_tanh_f16_nc = clCreateKernel(prog, "kernel_tanh_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q4_1_f32 + // neg { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q4_1_f32.cl.h" + #include "neg.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q4_1_f32.cl"); + const std::string kernel_src = read_file("neg.cl"); #endif - - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_1_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_1_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_1_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_1_f32_mc3", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_neg_f32 = clCreateKernel(prog, "kernel_neg_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_neg_f32_4 = clCreateKernel(prog, "kernel_neg_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_neg_f32_nc = clCreateKernel(prog, "kernel_neg_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_neg_f16 = clCreateKernel(prog, "kernel_neg_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_neg_f16_4 = clCreateKernel(prog, "kernel_neg_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_neg_f16_nc = clCreateKernel(prog, "kernel_neg_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q5_0_f32 + // exp { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q5_0_f32.cl.h" + #include "exp.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q5_0_f32.cl"); + const std::string kernel_src = read_file("exp.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_exp_f32 = clCreateKernel(prog, "kernel_exp_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_exp_f32_4 = clCreateKernel(prog, "kernel_exp_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_exp_f32_nc = clCreateKernel(prog, "kernel_exp_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_exp_f16 = clCreateKernel(prog, "kernel_exp_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_exp_f16_4 = clCreateKernel(prog, "kernel_exp_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_exp_f16_nc = clCreateKernel(prog, "kernel_exp_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q5_0_q8_1_dp4a (dp4a dense q5_0 prefill GEMM) - if (backend_ctx->has_integer_dot) { + // expm1 + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q5_0_q8_1_dp4a.cl.h" + #include "expm1.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q5_0_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("expm1.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_q8_1_dp4a", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_expm1_f32 = clCreateKernel(prog, "kernel_expm1_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_expm1_f32_4 = clCreateKernel(prog, "kernel_expm1_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_expm1_f32_nc = clCreateKernel(prog, "kernel_expm1_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_expm1_f16 = clCreateKernel(prog, "kernel_expm1_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_expm1_f16_4 = clCreateKernel(prog, "kernel_expm1_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_expm1_f16_nc = clCreateKernel(prog, "kernel_expm1_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q5_0_f32 + // abs { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q5_0_f32.cl.h" + #include "abs.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q5_0_f32.cl"); + const std::string kernel_src = read_file("abs.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_0_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_abs_f32 = clCreateKernel(prog, "kernel_abs_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_abs_f32_4 = clCreateKernel(prog, "kernel_abs_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_abs_f32_nc = clCreateKernel(prog, "kernel_abs_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_abs_f16 = clCreateKernel(prog, "kernel_abs_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_abs_f16_4 = clCreateKernel(prog, "kernel_abs_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_abs_f16_nc = clCreateKernel(prog, "kernel_abs_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q5_1_f32 + // unary_ext (sgn, step, elu, hardswish, hardsigmoid, floor, ceil, round, trunc) { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q5_1_f32.cl.h" + #include "unary_ext.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q5_1_f32.cl"); + const std::string kernel_src = read_file("unary_ext.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_1_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_1_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); +#define CL_UNARY_EXT_K(op) \ + CL_CHECK((backend_ctx->kernel_##op##_f32 = clCreateKernel(prog, "kernel_" #op "_f32", &err), err)); \ + CL_CHECK((backend_ctx->kernel_##op##_f32_4 = clCreateKernel(prog, "kernel_" #op "_f32_4", &err), err)); \ + CL_CHECK((backend_ctx->kernel_##op##_f32_nc = clCreateKernel(prog, "kernel_" #op "_f32_nc", &err), err)); \ + CL_CHECK((backend_ctx->kernel_##op##_f16 = clCreateKernel(prog, "kernel_" #op "_f16", &err), err)); \ + CL_CHECK((backend_ctx->kernel_##op##_f16_4 = clCreateKernel(prog, "kernel_" #op "_f16_4", &err), err)); \ + CL_CHECK((backend_ctx->kernel_##op##_f16_nc = clCreateKernel(prog, "kernel_" #op "_f16_nc", &err), err)); + CL_UNARY_EXT_K(sgn) + CL_UNARY_EXT_K(step) + CL_UNARY_EXT_K(elu) + CL_UNARY_EXT_K(hardswish) + CL_UNARY_EXT_K(hardsigmoid) + CL_UNARY_EXT_K(floor) + CL_UNARY_EXT_K(ceil) + CL_UNARY_EXT_K(round) + CL_UNARY_EXT_K(trunc) +#undef CL_UNARY_EXT_K CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q5_1_f32 + // softplus { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q5_1_f32.cl.h" + #include "softplus.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q5_1_f32.cl"); + const std::string kernel_src = read_file("softplus.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_1_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_1_f32", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_softplus_f32 = clCreateKernel(prog, "kernel_softplus_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_softplus_f32_4 = clCreateKernel(prog, "kernel_softplus_f32_4", &err), err)); + CL_CHECK((backend_ctx->kernel_softplus_f32_nc = clCreateKernel(prog, "kernel_softplus_f32_nc", &err), err)); + CL_CHECK((backend_ctx->kernel_softplus_f16 = clCreateKernel(prog, "kernel_softplus_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_softplus_f16_4 = clCreateKernel(prog, "kernel_softplus_f16_4", &err), err)); + CL_CHECK((backend_ctx->kernel_softplus_f16_nc = clCreateKernel(prog, "kernel_softplus_f16_nc", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_iq4_nl_f32 + // upscale { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_iq4_nl_f32.cl.h" + #include "upscale.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_iq4_nl_f32.cl"); + const std::string kernel_src = read_file("upscale.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq4_nl_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq4_nl_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + if (!kernel_src.empty()) { + backend_ctx->program_upscale = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_upscale = clCreateKernel(backend_ctx->program_upscale, "kernel_upscale", &err), err)); + if (backend_ctx->program_upscale) { + cl_int err_bilinear; + backend_ctx->kernel_upscale_bilinear = clCreateKernel(backend_ctx->program_upscale, "kernel_upscale_bilinear", &err_bilinear); + if (err_bilinear != CL_SUCCESS) { + GGML_LOG_WARN("ggml_opencl: kernel_upscale_bilinear not found in upscale.cl. Bilinear upscale will not be available. Error: %d\n", err_bilinear); + backend_ctx->kernel_upscale_bilinear = nullptr; + } + } else { + backend_ctx->kernel_upscale_bilinear = nullptr; + } + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: upscale kernel source not found or empty. Upscale operations will not be available.\n"); + backend_ctx->program_upscale = nullptr; + backend_ctx->kernel_upscale = nullptr; + backend_ctx->kernel_upscale_bilinear = nullptr; + } } - // gemm_noshuffle_iq4_nl_q8_1_dp4a (dp4a dense IQ4_NL prefill GEMM) - if (backend_ctx->has_integer_dot) { + // concat + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_iq4_nl_q8_1_dp4a.cl.h" + #include "concat.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_iq4_nl_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("concat.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_concat_b1 = clCreateKernel(prog, "kernel_concat_b1", &err), err)); + CL_CHECK((backend_ctx->kernel_concat_b2 = clCreateKernel(prog, "kernel_concat_b2", &err), err)); + CL_CHECK((backend_ctx->kernel_concat_b4 = clCreateKernel(prog, "kernel_concat_b4", &err), err)); + CL_CHECK((backend_ctx->kernel_concat_b8 = clCreateKernel(prog, "kernel_concat_b8", &err), err)); + CL_CHECK((backend_ctx->kernel_concat_b4_pack = clCreateKernel(prog, "kernel_concat_b4_pack", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q4_0_q8_1_dp4a (dp4a dense q4_0 prefill GEMM) - if (backend_ctx->has_integer_dot) { + // timestep_embedding + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q4_0_q8_1_dp4a.cl.h" + #include "tsembd.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q4_0_q8_1_dp4a.cl"); + + const std::string kernel_src = read_file("tsembd.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_0_q8_1_dp4a", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + if (!kernel_src.empty()) { + backend_ctx->program_tsembd = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_timestep_embedding = clCreateKernel(backend_ctx->program_tsembd, "kernel_timestep_embedding", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: timestep_embedding kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_tsembd = nullptr; + backend_ctx->kernel_timestep_embedding = nullptr; + } } - // gemv_noshuffle_iq4_nl_f32 + // set_rows { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_iq4_nl_f32.cl.h" + #include "set_rows.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_iq4_nl_f32.cl"); + const std::string kernel_src = read_file("set_rows.cl"); #endif + backend_ctx->program_set_rows = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_iq4_nl_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_iq4_nl_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_set_rows_f32_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f32_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f16_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f16_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q8_0_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q8_0_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q8_0_soa_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_soa_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q8_0_soa_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q8_0_soa_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q4_0_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q4_0_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q4_0_soa_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_soa_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_q4_0_soa_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_q4_0_soa_i32", &err), err)); GGML_LOG_CONT("."); } - // mul_mm_q8_0_f32_8x4 + // conv2d { -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemm_noshuffle_q8_0_f32.cl.h" - }; -#else - const std::string kernel_src = read_file("gemm_noshuffle_q8_0_f32.cl"); -#endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_f32", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - - // gemm_noshuffle_q8_0_f32_bin - { - size_t bin_size = 0; - backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q8_0_f32_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_f32_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } - } - - if (backend_ctx->has_integer_dot) { - size_t bin_size = 0; - backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } + #ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "conv2d.cl.h" + }; + const std::string kernel_src_f16_f32 { + #include "conv2d_f16_f32.cl.h" + }; + #else + const std::string kernel_src = read_file("conv2d.cl"); + const std::string kernel_src_f16_f32 = read_file("conv2d_f16_f32.cl"); + #endif + if (!kernel_src.empty()) { + backend_ctx->program_conv_2d_f16 = + build_program_from_source(backend_ctx, kernel_src.c_str(), (std::string(compile_opts) + " -DUSE_FP16=1").c_str()); + CL_CHECK((backend_ctx->kernel_conv_2d_f16 = clCreateKernel(backend_ctx->program_conv_2d_f16, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + backend_ctx->program_conv_2d_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f32 = clCreateKernel(backend_ctx->program_conv_2d_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16 = nullptr; + backend_ctx->kernel_conv_2d_f16 = nullptr; + backend_ctx->program_conv_2d_f32 = nullptr; + backend_ctx->kernel_conv_2d_f32 = nullptr; + } + if (!kernel_src_f16_f32.empty()) { + backend_ctx->program_conv_2d_f16_f32 = + build_program_from_source(backend_ctx, kernel_src_f16_f32.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f16_f32 = clCreateKernel(backend_ctx->program_conv_2d_f16_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d_f16_f32 kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16_f32 = nullptr; + backend_ctx->kernel_conv_2d_f16_f32 = nullptr; + } } - // gemv_noshuffle_general_q8_0_f32 + // conv2_dw { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; - } - #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src_CL_gemv_general { - #include "gemv_noshuffle_q8_0_f32.cl.h" + const std::string kernel_src { + #include "conv2_dw.cl.h" }; #else - const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q8_0_f32.cl"); + const std::string kernel_src = read_file("conv2_dw.cl"); #endif - - cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q8_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q8_0_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk = clCreateKernel(prog, "kernel_gemv_noshuffle_q8_0_f32_splitk", &err), err)); + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv2d_dw_f32_f32 = clCreateKernel(prog, "kernel_conv2d_dw_f32_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_conv2d_dwf16_f32 = clCreateKernel(prog, "kernel_conv2d_dwf16_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q4_k_f32 + // ssm_conv { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q4_k_f32.cl.h" + #include "ssm_conv.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q4_k_f32.cl"); + const std::string kernel_src = read_file("ssm_conv.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_r1 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_r1", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_kimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_kimg", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_cok = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_cok", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - // gemm_noshuffle_q4_k_q8_1_dp4a (dp4a dense prefill GEMM) - if (backend_ctx->has_integer_dot) { -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemm_noshuffle_q4_k_q8_1_dp4a.cl.h" - }; -#else - const std::string kernel_src = read_file("gemm_noshuffle_q4_k_q8_1_dp4a.cl"); -#endif - // Per-device dp4a dense tile. The X2-tuned TILESIZE_N=32 over-occupies LDS on - // X1 (1152 B/WG -> few resident WGs); TILESIZE_N=8 (288 B) lifts occupancy on - // X1, byte-identical. X2E keeps 32. Env override wins. - int q4k_dp4a_ts = (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E) ? 8 : 32; - if (const char * e = getenv("GGML_OPENCL_Q4K_DP4A_TS")) { q4k_dp4a_ts = atoi(e); } - std::string dp4a_opts = compile_opts + " -DTILESIZE_N=" + std::to_string(q4k_dp4a_ts); - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), dp4a_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg", &err), err)); + CL_CHECK((backend_ctx->kernel_ssm_conv_f32_f32 = clCreateKernel(prog, "kernel_ssm_conv_f32_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_ssm_conv_f32_f32_4 = clCreateKernel(prog, "kernel_ssm_conv_f32_f32_4", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q8_0_q8_1_dp4a (dp4a dense q8_0 prefill GEMM) - if (backend_ctx->has_integer_dot) { + // ssm_scan + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q8_0_q8_1_dp4a.cl.h" + #include "ssm_scan.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q8_0_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("ssm_scan.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - // gemm_noshuffle_q5_k_q8_1_dp4a (dp4a dense prefill GEMM for q5_K) - if (backend_ctx->has_integer_dot) { -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemm_noshuffle_q5_k_q8_1_dp4a.cl.h" - }; -#else - const std::string kernel_src = read_file("gemm_noshuffle_q5_k_q8_1_dp4a.cl"); -#endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_k_q8_1_dp4a", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } + CL_CHECK((backend_ctx->kernel_ssm_scan_f32 = clCreateKernel(prog, "kernel_ssm_scan_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_ssm_scan_f32_mamba2_d128 = clCreateKernel(prog, "kernel_ssm_scan_f32_mamba2_d128", &err), err)); + CL_CHECK((backend_ctx->kernel_ssm_scan_f32_mamba2_d256 = clCreateKernel(prog, "kernel_ssm_scan_f32_mamba2_d256", &err), err)); - // gemm_noshuffle_q6_k_q8_1_dp4a (dp4a dense prefill GEMM for q6_K ffn_down/output) - if (backend_ctx->has_integer_dot) { -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemm_noshuffle_q6_k_q8_1_dp4a.cl.h" + cl_kernel * kernels[] = { + &backend_ctx->kernel_ssm_scan_f32_mamba2_d128, + &backend_ctx->kernel_ssm_scan_f32_mamba2_d256 }; -#else - const std::string kernel_src = read_file("gemm_noshuffle_q6_k_q8_1_dp4a.cl"); + + // specialized kernels use subgroups and assume subgroup size is 64, + // if device does not support subgroups or subgroup size is not 64, + // release these kernels + for (int i = 0; i < 2; ++i) { + size_t subgroup_size = 0; +#if CL_TARGET_OPENCL_VERSION >= 210 + const size_t local_work_size[] = { 64, 1 }; + const cl_int subgroup_err = clGetKernelSubGroupInfo(*kernels[i], backend_ctx->device, CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE, + sizeof(local_work_size), local_work_size, sizeof(subgroup_size), &subgroup_size, nullptr); + if (subgroup_err != CL_SUCCESS) { + subgroup_size = 0; + } #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_k_q8_1_dp4a", &err), err)); + // The specialized kernels reduce over one 64-lane subgroup. + if (subgroup_size != 64) { + CL_CHECK(clReleaseKernel(*kernels[i])); + *kernels[i] = nullptr; + } + } CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // quant_a_q8_1 (plain activation q8_1 pre-pass for the dense dp4a GEMM) + // gated_delta_net: one kernel per (S_V, KDA, tgpp) triple. { -#ifdef GGML_OPENCL_EMBED_KERNELS + #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "quant_a_q8_1.cl.h" + #include "gated_delta_net.cl.h" }; -#else - const std::string kernel_src = read_file("quant_a_q8_1.cl"); -#endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_quant_a_q8_1 = clCreateKernel(prog, "kernel_quant_a_q8_1", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } + #else + const std::string kernel_src = read_file("gated_delta_net.cl"); + #endif - // gemv_noshuffle_q4_k_f32 - { - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } - if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X) { - CL_gemv_compile_opts += " -DGGML_CL_A6X_CONSTFOLD_FIX"; - } - // Opt-in: dequant-once-per-block mc3 verify GEMV (factors q4_K dequant - // out of the 3-column loop; byte-identical, lower spill). A/B vs the - // shipped inline mc3 in the same binary. - if (getenv("GGML_OPENCL_Q4K_MC3_DQ")) { - CL_gemv_compile_opts += " -DQ4K_MC3_DEQUANT_ONCE "; - } - // Opt-in: LDS-staged dequant mc3 verify GEMV (stages the dequantized - // q4_K weights in __local instead of private regs that spill to slow - // global on Adreno; byte-identical). A/B vs inline + dequant-once. - if (getenv("GGML_OPENCL_Q4K_MC3_LDS")) { - CL_gemv_compile_opts += " -DQ4K_MC3_DEQUANT_LDS "; + const int gdn_sizes[4] = { 16, 32, 64, 128 }; + const int sg_size = backend_ctx->gpu_family == GPU_FAMILY::ADRENO ? 64 : backend_ctx->gpu_family == GPU_FAMILY::INTEL ? 32 : -1; + if (sg_size < 0) { + GGML_LOG_ERROR("Unsupported GPU Family: only Adreno and Intel are supported.\n"); + exit(1); } -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q4_k_f32.cl.h" - }; -#else - const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32.cl"); -#endif - - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + for (int si = 0; si < 4; si++) { + const int S_V = gdn_sizes[si]; - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_mc3", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_splitk = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_splitk", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_splitk_reduce_f32 = clCreateKernel(prog, "kernel_gemv_splitk_reduce_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_glu = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_glu", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } + // MUST match the dispatcher heuristic in ggml_cl_gated_delta_net exactly. + int lanes_per_column; + if (S_V >= 128) { + lanes_per_column = 8; + } else { + lanes_per_column = std::min(S_V, sg_size); + } - // gemv_noshuffle_q4_k_f32_o4 — 4-output-per-WI variant for the long-vocab - // q4_K lm_head/embed GEMV (shares one activation read across 4 output rows). + // Round LANES_PER_COLUMN down until it is: + // * power-of-two + // * divides both S_V and sg_size + while (lanes_per_column > 1 && + (((lanes_per_column & (lanes_per_column - 1)) != 0) || + (S_V % lanes_per_column) != 0 || + (sg_size % lanes_per_column) != 0)) { + lanes_per_column >>= 1; + } + + GGML_ASSERT(lanes_per_column >= 1); + GGML_ASSERT(((lanes_per_column & (lanes_per_column - 1)) == 0)); + GGML_ASSERT((S_V % lanes_per_column) == 0); + GGML_ASSERT((sg_size % lanes_per_column) == 0); + + const bool is_partial_reduce = (lanes_per_column != 1) && (lanes_per_column < sg_size); + int use_qcom_shuffle = 0; + if (is_partial_reduce) { + if (backend_ctx->has_qcom_subgroup_shuffle) { + use_qcom_shuffle = 1; + } + } + for (int kda = 0; kda < 2; kda++) { + for (int tgpp = 0; tgpp < 2; tgpp++) { + const int cpl = (tgpp == 0) ? 1 : 4; + const int spw = (tgpp == 0) ? 1 : 1; + + std::string opts = compile_opts; + opts += " -DS_V=" + std::to_string(S_V); + opts += " -DKDA=" + std::to_string(kda); + opts += " -DSUBGROUP_SIZE=" + std::to_string(sg_size); + opts += " -DLANES_PER_COLUMN=" + std::to_string(lanes_per_column); + opts += " -DCOLS_PER_LANE_GROUP=" + std::to_string(cpl); + opts += " -DUSE_QCOM_SUBGROUP_SHUFFLE=" + std::to_string(use_qcom_shuffle); + + // Since spw=1 is found to be optimal, SUBGROUPS_PER_WG > 1 code in + // the kernel is removed. If you want to experiment with spw > 1, + // Please remember to implement code to handle it. + opts += " -DSUBGROUPS_PER_WG=" + std::to_string(spw); + + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + + CL_CHECK((backend_ctx->kernel_gated_delta_net_f32[si][kda][tgpp] = + clCreateKernel(prog, "kernel_gated_delta_net", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + } + } + } + GGML_LOG_CONT("."); + } + + // moe_combine (fused router-weight mul + cross-expert sum) { -#ifdef GGML_OPENCL_EMBED_KERNELS + #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q4_k_f32_o4.cl.h" + #include "moe_combine.cl.h" }; -#else - const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_o4.cl"); -#endif - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; - if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; - } + #else + const std::string kernel_src = read_file("moe_combine.cl"); + #endif cl_program prog = build_program_from_source( - backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_o4 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_o4", &err), err)); + backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_moe_combine_f32 = + clCreateKernel(prog, "kernel_moe_combine_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_moe_combine_bias_f32 = + clCreateKernel(prog, "kernel_moe_combine_bias_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q4_k_f32_tiled — tiled-wide canonical layout, default ON - // (opt out: GGML_OPENCL_Q4K_GEMV_TILED=0; separate convert + GEMV; weights via __global). + // mul_mv_id_q4_0_f32_8x_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q4_k_f32_tiled.cl.h" + #include "mul_mv_id_q4_0_f32_8x_flat.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_tiled.cl"); + const std::string kernel_src = read_file("mul_mv_id_q4_0_f32_8x_flat.cl"); #endif - std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; - cl_program prog = + backend_ctx->program_mul_mv_id_q4_0_f32_8x_flat = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_tiled = - clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_tiled", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + + CL_CHECK((backend_ctx->kernel_mul_mv_id_q4_0_f32_8x_flat = clCreateKernel(backend_ctx->program_mul_mv_id_q4_0_f32_8x_flat, "kernel_mul_mv_id_q4_0_f32_8x_flat", &err), err)); GGML_LOG_CONT("."); } - backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans = nullptr; - backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin = nullptr; - backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin = nullptr; + // mul_mv_id_q8_0_f32 { - if (backend_ctx->has_vector_subgroup_broadcast) { - std::string opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q4_k_f32_32b_trans.cl.h" - }; + const std::string kernel_src { + #include "mul_mv_id_q8_0_f32.cl.h" + }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_32b_trans.cl"); + const std::string kernel_src = read_file("mul_mv_id_q8_0_f32.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans = - clCreateKernel(prog, "gemv_noshuffle_q4_k_f32_32b_trans", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - - if (use_adreno_bin_kernels(backend_ctx)) { - size_t bin_size = 0; - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - - kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + backend_ctx->program_mul_mv_id_q8_0_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - } + CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32, "kernel_mul_mv_id_q8_0_f32", &err), err)); + GGML_LOG_CONT("."); } - backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans = nullptr; - backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin = nullptr; - backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin = nullptr; + // mul_mv_id_q8_0_f32_flat { - if (backend_ctx->has_vector_subgroup_broadcast) { - std::string opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q6_k_f32_32b_trans.cl.h" - }; + const std::string kernel_src { + #include "mul_mv_id_q8_0_f32_flat.cl.h" + }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_32b_trans.cl"); + const std::string kernel_src = read_file("mul_mv_id_q8_0_f32_flat.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans = - clCreateKernel(prog, "kernel_gemv_noshuffle_q6_k_f32_32b_trans", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - - if (use_adreno_bin_kernels(backend_ctx)) { - size_t bin_size = 0; - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q6_k_f32_32b_trans_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - - kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + backend_ctx->program_mul_mv_id_q8_0_f32_flat = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - } + CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32_flat, "kernel_mul_mv_id_q8_0_f32_flat", &err), err)); + GGML_LOG_CONT("."); } - backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans = nullptr; - backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin = nullptr; - backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin = nullptr; + // mul_mv_id_mxfp4_f32 { - if (backend_ctx->has_vector_subgroup_broadcast) { - std::string opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -DSIMDGROUP_WIDTH=" + - std::to_string(backend_ctx->adreno_wave_size); #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q5_k_f32_32b_trans.cl.h" - }; + const std::string kernel_src { + #include "mul_mv_id_mxfp4_f32.cl.h" + }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q5_k_f32_32b_trans.cl"); + const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans = - clCreateKernel(prog, "gemv_noshuffle_q5_k_f32_32b_trans", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - - if (use_adreno_bin_kernels(backend_ctx)) { - size_t bin_size = 0; - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q5_k_f32_32b_trans_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - - kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program bin_prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + backend_ctx->program_mul_mv_id_mxfp4_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin = - clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8", &err), err)); - CL_CHECK(clReleaseProgram(bin_prog)); - GGML_LOG_CONT("."); - } - } + CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32, "kernel_mul_mv_id_mxfp4_f32", &err), err)); + GGML_LOG_CONT("."); } - std::string CL_moe_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable " - " -cl-fast-relaxed-math"; - - // gemv_moe_q4_1_f32_ns + // mul_mv_id_mxfp4_f32_flat { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q4_1_f32_ns.cl.h" + #include "mul_mv_id_mxfp4_f32_flat.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q4_1_f32_ns.cl"); + const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32_flat.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + backend_ctx->program_mul_mv_id_mxfp4_f32_flat = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_moe_q4_1_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_1_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32_flat, "kernel_mul_mv_id_mxfp4_f32_flat", &err), err)); GGML_LOG_CONT("."); } - // gemm_moe_q4_1_f32_ns + // Adreno kernels +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // transpose { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q4_1_f32_ns.cl.h" + #include "transpose.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q4_1_f32_ns.cl"); + const std::string kernel_src = read_file("transpose.cl"); #endif - cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + backend_ctx->program_transpose = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_1_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_1_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + CL_CHECK((backend_ctx->kernel_transpose_32_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32_16", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_32 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_8_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_8_buf", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_16_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16_buf", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_32_buf = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32_buf", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_16_4x1 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16_4x1", &err), err)); GGML_LOG_CONT("."); } - // gemm_moe_q4_1_f32_ns_bin + // gemm_noshuffle_q1_0_f32 { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q4_1_f32_ns_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_1_f32_ns_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_1_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_1_f32_ns_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q1_0_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q1_0_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q1_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q1_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // gemv_moe_mxfp4_f32 + // gemv_noshuffle_q1_0_f32 { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); + #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_moe_mxfp4_f32.cl.h" + const std::string kernel_src_CL_gemv_general { + #include "gemv_noshuffle_q1_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_mxfp4_f32.cl"); + const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q1_0_f32.cl"); #endif - backend_ctx->program_gemv_moe_mxfp4_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32 = clCreateKernel(backend_ctx->program_gemv_moe_mxfp4_f32, "kernel_gemv_moe_mxfp4_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q1_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q1_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + + const char * nsg1_min_m_env = getenv("GGML_OPENCL_Q1_0_GEMV_NSG1_MIN_M"); + backend_ctx->min_m_gemv_nsg1_q1_0 = nsg1_min_m_env ? atoi(nsg1_min_m_env) : + (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E ? 8192 : 0); + if (backend_ctx->min_m_gemv_nsg1_q1_0 > 0) { + const std::string nsg1_opts = CL_gemv_compile_opts + " -DN_SIMDGROUP=1"; + cl_program prog_nsg1 = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), nsg1_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q1_0_f32_nsg1 = clCreateKernel(prog_nsg1, "kernel_gemv_noshuffle_q1_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog_nsg1)); + } GGML_LOG_CONT("."); } - // gemm_moe_mxfp4_f32 + // gemm_noshuffle_q3_k_q8_1_dp4a { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_mxfp4_f32.cl.h" + #include "gemm_noshuffle_q3_k_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_mxfp4_f32.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q3_k_q8_1_dp4a.cl"); #endif - backend_ctx->program_gemm_moe_mxfp4_f32 = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32 = clCreateKernel(backend_ctx->program_gemm_moe_mxfp4_f32, "kernel_gemm_moe_mxfp4_f32", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q3_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q3_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q3_k_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_q3_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_moe_q4_0_f32_ns + // gemm_noshuffle_q2_0_q8_1_dp4a { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q4_0_f32_ns.cl.h" + #include "gemm_noshuffle_q2_0_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q4_0_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q2_0_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_moe_q4_0_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_0_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_0_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_0_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_0_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_0_f32_ns + // gemm_noshuffle_q2_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q4_0_f32_ns.cl.h" + #include "gemm_noshuffle_q2_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q4_0_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q2_0_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_0_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_0_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_0_f32_ns_bin + // gemv_noshuffle_q2_0_f32 { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q4_0_f32_ns_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_0_f32_ns_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_0_f32_ns_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q2_0_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q2_0_f32.cl"); +#endif + if (const char * env = getenv("GGML_OPENCL_Q2_0_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->q2_0_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DQ2_0_MV_NSG=" + std::to_string(backend_ctx->q2_0_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_q2_0_f32", &err); + CL_CHECK(err); + CL_CHECK(clReleaseProgram(prog)); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->q2_0_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_q2_0_f32 = kernel; + break; } + CL_CHECK(clReleaseKernel(kernel)); + GGML_ASSERT(backend_ctx->q2_0_mv_nsg > 1); + backend_ctx->q2_0_mv_nsg /= 2; } + GGML_LOG_CONT("."); } - // gemm_moe_q8_0_f32_ns + // gemm_noshuffle_iq1_s_q8_1_dp4a { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q8_0_f32_ns.cl.h" + #include "gemm_noshuffle_iq1_s_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q8_0_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq1_s_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q8_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q8_0_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_s_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_s_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_s_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_s_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_moe_q5_0_f32_ns + // gemm_noshuffle_iq1_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q5_0_f32_ns.cl.h" + #include "gemm_noshuffle_iq1_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q5_0_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq1_s_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_moe_q5_0_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_0_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_s_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_s_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q5_0_f32_ns + // gemv_noshuffle_iq1_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q5_0_f32_ns.cl.h" + #include "gemv_noshuffle_iq1_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q5_0_f32_ns.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_iq1_s_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + if (const char * env = getenv("GGML_OPENCL_IQ1_S_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq1_s_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ1_S_MV_NSG=" + std::to_string(backend_ctx->iq1_s_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq1_s_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq1_s_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq1_s_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq1_s_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq1_s_grid_buffer.allocate(backend_ctx->context, 2048*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq1_s_grid_buffer.buffer)); + size_t global[] = { 2048 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); + CL_CHECK(clReleaseProgram(prog)); - CL_CHECK((backend_ctx->kernel_gemm_moe_q5_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_0_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 2048; + desc.buffer = backend_ctx->iq1_s_grid_buffer.buffer; + backend_ctx->iq1_s_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; + } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq1_s_mv_nsg > 1); + backend_ctx->iq1_s_mv_nsg /= 2; + } GGML_LOG_CONT("."); } - // gemv_moe_q5_1_f32_ns + // gemm_noshuffle_iq1_m_q8_1_dp4a { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q5_1_f32_ns.cl.h" + #include "gemm_noshuffle_iq1_m_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q5_1_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq1_m_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_moe_q5_1_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_1_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_m_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_m_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_m_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_m_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q5_1_f32_ns + // gemm_noshuffle_iq1_m_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q5_1_f32_ns.cl.h" + #include "gemm_noshuffle_iq1_m_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q5_1_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq1_m_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q5_1_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_1_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq1_m_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq1_m_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_moe_q4_k_f32_ns + // gemv_noshuffle_iq1_m_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q4_k_f32_ns.cl.h" + #include "gemv_noshuffle_iq1_m_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q4_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_iq1_m_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + if (const char * env = getenv("GGML_OPENCL_IQ1_M_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq1_m_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ1_M_MV_NSG=" + std::to_string(backend_ctx->iq1_m_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq1_s_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq1_m_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq1_m_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq1_m_f32 = kernel; + CL_CHECK(clReleaseProgram(prog)); + break; + } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq1_m_mv_nsg > 1); + backend_ctx->iq1_m_mv_nsg /= 2; + } + GGML_LOG_CONT("."); + } - CL_CHECK((backend_ctx->kernel_gemv_moe_q4_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_k_f32_ns", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_moe_q4_k_f32_ns_wimg = clCreateKernel(prog, "kernel_gemv_moe_q4_k_f32_ns_wimg", &err), err)); + // gemm_noshuffle_iq3_s_q8_1_dp4a + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_iq3_s_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_iq3_s_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_s_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_s_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_s_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_s_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_k_f32_ns + // gemm_noshuffle_iq3_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q4_k_f32_ns.cl.h" + #include "gemm_noshuffle_iq3_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q4_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq3_s_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_k_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_s_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_s_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_k_f32_ns_bin + // gemv_noshuffle_iq3_s_f32 { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q4_k_f32_ns_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_k_f32_ns_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_k_f32_ns_ila", &err), err)); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_iq3_s_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_iq3_s_f32.cl"); +#endif + if (const char * env = getenv("GGML_OPENCL_IQ3_S_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq3_s_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ3_S_MV_NSG=" + std::to_string(backend_ctx->iq3_s_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq3_s_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq3_s_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq3_s_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq3_s_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq3_s_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq3_s_grid_buffer.allocate(backend_ctx->context, 512*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq3_s_grid_buffer.buffer)); + size_t global[] = { 512 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 512; + desc.buffer = backend_ctx->iq3_s_grid_buffer.buffer; + backend_ctx->iq3_s_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq3_s_mv_nsg > 1); + backend_ctx->iq3_s_mv_nsg /= 2; } + GGML_LOG_CONT("."); } - // gemm_moe_q4_k_q8_1_dp4a (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { + // gemm_noshuffle_iq3_xxs_q8_1_dp4a + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q4_k_q8_1_dp4a.cl.h" + #include "gemm_noshuffle_iq3_xxs_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q4_k_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq3_xxs_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q4_k_q8_1_dp4a", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_k_q8_1_dp4a_bin (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a_bin = nullptr; + // gemm_noshuffle_iq3_xxs_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_iq3_xxs_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_iq3_xxs_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq3_xxs_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq3_xxs_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_k_q8_1_dp4a_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_k_q8_1_dp4a_ila", &err), err)); + // gemv_noshuffle_iq3_xxs_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_iq3_xxs_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_iq3_xxs_f32.cl"); +#endif + if (const char * env = getenv("GGML_OPENCL_IQ3_XXS_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq3_xxs_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ3_XXS_MV_NSG=" + std::to_string(backend_ctx->iq3_xxs_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq3_xxs_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq3_xxs_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq3_xxs_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq3_xxs_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq3_xxs_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq3_xxs_grid_buffer.allocate(backend_ctx->context, 256*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq3_xxs_grid_buffer.buffer)); + size_t global[] = { 256 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 256; + desc.buffer = backend_ctx->iq3_xxs_grid_buffer.buffer; + backend_ctx->iq3_xxs_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq3_xxs_mv_nsg > 1); + backend_ctx->iq3_xxs_mv_nsg /= 2; } + GGML_LOG_CONT("."); } - // gemm_moe_mxfp4_q8_1_dp4a (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { + // gemm_noshuffle_iq2_s_q8_1_dp4a + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_mxfp4_q8_1_dp4a.cl.h" + #include "gemm_noshuffle_iq2_s_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_mxfp4_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_s_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_q8_1_dp4a", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_s_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_s_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_s_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_s_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_mxfp4_q8_1_dp4a_bin (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_mxfp4_q8_1_dp4a_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_q8_1_dp4a_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } - } - - // gemm_moe_q4_0_q8_1_dp4a (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { + // gemm_noshuffle_iq2_xs_q8_1_dp4a + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q4_0_q8_1_dp4a.cl.h" + #include "gemm_noshuffle_iq2_xs_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q4_0_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_xs_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q4_0_q8_1_dp4a", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q4_0_q8_1_dp4a_bin (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_0_q8_1_dp4a_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_0_q8_1_dp4a_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } - } - - // gemm_moe_q8_1_dp4a (generic dp4a MoE GEMM; MOE_QT=80 -> q8_0 expert variant) - if (backend_ctx->has_integer_dot) { + // gemm_noshuffle_iq2_xxs_q8_1_dp4a + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q8_1_dp4a.cl.h" + #include "gemm_noshuffle_iq2_xxs_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_xxs_q8_1_dp4a.cl"); #endif - const std::string opts80 = CL_moe_compile_opts + " -DMOE_QT=80"; - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), opts80.c_str()); - CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q80 = clCreateKernel(prog, "kernel_gemm_moe_q8_1_dp4a", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a", &err), err)); CL_CHECK(clReleaseProgram(prog)); - - const std::string opts50 = CL_moe_compile_opts + " -DMOE_QT=50"; - cl_program prog50 = - build_program_from_source(backend_ctx, kernel_src.c_str(), opts50.c_str()); - CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q50 = clCreateKernel(prog50, "kernel_gemm_moe_q8_1_dp4a", &err), err)); - CL_CHECK(clReleaseProgram(prog50)); - - const std::string opts5 = CL_moe_compile_opts + " -DMOE_QT=5"; - cl_program prog5 = - build_program_from_source(backend_ctx, kernel_src.c_str(), opts5.c_str()); - CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q5k = clCreateKernel(prog5, "kernel_gemm_moe_q8_1_dp4a", &err), err)); - CL_CHECK(clReleaseProgram(prog5)); GGML_LOG_CONT("."); } - // moe_reorder_quant_a_q8_1 (fused reorder + q8_1 quant) + // gemm_noshuffle_iq2_xxs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "moe_reorder_quant_a_q8_1.cl.h" + #include "gemm_noshuffle_iq2_xxs_f32.cl.h" }; #else - const std::string kernel_src = read_file("moe_reorder_quant_a_q8_1.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_xxs_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_moe_reorder_quant_a_q8_1 = clCreateKernel(prog, "kernel_moe_reorder_quant_a_q8_1", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xxs_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xxs_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_moe_q5_k_f32_ns + // gemv_noshuffle_iq2_xxs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q5_k_f32_ns.cl.h" + #include "gemv_noshuffle_iq2_xxs_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q5_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_iq2_xxs_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + if (const char * env = getenv("GGML_OPENCL_IQ2_XXS_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq2_xxs_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ2_XXS_MV_NSG=" + std::to_string(backend_ctx->iq2_xxs_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xxs_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq2_xxs_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq2_xxs_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq2_xxs_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq2_xxs_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq2_xxs_grid_buffer.allocate(backend_ctx->context, 512*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq2_xxs_grid_buffer.buffer)); + size_t global[] = { 512 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); + CL_CHECK(clReleaseProgram(prog)); - CL_CHECK((backend_ctx->kernel_gemv_moe_q5_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_k_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 512; + desc.buffer = backend_ctx->iq2_xxs_grid_buffer.buffer; + backend_ctx->iq2_xxs_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; + } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq2_xxs_mv_nsg > 1); + backend_ctx->iq2_xxs_mv_nsg /= 2; + } GGML_LOG_CONT("."); } - // gemm_moe_q5_k_f32_ns + // gemm_noshuffle_iq2_xs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q5_k_f32_ns.cl.h" + #include "gemm_noshuffle_iq2_xs_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q5_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_xs_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q5_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_k_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_xs_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_xs_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_moe_q6_k_f32_ns + // gemv_noshuffle_iq2_xs_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_q6_k_f32_ns.cl.h" + #include "gemv_noshuffle_iq2_xs_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_q6_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_iq2_xs_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + if (const char * env = getenv("GGML_OPENCL_IQ2_XS_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq2_xs_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ2_XS_MV_NSG=" + std::to_string(backend_ctx->iq2_xs_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq2_xs_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq2_xs_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq2_xs_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq2_xs_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq2_xs_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq2_xs_grid_buffer.allocate(backend_ctx->context, 1024*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq2_xs_grid_buffer.buffer)); + size_t global[] = { 1024 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); + CL_CHECK(clReleaseProgram(prog)); - CL_CHECK((backend_ctx->kernel_gemv_moe_q6_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q6_k_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 1024; + desc.buffer = backend_ctx->iq2_xs_grid_buffer.buffer; + backend_ctx->iq2_xs_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; + } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq2_xs_mv_nsg > 1); + backend_ctx->iq2_xs_mv_nsg /= 2; + } GGML_LOG_CONT("."); } - // gemm_moe_q6_k_f32_ns + // gemm_noshuffle_iq2_s_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q6_k_f32_ns.cl.h" + #include "gemm_noshuffle_iq2_s_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q6_k_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_iq2_s_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q6_k_f32_ns", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq2_s_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq2_s_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q6_k_f32_ns_bin + // gemv_noshuffle_iq2_s_f32 { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q6_k_f32_ns_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q6_k_f32_ns_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q6_k_f32_ns_ila", &err), err)); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_iq2_s_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_iq2_s_f32.cl"); +#endif + if (const char * env = getenv("GGML_OPENCL_IQ2_S_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->iq2_s_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DIQ2_S_MV_NSG=" + std::to_string(backend_ctx->iq2_s_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, (iq2_s_grid_src + kernel_src).c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_iq2_s_f32", &err); + CL_CHECK(err); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->iq2_s_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_iq2_s_f32 = kernel; + cl_kernel export_grid = clCreateKernel(prog, "kernel_iq2_s_grid_export", &err); + CL_CHECK(err); + backend_ctx->iq2_s_grid_buffer.allocate(backend_ctx->context, 2048*sizeof(cl_uint)); + CL_CHECK(clSetKernelArg(export_grid, 0, sizeof(cl_mem), &backend_ctx->iq2_s_grid_buffer.buffer)); + size_t global[] = { 2048 }; + size_t local[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, export_grid, 1, nullptr, global, local, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseKernel(export_grid)); CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + + cl_image_format format = { CL_R, CL_UNSIGNED_INT32 }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = 2048; + desc.buffer = backend_ctx->iq2_s_grid_buffer.buffer; + backend_ctx->iq2_s_grid_image = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, &format, &desc, nullptr, &err); + CL_CHECK(err); + break; } + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(prog)); + GGML_ASSERT(backend_ctx->iq2_s_mv_nsg > 1); + backend_ctx->iq2_s_mv_nsg /= 2; } + GGML_LOG_CONT("."); } - // gemm_moe_q6_k_q8_1_dp4a (dp4a q6_K MoE prefill GEMM) - if (backend_ctx->has_integer_dot) { + // gemm_noshuffle_q3_k_f32 + { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_q6_k_q8_1_dp4a.cl.h" + #include "gemm_noshuffle_q3_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_q6_k_q8_1_dp4a.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q3_k_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q6_k_q8_1_dp4a", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q3_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q3_k_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_q6_k_q8_1_dp4a_bin (dp4a prefill GEMM) - if (backend_ctx->has_integer_dot) { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q6_k_q8_1_dp4a_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q6_k_q8_1_dp4a_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + // gemv_noshuffle_q3_k_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q3_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q3_k_f32.cl"); +#endif + if (const char * env = getenv("GGML_OPENCL_Q3_K_MV_R")) { + const int rows = atoi(env); + if (rows == 1 || rows == 2 || rows == 4) { + backend_ctx->q3_k_mv_rows = rows; + } + } + if (const char * env = getenv("GGML_OPENCL_Q3_K_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->q3_k_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DQ3_K_MV_R=" + std::to_string(backend_ctx->q3_k_mv_rows) + + " -DQ3_K_MV_NSG=" + std::to_string(backend_ctx->q3_k_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_q3_k_f32", &err); + CL_CHECK(err); + CL_CHECK(clReleaseProgram(prog)); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->q3_k_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_q3_k_f32 = kernel; + break; } + CL_CHECK(clReleaseKernel(kernel)); + GGML_ASSERT(backend_ctx->q3_k_mv_nsg > 1); + backend_ctx->q3_k_mv_nsg /= 2; } + GGML_LOG_CONT("."); } - // gemv_moe_mxfp4_f32_ns + // gemm_noshuffle_q2_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_moe_mxfp4_f32_ns.cl.h" + #include "gemm_noshuffle_q2_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_moe_mxfp4_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q2_k_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_mxfp4_f32_ns", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32_ns_wimg = clCreateKernel(prog, "kernel_gemv_moe_mxfp4_f32_ns_wimg", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_k_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_moe_mxfp4_f32_ns - { + // gemm_noshuffle_q2_k_q8_1_dp4a + if (backend_ctx->has_integer_dot) { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_moe_mxfp4_f32_ns.cl.h" + #include "gemm_noshuffle_q2_k_q8_1_dp4a.cl.h" }; #else - const std::string kernel_src = read_file("gemm_moe_mxfp4_f32_ns.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q2_k_q8_1_dp4a.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_f32_ns", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts + " -DTILESIZE_N=8"); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q2_k_q8_1_dp4a_narrow = clCreateKernel(prog, "kernel_gemm_noshuffle_q2_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // gemm_moe_mxfp4_f32_ns_bin - { - size_t bin_size = 0; - backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin = nullptr; - - if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_mxfp4_f32_ns_ila", &bin_size); - if (kernel_bin && bin_size > 0) { - cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - - CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_f32_ns_ila", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); - } - } - } - - // moe_reorder_b + // gemv_noshuffle_q2_k_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "moe_reorder_b.cl.h" + #include "gemv_noshuffle_q2_k_f32.cl.h" }; #else - const std::string kernel_src = read_file("moe_reorder_b.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_q2_k_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_moe_reorder_b = clCreateKernel(prog, "kernel_moe_reorder_b", &err), err)); - CL_CHECK(clReleaseProgram(prog)); + if (const char * env = getenv("GGML_OPENCL_Q2_K_MV_R")) { + const int rows = atoi(env); + if (rows == 1 || rows == 2 || rows == 4) { + backend_ctx->q2_k_mv_rows = rows; + } + } + if (const char * env = getenv("GGML_OPENCL_Q2_K_MV_NSG")) { + const int nsg = atoi(env); + if (nsg == 1 || nsg == 2 || nsg == 4 || nsg == 8) { + backend_ctx->q2_k_mv_nsg = nsg; + } + } + for (;;) { + const std::string opts = compile_opts + " -DQ2_K_MV_R=" + std::to_string(backend_ctx->q2_k_mv_rows) + + " -DQ2_K_MV_NSG=" + std::to_string(backend_ctx->q2_k_mv_nsg); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + cl_kernel kernel = clCreateKernel(prog, "kernel_gemv_noshuffle_q2_k_f32", &err); + CL_CHECK(err); + CL_CHECK(clReleaseProgram(prog)); + size_t max_workgroup; + CL_CHECK(clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(max_workgroup), &max_workgroup, nullptr)); + if (64*(size_t)backend_ctx->q2_k_mv_nsg <= max_workgroup) { + backend_ctx->kernel_gemv_noshuffle_q2_k_f32 = kernel; + break; + } + CL_CHECK(clReleaseKernel(kernel)); + GGML_ASSERT(backend_ctx->q2_k_mv_nsg > 1); + backend_ctx->q2_k_mv_nsg /= 2; + } GGML_LOG_CONT("."); } - // moe_sort_by_expert + // gemv_noshuffle_general { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X) { + CL_gemv_compile_opts += " -DGGML_CL_A6X_CONSTFOLD_FIX"; + } + #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "moe_sort_by_expert.cl.h" + const std::string kernel_src_CL_gemv_general { + #include "gemv_noshuffle_q4_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("moe_sort_by_expert.cl"); + const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q4_0_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - CL_CHECK((backend_ctx->kernel_moe_histogram = clCreateKernel(prog, "kernel_moe_histogram", &err), err)); - CL_CHECK((backend_ctx->kernel_moe_scan = clCreateKernel(prog, "kernel_moe_scan", &err), err)); - CL_CHECK((backend_ctx->kernel_moe_fill = clCreateKernel(prog, "kernel_moe_fill", &err), err)); - CL_CHECK((backend_ctx->kernel_moe_scatter = clCreateKernel(prog, "kernel_moe_scatter", &err), err)); - CL_CHECK((backend_ctx->kernel_moe_scatter_stable = clCreateKernel(prog, "kernel_moe_scatter_stable", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32_mc3", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q6_k_f32 + // gemv_noshuffle { + // Gemv 2048, 16384 + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DLINE_STRIDE_A=2048 " + " -DBLOCK_STRIDE_A=16384 " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q6_k_f32.cl.h" + const std::string kernel_src_CL_gemv { + #include "gemv_noshuffle_q4_0_f32_spec.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32.cl"); + const std::string kernel_src_CL_gemv = read_file("gemv_noshuffle_q4_0_f32_spec.cl"); #endif - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; + cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + + // Gemv 2048, 16384 + CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DLINE_STRIDE_A=2048 " + " -DBLOCK_STRIDE_A=16384 " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; } - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_11008 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_mc3", &err), err)); - if (getenv("GGML_OPENCL_MC3_PROBE")) { - cl_ulong pm6 = 0, pm4 = 0; size_t wg6 = 0, wg4 = 0, mult = 0; - clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, sizeof(pm6), &pm6, NULL); - clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(wg6), &wg6, NULL); - clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, sizeof(pm4), &pm4, NULL); - clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(wg4), &wg4, NULL); - clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE, sizeof(mult), &mult, NULL); - fprintf(stderr, "[MC3-PROBE] q4K_mc3 private=%llu wg_cap=%zu | q6K_mc3 private=%llu wg_cap=%zu | pref_mult=%zu\n", - (unsigned long long)pm4, wg4, (unsigned long long)pm6, wg6, mult); - fflush(stderr); + // Gemv 5504, 44032 + CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DLINE_STRIDE_A=5504 " + " -DBLOCK_STRIDE_A=44032 " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; } + + prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_11008_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); - } - // gemv_noshuffle_q6_k_f32_o4 — 4-output-per-WI variant, opt-in via - // GGML_OPENCL_Q6K_GEMV_O4=1 (~3x fewer dispatches on long-vocab lm_head). - { -#ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q6_k_f32_o4.cl.h" - }; -#else - const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_o4.cl"); -#endif + // Gemv 16000, 128000 + CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DLINE_STRIDE_A=16000 " + " -DBLOCK_STRIDE_A=128000 " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); - std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + - " -cl-mad-enable "; if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; } - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_o4", &err), err)); + prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32000_1_4096 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); - - // Global-read variant: weights read from __global coalesced instead of - // image1d_buffer (the texture cache caps the streaming lm_head read - // bandwidth). Opt-in via GGML_OPENCL_Q6K_GEMV_O4_GLOBAL. - cl_program prog_g = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts + " -DQ6K_O4_GLOBAL"); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4_global = - clCreateKernel(prog_g, "kernel_gemv_noshuffle_q6_K_f32_o4_global", &err), err)); - CL_CHECK(clReleaseProgram(prog_g)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q6_k_f32_tiled — tiled-wide canonical layout, default ON - // (opt out: GGML_OPENCL_Q6K_GEMV_TILED=0; separate convert + GEMV; weights via __global). + // mul_mat_Ab_Bi_8x4 { #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemv_noshuffle_q6_k_f32_tiled.cl.h" + const std::string kernel_src_CL_gemm { + #include "gemm_noshuffle_q4_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_tiled.cl"); + const std::string kernel_src_CL_gemm = read_file("gemm_noshuffle_q4_0_f32.cl"); #endif - std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled = - clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_tiled", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled_mc3 = - clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_tiled_mc3", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemm.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_0_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q6_k_f32_tiled — batched (N>1) GEMM over the same tiled-wide - // canonical layout, so batched lm_head/embed stays correct + on GPU. + backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans = nullptr; + backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin = nullptr; + backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin = nullptr; { + { + std::string opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); #ifdef GGML_OPENCL_EMBED_KERNELS - const std::string kernel_src { - #include "gemm_noshuffle_q6_k_f32_tiled.cl.h" - }; + const std::string kernel_src { + #include "gemv_noshuffle_q4_0_f32_32b_trans.cl.h" + }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q6_k_f32_tiled.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_q4_0_f32_32b_trans.cl"); #endif - std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32_tiled = - clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32_tiled", &err), err)); - CL_CHECK(clReleaseProgram(prog)); - GGML_LOG_CONT("."); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans = + clCreateKernel(prog, "kernel_gemv_noshuffle_q4_0_f32_32b_trans", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + if (use_adreno_bin_kernels(backend_ctx)) { + size_t bin_size = 0; + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_0_f32_32b_trans_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); + } + + kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); + } + } } - // gemm_noshuffle_q6_k_f32 + // gemm_noshuffle_q4_1_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q6_k_f32.cl.h" + #include "gemm_noshuffle_q4_1_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q6_k_f32.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q4_1_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32_cok = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32_cok", &err), err)); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_1_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_1_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemv_noshuffle_q5_k_f32 + // gemv_noshuffle_q4_1_f32 { std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; if (backend_ctx->has_vector_subgroup_broadcast) { - CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; } #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemv_noshuffle_q5_k_f32.cl.h" + #include "gemv_noshuffle_q4_1_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemv_noshuffle_q5_k_f32.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_q4_1_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_k_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_k_f32_mc3", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_1_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_1_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_1_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_1_f32_mc3", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // gemm_noshuffle_q5_k_f32 + // gemm_noshuffle_q5_0_f32 { #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "gemm_noshuffle_q5_k_f32.cl.h" + #include "gemm_noshuffle_q5_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("gemm_noshuffle_q5_k_f32.cl"); + const std::string kernel_src = read_file("gemm_noshuffle_q5_0_f32.cl"); #endif cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_k_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_f32", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // repack + // gemm_noshuffle_q5_0_q8_1_dp4a (dp4a dense q5_0 prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q5_0_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q5_0_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_q5_0_f32 { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + #ifdef GGML_OPENCL_EMBED_KERNELS const std::string kernel_src { - #include "flash_attn_repack.cl.h" + #include "gemv_noshuffle_q5_0_f32.cl.h" }; #else - const std::string kernel_src = read_file("flash_attn_repack.cl"); + const std::string kernel_src = read_file("gemv_noshuffle_q5_0_f32.cl"); #endif - cl_program prog = - build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } - CL_CHECK((backend_ctx->fa.kernel_repack_q_for_wmm = clCreateKernel(prog, "kernel_repack_q_for_wmm", &err), err)); - CL_CHECK((backend_ctx->fa.kernel_repack_k_for_wmm = clCreateKernel(prog, "kernel_repack_k_for_wmm", &err), err)); - CL_CHECK((backend_ctx->fa.kernel_repack_v_for_wmm = clCreateKernel(prog, "kernel_repack_v_for_wmm", &err), err)); - CL_CHECK((backend_ctx->fa.kernel_repack_mask_for_wmm = clCreateKernel(prog, "kernel_repack_mask_for_wmm", &err), err)); + // gemm_noshuffle_q5_1_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q5_1_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q5_1_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_1_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_1_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } - // kernel_flash_attn_f32_f16_bin + // gemv_noshuffle_q5_1_f32 + { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q5_1_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q5_1_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_1_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_1_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_iq4_nl_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_iq4_nl_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_iq4_nl_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq4_nl_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_iq4_nl_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_iq4_nl_q8_1_dp4a (dp4a dense IQ4_NL prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_iq4_nl_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_iq4_nl_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_q4_0_q8_1_dp4a (dp4a dense q4_0 prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q4_0_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q4_0_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_0_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_act_vload4 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_0_q8_1_dp4a_act_vload4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_iq4_nl_f32 + { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_iq4_nl_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_iq4_nl_f32.cl"); +#endif + + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_iq4_nl_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_iq4_nl_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // mul_mm_q8_0_f32_8x4 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q8_0_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q8_0_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_q8_0_f32_bin { size_t bin_size = 0; - backend_ctx->fa.kernel_flash_attn_f32_f16_bin = nullptr; + backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin = nullptr; if (use_adreno_bin_kernels(backend_ctx)) { - const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("flash_attn_f32_f16_wmm", &bin_size); + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q8_0_f32_ila", &bin_size); if (kernel_bin && bin_size > 0) { cl_program prog = - build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, compile_opts, bin_size); - CL_CHECK((backend_ctx->fa.kernel_flash_attn_f32_f16_bin = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_f32_ila", &err), err)); CL_CHECK(clReleaseProgram(prog)); GGML_LOG_CONT("."); } } } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS - GGML_LOG_CONT("\n"); - backend_ctx->kernels_loaded = true; -} -static ggml_backend_opencl_context * ggml_cl_init(ggml_backend_dev_t dev); -static bool ggml_opencl_is_device_supported(ggml_backend_dev_t dev); + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin = nullptr; -// FA per-(dk,dv) tile tuning table + GGML_OPENCL_FA_TUNE override parsing. -#include "fa_tune.h" + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, compile_opts, bin_size); -// FA variant key for the per-(dk,dv,variant) lazy compile cache. -// Kernel built on first dispatch to reduce kernel loading time. -// NB - a warmup run is recommended to get all necessary FA variants compiled -// before actual runs. -enum ggml_opencl_fa_variant { - FA_VARIANT_PRE = 0, // prepass kernels (kv_pad, mask_pad, blk) - FA_VARIANT_F16 = 1, - FA_VARIANT_F32 = 2, - FA_VARIANT_F32_F16 = 3, - FA_VARIANT_Q8_0 = 4, - FA_VARIANT_Q4_0 = 5, - FA_VARIANT_F32_F16_SPLIT = 6, - FA_VARIANT_Q8_0_SPLIT = 7, - FA_VARIANT_Q4_0_SPLIT = 8, -}; + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemv_noshuffle_general_q8_0_f32 + { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; + } -static std::string ggml_opencl_fa_kernel_src(ggml_opencl_fa_variant v) { #ifdef GGML_OPENCL_EMBED_KERNELS - switch (v) { - case FA_VARIANT_F16: - return std::string{ - #include "flash_attn_f16.cl.h" - }; - case FA_VARIANT_F32: - return std::string{ - #include "flash_attn_f32.cl.h" - }; - case FA_VARIANT_F32_F16: - case FA_VARIANT_F32_F16_SPLIT: - return std::string{ - #include "flash_attn_f32_f16.cl.h" - }; - case FA_VARIANT_PRE: - return std::string{ - #include "flash_attn_pre_f16.cl.h" - }; - case FA_VARIANT_Q8_0: - case FA_VARIANT_Q8_0_SPLIT: - return std::string{ - #include "flash_attn_f32_q8_0.cl.h" - }; - case FA_VARIANT_Q4_0: - case FA_VARIANT_Q4_0_SPLIT: - return std::string{ - #include "flash_attn_f32_q4_0.cl.h" - }; - } - return {}; + const std::string kernel_src_CL_gemv_general { + #include "gemv_noshuffle_q8_0_f32.cl.h" + }; #else - switch (v) { - case FA_VARIANT_F16: return read_file("flash_attn_f16.cl"); - case FA_VARIANT_F32: return read_file("flash_attn_f32.cl"); - case FA_VARIANT_F32_F16: - case FA_VARIANT_F32_F16_SPLIT: return read_file("flash_attn_f32_f16.cl"); - case FA_VARIANT_PRE: return read_file("flash_attn_pre_f16.cl"); - case FA_VARIANT_Q8_0: - case FA_VARIANT_Q8_0_SPLIT: return read_file("flash_attn_f32_q8_0.cl"); - case FA_VARIANT_Q4_0: - case FA_VARIANT_Q4_0_SPLIT: return read_file("flash_attn_f32_q4_0.cl"); - } - return {}; + const std::string kernel_src_CL_gemv_general = read_file("gemv_noshuffle_q8_0_f32.cl"); #endif -} -static std::string ggml_opencl_fa_compile_opts(ggml_backend_opencl_context * backend_ctx, - const ggml_opencl_fa_dim * cfg, - ggml_opencl_fa_variant variant) { - std::string opts = backend_ctx->kernel_compile_opts + - " -D DK=" + std::to_string(cfg->dk) + - " -D DV=" + std::to_string(cfg->dv) + - " -D BLOCK_M=" + std::to_string(cfg->bm) + - " -D BLOCK_N=" + std::to_string(cfg->bn); + cl_program prog = build_program_from_source(backend_ctx, kernel_src_CL_gemv_general.c_str(), CL_gemv_compile_opts); - if (backend_ctx->gpu_family == INTEL) { - opts += " -D FA_SG=32"; + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q8_0_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q8_0_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk = clCreateKernel(prog, "kernel_gemv_noshuffle_q8_0_f32_splitk", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - const bool is_split = variant == FA_VARIANT_F32_F16_SPLIT || - variant == FA_VARIANT_Q8_0_SPLIT || - variant == FA_VARIANT_Q4_0_SPLIT; - if (is_split) { - opts += " -D N_SPLIT=" + std::to_string(cfg->n_split); - } - // Shuffle define for the split tile paths AND the cluster-parallel decode - // kernel (q1_vec_mq_split_c8) in the plain F32_F16 program. Without it the - // c8 kernel is compiled out (HAS_SUBGROUP_SHUFFLE guard) and dispatch - // falls back to the baseline mq_split. - if ((is_split || variant == FA_VARIANT_F32_F16) && backend_ctx->has_subgroup_shuffle) { - opts += backend_ctx->has_qcom_subgroup_shuffle - ? " -D cl_qcom_subgroup_shuffle=1" - : " -D cl_khr_subgroup_shuffle=1"; - } - // X1E drops the explicit sub-group size pin on the c8 kernels, compiler - // routes the fp16-heavy kernel to a slow variant with explicit subgroup size - if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E) { - opts += " -D FA_C8_NO_SG_PIN"; - } - // Transposed K tile in local memory: the KV rows the QK loop walks together become - // adjacent, so a group of them is ONE 128-bit local read instead of several narrow - // ones. The QK loop is LDS-read-issue-bound (a wrong-math probe that kept every FMA/dp4a - // but removed the LDS reads ran the kernel ~40% faster), so this is worth up to +26% on - // fa=1 prefill. Output is bit-identical -- only the layout moves. - // - // DK <= 128 only. At DK=256 (gemma-3-4b) it measures 1-2% NEGATIVE and reproduces across - // rounds; padding the row stride does not recover it, so the cause is not a simple bank - // conflict and the wider tile does not want this layout. - // - // Default on within that gate; GGML_OPENCL_FA_K_LDS_T=0 restores the row-major tile. + // gemm_noshuffle_q4_k_f32 { - const char * e = getenv("GGML_OPENCL_FA_K_LDS_T"); - if ((e == nullptr || e[0] != '0') && cfg->dk <= 128) { - opts += " -D FA_K_LDS_T"; - } - } - return opts; -} - -// only register when the kernel's required dispatch workgroup size is within -// the limit of the device's maximum workgroup size -static bool ggml_opencl_fa_kernel_fits_wg(ggml_backend_opencl_context * backend_ctx, - cl_kernel kernel, size_t required_wg, - const char * name, int dk, int dv) { - if (kernel == NULL) { return false; } - const size_t dev_max = backend_ctx->max_workgroup_size; - if (dev_max < required_wg) { - GGML_LOG_INFO("ggml_opencl: %s DK=%d DV=%d requires WG %zu > device max %zu; skipping registration (will fall back)\n", - name, dk, dv, required_wg, dev_max); - return false; - } - size_t kwg = 0; - cl_int err = clGetKernelWorkGroupInfo(kernel, backend_ctx->device, - CL_KERNEL_WORK_GROUP_SIZE, - sizeof(kwg), &kwg, NULL); - if (err != CL_SUCCESS) { - GGML_LOG_INFO("ggml_opencl: clGetKernelWorkGroupInfo failed for %s DK=%d DV=%d (err=%d); skipping registration\n", - name, dk, dv, err); - return false; - } - if (kwg < required_wg) { - GGML_LOG_INFO("ggml_opencl: %s DK=%d DV=%d per-kernel max %zu < required %zu; skipping registration (will fall back)\n", - name, dk, dv, kwg, required_wg); - return false; +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q4_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q4_k_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_r1 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_r1", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_kimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_kimg", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_cok = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_f32_cok", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - return true; -} -// Log private memory for an FA kernel. Enable via `GGML_OPENCL_FA_LOG_SPILL=1`. -// On Adreno non-zero private_mem means spilling to global memory due to resource -// constraint and usually causes performance degradation. -// (per-work-item, no cache locality) — a strong signal to pick a config -// with smaller per-thread state (e.g. larger N_SPLIT). -static void ggml_opencl_log_fa_kernel_spill(ggml_backend_opencl_context * backend_ctx, - cl_kernel kernel, const char * name, int dk, int dv) { - static const bool enabled = []{ - const char * e = std::getenv("GGML_OPENCL_FA_LOG_SPILL"); - return e && e[0] && e[0] != '0'; - }(); + // gemm_noshuffle_q4_k_q8_1_dp4a (dp4a dense prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q4_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q4_k_q8_1_dp4a.cl"); +#endif + // X1 uses a smaller N tile to reduce local memory and register use. + int tile_n = (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E) ? 8 : 32; + if (const char * e = getenv("GGML_OPENCL_Q4K_DP4A_TS")) { tile_n = atoi(e); } + GGML_ASSERT(tile_n >= 4 && tile_n <= 64 && tile_n % 4 == 0); + backend_ctx->tile_n_dp4a_q4_k = tile_n; + std::string dp4a_opts = compile_opts + " -DTILESIZE_N=" + std::to_string(tile_n); + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), dp4a_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_act_vload4 = clCreateKernel(prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_act_vload4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); - if (!enabled || kernel == nullptr) { - return; + // Compile a smaller N tile to avoid unused columns in small batches. + int tile_n_narrow = MIN(tile_n, 16); + if (const char * e = getenv("GGML_OPENCL_Q4_K_DP4A_TS_NARROW")) { tile_n_narrow = atoi(e); } + GGML_ASSERT(tile_n_narrow >= 4 && tile_n_narrow <= 64 && tile_n_narrow % 4 == 0); + if (const char * e = getenv("GGML_OPENCL_Q4_K_DP4A_NARROW_MAX")) { + backend_ctx->max_n_dp4a_narrow_q4_k = atoi(e); + } + backend_ctx->tile_n_dp4a_narrow_q4_k = tile_n_narrow; + if (tile_n_narrow != tile_n) { + std::string narrow_opts = compile_opts + " -DTILESIZE_N=" + std::to_string(tile_n_narrow); + cl_program narrow_prog = build_program_from_source(backend_ctx, kernel_src.c_str(), narrow_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow = clCreateKernel(narrow_prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow_wimg = clCreateKernel(narrow_prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg", &err), err)); + CL_CHECK(clReleaseProgram(narrow_prog)); + } + GGML_LOG_CONT("."); } - cl_ulong priv_mem = 0; - if (clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, - sizeof(priv_mem), &priv_mem, NULL) == CL_SUCCESS) { - const char * tag = priv_mem > 0 ? "SPILL" : "ok"; - GGML_LOG_INFO("ggml_opencl: [%s] %s DK=%d DV=%d private_mem=%llu bytes\n", - tag, name, dk, dv, (unsigned long long) priv_mem); + // gemm_noshuffle_q8_0_q8_1_dp4a (dp4a dense q8_0 prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q8_0_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q8_0_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_act_vload4 = clCreateKernel(prog, "kernel_gemm_noshuffle_q8_0_q8_1_dp4a_act_vload4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } -} -static void ggml_opencl_ensure_fa_pre_kernels(ggml_backend_opencl_context * backend_ctx, int dk, int dv) { - const std::pair dk_dv = {dk, dv}; + // gemm_noshuffle_q5_k_q8_1_dp4a (dp4a dense prefill GEMM for q5_K) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q5_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q5_k_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_k_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_act_vload4 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_k_q8_1_dp4a_act_vload4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == dk && d.dv == dv) { - cfg = &d; break; - } + // gemm_noshuffle_q6_k_q8_1_dp4a (dp4a dense prefill GEMM for q6_K ffn_down/output) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q6_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q6_k_q8_1_dp4a.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_k_q8_1_dp4a", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_act_vload4 = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_k_q8_1_dp4a_act_vload4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - if (cfg == nullptr) { - GGML_ABORT("ggml_opencl: no flash_attn config for DK=%d DV=%d", dk, dv); + // quant_a_q8_1 (plain activation q8_1 pre-pass for the dense dp4a GEMM) + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "quant_a_q8_1.cl.h" + }; +#else + const std::string kernel_src = read_file("quant_a_q8_1.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_quant_a_q8_1 = clCreateKernel(prog, "kernel_quant_a_q8_1", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // BM-tile metadata is consumed by the prefill dispatch (n_q_blocks / wg - // sizing) regardless of whether the prepass kernels are needed for this - // n_kv — set it unconditionally - backend_ctx->fa.f32_f16_bm[{dk, dv}] = cfg->bm; - backend_ctx->fa.f32_f16_bn[{dk, dv}] = cfg->bn; - backend_ctx->fa.f32_f16_wg_size[{dk, dv}] = cfg->bm; - backend_ctx->fa.bm[{dk, dv}] = cfg->bm; - backend_ctx->fa.bn[{dk, dv}] = cfg->bn; + // gemv_noshuffle_q4_k_f32 + { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X) { + CL_gemv_compile_opts += " -DGGML_CL_A6X_CONSTFOLD_FIX"; + } + // Opt-in: dequant-once-per-block mc3 verify GEMV (factors q4_K dequant + // out of the 3-column loop; byte-identical, lower spill). A/B vs the + // shipped inline mc3 in the same binary. + if (getenv("GGML_OPENCL_Q4K_MC3_DQ")) { + CL_gemv_compile_opts += " -DQ4K_MC3_DEQUANT_ONCE "; + } + // Opt-in: LDS-staged dequant mc3 verify GEMV (stages the dequantized + // q4_K weights in __local instead of private regs that spill to slow + // global on Adreno; byte-identical). A/B vs inline + dequant-once. + if (getenv("GGML_OPENCL_Q4K_MC3_LDS")) { + CL_gemv_compile_opts += " -DQ4K_MC3_DEQUANT_LDS "; + } - if (backend_ctx->fa.kv_pad_f16.count(dk_dv) > 0) { return; } +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q4_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32.cl"); +#endif - GGML_LOG_INFO("ggml_opencl: lazy-compiling flash_attn prepass for DK=%d DV=%d\n", dk, dv); - cl_int err; - const std::string src = ggml_opencl_fa_kernel_src(FA_VARIANT_PRE); - const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_PRE); - // retry when kernel compile fails - cl_program prog_pre_f16 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts, - /*fatal=*/false, "fa prepass f16", backend_ctx->queue); - if (!prog_pre_f16) { return; } - cl_kernel k_kv_pad_f16 = clCreateKernel(prog_pre_f16, "flash_attn_kv_pad_f16", &err); - if (err != CL_SUCCESS) { clReleaseProgram(prog_pre_f16); return; } - cl_kernel k_mask_pad_f16 = clCreateKernel(prog_pre_f16, "flash_attn_mask_pad_f16", &err); - if (err != CL_SUCCESS) { clReleaseKernel(k_kv_pad_f16); clReleaseProgram(prog_pre_f16); return; } - cl_kernel k_blk_f16 = clCreateKernel(prog_pre_f16, "flash_attn_blk_f16", &err); - if (err != CL_SUCCESS) { clReleaseKernel(k_kv_pad_f16); clReleaseKernel(k_mask_pad_f16); clReleaseProgram(prog_pre_f16); return; } - backend_ctx->fa.kv_pad_f16[{dk, dv}] = k_kv_pad_f16; - backend_ctx->fa.mask_pad_f16[{dk, dv}] = k_mask_pad_f16; - backend_ctx->fa.blk_f16[{dk, dv}] = k_blk_f16; - clReleaseProgram(prog_pre_f16); -} + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); -static bool ggml_opencl_ensure_fa_f32_f16_vec_512(ggml_backend_opencl_context * backend_ctx) { - const std::pair key = {512, 512}; - auto & fa = backend_ctx->fa; - if (fa.f32_f16_q1_vec.count(key) > 0) { - return true; - } - if (fa.f32_f16_vec_512_attempted || backend_ctx->kernel_compile_opts.empty()) { - return false; + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_mc3", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_splitk = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_splitk", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_splitk_reduce_f32 = clCreateKernel(prog, "kernel_gemv_splitk_reduce_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_glu = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_glu", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - fa.f32_f16_vec_512_attempted = true; - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == 512 && d.dv == 512) { - cfg = &d; - break; + // gemv_noshuffle_q4_k_f32_o4 — 4-output-per-WI variant for the long-vocab + // q4_K lm_head/embed GEMV (shares one activation read across 4 output rows). + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q4_k_f32_o4.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_o4.cl"); +#endif + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; } - } - if (cfg == nullptr) { - return false; + cl_program prog = build_program_from_source( + backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_o4 = clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_o4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // Compile only vec decode and merge to stay within the Adreno compiler's memory limit. - const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_F32_F16) + - " -D FA_DECODE_ONLY -D FA_VEC_ONLY"; - cl_program prog = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, - ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts, - /*fatal=*/false, "fa f32_f16 decode512 vec", backend_ctx->queue); - if (!prog) { - return false; - } - cl_int err; - cl_kernel vec = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec", &err); - if (err != CL_SUCCESS) { - clReleaseProgram(prog); - return false; - } - cl_kernel merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); - clReleaseProgram(prog); - if (err != CL_SUCCESS) { - clReleaseKernel(vec); - return false; - } - if (!ggml_opencl_fa_kernel_fits_wg(backend_ctx, vec, 256, "flash_attn_f32_f16_q1_vec", 512, 512) || - !ggml_opencl_fa_kernel_fits_wg(backend_ctx, merge, 128, "flash_attn_f32_merge", 512, 512)) { - clReleaseKernel(vec); - clReleaseKernel(merge); - return false; - } - fa.f32_f16_q1_vec[key] = vec; - if (fa.f32_merge.count(key) > 0) { - clReleaseKernel(merge); - } else { - fa.f32_merge[key] = merge; + // gemv_noshuffle_q4_k_f32_tiled — tiled-wide canonical layout, default ON + // (opt out: GGML_OPENCL_Q4K_GEMV_TILED=0; separate convert + GEMV; weights via __global). + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q4_k_f32_tiled.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_tiled.cl"); +#endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_tiled = + clCreateKernel(prog, "kernel_gemv_noshuffle_q4_k_f32_tiled", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - return true; -} -static void ggml_opencl_ensure_fa_f32_f16_mq_decode(ggml_backend_opencl_context * backend_ctx, int dk, int dv, int gqa) { - const std::tuple key = {dk, dv, gqa}; - auto & fa = backend_ctx->fa; - if (fa.f32_f16_mq_decode.count(key) > 0 || fa.f32_f16_mq_decode_attempted.count(key) > 0 || - backend_ctx->kernel_compile_opts.empty()) { - return; - } - if (gqa == 4 && dk != 128 && fa.f32_f16_q1_vec_mq_split.count({dk, dv}) > 0) { - fa.f32_f16_mq_decode[key] = fa.f32_f16_q1_vec_mq_split.at({dk, dv}); - fa.f32_f16_mq_decode_wg[key] = 256; - fa.f32_f16_mq_decode_hs[key] = 1; - return; - } - fa.f32_f16_mq_decode_attempted.insert(key); - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == dk && d.dv == dv) { - cfg = &d; - break; - } - } - if (cfg == nullptr) { - return; + // gemm_noshuffle_q4_K_f32_tiled_dp4a + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q4_K_f32_tiled_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q4_K_f32_tiled_dp4a.cl"); +#endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_K_f32_tiled_dp4a = + clCreateKernel(prog, "kernel_gemm_noshuffle_q4_K_f32_tiled_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - const bool cluster = dk == 64 || dk == 128; - const int head_sub = cluster ? 2 : (gqa == 8 ? (dk == 512 ? 4 : 2) : 1); - const int nsg_max = dk == 64 ? 1 : (dk == 128 || (gqa == 8 && dk == 256) ? 2 : 4); - const char * kernel_name = cluster ? "flash_attn_f32_f16_q1_vec_mq_split_c8" : "flash_attn_f32_f16_q1_vec_mq_split"; - const std::string src = ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16); - const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_F32_F16) + - " -D FA_MQ_ONLY -D MQ_GQA=" + std::to_string(gqa / head_sub) + - " -D FA_HEAD_SUB=" + std::to_string(head_sub) + - (cluster ? " -D MQ_NSG=" + std::to_string(nsg_max) + " -D FA_CL_C=16" : " -D FA_MQ_SPLIT_ONLY") + - (dk == 64 ? " -D FA_CL_MHRED -D FA_CL_MASK_BCAST" : "") + - (gqa == 8 && dk == 256 ? " -D FA_Q1_Q_REG" : ""); - for (int nsg = nsg_max; nsg >= 1; nsg /= 2) { - const size_t wg = 64 * nsg; - cl_program prog = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), - opts + " -D MQ_NSG_SPLIT=" + std::to_string(nsg), - /*fatal=*/false, "fa f32_f16 mq decode", backend_ctx->queue); - if (!prog) { - continue; - } - cl_int err; - cl_kernel kernel = clCreateKernel(prog, kernel_name, &err); - clReleaseProgram(prog); - if (err != CL_SUCCESS) { - continue; - } - if (!ggml_opencl_fa_kernel_fits_wg(backend_ctx, kernel, wg, kernel_name, dk, dv)) { - clReleaseKernel(kernel); - continue; + backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans = nullptr; + backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin = nullptr; + backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin = nullptr; + { + if (backend_ctx->has_vector_subgroup_broadcast) { + std::string opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q4_k_f32_32b_trans.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_32b_trans.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans = + clCreateKernel(prog, "gemv_noshuffle_q4_k_f32_32b_trans", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - fa.f32_f16_mq_decode[key] = kernel; - fa.f32_f16_mq_decode_wg[key] = wg; - fa.f32_f16_mq_decode_hs[key] = head_sub; - return; - } -} -// DK=512 prefill BM-tile -static bool ggml_opencl_ensure_fa_f32_f16_prefill_512(ggml_backend_opencl_context * backend_ctx, bool split) { - const int dk = 512, dv = 512; - const std::pair dk_dv = {dk, dv}; - auto & target = split ? backend_ctx->fa.f32_f16_split : backend_ctx->fa.f32_f16; - if (target.count(dk_dv) > 0) { return true; } - - static bool failed[2] = { false, false }; - if (failed[split ? 1 : 0]) { return false; } + if (use_adreno_bin_kernels(backend_ctx)) { + size_t bin_size = 0; + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == dk && d.dv == dv) { cfg = &d; break; } - } - if (cfg == nullptr) { failed[split ? 1 : 0] = true; return false; } - if (split && cfg->n_split <= 1) { failed[1] = true; return false; } + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); + } - const ggml_opencl_fa_variant variant = split ? FA_VARIANT_F32_F16_SPLIT : FA_VARIANT_F32_F16; - std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant) + " -D FA_PREFILL_ONLY"; - cl_program prog = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, - ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts, - /*fatal=*/false, split ? "fa f32_f16 prefill512 split" : "fa f32_f16 prefill512", - backend_ctx->queue); - if (!prog) { failed[split ? 1 : 0] = true; return false; } + kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - cl_int err; - cl_kernel k = clCreateKernel(prog, "flash_attn_f32_f16", &err); - if (err != CL_SUCCESS) { clReleaseProgram(prog); failed[split ? 1 : 0] = true; return false; } - target[dk_dv] = k; - if (split) { - backend_ctx->fa.f32_f16_split_wg_size[dk_dv] = cfg->bm * cfg->n_split; - backend_ctx->fa.f32_f16_split_nkv_threshold[dk_dv] = cfg->nkv_split_threshold; + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); + } + } } - ggml_opencl_log_fa_kernel_spill(backend_ctx, k, - split ? "flash_attn_f32_f16 (prefill512 split)" : "flash_attn_f32_f16 (prefill512)", dk, dv); - clReleaseProgram(prog); - // determine whether to use the K-image variant of the split tile - static const char * pkimg_build_env = getenv("GGML_OPENCL_FA_PREFILL_K_IMG"); - const bool pkimg_build = (pkimg_build_env != NULL) && (pkimg_build_env[0] != '0'); - if (split && pkimg_build && backend_ctx->fa.f32_f16_split_k_img.count(dk_dv) == 0) { - std::string opts_img = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant) + - " -D FA_PREFILL_ONLY -D FA_K_IMG -D FA_TILE_NAME=flash_attn_f32_f16_k_img"; - cl_program prog_img = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, - ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts_img, - /*fatal=*/false, "fa f32_f16 prefill512 split k_img", backend_ctx->queue); - if (prog_img) { - cl_int err_img; - cl_kernel k_img = clCreateKernel(prog_img, "flash_attn_f32_f16_k_img", &err_img); - if (err_img == CL_SUCCESS) { - backend_ctx->fa.f32_f16_split_k_img[dk_dv] = k_img; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_img, - "flash_attn_f32_f16 (prefill512 split k_img)", dk, dv); - } - clReleaseProgram(prog_img); + backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans = nullptr; + backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin = nullptr; + backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin = nullptr; + { + if (backend_ctx->has_vector_subgroup_broadcast) { + std::string opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q6_k_f32_32b_trans.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_32b_trans.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans = + clCreateKernel(prog, "kernel_gemv_noshuffle_q6_k_f32_32b_trans", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - } - return true; -} - -// Compile one (variant, dk, dv); memoised. false = compiler rejected. -static bool ggml_opencl_ensure_fa_variant(ggml_backend_opencl_context * backend_ctx, int dk, int dv, ggml_opencl_fa_variant variant) { - const std::pair dk_dv = {dk, dv}; - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == dk && d.dv == dv) { - cfg = &d; break; - } - } - if (cfg == nullptr) { - return false; - } + if (use_adreno_bin_kernels(backend_ctx)) { + size_t bin_size = 0; + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q6_k_f32_32b_trans_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); - // if a variant has already been compiled - switch (variant) { - case FA_VARIANT_F16: { - if (backend_ctx->fa.f16.count(dk_dv)) { - return true; - } - break; - } - case FA_VARIANT_F32: { - if (backend_ctx->fa.f32.count(dk_dv)) { - return true; - } - break; - } - case FA_VARIANT_F32_F16: { - // The DK=512 decode-only program does not create the f32_f16 - // prefill kernel; check the q1 kernel instead so that repeated - // calls return a consistent result. - const bool decode_only = (dk == 512); - if (decode_only ? (backend_ctx->fa.f32_f16_q1.count(dk_dv) > 0) - : (backend_ctx->fa.f32_f16.count(dk_dv) > 0)) { - return true; - } - break; - } - case FA_VARIANT_Q8_0: { - if (backend_ctx->fa.f32_q8_0.count(dk_dv)) { - return true; + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); } - break; - } - case FA_VARIANT_Q4_0: { - if (backend_ctx->fa.f32_q4_0.count(dk_dv)) { - return true; + + kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); } - break; } - case FA_VARIANT_F32_F16_SPLIT: { - if (backend_ctx->fa.f32_f16_split.count(dk_dv)) { - return true; - } - break; + } + + backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans = nullptr; + backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin = nullptr; + backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin = nullptr; + { + if (backend_ctx->has_vector_subgroup_broadcast) { + std::string opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -DSIMDGROUP_WIDTH=" + + std::to_string(backend_ctx->adreno_wave_size); +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q5_k_f32_32b_trans.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q5_k_f32_32b_trans.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans = + clCreateKernel(prog, "gemv_noshuffle_q5_k_f32_32b_trans", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - case FA_VARIANT_Q8_0_SPLIT: { - if (backend_ctx->fa.f32_q8_0_split.count(dk_dv)) { - return true; + + if (use_adreno_bin_kernels(backend_ctx)) { + size_t bin_size = 0; + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q5_k_f32_32b_trans_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); } - break; - } - case FA_VARIANT_Q4_0_SPLIT: { - if (backend_ctx->fa.f32_q4_0_split.count(dk_dv)) { - return true; + + kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program bin_prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin = + clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8", &err), err)); + CL_CHECK(clReleaseProgram(bin_prog)); + GGML_LOG_CONT("."); } - break; - } - case FA_VARIANT_PRE: { - ggml_opencl_ensure_fa_pre_kernels(backend_ctx, dk, dv); - return true; } } - // not registered but attempted - meaning these kernels failed to compile - const auto attempt_key = std::make_pair(variant, dk_dv); - if (backend_ctx->fa.variant_attempted.count(attempt_key)) { - return false; - } - backend_ctx->fa.variant_attempted.insert(attempt_key); + std::string CL_moe_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable " + " -cl-fast-relaxed-math"; - const bool is_split = variant == FA_VARIANT_F32_F16_SPLIT || - variant == FA_VARIANT_Q8_0_SPLIT || - variant == FA_VARIANT_Q4_0_SPLIT; - const bool is_quant = variant == FA_VARIANT_Q8_0 || variant == FA_VARIANT_Q8_0_SPLIT || - variant == FA_VARIANT_Q4_0 || variant == FA_VARIANT_Q4_0_SPLIT; - if (is_quant && (dk % 32 != 0 || dv % 32 != 0)) { - return false; - } - if (is_split && cfg->n_split <= 1) { - return false; - } - if ((variant == FA_VARIANT_Q8_0_SPLIT || variant == FA_VARIANT_Q4_0_SPLIT) && - ((dk / 32) % cfg->n_split != 0 || (dv / 4) % cfg->n_split != 0)) { - return false; + // gemv_moe_q4_1_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q4_1_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q4_1_f32_ns.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q4_1_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_1_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - const std::string src = ggml_opencl_fa_kernel_src(variant); - if (src.empty()) { return false; } - std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant); + // gemm_moe_q4_1_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q4_1_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q4_1_f32_ns.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); - // bypass kernels for DK=512 - const bool fa_decode_only = (variant == FA_VARIANT_F32_F16 && dk == 512); - if (fa_decode_only) { - opts += " -D FA_DECODE_ONLY -D FA_DECODE_MINIMAL"; + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_1_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_1_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // c8 cluster width (GGML_OPENCL_FA_CL_C overrides): value = GQA4 cluster - // width (kernel default 8); the g8 programs use 2x the value (default 16). - // Wider clusters halve per-lane o_acc at the cost of position streams per - // subgroup - static const int fa_cl_c_env = []{ - const char * e = std::getenv("GGML_OPENCL_FA_CL_C"); - const int x = (e && e[0]) ? atoi(e) : 0; - return (x == 8 || x == 16 || x == 32) ? x : 0; // 0 = per-gen default - }(); - // X2E needs 16 to keep per-lane o_acc at 128B (the compiler spills the - // kernel-default width); X1E does not spill, but C=16 is still a measured - // +28-30% DK128-GQA4 decode win there (X1-85, kv 4096/8192), neutral on - // DK64 / GQA1 / quant-KV. - const int fa_cl_c_gqa4 = fa_cl_c_env ? fa_cl_c_env - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || - backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E ? 16 : 0); - const std::string opts_cl_c_gqa4 = fa_cl_c_gqa4 - ? " -D FA_CL_C=" + std::to_string(fa_cl_c_gqa4) : std::string(); - const std::string fa_cl_c_g8_val = std::to_string(fa_cl_c_gqa4 ? fa_cl_c_gqa4 * 2 : 16); + // gemm_moe_q4_1_f32_ns_bin + { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q4_1_f32_ns_bin = nullptr; - const char * tag = nullptr; - switch (variant) { - case FA_VARIANT_F16: tag = "fa f16"; break; - case FA_VARIANT_F32: tag = "fa f32"; break; - case FA_VARIANT_F32_F16: tag = "fa f32_f16"; break; - case FA_VARIANT_Q8_0: tag = "fa q8_0"; break; - case FA_VARIANT_Q4_0: tag = "fa q4_0"; break; - case FA_VARIANT_F32_F16_SPLIT: tag = "fa f32_f16 split"; break; - case FA_VARIANT_Q8_0_SPLIT: tag = "fa q8_0 split"; break; - case FA_VARIANT_Q4_0_SPLIT: tag = "fa q4_0 split"; break; - default: break; - } - cl_program prog = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts + opts_cl_c_gqa4, - /*fatal=*/false, tag, backend_ctx->queue); - if (!prog) { return false; } + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_1_f32_ns_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); - cl_int err; - switch (variant) { - case FA_VARIANT_F16: { - cl_kernel k, kq1; - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f16", &err), err)); - CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f16_q1", &err), err)); - backend_ctx->fa.f16[{dk, dv}] = k; - backend_ctx->fa.f16_q1[{dk, dv}] = kq1; - break; - } - case FA_VARIANT_F32: { - cl_kernel k, kq1; - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32", &err), err)); - CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f32_q1", &err), err)); - backend_ctx->fa.f32[{dk, dv}] = k; - backend_ctx->fa.f32_q1[{dk, dv}] = kq1; - break; - } - case FA_VARIANT_F32_F16: { - cl_kernel kq1; - // BM-tile prefill kernel is excluded from the decode-only (DK=512) - if (!fa_decode_only) { - cl_kernel k; - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); - backend_ctx->fa.f32_f16[{dk, dv}] = k; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k, "flash_attn_f32_f16", dk, dv); - } - CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f32_f16_q1", &err), err)); - backend_ctx->fa.f32_f16_q1[{dk, dv}] = kq1; - ggml_opencl_log_fa_kernel_spill(backend_ctx, kq1, "flash_attn_f32_f16_q1", dk, dv); - cl_kernel k_split = clCreateKernel(prog, "flash_attn_f32_f16_q1_split", &err); - if (err == CL_SUCCESS) { - backend_ctx->fa.f32_f16_q1_split[{dk, dv}] = k_split; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_split, "flash_attn_f32_f16_q1_split", dk, dv); - } - // q1_vec decode kernel (DV-split + subgroup reduce) - cl_kernel k_q1_vec = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec, 256, - "flash_attn_f32_f16_q1_vec", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec[{dk, dv}] = k_q1_vec; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec, "flash_attn_f32_f16_q1_vec", dk, dv); - } else { - clReleaseKernel(k_q1_vec); - } - } - // KV-head-coalesced vec for high-GQA small models - cl_kernel k_q1_vec_mq = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq, 256, - "flash_attn_f32_f16_q1_vec_mq", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq[{dk, dv}] = k_q1_vec_mq; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq, "flash_attn_f32_f16_q1_vec_mq", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq); - } - } - // KV-head-coalesced + flash-decoding split, reuses merge kernel - cl_kernel k_q1_vec_mq_split = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split, 256, - "flash_attn_f32_f16_q1_vec_mq_split", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split[{dk, dv}] = k_q1_vec_mq_split; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split, "flash_attn_f32_f16_q1_vec_mq_split", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split); - } - } - // K-image variant of MQ_GQA=4 split - cl_kernel k_q1_vec_mq_split_k_img = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split_k_img", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_k_img, 256, - "flash_attn_f32_f16_q1_vec_mq_split_k_img", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img[{dk, dv}] = k_q1_vec_mq_split_k_img; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_k_img, "flash_attn_f32_f16_q1_vec_mq_split_k_img", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split_k_img); - } - } - // Cluster-parallel decode variant - cl_kernel k_q1_vec_mq_split_c8 = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_c8, 256, - "flash_attn_f32_f16_q1_vec_mq_split_c8", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_c8[{dk, dv}] = k_q1_vec_mq_split_c8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split_c8); - } - } - cl_kernel k_merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); - if (err == CL_SUCCESS) { - backend_ctx->fa.f32_merge[{dk, dv}] = k_merge; + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_1_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_1_f32_ns_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // local-tile decode variant - if (dk == 128 && dv == 128) { - cl_kernel k_lt = clCreateKernel(prog, "flash_attn_f32_f16_q1_local_tile", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lt, 128, - "flash_attn_f32_f16_q1_local_tile", dk, dv)) { - backend_ctx->fa.f32_f16_q1_local_tile[{dk, dv}] = k_lt; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lt, "flash_attn_f32_f16_q1_local_tile", dk, dv); - } else { - clReleaseKernel(k_lt); - } - } - // hybrid local-tile + MQ + FD-split - cl_kernel k_lmq = clCreateKernel(prog, "flash_attn_f32_f16_q1_local_mq_split", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lmq, 64, - "flash_attn_f32_f16_q1_local_mq_split", dk, dv)) { - backend_ctx->fa.f32_f16_q1_local_mq_split[{dk, dv}] = k_lmq; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lmq, "flash_attn_f32_f16_q1_local_mq_split", dk, dv); - } else { - clReleaseKernel(k_lmq); - } - } + } + } + + // gemv_moe_mxfp4_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_mxfp4_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_mxfp4_f32.cl"); +#endif + backend_ctx->program_gemv_moe_mxfp4_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32 = clCreateKernel(backend_ctx->program_gemv_moe_mxfp4_f32, "kernel_gemv_moe_mxfp4_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // gemm_moe_mxfp4_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_mxfp4_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_mxfp4_f32.cl"); +#endif + backend_ctx->program_gemm_moe_mxfp4_f32 = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32 = clCreateKernel(backend_ctx->program_gemm_moe_mxfp4_f32, "kernel_gemm_moe_mxfp4_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q4_0_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q4_0_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q4_0_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q4_0_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_0_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_0_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q4_0_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q4_0_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_0_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_0_f32_ns_bin + { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q4_0_f32_ns_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_0_f32_ns_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_0_f32_ns_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } + } + } - // second compile of the same source with -DMQ_GQA=8. - // FA_MQ_ONLY keeps only the vec_mq kernels so that the program - // compiles within the Adreno compiler's memory budget at DK>=256. - // FA_CL_C for the g8 program: MQ_GQA=8 doubles the c8 kernel's - // per-lane o_acc, so widen the cluster to keep the register - // footprint inside the 192-thread WG cap (see fa_cl_c_gqa4 above - // for the per-gen default). - const std::string opts_g8 = opts + " -D MQ_GQA=8 -D MQ_NSG=3 -D MQ_NSG_SPLIT=3 -D FA_MQ_ONLY -D FA_CL_C=" + fa_cl_c_g8_val; - cl_program prog_g8 = fa_decode_only ? nullptr : build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8, - /*fatal=*/false, "fa f32_f16 MQ_GQA=8", backend_ctx->queue); - if (prog_g8) { - const size_t mq_g8_required_wg = 192; // Q1_WG_SIZE(64) * MQ_NSG_SPLIT(3) - cl_kernel k_q1_vec_mq_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_g8, mq_g8_required_wg, - "flash_attn_f32_f16_q1_vec_mq (g8)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_g8[{dk, dv}] = k_q1_vec_mq_g8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_g8, "flash_attn_f32_f16_q1_vec_mq_g8", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_g8); - } - } - cl_kernel k_q1_vec_mq_split_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8, mq_g8_required_wg, - "flash_attn_f32_f16_q1_vec_mq_split (g8)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8[{dk, dv}] = k_q1_vec_mq_split_g8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8, "flash_attn_f32_f16_q1_vec_mq_split_g8", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split_g8); - } - } - // K-image variant - cl_kernel k_q1_vec_mq_split_g8_k_img = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split_k_img", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8_k_img, mq_g8_required_wg, - "flash_attn_f32_f16_q1_vec_mq_split_k_img (g8)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img[{dk, dv}] = k_q1_vec_mq_split_g8_k_img; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8_k_img, "flash_attn_f32_f16_q1_vec_mq_split_g8_k_img", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split_g8_k_img); - } - } - // Cluster-parallel decode, MQ_GQA=8 / FA_CL_C=16 specialization - cl_kernel k_q1_vec_mq_split_g8_c8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8_c8, mq_g8_required_wg, - "flash_attn_f32_f16_q1_vec_mq_split_c8 (g8)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8[{dk, dv}] = k_q1_vec_mq_split_g8_c8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8_c8, "flash_attn_f32_f16_q1_vec_mq_split_g8_c8", dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split_g8_c8); - } - } - // hybrid local-tile + MQ_GQA=8 - if (dk == 128 && dv == 128) { - cl_kernel k_lmq_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_local_mq_split", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lmq_g8, 64, - "flash_attn_f32_f16_q1_local_mq_split (g8)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_local_mq_split_g8[{dk, dv}] = k_lmq_g8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lmq_g8, "flash_attn_f32_f16_q1_local_mq_split_g8", dk, dv); - } else { - clReleaseKernel(k_lmq_g8); - } - } - } - clReleaseProgram(prog_g8); - } - // NSG_SPLIT=2 programs for the cluster-parallel kernel: its register - // footprint caps the per-kernel WG at 128 on X2 (< the stock 256/192 - // requirement), so it can never register from the stock programs. - // With FA_CL_NCL position streams per subgroup, 2 subgroups still - // carry 16 in-flight rows per WG (baseline WG has 4). FA_MQ_ONLY - // keeps these compiles minimal; skipped when the stock program c8 - // registered (some other device) or shuffles are absent. - if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && - backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count({dk, dv}) == 0) { - const std::string opts_c8_ns2 = opts + " -D FA_MQ_ONLY -D MQ_GQA=4 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2" + opts_cl_c_gqa4; - cl_program prog_c8 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8_ns2, - /*fatal=*/false, "fa f32_f16 c8 NSG2", backend_ctx->queue); - if (prog_c8) { - cl_kernel k_c8 = clCreateKernel(prog_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); - if (err == CL_SUCCESS) { - // WG = MQ_NSG(2) × Q1_WG_SIZE(=FA_SG): 128 Adreno (64), 64 Intel (32). - const size_t c8_ns2_wg = backend_ctx->gpu_family == INTEL ? 64 : 128; - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8, c8_ns2_wg, - "flash_attn_f32_f16_q1_vec_mq_split_c8 (ns2)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2[{dk, dv}] = k_c8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8_ns2", dk, dv); - } else { - clReleaseKernel(k_c8); - } - } - clReleaseProgram(prog_c8); - } + // gemm_moe_q8_0_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q8_0_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q8_0_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q8_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q8_0_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q5_0_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q5_0_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q5_0_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q5_0_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_0_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q5_0_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q5_0_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q5_0_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q5_0_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_0_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q5_1_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q5_1_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q5_1_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q5_1_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_1_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q5_1_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q5_1_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q5_1_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q5_1_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_1_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q4_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q4_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q4_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q4_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q4_k_f32_ns", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_moe_q4_k_f32_ns_wimg = clCreateKernel(prog, "kernel_gemv_moe_q4_k_f32_ns_wimg", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q4_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q4_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q4_k_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_k_f32_ns_bin + { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q4_k_f32_ns_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_k_f32_ns_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_k_f32_ns_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - // FA_CL_C=32 g8 program for the DK=DV=256 GQA=8 - if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && - dk == 256 && dv == 256) { - const std::string opts_g8_c32 = opts + " -D FA_MQ_ONLY -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2 -D FA_CL_C=32"; - cl_program prog_g8_c32 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8_c32, - /*fatal=*/false, "fa f32_f16 c32 g8 d256 NSG2", backend_ctx->queue); - if (prog_g8_c32) { - cl_kernel k_g8_c32 = clCreateKernel(prog_g8_c32, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_g8_c32, 128, - "flash_attn_f32_f16_q1_vec_mq_split_c8 (g8 c32 d256)", dk, dv)) { - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32[{dk, dv}] = k_g8_c32; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_g8_c32, "flash_attn_f32_f16_q1_vec_mq_split_g8_c32", dk, dv); - } else { - clReleaseKernel(k_g8_c32); - } - } - clReleaseProgram(prog_g8_c32); - } + } + } + + // gemm_moe_q4_k_q8_1_dp4a (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q4_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q4_k_q8_1_dp4a.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q4_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_k_q8_1_dp4a_bin (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_k_q8_1_dp4a_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_k_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_k_q8_1_dp4a_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); } - if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count({dk, dv}) == 0) { - const std::string opts_g8_c8_ns2 = opts + " -D FA_MQ_ONLY -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2 -D FA_CL_C=" + fa_cl_c_g8_val; - cl_program prog_g8_c8 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8_c8_ns2, - /*fatal=*/false, "fa f32_f16 c8 g8 NSG2", backend_ctx->queue); + } + } + + // gemm_moe_mxfp4_q8_1_dp4a (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_mxfp4_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_mxfp4_q8_1_dp4a.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_mxfp4_q8_1_dp4a_bin (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_mxfp4_q8_1_dp4a_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_q8_1_dp4a_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemm_moe_mxfp4_q8_1_dp4a_ldck_bin (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_ldck_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_mxfp4_q8_1_dp4a_ila_ldck", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_ldck_bin = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_q8_1_dp4a_ila_ldck", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemm_moe_q4_0_q8_1_dp4a (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q4_0_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q4_0_q8_1_dp4a.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q4_0_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q4_0_q8_1_dp4a_bin (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q4_0_q8_1_dp4a_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q4_0_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q4_0_q8_1_dp4a_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemm_moe_q8_1_dp4a (generic dp4a MoE GEMM; MOE_QT=80 -> q8_0 expert variant) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q8_1_dp4a.cl"); +#endif + const std::string opts80 = CL_moe_compile_opts + " -DMOE_QT=80"; + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), opts80.c_str()); + CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q80 = clCreateKernel(prog, "kernel_gemm_moe_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + + const std::string opts50 = CL_moe_compile_opts + " -DMOE_QT=50"; + cl_program prog50 = + build_program_from_source(backend_ctx, kernel_src.c_str(), opts50.c_str()); + CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q50 = clCreateKernel(prog50, "kernel_gemm_moe_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog50)); + + const std::string opts5 = CL_moe_compile_opts + " -DMOE_QT=5"; + cl_program prog5 = + build_program_from_source(backend_ctx, kernel_src.c_str(), opts5.c_str()); + CL_CHECK((backend_ctx->kernel_gemm_moe_q8_1_dp4a_q5k = clCreateKernel(prog5, "kernel_gemm_moe_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog5)); + GGML_LOG_CONT("."); + } + + // moe_reorder_quant_a_q8_1 (fused reorder + q8_1 quant) + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "moe_reorder_quant_a_q8_1.cl.h" + }; +#else + const std::string kernel_src = read_file("moe_reorder_quant_a_q8_1.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_moe_reorder_quant_a_q8_1 = clCreateKernel(prog, "kernel_moe_reorder_quant_a_q8_1", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // transpose_activation_q8 (per-tile transpose of q8_1 activations for the ldck dp4a GEMM) + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "transpose_activation_q8.cl.h" + }; +#else + const std::string kernel_src = read_file("transpose_activation_q8.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_transpose_activation_q8 = clCreateKernel(prog, "kernel_transpose_activation_q8", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q5_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q5_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q5_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q5_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q5_k_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q5_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q5_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q5_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q5_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q5_k_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_moe_q6_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_q6_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_q6_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_q6_k_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_q6_k_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q6_k_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q6_k_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q6_k_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_q6_k_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q6_k_f32_ns_bin + { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q6_k_f32_ns_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q6_k_f32_ns_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_q6_k_f32_ns_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemm_moe_q6_k_q8_1_dp4a (dp4a q6_K MoE prefill GEMM) + if (backend_ctx->has_integer_dot) { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_q6_k_q8_1_dp4a.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_q6_k_q8_1_dp4a.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a = clCreateKernel(prog, "kernel_gemm_moe_q6_k_q8_1_dp4a", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_q6_k_q8_1_dp4a_bin (dp4a prefill GEMM) + if (backend_ctx->has_integer_dot) { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_q6_k_q8_1_dp4a_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_q6_k_q8_1_dp4a_bin = clCreateKernel(prog, "kernel_gemm_moe_q6_k_q8_1_dp4a_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // gemv_moe_mxfp4_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_moe_mxfp4_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_moe_mxfp4_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32_ns = clCreateKernel(prog, "kernel_gemv_moe_mxfp4_f32_ns", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_moe_mxfp4_f32_ns_wimg = clCreateKernel(prog, "kernel_gemv_moe_mxfp4_f32_ns_wimg", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_mxfp4_f32_ns + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_moe_mxfp4_f32_ns.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_moe_mxfp4_f32_ns.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32_ns = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_f32_ns", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_moe_mxfp4_f32_ns_bin + { + size_t bin_size = 0; + backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_moe_mxfp4_f32_ns_ila", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin = clCreateKernel(prog, "kernel_gemm_moe_mxfp4_f32_ns_ila", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + + // moe_reorder_b + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "moe_reorder_b.cl.h" + }; +#else + const std::string kernel_src = read_file("moe_reorder_b.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_moe_reorder_b = clCreateKernel(prog, "kernel_moe_reorder_b", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // moe_sort_by_expert + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "moe_sort_by_expert.cl.h" + }; +#else + const std::string kernel_src = read_file("moe_sort_by_expert.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_moe_histogram = clCreateKernel(prog, "kernel_moe_histogram", &err), err)); + CL_CHECK((backend_ctx->kernel_moe_scan = clCreateKernel(prog, "kernel_moe_scan", &err), err)); + CL_CHECK((backend_ctx->kernel_moe_fill = clCreateKernel(prog, "kernel_moe_fill", &err), err)); + CL_CHECK((backend_ctx->kernel_moe_scatter = clCreateKernel(prog, "kernel_moe_scatter", &err), err)); + CL_CHECK((backend_ctx->kernel_moe_scatter_stable = clCreateKernel(prog, "kernel_moe_scatter_stable", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_q6_k_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q6_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32.cl"); +#endif + + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; + } + + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_mc3", &err), err)); + if (getenv("GGML_OPENCL_MC3_PROBE")) { + cl_ulong pm6 = 0, pm4 = 0; size_t wg6 = 0, wg4 = 0, mult = 0; + clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, sizeof(pm6), &pm6, NULL); + clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(wg6), &wg6, NULL); + clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, sizeof(pm4), &pm4, NULL); + clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3, backend_ctx->device, CL_KERNEL_WORK_GROUP_SIZE, sizeof(wg4), &wg4, NULL); + clGetKernelWorkGroupInfo(backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3, backend_ctx->device, CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE, sizeof(mult), &mult, NULL); + fprintf(stderr, "[MC3-PROBE] q4K_mc3 private=%llu wg_cap=%zu | q6K_mc3 private=%llu wg_cap=%zu | pref_mult=%zu\n", + (unsigned long long)pm4, wg4, (unsigned long long)pm6, wg6, mult); + fflush(stderr); + } + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_q6_k_f32_o4 — 4-output-per-WI variant, opt-in via + // GGML_OPENCL_Q6K_GEMV_O4=1 (~3x fewer dispatches on long-vocab lm_head). + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q6_k_f32_o4.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_o4.cl"); +#endif + + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAT "; + } + + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4 = clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_o4", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + + // Global-read variant: weights read from __global coalesced instead of + // image1d_buffer (the texture cache caps the streaming lm_head read + // bandwidth). Opt-in via GGML_OPENCL_Q6K_GEMV_O4_GLOBAL. + cl_program prog_g = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts + " -DQ6K_O4_GLOBAL"); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4_global = + clCreateKernel(prog_g, "kernel_gemv_noshuffle_q6_K_f32_o4_global", &err), err)); + CL_CHECK(clReleaseProgram(prog_g)); + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_q6_k_f32_tiled — tiled-wide canonical layout, default ON + // (opt out: GGML_OPENCL_Q6K_GEMV_TILED=0; separate convert + GEMV; weights via __global). + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q6_k_f32_tiled.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q6_k_f32_tiled.cl"); +#endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled = + clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_tiled", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled_mc3 = + clCreateKernel(prog, "kernel_gemv_noshuffle_q6_K_f32_tiled_mc3", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_q6_k_f32_tiled — batched (N>1) GEMM over the same tiled-wide + // canonical layout, so batched lm_head/embed stays correct + on GPU. + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q6_k_f32_tiled.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q6_k_f32_tiled.cl"); +#endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + " -cl-mad-enable "; + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32_tiled = + clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32_tiled", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_q6_k_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q6_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q6_k_f32.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), CL_moe_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q6_K_f32_cok = clCreateKernel(prog, "kernel_gemm_noshuffle_q6_K_f32_cok", &err), err)); + GGML_LOG_CONT("."); + } + + // gemv_noshuffle_q5_k_f32 + { + std::string CL_gemv_compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable "; + if (backend_ctx->has_vector_subgroup_broadcast) { + CL_gemv_compile_opts += " -DVECTOR_SUB_GROUP_BROADCAST "; + } + +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemv_noshuffle_q5_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemv_noshuffle_q5_k_f32.cl"); +#endif + + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), CL_gemv_compile_opts); + + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_k_f32", &err), err)); + CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q5_k_f32_mc3 = clCreateKernel(prog, "kernel_gemv_noshuffle_q5_k_f32_mc3", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // gemm_noshuffle_q5_k_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "gemm_noshuffle_q5_k_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("gemm_noshuffle_q5_k_f32.cl"); +#endif + cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q5_k_f32 = clCreateKernel(prog, "kernel_gemm_noshuffle_q5_k_f32", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + + // repack + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "flash_attn_repack.cl.h" + }; +#else + const std::string kernel_src = read_file("flash_attn_repack.cl"); +#endif + cl_program prog = + build_program_from_source(backend_ctx, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->fa.kernel_repack_q_for_wmm = clCreateKernel(prog, "kernel_repack_q_for_wmm", &err), err)); + CL_CHECK((backend_ctx->fa.kernel_repack_k_for_wmm = clCreateKernel(prog, "kernel_repack_k_for_wmm", &err), err)); + CL_CHECK((backend_ctx->fa.kernel_repack_v_for_wmm = clCreateKernel(prog, "kernel_repack_v_for_wmm", &err), err)); + CL_CHECK((backend_ctx->fa.kernel_repack_mask_for_wmm = clCreateKernel(prog, "kernel_repack_mask_for_wmm", &err), err)); + GGML_LOG_CONT("."); + } + + // kernel_flash_attn_f32_f16_bin + { + size_t bin_size = 0; + backend_ctx->fa.kernel_flash_attn_f32_f16_bin = nullptr; + + if (use_adreno_bin_kernels(backend_ctx)) { + const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("flash_attn_f32_f16_wmm", &bin_size); + if (kernel_bin && bin_size > 0) { + cl_program prog = + build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, CL_moe_compile_opts, bin_size); + + CL_CHECK((backend_ctx->fa.kernel_flash_attn_f32_f16_bin = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); + CL_CHECK(clReleaseProgram(prog)); + GGML_LOG_CONT("."); + } + } + } + load_cl_kernels_gemm_coopk(backend_ctx); +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + GGML_LOG_CONT("\n"); + backend_ctx->kernels_loaded = true; +} + +static ggml_backend_opencl_context * ggml_cl_init(ggml_backend_dev_t dev); +static bool ggml_opencl_is_device_supported(ggml_backend_dev_t dev); + +// FA per-(dk,dv) tile tuning table + GGML_OPENCL_FA_TUNE override parsing. +#include "fa_tune.h" + +// FA variant key for the per-(dk,dv,variant) lazy compile cache. +// Kernel built on first dispatch to reduce kernel loading time. +// NB - a warmup run is recommended to get all necessary FA variants compiled +// before actual runs. +enum ggml_opencl_fa_variant { + FA_VARIANT_PRE = 0, // prepass kernels (kv_pad, mask_pad, blk) + FA_VARIANT_F16 = 1, + FA_VARIANT_F32 = 2, + FA_VARIANT_F32_F16 = 3, + FA_VARIANT_Q8_0 = 4, + FA_VARIANT_Q4_0 = 5, + FA_VARIANT_F32_F16_SPLIT = 6, + FA_VARIANT_Q8_0_SPLIT = 7, + FA_VARIANT_Q4_0_SPLIT = 8, +}; + +static std::string ggml_opencl_fa_kernel_src(ggml_opencl_fa_variant v) { +#ifdef GGML_OPENCL_EMBED_KERNELS + switch (v) { + case FA_VARIANT_F16: + return std::string{ + #include "flash_attn_f16.cl.h" + }; + case FA_VARIANT_F32: + return std::string{ + #include "flash_attn_f32.cl.h" + }; + case FA_VARIANT_F32_F16: + case FA_VARIANT_F32_F16_SPLIT: + return std::string{ + #include "flash_attn_f32_f16.cl.h" + }; + case FA_VARIANT_PRE: + return std::string{ + #include "flash_attn_pre_f16.cl.h" + }; + case FA_VARIANT_Q8_0: + case FA_VARIANT_Q8_0_SPLIT: + return std::string{ + #include "flash_attn_f32_q8_0.cl.h" + }; + case FA_VARIANT_Q4_0: + case FA_VARIANT_Q4_0_SPLIT: + return std::string{ + #include "flash_attn_f32_q4_0.cl.h" + }; + } + return {}; +#else + switch (v) { + case FA_VARIANT_F16: return read_file("flash_attn_f16.cl"); + case FA_VARIANT_F32: return read_file("flash_attn_f32.cl"); + case FA_VARIANT_F32_F16: + case FA_VARIANT_F32_F16_SPLIT: return read_file("flash_attn_f32_f16.cl"); + case FA_VARIANT_PRE: return read_file("flash_attn_pre_f16.cl"); + case FA_VARIANT_Q8_0: + case FA_VARIANT_Q8_0_SPLIT: return read_file("flash_attn_f32_q8_0.cl"); + case FA_VARIANT_Q4_0: + case FA_VARIANT_Q4_0_SPLIT: return read_file("flash_attn_f32_q4_0.cl"); + } + return {}; +#endif +} + +static std::string ggml_opencl_fa_compile_opts(ggml_backend_opencl_context * backend_ctx, + const ggml_opencl_fa_dim * cfg, + ggml_opencl_fa_variant variant) { + std::string opts = backend_ctx->kernel_compile_opts + + " -D DK=" + std::to_string(cfg->dk) + + " -D DV=" + std::to_string(cfg->dv) + + " -D BLOCK_M=" + std::to_string(cfg->bm) + + " -D BLOCK_N=" + std::to_string(cfg->bn); + + if (backend_ctx->gpu_family == INTEL) { + opts += " -D FA_SG=32"; + } + + const bool is_split = variant == FA_VARIANT_F32_F16_SPLIT || + variant == FA_VARIANT_Q8_0_SPLIT || + variant == FA_VARIANT_Q4_0_SPLIT; + if (is_split) { + opts += " -D N_SPLIT=" + std::to_string(cfg->n_split); + } + // Shuffle define for the split tile paths AND the cluster-parallel decode + // kernel (q1_vec_mq_split_c8) in the plain F32_F16 program. Without it the + // c8 kernel is compiled out (HAS_SUBGROUP_SHUFFLE guard) and dispatch + // falls back to the baseline mq_split. + if ((is_split || variant == FA_VARIANT_F32_F16) && backend_ctx->has_subgroup_shuffle) { + opts += backend_ctx->has_qcom_subgroup_shuffle + ? " -D cl_qcom_subgroup_shuffle=1" + : " -D cl_khr_subgroup_shuffle=1"; + } + // X1E drops the explicit sub-group size pin on the c8 kernels, compiler + // routes the fp16-heavy kernel to a slow variant with explicit subgroup size + if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E) { + opts += " -D FA_C8_NO_SG_PIN"; + } + // Transposed K tile in local memory: the KV rows the QK loop walks together become + // adjacent, so a group of them is ONE 128-bit local read instead of several narrow + // ones. The QK loop is LDS-read-issue-bound (a wrong-math probe that kept every FMA/dp4a + // but removed the LDS reads ran the kernel ~40% faster), so this is worth up to +26% on + // fa=1 prefill. Output is bit-identical -- only the layout moves. + // + // DK <= 128 only. At DK=256 (gemma-3-4b) it measures 1-2% NEGATIVE and reproduces across + // rounds; padding the row stride does not recover it, so the cause is not a simple bank + // conflict and the wider tile does not want this layout. + // + // Default on within that gate; GGML_OPENCL_FA_K_LDS_T=0 restores the row-major tile. + { + const char * e = getenv("GGML_OPENCL_FA_K_LDS_T"); + if ((e == nullptr || e[0] != '0') && cfg->dk <= 128) { + opts += " -D FA_K_LDS_T"; + } + } + return opts; +} + +// only register when the kernel's required dispatch workgroup size is within +// the limit of the device's maximum workgroup size +static bool ggml_opencl_fa_kernel_fits_wg(ggml_backend_opencl_context * backend_ctx, + cl_kernel kernel, size_t required_wg, + const char * name, int dk, int dv) { + if (kernel == NULL) { return false; } + const size_t dev_max = backend_ctx->max_workgroup_size; + if (dev_max < required_wg) { + GGML_LOG_INFO("ggml_opencl: %s DK=%d DV=%d requires WG %zu > device max %zu; skipping registration (will fall back)\n", + name, dk, dv, required_wg, dev_max); + return false; + } + size_t kwg = 0; + cl_int err = clGetKernelWorkGroupInfo(kernel, backend_ctx->device, + CL_KERNEL_WORK_GROUP_SIZE, + sizeof(kwg), &kwg, NULL); + if (err != CL_SUCCESS) { + GGML_LOG_INFO("ggml_opencl: clGetKernelWorkGroupInfo failed for %s DK=%d DV=%d (err=%d); skipping registration\n", + name, dk, dv, err); + return false; + } + if (kwg < required_wg) { + GGML_LOG_INFO("ggml_opencl: %s DK=%d DV=%d per-kernel max %zu < required %zu; skipping registration (will fall back)\n", + name, dk, dv, kwg, required_wg); + return false; + } + return true; +} + +// Log private memory for an FA kernel. Enable via `GGML_OPENCL_FA_LOG_SPILL=1`. +// On Adreno non-zero private_mem means spilling to global memory due to resource +// constraint and usually causes performance degradation. +// (per-work-item, no cache locality) — a strong signal to pick a config +// with smaller per-thread state (e.g. larger N_SPLIT). +static void ggml_opencl_log_fa_kernel_spill(ggml_backend_opencl_context * backend_ctx, + cl_kernel kernel, const char * name, int dk, int dv) { + static const bool enabled = []{ + const char * e = std::getenv("GGML_OPENCL_FA_LOG_SPILL"); + return e && e[0] && e[0] != '0'; + }(); + + if (!enabled || kernel == nullptr) { + return; + } + + cl_ulong priv_mem = 0; + if (clGetKernelWorkGroupInfo(kernel, backend_ctx->device, CL_KERNEL_PRIVATE_MEM_SIZE, + sizeof(priv_mem), &priv_mem, NULL) == CL_SUCCESS) { + const char * tag = priv_mem > 0 ? "SPILL" : "ok"; + GGML_LOG_INFO("ggml_opencl: [%s] %s DK=%d DV=%d private_mem=%llu bytes\n", + tag, name, dk, dv, (unsigned long long) priv_mem); + } +} + +static void ggml_opencl_ensure_fa_pre_kernels(ggml_backend_opencl_context * backend_ctx, int dk, int dv) { + const std::pair dk_dv = {dk, dv}; + + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == dk && d.dv == dv) { + cfg = &d; break; + } + } + + if (cfg == nullptr) { + GGML_ABORT("ggml_opencl: no flash_attn config for DK=%d DV=%d", dk, dv); + } + + // BM-tile metadata is consumed by the prefill dispatch (n_q_blocks / wg + // sizing) regardless of whether the prepass kernels are needed for this + // n_kv — set it unconditionally + backend_ctx->fa.f32_f16_bm[{dk, dv}] = cfg->bm; + backend_ctx->fa.f32_f16_bn[{dk, dv}] = cfg->bn; + backend_ctx->fa.f32_f16_wg_size[{dk, dv}] = cfg->bm; + backend_ctx->fa.bm[{dk, dv}] = cfg->bm; + backend_ctx->fa.bn[{dk, dv}] = cfg->bn; + + if (backend_ctx->fa.kv_pad_f16.count(dk_dv) > 0) { return; } + + GGML_LOG_INFO("ggml_opencl: lazy-compiling flash_attn prepass for DK=%d DV=%d\n", dk, dv); + cl_int err; + const std::string src = ggml_opencl_fa_kernel_src(FA_VARIANT_PRE); + const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_PRE); + // retry when kernel compile fails + cl_program prog_pre_f16 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts, + /*fatal=*/false, "fa prepass f16", backend_ctx->queue); + if (!prog_pre_f16) { return; } + cl_kernel k_kv_pad_f16 = clCreateKernel(prog_pre_f16, "flash_attn_kv_pad_f16", &err); + if (err != CL_SUCCESS) { clReleaseProgram(prog_pre_f16); return; } + cl_kernel k_mask_pad_f16 = clCreateKernel(prog_pre_f16, "flash_attn_mask_pad_f16", &err); + if (err != CL_SUCCESS) { clReleaseKernel(k_kv_pad_f16); clReleaseProgram(prog_pre_f16); return; } + cl_kernel k_blk_f16 = clCreateKernel(prog_pre_f16, "flash_attn_blk_f16", &err); + if (err != CL_SUCCESS) { clReleaseKernel(k_kv_pad_f16); clReleaseKernel(k_mask_pad_f16); clReleaseProgram(prog_pre_f16); return; } + backend_ctx->fa.kv_pad_f16[{dk, dv}] = k_kv_pad_f16; + backend_ctx->fa.mask_pad_f16[{dk, dv}] = k_mask_pad_f16; + backend_ctx->fa.blk_f16[{dk, dv}] = k_blk_f16; + clReleaseProgram(prog_pre_f16); +} + +static bool ggml_opencl_ensure_fa_f32_f16_vec_512(ggml_backend_opencl_context * backend_ctx) { + const std::pair key = {512, 512}; + auto & fa = backend_ctx->fa; + if (fa.f32_f16_q1_vec.count(key) > 0) { + return true; + } + if (fa.f32_f16_vec_512_attempted || backend_ctx->kernel_compile_opts.empty()) { + return false; + } + fa.f32_f16_vec_512_attempted = true; + + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == 512 && d.dv == 512) { + cfg = &d; + break; + } + } + if (cfg == nullptr) { + return false; + } + + // Compile only vec decode and merge to stay within the Adreno compiler's memory limit. + const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_F32_F16) + + " -D FA_DECODE_ONLY -D FA_VEC_ONLY"; + cl_program prog = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, + ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts, + /*fatal=*/false, "fa f32_f16 decode512 vec", backend_ctx->queue); + if (!prog) { + return false; + } + cl_int err; + cl_kernel vec = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec", &err); + if (err != CL_SUCCESS) { + clReleaseProgram(prog); + return false; + } + cl_kernel merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); + clReleaseProgram(prog); + if (err != CL_SUCCESS) { + clReleaseKernel(vec); + return false; + } + if (!ggml_opencl_fa_kernel_fits_wg(backend_ctx, vec, 256, "flash_attn_f32_f16_q1_vec", 512, 512) || + !ggml_opencl_fa_kernel_fits_wg(backend_ctx, merge, 128, "flash_attn_f32_merge", 512, 512)) { + clReleaseKernel(vec); + clReleaseKernel(merge); + return false; + } + fa.f32_f16_q1_vec[key] = vec; + if (fa.f32_merge.count(key) > 0) { + clReleaseKernel(merge); + } else { + fa.f32_merge[key] = merge; + } + return true; +} + +static void ggml_opencl_ensure_fa_f32_f16_mq_decode(ggml_backend_opencl_context * backend_ctx, int dk, int dv, int gqa) { + const std::tuple key = {dk, dv, gqa}; + auto & fa = backend_ctx->fa; + if (fa.f32_f16_mq_decode.count(key) > 0 || fa.f32_f16_mq_decode_attempted.count(key) > 0 || + backend_ctx->kernel_compile_opts.empty()) { + return; + } + if (gqa == 4 && dk != 128 && fa.f32_f16_q1_vec_mq_split.count({dk, dv}) > 0) { + fa.f32_f16_mq_decode[key] = fa.f32_f16_q1_vec_mq_split.at({dk, dv}); + fa.f32_f16_mq_decode_wg[key] = 256; + fa.f32_f16_mq_decode_hs[key] = 1; + return; + } + fa.f32_f16_mq_decode_attempted.insert(key); + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == dk && d.dv == dv) { + cfg = &d; + break; + } + } + if (cfg == nullptr) { + return; + } + + const bool cluster = dk == 64 || dk == 128; + const int head_sub = cluster ? 2 : (gqa == 8 ? (dk == 512 ? 4 : 2) : 1); + const int nsg_max = dk == 64 ? 1 : (dk == 128 || (gqa == 8 && dk == 256) ? 2 : 4); + const char * kernel_name = cluster ? "flash_attn_f32_f16_q1_vec_mq_split_c8" : "flash_attn_f32_f16_q1_vec_mq_split"; + const std::string src = ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16); + const std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, FA_VARIANT_F32_F16) + + " -D FA_MQ_ONLY -D MQ_GQA=" + std::to_string(gqa / head_sub) + + " -D FA_HEAD_SUB=" + std::to_string(head_sub) + + (cluster ? " -D MQ_NSG=" + std::to_string(nsg_max) + " -D FA_CL_C=16" : " -D FA_MQ_SPLIT_ONLY") + + (dk == 64 ? " -D FA_CL_MHRED -D FA_CL_MASK_BCAST" : "") + + (gqa == 8 && dk == 256 ? " -D FA_Q1_Q_REG" : ""); + for (int nsg = nsg_max; nsg >= 1; nsg /= 2) { + const size_t wg = 64 * nsg; + cl_program prog = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), + opts + " -D MQ_NSG_SPLIT=" + std::to_string(nsg), + /*fatal=*/false, "fa f32_f16 mq decode", backend_ctx->queue); + if (!prog) { + continue; + } + cl_int err; + cl_kernel kernel = clCreateKernel(prog, kernel_name, &err); + clReleaseProgram(prog); + if (err != CL_SUCCESS) { + continue; + } + if (!ggml_opencl_fa_kernel_fits_wg(backend_ctx, kernel, wg, kernel_name, dk, dv)) { + clReleaseKernel(kernel); + continue; + } + fa.f32_f16_mq_decode[key] = kernel; + fa.f32_f16_mq_decode_wg[key] = wg; + fa.f32_f16_mq_decode_hs[key] = head_sub; + return; + } +} + +// DK=512 prefill BM-tile +static bool ggml_opencl_ensure_fa_f32_f16_prefill_512(ggml_backend_opencl_context * backend_ctx, bool split) { + const int dk = 512, dv = 512; + const std::pair dk_dv = {dk, dv}; + auto & target = split ? backend_ctx->fa.f32_f16_split : backend_ctx->fa.f32_f16; + if (target.count(dk_dv) > 0) { return true; } + + static bool failed[2] = { false, false }; + if (failed[split ? 1 : 0]) { return false; } + + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == dk && d.dv == dv) { cfg = &d; break; } + } + if (cfg == nullptr) { failed[split ? 1 : 0] = true; return false; } + if (split && cfg->n_split <= 1) { failed[1] = true; return false; } + + const ggml_opencl_fa_variant variant = split ? FA_VARIANT_F32_F16_SPLIT : FA_VARIANT_F32_F16; + std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant) + " -D FA_PREFILL_ONLY"; + cl_program prog = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, + ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts, + /*fatal=*/false, split ? "fa f32_f16 prefill512 split" : "fa f32_f16 prefill512", + backend_ctx->queue); + if (!prog) { failed[split ? 1 : 0] = true; return false; } + + cl_int err; + cl_kernel k = clCreateKernel(prog, "flash_attn_f32_f16", &err); + if (err != CL_SUCCESS) { clReleaseProgram(prog); failed[split ? 1 : 0] = true; return false; } + target[dk_dv] = k; + if (split) { + backend_ctx->fa.f32_f16_split_wg_size[dk_dv] = cfg->bm * cfg->n_split; + backend_ctx->fa.f32_f16_split_nkv_threshold[dk_dv] = cfg->nkv_split_threshold; + } + ggml_opencl_log_fa_kernel_spill(backend_ctx, k, + split ? "flash_attn_f32_f16 (prefill512 split)" : "flash_attn_f32_f16 (prefill512)", dk, dv); + clReleaseProgram(prog); + + // determine whether to use the K-image variant of the split tile + static const char * pkimg_build_env = getenv("GGML_OPENCL_FA_PREFILL_K_IMG"); + const bool pkimg_build = (pkimg_build_env != NULL) && (pkimg_build_env[0] != '0'); + if (split && pkimg_build && backend_ctx->fa.f32_f16_split_k_img.count(dk_dv) == 0) { + std::string opts_img = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant) + + " -D FA_PREFILL_ONLY -D FA_K_IMG -D FA_TILE_NAME=flash_attn_f32_f16_k_img"; + cl_program prog_img = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, + ggml_opencl_fa_kernel_src(FA_VARIANT_F32_F16).c_str(), opts_img, + /*fatal=*/false, "fa f32_f16 prefill512 split k_img", backend_ctx->queue); + if (prog_img) { + cl_int err_img; + cl_kernel k_img = clCreateKernel(prog_img, "flash_attn_f32_f16_k_img", &err_img); + if (err_img == CL_SUCCESS) { + backend_ctx->fa.f32_f16_split_k_img[dk_dv] = k_img; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_img, + "flash_attn_f32_f16 (prefill512 split k_img)", dk, dv); + } + clReleaseProgram(prog_img); + } + } + return true; +} + +// Compile one (variant, dk, dv); memoised. false = compiler rejected. +static bool ggml_opencl_ensure_fa_variant(ggml_backend_opencl_context * backend_ctx, int dk, int dv, ggml_opencl_fa_variant variant) { + const std::pair dk_dv = {dk, dv}; + + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == dk && d.dv == dv) { + cfg = &d; break; + } + } + if (cfg == nullptr) { + return false; + } + + // if a variant has already been compiled + switch (variant) { + case FA_VARIANT_F16: { + if (backend_ctx->fa.f16.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_F32: { + if (backend_ctx->fa.f32.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_F32_F16: { + // The DK=512 decode-only program does not create the f32_f16 + // prefill kernel; check the q1 kernel instead so that repeated + // calls return a consistent result. + const bool decode_only = (dk == 512); + if (decode_only ? (backend_ctx->fa.f32_f16_q1.count(dk_dv) > 0) + : (backend_ctx->fa.f32_f16.count(dk_dv) > 0)) { + return true; + } + break; + } + case FA_VARIANT_Q8_0: { + if (backend_ctx->fa.f32_q8_0.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_Q4_0: { + if (backend_ctx->fa.f32_q4_0.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_F32_F16_SPLIT: { + if (backend_ctx->fa.f32_f16_split.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_Q8_0_SPLIT: { + if (backend_ctx->fa.f32_q8_0_split.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_Q4_0_SPLIT: { + if (backend_ctx->fa.f32_q4_0_split.count(dk_dv)) { + return true; + } + break; + } + case FA_VARIANT_PRE: { + ggml_opencl_ensure_fa_pre_kernels(backend_ctx, dk, dv); + return true; + } + } + + // not registered but attempted - meaning these kernels failed to compile + const auto attempt_key = std::make_pair(variant, dk_dv); + if (backend_ctx->fa.variant_attempted.count(attempt_key)) { + return false; + } + backend_ctx->fa.variant_attempted.insert(attempt_key); + + const bool is_split = variant == FA_VARIANT_F32_F16_SPLIT || + variant == FA_VARIANT_Q8_0_SPLIT || + variant == FA_VARIANT_Q4_0_SPLIT; + const bool is_quant = variant == FA_VARIANT_Q8_0 || variant == FA_VARIANT_Q8_0_SPLIT || + variant == FA_VARIANT_Q4_0 || variant == FA_VARIANT_Q4_0_SPLIT; + if (is_quant && (dk % 32 != 0 || dv % 32 != 0)) { + return false; + } + if (is_split && cfg->n_split <= 1) { + return false; + } + if ((variant == FA_VARIANT_Q8_0_SPLIT || variant == FA_VARIANT_Q4_0_SPLIT) && + ((dk / 32) % cfg->n_split != 0 || (dv / 4) % cfg->n_split != 0)) { + return false; + } + + const std::string src = ggml_opencl_fa_kernel_src(variant); + if (src.empty()) { return false; } + std::string opts = ggml_opencl_fa_compile_opts(backend_ctx, cfg, variant); + + // bypass kernels for DK=512 + const bool fa_decode_only = (variant == FA_VARIANT_F32_F16 && dk == 512); + if (fa_decode_only) { + opts += " -D FA_DECODE_ONLY -D FA_DECODE_MINIMAL"; + } + + // c8 cluster width (GGML_OPENCL_FA_CL_C overrides): value = GQA4 cluster + // width (kernel default 8); the g8 programs use 2x the value (default 16). + // Wider clusters halve per-lane o_acc at the cost of position streams per + // subgroup + static const int fa_cl_c_env = []{ + const char * e = std::getenv("GGML_OPENCL_FA_CL_C"); + const int x = (e && e[0]) ? atoi(e) : 0; + return (x == 8 || x == 16 || x == 32) ? x : 0; // 0 = per-gen default + }(); + // X2E needs 16 to keep per-lane o_acc at 128B (the compiler spills the + // kernel-default width); X1E does not spill, but C=16 is still a measured + // +28-30% DK128-GQA4 decode win there (X1-85, kv 4096/8192), neutral on + // DK64 / GQA1 / quant-KV. + const int fa_cl_c_gqa4 = fa_cl_c_env ? fa_cl_c_env + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E ? 16 : 0); + const std::string opts_cl_c_gqa4 = fa_cl_c_gqa4 + ? " -D FA_CL_C=" + std::to_string(fa_cl_c_gqa4) : std::string(); + const std::string fa_cl_c_g8_val = std::to_string(fa_cl_c_gqa4 ? fa_cl_c_gqa4 * 2 : 16); + + const char * tag = nullptr; + switch (variant) { + case FA_VARIANT_F16: tag = "fa f16"; break; + case FA_VARIANT_F32: tag = "fa f32"; break; + case FA_VARIANT_F32_F16: tag = "fa f32_f16"; break; + case FA_VARIANT_Q8_0: tag = "fa q8_0"; break; + case FA_VARIANT_Q4_0: tag = "fa q4_0"; break; + case FA_VARIANT_F32_F16_SPLIT: tag = "fa f32_f16 split"; break; + case FA_VARIANT_Q8_0_SPLIT: tag = "fa q8_0 split"; break; + case FA_VARIANT_Q4_0_SPLIT: tag = "fa q4_0 split"; break; + default: break; + } + cl_program prog = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts + opts_cl_c_gqa4, + /*fatal=*/false, tag, backend_ctx->queue); + if (!prog) { return false; } + + cl_int err; + switch (variant) { + case FA_VARIANT_F16: { + cl_kernel k, kq1; + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f16", &err), err)); + CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f16_q1", &err), err)); + backend_ctx->fa.f16[{dk, dv}] = k; + backend_ctx->fa.f16_q1[{dk, dv}] = kq1; + break; + } + case FA_VARIANT_F32: { + cl_kernel k, kq1; + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32", &err), err)); + CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f32_q1", &err), err)); + backend_ctx->fa.f32[{dk, dv}] = k; + backend_ctx->fa.f32_q1[{dk, dv}] = kq1; + break; + } + case FA_VARIANT_F32_F16: { + cl_kernel kq1; + // BM-tile prefill kernel is excluded from the decode-only (DK=512) + if (!fa_decode_only) { + cl_kernel k; + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); + backend_ctx->fa.f32_f16[{dk, dv}] = k; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k, "flash_attn_f32_f16", dk, dv); + } + CL_CHECK((kq1 = clCreateKernel(prog, "flash_attn_f32_f16_q1", &err), err)); + backend_ctx->fa.f32_f16_q1[{dk, dv}] = kq1; + ggml_opencl_log_fa_kernel_spill(backend_ctx, kq1, "flash_attn_f32_f16_q1", dk, dv); + cl_kernel k_split = clCreateKernel(prog, "flash_attn_f32_f16_q1_split", &err); + if (err == CL_SUCCESS) { + backend_ctx->fa.f32_f16_q1_split[{dk, dv}] = k_split; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_split, "flash_attn_f32_f16_q1_split", dk, dv); + } + // q1_vec decode kernel (DV-split + subgroup reduce) + cl_kernel k_q1_vec = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec, 256, + "flash_attn_f32_f16_q1_vec", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec[{dk, dv}] = k_q1_vec; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec, "flash_attn_f32_f16_q1_vec", dk, dv); + } else { + clReleaseKernel(k_q1_vec); + } + } + // KV-head-coalesced vec for high-GQA small models + cl_kernel k_q1_vec_mq = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq, 256, + "flash_attn_f32_f16_q1_vec_mq", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq[{dk, dv}] = k_q1_vec_mq; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq, "flash_attn_f32_f16_q1_vec_mq", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq); + } + } + // KV-head-coalesced + flash-decoding split, reuses merge kernel + cl_kernel k_q1_vec_mq_split = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split, 256, + "flash_attn_f32_f16_q1_vec_mq_split", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split[{dk, dv}] = k_q1_vec_mq_split; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split, "flash_attn_f32_f16_q1_vec_mq_split", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split); + } + } + // K-image variant of MQ_GQA=4 split + cl_kernel k_q1_vec_mq_split_k_img = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split_k_img", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_k_img, 256, + "flash_attn_f32_f16_q1_vec_mq_split_k_img", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img[{dk, dv}] = k_q1_vec_mq_split_k_img; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_k_img, "flash_attn_f32_f16_q1_vec_mq_split_k_img", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split_k_img); + } + } + // Cluster-parallel decode variant + cl_kernel k_q1_vec_mq_split_c8 = clCreateKernel(prog, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_c8, 256, + "flash_attn_f32_f16_q1_vec_mq_split_c8", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_c8[{dk, dv}] = k_q1_vec_mq_split_c8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split_c8); + } + } + cl_kernel k_merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); + if (err == CL_SUCCESS) { + backend_ctx->fa.f32_merge[{dk, dv}] = k_merge; + } + // local-tile decode variant + if (dk == 128 && dv == 128) { + cl_kernel k_lt = clCreateKernel(prog, "flash_attn_f32_f16_q1_local_tile", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lt, 128, + "flash_attn_f32_f16_q1_local_tile", dk, dv)) { + backend_ctx->fa.f32_f16_q1_local_tile[{dk, dv}] = k_lt; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lt, "flash_attn_f32_f16_q1_local_tile", dk, dv); + } else { + clReleaseKernel(k_lt); + } + } + // hybrid local-tile + MQ + FD-split + cl_kernel k_lmq = clCreateKernel(prog, "flash_attn_f32_f16_q1_local_mq_split", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lmq, 64, + "flash_attn_f32_f16_q1_local_mq_split", dk, dv)) { + backend_ctx->fa.f32_f16_q1_local_mq_split[{dk, dv}] = k_lmq; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lmq, "flash_attn_f32_f16_q1_local_mq_split", dk, dv); + } else { + clReleaseKernel(k_lmq); + } + } + } + + // second compile of the same source with -DMQ_GQA=8. + // FA_MQ_ONLY keeps only the vec_mq kernels so that the program + // compiles within the Adreno compiler's memory budget at DK>=256. + // FA_CL_C for the g8 program: MQ_GQA=8 doubles the c8 kernel's + // per-lane o_acc, so widen the cluster to keep the register + // footprint inside the 192-thread WG cap (see fa_cl_c_gqa4 above + // for the per-gen default). + const std::string opts_g8 = opts + " -D MQ_GQA=8 -D MQ_NSG=3 -D MQ_NSG_SPLIT=3 -D FA_MQ_ONLY -D FA_CL_C=" + fa_cl_c_g8_val; + cl_program prog_g8 = fa_decode_only ? nullptr : build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8, + /*fatal=*/false, "fa f32_f16 MQ_GQA=8", backend_ctx->queue); + if (prog_g8) { + const size_t mq_g8_required_wg = 192; // Q1_WG_SIZE(64) * MQ_NSG_SPLIT(3) + cl_kernel k_q1_vec_mq_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_g8, mq_g8_required_wg, + "flash_attn_f32_f16_q1_vec_mq (g8)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_g8[{dk, dv}] = k_q1_vec_mq_g8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_g8, "flash_attn_f32_f16_q1_vec_mq_g8", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_g8); + } + } + cl_kernel k_q1_vec_mq_split_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8, mq_g8_required_wg, + "flash_attn_f32_f16_q1_vec_mq_split (g8)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8[{dk, dv}] = k_q1_vec_mq_split_g8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8, "flash_attn_f32_f16_q1_vec_mq_split_g8", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split_g8); + } + } + // K-image variant + cl_kernel k_q1_vec_mq_split_g8_k_img = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split_k_img", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8_k_img, mq_g8_required_wg, + "flash_attn_f32_f16_q1_vec_mq_split_k_img (g8)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img[{dk, dv}] = k_q1_vec_mq_split_g8_k_img; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8_k_img, "flash_attn_f32_f16_q1_vec_mq_split_g8_k_img", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split_g8_k_img); + } + } + // Cluster-parallel decode, MQ_GQA=8 / FA_CL_C=16 specialization + cl_kernel k_q1_vec_mq_split_g8_c8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split_g8_c8, mq_g8_required_wg, + "flash_attn_f32_f16_q1_vec_mq_split_c8 (g8)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8[{dk, dv}] = k_q1_vec_mq_split_g8_c8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split_g8_c8, "flash_attn_f32_f16_q1_vec_mq_split_g8_c8", dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split_g8_c8); + } + } + // hybrid local-tile + MQ_GQA=8 + if (dk == 128 && dv == 128) { + cl_kernel k_lmq_g8 = clCreateKernel(prog_g8, "flash_attn_f32_f16_q1_local_mq_split", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_lmq_g8, 64, + "flash_attn_f32_f16_q1_local_mq_split (g8)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_local_mq_split_g8[{dk, dv}] = k_lmq_g8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_lmq_g8, "flash_attn_f32_f16_q1_local_mq_split_g8", dk, dv); + } else { + clReleaseKernel(k_lmq_g8); + } + } + } + clReleaseProgram(prog_g8); + } + // NSG_SPLIT=2 programs for the cluster-parallel kernel: its register + // footprint caps the per-kernel WG at 128 on X2 (< the stock 256/192 + // requirement), so it can never register from the stock programs. + // With FA_CL_NCL position streams per subgroup, 2 subgroups still + // carry 16 in-flight rows per WG (baseline WG has 4). FA_MQ_ONLY + // keeps these compiles minimal; skipped when the stock program c8 + // registered (some other device) or shuffles are absent. + if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && + backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count({dk, dv}) == 0) { + const std::string opts_c8_ns2 = opts + " -D FA_MQ_ONLY -D MQ_GQA=4 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2" + opts_cl_c_gqa4; + cl_program prog_c8 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8_ns2, + /*fatal=*/false, "fa f32_f16 c8 NSG2", backend_ctx->queue); + if (prog_c8) { + cl_kernel k_c8 = clCreateKernel(prog_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); + if (err == CL_SUCCESS) { + // WG = MQ_NSG(2) × Q1_WG_SIZE(=FA_SG): 128 Adreno (64), 64 Intel (32). + const size_t c8_ns2_wg = backend_ctx->gpu_family == INTEL ? 64 : 128; + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8, c8_ns2_wg, + "flash_attn_f32_f16_q1_vec_mq_split_c8 (ns2)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2[{dk, dv}] = k_c8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8_ns2", dk, dv); + } else { + clReleaseKernel(k_c8); + } + } + clReleaseProgram(prog_c8); + } + } + // FA_CL_C=32 g8 program for the DK=DV=256 GQA=8 + if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && + dk == 256 && dv == 256) { + const std::string opts_g8_c32 = opts + " -D FA_MQ_ONLY -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2 -D FA_CL_C=32"; + cl_program prog_g8_c32 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8_c32, + /*fatal=*/false, "fa f32_f16 c32 g8 d256 NSG2", backend_ctx->queue); + if (prog_g8_c32) { + cl_kernel k_g8_c32 = clCreateKernel(prog_g8_c32, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_g8_c32, 128, + "flash_attn_f32_f16_q1_vec_mq_split_c8 (g8 c32 d256)", dk, dv)) { + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32[{dk, dv}] = k_g8_c32; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_g8_c32, "flash_attn_f32_f16_q1_vec_mq_split_g8_c32", dk, dv); + } else { + clReleaseKernel(k_g8_c32); + } + } + clReleaseProgram(prog_g8_c32); + } + } + if (!fa_decode_only && backend_ctx->has_subgroup_shuffle && + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count({dk, dv}) == 0) { + const std::string opts_g8_c8_ns2 = opts + " -D FA_MQ_ONLY -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2 -D FA_CL_C=" + fa_cl_c_g8_val; + cl_program prog_g8_c8 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_g8_c8_ns2, + /*fatal=*/false, "fa f32_f16 c8 g8 NSG2", backend_ctx->queue); if (prog_g8_c8) { cl_kernel k_g8_c8 = clCreateKernel(prog_g8_c8, "flash_attn_f32_f16_q1_vec_mq_split_c8", &err); if (err == CL_SUCCESS) { @@ -6211,3907 +8182,5372 @@ static bool ggml_opencl_ensure_fa_variant(ggml_backend_opencl_context * backend_ clReleaseProgram(prog_g8_c8); } } - break; + break; + } + case FA_VARIANT_Q8_0: + case FA_VARIANT_Q4_0: { + const bool is_q8 = variant == FA_VARIANT_Q8_0; + const std::string base = is_q8 ? "flash_attn_f32_q8_0" : "flash_attn_f32_q4_0"; + const std::string name_q1 = base + "_q1"; + const std::string name_q1_split = base + "_q1_split"; + auto & m_q1 = is_q8 ? backend_ctx->fa.f32_q8_0_q1 : backend_ctx->fa.f32_q4_0_q1; + auto & m_prefill = is_q8 ? backend_ctx->fa.f32_q8_0 : backend_ctx->fa.f32_q4_0; + auto & m_q1_split = is_q8 ? backend_ctx->fa.f32_q8_0_q1_split : backend_ctx->fa.f32_q4_0_q1_split; + + cl_kernel k, kq1; + CL_CHECK((kq1 = clCreateKernel(prog, name_q1.c_str(), &err), err)); + CL_CHECK((k = clCreateKernel(prog, base.c_str(), &err), err)); + m_q1[{dk, dv}] = kq1; + m_prefill[{dk, dv}] = k; + ggml_opencl_log_fa_kernel_spill(backend_ctx, kq1, name_q1.c_str(), dk, dv); + ggml_opencl_log_fa_kernel_spill(backend_ctx, k, base.c_str(), dk, dv); + cl_kernel k_split = clCreateKernel(prog, name_q1_split.c_str(), &err); + if (err == CL_SUCCESS) { + m_q1_split[{dk, dv}] = k_split; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_split, name_q1_split.c_str(), dk, dv); + } + + // DV-split decode variant (q1_vec) + auto & m_q1_vec = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec : backend_ctx->fa.f32_q4_0_q1_vec; + const std::string name_q1_vec = name_q1 + "_vec"; + cl_kernel k_q1_vec = clCreateKernel(prog, name_q1_vec.c_str(), &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec, 256, + name_q1_vec.c_str(), dk, dv)) { + m_q1_vec[{dk, dv}] = k_q1_vec; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec, name_q1_vec.c_str(), dk, dv); + } else { + clReleaseKernel(k_q1_vec); + } + } + + // KV-head-coalesced + flash-decoding split + auto & m_mq_split = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split + : backend_ctx->fa.f32_q4_0_q1_vec_mq_split; + const std::string name_mq_split = name_q1 + "_vec_mq_split"; + cl_kernel k_q1_vec_mq_split = clCreateKernel(prog, name_mq_split.c_str(), &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split, 256, + name_mq_split.c_str(), dk, dv)) { + m_mq_split[{dk, dv}] = k_q1_vec_mq_split; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split, name_mq_split.c_str(), dk, dv); + } else { + clReleaseKernel(k_q1_vec_mq_split); + } + } + if (!backend_ctx->fa.f32_merge.count({dk, dv})) { + cl_kernel k_merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); + if (err == CL_SUCCESS) { + backend_ctx->fa.f32_merge[{dk, dv}] = k_merge; + } + } + // Second compile with MQ_GQA=8, MQ_NSG=3, MQ_NSG_SPLIT=3 + auto & m_mq_split_g8 = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8 + : backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8; + const std::string opts_mq_g8 = opts + " -D MQ_GQA=8 -D MQ_NSG=3 -D MQ_NSG_SPLIT=3"; + cl_program prog_mq_g8 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_mq_g8, + /*fatal=*/false, is_q8 ? "fa q8_0 MQ_GQA=8" : "fa q4_0 MQ_GQA=8", + backend_ctx->queue); + if (prog_mq_g8) { + const size_t mq_g8_required_wg = 192; + cl_kernel k_g8 = clCreateKernel(prog_mq_g8, name_mq_split.c_str(), &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_g8, mq_g8_required_wg, + name_mq_split.c_str(), dk, dv)) { + m_mq_split_g8[{dk, dv}] = k_g8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_g8, name_mq_split.c_str(), dk, dv); + } else { + clReleaseKernel(k_g8); + } + } + clReleaseProgram(prog_mq_g8); + } + // GQA=4 cluster-parallel program (NSG_SPLIT=2 / WG=128) + if (backend_ctx->has_subgroup_shuffle) { + auto & m_c8_gqa4 = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8 + : backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8; + const std::string name_c8_gqa4 = name_q1 + "_vec_mq_split_c8"; + const std::string opts_c8_gqa4 = opts + " -D MQ_GQA=4 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2" + opts_cl_c_gqa4; + cl_program prog_c8_gqa4 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8_gqa4, + /*fatal=*/false, is_q8 ? "fa q8_0 c8 GQA4 NSG2" : "fa q4_0 c8 GQA4 NSG2", + backend_ctx->queue); + if (prog_c8_gqa4) { + cl_kernel k_c8_gqa4 = clCreateKernel(prog_c8_gqa4, name_c8_gqa4.c_str(), &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8_gqa4, 128, + name_c8_gqa4.c_str(), dk, dv)) { + m_c8_gqa4[{dk, dv}] = k_c8_gqa4; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8_gqa4, name_c8_gqa4.c_str(), dk, dv); + } else { + clReleaseKernel(k_c8_gqa4); + } + } + clReleaseProgram(prog_c8_gqa4); + } + } + // Cluster-parallel q4_0 decode kernel + if (!is_q8 && backend_ctx->has_subgroup_shuffle) { + const std::string opts_c8 = opts + " -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2"; + cl_program prog_c8 = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8, + /*fatal=*/false, "fa q4_0 c8 NSG2", backend_ctx->queue); + if (prog_c8) { + cl_kernel k_c8 = clCreateKernel(prog_c8, "flash_attn_f32_q4_0_q1_vec_mq_split_c8", &err); + if (err == CL_SUCCESS) { + if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8, 128, + "flash_attn_f32_q4_0_q1_vec_mq_split_c8 (g8 ns2)", dk, dv)) { + backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8[{dk, dv}] = k_c8; + ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8, "flash_attn_f32_q4_0_q1_vec_mq_split_g8_c8", dk, dv); + } else { + clReleaseKernel(k_c8); + } + } + clReleaseProgram(prog_c8); + } + } + break; + } + case FA_VARIANT_F32_F16_SPLIT: { + cl_kernel k; + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); + backend_ctx->fa.f32_f16_split[{dk, dv}] = k; + backend_ctx->fa.f32_f16_split_wg_size[{dk, dv}] = cfg->bm * cfg->n_split; + backend_ctx->fa.f32_f16_split_nkv_threshold[{dk, dv}] = cfg->nkv_split_threshold; + break; + } + case FA_VARIANT_Q8_0_SPLIT: + case FA_VARIANT_Q4_0_SPLIT: { + const bool is_q8 = variant == FA_VARIANT_Q8_0_SPLIT; + cl_kernel k; + CL_CHECK((k = clCreateKernel(prog, is_q8 ? "flash_attn_f32_q8_0" : "flash_attn_f32_q4_0", &err), err)); + auto & split = is_q8 ? backend_ctx->fa.f32_q8_0_split : backend_ctx->fa.f32_q4_0_split; + auto & split_wg = is_q8 ? backend_ctx->fa.f32_q8_0_split_wg_size : backend_ctx->fa.f32_q4_0_split_wg_size; + auto & split_bm = is_q8 ? backend_ctx->fa.f32_q8_0_split_bm : backend_ctx->fa.f32_q4_0_split_bm; + auto & split_thresh = is_q8 ? backend_ctx->fa.f32_q8_0_split_nkv_threshold : backend_ctx->fa.f32_q4_0_split_nkv_threshold; + split[{dk, dv}] = k; + split_wg[{dk, dv}] = cfg->bm * cfg->n_split; + split_bm[{dk, dv}] = cfg->bm; + split_thresh[{dk, dv}] = 0; // quant prefill: always split + break; + } + default: + break; + } + CL_CHECK(clReleaseProgram(prog)); + return true; +} + +// Compile a quant FA split kernel with a hand-picked (BLOCK_M, N_SPLIT) that +// overrides the default fa_dims tuning, for the DK values where the default +// N_SPLIT is degenerate for quant prefill: +// DK=256: default N_SPLIT=16 leaves DK/32=8 blocks -> 0 blocks/split. +// Override N_SPLIT=8 (1 block/split), BLOCK_M=16. +// DK=96 : DK/32 = 3 blocks, not divisible by the default N_SPLIT=2 -> +// override N_SPLIT=3. BLOCK_M must be 16, not 32: the N_SPLIT=3 +// QK-partial reduction uses sub_group_shuffle, so all 3 split +// threads of a query must land in one subgroup — WG_SIZE = +// BLOCK_M*N_SPLIT must be <= the 64-lane Adreno subgroup (16*3=48). +static bool ggml_opencl_ensure_fa_quant_split_override( + ggml_backend_opencl_context * backend_ctx, + int dk, int dv, int quant_bm, int quant_n_split, bool is_q8_0 +) { + const std::pair dk_dv = {dk, dv}; + if (is_q8_0 && backend_ctx->fa.f32_q8_0_split.count(dk_dv)) { + return true; + } + if (!is_q8_0 && backend_ctx->fa.f32_q4_0_split.count(dk_dv)) { + return true; + } + + const ggml_opencl_fa_variant variant = is_q8_0 ? FA_VARIANT_Q8_0_SPLIT : FA_VARIANT_Q4_0_SPLIT; + const auto attempt_key = std::make_pair(variant, dk_dv); + if (backend_ctx->fa.variant_attempted.count(attempt_key)) { + return false; + } + + backend_ctx->fa.variant_attempted.insert(attempt_key); + + std::string shuffle_opts; + if (backend_ctx->has_subgroup_shuffle) { + shuffle_opts = backend_ctx->has_qcom_subgroup_shuffle + ? " -D cl_qcom_subgroup_shuffle=1" + : " -D cl_khr_subgroup_shuffle=1"; + } + const ggml_opencl_fa_dim * cfg = nullptr; + for (const auto & d : g_opencl_fa_dims) { + if (d.dk == dk && d.dv == dv) { + cfg = &d; break; + } + } + if (cfg == nullptr) { + return false; + } + + // BLK_PREPASS_BM is the prepass-kernel BLOCK_M, needed so the quant kernel + // indexes the blk[] classification buffer correctly. + std::string opts = backend_ctx->kernel_compile_opts + shuffle_opts + + " -D DK=" + std::to_string(dk) + + " -D DV=" + std::to_string(dv) + + " -D BLOCK_M=" + std::to_string(quant_bm) + + " -D BLOCK_N=" + std::to_string(cfg->bn) + + " -D N_SPLIT=" + std::to_string(quant_n_split) + + " -D BLK_PREPASS_BM=" + std::to_string(cfg->bm); + + const std::string src = ggml_opencl_fa_kernel_src(variant); + if (src.empty()) { + return false; + } + + const std::string tag = std::string("fa ") + (is_q8_0 ? "q8_0" : "q4_0") + + " split DK=" + std::to_string(dk); + cl_program prog = build_program_from_source_ex( + backend_ctx->context, backend_ctx->device, src.c_str(), opts, + /*fatal=*/false, tag.c_str(), backend_ctx->queue); + if (!prog) { return false; } + cl_int err; + cl_kernel k; + if (is_q8_0) { + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_q8_0", &err), err)); + backend_ctx->fa.f32_q8_0_split[dk_dv] = k; + backend_ctx->fa.f32_q8_0_split_wg_size[dk_dv] = quant_bm * quant_n_split; + backend_ctx->fa.f32_q8_0_split_bm[dk_dv] = quant_bm; + backend_ctx->fa.f32_q8_0_split_nkv_threshold[dk_dv] = 0; + } else { + CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_q4_0", &err), err)); + backend_ctx->fa.f32_q4_0_split[dk_dv] = k; + backend_ctx->fa.f32_q4_0_split_wg_size[dk_dv] = quant_bm * quant_n_split; + backend_ctx->fa.f32_q4_0_split_bm[dk_dv] = quant_bm; + backend_ctx->fa.f32_q4_0_split_nkv_threshold[dk_dv] = 0; + } + CL_CHECK(clReleaseProgram(prog)); + return true; +} + +namespace /* anonymous */ { +extern struct ggml_backend_device_i ggml_backend_opencl_device_i; +} + +// Look for available and suitable devices. +static std::vector ggml_opencl_probe_devices(ggml_backend_reg * reg) { + std::vector found_devices; + +#ifdef GGML_OPENCL_PROFILING + GGML_LOG_INFO("ggml_opencl: OpenCL profiling enabled\n"); +#endif + + struct cl_device; + struct cl_platform { + cl_platform_id id; + unsigned number; + char name[128]; + char vendor[128]; + struct cl_device * devices; + unsigned n_devices; + struct cl_device * default_device; + }; + + struct cl_device { + struct cl_platform * platform; + cl_device_id id; + unsigned number; + cl_device_type type; + char name[128]; + char version[128]; + }; + + enum { NPLAT = 16, NDEV = 16 }; + + struct cl_platform platforms[NPLAT]; + unsigned n_platforms = 0; + struct cl_device devices[NDEV]; + unsigned n_devices = 0; + struct cl_device * default_device = NULL; + unsigned default_platform_number = 0; + + cl_platform_id platform_ids[NPLAT]; + if (clGetPlatformIDs(NPLAT, platform_ids, &n_platforms) != CL_SUCCESS) { + GGML_LOG_ERROR("ggml_opencl: platform IDs not available.\n"); + return found_devices; + } + + for (unsigned i = 0; i < n_platforms; i++) { + struct cl_platform * p = &platforms[i]; + p->number = i; + p->id = platform_ids[i]; + CL_CHECK(clGetPlatformInfo(p->id, CL_PLATFORM_NAME, sizeof(p->name), &p->name, NULL)); + CL_CHECK(clGetPlatformInfo(p->id, CL_PLATFORM_VENDOR, sizeof(p->vendor), &p->vendor, NULL)); + + cl_device_id device_ids[NDEV]; + cl_int clGetDeviceIDsError = clGetDeviceIDs(p->id, CL_DEVICE_TYPE_ALL, NDEV, device_ids, &p->n_devices); + if (clGetDeviceIDsError == CL_DEVICE_NOT_FOUND) { + p->n_devices = 0; + } else { + CL_CHECK(clGetDeviceIDsError); + } + p->devices = p->n_devices > 0 ? &devices[n_devices] : NULL; + p->default_device = NULL; + + for (unsigned j = 0; j < p->n_devices; j++) { + struct cl_device * d = &devices[n_devices]; + d->number = n_devices++; + d->id = device_ids[j]; + d->platform = p; + CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_NAME, sizeof(d->name), &d->name, NULL)); + CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_TYPE, sizeof(d->type), &d->type, NULL)); + CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_VERSION, sizeof(d->version), &d->version, NULL)); + + if (p->default_device == NULL && d->type == CL_DEVICE_TYPE_GPU) { + p->default_device = d; + } + } + + if (default_device == NULL && p->default_device != NULL) { + default_device = p->default_device; + default_platform_number = i; + } + } + + if (n_devices == 0) { + GGML_LOG_ERROR("ggml_opencl: could find any OpenCL devices.\n"); + return found_devices; + } + + char * user_platform_string = getenv("GGML_OPENCL_PLATFORM"); + char * user_device_string = getenv("GGML_OPENCL_DEVICE"); + int user_platform_number = -1; + int user_device_number = -1; + cl_device * candidate_devices = nullptr; + unsigned n_candidate_devices = 0; + + unsigned n; + if (user_platform_string != NULL && sscanf(user_platform_string, " %u", &n) == 1 && n < n_platforms) { + user_platform_number = (int)n; + } + if (user_device_string != NULL && sscanf(user_device_string, " %u", &n) == 1 && n < n_devices) { + user_device_number = (int)n; + } + if (user_platform_number != -1 && user_device_number != -1) { + cl_platform* platform = &platforms[user_platform_number]; + if ((unsigned)user_device_number >= platform->n_devices) { + GGML_LOG_ERROR("ggml_opencl: invalid device number %d\n", user_device_number); + exit(1); + } + default_device = &platform->devices[user_device_number]; + candidate_devices = platform->devices; + n_candidate_devices = platform->n_devices; + } else { + // Choose a platform by matching a substring. + if (user_platform_number == -1 && user_platform_string != NULL && user_platform_string[0] != 0) { + for (unsigned i = 0; i < n_platforms; i++) { + struct cl_platform * p = &platforms[i]; + if (strstr(p->name, user_platform_string) != NULL || + strstr(p->vendor, user_platform_string) != NULL) { + user_platform_number = (int)i; + break; + } + } + if (user_platform_number == -1) { + GGML_LOG_ERROR("ggml_opencl: no platform matching '%s' was found.\n", user_platform_string); + exit(1); + } + } + + int platform_idx = user_platform_number != -1 ? user_platform_number : default_platform_number; + struct cl_platform * p = &platforms[platform_idx]; + candidate_devices = p->devices; + n_candidate_devices = p->n_devices; + default_device = p->default_device; + if (n_candidate_devices == 0) { + GGML_LOG_ERROR("ggml_opencl: selected platform '%s' does not have any devices.\n", p->name); + exit(1); + } + + if (user_device_number == -1 && user_device_string != NULL && user_device_string[0] != 0) { + for (unsigned i = 0; i < n_candidate_devices; i++) { + struct cl_device * d = &candidate_devices[i]; + if (strstr(d->name, user_device_string) != NULL) { + user_device_number = d->number; + break; + } + } + if (user_device_number == -1) { + GGML_LOG_ERROR("ggml_opencl: no device matching '%s' was found.\n", user_device_string); + exit(1); + } + } + if (user_device_number != -1) { + candidate_devices = &devices[user_device_number]; + n_candidate_devices = 1; + default_device = &candidate_devices[0]; + } + + GGML_ASSERT(n_candidate_devices > 0); + + if (default_device == NULL) { + default_device = &candidate_devices[0]; + } + } + + GGML_ASSERT(n_candidate_devices != 0 && candidate_devices); + + // Put the default device in front. + for (unsigned i = 1; i < n_candidate_devices; i++) { + if (&candidate_devices[i] == default_device) { + std::swap(candidate_devices[0], candidate_devices[i]); + default_device = &candidate_devices[0]; + break; + } + } + + GGML_LOG_INFO("ggml_opencl: selected platform: '%s'\n", default_device->platform->name); + + std::vector device_ids; + for (auto dev = candidate_devices, dev_end = candidate_devices + n_candidate_devices; dev != dev_end; dev++) { + device_ids.push_back(dev->id); + } + + cl_int err; + cl_context shared_context; + cl_context_properties properties[] = { (intptr_t) CL_CONTEXT_PLATFORM, (intptr_t) default_device->platform->id, 0 }; + + CL_CHECK( + (shared_context = clCreateContext(properties, device_ids.size(), device_ids.data(), NULL, NULL, &err), err)); + + for (auto dev = candidate_devices, dev_end = candidate_devices + n_candidate_devices; dev != dev_end; dev++) { + GGML_LOG_INFO("\nggml_opencl: device: '%s (%s)'\n", dev->name, dev->version); + + auto dev_ctx = std::unique_ptr(new ggml_backend_opencl_device_context{ + /*.platform =*/dev->platform->id, + /*.platform_nane =*/dev->platform->name, + /*.device =*/dev->id, + /*.device_name =*/dev->name, + /*.device_type =*/dev->type, + /*.device_version =*/dev->version, + /*.backend_ctx =*/nullptr, + /*.buffer_type =*/{}, + /*.context =*/shared_context, + }); + + found_devices.push_back(ggml_backend_device{ + /* .iface = */ ggml_backend_opencl_device_i, + /* .reg = */ reg, + /* .context = */ dev_ctx.get(), + }); + + if (!ggml_opencl_is_device_supported(&found_devices.back())) { + found_devices.pop_back(); + GGML_LOG_WARN("ggml_opencl: drop unsupported device '%s'.\n", dev->name); + continue; + } + + g_ggml_backend_opencl_dev_ctxs.push_back(std::move(dev_ctx)); + } + + if (found_devices.size()) { + auto * dev_ctx = static_cast(found_devices.front().context); + GGML_LOG_INFO("ggml_opencl: default device: '%s (%s)'\n", dev_ctx->device_name.c_str(), + dev_ctx->device_version.c_str()); + + if (dev_ctx->device_type != CL_DEVICE_TYPE_GPU) { + GGML_LOG_WARN("ggml_opencl: warning, the default device is not a GPU: '%s'.\n", + dev_ctx->device_name.c_str()); + } + } + + return found_devices; +} + +static void ggml_opencl_print_backend_info(ggml_backend_opencl_device_context * dev_ctx) { + GGML_ASSERT(dev_ctx); + GGML_ASSERT(dev_ctx->backend_ctx); + + auto * backend_ctx = dev_ctx->backend_ctx; + + GGML_LOG_INFO("ggml_opencl: OpenCL device: %s\n", + backend_ctx->device_name.c_str()); + GGML_LOG_INFO("ggml_opencl: OpenCL driver: %s\n", + backend_ctx->driver_version.c_str()); + GGML_LOG_INFO("ggml_opencl: vector subgroup broadcast support: %s\n", + backend_ctx->has_vector_subgroup_broadcast ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: subgroup shuffle support: %s\n", + backend_ctx->has_subgroup_shuffle ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: device FP16 support: %s\n", + backend_ctx->fp16_support ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: khr dot product support: %s\n", + backend_ctx->has_integer_dot ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: mem base addr align: %u\n", + backend_ctx->alignment); + GGML_LOG_INFO("ggml_opencl: global mem size: %zu MB\n", + backend_ctx->global_mem_size/1024/1024); + GGML_LOG_INFO("ggml_opencl: max mem alloc size: %zu MB\n", + backend_ctx->max_alloc_size/1024/1024); + GGML_LOG_INFO("ggml_opencl: device max image buffer size (pixels): %zu\n", + backend_ctx->image_max_buffer_size); + GGML_LOG_INFO("ggml_opencl: device max image2d size: %zu x %zu\n", + backend_ctx->image2d_max_width, backend_ctx->image2d_max_height); + GGML_LOG_INFO("ggml_opencl: device max workgroup size: %zu\n", + backend_ctx->max_workgroup_size); + GGML_LOG_INFO("ggml_opencl: SVM coarse grain buffer support: %s\n", + backend_ctx->svm_caps & CL_DEVICE_SVM_COARSE_GRAIN_BUFFER ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: SVM fine grain buffer support: %s\n", + backend_ctx->svm_caps & CL_DEVICE_SVM_FINE_GRAIN_BUFFER ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: SVM fine grain system support: %s\n", + backend_ctx->svm_caps & CL_DEVICE_SVM_FINE_GRAIN_SYSTEM ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: SVM atomics support: %s\n", + backend_ctx->svm_caps & CL_DEVICE_SVM_ATOMICS ? "true" : "false"); + GGML_LOG_INFO("ggml_opencl: cl_qcom_subgroup_shuffle support: %s\n", + backend_ctx->has_qcom_subgroup_shuffle ? "true" : "false"); + + // Print out configurations +#ifdef GGML_OPENCL_SOA_Q + GGML_LOG_INFO("ggml_opencl: flattening quantized weights representation as struct of arrays (GGML_OPENCL_SOA_Q)\n"); +#endif // GGML_OPENCL_SOA_Q + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + GGML_LOG_INFO("ggml_opencl: using kernels optimized for Adreno (GGML_OPENCL_USE_ADRENO_KERNELS)\n"); + if (backend_ctx->adreno_xmem_gemm_enabled) { + GGML_LOG_INFO("ggml_opencl: Adreno xmem F16xF32 GEMM enabled (temporary weight prepack)\n"); + } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + + if (backend_ctx->adreno_use_large_buffer) { + if (!backend_ctx->adreno_has_large_buffer) { + GGML_LOG_INFO("ggml_opencl: Adreno large buffer requested but not supported by driver, will use regular buffer\n"); + backend_ctx->adreno_use_large_buffer = false; + } else { + GGML_LOG_INFO("ggml_opencl: Adreno large buffer enabled\n"); + } + } + + if (dev_ctx->opfilter) { + // for information only, the actual regex object is created in ggml_opencl_is_device_supported + GGML_LOG_INFO("ggml_opencl: opfilter regex = \"%s\"\n", dev_ctx->opfilter_str.c_str()); + } +} + +// check if device should be accepted +static bool ggml_opencl_is_device_supported(ggml_backend_dev_t dev) { + GGML_ASSERT(dev); + GGML_ASSERT(dev->context); + + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; + GGML_ASSERT(dev_ctx->platform); + GGML_ASSERT(dev_ctx->device); + + if (strstr(dev_ctx->device_name.c_str(), "Adreno") || + strstr(dev_ctx->device_name.c_str(), "Qualcomm") || + strstr(dev_ctx->device_version.c_str(), "Adreno")) { + dev_ctx->gpu_family = GPU_FAMILY::ADRENO; + + // Usually device version contains the detailed device name + dev_ctx->adreno_gen = get_adreno_gpu_gen(dev_ctx->device_version.c_str()); + if (dev_ctx->adreno_gen == ADRENO_GPU_GEN::ADRENO_UNKNOWN) { + dev_ctx->adreno_gen = get_adreno_gpu_gen(dev_ctx->device_name.c_str()); + } + } else if (strstr(dev_ctx->device_name.c_str(), "Intel")) { + dev_ctx->gpu_family = GPU_FAMILY::INTEL; + } else { + GGML_LOG_WARN("ggml_opencl: unsupported GPU '%s'.\n", dev_ctx->device_name.c_str()); + dev_ctx->gpu_family = GPU_FAMILY::UNKNOWN; + return false; + } + + ggml_cl_version platform_version = get_opencl_platform_version(dev_ctx->platform); + + // Check device OpenCL version, OpenCL 2.0 or above is required + ggml_cl_version opencl_c_version = get_opencl_c_version(platform_version, dev_ctx->device); + if (opencl_c_version.major < 2) { + GGML_LOG_WARN("ggml_opencl: OpenCL 2.0 or above is required\n"); + return false; + } + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (dev_ctx->gpu_family != GPU_FAMILY::ADRENO) { + GGML_LOG_WARN("ggml_opencl: Adreno-specific kernels should not be enabled for non-Adreno GPUs; " + "run on an Adreno GPU or recompile with CMake option `-DGGML_OPENCL_USE_ADRENO_KERNELS=OFF`\n"); + return false; + } +#endif + + size_t ext_str_size; + CL_CHECK(clGetDeviceInfo(dev_ctx->device, CL_DEVICE_EXTENSIONS, 0, NULL, &ext_str_size)); + + std::vector ext_buffer(ext_str_size + 1); + CL_CHECK(clGetDeviceInfo(dev_ctx->device, CL_DEVICE_EXTENSIONS, ext_str_size, ext_buffer.data(), NULL)); + ext_buffer[ext_str_size] = '\0'; + + // Check if ext_buffer contains cl_khr_fp16 + bool fp16_support = strstr(ext_buffer.data(), "cl_khr_fp16") != NULL; + if (!fp16_support) { + GGML_LOG_WARN("ggml_opencl: device does not support FP16\n"); + return false; + } + + // If OpenCL 3.0 is supported, then check for cl_khr_subgroups, which becomes + // optional in OpenCL 3.0 (cl_khr_subgroup is mandatory in OpenCL 2.x) + if (opencl_c_version.major == 3 && strstr(ext_buffer.data(), "cl_khr_subgroups") == NULL && + strstr(ext_buffer.data(), "cl_intel_subgroups") == NULL) { + GGML_LOG_WARN("ggml_opencl: device does not support subgroups (cl_khr_subgroups or cl_intel_subgroups) " + "(note that subgroups is an optional feature in OpenCL 3.0)\n"); + return false; + } + + clGetDeviceInfo(dev_ctx->device, CL_DEVICE_GLOBAL_MEM_SIZE, sizeof(size_t), &dev_ctx->global_mem_size, NULL); + + const char * str_opfilter = getenv("GGML_OPENCL_OPFILTER"); + if (str_opfilter) { + dev_ctx->opfilter_str = str_opfilter; + dev_ctx->opfilter = new std::regex(str_opfilter, std::regex_constants::icase); + } + + return true; +} + +// Initialize device if it is supported (returns nullptr if it is not). +static ggml_backend_opencl_context * ggml_cl_init(ggml_backend_dev_t dev) { + GGML_ASSERT(dev); + GGML_ASSERT(dev->context); + + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; + GGML_ASSERT(dev_ctx->platform); + GGML_ASSERT(dev_ctx->device); + + if (dev_ctx->backend_ctx) { + return dev_ctx->backend_ctx; + } + + auto backend_ctx = std::make_unique(); + backend_ctx->device = dev_ctx->device; + backend_ctx->gpu_family = GPU_FAMILY::UNKNOWN; + + // ref_count get increased in ggml_backend_opencl_device_init + // This function is also used to retrieve backend context, so we don't want + // to increase ref_count for each call. We only want to increase ref_count + // when the associated device is initialized + backend_ctx->ref_count = 0; + + backend_ctx->gpu_family = dev_ctx->gpu_family; + backend_ctx->adreno_gen = dev_ctx->adreno_gen; + if (backend_ctx->gpu_family == GPU_FAMILY::ADRENO) { + ggml_cl_init_fa_dims_table(); + + // Use wave size of 64 for all Adreno GPUs. + backend_ctx->adreno_wave_size = 64; + } + + // Populate backend device name + backend_ctx->device_name = dev_ctx->device_name; + + // A local ref of cl_device_id for convenience + cl_device_id device = backend_ctx->device; + + ggml_cl_version platform_version = get_opencl_platform_version(dev_ctx->platform); + ggml_cl_version opencl_c_version = get_opencl_c_version(platform_version, device); + + backend_ctx->platform_version = platform_version; + backend_ctx->opencl_c_version = opencl_c_version; + + // Check driver version + size_t driver_version_str_size; + CL_CHECK(clGetDeviceInfo(device, CL_DRIVER_VERSION, 0, NULL, &driver_version_str_size)); + std::vector driver_version(driver_version_str_size + 1); + CL_CHECK(clGetDeviceInfo(device, CL_DRIVER_VERSION, driver_version_str_size, driver_version.data(), NULL)); + driver_version[driver_version_str_size] = '\0'; + backend_ctx->driver_version = driver_version.data(); + + backend_ctx->adreno_cl_compiler_version = get_adreno_cl_compiler_version(driver_version.data()); + backend_ctx->has_vector_subgroup_broadcast = + (backend_ctx->adreno_cl_compiler_version.type == E031 && backend_ctx->adreno_cl_compiler_version.major >= 47) || + (backend_ctx->adreno_cl_compiler_version.type == DX && backend_ctx->adreno_cl_compiler_version.major >= 17) || + (backend_ctx->adreno_cl_compiler_version.type == E17); + + // The q6_K flat mul_mat miscompile is a defect of the older E031 compilers, not a + // property of any GPU generation: it reproduces on E031.38 (Adreno 642L) and E031.41 + // (Adreno 740) and is fixed by E031.45 (Adreno 619). Gate on the compiler so parts + // that do not need the workarounds do not pay for them. The explicit type check is + // required: newer_than_or_same() is false for every non-E031 compiler, so negating it + // alone would enable the workarounds on E17/DX. + backend_ctx->q6_k_flat_old_compiler = + backend_ctx->adreno_cl_compiler_version.type == E031 && + !backend_ctx->adreno_cl_compiler_version.newer_than_or_same(E031, 45, 0, 0); + + size_t ext_str_size; + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_EXTENSIONS, 0, NULL, &ext_str_size)); + std::vector ext_buffer(ext_str_size + 1); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_EXTENSIONS, ext_str_size, ext_buffer.data(), NULL)); + ext_buffer[ext_str_size] = '\0'; // ensure it is null terminated + + // check support for qcom_subgroup_shuffle + if (strstr(ext_buffer.data(), "cl_qcom_subgroup_shuffle") != NULL) { + backend_ctx->has_qcom_subgroup_shuffle = true; + } + + // Check if ext_buffer contains cl_khr_fp16 + backend_ctx->fp16_support = strstr(ext_buffer.data(), "cl_khr_fp16") != NULL; + + // check Adreno large buffer support + backend_ctx->adreno_has_large_buffer = strstr(ext_buffer.data(), "cl_qcom_large_buffer") != NULL; + + // subgroup shuffle support (N_SPLIT>1 FA kernel) + backend_ctx->has_qcom_subgroup_shuffle = strstr(ext_buffer.data(), "cl_qcom_subgroup_shuffle") != NULL; + backend_ctx->has_khr_subgroup_shuffle = strstr(ext_buffer.data(), "cl_khr_subgroup_shuffle") != NULL; + backend_ctx->has_subgroup_shuffle = backend_ctx->has_khr_subgroup_shuffle || backend_ctx->has_qcom_subgroup_shuffle; + + // check for cl_khr_integer_dot_product + // cl_qcom_dot_product8 uses signed * unsigned + // while cl_khr_integer_dot_product uses signed * signed -- we stick with khr for now + backend_ctx->has_integer_dot = + strstr(ext_buffer.data(), "cl_khr_integer_dot_product") != NULL; + + cl_uint base_align_in_bits; + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MEM_BASE_ADDR_ALIGN, sizeof(cl_uint), &base_align_in_bits, NULL)); + GGML_ASSERT(base_align_in_bits % 8u == 0); + backend_ctx->alignment = base_align_in_bits / 8u; + + backend_ctx->global_mem_size = dev_ctx->global_mem_size; + + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_MEM_ALLOC_SIZE, sizeof(size_t), &backend_ctx->max_alloc_size, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE_MAX_BUFFER_SIZE, sizeof(size_t), &backend_ctx->image_max_buffer_size, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE2D_MAX_WIDTH, sizeof(size_t), &backend_ctx->image2d_max_width, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE2D_MAX_HEIGHT, sizeof(size_t), &backend_ctx->image2d_max_height, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_WORK_GROUP_SIZE, sizeof(size_t), &backend_ctx->max_workgroup_size, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_LOCAL_MEM_SIZE, sizeof(cl_ulong), &backend_ctx->local_mem_size, NULL)); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_SVM_CAPABILITIES, sizeof(cl_device_svm_capabilities), &backend_ctx->svm_caps, 0)); + + if (opencl_c_version.major >= 3) { + // Assume it is not available for 3.0, since it is optional in 3.0. + // If compiling against 3.0, then we can query. + backend_ctx->non_uniform_workgroups = false; +#if CL_TARGET_OPENCL_VERSION >= 300 + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT, sizeof(cl_bool), + &backend_ctx->non_uniform_workgroups, 0)); +#endif + } else { + GGML_ASSERT(opencl_c_version.major == 2); + // Non-uniform workgroup sizes is mandatory feature in v2.x. + backend_ctx->non_uniform_workgroups = true; + } + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // Adreno xmem F16xF32 GEMM, default on adreno, opt out with GGML_OPENCL_ADRENO_XMEM_GEMM=0. + // This helps models with f16 attention weights, e.g., gpt-oss-20b-f16 + { + const char * xmem_env = getenv("GGML_OPENCL_ADRENO_XMEM_GEMM"); + backend_ctx->adreno_xmem_gemm_enabled = backend_ctx->gpu_family == GPU_FAMILY::ADRENO && + (xmem_env ? atoi(xmem_env) != 0 : true); + } +#endif + + // determine whether to use large buffer for Adreno + backend_ctx->adreno_use_large_buffer = getenv("GGML_OPENCL_ADRENO_USE_LARGE_BUFFER") != nullptr && + backend_ctx->gpu_family == GPU_FAMILY::ADRENO; + + backend_ctx->kernel_compile_opts = ggml_opencl_make_compile_opts(backend_ctx.get()); + CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_COMPUTE_UNITS, + sizeof(backend_ctx->fa.compute_units), &backend_ctx->fa.compute_units, NULL)); + + // ragged moe, unspecified or non-zero means enabled, set to 0 to disable + static const char * ragged_fp16_env = getenv("GGML_OPENCL_MOE_RAGGED_FP16"); + backend_ctx->adreno_use_moe_ragged = (ragged_fp16_env == NULL) ? 1 : (atoi(ragged_fp16_env) != 0); + + // ragged moe, tile-skip granularity (columns per skip-group): 8 = quarter (default), + // 16 = half (legacy), 32 = disabled. Override with GGML_OPENCL_MOE_RAGGED_GRAN={8,16,32} + static const char * ragged_gran_env = getenv("GGML_OPENCL_MOE_RAGGED_GRAN"); + backend_ctx->adreno_moe_ragged_skip_gran = (ragged_gran_env != NULL) ? atoi(ragged_gran_env) : 8; + + // whether fuse moe combine + static const char * fuse_moe_bias_glu_env = getenv("GGML_OPENCL_FUSE_MOE_BIAS_GLU"); + backend_ctx->fuse_moe_bias_glu = fuse_moe_bias_glu_env == NULL ? 1 : (atoi(fuse_moe_bias_glu_env) != 0); + + static const char * fuse_moe_bias_combine_env = getenv("GGML_OPENCL_FUSE_MOE_BIAS_COMBINE"); + backend_ctx->fuse_moe_bias_combine = fuse_moe_bias_combine_env == NULL ? 1 : (atoi(fuse_moe_bias_combine_env) != 0); + + static const char * fuse_moe_combine_env = getenv("GGML_OPENCL_FUSE_MOE_COMBINE"); + backend_ctx->fuse_moe_combine = fuse_moe_combine_env == NULL ? 1 : (atoi(fuse_moe_combine_env) != 0); + + // ragged moe dp4 variant + static const char * ragged_dp4_env = getenv("GGML_OPENCL_MOE_RAGGED"); + backend_ctx->adreno_use_moe_ragged_dp4 = ragged_dp4_env == NULL ? 1 : (atoi(ragged_dp4_env) != 0); + +#ifdef GGML_OPENCL_USE_ADRENO_BIN_KERNELS + // try loading adreno binary kernels if enabled + // if fails to load, builtin kernels will be used + { + dl_handle * kernel_lib_handle = dl_load_library(KERNEL_LIB_NAME); + backend_ctx->adreno_use_bin_kernels = false; + + if (kernel_lib_handle) { + backend_ctx->get_adreno_bin_kernel_func = (get_adreno_bin_kernel_func_t)dl_get_sym(kernel_lib_handle, "get_adreno_kernels"); + if (backend_ctx->get_adreno_bin_kernel_func) { + GGML_LOG_INFO("ggml_opencl: loaded bin kernel library %s\n", KERNEL_LIB_NAME); + backend_ctx->adreno_use_bin_kernels = true; + } else { + GGML_LOG_INFO("ggml_opencl: bin kernel library %s is invalid, will use builtin kernels\n", KERNEL_LIB_NAME); + } + } else { + GGML_LOG_INFO("ggml_opencl: failed to load %s, will use builtin kernels\n", KERNEL_LIB_NAME); + } + } +#endif // GGML_OPENCL_USE_ADRENO_BIN_KERNELS + + cl_int err; + + // A local ref of cl_context for convenience + cl_context context = backend_ctx->context = dev_ctx->context; + + //CL_CHECK((queue = clCreateCommandQueue(context, device, CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE, &err), + // (err != CL_INVALID_QUEUE_PROPERTIES && err != CL_INVALID_VALUE ? err : + // (queue = clCreateCommandQueue(context, device, 0, &err), err) + //))); + cl_command_queue_properties command_queue_props = 0; +#ifdef GGML_OPENCL_PROFILING + command_queue_props |= CL_QUEUE_PROFILING_ENABLE; +#endif + CL_CHECK((backend_ctx->queue = clCreateCommandQueue(context, device, command_queue_props, &err), err)); + + // delay kernel loading until the first buffer is created + // load_cl_kernels(backend_ctx.get()); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // Allocate intermediate buffers and images + size_t required_A_q_d_bytes = 311164928; + size_t required_A_s_d_bytes = 38895616; + size_t required_B_d_bytes = 45088768; + + // Ensure buffer sizes do not exceed the maximum allocation size + size_t max_A_q_d_bytes = MIN(required_A_q_d_bytes, backend_ctx->max_alloc_size); + size_t max_A_s_d_bytes = MIN(required_A_s_d_bytes, backend_ctx->max_alloc_size); + size_t max_B_d_bytes = MIN(required_B_d_bytes, backend_ctx->max_alloc_size); + if (required_A_q_d_bytes > backend_ctx->max_alloc_size) { + GGML_LOG_WARN("ggml_opencl: A_q_d buffer size reduced from %zu to %zu due to device limitations.\n", + required_A_q_d_bytes, max_A_q_d_bytes); + } + if (required_A_s_d_bytes > backend_ctx->max_alloc_size) { + GGML_LOG_WARN("ggml_opencl: A_s_d buffer size reduced from %zu to %zu due to device limitations.\n", + required_A_s_d_bytes, max_A_s_d_bytes); + } + if (required_B_d_bytes > backend_ctx->max_alloc_size) { + GGML_LOG_WARN("ggml_opencl: B_d buffer size reduced from %zu to %zu due to device limitations.\n", + required_B_d_bytes, max_B_d_bytes); + } + + backend_ctx->prealloc_quant_trans.allocate(context, max_A_q_d_bytes); + backend_ctx->prealloc_scales_trans.allocate(context, max_A_s_d_bytes); + backend_ctx->prealloc_act_trans.allocate(context, max_B_d_bytes); +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + + backend_ctx->disable_fusion = getenv("GGML_OPENCL_DISABLE_FUSION") != nullptr; + if (const char * env = getenv("GGML_OPENCL_FUSE_MM_GLU")) { + backend_ctx->fuse_mm_glu = atoi(env) != 0; + } + if (const char * env = getenv("GGML_OPENCL_FUSE_RMS_ADD")) { + backend_ctx->fuse_rms_add = atoi(env) != 0; + } + if (const char * env = getenv("GGML_OPENCL_F16_MROW")) { + backend_ctx->f16_mrow = atoi(env) != 0; + } + if (const char * env = getenv("GGML_OPENCL_F16_MROW_RPT")) { + const int v = atoi(env); + backend_ctx->f16_mrow_rpt = (v == 2 || v == 4 || v == 8 || v == 16) ? v : 1; + } + + dev_ctx->backend_ctx = backend_ctx.release(); + return dev_ctx->backend_ctx; +} + +static void ggml_cl_free(ggml_backend_t backend) { + ggml_backend_opencl_context * ctx = (ggml_backend_opencl_context *) backend->context; + ctx->free(); +} + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static void transpose_2d( + ggml_backend_opencl_context * backend_ctx, + cl_kernel kernel, + cl_mem src, cl_mem dst, size_t size, + cl_int stride, cl_int rows, + bool blocking = true, + bool auto_local = false // let driver pick local size for non-uniform workgroups +) { + static ggml_cl_buffer buf; + + cl_event evt; + cl_int err; + + buf.allocate(backend_ctx->context, size); + + cl_mem trans; + cl_buffer_region region; + + region.origin = 0; + region.size = size; + CL_CHECK((trans = clCreateSubBuffer( + buf.buffer, CL_MEM_READ_WRITE, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &src)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_int), &stride)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_int), &rows)); + + size_t local_size[3] = {64, 1, 1}; + size_t global_size[3] = {(size_t)stride, (size_t)rows, 1};; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, + global_size, auto_local ? NULL : local_size, 0, NULL, NULL)); + + if (blocking) { + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, trans, dst, 0, 0, size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + } else { + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, trans, dst, 0, 0, size, 0, NULL, NULL)); + } + + CL_CHECK(clReleaseMemObject(trans)); +} + +static void transpose_2d_as_8b( + ggml_backend_opencl_context * backend_ctx, + cl_mem src, cl_mem dst, size_t size, + cl_int stride, cl_int rows, + bool blocking = true, + bool auto_local = false +) { + transpose_2d(backend_ctx, backend_ctx->kernel_transpose_8_buf, + src, dst, size, stride, rows, blocking, auto_local); +} + +static void transpose_2d_as_16b( + ggml_backend_opencl_context * backend_ctx, + cl_mem src, cl_mem dst, size_t size, + cl_int stride, cl_int rows, + bool blocking = true, + bool auto_local = false +) { + transpose_2d(backend_ctx, backend_ctx->kernel_transpose_16_buf, + src, dst, size, stride, rows, blocking, auto_local); +} + +static void transpose_2d_as_32b( + ggml_backend_opencl_context * backend_ctx, + cl_mem src, cl_mem dst, size_t size, + cl_int stride, cl_int rows, + bool blocking = true, + bool auto_local = false +) { + transpose_2d(backend_ctx, backend_ctx->kernel_transpose_32_buf, + src, dst, size, stride, rows, blocking, auto_local); +} +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + +//------------------------------------------------------------------------------ +// Tensor extra management +//------------------------------------------------------------------------------ +struct ggml_tensor_extra_cl { + // The buffer object that holds the data. + cl_mem data_device; + // The offset into the buffer object. This is primarily for scratch buffer + // and view operation. + // NB: this offset no longer includes view offset (view_offs). Whenever this + // offset is used, view_offs should be considered. + cl_ulong offset; + // The actual size of the cl_mem object. This is needed when returning the + // block to the pool. + size_t actual_size; + + void reset() { + data_device = nullptr; + offset = 0; + actual_size = 0; + } +}; + +struct ggml_tensor_extra_cl_q1_0 { + cl_mem q = nullptr; + cl_mem q_img = nullptr; + + cl_mem d = nullptr; + cl_mem d_img = nullptr; + + size_t size_q = 0; + size_t size_d = 0; + + ~ggml_tensor_extra_cl_q1_0() { + reset(); + } + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + q_img = nullptr; + d_img = nullptr; + size_q = 0; + size_d = 0; + } +}; + +// Additional tensor extra structs for quantized tensors. +// These tensors are loaded from files and should not be allocated in scratch -- +// they should always be allocated from the pool. Hence, they do not have an +// `offset`, which indicate their locations in the scratch buffer. +struct ggml_tensor_extra_cl_q4_0 { + // Quantized values. + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Scales. + cl_mem d = nullptr; + // Scales in image1d_buffer_t. + cl_mem d_img = nullptr; + // Size of quantized values. + size_t size_q = 0; + // Size of scales. + size_t size_d = 0; + + ~ggml_tensor_extra_cl_q4_0() { + reset(); + } + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; } - case FA_VARIANT_Q8_0: - case FA_VARIANT_Q4_0: { - const bool is_q8 = variant == FA_VARIANT_Q8_0; - const std::string base = is_q8 ? "flash_attn_f32_q8_0" : "flash_attn_f32_q4_0"; - const std::string name_q1 = base + "_q1"; - const std::string name_q1_split = base + "_q1_split"; - auto & m_q1 = is_q8 ? backend_ctx->fa.f32_q8_0_q1 : backend_ctx->fa.f32_q4_0_q1; - auto & m_prefill = is_q8 ? backend_ctx->fa.f32_q8_0 : backend_ctx->fa.f32_q4_0; - auto & m_q1_split = is_q8 ? backend_ctx->fa.f32_q8_0_q1_split : backend_ctx->fa.f32_q4_0_q1_split; + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q_img = nullptr; + } + if (d_img != nullptr) { + CL_CHECK(clReleaseMemObject(d_img)); + d_img = nullptr; + } + size_q = 0; + size_d = 0; + } +}; - cl_kernel k, kq1; - CL_CHECK((kq1 = clCreateKernel(prog, name_q1.c_str(), &err), err)); - CL_CHECK((k = clCreateKernel(prog, base.c_str(), &err), err)); - m_q1[{dk, dv}] = kq1; - m_prefill[{dk, dv}] = k; - ggml_opencl_log_fa_kernel_spill(backend_ctx, kq1, name_q1.c_str(), dk, dv); - ggml_opencl_log_fa_kernel_spill(backend_ctx, k, base.c_str(), dk, dv); - cl_kernel k_split = clCreateKernel(prog, name_q1_split.c_str(), &err); - if (err == CL_SUCCESS) { - m_q1_split[{dk, dv}] = k_split; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_split, name_q1_split.c_str(), dk, dv); - } +struct ggml_tensor_extra_cl_q4_1 { + // Quantized values. + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Scales. + cl_mem d = nullptr; + // Scales in image1d_buffer_t. + cl_mem d_img = nullptr; + // Min + cl_mem m = nullptr; + // Min in image1d_buffer_t. + cl_mem m_img = nullptr; + // Size of quantized values. + size_t size_q = 0; + // Size of scales. + size_t size_d = 0; + // Size of min values. + size_t size_m = 0; - // DV-split decode variant (q1_vec) - auto & m_q1_vec = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec : backend_ctx->fa.f32_q4_0_q1_vec; - const std::string name_q1_vec = name_q1 + "_vec"; - cl_kernel k_q1_vec = clCreateKernel(prog, name_q1_vec.c_str(), &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec, 256, - name_q1_vec.c_str(), dk, dv)) { - m_q1_vec[{dk, dv}] = k_q1_vec; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec, name_q1_vec.c_str(), dk, dv); - } else { - clReleaseKernel(k_q1_vec); - } - } + ~ggml_tensor_extra_cl_q4_1() { + reset(); + } - // KV-head-coalesced + flash-decoding split - auto & m_mq_split = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split - : backend_ctx->fa.f32_q4_0_q1_vec_mq_split; - const std::string name_mq_split = name_q1 + "_vec_mq_split"; - cl_kernel k_q1_vec_mq_split = clCreateKernel(prog, name_mq_split.c_str(), &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_q1_vec_mq_split, 256, - name_mq_split.c_str(), dk, dv)) { - m_mq_split[{dk, dv}] = k_q1_vec_mq_split; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_q1_vec_mq_split, name_mq_split.c_str(), dk, dv); - } else { - clReleaseKernel(k_q1_vec_mq_split); - } - } - if (!backend_ctx->fa.f32_merge.count({dk, dv})) { - cl_kernel k_merge = clCreateKernel(prog, "flash_attn_f32_merge", &err); - if (err == CL_SUCCESS) { - backend_ctx->fa.f32_merge[{dk, dv}] = k_merge; - } - } - // Second compile with MQ_GQA=8, MQ_NSG=3, MQ_NSG_SPLIT=3 - auto & m_mq_split_g8 = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8 - : backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8; - const std::string opts_mq_g8 = opts + " -D MQ_GQA=8 -D MQ_NSG=3 -D MQ_NSG_SPLIT=3"; - cl_program prog_mq_g8 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_mq_g8, - /*fatal=*/false, is_q8 ? "fa q8_0 MQ_GQA=8" : "fa q4_0 MQ_GQA=8", - backend_ctx->queue); - if (prog_mq_g8) { - const size_t mq_g8_required_wg = 192; - cl_kernel k_g8 = clCreateKernel(prog_mq_g8, name_mq_split.c_str(), &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_g8, mq_g8_required_wg, - name_mq_split.c_str(), dk, dv)) { - m_mq_split_g8[{dk, dv}] = k_g8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_g8, name_mq_split.c_str(), dk, dv); - } else { - clReleaseKernel(k_g8); - } - } - clReleaseProgram(prog_mq_g8); - } - // GQA=4 cluster-parallel program (NSG_SPLIT=2 / WG=128) - if (backend_ctx->has_subgroup_shuffle) { - auto & m_c8_gqa4 = is_q8 ? backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8 - : backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8; - const std::string name_c8_gqa4 = name_q1 + "_vec_mq_split_c8"; - const std::string opts_c8_gqa4 = opts + " -D MQ_GQA=4 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2" + opts_cl_c_gqa4; - cl_program prog_c8_gqa4 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8_gqa4, - /*fatal=*/false, is_q8 ? "fa q8_0 c8 GQA4 NSG2" : "fa q4_0 c8 GQA4 NSG2", - backend_ctx->queue); - if (prog_c8_gqa4) { - cl_kernel k_c8_gqa4 = clCreateKernel(prog_c8_gqa4, name_c8_gqa4.c_str(), &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8_gqa4, 128, - name_c8_gqa4.c_str(), dk, dv)) { - m_c8_gqa4[{dk, dv}] = k_c8_gqa4; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8_gqa4, name_c8_gqa4.c_str(), dk, dv); - } else { - clReleaseKernel(k_c8_gqa4); - } - } - clReleaseProgram(prog_c8_gqa4); - } - } - // Cluster-parallel q4_0 decode kernel - if (!is_q8 && backend_ctx->has_subgroup_shuffle) { - const std::string opts_c8 = opts + " -D MQ_GQA=8 -D MQ_NSG=2 -D MQ_NSG_SPLIT=2"; - cl_program prog_c8 = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts_c8, - /*fatal=*/false, "fa q4_0 c8 NSG2", backend_ctx->queue); - if (prog_c8) { - cl_kernel k_c8 = clCreateKernel(prog_c8, "flash_attn_f32_q4_0_q1_vec_mq_split_c8", &err); - if (err == CL_SUCCESS) { - if (ggml_opencl_fa_kernel_fits_wg(backend_ctx, k_c8, 128, - "flash_attn_f32_q4_0_q1_vec_mq_split_c8 (g8 ns2)", dk, dv)) { - backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8[{dk, dv}] = k_c8; - ggml_opencl_log_fa_kernel_spill(backend_ctx, k_c8, "flash_attn_f32_q4_0_q1_vec_mq_split_g8_c8", dk, dv); - } else { - clReleaseKernel(k_c8); - } - } - clReleaseProgram(prog_c8); - } - } - break; + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; } - case FA_VARIANT_F32_F16_SPLIT: { - cl_kernel k; - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_f16", &err), err)); - backend_ctx->fa.f32_f16_split[{dk, dv}] = k; - backend_ctx->fa.f32_f16_split_wg_size[{dk, dv}] = cfg->bm * cfg->n_split; - backend_ctx->fa.f32_f16_split_nkv_threshold[{dk, dv}] = cfg->nkv_split_threshold; - break; + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; } - case FA_VARIANT_Q8_0_SPLIT: - case FA_VARIANT_Q4_0_SPLIT: { - const bool is_q8 = variant == FA_VARIANT_Q8_0_SPLIT; - cl_kernel k; - CL_CHECK((k = clCreateKernel(prog, is_q8 ? "flash_attn_f32_q8_0" : "flash_attn_f32_q4_0", &err), err)); - auto & split = is_q8 ? backend_ctx->fa.f32_q8_0_split : backend_ctx->fa.f32_q4_0_split; - auto & split_wg = is_q8 ? backend_ctx->fa.f32_q8_0_split_wg_size : backend_ctx->fa.f32_q4_0_split_wg_size; - auto & split_bm = is_q8 ? backend_ctx->fa.f32_q8_0_split_bm : backend_ctx->fa.f32_q4_0_split_bm; - auto & split_thresh = is_q8 ? backend_ctx->fa.f32_q8_0_split_nkv_threshold : backend_ctx->fa.f32_q4_0_split_nkv_threshold; - split[{dk, dv}] = k; - split_wg[{dk, dv}] = cfg->bm * cfg->n_split; - split_bm[{dk, dv}] = cfg->bm; - split_thresh[{dk, dv}] = 0; // quant prefill: always split - break; + if (m != nullptr) { + CL_CHECK(clReleaseMemObject(m)); + m = nullptr; } - default: - break; + if (q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q_img = nullptr; + } + // Currently, q_img and d_img are only initialized when SMALL_ALLOC is + // enabled. They point to the images in ggml_backend_opencl_buffer_context. + // So, there is no need to release them here. + // TODO: initialize them for non SMALL_PATH path, or remove them. + d_img = nullptr; + m_img = nullptr; + size_q = 0; + size_d = 0; + size_m = 0; } - CL_CHECK(clReleaseProgram(prog)); - return true; -} +}; + +struct ggml_tensor_extra_cl_q5_0 { + // Quantized values. + cl_mem qs = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem qs_img = nullptr; + // 5-th bit values. + cl_mem qh = nullptr; + // 5-th bit values in image1d_buffer_t. + cl_mem qh_img = nullptr; + // Scales. + cl_mem d = nullptr; + // Scales in image1d_buffer_t. + cl_mem d_img = nullptr; + // Uniform per-32-block scale (2/block) + min (1/block, = d*16 for the -16 centering) + // for the generic dp4a MoE GEMM. Built from d. + cl_mem scale = nullptr; + cl_mem min = nullptr; + // Size of quantized values. + size_t size_qs = 0; + // Size of 5-th bit values. + size_t size_qh = 0; + // Size of scales. + size_t size_d = 0; -// Compile a quant FA split kernel with a hand-picked (BLOCK_M, N_SPLIT) that -// overrides the default fa_dims tuning, for the DK values where the default -// N_SPLIT is degenerate for quant prefill: -// DK=256: default N_SPLIT=16 leaves DK/32=8 blocks -> 0 blocks/split. -// Override N_SPLIT=8 (1 block/split), BLOCK_M=16. -// DK=96 : DK/32 = 3 blocks, not divisible by the default N_SPLIT=2 -> -// override N_SPLIT=3. BLOCK_M must be 16, not 32: the N_SPLIT=3 -// QK-partial reduction uses sub_group_shuffle, so all 3 split -// threads of a query must land in one subgroup — WG_SIZE = -// BLOCK_M*N_SPLIT must be <= the 64-lane Adreno subgroup (16*3=48). -static bool ggml_opencl_ensure_fa_quant_split_override( - ggml_backend_opencl_context * backend_ctx, - int dk, int dv, int quant_bm, int quant_n_split, bool is_q8_0 -) { - const std::pair dk_dv = {dk, dv}; - if (is_q8_0 && backend_ctx->fa.f32_q8_0_split.count(dk_dv)) { - return true; - } - if (!is_q8_0 && backend_ctx->fa.f32_q4_0_split.count(dk_dv)) { - return true; + ~ggml_tensor_extra_cl_q5_0() { + reset(); } - const ggml_opencl_fa_variant variant = is_q8_0 ? FA_VARIANT_Q8_0_SPLIT : FA_VARIANT_Q4_0_SPLIT; - const auto attempt_key = std::make_pair(variant, dk_dv); - if (backend_ctx->fa.variant_attempted.count(attempt_key)) { - return false; + void reset() { + if (qs != nullptr) { + CL_CHECK(clReleaseMemObject(qs)); + qs = nullptr; + } + if (qh != nullptr) { + CL_CHECK(clReleaseMemObject(qh)); + qh = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (qs_img != nullptr) { + CL_CHECK(clReleaseMemObject(qs_img)); + qs_img = nullptr; + } + if (scale != nullptr) { + CL_CHECK(clReleaseMemObject(scale)); + scale = nullptr; + } + if (min != nullptr) { + CL_CHECK(clReleaseMemObject(min)); + min = nullptr; + } + + qh_img = nullptr; + d_img = nullptr; + size_qs = 0; + size_qh = 0; + size_d = 0; } +}; - backend_ctx->fa.variant_attempted.insert(attempt_key); +struct ggml_tensor_extra_cl_q5_1 { + // Quantized values. + cl_mem qs = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem qs_img = nullptr; + // 5-th bit values. + cl_mem qh = nullptr; + // 5-th bit values in image1d_buffer_t. + cl_mem qh_img = nullptr; + // Scales. + cl_mem d = nullptr; + // Scales in image1d_buffer_t. + cl_mem d_img = nullptr; + // Min + cl_mem m = nullptr; + // Min in image1d_buffer_t. + cl_mem m_img = nullptr; + // Size of quantized values. + size_t size_qs = 0; + // Size of 5-th bit values. + size_t size_qh = 0; + // Size of scales. + size_t size_d = 0; + // Size of min values. + size_t size_m = 0; - std::string shuffle_opts; - if (backend_ctx->has_subgroup_shuffle) { - shuffle_opts = backend_ctx->has_qcom_subgroup_shuffle - ? " -D cl_qcom_subgroup_shuffle=1" - : " -D cl_khr_subgroup_shuffle=1"; + ~ggml_tensor_extra_cl_q5_1() { + reset(); } - const ggml_opencl_fa_dim * cfg = nullptr; - for (const auto & d : g_opencl_fa_dims) { - if (d.dk == dk && d.dv == dv) { - cfg = &d; break; + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (qs != nullptr) { + CL_CHECK(clReleaseMemObject(qs)); + qs = nullptr; } + if (qh != nullptr) { + CL_CHECK(clReleaseMemObject(qh)); + qh = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (m != nullptr) { + CL_CHECK(clReleaseMemObject(m)); + m = nullptr; + } + if (qs_img != nullptr) { + CL_CHECK(clReleaseMemObject(qs_img)); + qs_img = nullptr; + } + // qh_img, d_img, and m_img are not currently allocated separately. + // TODO: initialize them for non SMALL_PATH path, or remove them. + qh_img = nullptr; + d_img = nullptr; + m_img = nullptr; + size_qs = 0; + size_qh = 0; + size_d = 0; + size_m = 0; } - if (cfg == nullptr) { - return false; - } +}; - // BLK_PREPASS_BM is the prepass-kernel BLOCK_M, needed so the quant kernel - // indexes the blk[] classification buffer correctly. - std::string opts = backend_ctx->kernel_compile_opts + shuffle_opts + - " -D DK=" + std::to_string(dk) + - " -D DV=" + std::to_string(dv) + - " -D BLOCK_M=" + std::to_string(quant_bm) + - " -D BLOCK_N=" + std::to_string(cfg->bn) + - " -D N_SPLIT=" + std::to_string(quant_n_split) + - " -D BLK_PREPASS_BM=" + std::to_string(cfg->bm); +struct ggml_tensor_extra_cl_mxfp4 { + // Quantized values. + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Scales in E8M0. + cl_mem e = nullptr; + // Scales in image1d_buffer_t. + cl_mem e_img = nullptr; + // Size of quantized values. + size_t size_q = 0; + // Size of scales. + size_t size_e = 0; - const std::string src = ggml_opencl_fa_kernel_src(variant); - if (src.empty()) { - return false; + ~ggml_tensor_extra_cl_mxfp4() { + reset(); } - const std::string tag = std::string("fa ") + (is_q8_0 ? "q8_0" : "q4_0") + - " split DK=" + std::to_string(dk); - cl_program prog = build_program_from_source_ex( - backend_ctx->context, backend_ctx->device, src.c_str(), opts, - /*fatal=*/false, tag.c_str(), backend_ctx->queue); - if (!prog) { return false; } - cl_int err; - cl_kernel k; - if (is_q8_0) { - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_q8_0", &err), err)); - backend_ctx->fa.f32_q8_0_split[dk_dv] = k; - backend_ctx->fa.f32_q8_0_split_wg_size[dk_dv] = quant_bm * quant_n_split; - backend_ctx->fa.f32_q8_0_split_bm[dk_dv] = quant_bm; - backend_ctx->fa.f32_q8_0_split_nkv_threshold[dk_dv] = 0; - } else { - CL_CHECK((k = clCreateKernel(prog, "flash_attn_f32_q4_0", &err), err)); - backend_ctx->fa.f32_q4_0_split[dk_dv] = k; - backend_ctx->fa.f32_q4_0_split_wg_size[dk_dv] = quant_bm * quant_n_split; - backend_ctx->fa.f32_q4_0_split_bm[dk_dv] = quant_bm; - backend_ctx->fa.f32_q4_0_split_nkv_threshold[dk_dv] = 0; + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; + } + if (e != nullptr) { + CL_CHECK(clReleaseMemObject(e)); + e = nullptr; + } + if (q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q_img = nullptr; + } + // Currently, e_img is not used. They can be image1d_buffer_t + // that wraps around q and d to utilize image access path. + e_img = nullptr; + size_q = 0; + size_e = 0; } - CL_CHECK(clReleaseProgram(prog)); - return true; -} +}; -namespace /* anonymous */ { -extern struct ggml_backend_device_i ggml_backend_opencl_device_i; -} +struct ggml_tensor_extra_cl_q8_0 { + cl_mem q = nullptr; + cl_mem q_img = nullptr; -// Look for available and suitable devices. -static std::vector ggml_opencl_probe_devices(ggml_backend_reg * reg) { - std::vector found_devices; + cl_mem d = nullptr; + cl_mem d_img = nullptr; -#ifdef GGML_OPENCL_PROFILING - GGML_LOG_INFO("ggml_opencl: OpenCL profiling enabled\n"); -#endif + // Uniform per-16-segment scale (16/superblock) for the generic dp4a MoE GEMM. + // Expanded from d at set_tensor; the int8 codes are reused from q. + // q8_0 is symmetric so no min buffer (has_min=0). + cl_mem scale = nullptr; - struct cl_device; - struct cl_platform { - cl_platform_id id; - unsigned number; - char name[128]; - char vendor[128]; - struct cl_device * devices; - unsigned n_devices; - struct cl_device * default_device; - }; + size_t size_q = 0; + size_t size_d = 0; + + ~ggml_tensor_extra_cl_q8_0() { + reset(); + } + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (scale != nullptr) { + CL_CHECK(clReleaseMemObject(scale)); + scale = nullptr; + } + // Currently, q_img and d_img are not used. They can be image1d_buffer_t + // that wraps around q and d to utilize image access path. + q_img = nullptr; + d_img = nullptr; + size_q = 0; + size_d = 0; + } +}; - struct cl_device { - struct cl_platform * platform; - cl_device_id id; - unsigned number; - cl_device_type type; - char name[128]; - char version[128]; - }; +struct ggml_tensor_extra_cl_iq4_nl { + cl_mem q = nullptr; + cl_mem q_img = nullptr; - enum { NPLAT = 16, NDEV = 16 }; + cl_mem d = nullptr; + cl_mem d_img = nullptr; - struct cl_platform platforms[NPLAT]; - unsigned n_platforms = 0; - struct cl_device devices[NDEV]; - unsigned n_devices = 0; - struct cl_device * default_device = NULL; - unsigned default_platform_number = 0; + size_t size_q = 0; + size_t size_d = 0; - cl_platform_id platform_ids[NPLAT]; - if (clGetPlatformIDs(NPLAT, platform_ids, &n_platforms) != CL_SUCCESS) { - GGML_LOG_ERROR("ggml_opencl: platform IDs not available.\n"); - return found_devices; + ~ggml_tensor_extra_cl_iq4_nl() { + reset(); } - for (unsigned i = 0; i < n_platforms; i++) { - struct cl_platform * p = &platforms[i]; - p->number = i; - p->id = platform_ids[i]; - CL_CHECK(clGetPlatformInfo(p->id, CL_PLATFORM_NAME, sizeof(p->name), &p->name, NULL)); - CL_CHECK(clGetPlatformInfo(p->id, CL_PLATFORM_VENDOR, sizeof(p->vendor), &p->vendor, NULL)); + void reset() { + if (q != nullptr) { CL_CHECK(clReleaseMemObject(q)); q = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + q_img = nullptr; + d_img = nullptr; + size_q = 0; + size_d = 0; + } +}; - cl_device_id device_ids[NDEV]; - cl_int clGetDeviceIDsError = clGetDeviceIDs(p->id, CL_DEVICE_TYPE_ALL, NDEV, device_ids, &p->n_devices); - if (clGetDeviceIDsError == CL_DEVICE_NOT_FOUND) { - p->n_devices = 0; - } else { - CL_CHECK(clGetDeviceIDsError); - } - p->devices = p->n_devices > 0 ? &devices[n_devices] : NULL; - p->default_device = NULL; +struct ggml_tensor_extra_cl_q4_K { + // Quantized values + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Scales for each super block. + cl_mem s = nullptr; + // Scales + cl_mem d = nullptr; + // Min + cl_mem dm = nullptr; - for (unsigned j = 0; j < p->n_devices; j++) { - struct cl_device * d = &devices[n_devices]; - d->number = n_devices++; - d->id = device_ids[j]; - d->platform = p; - CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_NAME, sizeof(d->name), &d->name, NULL)); - CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_TYPE, sizeof(d->type), &d->type, NULL)); - CL_CHECK(clGetDeviceInfo(d->id, CL_DEVICE_VERSION, sizeof(d->version), &d->version, NULL)); + ~ggml_tensor_extra_cl_q4_K() { + reset(); + } - if (p->default_device == NULL && d->type == CL_DEVICE_TYPE_GPU) { - p->default_device = d; - } + void reset() { + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; } - - if (default_device == NULL && p->default_device != NULL) { - default_device = p->default_device; - default_platform_number = i; + if (s != nullptr) { + CL_CHECK(clReleaseMemObject(s)); + s = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (dm != nullptr) { + CL_CHECK(clReleaseMemObject(dm)); + dm = nullptr; + } + if (q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q_img = nullptr; } } +}; - if (n_devices == 0) { - GGML_LOG_ERROR("ggml_opencl: could find any OpenCL devices.\n"); - return found_devices; - } +struct ggml_tensor_extra_cl_q5_K { + // Lower 4 bits of quantized weights. + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Upper 1 bit of quantized weights. + cl_mem qh = nullptr; + // Scales for each block. + cl_mem s = nullptr; + // Scales for each super block. + cl_mem d = nullptr; + // Min for each super block. + cl_mem dm = nullptr; + // Uniform per-32-block scale (2/block) + min (1/block, = dm*mn) decoded from the + // 6-bit packed s[] for the generic dp4a MoE GEMM kernel_gemm_moe_q8_1_dp4a. + // Built from s/d/dm at set_tensor; q/qh are reused as-is. + cl_mem scale = nullptr; + cl_mem min = nullptr; - char * user_platform_string = getenv("GGML_OPENCL_PLATFORM"); - char * user_device_string = getenv("GGML_OPENCL_DEVICE"); - int user_platform_number = -1; - int user_device_number = -1; - cl_device * candidate_devices = nullptr; - unsigned n_candidate_devices = 0; + size_t size_q = 0; + size_t size_qh = 0; + size_t size_s = 0; + size_t size_d = 0; + size_t size_dm = 0; - unsigned n; - if (user_platform_string != NULL && sscanf(user_platform_string, " %u", &n) == 1 && n < n_platforms) { - user_platform_number = (int)n; - } - if (user_device_string != NULL && sscanf(user_device_string, " %u", &n) == 1 && n < n_devices) { - user_device_number = (int)n; + ~ggml_tensor_extra_cl_q5_K() { + reset(); } - if (user_platform_number != -1 && user_device_number != -1) { - cl_platform* platform = &platforms[user_platform_number]; - if ((unsigned)user_device_number >= platform->n_devices) { - GGML_LOG_ERROR("ggml_opencl: invalid device number %d\n", user_device_number); - exit(1); + + void reset() { + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; } - default_device = &platform->devices[user_device_number]; - candidate_devices = platform->devices; - n_candidate_devices = platform->n_devices; - } else { - // Choose a platform by matching a substring. - if (user_platform_number == -1 && user_platform_string != NULL && user_platform_string[0] != 0) { - for (unsigned i = 0; i < n_platforms; i++) { - struct cl_platform * p = &platforms[i]; - if (strstr(p->name, user_platform_string) != NULL || - strstr(p->vendor, user_platform_string) != NULL) { - user_platform_number = (int)i; - break; - } - } - if (user_platform_number == -1) { - GGML_LOG_ERROR("ggml_opencl: no platform matching '%s' was found.\n", user_platform_string); - exit(1); - } + if (qh != nullptr) { + CL_CHECK(clReleaseMemObject(qh)); + qh = nullptr; } - - int platform_idx = user_platform_number != -1 ? user_platform_number : default_platform_number; - struct cl_platform * p = &platforms[platform_idx]; - candidate_devices = p->devices; - n_candidate_devices = p->n_devices; - default_device = p->default_device; - if (n_candidate_devices == 0) { - GGML_LOG_ERROR("ggml_opencl: selected platform '%s' does not have any devices.\n", p->name); - exit(1); + if (s != nullptr) { + CL_CHECK(clReleaseMemObject(s)); + s = nullptr; } - - if (user_device_number == -1 && user_device_string != NULL && user_device_string[0] != 0) { - for (unsigned i = 0; i < n_candidate_devices; i++) { - struct cl_device * d = &candidate_devices[i]; - if (strstr(d->name, user_device_string) != NULL) { - user_device_number = d->number; - break; - } - } - if (user_device_number == -1) { - GGML_LOG_ERROR("ggml_opencl: no device matching '%s' was found.\n", user_device_string); - exit(1); - } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; } - if (user_device_number != -1) { - candidate_devices = &devices[user_device_number]; - n_candidate_devices = 1; - default_device = &candidate_devices[0]; + if (dm != nullptr) { + CL_CHECK(clReleaseMemObject(dm)); + dm = nullptr; } - - GGML_ASSERT(n_candidate_devices > 0); - - if (default_device == NULL) { - default_device = &candidate_devices[0]; + if (q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q_img = nullptr; } - } - - GGML_ASSERT(n_candidate_devices != 0 && candidate_devices); - - // Put the default device in front. - for (unsigned i = 1; i < n_candidate_devices; i++) { - if (&candidate_devices[i] == default_device) { - std::swap(candidate_devices[0], candidate_devices[i]); - default_device = &candidate_devices[0]; - break; + if (scale != nullptr) { + CL_CHECK(clReleaseMemObject(scale)); + scale = nullptr; + } + if (min != nullptr) { + CL_CHECK(clReleaseMemObject(min)); + min = nullptr; } - } - - GGML_LOG_INFO("ggml_opencl: selected platform: '%s'\n", default_device->platform->name); - std::vector device_ids; - for (auto dev = candidate_devices, dev_end = candidate_devices + n_candidate_devices; dev != dev_end; dev++) { - device_ids.push_back(dev->id); + size_q = 0; + size_qh = 0; + size_s = 0; + size_d = 0; + size_dm = 0; } +}; + +struct ggml_tensor_extra_cl_q2_K { + bool noshuffle = false; + cl_mem qs = nullptr; // quantized values + cl_mem sc = nullptr; // one uchar per 16 weights: scale nibble + min nibble + cl_mem dm = nullptr; // half2 per super-block: d, dmin - cl_int err; - cl_context shared_context; - cl_context_properties properties[] = { (intptr_t) CL_CONTEXT_PLATFORM, (intptr_t) default_device->platform->id, 0 }; + size_t size_qs = 0, size_sc = 0, size_dm = 0; - CL_CHECK( - (shared_context = clCreateContext(properties, device_ids.size(), device_ids.data(), NULL, NULL, &err), err)); + ~ggml_tensor_extra_cl_q2_K() { reset(); } - for (auto dev = candidate_devices, dev_end = candidate_devices + n_candidate_devices; dev != dev_end; dev++) { - GGML_LOG_INFO("\nggml_opencl: device: '%s (%s)'\n", dev->name, dev->version); + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + if (dm != nullptr) { CL_CHECK(clReleaseMemObject(dm)); dm = nullptr; } + size_qs = size_sc = size_dm = 0; + } +}; - auto dev_ctx = std::unique_ptr(new ggml_backend_opencl_device_context{ - /*.platform =*/dev->platform->id, - /*.platform_nane =*/dev->platform->name, - /*.device =*/dev->id, - /*.device_name =*/dev->name, - /*.device_type =*/dev->type, - /*.device_version =*/dev->version, - /*.backend_ctx =*/nullptr, - /*.buffer_type =*/{}, - /*.context =*/shared_context, - }); +struct ggml_tensor_extra_cl_q3_K { + bool noshuffle = false; + cl_mem qs = nullptr; // quantized values + cl_mem hm = nullptr; // high bits + cl_mem sc = nullptr; // packed 6-bit scales + cl_mem d = nullptr; // super-block scales - found_devices.push_back(ggml_backend_device{ - /* .iface = */ ggml_backend_opencl_device_i, - /* .reg = */ reg, - /* .context = */ dev_ctx.get(), - }); + size_t size_qs = 0, size_hm = 0, size_sc = 0, size_d = 0; - if (!ggml_opencl_is_device_supported(&found_devices.back())) { - found_devices.pop_back(); - GGML_LOG_WARN("ggml_opencl: drop unsupported device '%s'.\n", dev->name); - continue; - } + ~ggml_tensor_extra_cl_q3_K() { reset(); } - g_ggml_backend_opencl_dev_ctxs.push_back(std::move(dev_ctx)); + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (hm != nullptr) { CL_CHECK(clReleaseMemObject(hm)); hm = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_hm = size_sc = size_d = 0; } +}; - if (found_devices.size()) { - auto * dev_ctx = static_cast(found_devices.front().context); - GGML_LOG_INFO("ggml_opencl: default device: '%s (%s)'\n", dev_ctx->device_name.c_str(), - dev_ctx->device_version.c_str()); +struct ggml_tensor_extra_cl_iq3_xxs { + bool noshuffle = false; + cl_mem qs = nullptr; // grid indices + cl_mem sas = nullptr; // packed sign codes and scales + cl_mem d = nullptr; // super-block scales - if (dev_ctx->device_type != CL_DEVICE_TYPE_GPU) { - GGML_LOG_WARN("ggml_opencl: warning, the default device is not a GPU: '%s'.\n", - dev_ctx->device_name.c_str()); - } - } + size_t size_qs = 0, size_sas = 0, size_d = 0; - return found_devices; -} + ~ggml_tensor_extra_cl_iq3_xxs() { reset(); } -static void ggml_opencl_print_backend_info(ggml_backend_opencl_device_context * dev_ctx) { - GGML_ASSERT(dev_ctx); - GGML_ASSERT(dev_ctx->backend_ctx); + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sas != nullptr) { CL_CHECK(clReleaseMemObject(sas)); sas = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_sas = size_d = 0; + } +}; - auto * backend_ctx = dev_ctx->backend_ctx; +struct ggml_tensor_extra_cl_iq3_s { + bool noshuffle = false; + cl_mem qs = nullptr; // grid index low bits + cl_mem sg = nullptr; // sign bits + cl_mem qh = nullptr; // grid index high bits + cl_mem sc = nullptr; // packed scales + cl_mem d = nullptr; // super-block scales - GGML_LOG_INFO("ggml_opencl: OpenCL device: %s\n", - backend_ctx->device_name.c_str()); - GGML_LOG_INFO("ggml_opencl: OpenCL driver: %s\n", - backend_ctx->driver_version.c_str()); - GGML_LOG_INFO("ggml_opencl: vector subgroup broadcast support: %s\n", - backend_ctx->has_vector_subgroup_broadcast ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: subgroup shuffle support: %s\n", - backend_ctx->has_subgroup_shuffle ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: device FP16 support: %s\n", - backend_ctx->fp16_support ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: khr dot product support: %s\n", - backend_ctx->has_integer_dot ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: mem base addr align: %u\n", - backend_ctx->alignment); - GGML_LOG_INFO("ggml_opencl: global mem size: %zu MB\n", - backend_ctx->global_mem_size/1024/1024); - GGML_LOG_INFO("ggml_opencl: max mem alloc size: %zu MB\n", - backend_ctx->max_alloc_size/1024/1024); - GGML_LOG_INFO("ggml_opencl: device max image buffer size (pixels): %zu\n", - backend_ctx->image_max_buffer_size); - GGML_LOG_INFO("ggml_opencl: device max image2d size: %zu x %zu\n", - backend_ctx->image2d_max_width, backend_ctx->image2d_max_height); - GGML_LOG_INFO("ggml_opencl: device max workgroup size: %zu\n", - backend_ctx->max_workgroup_size); - GGML_LOG_INFO("ggml_opencl: SVM coarse grain buffer support: %s\n", - backend_ctx->svm_caps & CL_DEVICE_SVM_COARSE_GRAIN_BUFFER ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: SVM fine grain buffer support: %s\n", - backend_ctx->svm_caps & CL_DEVICE_SVM_FINE_GRAIN_BUFFER ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: SVM fine grain system support: %s\n", - backend_ctx->svm_caps & CL_DEVICE_SVM_FINE_GRAIN_SYSTEM ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: SVM atomics support: %s\n", - backend_ctx->svm_caps & CL_DEVICE_SVM_ATOMICS ? "true" : "false"); - GGML_LOG_INFO("ggml_opencl: cl_qcom_subgroup_shuffle support: %s\n", - backend_ctx->has_qcom_subgroup_shuffle ? "true" : "false"); + size_t size_qs = 0, size_sg = 0, size_qh = 0, size_sc = 0, size_d = 0; - // Print out configurations -#ifdef GGML_OPENCL_SOA_Q - GGML_LOG_INFO("ggml_opencl: flattening quantized weights representation as struct of arrays (GGML_OPENCL_SOA_Q)\n"); -#endif // GGML_OPENCL_SOA_Q + ~ggml_tensor_extra_cl_iq3_s() { reset(); } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - GGML_LOG_INFO("ggml_opencl: using kernels optimized for Adreno (GGML_OPENCL_USE_ADRENO_KERNELS)\n"); - if (backend_ctx->adreno_xmem_gemm_enabled) { - GGML_LOG_INFO("ggml_opencl: Adreno xmem F16xF32 GEMM enabled (temporary weight prepack)\n"); + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sg != nullptr) { CL_CHECK(clReleaseMemObject(sg)); sg = nullptr; } + if (qh != nullptr) { CL_CHECK(clReleaseMemObject(qh)); qh = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_sg = size_qh = size_sc = size_d = 0; } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS +}; - if (backend_ctx->adreno_use_large_buffer) { - if (!backend_ctx->adreno_has_large_buffer) { - GGML_LOG_INFO("ggml_opencl: Adreno large buffer requested but not supported by driver, will use regular buffer\n"); - backend_ctx->adreno_use_large_buffer = false; - } else { - GGML_LOG_INFO("ggml_opencl: Adreno large buffer enabled\n"); - } - } - if (dev_ctx->opfilter) { - // for information only, the actual regex object is created in ggml_opencl_is_device_supported - GGML_LOG_INFO("ggml_opencl: opfilter regex = \"%s\"\n", dev_ctx->opfilter_str.c_str()); +struct ggml_tensor_extra_cl_iq2_xxs { + bool noshuffle = false; + cl_mem qs = nullptr; // grid indices + cl_mem sas = nullptr; // packed sign codes and scales + cl_mem d = nullptr; // super-block scales + + size_t size_qs = 0, size_sas = 0, size_d = 0; + + ~ggml_tensor_extra_cl_iq2_xxs() { reset(); } + + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sas != nullptr) { CL_CHECK(clReleaseMemObject(sas)); sas = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_sas = size_d = 0; } -} +}; -// check if device should be accepted -static bool ggml_opencl_is_device_supported(ggml_backend_dev_t dev) { - GGML_ASSERT(dev); - GGML_ASSERT(dev->context); +struct ggml_tensor_extra_cl_iq2_xs { + bool noshuffle = false; + cl_mem qs = nullptr; // packed grid indices and sign codes + cl_mem sc = nullptr; // packed scales + cl_mem d = nullptr; // super-block scales - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; - GGML_ASSERT(dev_ctx->platform); - GGML_ASSERT(dev_ctx->device); + size_t size_qs = 0, size_sc = 0, size_d = 0; - if (strstr(dev_ctx->device_name.c_str(), "Adreno") || - strstr(dev_ctx->device_name.c_str(), "Qualcomm") || - strstr(dev_ctx->device_version.c_str(), "Adreno")) { - dev_ctx->gpu_family = GPU_FAMILY::ADRENO; + ~ggml_tensor_extra_cl_iq2_xs() { reset(); } - // Usually device version contains the detailed device name - dev_ctx->adreno_gen = get_adreno_gpu_gen(dev_ctx->device_version.c_str()); - if (dev_ctx->adreno_gen == ADRENO_GPU_GEN::ADRENO_UNKNOWN) { - dev_ctx->adreno_gen = get_adreno_gpu_gen(dev_ctx->device_name.c_str()); - } - } else if (strstr(dev_ctx->device_name.c_str(), "Intel")) { - dev_ctx->gpu_family = GPU_FAMILY::INTEL; - } else { - GGML_LOG_WARN("ggml_opencl: unsupported GPU '%s'.\n", dev_ctx->device_name.c_str()); - dev_ctx->gpu_family = GPU_FAMILY::UNKNOWN; - return false; + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_sc = size_d = 0; } +}; - ggml_cl_version platform_version = get_opencl_platform_version(dev_ctx->platform); +struct ggml_tensor_extra_cl_iq2_s { + bool noshuffle = false; + cl_mem qs = nullptr; // grid index low bits + cl_mem sg = nullptr; // sign bits + cl_mem qh = nullptr; // grid index high bits + cl_mem sc = nullptr; // packed scales + cl_mem d = nullptr; // super-block scales - // Check device OpenCL version, OpenCL 2.0 or above is required - ggml_cl_version opencl_c_version = get_opencl_c_version(platform_version, dev_ctx->device); - if (opencl_c_version.major < 2) { - GGML_LOG_WARN("ggml_opencl: OpenCL 2.0 or above is required\n"); - return false; - } + size_t size_qs = 0, size_sg = 0, size_qh = 0, size_sc = 0, size_d = 0; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (dev_ctx->gpu_family != GPU_FAMILY::ADRENO) { - GGML_LOG_WARN("ggml_opencl: Adreno-specific kernels should not be enabled for non-Adreno GPUs; " - "run on an Adreno GPU or recompile with CMake option `-DGGML_OPENCL_USE_ADRENO_KERNELS=OFF`\n"); - return false; + ~ggml_tensor_extra_cl_iq2_s() { reset(); } + + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (sg != nullptr) { CL_CHECK(clReleaseMemObject(sg)); sg = nullptr; } + if (qh != nullptr) { CL_CHECK(clReleaseMemObject(qh)); qh = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_sg = size_qh = size_sc = size_d = 0; } -#endif +}; - size_t ext_str_size; - CL_CHECK(clGetDeviceInfo(dev_ctx->device, CL_DEVICE_EXTENSIONS, 0, NULL, &ext_str_size)); +struct ggml_tensor_extra_cl_q2_0 { + bool noshuffle = false; + cl_mem qs = nullptr; + cl_mem d = nullptr; - std::vector ext_buffer(ext_str_size + 1); - CL_CHECK(clGetDeviceInfo(dev_ctx->device, CL_DEVICE_EXTENSIONS, ext_str_size, ext_buffer.data(), NULL)); - ext_buffer[ext_str_size] = '\0'; + size_t size_qs = 0, size_d = 0; - // Check if ext_buffer contains cl_khr_fp16 - bool fp16_support = strstr(ext_buffer.data(), "cl_khr_fp16") != NULL; - if (!fp16_support) { - GGML_LOG_WARN("ggml_opencl: device does not support FP16\n"); - return false; - } + ~ggml_tensor_extra_cl_q2_0() { reset(); } - // If OpenCL 3.0 is supported, then check for cl_khr_subgroups, which becomes - // optional in OpenCL 3.0 (cl_khr_subgroup is mandatory in OpenCL 2.x) - if (opencl_c_version.major == 3 && strstr(ext_buffer.data(), "cl_khr_subgroups") == NULL && - strstr(ext_buffer.data(), "cl_intel_subgroups") == NULL) { - GGML_LOG_WARN("ggml_opencl: device does not support subgroups (cl_khr_subgroups or cl_intel_subgroups) " - "(note that subgroups is an optional feature in OpenCL 3.0)\n"); - return false; + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_d = 0; } +}; - clGetDeviceInfo(dev_ctx->device, CL_DEVICE_GLOBAL_MEM_SIZE, sizeof(size_t), &dev_ctx->global_mem_size, NULL); +struct ggml_tensor_extra_cl_iq1_s { + bool noshuffle = false; + cl_mem qs = nullptr; // grid indices + cl_mem qh = nullptr; // high grid bits, scales, and shifts + cl_mem d = nullptr; // super-block scales - const char * str_opfilter = getenv("GGML_OPENCL_OPFILTER"); - if (str_opfilter) { - dev_ctx->opfilter_str = str_opfilter; - dev_ctx->opfilter = new std::regex(str_opfilter, std::regex_constants::icase); + size_t size_qs = 0, size_qh = 0, size_d = 0; + + ~ggml_tensor_extra_cl_iq1_s() { reset(); } + + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (qh != nullptr) { CL_CHECK(clReleaseMemObject(qh)); qh = nullptr; } + if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } + size_qs = size_qh = size_d = 0; } +}; - return true; -} +struct ggml_tensor_extra_cl_iq1_m { + bool noshuffle = false; + cl_mem qs = nullptr; // grid indices + cl_mem qh = nullptr; // high grid bits and shifts + cl_mem sc = nullptr; // packed block and super-block scales -// Initialize device if it is supported (returns nullptr if it is not). -static ggml_backend_opencl_context * ggml_cl_init(ggml_backend_dev_t dev) { - GGML_ASSERT(dev); - GGML_ASSERT(dev->context); + size_t size_qs = 0, size_qh = 0, size_sc = 0; - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; - GGML_ASSERT(dev_ctx->platform); - GGML_ASSERT(dev_ctx->device); + ~ggml_tensor_extra_cl_iq1_m() { reset(); } - if (dev_ctx->backend_ctx) { - return dev_ctx->backend_ctx; + void reset() { + noshuffle = false; + if (qs != nullptr) { CL_CHECK(clReleaseMemObject(qs)); qs = nullptr; } + if (qh != nullptr) { CL_CHECK(clReleaseMemObject(qh)); qh = nullptr; } + if (sc != nullptr) { CL_CHECK(clReleaseMemObject(sc)); sc = nullptr; } + size_qs = size_qh = size_sc = 0; } +}; - auto backend_ctx = std::make_unique(); - backend_ctx->device = dev_ctx->device; - backend_ctx->gpu_family = GPU_FAMILY::UNKNOWN; +struct ggml_tensor_extra_cl_q6_K { + // Lower 4 bits of quantized weights. + cl_mem ql = nullptr; + // Lower 4 bits as image1d_buffer_t + cl_mem ql_img = nullptr; + // Upper 2 bits of quantized weights. + cl_mem qh = nullptr; + // Upper 2 bits as image1d_buffer_t + cl_mem qh_img = nullptr; + // Scales for each block. + cl_mem s = nullptr; + // Scales for each super block. + cl_mem d = nullptr; - // ref_count get increased in ggml_backend_opencl_device_init - // This function is also used to retrieve backend context, so we don't want - // to increase ref_count for each call. We only want to increase ref_count - // when the associated device is initialized - backend_ctx->ref_count = 0; + size_t size_ql = 0; + size_t size_qh = 0; + size_t size_s = 0; + size_t size_d = 0; - backend_ctx->gpu_family = dev_ctx->gpu_family; - backend_ctx->adreno_gen = dev_ctx->adreno_gen; - if (backend_ctx->gpu_family == GPU_FAMILY::ADRENO) { - ggml_cl_init_fa_dims_table(); + ~ggml_tensor_extra_cl_q6_K() { + reset(); + } + + void reset() { + if (ql != nullptr) { + CL_CHECK(clReleaseMemObject(ql)); + ql = nullptr; + } + if (qh != nullptr) { + CL_CHECK(clReleaseMemObject(qh)); + qh = nullptr; + } + if (s != nullptr) { + CL_CHECK(clReleaseMemObject(s)); + s = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + if (ql_img != nullptr) { + CL_CHECK(clReleaseMemObject(ql_img)); + ql_img = nullptr; + } + if (qh_img != nullptr) { + CL_CHECK(clReleaseMemObject(qh_img)); + qh_img = nullptr; + } - // Use wave size of 64 for all Adreno GPUs. - backend_ctx->adreno_wave_size = 64; + size_ql = 0; + size_qh = 0; + size_s = 0; + size_d = 0; } +}; - // Populate backend device name - backend_ctx->device_name = dev_ctx->device_name; - - // A local ref of cl_device_id for convenience - cl_device_id device = backend_ctx->device; - - ggml_cl_version platform_version = get_opencl_platform_version(dev_ctx->platform); - ggml_cl_version opencl_c_version = get_opencl_c_version(platform_version, device); - - backend_ctx->platform_version = platform_version; - backend_ctx->opencl_c_version = opencl_c_version; - - // Check driver version - size_t driver_version_str_size; - CL_CHECK(clGetDeviceInfo(device, CL_DRIVER_VERSION, 0, NULL, &driver_version_str_size)); - std::vector driver_version(driver_version_str_size + 1); - CL_CHECK(clGetDeviceInfo(device, CL_DRIVER_VERSION, driver_version_str_size, driver_version.data(), NULL)); - driver_version[driver_version_str_size] = '\0'; - backend_ctx->driver_version = driver_version.data(); +//------------------------------------------------------------------------------ +// Backend API +//------------------------------------------------------------------------------ - backend_ctx->adreno_cl_compiler_version = get_adreno_cl_compiler_version(driver_version.data()); - backend_ctx->has_vector_subgroup_broadcast = - (backend_ctx->adreno_cl_compiler_version.type == E031 && backend_ctx->adreno_cl_compiler_version.major >= 47) || - (backend_ctx->adreno_cl_compiler_version.type == DX && backend_ctx->adreno_cl_compiler_version.major >= 17) || - (backend_ctx->adreno_cl_compiler_version.type == E17); +// +// backend +// +static const char * ggml_backend_opencl_name(ggml_backend_t backend) { + return "OpenCL"; - // The q6_K flat mul_mat miscompile is a defect of the older E031 compilers, not a - // property of any GPU generation: it reproduces on E031.38 (Adreno 642L) and E031.41 - // (Adreno 740) and is fixed by E031.45 (Adreno 619). Gate on the compiler so parts - // that do not need the workarounds do not pay for them. The explicit type check is - // required: newer_than_or_same() is false for every non-E031 compiler, so negating it - // alone would enable the workarounds on E17/DX. - backend_ctx->q6_k_flat_old_compiler = - backend_ctx->adreno_cl_compiler_version.type == E031 && - !backend_ctx->adreno_cl_compiler_version.newer_than_or_same(E031, 45, 0, 0); + UNUSED(backend); +} - size_t ext_str_size; - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_EXTENSIONS, 0, NULL, &ext_str_size)); - std::vector ext_buffer(ext_str_size + 1); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_EXTENSIONS, ext_str_size, ext_buffer.data(), NULL)); - ext_buffer[ext_str_size] = '\0'; // ensure it is null terminated +static void ggml_backend_opencl_free(ggml_backend_t backend) { + ggml_cl_free(backend); +} - // check support for qcom_subgroup_shuffle - if (strstr(ext_buffer.data(), "cl_qcom_subgroup_shuffle") != NULL) { - backend_ctx->has_qcom_subgroup_shuffle = true; - } +static void ggml_backend_opencl_set_tensor_async(ggml_backend_t backend, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + GGML_UNUSED(backend); + GGML_UNUSED(tensor); + GGML_UNUSED(data); + GGML_UNUSED(offset); + GGML_UNUSED(size); +} - // Check if ext_buffer contains cl_khr_fp16 - backend_ctx->fp16_support = strstr(ext_buffer.data(), "cl_khr_fp16") != NULL; +static void ggml_backend_opencl_get_tensor_async(ggml_backend_t backend, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { + GGML_UNUSED(backend); + GGML_UNUSED(tensor); + GGML_UNUSED(data); + GGML_UNUSED(offset); + GGML_UNUSED(size); +} - // check Adreno large buffer support - backend_ctx->adreno_has_large_buffer = strstr(ext_buffer.data(), "cl_qcom_large_buffer") != NULL; +static bool ggml_backend_opencl_cpy_tensor_async(ggml_backend_t backend, const ggml_tensor * src, ggml_tensor * dst) { + GGML_UNUSED(backend); + GGML_UNUSED(src); + GGML_UNUSED(dst); + return false; +} - // subgroup shuffle support (N_SPLIT>1 FA kernel) - backend_ctx->has_qcom_subgroup_shuffle = strstr(ext_buffer.data(), "cl_qcom_subgroup_shuffle") != NULL; - backend_ctx->has_subgroup_shuffle = - strstr(ext_buffer.data(), "cl_khr_subgroup_shuffle") != NULL || - backend_ctx->has_qcom_subgroup_shuffle; +static void ggml_backend_opencl_synchronize(ggml_backend_t backend) { + auto * backend_ctx = static_cast(backend->context); - // check for cl_khr_integer_dot_product - // cl_qcom_dot_product8 uses signed * unsigned - // while cl_khr_integer_dot_product uses signed * signed -- we stick with khr for now - backend_ctx->has_integer_dot = - strstr(ext_buffer.data(), "cl_khr_integer_dot_product") != NULL; + cl_event evt; + CL_CHECK(clEnqueueBarrierWithWaitList(backend_ctx->queue, 0, nullptr, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); +} - cl_uint base_align_in_bits; - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MEM_BASE_ADDR_ALIGN, sizeof(cl_uint), &base_align_in_bits, NULL)); - GGML_ASSERT(base_align_in_bits % 8u == 0); - backend_ctx->alignment = base_align_in_bits / 8u; +// Synchronizes the 'backend_ctx's device with others so that commands +// enqueued to it won't start until commands in the other devices have +// completed. +static void sync_with_other_backends(ggml_backend_opencl_context * backend_ctx) { + if (g_ggml_backend_opencl_devices.size() < 2) { + return; // No other devices to synchronize with. + } - backend_ctx->global_mem_size = dev_ctx->global_mem_size; + std::vector events; + events.reserve(g_ggml_backend_opencl_devices.size()); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_MEM_ALLOC_SIZE, sizeof(size_t), &backend_ctx->max_alloc_size, NULL)); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE_MAX_BUFFER_SIZE, sizeof(size_t), &backend_ctx->image_max_buffer_size, NULL)); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE2D_MAX_WIDTH, sizeof(size_t), &backend_ctx->image2d_max_width, NULL)); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_IMAGE2D_MAX_HEIGHT, sizeof(size_t), &backend_ctx->image2d_max_height, NULL)); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_WORK_GROUP_SIZE, sizeof(size_t), &backend_ctx->max_workgroup_size, NULL)); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_SVM_CAPABILITIES, sizeof(cl_device_svm_capabilities), &backend_ctx->svm_caps, 0)); + for (ggml_backend_device & backend_dev : g_ggml_backend_opencl_devices) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) backend_dev.context; + auto * other_backend_ctx = dev_ctx->backend_ctx; - if (opencl_c_version.major >= 3) { - // Assume it is not available for 3.0, since it is optional in 3.0. - // If compiling against 3.0, then we can query. - backend_ctx->non_uniform_workgroups = false; -#if CL_TARGET_OPENCL_VERSION >= 300 - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT, sizeof(cl_bool), - &backend_ctx->non_uniform_workgroups, 0)); -#endif - } else { - GGML_ASSERT(opencl_c_version.major == 2); - // Non-uniform workgroup sizes is mandatory feature in v2.x. - backend_ctx->non_uniform_workgroups = true; + if (backend_ctx != other_backend_ctx) { + cl_event ev; + CL_CHECK(clEnqueueMarkerWithWaitList(other_backend_ctx->queue, 0, nullptr, &ev)); + CL_CHECK(clFlush(other_backend_ctx->queue)); + events.push_back(ev); + } } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // Adreno xmem F16xF32 GEMM, default on adreno, opt out with GGML_OPENCL_ADRENO_XMEM_GEMM=0. - // This helps models with f16 attention weights, e.g., gpt-oss-20b-f16 - { - const char * xmem_env = getenv("GGML_OPENCL_ADRENO_XMEM_GEMM"); - backend_ctx->adreno_xmem_gemm_enabled = backend_ctx->gpu_family == GPU_FAMILY::ADRENO && - (xmem_env ? atoi(xmem_env) != 0 : true); + CL_CHECK(clEnqueueBarrierWithWaitList(backend_ctx->queue, events.size(), events.data(), nullptr)); + for (auto ev : events) { + CL_CHECK(clReleaseEvent(ev)); } -#endif - - // determine whether to use large buffer for Adreno - backend_ctx->adreno_use_large_buffer = getenv("GGML_OPENCL_ADRENO_USE_LARGE_BUFFER") != nullptr && - backend_ctx->gpu_family == GPU_FAMILY::ADRENO; - - backend_ctx->kernel_compile_opts = ggml_opencl_make_compile_opts(backend_ctx.get()); - CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_MAX_COMPUTE_UNITS, - sizeof(backend_ctx->fa.compute_units), &backend_ctx->fa.compute_units, NULL)); - - // ragged moe, unspecified or non-zero means enabled, set to 0 to disable - static const char * ragged_fp16_env = getenv("GGML_OPENCL_MOE_RAGGED_FP16"); - backend_ctx->adreno_use_moe_ragged = (ragged_fp16_env == NULL) ? 1 : (atoi(ragged_fp16_env) != 0); +} - // ragged moe, tile-skip granularity (columns per skip-group): 8 = quarter (default), - // 16 = half (legacy), 32 = disabled. Override with GGML_OPENCL_MOE_RAGGED_GRAN={8,16,32} - static const char * ragged_gran_env = getenv("GGML_OPENCL_MOE_RAGGED_GRAN"); - backend_ctx->adreno_moe_ragged_skip_gran = (ragged_gran_env != NULL) ? atoi(ragged_gran_env) : 8; +static void sync_with_other_backends(ggml_backend_t backend) { + auto * backend_ctx = static_cast(backend->context); + sync_with_other_backends(backend_ctx); +} - // whether fuse moe combine - static const char * fuse_moe_bias_glu_env = getenv("GGML_OPENCL_FUSE_MOE_BIAS_GLU"); - backend_ctx->fuse_moe_bias_glu = fuse_moe_bias_glu_env == NULL ? 1 : (atoi(fuse_moe_bias_glu_env) != 0); +// True if two tensors share a device buffer with overlapping byte ranges. The pool +// allocator may place a fused op's output over a sequentially-dead input (safe for the +// original separate kernels, but a read/write race inside one fused kernel). +static bool ggml_cl_tensors_overlap(const ggml_tensor * x, const ggml_tensor * y) { + ggml_tensor_extra_cl * ex = (ggml_tensor_extra_cl *)x->extra; + ggml_tensor_extra_cl * ey = (ggml_tensor_extra_cl *)y->extra; + if (!ex || !ey || ex->data_device != ey->data_device) { return false; } + const cl_ulong xo = ex->offset + x->view_offs, xe = xo + ggml_nbytes(x); + const cl_ulong yo = ey->offset + y->view_offs, ye = yo + ggml_nbytes(y); + return xo < ye && yo < xe; +} - static const char * fuse_moe_bias_combine_env = getenv("GGML_OPENCL_FUSE_MOE_BIAS_COMBINE"); - backend_ctx->fuse_moe_bias_combine = fuse_moe_bias_combine_env == NULL ? 1 : (atoi(fuse_moe_bias_combine_env) != 0); +// Detect the MoE combine epilogue: router-weight MUL ([n_embd,k,nt] * [1,k,nt]) followed +// by k VIEWs of it and a (k-1)-long ADD reduction chain producing [n_embd, nt]. When it +// matches (and the output does not alias the inputs), the whole subgraph collapses to one +// weighted-sum-across-experts kernel. +static bool ggml_opencl_can_fuse_moe_combine(const struct ggml_cgraph * cgraph, int node_idx, + const ggml_tensor ** out_final_add) { + const ggml_tensor * mul = cgraph->nodes[node_idx]; + if (mul->op != GGML_OP_MUL) { return false; } + const ggml_tensor * experts = mul->src[0]; + const ggml_tensor * weights = mul->src[1]; + if (!experts || !weights) { return false; } + if (experts->type != GGML_TYPE_F32 || weights->type != GGML_TYPE_F32 || mul->type != GGML_TYPE_F32) { return false; } - static const char * fuse_moe_combine_env = getenv("GGML_OPENCL_FUSE_MOE_COMBINE"); - backend_ctx->fuse_moe_combine = fuse_moe_combine_env == NULL ? 1 : (atoi(fuse_moe_combine_env) != 0); + const int64_t n_embd = experts->ne[0]; + const int64_t k = experts->ne[1]; + const int64_t nt = experts->ne[2]; + if (k < 2 || k > 64 || experts->ne[3] != 1 || n_embd % 4 != 0) { return false; } + if (weights->ne[0] != 1 || weights->ne[1] != k || weights->ne[2] != nt || weights->ne[3] != 1) { return false; } + if (mul->ne[0] != n_embd || mul->ne[1] != k || mul->ne[2] != nt) { return false; } + // the fused kernel needs contiguous experts/weights and a contiguous 2D dst + if (!ggml_is_contiguous(experts) || !ggml_is_contiguous(weights)) { return false; } - // ragged moe dp4 variant - static const char * ragged_dp4_env = getenv("GGML_OPENCL_MOE_RAGGED"); - backend_ctx->adreno_use_moe_ragged_dp4 = ragged_dp4_env == NULL ? 1 : (atoi(ragged_dp4_env) != 0); + const int n_nodes = 1 + (int)k + (int)(k - 1); // MUL + k*VIEW + (k-1)*ADD + if (n_nodes >= 32) { return false; } + if (node_idx + n_nodes > cgraph->n_nodes) { return false; } -#ifdef GGML_OPENCL_USE_ADRENO_BIN_KERNELS - // try loading adreno binary kernels if enabled - // if fails to load, builtin kernels will be used - { - dl_handle * kernel_lib_handle = dl_load_library(KERNEL_LIB_NAME); - backend_ctx->adreno_use_bin_kernels = false; + enum ggml_op ops[1 + 64 + 63]; + int n = 0; + ops[n++] = GGML_OP_MUL; + for (int j = 0; j < (int)k; ++j) { ops[n++] = GGML_OP_VIEW; } + for (int j = 0; j < (int)k - 1; ++j) { ops[n++] = GGML_OP_ADD; } + const int outs[] = { node_idx + n_nodes - 1 }; + if (!ggml_can_fuse_subgraph(cgraph, node_idx, n_nodes, ops, outs, 1)) { return false; } - if (kernel_lib_handle) { - backend_ctx->get_adreno_bin_kernel_func = (get_adreno_bin_kernel_func_t)dl_get_sym(kernel_lib_handle, "get_adreno_kernels"); - if (backend_ctx->get_adreno_bin_kernel_func) { - GGML_LOG_INFO("ggml_opencl: loaded bin kernel library %s\n", KERNEL_LIB_NAME); - backend_ctx->adreno_use_bin_kernels = true; - } else { - GGML_LOG_INFO("ggml_opencl: bin kernel library %s is invalid, will use builtin kernels\n", KERNEL_LIB_NAME); - } - } else { - GGML_LOG_INFO("ggml_opencl: failed to load %s, will use builtin kernels\n", KERNEL_LIB_NAME); - } + for (int j = 0; j < (int)k; ++j) { + const ggml_tensor * vw = cgraph->nodes[node_idx + 1 + j]; + if (vw->op != GGML_OP_VIEW || vw->src[0] != mul || vw->ne[0] != n_embd || vw->ne[1] != nt) { return false; } } -#endif // GGML_OPENCL_USE_ADRENO_BIN_KERNELS - - cl_int err; + const ggml_tensor * final_add = cgraph->nodes[node_idx + n_nodes - 1]; + if (final_add->op != GGML_OP_ADD || final_add->type != GGML_TYPE_F32 || + final_add->ne[0] != n_embd || final_add->ne[1] != nt || final_add->ne[2] != 1) { return false; } + if (!ggml_is_contiguous(final_add)) { return false; } + // the fused kernel reads experts + writes final_add in one pass; bail if the + // pool allocator overlapped the output with the (large) experts input -- would race. + // The small weights input is copied to a private scratch in the dispatch, so its own + // aliasing with the output is handled there and does not block the fusion. + if (ggml_cl_tensors_overlap(experts, final_add)) { return false; } - // A local ref of cl_context for convenience - cl_context context = backend_ctx->context = dev_ctx->context; + *out_final_add = final_add; + return true; +} - //CL_CHECK((queue = clCreateCommandQueue(context, device, CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE, &err), - // (err != CL_INVALID_QUEUE_PROPERTIES && err != CL_INVALID_VALUE ? err : - // (queue = clCreateCommandQueue(context, device, 0, &err), err) - //))); - cl_command_queue_properties command_queue_props = 0; -#ifdef GGML_OPENCL_PROFILING - command_queue_props |= CL_QUEUE_PROFILING_ENABLE; -#endif - CL_CHECK((backend_ctx->queue = clCreateCommandQueue(context, device, command_queue_props, &err), err)); +// Detect the gpt-oss MoE bias+activation epilogue on the PREFILL path: +// {MUL_MAT_ID(gate), ADD_ID(gate_bias), MUL_MAT_ID(up), ADD_ID(up_bias), GLU(swiglu_oai)}. +// The two matmuls still run as their own dispatches (the prefill GEMM is the vendor's); +// what collapses is the epilogue — both add_id passes are in-place read-modify-writes of a +// tensor the GLU immediately reads again, so they are three full passes over the same +// [n_ff, n_expert_used, n_tokens] f32 tensor where one suffices. +// +// The decode counterpart is handled by the mxfp4 fused GEMV arm in ggml_opencl_can_fuse, +// which folds the matmul too; this one deliberately fires only when that cannot (ne[2] > 1). +static bool ggml_opencl_can_fuse_moe_bias_glu(const struct ggml_cgraph * cgraph, int node_idx) { + if (node_idx + 4 >= cgraph->n_nodes) { + return false; + } - // delay kernel loading until the first buffer is created - // load_cl_kernels(backend_ctx.get()); + const enum ggml_op mg_ops[] = { GGML_OP_MUL_MAT_ID, GGML_OP_ADD_ID, GGML_OP_MUL_MAT_ID, GGML_OP_ADD_ID, GGML_OP_GLU }; + const int mg_out[] = { node_idx + 4 }; + if (!ggml_can_fuse_subgraph(cgraph, node_idx, 5, mg_ops, mg_out, 1)) { + return false; + } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // Allocate intermediate buffers and images - size_t required_A_q_d_bytes = 311164928; - size_t required_A_s_d_bytes = 38895616; - size_t required_B_d_bytes = 45088768; + const ggml_tensor * gmm = cgraph->nodes[node_idx]; + const ggml_tensor * gad = cgraph->nodes[node_idx+1]; + const ggml_tensor * umm = cgraph->nodes[node_idx+2]; + const ggml_tensor * uad = cgraph->nodes[node_idx+3]; + const ggml_tensor * glu = cgraph->nodes[node_idx+4]; - // Ensure buffer sizes do not exceed the maximum allocation size - size_t max_A_q_d_bytes = MIN(required_A_q_d_bytes, backend_ctx->max_alloc_size); - size_t max_A_s_d_bytes = MIN(required_A_s_d_bytes, backend_ctx->max_alloc_size); - size_t max_B_d_bytes = MIN(required_B_d_bytes, backend_ctx->max_alloc_size); - if (required_A_q_d_bytes > backend_ctx->max_alloc_size) { - GGML_LOG_WARN("ggml_opencl: A_q_d buffer size reduced from %zu to %zu due to device limitations.\n", - required_A_q_d_bytes, max_A_q_d_bytes); + if (ggml_get_glu_op(glu) != GGML_GLU_OP_SWIGLU_OAI) { + return false; } - if (required_A_s_d_bytes > backend_ctx->max_alloc_size) { - GGML_LOG_WARN("ggml_opencl: A_s_d buffer size reduced from %zu to %zu due to device limitations.\n", - required_A_s_d_bytes, max_A_s_d_bytes); + // Prefill only — at one token the mxfp4 arm above folds the matmul as well. + if (gmm->src[1]->ne[2] == 1) { + return false; } - if (required_B_d_bytes > backend_ctx->max_alloc_size) { - GGML_LOG_WARN("ggml_opencl: B_d buffer size reduced from %zu to %zu due to device limitations.\n", - required_B_d_bytes, max_B_d_bytes); + // Wiring: both matmuls share the activation and the expert selection, each add_id + // biases its own matmul, and the GLU consumes the two biased results as separate + // operands (so the same-buffer ne00_off/ne10_off split path is not in play). + if (gad->src[0] != gmm || uad->src[0] != umm || + glu->src[0] != gad || glu->src[1] != uad || + umm->src[1] != gmm->src[1] || umm->src[2] != gmm->src[2]) { + return false; } - - backend_ctx->prealloc_quant_trans.allocate(context, max_A_q_d_bytes); - backend_ctx->prealloc_scales_trans.allocate(context, max_A_s_d_bytes); - backend_ctx->prealloc_act_trans.allocate(context, max_B_d_bytes); -#endif // GGML_OPENCL_USE_ADRENO_KERNELS - - backend_ctx->disable_fusion = getenv("GGML_OPENCL_DISABLE_FUSION") != nullptr; - if (const char * env = getenv("GGML_OPENCL_FUSE_MM_GLU")) { - backend_ctx->fuse_mm_glu = atoi(env) != 0; + // A swapped GLU would exchange the gate/up roles the fused kernel hard-codes. + if (ggml_get_op_params_i32(glu, 1)) { + return false; } - if (const char * env = getenv("GGML_OPENCL_FUSE_RMS_ADD")) { - backend_ctx->fuse_rms_add = atoi(env) != 0; + if (gad->type != GGML_TYPE_F32 || uad->type != GGML_TYPE_F32 || glu->type != GGML_TYPE_F32) { + return false; } - if (const char * env = getenv("GGML_OPENCL_F16_MROW")) { - backend_ctx->f16_mrow = atoi(env) != 0; + if (!gad->src[1] || gad->src[1]->type != GGML_TYPE_F32 || + !uad->src[1] || uad->src[1]->type != GGML_TYPE_F32) { + return false; } - if (const char * env = getenv("GGML_OPENCL_F16_MROW_RPT")) { - const int v = atoi(env); - backend_ctx->f16_mrow_rpt = (v == 2 || v == 4 || v == 8 || v == 16) ? v : 1; + if (!gad->src[2] || gad->src[2]->type != GGML_TYPE_I32 || uad->src[2] != gad->src[2]) { + return false; } - - dev_ctx->backend_ctx = backend_ctx.release(); - return dev_ctx->backend_ctx; -} - -static void ggml_cl_free(ggml_backend_t backend) { - ggml_backend_opencl_context * ctx = (ggml_backend_opencl_context *) backend->context; - ctx->free(); + // Full width on both operands: the kernel writes one output element per input pair. + if (!ggml_are_same_shape(gad, uad) || glu->ne[0] != gad->ne[0] || + glu->ne[1] != gad->ne[1] || glu->ne[2] != gad->ne[2] || glu->ne[3] != gad->ne[3]) { + return false; + } + if (gad->ne[3] != 1) { + return false; + } + // The destination is addressed by (expert slot, token) rather than the GLU's flat row + // walk; those agree only for a contiguous destination. + if (!ggml_is_contiguous(glu) || !ggml_is_contiguous(gmm) || !ggml_is_contiguous(umm)) { + return false; + } + return true; } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void transpose_2d( - ggml_backend_opencl_context * backend_ctx, - cl_kernel kernel, - cl_mem src, cl_mem dst, size_t size, - cl_int stride, cl_int rows, - bool blocking = true, - bool auto_local = false // let driver pick local size for non-uniform workgroups -) { - static ggml_cl_buffer buf; - - cl_event evt; - cl_int err; - - buf.allocate(backend_ctx->context, size); - - cl_mem trans; - cl_buffer_region region; - - region.origin = 0; - region.size = size; - CL_CHECK((trans = clCreateSubBuffer( - buf.buffer, CL_MEM_READ_WRITE, - CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &src)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_int), &stride)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_int), &rows)); +static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst); - size_t local_size[3] = {64, 1, 1}; - size_t global_size[3] = {(size_t)stride, (size_t)rows, 1};; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, - global_size, auto_local ? NULL : local_size, 0, NULL, NULL)); +// Runs the gate and up matmuls unchanged, then one kernel in place of +// add_id(gate) + add_id(up) + swiglu_oai. See ggml_opencl_can_fuse_moe_bias_glu. +static void ggml_cl_moe_bias_glu_fused(ggml_backend_t backend, ggml_tensor * gate_mm, const ggml_tensor * gate_add, + ggml_tensor * up_mm, const ggml_tensor * up_add, const ggml_tensor * glu) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; - if (blocking) { - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, trans, dst, 0, 0, size, 0, NULL, &evt)); - CL_CHECK(clWaitForEvents(1, &evt)); - CL_CHECK(clReleaseEvent(evt)); - } else { - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, trans, dst, 0, 0, size, 0, NULL, NULL)); - } + ggml_cl_mul_mat_id(backend, gate_mm->src[0], gate_mm->src[1], gate_mm); + ggml_cl_mul_mat_id(backend, up_mm->src[0], up_mm->src[1], up_mm); - CL_CHECK(clReleaseMemObject(trans)); -} + const ggml_tensor * gbias = gate_add->src[1]; + const ggml_tensor * ubias = up_add->src[1]; + const ggml_tensor * ids = gate_add->src[2]; -static void transpose_2d_as_8b( - ggml_backend_opencl_context * backend_ctx, - cl_mem src, cl_mem dst, size_t size, - cl_int stride, cl_int rows, - bool blocking = true, - bool auto_local = false -) { - transpose_2d(backend_ctx, backend_ctx->kernel_transpose_8_buf, - src, dst, size, stride, rows, blocking, auto_local); -} + ggml_tensor_extra_cl * eg = (ggml_tensor_extra_cl *)gate_mm->extra; + ggml_tensor_extra_cl * egb = (ggml_tensor_extra_cl *)gbias->extra; + ggml_tensor_extra_cl * eu = (ggml_tensor_extra_cl *)up_mm->extra; + ggml_tensor_extra_cl * eub = (ggml_tensor_extra_cl *)ubias->extra; + ggml_tensor_extra_cl * ei = (ggml_tensor_extra_cl *)ids->extra; + ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)glu->extra; -static void transpose_2d_as_16b( - ggml_backend_opencl_context * backend_ctx, - cl_mem src, cl_mem dst, size_t size, - cl_int stride, cl_int rows, - bool blocking = true -) { - transpose_2d(backend_ctx, backend_ctx->kernel_transpose_16_buf, - src, dst, size, stride, rows, blocking); -} + cl_ulong off_g = eg->offset + gate_mm->view_offs; + cl_ulong off_gb = egb->offset + gbias->view_offs; + cl_ulong off_u = eu->offset + up_mm->view_offs; + cl_ulong off_ub = eub->offset + ubias->view_offs; + cl_ulong off_i = ei->offset + ids->view_offs; + cl_ulong off_d = ed->offset + glu->view_offs; -static void transpose_2d_as_32b( - ggml_backend_opencl_context * backend_ctx, - cl_mem src, cl_mem dst, size_t size, - cl_int stride, cl_int rows, - bool blocking = true -) { - transpose_2d(backend_ctx, backend_ctx->kernel_transpose_32_buf, - src, dst, size, stride, rows, blocking); -} -#endif // GGML_OPENCL_USE_ADRENO_KERNELS + const cl_ulong nb01_g = gate_mm->nb[1]; + const cl_ulong nb02_g = gate_mm->nb[2]; + const cl_ulong nb01_u = up_mm->nb[1]; + const cl_ulong nb02_u = up_mm->nb[2]; + const cl_ulong nb11_g = gbias->nb[1]; + const cl_ulong nb11_u = ubias->nb[1]; + const cl_ulong nb21 = ids->nb[1]; + const cl_ulong nbd1 = glu->nb[1]; + const cl_ulong nbd2 = glu->nb[2]; -//------------------------------------------------------------------------------ -// Tensor extra management -//------------------------------------------------------------------------------ -struct ggml_tensor_extra_cl { - // The buffer object that holds the data. - cl_mem data_device; - // The offset into the buffer object. This is primarily for scratch buffer - // and view operation. - // NB: this offset no longer includes view offset (view_offs). Whenever this - // offset is used, view_offs should be considered. - cl_ulong offset; - // The actual size of the cl_mem object. This is needed when returning the - // block to the pool. - size_t actual_size; + const int ne0 = (int)glu->ne[0]; + const float alpha = ggml_get_op_params_f32(glu, 2); + const float limit = ggml_get_op_params_f32(glu, 3); - void reset() { - data_device = nullptr; - offset = 0; - actual_size = 0; - } -}; + cl_kernel kernel = backend_ctx->kernel_add_id_add_id_swiglu_oai; -struct ggml_tensor_extra_cl_q1_0 { - cl_mem q = nullptr; - cl_mem q_img = nullptr; + int i = 0; + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eg->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_g)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &egb->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_gb)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eu->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_u)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eub->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_ub)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &ei->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_i)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &ed->data_device)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_d)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb01_g)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb02_g)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb01_u)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb02_u)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb11_g)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb11_u)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nbd1)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nbd2)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(float), &limit)); + CL_CHECK(clSetKernelArg(kernel, i++, sizeof(float), &alpha)); - cl_mem d = nullptr; - cl_mem d_img = nullptr; + const int nth = MIN(ne0, (int) backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global_work_size[] = { (size_t)glu->ne[1]*nth, (size_t)glu->ne[2], 1 }; + size_t local_work_size[] = { (size_t)nth, 1, 1 }; - size_t size_q = 0; - size_t size_d = 0; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, glu); +} - ~ggml_tensor_extra_cl_q1_0() { - reset(); +// Fusion B: the MoE down-projection bias add feeding the combine. +// +// The graph runs ADD_ID(down_bias) and then immediately the combine subgraph +// {MUL(router weights), k VIEWs, k-1 ADDs}, and the ADD_ID's only consumer is that +// MUL. Since the ADD_ID is an in-place read-modify-write of a tensor the combine +// reads once more, the bias can be added inside the combine instead, dropping a +// full pass over [n_embd, k, n_tokens]. +// +// Shape checks for the combine tail are delegated to ggml_opencl_can_fuse_moe_combine +// (which also owns the n_nodes >= 32 bail and the experts/dst aliasing bail); what is +// added here is the ADD_ID wiring plus a subgraph check over the WHOLE run, so that +// the intermediate bias result is confirmed not to escape. +static bool ggml_opencl_can_fuse_moe_bias_combine(const struct ggml_cgraph * cgraph, int node_idx, + const ggml_tensor ** out_final_add) { + if (node_idx + 1 >= cgraph->n_nodes) { + return false; } - - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - q_img = nullptr; - d_img = nullptr; - size_q = 0; - size_d = 0; + const ggml_tensor * add = cgraph->nodes[node_idx]; + if (add->op != GGML_OP_ADD_ID) { + return false; } -}; - -// Additional tensor extra structs for quantized tensors. -// These tensors are loaded from files and should not be allocated in scratch -- -// they should always be allocated from the pool. Hence, they do not have an -// `offset`, which indicate their locations in the scratch buffer. -struct ggml_tensor_extra_cl_q4_0 { - // Quantized values. - cl_mem q = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem q_img = nullptr; - // Scales. - cl_mem d = nullptr; - // Scales in image1d_buffer_t. - cl_mem d_img = nullptr; - // Size of quantized values. - size_t size_q = 0; - // Size of scales. - size_t size_d = 0; - - ~ggml_tensor_extra_cl_q4_0() { - reset(); + const ggml_tensor * mul = cgraph->nodes[node_idx+1]; + if (mul->op != GGML_OP_MUL || mul->src[0] != add) { + return false; } - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q_img)); - q_img = nullptr; - } - if (d_img != nullptr) { - CL_CHECK(clReleaseMemObject(d_img)); - d_img = nullptr; - } - size_q = 0; - size_d = 0; + const ggml_tensor * final_add = NULL; + if (!ggml_opencl_can_fuse_moe_combine(cgraph, node_idx+1, &final_add)) { + return false; } -}; - -struct ggml_tensor_extra_cl_q4_1 { - // Quantized values. - cl_mem q = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem q_img = nullptr; - // Scales. - cl_mem d = nullptr; - // Scales in image1d_buffer_t. - cl_mem d_img = nullptr; - // Min - cl_mem m = nullptr; - // Min in image1d_buffer_t. - cl_mem m_img = nullptr; - // Size of quantized values. - size_t size_q = 0; - // Size of scales. - size_t size_d = 0; - // Size of min values. - size_t size_m = 0; - ~ggml_tensor_extra_cl_q4_1() { - reset(); + const ggml_tensor * raw = add->src[0]; + const ggml_tensor * bias = add->src[1]; + const ggml_tensor * ids = add->src[2]; + if (!raw || !bias || !ids) { + return false; } - - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (m != nullptr) { - CL_CHECK(clReleaseMemObject(m)); - m = nullptr; - } - if (q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q_img)); - q_img = nullptr; - } - // Currently, q_img and d_img are only initialized when SMALL_ALLOC is - // enabled. They point to the images in ggml_backend_opencl_buffer_context. - // So, there is no need to release them here. - // TODO: initialize them for non SMALL_PATH path, or remove them. - d_img = nullptr; - m_img = nullptr; - size_q = 0; - size_d = 0; - size_m = 0; + if (raw->type != GGML_TYPE_F32 || bias->type != GGML_TYPE_F32 || + ids->type != GGML_TYPE_I32 || add->type != GGML_TYPE_F32) { + return false; } -}; - -struct ggml_tensor_extra_cl_q5_0 { - // Quantized values. - cl_mem qs = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem qs_img = nullptr; - // 5-th bit values. - cl_mem qh = nullptr; - // 5-th bit values in image1d_buffer_t. - cl_mem qh_img = nullptr; - // Scales. - cl_mem d = nullptr; - // Scales in image1d_buffer_t. - cl_mem d_img = nullptr; - // Uniform per-32-block scale (2/block) + min (1/block, = d*16 for the -16 centering) - // for the generic dp4a MoE GEMM. Built from d. - cl_mem scale = nullptr; - cl_mem min = nullptr; - // Size of quantized values. - size_t size_qs = 0; - // Size of 5-th bit values. - size_t size_qh = 0; - // Size of scales. - size_t size_d = 0; - - ~ggml_tensor_extra_cl_q5_0() { - reset(); + // The combine reads the raw matmul output with the strides it computed from the + // add_id result, so the two must have the same layout. + if (!ggml_are_same_shape(raw, add) || !ggml_is_contiguous(raw)) { + return false; + } + if (raw->nb[1] != add->nb[1] || raw->nb[2] != add->nb[2]) { + return false; + } + // ids is indexed as [expert slot, token]; the combine walks the same two axes. + if (ids->ne[0] < add->ne[1] || ids->ne[1] < add->ne[2]) { + return false; } - void reset() { - if (qs != nullptr) { - CL_CHECK(clReleaseMemObject(qs)); - qs = nullptr; - } - if (qh != nullptr) { - CL_CHECK(clReleaseMemObject(qh)); - qh = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (qs_img != nullptr) { - CL_CHECK(clReleaseMemObject(qs_img)); - qs_img = nullptr; - } - if (scale != nullptr) { - CL_CHECK(clReleaseMemObject(scale)); - scale = nullptr; - } - if (min != nullptr) { - CL_CHECK(clReleaseMemObject(min)); - min = nullptr; - } - - qh_img = nullptr; - d_img = nullptr; - size_qs = 0; - size_qh = 0; - size_d = 0; + // Whole-run escape check: ADD_ID + MUL + k VIEWs + (k-1) ADDs, only the last node escapes. + const int k = (int)add->ne[1]; + const int n_nodes = 2 + k + (k - 1); + if (n_nodes >= 32 || node_idx + n_nodes > cgraph->n_nodes) { + return false; + } + enum ggml_op ops[32]; + int n = 0; + ops[n++] = GGML_OP_ADD_ID; + ops[n++] = GGML_OP_MUL; + for (int j = 0; j < k; ++j) ops[n++] = GGML_OP_VIEW; + for (int j = 0; j < k - 1; ++j) ops[n++] = GGML_OP_ADD; + const int outs[] = { node_idx + n_nodes - 1 }; + if (!ggml_can_fuse_subgraph(cgraph, node_idx, n_nodes, ops, outs, 1)) { + return false; } -}; -struct ggml_tensor_extra_cl_q5_1 { - // Quantized values. - cl_mem qs = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem qs_img = nullptr; - // 5-th bit values. - cl_mem qh = nullptr; - // 5-th bit values in image1d_buffer_t. - cl_mem qh_img = nullptr; - // Scales. - cl_mem d = nullptr; - // Scales in image1d_buffer_t. - cl_mem d_img = nullptr; - // Min - cl_mem m = nullptr; - // Min in image1d_buffer_t. - cl_mem m_img = nullptr; - // Size of quantized values. - size_t size_qs = 0; - // Size of 5-th bit values. - size_t size_qh = 0; - // Size of scales. - size_t size_d = 0; - // Size of min values. - size_t size_m = 0; + *out_final_add = final_add; + return true; +} - ~ggml_tensor_extra_cl_q5_1() { - reset(); - } - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (qs != nullptr) { - CL_CHECK(clReleaseMemObject(qs)); - qs = nullptr; - } - if (qh != nullptr) { - CL_CHECK(clReleaseMemObject(qh)); - qh = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (m != nullptr) { - CL_CHECK(clReleaseMemObject(m)); - m = nullptr; - } - if (qs_img != nullptr) { - CL_CHECK(clReleaseMemObject(qs_img)); - qs_img = nullptr; - } - // qh_img, d_img, and m_img are not currently allocated separately. - // TODO: initialize them for non SMALL_PATH path, or remove them. - qh_img = nullptr; - d_img = nullptr; - m_img = nullptr; - size_qs = 0; - size_qh = 0; - size_d = 0; - size_m = 0; - } -}; +// Fusion B dispatch: the combine, reading the RAW matmul output and adding the +// per-expert bias row inline. See ggml_opencl_can_fuse_moe_bias_combine. +static void ggml_cl_moe_bias_combine_fused(ggml_backend_t backend, const ggml_tensor * add, + const ggml_tensor * mul, const ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; -struct ggml_tensor_extra_cl_mxfp4 { - // Quantized values. - cl_mem q = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem q_img = nullptr; - // Scales in E8M0. - cl_mem e = nullptr; - // Scales in image1d_buffer_t. - cl_mem e_img = nullptr; - // Size of quantized values. - size_t size_q = 0; - // Size of scales. - size_t size_e = 0; + const ggml_tensor * experts = add->src[0]; // raw matmul output, bias not yet applied + const ggml_tensor * bias = add->src[1]; + const ggml_tensor * ids = add->src[2]; + const ggml_tensor * weights = mul->src[1]; - ~ggml_tensor_extra_cl_mxfp4() { - reset(); - } + ggml_tensor_extra_cl * ee = (ggml_tensor_extra_cl *)experts->extra; + ggml_tensor_extra_cl * eb = (ggml_tensor_extra_cl *)bias->extra; + ggml_tensor_extra_cl * ei = (ggml_tensor_extra_cl *)ids->extra; + ggml_tensor_extra_cl * ew = (ggml_tensor_extra_cl *)weights->extra; + ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)dst->extra; + cl_ulong off_e = ee->offset + experts->view_offs; + cl_ulong off_b = eb->offset + bias->view_offs; + cl_ulong off_i = ei->offset + ids->view_offs; + cl_ulong off_w = ew->offset + weights->view_offs; + cl_ulong off_d = ed->offset + dst->view_offs; - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (e != nullptr) { - CL_CHECK(clReleaseMemObject(e)); - e = nullptr; - } - if (q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q_img)); - q_img = nullptr; - } - // Currently, e_img is not used. They can be image1d_buffer_t - // that wraps around q and d to utilize image access path. - e_img = nullptr; - size_q = 0; - size_e = 0; - } -}; + const int n_embd4 = (int)(experts->ne[0] / 4); + const int k = (int)experts->ne[1]; + const int nt = (int)experts->ne[2]; + const cl_uint e1 = (cl_uint)(experts->nb[1] / sizeof(float)); + const cl_uint e2 = (cl_uint)(experts->nb[2] / sizeof(float)); + const cl_uint w1 = (cl_uint)(weights->nb[1] / sizeof(float)); + const cl_uint w2 = (cl_uint)(weights->nb[2] / sizeof(float)); + const cl_uint d1 = (cl_uint)(dst->nb[1] / sizeof(float)); + const cl_ulong nb_b1 = bias->nb[1]; + const cl_ulong nb_i1 = ids->nb[1]; -struct ggml_tensor_extra_cl_q8_0 { - cl_mem q = nullptr; - cl_mem q_img = nullptr; + const size_t w_bytes = ggml_nbytes(weights); + backend_ctx->prealloc_moe_combine_w.allocate(backend_ctx->context, w_bytes); + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, ew->data_device, backend_ctx->prealloc_moe_combine_w.buffer, + off_w, 0, w_bytes, 0, NULL, NULL)); + cl_mem w_dev = backend_ctx->prealloc_moe_combine_w.buffer; + cl_ulong w_off = 0; - cl_mem d = nullptr; - cl_mem d_img = nullptr; + cl_kernel kernel = backend_ctx->kernel_moe_combine_bias_f32; + int a = 0; + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ee->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_e)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &w_dev)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &w_off)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &eb->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_b)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ei->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_i)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ed->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_d)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &n_embd4)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &nt)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e2)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w2)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &d1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &nb_b1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &nb_i1)); - // Uniform per-16-segment scale (16/superblock) for the generic dp4a MoE GEMM. - // Expanded from d at set_tensor; the int8 codes are reused from q. - // q8_0 is symmetric so no min buffer (has_min=0). - cl_mem scale = nullptr; + size_t lws[2] = { 64, 1 }; + size_t gws[2] = { (size_t)(((n_embd4 + 63) / 64) * 64), (size_t)nt }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, gws, lws, dst); +} - size_t size_q = 0; - size_t size_d = 0; - ~ggml_tensor_extra_cl_q8_0() { - reset(); - } +static void ggml_cl_moe_combine_fused(ggml_backend_t backend, const ggml_tensor * mul, const ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + const ggml_tensor * experts = mul->src[0]; + const ggml_tensor * weights = mul->src[1]; - void reset() { - // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. - // They must be properly released so that the original buffer can be - // properly released to avoid memory leak. - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (scale != nullptr) { - CL_CHECK(clReleaseMemObject(scale)); - scale = nullptr; - } - // Currently, q_img and d_img are not used. They can be image1d_buffer_t - // that wraps around q and d to utilize image access path. - q_img = nullptr; - d_img = nullptr; - size_q = 0; - size_d = 0; - } -}; + ggml_tensor_extra_cl * ee = (ggml_tensor_extra_cl *)experts->extra; + ggml_tensor_extra_cl * ew = (ggml_tensor_extra_cl *)weights->extra; + ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)dst->extra; + cl_ulong off_e = ee->offset + experts->view_offs; + cl_ulong off_w = ew->offset + weights->view_offs; + cl_ulong off_d = ed->offset + dst->view_offs; -struct ggml_tensor_extra_cl_iq4_nl { - cl_mem q = nullptr; - cl_mem q_img = nullptr; + const int n_embd4 = (int)(experts->ne[0] / 4); + const int k = (int)experts->ne[1]; + const int nt = (int)experts->ne[2]; + const cl_uint e1 = (cl_uint)(experts->nb[1] / sizeof(float)); + const cl_uint e2 = (cl_uint)(experts->nb[2] / sizeof(float)); + const cl_uint w1 = (cl_uint)(weights->nb[1] / sizeof(float)); + const cl_uint w2 = (cl_uint)(weights->nb[2] / sizeof(float)); + const cl_uint d1 = (cl_uint)(dst->nb[1] / sizeof(float)); - cl_mem d = nullptr; - cl_mem d_img = nullptr; + // The router weights are tiny ([1,k,nt]) and may share a pool buffer with the output; + // copy them into a private scratch so the fused kernel never reads aliased memory. + const size_t w_bytes = ggml_nbytes(weights); + backend_ctx->prealloc_moe_combine_w.allocate(backend_ctx->context, w_bytes); + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, ew->data_device, backend_ctx->prealloc_moe_combine_w.buffer, + off_w, 0, w_bytes, 0, NULL, NULL)); + cl_mem w_dev = backend_ctx->prealloc_moe_combine_w.buffer; + cl_ulong w_off = 0; + + cl_kernel kernel = backend_ctx->kernel_moe_combine_f32; + int a = 0; + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ee->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_e)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &w_dev)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &w_off)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ed->data_device)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_d)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &n_embd4)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &nt)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e2)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w1)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w2)); + CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &d1)); - size_t size_q = 0; - size_t size_d = 0; + size_t lws[2] = { 64, 1 }; + size_t gws[2] = { (size_t)(((n_embd4 + 63) / 64) * 64), (size_t)nt }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, gws, lws, dst); +} - ~ggml_tensor_extra_cl_iq4_nl() { - reset(); - } +inline bool use_q4k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below (used by the GLU-subgraph fuse check) +inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); +inline bool use_adreno_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below - void reset() { - if (q != nullptr) { CL_CHECK(clReleaseMemObject(q)); q = nullptr; } - if (d != nullptr) { CL_CHECK(clReleaseMemObject(d)); d = nullptr; } - q_img = nullptr; - d_img = nullptr; - size_q = 0; - size_d = 0; - } -}; +static bool ggml_opencl_can_fuse(const ggml_backend_opencl_context * backend_ctx, const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops) { -struct ggml_tensor_extra_cl_q4_K { - // Quantized values - cl_mem q = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem q_img = nullptr; - // Scales for each super block. - cl_mem s = nullptr; - // Scales - cl_mem d = nullptr; - // Min - cl_mem dm = nullptr; + // glu(mul_mat(Wg,x), mul_mat(Wu,x)) — the FFN gate/up GEMVs + GLU. This is a + // non-linear subgraph (up does NOT consume gate), so the contiguous + // ggml_can_fuse below rejects it; use ggml_can_fuse_subgraph with the glu as + // the sole output and validate the edges explicitly. q4_K decode only; + // byte-identical to the per-op path. + if (ops.size() == 3 && ops.begin()[0] == GGML_OP_MUL_MAT && + ops.begin()[1] == GGML_OP_MUL_MAT && ops.begin()[2] == GGML_OP_GLU) { + const enum ggml_op glu_ops[] = { GGML_OP_MUL_MAT, GGML_OP_MUL_MAT, GGML_OP_GLU }; + const int glu_out[] = { node_idx + 2 }; + if (!ggml_can_fuse_subgraph(cgraph, node_idx, 3, glu_ops, glu_out, 1)) { + return false; + } - ~ggml_tensor_extra_cl_q4_K() { - reset(); - } + const ggml_tensor *gate = cgraph->nodes[node_idx]; + const ggml_tensor *up = cgraph->nodes[node_idx+1]; + const ggml_tensor *glu = cgraph->nodes[node_idx+2]; - void reset() { - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; + // decode GEMV path only (single token); prefill GEMM is separate + if (gate->ne[1] != 1 || up->ne[1] != 1) { + return false; } - if (s != nullptr) { - CL_CHECK(clReleaseMemObject(s)); - s = nullptr; + // both projections must be q4_K weights, f32 activation/output + if (gate->src[0]->type != GGML_TYPE_Q4_K || up->src[0]->type != GGML_TYPE_Q4_K || + gate->src[1]->type != GGML_TYPE_F32 || up->src[1]->type != GGML_TYPE_F32 || + gate->type != GGML_TYPE_F32 || up->type != GGML_TYPE_F32 || glu->type != GGML_TYPE_F32) { + return false; } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; + // gate and up must share the same activation and have matching shape/stride + if (gate->src[1] != up->src[1] || + !ggml_are_same_shape(gate->src[0], up->src[0]) || + !ggml_are_same_stride(gate->src[0], up->src[0])) { + return false; } - if (dm != nullptr) { - CL_CHECK(clReleaseMemObject(dm)); - dm = nullptr; + // GLU must read gate as src[0] and up as src[1], no swap (the fused + // epilogue applies the activation to gate, multiplies by up) + if (glu->src[0] != gate || glu->src[1] != up) { + return false; } - if (q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q_img)); - q_img = nullptr; + if (ggml_get_op_params_i32(glu, 1) /* swapped */) { + return false; + } + // SWIGLU_OAI carries extra alpha/limit params -> not handled by the fused kernel + if (ggml_get_glu_op(glu) == GGML_GLU_OP_SWIGLU_OAI) { + return false; + } + // the fused kernel reads the standard noshuffle image layout; the tiled + // layout packs weights differently -> defer those to the per-op path + if (use_q4k_tiled(backend_ctx, gate->src[0]) || use_q4k_tiled(backend_ctx, up->src[0])) { + return false; + } + // q4_K bin kernel requires 32b transposed layout, not compatible with the fused gemv + if (use_q4_k_bin_kernels(backend_ctx, gate->src[0]) || use_q4_k_bin_kernels(backend_ctx, up->src[0])) { + return false; + } + // that noshuffle layout is only produced at set_tensor time when + // use_adreno_kernels() accepts the weight (ne0 >= 512 && ne1 >= 512). + // Smaller weights stay in the plain q4_K layout, which this kernel would + // misread -> defer them to the per-op path. Real FFN gate/up weights are + // far above the threshold, so production dispatch is unchanged. + if (!use_adreno_kernels(backend_ctx, gate->src[0]) || + !use_adreno_kernels(backend_ctx, up->src[0])) { + return false; } + return true; } -}; -struct ggml_tensor_extra_cl_q5_K { - // Lower 4 bits of quantized weights. - cl_mem q = nullptr; - // Quantized values in image1d_buffer_t. - cl_mem q_img = nullptr; - // Upper 1 bit of quantized weights. - cl_mem qh = nullptr; - // Scales for each block. - cl_mem s = nullptr; - // Scales for each super block. - cl_mem d = nullptr; - // Min for each super block. - cl_mem dm = nullptr; - // Uniform per-32-block scale (2/block) + min (1/block, = dm*mn) decoded from the - // 6-bit packed s[] for the generic dp4a MoE GEMM kernel_gemm_moe_q8_1_dp4a. - // Built from s/d/dm at set_tensor; q/qh are reused as-is. - cl_mem scale = nullptr; - cl_mem min = nullptr; + if (!ggml_can_fuse(cgraph, node_idx, ops)) { + return false; + } - size_t size_q = 0; - size_t size_qh = 0; - size_t size_s = 0; - size_t size_d = 0; - size_t size_dm = 0; + if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; - ~ggml_tensor_extra_cl_q5_K() { - reset(); - } + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); - void reset() { - if (q != nullptr) { - CL_CHECK(clReleaseMemObject(q)); - q = nullptr; - } - if (qh != nullptr) { - CL_CHECK(clReleaseMemObject(qh)); - qh = nullptr; - } - if (s != nullptr) { - CL_CHECK(clReleaseMemObject(s)); - s = nullptr; - } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; - } - if (dm != nullptr) { - CL_CHECK(clReleaseMemObject(dm)); - dm = nullptr; - } - if (q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q_img)); - q_img = nullptr; + // rms_norm only supports f32 + if (mul->src[0]->type != GGML_TYPE_F32 || + mul->src[1]->type != GGML_TYPE_F32 || + mul->type != GGML_TYPE_F32) { + return false; } - if (scale != nullptr) { - CL_CHECK(clReleaseMemObject(scale)); - scale = nullptr; + + // if rms_norm is the B operand, then we don't handle broadcast + if (rms_norm == mul->src[1] && + !ggml_are_same_shape(mul->src[0], rms_norm)) { + return false; } - if (min != nullptr) { - CL_CHECK(clReleaseMemObject(min)); - min = nullptr; + + // rms_norm assumes contiguous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { + return false; } + } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { + const ggml_tensor *norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = cgraph->nodes[node_idx+2]; + const ggml_tensor *w = mul->src[0] == norm ? mul->src[1] : mul->src[0]; + const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; - size_q = 0; - size_qh = 0; - size_s = 0; - size_d = 0; - size_dm = 0; - } -}; + // norm fusion only supports F32 + if (norm->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { + return false; + } -struct ggml_tensor_extra_cl_q6_K { - // Lower 4 bits of quantized weights. - cl_mem ql = nullptr; - // Lower 4 bits as image1d_buffer_t - cl_mem ql_img = nullptr; - // Upper 2 bits of quantized weights. - cl_mem qh = nullptr; - // Upper 2 bits as image1d_buffer_t - cl_mem qh_img = nullptr; - // Scales for each block. - cl_mem s = nullptr; - // Scales for each super block. - cl_mem d = nullptr; + if (norm->src[0]->ne[0] % 4 != 0) { + return false; + } - size_t size_ql = 0; - size_t size_qh = 0; - size_t size_s = 0; - size_t size_d = 0; + if (!ggml_is_contiguous(norm->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { + return false; + } + } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { + // rms_norm(x) * w + b, fused (residual). Mirrors the RMS_NORM+MUL gate + // plus the residual-add operand's constraints. + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = cgraph->nodes[node_idx+2]; + const ggml_tensor *w = mul->src[0] == rms_norm ? mul->src[1] : mul->src[0]; + const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; - ~ggml_tensor_extra_cl_q6_K() { - reset(); - } + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); - void reset() { - if (ql != nullptr) { - CL_CHECK(clReleaseMemObject(ql)); - ql = nullptr; + if (w->type != GGML_TYPE_F32 || mul->type != GGML_TYPE_F32 || + b->type != GGML_TYPE_F32 || add->type != GGML_TYPE_F32) { + return false; } - if (qh != nullptr) { - CL_CHECK(clReleaseMemObject(qh)); - qh = nullptr; + if (rms_norm->src[0]->ne[0] % 4 != 0) { + return false; } - if (s != nullptr) { - CL_CHECK(clReleaseMemObject(s)); - s = nullptr; + // if rms_norm is the B operand of mul, broadcast is not handled + if (rms_norm == mul->src[1] && !ggml_are_same_shape(mul->src[0], rms_norm)) { + return false; } - if (d != nullptr) { - CL_CHECK(clReleaseMemObject(d)); - d = nullptr; + // the residual must match the normed output shape (no add broadcast) + if (!ggml_are_same_shape(b, add)) { + return false; } - if (ql_img != nullptr) { - CL_CHECK(clReleaseMemObject(ql_img)); - ql_img = nullptr; + // rms_norm assumes contiguous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1]) || + !ggml_is_contiguous_rows(b)) { + return false; } - if (qh_img != nullptr) { - CL_CHECK(clReleaseMemObject(qh_img)); - qh_img = nullptr; + } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_GROUP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { + const ggml_tensor *gn = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = cgraph->nodes[node_idx+2]; + const ggml_tensor *w = mul->src[0] == gn ? mul->src[1] : mul->src[0]; + const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; + + if (gn->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { + return false; } - size_ql = 0; - size_qh = 0; - size_s = 0; - size_d = 0; + if (!ggml_is_contiguous(gn->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { + return false; + } } -}; -//------------------------------------------------------------------------------ -// Backend API -//------------------------------------------------------------------------------ + return true; +} -// -// backend -// -static const char * ggml_backend_opencl_name(ggml_backend_t backend) { - return "OpenCL"; +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor); +static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); +static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); - UNUSED(backend); -} +static void ggml_cl_mul_mat_q4_k_glu_fused(ggml_backend_t backend, ggml_tensor * gate_tensor, ggml_tensor * up_tensor, ggml_tensor * glu_tensor) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + GGML_ASSERT(gate_tensor && up_tensor && glu_tensor); -static void ggml_backend_opencl_free(ggml_backend_t backend) { - ggml_cl_free(backend); -} + const ggml_tensor * Wg = gate_tensor->src[0]; + const ggml_tensor * Wu = up_tensor->src[0]; + const ggml_tensor * src1 = gate_tensor->src[1]; // == up_tensor->src[1] + const ggml_tensor * dst = glu_tensor; -static void ggml_backend_opencl_set_tensor_async(ggml_backend_t backend, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { - GGML_UNUSED(backend); - GGML_UNUSED(tensor); - GGML_UNUSED(data); - GGML_UNUSED(offset); - GGML_UNUSED(size); -} + GGML_ASSERT(Wg && Wg->extra); + GGML_ASSERT(Wu && Wu->extra); + GGML_ASSERT(src1 && src1->extra); + GGML_ASSERT(dst && dst->extra); -static void ggml_backend_opencl_get_tensor_async(ggml_backend_t backend, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { - GGML_UNUSED(backend); - GGML_UNUSED(tensor); - GGML_UNUSED(data); - GGML_UNUSED(offset); - GGML_UNUSED(size); -} + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; -static bool ggml_backend_opencl_cpy_tensor_async(ggml_backend_t backend, const ggml_tensor * src, ggml_tensor * dst) { - GGML_UNUSED(backend); - GGML_UNUSED(src); - GGML_UNUSED(dst); - return false; -} + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q4_K * extra_g = (ggml_tensor_extra_cl_q4_K *)Wg->extra; + ggml_tensor_extra_cl_q4_K * extra_u = (ggml_tensor_extra_cl_q4_K *)Wu->extra; -static void ggml_backend_opencl_synchronize(ggml_backend_t backend) { - auto * backend_ctx = static_cast(backend->context); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_event evt; - CL_CHECK(clEnqueueBarrierWithWaitList(backend_ctx->queue, 0, nullptr, &evt)); - CL_CHECK(clWaitForEvents(1, &evt)); - CL_CHECK(clReleaseEvent(evt)); -} + const int K = Wg->ne[0]; // ne00 + const int M = Wg->ne[1]; // ne01 (= ffn intermediate width) + const int N = 1; // decode GEMV -// Synchronizes the 'backend_ctx's device with others so that commands -// enqueued to it won't start until commands in the other devices have -// completed. -static void sync_with_other_backends(ggml_backend_opencl_context * backend_ctx) { - if (g_ggml_backend_opencl_devices.size() < 2) { - return; // No other devices to synchronize with. - } + const cl_uchar mask_d6 = 0x3F, mask_d4 = 0x0F, mask_hi2 = 0xC0; + const int glu_op = (int)ggml_get_glu_op(dst); - std::vector events; - events.reserve(g_ggml_backend_opencl_devices.size()); + cl_context context = backend_ctx->context; + cl_int err; + cl_image_format img_fmt; + cl_image_desc img_desc; + cl_buffer_region region; - for (ggml_backend_device & backend_dev : g_ggml_backend_opencl_devices) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) backend_dev.context; - auto * other_backend_ctx = dev_ctx->backend_ctx; + // q images for the two weight matrices (standard noshuffle layout) + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * K / 2 / 4; + img_desc.buffer = extra_g->q; + cl_mem qg_img = nullptr, qu_img = nullptr; + CL_CHECK((qg_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_desc.buffer = extra_u->q; + CL_CHECK((qu_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - if (backend_ctx != other_backend_ctx) { - cl_event ev; - CL_CHECK(clEnqueueMarkerWithWaitList(other_backend_ctx->queue, 0, nullptr, &ev)); - CL_CHECK(clFlush(other_backend_ctx->queue)); - events.push_back(ev); - } - } + // shared activation image (one column at decode) + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + cl_mem b_sub_buf = nullptr, b_img = nullptr; + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + img_fmt = { CL_RGBA, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - CL_CHECK(clEnqueueBarrierWithWaitList(backend_ctx->queue, events.size(), events.data(), nullptr)); - for (auto ev : events) { - CL_CHECK(clReleaseEvent(ev)); + cl_kernel kernel = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_glu; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qg_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra_g->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_g->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra_g->s)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &qu_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra_u->d)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra_u->dm)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extra_u->s)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_int), &K)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_int), &glu_op)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_uchar), &mask_hi2)); + + // K-split = nsg_y subgroups. HARD-CAP at 8 (512 work-items): the fused + // kernel's cross-subgroup reduce uses a float4 reduceLM (gate+up packed) = + // 2x the LDS of the base GEMV's float2 reduce, so 16 co-resident subgroups + // exceed the per-CU LDS budget on X2 and the WG barrier DEADLOCKS -> GPU TDR + // (reproduced on upstream gemma-4 E4B decode, K=2560 M=10240). This used to + // be masked: get_kernel_workgroup_size reported 896 for this kernel (so the + // cap loop fell to 8), but it now returns 1024 and the Adreno per-kernel WG + // query is unreliable (over-reports), so cap explicitly instead of trusting + // it. nsg_y < 16 also means the cross-subgroup accumulation grouping differs + // from the standalone wide (nsg=16) GEMV, so the output is coherent but NOT + // byte-identical to the per-op path. Keep the maxwg query as a further floor + // for any driver that reports < 512. + size_t maxwg = backend_ctx->get_kernel_workgroup_size(kernel); + size_t nsg_y = 8; + while (nsg_y > 1 && 64 * nsg_y > maxwg) { nsg_y >>= 1; } + size_t local_work_size[3] = { 64, nsg_y, 1 }; + size_t global_work_size[3] = { (size_t)CEIL_DIV(M / 2, 64) * 64, nsg_y, 1 }; + + if (getenv("GGML_OPENCL_FUSE_DEBUG")) { + static int dbg = 0; + if (dbg < 3) { fprintf(stderr, "[FUSE_MM_GLU] fired #%d K=%d M=%d glu_op=%d nsg=%zu maxwg=%zu\n", ++dbg, K, M, glu_op, nsg_y, maxwg); fflush(stderr); } } -} -static void sync_with_other_backends(ggml_backend_t backend) { - auto * backend_ctx = static_cast(backend->context); - sync_with_other_backends(backend_ctx); -} + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); -// True if two tensors share a device buffer with overlapping byte ranges. The pool -// allocator may place a fused op's output over a sequentially-dead input (safe for the -// original separate kernels, but a read/write race inside one fused kernel). -static bool ggml_cl_tensors_overlap(const ggml_tensor * x, const ggml_tensor * y) { - ggml_tensor_extra_cl * ex = (ggml_tensor_extra_cl *)x->extra; - ggml_tensor_extra_cl * ey = (ggml_tensor_extra_cl *)y->extra; - if (!ex || !ey || ex->data_device != ey->data_device) { return false; } - const cl_ulong xo = ex->offset + x->view_offs, xe = xo + ggml_nbytes(x); - const cl_ulong yo = ey->offset + y->view_offs, ye = yo + ggml_nbytes(y); - return xo < ye && yo < xe; + CL_CHECK(clReleaseMemObject(qg_img)); + CL_CHECK(clReleaseMemObject(qu_img)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +#else + GGML_UNUSED(backend); + GGML_UNUSED(gate_tensor); + GGML_UNUSED(up_tensor); + GGML_UNUSED(glu_tensor); +#endif } -// Detect the MoE combine epilogue: router-weight MUL ([n_embd,k,nt] * [1,k,nt]) followed -// by k VIEWs of it and a (k-1)-long ADD reduction chain producing [n_embd, nt]. When it -// matches (and the output does not alias the inputs), the whole subgraph collapses to one -// weighted-sum-across-experts kernel. -static bool ggml_opencl_can_fuse_moe_combine(const struct ggml_cgraph * cgraph, int node_idx, - const ggml_tensor ** out_final_add) { - const ggml_tensor * mul = cgraph->nodes[node_idx]; - if (mul->op != GGML_OP_MUL) { return false; } - const ggml_tensor * experts = mul->src[0]; - const ggml_tensor * weights = mul->src[1]; - if (!experts || !weights) { return false; } - if (experts->type != GGML_TYPE_F32 || weights->type != GGML_TYPE_F32 || mul->type != GGML_TYPE_F32) { return false; } - const int64_t n_embd = experts->ne[0]; - const int64_t k = experts->ne[1]; - const int64_t nt = experts->ne[2]; - if (k < 2 || k > 64 || experts->ne[3] != 1 || n_embd % 4 != 0) { return false; } - if (weights->ne[0] != 1 || weights->ne[1] != k || weights->ne[2] != nt || weights->ne[3] != 1) { return false; } - if (mul->ne[0] != n_embd || mul->ne[1] != k || mul->ne[2] != nt) { return false; } - // the fused kernel needs contiguous experts/weights and a contiguous 2D dst - if (!ggml_is_contiguous(experts) || !ggml_is_contiguous(weights)) { return false; } +static void ggml_opencl_op_rms_norm_mul_add_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { + GGML_ASSERT(rms_norm_tensor && mul_tensor && add_tensor); + + const ggml_tensor * src0 = rms_norm_tensor->src[0]; + const ggml_tensor * src1 = mul_tensor->src[0] == rms_norm_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; + const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; + const ggml_tensor * dst = add_tensor; + + GGML_ASSERT(src0 && src0->extra); + GGML_ASSERT(src1 && src1->extra); + GGML_ASSERT(src2 && src2->extra); + GGML_ASSERT(dst && dst->extra); + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + float eps; + memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); + + const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; + const cl_ulong nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; + const int ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3]; + const cl_ulong nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; + const int ne20 = src2->ne[0], ne21 = src2->ne[1], ne22 = src2->ne[2], ne23 = src2->ne[3]; + const cl_ulong nb21 = src2->nb[1], nb22 = src2->nb[2], nb23 = src2->nb[3]; + const cl_ulong nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3]; + + GGML_ASSERT(ne00 % 4 == 0); + + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) sgs = 64; + else if (backend_ctx->gpu_family == INTEL) sgs = 32; + else GGML_ASSERT(false && "Unsupported GPU"); - const int n_nodes = 1 + (int)k + (int)(k - 1); // MUL + k*VIEW + (k-1)*ADD - if (n_nodes >= 32) { return false; } - if (node_idx + n_nodes > cgraph->n_nodes) { return false; } + cl_kernel kernel = backend_ctx->kernel_rms_norm_mul_add; - enum ggml_op ops[1 + 64 + 63]; - int n = 0; - ops[n++] = GGML_OP_MUL; - for (int j = 0; j < (int)k; ++j) { ops[n++] = GGML_OP_VIEW; } - for (int j = 0; j < (int)k - 1; ++j) { ops[n++] = GGML_OP_ADD; } - const int outs[] = { node_idx + n_nodes - 1 }; - if (!ggml_can_fuse_subgraph(cgraph, node_idx, n_nodes, ops, outs, 1)) { return false; } + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00 && nth < max_workgroup_size) nth *= 2; + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00); - for (int j = 0; j < (int)k; ++j) { - const ggml_tensor * vw = cgraph->nodes[node_idx + 1 + j]; - if (vw->op != GGML_OP_VIEW || vw->src[0] != mul || vw->ne[0] != n_embd || vw->ne[1] != nt) { return false; } - } - const ggml_tensor * final_add = cgraph->nodes[node_idx + n_nodes - 1]; - if (final_add->op != GGML_OP_ADD || final_add->type != GGML_TYPE_F32 || - final_add->ne[0] != n_embd || final_add->ne[1] != nt || final_add->ne[2] != 1) { return false; } - if (!ggml_is_contiguous(final_add)) { return false; } - // the fused kernel reads experts + writes final_add in one pass; bail if the - // pool allocator overlapped the output with the (large) experts input -- would race. - // The small weights input is copied to a private scratch in the dispatch, so its own - // aliasing with the output is handled there and does not block the fusion. - if (ggml_cl_tensors_overlap(experts, final_add)) { return false; } + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; - *out_final_add = final_add; - return true; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne22)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne23)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb22)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb23)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(float)*sgs, NULL)); + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -// Detect the gpt-oss MoE bias+activation epilogue on the PREFILL path: -// {MUL_MAT_ID(gate), ADD_ID(gate_bias), MUL_MAT_ID(up), ADD_ID(up_bias), GLU(swiglu_oai)}. -// The two matmuls still run as their own dispatches (the prefill GEMM is the vendor's); -// what collapses is the epilogue — both add_id passes are in-place read-modify-writes of a -// tensor the GLU immediately reads again, so they are three full passes over the same -// [n_ff, n_expert_used, n_tokens] f32 tensor where one suffices. -// -// The decode counterpart is handled by the mxfp4 fused GEMV arm in ggml_opencl_can_fuse, -// which folds the matmul too; this one deliberately fires only when that cannot (ne[2] > 1). -static bool ggml_opencl_can_fuse_moe_bias_glu(const struct ggml_cgraph * cgraph, int node_idx) { - if (node_idx + 4 >= cgraph->n_nodes) { - return false; - } +static ggml_status ggml_backend_opencl_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - const enum ggml_op mg_ops[] = { GGML_OP_MUL_MAT_ID, GGML_OP_ADD_ID, GGML_OP_MUL_MAT_ID, GGML_OP_ADD_ID, GGML_OP_GLU }; - const int mg_out[] = { node_idx + 4 }; - if (!ggml_can_fuse_subgraph(cgraph, node_idx, 5, mg_ops, mg_out, 1)) { - return false; - } + for (int i = 0; i < cgraph->n_nodes; i++) { + ggml_tensor * node = cgraph->nodes[i]; - const ggml_tensor * gmm = cgraph->nodes[node_idx]; - const ggml_tensor * gad = cgraph->nodes[node_idx+1]; - const ggml_tensor * umm = cgraph->nodes[node_idx+2]; - const ggml_tensor * uad = cgraph->nodes[node_idx+3]; - const ggml_tensor * glu = cgraph->nodes[node_idx+4]; + // NOTE: this may oversynchronize by synchronizing with + // backends/devices which don't compute 'cgraph's + // dependencies. + sync_with_other_backends(backend); - if (ggml_get_glu_op(glu) != GGML_GLU_OP_SWIGLU_OAI) { - return false; - } - // Prefill only — at one token the mxfp4 arm above folds the matmul as well. - if (gmm->src[1]->ne[2] == 1) { - return false; - } - // Wiring: both matmuls share the activation and the expert selection, each add_id - // biases its own matmul, and the GLU consumes the two biased results as separate - // operands (so the same-buffer ne00_off/ne10_off split path is not in play). - if (gad->src[0] != gmm || uad->src[0] != umm || - glu->src[0] != gad || glu->src[1] != uad || - umm->src[1] != gmm->src[1] || umm->src[2] != gmm->src[2]) { - return false; - } - // A swapped GLU would exchange the gate/up roles the fused kernel hard-codes. - if (ggml_get_op_params_i32(glu, 1)) { - return false; - } - if (gad->type != GGML_TYPE_F32 || uad->type != GGML_TYPE_F32 || glu->type != GGML_TYPE_F32) { - return false; - } - if (!gad->src[1] || gad->src[1]->type != GGML_TYPE_F32 || - !uad->src[1] || uad->src[1]->type != GGML_TYPE_F32) { - return false; - } - if (!gad->src[2] || gad->src[2]->type != GGML_TYPE_I32 || uad->src[2] != gad->src[2]) { - return false; - } - // Full width on both operands: the kernel writes one output element per input pair. - if (!ggml_are_same_shape(gad, uad) || glu->ne[0] != gad->ne[0] || - glu->ne[1] != gad->ne[1] || glu->ne[2] != gad->ne[2] || glu->ne[3] != gad->ne[3]) { - return false; - } - if (gad->ne[3] != 1) { - return false; - } - // The destination is addressed by (expert slot, token) rather than the GLU's flat row - // walk; those agree only for a contiguous destination. - if (!ggml_is_contiguous(glu) || !ggml_is_contiguous(gmm) || !ggml_is_contiguous(umm)) { - return false; - } - return true; -} + if (ggml_is_empty(node) || node->op == GGML_OP_RESHAPE || node->op == GGML_OP_TRANSPOSE || node->op == GGML_OP_VIEW || node->op == GGML_OP_PERMUTE || node->op == GGML_OP_NONE) { + continue; + } -static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst); + if ((node->flags & GGML_TENSOR_FLAG_COMPUTE) == 0) { + continue; + } -// Runs the gate and up matmuls unchanged, then one kernel in place of -// add_id(gate) + add_id(up) + swiglu_oai. See ggml_opencl_can_fuse_moe_bias_glu. -static void ggml_cl_moe_bias_glu_fused(ggml_backend_t backend, ggml_tensor * gate_mm, const ggml_tensor * gate_add, - ggml_tensor * up_mm, const ggml_tensor * up_add, const ggml_tensor * glu) { - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { + ggml_opencl_op_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_GROUP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { + ggml_opencl_op_group_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + // Fuse the MoE combine: router-weight mul + cross-expert add chain -> + // one weighted-sum-across-experts kernel. + // Fold the gpt-oss MoE bias epilogue: add_id(gate_bias) + add_id(up_bias) + + // glu(swiglu_oai) -> one kernel, leaving the two matmuls as their own dispatches. + // Both add_ids are in-place passes over a tensor the GLU reads again, so this + // drops two full read+write passes per layer. Opt out GGML_OPENCL_FUSE_MOE_BIAS_GLU=0. + if (backend_ctx->fuse_moe_bias_glu && !backend_ctx->disable_fusion && + ggml_opencl_can_fuse_moe_bias_glu(cgraph, i)) { + ggml_cl_moe_bias_glu_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2], + cgraph->nodes[i+3], cgraph->nodes[i+4]); + i += 4; + continue; + } - ggml_cl_mul_mat_id(backend, gate_mm->src[0], gate_mm->src[1], gate_mm); - ggml_cl_mul_mat_id(backend, up_mm->src[0], up_mm->src[1], up_mm); + // Fold the MoE down-projection bias into the combine: add_id(down_bias) + the whole + // combine subgraph -> one kernel. Checked before the plain combine arm so the longer + // pattern wins. Opt out GGML_OPENCL_FUSE_MOE_BIAS_COMBINE=0. + if (backend_ctx->fuse_moe_bias_combine && backend_ctx->fuse_moe_combine && + !backend_ctx->disable_fusion) { + const ggml_tensor * bias_combine_out = nullptr; + if (ggml_opencl_can_fuse_moe_bias_combine(cgraph, i, &bias_combine_out)) { + ggml_cl_moe_bias_combine_fused(backend, node, cgraph->nodes[i+1], bias_combine_out); + i += 2 * (int)node->ne[1]; // ADD_ID + MUL + k VIEWs + (k-1) ADDs + continue; + } + } - const ggml_tensor * gbias = gate_add->src[1]; - const ggml_tensor * ubias = up_add->src[1]; - const ggml_tensor * ids = gate_add->src[2]; + if (backend_ctx->fuse_moe_combine && !backend_ctx->disable_fusion) { + const ggml_tensor * combine_out = nullptr; + if (ggml_opencl_can_fuse_moe_combine(cgraph, i, &combine_out)) { + ggml_cl_moe_combine_fused(backend, node, combine_out); + i += 2 * (int)node->ne[1] - 1; // skip the k VIEWs + (k-1) ADDs + continue; + } + } + + // Fuse rms_norm + mul(weight) + add(residual). Checked before the + // rms_norm+mul fuse so the 3-op pattern wins over its 2-op prefix. + // Default on, opt-out GGML_OPENCL_FUSE_RMS_ADD=0. + if (!backend_ctx->disable_fusion && backend_ctx->fuse_rms_add && + ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL, GGML_OP_ADD })) { + ggml_opencl_op_rms_norm_mul_add_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) { + ggml_opencl_op_rms_norm_fused(backend, node, cgraph->nodes[i+1]); + i++; + continue; + } + // Fuse mul_mat(Wg,x) + mul_mat(Wu,x) + glu — fold the FFN's two decode + // GEMVs and the GLU into one dispatch. q4_K only (guarded below); the + // fused kernel uses the same accumulation/reduction order and the same + // scalar GLU formula -> coherent. Default on, opt-out GGML_OPENCL_FUSE_MM_GLU=0. +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // The fused executor (ggml_cl_mul_mat_q4_k_glu_fused) is image-path / + // Adreno-only (GGML_ABORT on the non-Adreno #else); gate the dispatch to + // match so the FFN GLU subgraph stays dormant on Intel/other drivers. + if (backend_ctx->fuse_mm_glu && !backend_ctx->disable_fusion && + ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_MUL_MAT, GGML_OP_MUL_MAT, GGML_OP_GLU })) { + ggml_cl_mul_mat_q4_k_glu_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } +#endif - ggml_tensor_extra_cl * eg = (ggml_tensor_extra_cl *)gate_mm->extra; - ggml_tensor_extra_cl * egb = (ggml_tensor_extra_cl *)gbias->extra; - ggml_tensor_extra_cl * eu = (ggml_tensor_extra_cl *)up_mm->extra; - ggml_tensor_extra_cl * eub = (ggml_tensor_extra_cl *)ubias->extra; - ggml_tensor_extra_cl * ei = (ggml_tensor_extra_cl *)ids->extra; - ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)glu->extra; + bool ok = ggml_cl_compute_forward(backend, node); + if (!ok) { + GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); + } + GGML_ASSERT(ok); + } - cl_ulong off_g = eg->offset + gate_mm->view_offs; - cl_ulong off_gb = egb->offset + gbias->view_offs; - cl_ulong off_u = eu->offset + up_mm->view_offs; - cl_ulong off_ub = eub->offset + ubias->view_offs; - cl_ulong off_i = ei->offset + ids->view_offs; - cl_ulong off_d = ed->offset + glu->view_offs; + return GGML_STATUS_SUCCESS; +} - const cl_ulong nb01_g = gate_mm->nb[1]; - const cl_ulong nb02_g = gate_mm->nb[2]; - const cl_ulong nb01_u = up_mm->nb[1]; - const cl_ulong nb02_u = up_mm->nb[2]; - const cl_ulong nb11_g = gbias->nb[1]; - const cl_ulong nb11_u = ubias->nb[1]; - const cl_ulong nb21 = ids->nb[1]; - const cl_ulong nbd1 = glu->nb[1]; - const cl_ulong nbd2 = glu->nb[2]; +// The optimized gemm and gemv kernels are used for large matrices without batch. +// tensor is the quantized weights matrix. +inline bool use_adreno_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + int64_t threshold_ne0 = 512; + int64_t threshold_ne1 = 512; + if (!backend_ctx->adreno_cl_compiler_version.newer_than_or_same(E031, 38, 11, 0) && + backend_ctx->adreno_cl_compiler_version.type != DX) { + threshold_ne0 = 128; + threshold_ne1 = 128; + } + bool threashold_ok = tensor->ne[0] >= threshold_ne0 && tensor->ne[1] >= threshold_ne1 && + tensor->ne[2] == 1 && tensor->ne[3] == 1; - const int ne0 = (int)glu->ne[0]; - const float alpha = ggml_get_op_params_f32(glu, 2); - const float limit = ggml_get_op_params_f32(glu, 3); + // the transposed layout needs K % 32 == 0 and M % 4 == 0 + if (tensor->ne[0] % 32 != 0 || tensor->ne[1] % 4 != 0) { + return false; + } - cl_kernel kernel = backend_ctx->kernel_add_id_add_id_swiglu_oai; + // The noshuffle layout packs 2 rows per 32-bit texel and the GEMV reads it at an + // ne1/2 texel stride with an exact-cover dispatch, so it is only addressable when + // ne1 is a multiple of 64; an unaligned ne1 truncates the stride and the weight is + // read misaligned. That is a property of the layout, not of one quant -- q4_K, q5_K + // and q8_0 read the same packing as q6_K. The bound is 64, not 128: a q8_0 attention + // weight of ne1 = 2880 is a multiple of 64 but not 128 and is correct. + switch (tensor->type) { + case GGML_TYPE_Q4_K: + case GGML_TYPE_Q5_K: + case GGML_TYPE_Q6_K: + case GGML_TYPE_Q8_0: + return threashold_ok && tensor->ne[1] % 64 == 0; + default: + break; + } + return threashold_ok; +} - int i = 0; - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eg->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_g)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &egb->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_gb)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eu->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_u)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &eub->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_ub)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &ei->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_i)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_mem), &ed->data_device)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &off_d)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb01_g)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb02_g)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb01_u)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb02_u)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb11_g)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb11_u)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nb21)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nbd1)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(cl_ulong), &nbd2)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(float), &limit)); - CL_CHECK(clSetKernelArg(kernel, i++, sizeof(float), &alpha)); +static bool adreno_e17_compiler_quirks(const ggml_backend_opencl_context *backend_ctx) { + if (!backend_ctx || backend_ctx->gpu_family != GPU_FAMILY::ADRENO || + backend_ctx->adreno_cl_compiler_version.type != ADRENO_CL_COMPILER_TYPE::E17) { + return false; + } + const char * env = getenv("GGML_OPENCL_ADRENO_E17_QUIRKS"); + return !(env && env[0] == '0'); +} - const int nth = MIN(ne0, (int) backend_ctx->get_kernel_workgroup_size(kernel)); - size_t global_work_size[] = { (size_t)glu->ne[1]*nth, (size_t)glu->ne[2], 1 }; - size_t local_work_size[] = { (size_t)nth, 1, 1 }; +static bool ggml_cl_q2_k_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_Q2_K_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } + } + return tensor->type == GGML_TYPE_Q2_K && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, glu); +static bool ggml_cl_q3_k_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_Q3_K_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } + } + return tensor->type == GGML_TYPE_Q3_K && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif } -// Fusion B: the MoE down-projection bias add feeding the combine. -// -// The graph runs ADD_ID(down_bias) and then immediately the combine subgraph -// {MUL(router weights), k VIEWs, k-1 ADDs}, and the ADD_ID's only consumer is that -// MUL. Since the ADD_ID is an in-place read-modify-write of a tensor the combine -// reads once more, the bias can be added inside the combine instead, dropping a -// full pass over [n_embd, k, n_tokens]. -// -// Shape checks for the combine tail are delegated to ggml_opencl_can_fuse_moe_combine -// (which also owns the n_nodes >= 32 bail and the experts/dst aliasing bail); what is -// added here is the ADD_ID wiring plus a subgraph check over the WHOLE run, so that -// the intermediate bias result is confirmed not to escape. -static bool ggml_opencl_can_fuse_moe_bias_combine(const struct ggml_cgraph * cgraph, int node_idx, - const ggml_tensor ** out_final_add) { - if (node_idx + 1 >= cgraph->n_nodes) { - return false; +static bool ggml_cl_iq3_s_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ3_S_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - const ggml_tensor * add = cgraph->nodes[node_idx]; - if (add->op != GGML_OP_ADD_ID) { - return false; + return tensor->type == GGML_TYPE_IQ3_S && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +static bool ggml_cl_iq3_xxs_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ3_XXS_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - const ggml_tensor * mul = cgraph->nodes[node_idx+1]; - if (mul->op != GGML_OP_MUL || mul->src[0] != add) { - return false; + return tensor->type == GGML_TYPE_IQ3_XXS && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +static bool ggml_cl_iq1_m_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ1_M_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } + return tensor->type == GGML_TYPE_IQ1_M && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - const ggml_tensor * final_add = NULL; - if (!ggml_opencl_can_fuse_moe_combine(cgraph, node_idx+1, &final_add)) { - return false; +static bool ggml_cl_iq1_s_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ1_S_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } + return tensor->type == GGML_TYPE_IQ1_S && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - const ggml_tensor * raw = add->src[0]; - const ggml_tensor * bias = add->src[1]; - const ggml_tensor * ids = add->src[2]; - if (!raw || !bias || !ids) { - return false; +static bool ggml_cl_q2_0_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_Q2_0_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - if (raw->type != GGML_TYPE_F32 || bias->type != GGML_TYPE_F32 || - ids->type != GGML_TYPE_I32 || add->type != GGML_TYPE_F32) { - return false; + return tensor->type == GGML_TYPE_Q2_0 && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +static bool ggml_cl_iq2_s_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ2_S_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - // The combine reads the raw matmul output with the strides it computed from the - // add_id result, so the two must have the same layout. - if (!ggml_are_same_shape(raw, add) || !ggml_is_contiguous(raw)) { - return false; + return tensor->type == GGML_TYPE_IQ2_S && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +static bool ggml_cl_iq2_xs_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ2_XS_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - if (raw->nb[1] != add->nb[1] || raw->nb[2] != add->nb[2]) { - return false; + return tensor->type == GGML_TYPE_IQ2_XS && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +static bool ggml_cl_iq2_xxs_use_noshuffle(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * tensor) { +#if defined(GGML_OPENCL_SOA_Q) && defined(GGML_OPENCL_USE_ADRENO_KERNELS) + if (const char * env = getenv("GGML_OPENCL_IQ2_XXS_NOSHUFFLE")) { + if (env[0] == '0') { + return false; + } } - // ids is indexed as [expert slot, token]; the combine walks the same two axes. - if (ids->ne[0] < add->ne[1] || ids->ne[1] < add->ne[2]) { + return tensor->type == GGML_TYPE_IQ2_XXS && + backend_ctx->gpu_family == ADRENO && + ggml_is_contiguous(tensor) && !tensor->view_src && + use_adreno_kernels(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} + +inline bool use_adreno_moe_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + // The moe weight repack kernels *_trans4_ns alias a private ushort8 through a uchar*. + // Certain compilers (found with some A7x and A6x) miscompiles this, corrupting the weights. + // So, exclude A6x and A7x from using Adreno MoE kernels for now. + // The quants that have a general mul_mat_id kernel fallback to the general version; the + // rest fallback to CPU. + if (backend_ctx && (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::ADRENO_UNKNOWN)) { return false; } - // Whole-run escape check: ADD_ID + MUL + k VIEWs + (k-1) ADDs, only the last node escapes. - const int k = (int)add->ne[1]; - const int n_nodes = 2 + k + (k - 1); - if (n_nodes >= 32 || node_idx + n_nodes > cgraph->n_nodes) { + if (adreno_e17_compiler_quirks(backend_ctx)) { return false; } - enum ggml_op ops[32]; - int n = 0; - ops[n++] = GGML_OP_ADD_ID; - ops[n++] = GGML_OP_MUL; - for (int j = 0; j < k; ++j) ops[n++] = GGML_OP_VIEW; - for (int j = 0; j < k - 1; ++j) ops[n++] = GGML_OP_ADD; - const int outs[] = { node_idx + n_nodes - 1 }; - if (!ggml_can_fuse_subgraph(cgraph, node_idx, n_nodes, ops, outs, 1)) { - return false; + + int ne01 = tensor->ne[1]; + return (((strstr(tensor->name, "ffn") != NULL) && (strstr(tensor->name, "exps") != NULL)) || (strstr(tensor->name, "as") != NULL)) && (ne01 % 32 == 0); +} + +// Device default for the tiled-wide lm_head/embed GEMV layout: ON for X2E and A8X. +// +// These kernels were previously off everywhere on the grounds that they compute +// wrong values at multi-superblock K. They do not: that NMSE ~2 came from the +// backend having no get_tensor restore path for the tiled layout, so +// test-backend-ops (which builds its CPU reference by copying the weights back +// out of the backend) compared a correct GPU result against a reference +// dequantized from tiled bytes. With the restore path added, MUL_MAT passes with +// the tiled kernels on, unmodified, on both devices. +// +// Perf, Qwen3-4B-Q4_K_M (q6_K lm_head 151936x2560), tg128, matched pairs with +// alternating lead, tiled vs o4: +// +// A8X +11.9% 6/6 pairs positive, order bias -0.06% (16.93 vs 15.14 tok/s) +// X2E +6.9% 4/4 pairs positive, order bias -0.03% (35.24 vs 32.87 tok/s) +// +// Measure this one on a COLD device. These kernels are far more clock-sensitive +// than the o4 route they replace: on a heat-soaked A8X (CPU cap at 1.5-1.9 GHz) +// tiled pins at ~14.2 tok/s while o4 still makes ~14.9, which reads as a 4-5% +// LOSS and inverts the ranking. The same box, after a reboot and a gate that +// waits for policy6 to return to 4396800, reports the +11.9% above with no +// order bias. A7X regresses hard on this layout and stays off. +// GGML_OPENCL_{Q4K,Q6K}_GEMV_TILED forces either way (=0 off, any other value on). +inline bool tiled_gemv_default_on(const ggml_backend_opencl_context *backend_ctx) { + return backend_ctx && (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A8X); +} + +// Tiled-wide q6_K GEMV (default OFF; GGML_OPENCL_Q6K_GEMV_TILED forces either +// way: =0 off everywhere, any other value on everywhere). +// Both the convert (set_tensor) and the GEMV dispatch must agree on this so the +// buffer layout matches the kernel. +inline bool q6k_gemv_tiled_enabled(const ggml_backend_opencl_context *backend_ctx) { + static const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_TILED"); + if (e && e[0] != '\0') { + return e[0] != '0'; } + return tiled_gemv_default_on(backend_ctx); +} - *out_final_add = final_add; - return true; +// Only the long-vocab lm_head/embed shapes use the tiled layout; ne01 % 64 == 0 +// is required by the 64-row tiling (no row padding in the buffers). +// use_adreno_kernels is required: only the Adreno GEMV path can read the tiled +// layout, so converting a weight it would decline (e.g. ne00 < 512) leaves the +// generic kernel reading tiled bytes as plain SOA. +inline bool use_q6k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + return q6k_gemv_tiled_enabled(backend_ctx) && tensor->type == GGML_TYPE_Q6_K && + tensor->ne[1] >= 32768 && tensor->ne[1] % 64 == 0 && + use_adreno_kernels(backend_ctx, tensor); } +// Select untiled Q4_K before upload if the batched DP4A reader is unavailable. +inline bool q4k_gemv_tiled_enabled(const ggml_backend_opencl_context *backend_ctx) { + if (!backend_ctx->has_integer_dot) { + return false; + } + static const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_TILED"); + if (e && e[0] != '\0') { + return e[0] != '0'; + } + return tiled_gemv_default_on(backend_ctx); +} +inline bool use_q4k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + return q4k_gemv_tiled_enabled(backend_ctx) && tensor->type == GGML_TYPE_Q4_K && + tensor->ne[1] >= 32768 && tensor->ne[1] % 64 == 0 && + use_adreno_kernels(backend_ctx, tensor); +} -// Fusion B dispatch: the combine, reading the RAW matmul output and adding the -// per-expert bias row inline. See ggml_opencl_can_fuse_moe_bias_combine. -static void ggml_cl_moe_bias_combine_fused(ggml_backend_t backend, const ggml_tensor * add, - const ggml_tensor * mul, const ggml_tensor * dst) { - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; +inline bool enable_adreno_trans_weight(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - const ggml_tensor * experts = add->src[0]; // raw matmul output, bias not yet applied - const ggml_tensor * bias = add->src[1]; - const ggml_tensor * ids = add->src[2]; - const ggml_tensor * weights = mul->src[1]; + bool adreno_kernel = use_adreno_kernels(backend_ctx, tensor); - ggml_tensor_extra_cl * ee = (ggml_tensor_extra_cl *)experts->extra; - ggml_tensor_extra_cl * eb = (ggml_tensor_extra_cl *)bias->extra; - ggml_tensor_extra_cl * ei = (ggml_tensor_extra_cl *)ids->extra; - ggml_tensor_extra_cl * ew = (ggml_tensor_extra_cl *)weights->extra; - ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)dst->extra; - cl_ulong off_e = ee->offset + experts->view_offs; - cl_ulong off_b = eb->offset + bias->view_offs; - cl_ulong off_i = ei->offset + ids->view_offs; - cl_ulong off_w = ew->offset + weights->view_offs; - cl_ulong off_d = ed->offset + dst->view_offs; + size_t elem_num = tensor->ne[0] * tensor->ne[1] * tensor->ne[2] * tensor->ne[3]; - const int n_embd4 = (int)(experts->ne[0] / 4); - const int k = (int)experts->ne[1]; - const int nt = (int)experts->ne[2]; - const cl_uint e1 = (cl_uint)(experts->nb[1] / sizeof(float)); - const cl_uint e2 = (cl_uint)(experts->nb[2] / sizeof(float)); - const cl_uint w1 = (cl_uint)(weights->nb[1] / sizeof(float)); - const cl_uint w2 = (cl_uint)(weights->nb[2] / sizeof(float)); - const cl_uint d1 = (cl_uint)(dst->nb[1] / sizeof(float)); - const cl_ulong nb_b1 = bias->nb[1]; - const cl_ulong nb_i1 = ids->nb[1]; + // The 2D weight transpose (transpose_2d_as_*) tiles rows by 4 over a 2D matrix, + // so it requires K(ne0)%32==0, M(ne1)%4==0 and ne2==ne3==1. + const bool shape_ok = (tensor->ne[0] % 32 == 0) && (tensor->ne[1] % 4 == 0) && + (tensor->ne[2] == 1) && (tensor->ne[3] == 1); - const size_t w_bytes = ggml_nbytes(weights); - backend_ctx->prealloc_moe_combine_w.allocate(backend_ctx->context, w_bytes); - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, ew->data_device, backend_ctx->prealloc_moe_combine_w.buffer, - off_w, 0, w_bytes, 0, NULL, NULL)); - cl_mem w_dev = backend_ctx->prealloc_moe_combine_w.buffer; - cl_ulong w_off = 0; + return ((elem_num < 128 * 1024 * 1024) && adreno_kernel && shape_ok); // max element num: 2**27 +} - cl_kernel kernel = backend_ctx->kernel_moe_combine_bias_f32; - int a = 0; - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ee->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_e)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &w_dev)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &w_off)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &eb->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_b)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ei->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_i)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ed->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_d)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &n_embd4)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &k)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &nt)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e2)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w2)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &d1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &nb_b1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &nb_i1)); +inline bool enable_adreno_trans_weight_q5_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + if (!use_adreno_kernels(backend_ctx, tensor)) { + return false; + } - size_t lws[2] = { 64, 1 }; - size_t gws[2] = { (size_t)(((n_embd4 + 63) / 64) * 64), (size_t)nt }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, gws, lws, dst); + const size_t elem_num = ggml_nelements(tensor); + const size_t q_img_width = elem_num / 8; + const size_t qh_img_width = elem_num / 16; + const bool shape_ok = tensor->ne[0] % 32 == 0 && tensor->ne[1] % 4 == 0 && + tensor->ne[2] == 1 && tensor->ne[3] == 1; + + return shape_ok && q_img_width <= backend_ctx->image_max_buffer_size && + qh_img_width <= backend_ctx->image_max_buffer_size; } +inline bool use_q4_0_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (!backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans || + !backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin) { + return false; + } -static void ggml_cl_moe_combine_fused(ggml_backend_t backend, const ggml_tensor * mul, const ggml_tensor * dst) { - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; - const ggml_tensor * experts = mul->src[0]; - const ggml_tensor * weights = mul->src[1]; + // bin kernels require ne2 == 1 and ne3 == 1 for weights + return tensor->ne[2] == 1 && tensor->ne[3] == 1 && + (tensor->ne[0] % 32 == 0) && (tensor->ne[1] % 64 == 0); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - ggml_tensor_extra_cl * ee = (ggml_tensor_extra_cl *)experts->extra; - ggml_tensor_extra_cl * ew = (ggml_tensor_extra_cl *)weights->extra; - ggml_tensor_extra_cl * ed = (ggml_tensor_extra_cl *)dst->extra; - cl_ulong off_e = ee->offset + experts->view_offs; - cl_ulong off_w = ew->offset + weights->view_offs; - cl_ulong off_d = ed->offset + dst->view_offs; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static bool use_fa_bin_kernels_prefill(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * q, const ggml_tensor * k, const ggml_tensor * v) { + if (backend_ctx->fa.kernel_flash_attn_f32_f16_bin == nullptr) { + return false; + } - const int n_embd4 = (int)(experts->ne[0] / 4); - const int k = (int)experts->ne[1]; - const int nt = (int)experts->ne[2]; - const cl_uint e1 = (cl_uint)(experts->nb[1] / sizeof(float)); - const cl_uint e2 = (cl_uint)(experts->nb[2] / sizeof(float)); - const cl_uint w1 = (cl_uint)(weights->nb[1] / sizeof(float)); - const cl_uint w2 = (cl_uint)(weights->nb[2] / sizeof(float)); - const cl_uint d1 = (cl_uint)(dst->nb[1] / sizeof(float)); + const bool is_mixed = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && v->type == GGML_TYPE_F16; + const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; - // The router weights are tiny ([1,k,nt]) and may share a pool buffer with the output; - // copy them into a private scratch so the fused kernel never reads aliased memory. - const size_t w_bytes = ggml_nbytes(weights); - backend_ctx->prealloc_moe_combine_w.allocate(backend_ctx->context, w_bytes); - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, ew->data_device, backend_ctx->prealloc_moe_combine_w.buffer, - off_w, 0, w_bytes, 0, NULL, NULL)); - cl_mem w_dev = backend_ctx->prealloc_moe_combine_w.buffer; - cl_ulong w_off = 0; + const int n_q = q->ne[1]; + const int dk = q->ne[0]; + const int dv = v->ne[0]; - cl_kernel kernel = backend_ctx->kernel_moe_combine_f32; - int a = 0; - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ee->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_e)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &w_dev)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &w_off)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_mem), &ed->data_device)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_ulong), &off_d)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &n_embd4)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &k)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(int), &nt)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &e2)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w1)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &w2)); - CL_CHECK(clSetKernelArg(kernel, a++, sizeof(cl_uint), &d1)); + constexpr bool prefill_only = true; + + return (backend_ctx->gpu_family == GPU_FAMILY::ADRENO && + (is_mixed || is_q8_0) && (dk == dv) + && (dk == 64 || dk == 128 || dk == 256 || dk == 512) + && (!prefill_only || n_q != 1)); +} +#endif + +// The flat-GEMV large-m escape is OPT-IN (GGML_OPENCL_FLAT_LARGE_M=1) because it +// is SLOWER than the route it replaces, not because it is unsafe. It was first +// parked on the theory that it out-of-bounds-writes at vocab-scale shapes; that +// was a misattribution (the test-backend-ops dst sentinel was tripped by the o4 +// GEMV's unguarded tail store, fixed separately - and at the shape it was blamed +// for, k=1536, this predicate returns false anyway, so the flat route never ran). +// +// The escape's original rationale, "gemv_noshuffle perf drops for large M", +// predates the o4 kernel, which now covers the same long-vocab shapes and beats +// this route on every device measured (Qwen3-4B-Q4_K_M, q6_K lm_head +// 151936x2560, tg128, matched pairs vs o4): A8X -10.3% (0/3 pairs), X2E -3.7% +// (0/3). Keep it reachable for shapes o4 declines, but do not default it on. +static inline bool flat_large_m_enabled() { + static const char * e = getenv("GGML_OPENCL_FLAT_LARGE_M"); + static const bool en = e != nullptr && atoi(e) != 0; + return en; +} - size_t lws[2] = { 64, 1 }; - size_t gws[2] = { (size_t)(((n_embd4 + 63) / 64) * 64), (size_t)nt }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, gws, lws, dst); +// The noshuffle Q4_K weight image stores eight weights per uint texel. +static inline bool q4_K_weight_image_fits(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + const size_t texels = (size_t) ggml_nelements(tensor) / 8; + return texels != 0 && texels <= backend_ctx->image_max_buffer_size; } -inline bool use_q4k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below (used by the GLU-subgraph fuse check) -inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); -inline bool use_adreno_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below +static inline bool use_flat_gemv_for_large_m_q4_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + if (tensor->ne[1] % 4 != 0 && tensor->ne[2] == 1 && tensor->ne[3] == 1) { + return true; + } -static bool ggml_opencl_can_fuse(const ggml_backend_opencl_context * backend_ctx, const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops) { + if (tensor->ne[2] != 1 || tensor->ne[3] != 1 || use_q4k_tiled(backend_ctx, tensor)) { + return false; + } - // glu(mul_mat(Wg,x), mul_mat(Wu,x)) — the FFN gate/up GEMVs + GLU. This is a - // non-linear subgraph (up does NOT consume gate), so the contiguous - // ggml_can_fuse below rejects it; use ggml_can_fuse_subgraph with the glu as - // the sole output and validate the edges explicitly. q4_K decode only; - // byte-identical to the per-op path. - if (ops.size() == 3 && ops.begin()[0] == GGML_OP_MUL_MAT && - ops.begin()[1] == GGML_OP_MUL_MAT && ops.begin()[2] == GGML_OP_GLU) { - const enum ggml_op glu_ops[] = { GGML_OP_MUL_MAT, GGML_OP_MUL_MAT, GGML_OP_GLU }; - const int glu_out[] = { node_idx + 2 }; - if (!ggml_can_fuse_subgraph(cgraph, node_idx, 3, glu_ops, glu_out, 1)) { - return false; - } + // The image limit is a correctness guard, independent of the large-M opt-in. + if (!q4_K_weight_image_fits(backend_ctx, tensor)) { + return true; + } - const ggml_tensor *gate = cgraph->nodes[node_idx]; - const ggml_tensor *up = cgraph->nodes[node_idx+1]; - const ggml_tensor *glu = cgraph->nodes[node_idx+2]; + // gemv_noshuffle variant perf drops for large M, use flat variant for large M. + // threshold is well above typical hidden/FFN dims, but below typical vocab sizes. + // note that this forces large M weights to use LM GEMM. + return flat_large_m_enabled() && tensor->ne[1] >= 32768; +} - // decode GEMV path only (single token); prefill GEMM is separate - if (gate->ne[1] != 1 || up->ne[1] != 1) { - return false; - } - // both projections must be q4_K weights, f32 activation/output - if (gate->src[0]->type != GGML_TYPE_Q4_K || up->src[0]->type != GGML_TYPE_Q4_K || - gate->src[1]->type != GGML_TYPE_F32 || up->src[1]->type != GGML_TYPE_F32 || - gate->type != GGML_TYPE_F32 || up->type != GGML_TYPE_F32 || glu->type != GGML_TYPE_F32) { - return false; - } - // gate and up must share the same activation and have matching shape/stride - if (gate->src[1] != up->src[1] || - !ggml_are_same_shape(gate->src[0], up->src[0]) || - !ggml_are_same_stride(gate->src[0], up->src[0])) { - return false; - } - // GLU must read gate as src[0] and up as src[1], no swap (the fused - // epilogue applies the activation to gate, multiplies by up) - if (glu->src[0] != gate || glu->src[1] != up) { - return false; - } - if (ggml_get_op_params_i32(glu, 1) /* swapped */) { - return false; - } - // SWIGLU_OAI carries extra alpha/limit params -> not handled by the fused kernel - if (ggml_get_glu_op(glu) == GGML_GLU_OP_SWIGLU_OAI) { - return false; - } - // the fused kernel reads the standard noshuffle image layout; the tiled - // layout packs weights differently -> defer those to the per-op path - if (use_q4k_tiled(backend_ctx, gate->src[0]) || use_q4k_tiled(backend_ctx, up->src[0])) { - return false; - } - // q4_K bin kernel requires 32b transposed layout, not compatible with the fused gemv - if (use_q4_k_bin_kernels(backend_ctx, gate->src[0]) || use_q4_k_bin_kernels(backend_ctx, up->src[0])) { - return false; - } - // that noshuffle layout is only produced at set_tensor time when - // use_adreno_kernels() accepts the weight (ne0 >= 512 && ne1 >= 512). - // Smaller weights stay in the plain q4_K layout, which this kernel would - // misread -> defer them to the per-op path. Real FFN gate/up weights are - // far above the threshold, so production dispatch is unchanged. - if (!use_adreno_kernels(backend_ctx, gate->src[0]) || - !use_adreno_kernels(backend_ctx, up->src[0])) { - return false; - } +static inline bool use_flat_gemv_for_large_m_q6_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + // NOTE on ordering: the ne01 % 128 escape below is a CORRECTNESS guard, not a + // performance one, so it must be reachable regardless of flat_large_m_enabled(). + // The opt-in gate therefore sits after it, and after the tiled deferral. + // gemv_noshuffle variant perf drops for large M, use flat variant for large M. + // threshold is well above typical hidden/FFN dims, but below typical vocab sizes. + // q6_K flat gemv is worse for smaller K; 2048 seems to be a reasonable threshold. + // note that this forces large M weights to use LM GEMM. + // When this branch's tiled-canonical lm_head/embed layout is active, the weight is + // converted to the 64-row tiled layout, which the flat gemv would misread as + // garbage. use_q6k_tiled owns these large-M weights (it requires ne01 % 64 == 0, + // so it never claims an odd-vocab weight), so defer to it first. + if (use_q6k_tiled(backend_ctx, tensor)) { + return false; + } + // The noshuffle (transposed-weight) layout packs 2 rows per 32-bit texel and the + // gemv reads it with a ne01/2 texel stride and an exact-cover dispatch of + // ceil(ne01/2 / 64)*64 work-items with no store guard; the gemm uses 4-row tiles. + // It is therefore only correct for ne01 % 128 == 0: an odd ne01 (e.g. granitemoe + // lm_head [1536, 49155] -- odd vocab) truncates the texel stride, misaligning every + // odd column of the transposed layout (gross garbage) and dropping the last row; + // other non-multiples over-dispatch and write past the end of dst. Route such + // tensors to the flat GEMV + regular convert; the matching GEMM (ne1>1) falls back + // to CPU (see supports_op). All standard even-vocab/hidden dims are multiples of + // 128 and keep the noshuffle path. + if ((tensor->ne[1] % 128 != 0) && tensor->ne[2] == 1 && tensor->ne[3] == 1) { return true; } - if (!ggml_can_fuse(cgraph, node_idx, ops)) { + if (!flat_large_m_enabled()) { return false; } - if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { - const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; - const ggml_tensor *mul = cgraph->nodes[node_idx+1]; - - GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); - GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); - - // rms_norm only supports f32 - if (mul->src[0]->type != GGML_TYPE_F32 || - mul->src[1]->type != GGML_TYPE_F32 || - mul->type != GGML_TYPE_F32) { - return false; - } + // The gemv_noshuffle slowdown tracks TOTAL weight size, not ne0 alone; ne0 >= 2048 is a + // proxy for "large weight" that misses a narrow-hidden vocab-scale lm_head. + // Add a direct size escape so such weights also take the flat path, without changing + // which weights ne0 >= 2048 already routes there. + // The size escape is not taken on the A7X since its compiler miscompiles the flat K-quant GEMV + return tensor->ne[1] >= 32768 + && (tensor->ne[0] >= 2048 || (backend_ctx->adreno_gen != ADRENO_GPU_GEN::A7X && ggml_nbytes(tensor) >= (256ull << 20))) + && tensor->ne[2] == 1 && tensor->ne[3] == 1; +} - // if rms_norm is the B operand, then we don't handle broadcast - if (rms_norm == mul->src[1] && - !ggml_are_same_shape(mul->src[0], rms_norm)) { - return false; - } +inline bool use_q6_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (!backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans || + !backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin) { + return false; + } + // bin kernels require ne2 == 1 and ne3 == 1 for weights + return tensor->ne[2] == 1 && tensor->ne[3] == 1 && + (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0) && + !use_q6k_tiled(backend_ctx, tensor) && !use_flat_gemv_for_large_m_q6_K(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - // rms_norm assumes contiguous rows - if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { - return false; - } - } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { - const ggml_tensor *norm = cgraph->nodes[node_idx]; - const ggml_tensor *mul = cgraph->nodes[node_idx+1]; - const ggml_tensor *add = cgraph->nodes[node_idx+2]; - const ggml_tensor *w = mul->src[0] == norm ? mul->src[1] : mul->src[0]; - const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; +inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (!backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans || + !backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin) { + return false; + } + // bin kernels require ne2 == 1 and ne3 == 1 for weights + return tensor->ne[2] == 1 && tensor->ne[3] == 1 && + (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0) && + !use_q4k_tiled(backend_ctx, tensor) && !use_flat_gemv_for_large_m_q4_K(backend_ctx, tensor); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - // norm fusion only supports F32 - if (norm->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { - return false; - } +inline bool use_q5_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (!backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans || + !backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin) { + return false; + } + return (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0); +#else + GGML_UNUSED(backend_ctx); + GGML_UNUSED(tensor); + return false; +#endif +} - if (norm->src[0]->ne[0] % 4 != 0) { - return false; - } +static bool ggml_cl_mul_mat_can_use_fwht(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * op) { + const ggml_tensor * a = op->src[0]; + const ggml_tensor * b = op->src[1]; + const int64_t n = a->ne[0]; + + return ggml_get_op_params_i32(op, 1) == GGML_HINT_SRC0_IS_HADAMARD && + a->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && + (b->type == GGML_TYPE_F32 || b->type == GGML_TYPE_F16) && + n >= 2 && n <= std::numeric_limits::max() && (n & (n - 1)) == 0 && a->ne[1] == n && + (uint64_t)n <= backend_ctx->local_mem_size/sizeof(float) && + ggml_is_contiguous_rows(b) && ggml_is_contiguous(op) && ggml_are_same_shape(b, op); +} - if (!ggml_is_contiguous(norm->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { - return false; - } - } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { - // rms_norm(x) * w + b, fused (residual). Mirrors the RMS_NORM+MUL gate - // plus the residual-add operand's constraints. - const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; - const ggml_tensor *mul = cgraph->nodes[node_idx+1]; - const ggml_tensor *add = cgraph->nodes[node_idx+2]; - const ggml_tensor *w = mul->src[0] == rms_norm ? mul->src[1] : mul->src[0]; - const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; +static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *)dev->context; + ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx; - GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); - GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); + // reject ops that match the opfilter regex + if (dev_ctx->opfilter && std::regex_match(std::string(ggml_op_desc(op)), *dev_ctx->opfilter)) { + return false; + } - if (w->type != GGML_TYPE_F32 || mul->type != GGML_TYPE_F32 || - b->type != GGML_TYPE_F32 || add->type != GGML_TYPE_F32) { - return false; - } - if (rms_norm->src[0]->ne[0] % 4 != 0) { - return false; - } - // if rms_norm is the B operand of mul, broadcast is not handled - if (rms_norm == mul->src[1] && !ggml_are_same_shape(mul->src[0], rms_norm)) { - return false; - } - // the residual must match the normed output shape (no add broadcast) - if (!ggml_are_same_shape(b, add)) { - return false; + switch (op->op) { + case GGML_OP_NONE: + return true; + case GGML_OP_GET_ROWS: + switch (op->src[0]->type) { + case GGML_TYPE_I32: + return op->type == GGML_TYPE_I32; + case GGML_TYPE_F32: + case GGML_TYPE_F16: + return true; + case GGML_TYPE_Q4_0: +#ifdef GGML_OPENCL_SOA_Q + // We do not support flattened Q4_0 (and possibly other Q's) + return false; +#else // GGML_OPENCL_SOA_Q + return true; +#endif // GGML_OPENCL_SOA_Q + default: + return false; + } + case GGML_OP_SET_ROWS: + { + // TODO: add support + // ref: https://github.com/ggml-org/llama.cpp/pull/14274 +#pragma message("TODO: implement BF16, Q4_0, Q4_1, Q5_0, Q5_1, Q8_0, IQ4_NL support (https://github.com/ggml-org/llama.cpp/pull/14661)") + if (op->src[0]->type != GGML_TYPE_F32) { + return false; + } + switch (op->type) { + case GGML_TYPE_F16: + case GGML_TYPE_F32: + case GGML_TYPE_Q8_0: + case GGML_TYPE_Q4_0: + return (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); + default: + return false; + } + } + case GGML_OP_CPY: + case GGML_OP_DUP: + case GGML_OP_CONT: + switch (op->src[0]->type) { + case GGML_TYPE_F32: + switch (op->type) { + case GGML_TYPE_I32: + case GGML_TYPE_F16: + case GGML_TYPE_F32: + return true; + default: + return false; + } + case GGML_TYPE_F16: + switch (op->type) { + case GGML_TYPE_F16: + case GGML_TYPE_F32: + return true; + default: + return false; + } + case GGML_TYPE_I32: + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_I32: + return true; + default: + return false; + } + default: + return false; + } + case GGML_OP_SET: { + return (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_I32) && + op->type == op->src[0]->type && + op->type == op->src[1]->type; } - // rms_norm assumes contiguous rows - if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1]) || - !ggml_is_contiguous_rows(b)) { - return false; + case GGML_OP_SCALE: + return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_ADD: + if (op->type == GGML_TYPE_F16) { + const bool src0_ok = op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32; + const bool src1_ok = op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32; + if (src0_ok && src1_ok) { + return true; + } + } + case GGML_OP_MUL: + case GGML_OP_DIV: + case GGML_OP_SUB: + return (op->src[0]->type == op->src[1]->type) && + (op->src[0]->type == op->type) && + (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16); + case GGML_OP_ADD_ID: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_SQR: + case GGML_OP_SQRT: + return (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16) && + ggml_is_contiguous(op->src[0]); + case GGML_OP_UNARY: + switch (ggml_get_unary_op(op)) { + case GGML_UNARY_OP_GELU: + case GGML_UNARY_OP_SILU: + case GGML_UNARY_OP_RELU: + case GGML_UNARY_OP_GELU_ERF: + case GGML_UNARY_OP_GELU_QUICK: + return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; + case GGML_UNARY_OP_SIGMOID: + return ggml_is_contiguous(op->src[0]); + case GGML_UNARY_OP_TANH: + case GGML_UNARY_OP_NEG: + case GGML_UNARY_OP_EXP: + // Adreno F16 exp/expm1 overflow even post-half->float convert. + return op->src[0]->type == GGML_TYPE_F32; + case GGML_UNARY_OP_EXPM1: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_UNARY_OP_ABS: + case GGML_UNARY_OP_SGN: + case GGML_UNARY_OP_STEP: + case GGML_UNARY_OP_ELU: + case GGML_UNARY_OP_HARDSWISH: + case GGML_UNARY_OP_HARDSIGMOID: + case GGML_UNARY_OP_FLOOR: + case GGML_UNARY_OP_CEIL: + case GGML_UNARY_OP_ROUND: + case GGML_UNARY_OP_TRUNC: + return op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16; + case GGML_UNARY_OP_SOFTPLUS: + return op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16; + default: + return false; + } + case GGML_OP_GLU: + switch (ggml_get_glu_op(op)) { + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_REGLU: + case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: + case GGML_GLU_OP_GEGLU_ERF: + case GGML_GLU_OP_GEGLU_QUICK: + case GGML_GLU_OP_SWIGLU_CLAMP: + return ggml_is_contiguous_1(op->src[0]) && (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16); + default: + return false; + } + case GGML_OP_TRI: + return op->type == GGML_TYPE_F32 && ggml_is_contiguous(op); + case GGML_OP_FILL: + return op->type == GGML_TYPE_F32 && ggml_is_contiguous(op); + case GGML_OP_CLAMP: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_SOFT_MAX: + case GGML_OP_NORM: + return true; + case GGML_OP_RMS_NORM: + return op->ne[0] % 4 == 0 && ggml_is_contiguous_rows(op->src[0]); + case GGML_OP_L2_NORM: + return ggml_is_contiguous_rows(op->src[0]); + case GGML_OP_REPEAT: + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; // Assuming F32 for now, can be expanded + case GGML_OP_PAD: + // TODO: add circular padding support for opencl, see https://github.com/ggml-org/llama.cpp/pull/16985 + if (ggml_get_op_params_i32(op, 8) != 0) { + return false; + } + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + case GGML_OP_UPSCALE: { + ggml_scale_mode mode = (ggml_scale_mode)(ggml_get_op_params_i32(op, 0) & 0xFF); + const bool antialias = (ggml_scale_mode)(ggml_get_op_params_i32(op, 0) & GGML_SCALE_FLAG_ANTIALIAS); + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && + (mode == GGML_SCALE_MODE_NEAREST || mode == GGML_SCALE_MODE_BILINEAR) && !antialias; } - } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_GROUP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { - const ggml_tensor *gn = cgraph->nodes[node_idx]; - const ggml_tensor *mul = cgraph->nodes[node_idx+1]; - const ggml_tensor *add = cgraph->nodes[node_idx+2]; - const ggml_tensor *w = mul->src[0] == gn ? mul->src[1] : mul->src[0]; - const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; + case GGML_OP_CONV_2D: + return (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16) || + (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32) || + (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32); + case GGML_OP_CONV_2D_DW: + return op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && + op->src[0]->nb[0] == ggml_type_size(op->src[0]->type) && + op->src[1]->nb[0] == sizeof(float) && op->nb[0] == sizeof(float) && + (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16); + case GGML_OP_SSM_CONV: + // the channels-major input layout is only implemented on CPU/CUDA + return (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && ggml_ssm_conv_get_layout(op) == GGML_SSM_CONV_LAYOUT_TIME_MAJOR); + case GGML_OP_SSM_SCAN: { + if (op->type != GGML_TYPE_F32 || op->src[0]->type != GGML_TYPE_F32 || + op->src[1]->type != GGML_TYPE_F32 || op->src[2]->type != GGML_TYPE_F32 || + op->src[3]->type != GGML_TYPE_F32 || op->src[4]->type != GGML_TYPE_F32 || + op->src[5]->type != GGML_TYPE_F32 || op->src[6]->type != GGML_TYPE_I32) { + return false; + } - if (gn->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { + const int64_t d_state = op->src[0]->ne[0]; + return d_state >= 1 && d_state <= 256 && (d_state & (d_state - 1)) == 0; + } + case GGML_OP_GATED_DELTA_NET: + { + // Match the Vulkan backend: only F32 -> F32, S_v in {16, 32, 64, 128}. + if (op->src[0]->type != GGML_TYPE_F32 || op->type != GGML_TYPE_F32) { + return false; + } + const int64_t S_v = op->src[2]->ne[0]; + return S_v == 16 || S_v == 32 || S_v == 64 || S_v == 128; + } + case GGML_OP_CONCAT: + { + const ggml_type t = op->src[0]->type; + return op->src[1]->type == t && op->type == t && + !ggml_is_quantized(t) && ggml_blck_size(t) == 1 && + (ggml_type_size(t) == 1 || ggml_type_size(t) == 2 || + ggml_type_size(t) == 4 || ggml_type_size(t) == 8); + } + case GGML_OP_TIMESTEP_EMBEDDING: + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + case GGML_OP_GROUP_NORM: + return ggml_is_contiguous(op->src[0]); + case GGML_OP_MUL_MAT: + if (ggml_cl_mul_mat_can_use_fwht(backend_ctx, op)) { + return true; + } + if (op->src[0]->type == GGML_TYPE_F16) { + return true; + } else if (op->src[0]->type == GGML_TYPE_BF16) { + return true; + } else if (op->src[0]->type == GGML_TYPE_F32) { + return op->src[1]->type == GGML_TYPE_F32; + } else if (op->src[0]->type == GGML_TYPE_Q1_0) { + return op->src[1]->type == GGML_TYPE_F32; + } else if (op->src[0]->type == GGML_TYPE_Q4_0) { + // Non-contig src0 routes through on-device dequant-to-f16. + return op->src[1]->type == GGML_TYPE_F32; + } else if (op->src[0]->type == GGML_TYPE_IQ2_XXS) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq2_xxs_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ2_XS) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq2_xs_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ2_S) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq2_s_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q2_0) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_q2_0_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ1_S) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq1_s_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ1_M) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq1_m_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ3_S) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq3_s_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_IQ3_XXS) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_iq3_xxs_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q3_K) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_q3_k_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q2_K) { + const ggml_tensor * weight = op->src[0]->view_src; + if (weight && ggml_cl_q2_k_use_noshuffle(backend_ctx, weight)) { + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && + ggml_is_contiguous_rows(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q4_1 || + op->src[0]->type == GGML_TYPE_Q5_0 || op->src[0]->type == GGML_TYPE_Q5_1 || + op->src[0]->type == GGML_TYPE_MXFP4 || + op->src[0]->type == GGML_TYPE_IQ4_NL || + op->src[0]->type == GGML_TYPE_Q4_K || + op->src[0]->type == GGML_TYPE_Q5_K || + op->src[0]->type == GGML_TYPE_Q6_K) { + // The E031.41 compiler (usually with A7x) miscompiles the flat K-quant + // GEMV kernels (kernel_mul_mv_q*_K_f32_flat) and makes lm_head run much + // slower than it should. So, make it fallback to CPU to preserve performance + // for this compiler series. + static const char * a7x_lmhead_env = getenv("GGML_OPENCL_A7X_LMHEAD_CPU"); + static const bool a7x_lmhead_cpu = (a7x_lmhead_env == nullptr || a7x_lmhead_env[0] != '0'); + if (a7x_lmhead_cpu && + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && + (op->src[0]->type == GGML_TYPE_Q4_K || op->src[0]->type == GGML_TYPE_Q5_K || + op->src[0]->type == GGML_TYPE_Q6_K) && + op->src[0]->ne[1] >= 32768) { // vocab-scale weight; no FFN/attn weight is this tall + return false; + } + return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q8_0) { + // ggml_cl_mul_mat_q8_0_f32_adreno now honors src1/dst view_offs (the + // activation sub-buffer starts at offset1 and the kernels take offsetd), + // so a broadcast q8_0 matmul (src1 batch > src0 batch, e.g. Qwen3.5-9B-UD + // / Qwen3.6-35B q8_0 GDN ssm_out) runs on GPU via the per-slice broadcast + // iteration in ggml_cl_mul_mat. No special-casing needed. + return op->src[1]->type == GGML_TYPE_F32; + } return false; - } - - if (!ggml_is_contiguous(gn->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { + case GGML_OP_MUL_MAT_ID: +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (ggml_get_op_params_i32(op, 3) == GGML_PREC_F32 && + use_adreno_moe_kernels(backend_ctx, op->src[0])) { + return false; + } +#endif + if (op->src[0]->type == GGML_TYPE_Q4_0 || + op->src[0]->type == GGML_TYPE_Q8_0 || + op->src[0]->type == GGML_TYPE_MXFP4) { + if (op->src[1]->type == GGML_TYPE_F32) { + return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); + } + } + // q4_0, q8_0 and mxfp4 have general MUL_MAT_ID support, + // the quantizations here currently do not - they are only supported by Adreno with certain shapes + if (op->src[0]->type == GGML_TYPE_Q4_1 || + op->src[0]->type == GGML_TYPE_Q5_0 || + op->src[0]->type == GGML_TYPE_Q5_1 || + op->src[0]->type == GGML_TYPE_Q4_K || + op->src[0]->type == GGML_TYPE_Q5_K || + op->src[0]->type == GGML_TYPE_Q6_K) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (op->src[1]->type == GGML_TYPE_F32) { + return use_adreno_moe_kernels(backend_ctx, op->src[0]) + && ggml_is_contiguous(op->src[0]) + && ggml_is_contiguous(op->src[1]); + } +#endif + return false; + } return false; + case GGML_OP_RESHAPE: + case GGML_OP_VIEW: + case GGML_OP_PERMUTE: + case GGML_OP_TRANSPOSE: + return true; + case GGML_OP_DIAG: + return true; + case GGML_OP_DIAG_MASK_INF: + return op->ne[3] == 1; + case GGML_OP_ROPE: { + const int mode = ((const int32_t *) op->op_params)[2]; + const bool is_mrope = mode & GGML_ROPE_TYPE_MROPE; + const bool is_vision = mode == GGML_ROPE_TYPE_VISION; + if (is_mrope && !is_vision) { + if (op->src[0]->type == GGML_TYPE_F32 || + op->src[0]->type == GGML_TYPE_F16) { + return true; + } + return false; + } + if (is_vision) { + if (op->src[0]->type == GGML_TYPE_F32 || + op->src[0]->type == GGML_TYPE_F16) { + return true; + } + return false; + } + return true; } - } + case GGML_OP_SOLVE_TRI: + return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_IM2COL: + return true; + case GGML_OP_IM2COL_3D: + return true; + case GGML_OP_ARGMAX: + load_cl_kernels_argmax(backend_ctx); + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_I32 && + ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op) && + backend_ctx->get_kernel_workgroup_size(backend_ctx->kernel_argmax_f32_i32) >= 64; + case GGML_OP_LIGHTNING_INDEXER: + return op->src[0]->type == GGML_TYPE_F32 && + (op->src[1]->type == GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_BF16) && + op->src[2]->type == GGML_TYPE_F32 && op->src[3]->type == GGML_TYPE_F16 && + op->src[0]->nb[0] == sizeof(float) && op->src[1]->nb[0] == ggml_type_size(op->src[1]->type) && + op->src[2]->nb[0] == sizeof(float) && op->src[3]->nb[0] == sizeof(ggml_fp16_t); + case GGML_OP_TOP_K: + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_I32; + case GGML_OP_TOP_K_MASK: + return (op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32) && + op->src[0]->type == op->type && + op->src[0]->nb[0] == ggml_type_size(op->type) && op->nb[0] == ggml_type_size(op->type) && + op->src[1]->type == GGML_TYPE_I32 && + (!op->src[2] || op->src[2]->type == GGML_TYPE_F32) && + (!op->src[3] || op->src[3]->type == GGML_TYPE_I32) && + (!op->src[4] || op->src[4]->type == GGML_TYPE_I32); + case GGML_OP_ARGSORT: { + load_cl_kernels_argsort(backend_ctx); - return true; -} + cl_kernel kernel = backend_ctx->kernel_argsort_f32_i32; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); -static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor); -static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); -static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); + int cols = 1; + while (cols < op->ne[0]) { + cols *= 2; + } -static void ggml_cl_mul_mat_q4_k_glu_fused(ggml_backend_t backend, ggml_tensor * gate_tensor, ggml_tensor * up_tensor, ggml_tensor * glu_tensor) { + return cols <= max_workgroup_size && op->src[0]->type == GGML_TYPE_F32; + } + case GGML_OP_SUM_ROWS: + case GGML_OP_CUMSUM: + return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_MEAN: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_FLASH_ATTN_EXT: { + // K/V row lists (ggml_flash_attn_ext_rows) are not supported + if (op->src[5] != nullptr) { + return false; + } #ifdef GGML_OPENCL_USE_ADRENO_KERNELS - GGML_ASSERT(gate_tensor && up_tensor && glu_tensor); - - const ggml_tensor * Wg = gate_tensor->src[0]; - const ggml_tensor * Wu = up_tensor->src[0]; - const ggml_tensor * src1 = gate_tensor->src[1]; // == up_tensor->src[1] - const ggml_tensor * dst = glu_tensor; - - GGML_ASSERT(Wg && Wg->extra); - GGML_ASSERT(Wu && Wu->extra); - GGML_ASSERT(src1 && src1->extra); - GGML_ASSERT(dst && dst->extra); - - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_K * extra_g = (ggml_tensor_extra_cl_q4_K *)Wg->extra; - ggml_tensor_extra_cl_q4_K * extra_u = (ggml_tensor_extra_cl_q4_K *)Wu->extra; - - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; - - const int K = Wg->ne[0]; // ne00 - const int M = Wg->ne[1]; // ne01 (= ffn intermediate width) - const int N = 1; // decode GEMV - - const cl_uchar mask_d6 = 0x3F, mask_d4 = 0x0F, mask_hi2 = 0xC0; - const int glu_op = (int)ggml_get_glu_op(dst); - - cl_context context = backend_ctx->context; - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; - - // q images for the two weight matrices (standard noshuffle layout) - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * K / 2 / 4; - img_desc.buffer = extra_g->q; - cl_mem qg_img = nullptr, qu_img = nullptr; - CL_CHECK((qg_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - img_desc.buffer = extra_u->q; - CL_CHECK((qu_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // shared activation image (one column at decode) - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - cl_mem b_sub_buf = nullptr, b_img = nullptr; - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - img_fmt = { CL_RGBA, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - cl_kernel kernel = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_glu; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qg_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra_g->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_g->dm)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra_g->s)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &qu_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra_u->d)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra_u->dm)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extra_u->s)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_int), &K)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_int), &M)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_int), &glu_op)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_uchar), &mask_hi2)); - - // K-split = nsg_y subgroups. HARD-CAP at 8 (512 work-items): the fused - // kernel's cross-subgroup reduce uses a float4 reduceLM (gate+up packed) = - // 2x the LDS of the base GEMV's float2 reduce, so 16 co-resident subgroups - // exceed the per-CU LDS budget on X2 and the WG barrier DEADLOCKS -> GPU TDR - // (reproduced on upstream gemma-4 E4B decode, K=2560 M=10240). This used to - // be masked: get_kernel_workgroup_size reported 896 for this kernel (so the - // cap loop fell to 8), but it now returns 1024 and the Adreno per-kernel WG - // query is unreliable (over-reports), so cap explicitly instead of trusting - // it. nsg_y < 16 also means the cross-subgroup accumulation grouping differs - // from the standalone wide (nsg=16) GEMV, so the output is coherent but NOT - // byte-identical to the per-op path. Keep the maxwg query as a further floor - // for any driver that reports < 512. - size_t maxwg = backend_ctx->get_kernel_workgroup_size(kernel); - size_t nsg_y = 8; - while (nsg_y > 1 && 64 * nsg_y > maxwg) { nsg_y >>= 1; } - size_t local_work_size[3] = { 64, nsg_y, 1 }; - size_t global_work_size[3] = { (size_t)CEIL_DIV(M / 2, 64) * 64, nsg_y, 1 }; - - if (getenv("GGML_OPENCL_FUSE_DEBUG")) { - static int dbg = 0; - if (dbg < 3) { fprintf(stderr, "[FUSE_MM_GLU] fired #%d K=%d M=%d glu_op=%d nsg=%zu maxwg=%zu\n", ++dbg, K, M, glu_op, nsg_y, maxwg); fflush(stderr); } - } - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(qg_img)); - CL_CHECK(clReleaseMemObject(qu_img)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); -#else - GGML_UNUSED(backend); - GGML_UNUSED(gate_tensor); - GGML_UNUSED(up_tensor); - GGML_UNUSED(glu_tensor); + if (use_fa_bin_kernels_prefill(backend_ctx, op->src[0], op->src[1], op->src[2])) { + return true; + } #endif -} + // The E17 compilers segfault while building FA kernels, skip E17 for now + if (adreno_e17_compiler_quirks(backend_ctx)) { + return false; + } + const ggml_tensor * q = op->src[0]; + const ggml_tensor * k = op->src[1]; + const ggml_tensor * v = op->src[2]; + const int dk = q->ne[0]; + const int dv = v->ne[0]; -static void ggml_opencl_op_rms_norm_mul_add_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { - GGML_ASSERT(rms_norm_tensor && mul_tensor && add_tensor); + const struct { int dk; int dv; } supported_dims[] = { + { 40, 40}, { 64, 64}, { 80, 80}, { 96, 96}, + {112, 112}, {128, 128}, {192, 128}, + {192, 192}, {256, 256}, + {512, 512}, + }; - const ggml_tensor * src0 = rms_norm_tensor->src[0]; - const ggml_tensor * src1 = mul_tensor->src[0] == rms_norm_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; - const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; - const ggml_tensor * dst = add_tensor; + bool dims_supported = false; + for (size_t i = 0; i < sizeof(supported_dims)/sizeof(supported_dims[0]); ++i) { + if (supported_dims[i].dk == dk && supported_dims[i].dv == dv) { + dims_supported = true; + break; + } + } + if (!dims_supported) { + return false; + } - GGML_ASSERT(src0 && src0->extra); - GGML_ASSERT(src1 && src1->extra); - GGML_ASSERT(src2 && src2->extra); - GGML_ASSERT(dst && dst->extra); + const bool is_f32_f32 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F32 && + v->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + const bool is_f16_f16 = q->type == GGML_TYPE_F16 && k->type == GGML_TYPE_F16 && + v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16; + const bool is_f32_f16 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && + v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F32; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const bool is_f32_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && + v->type == GGML_TYPE_Q8_0 && op->type == GGML_TYPE_F32 && + dk % 32 == 0 && dv % 32 == 0; + const bool is_f32_q4_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q4_0 && + v->type == GGML_TYPE_Q4_0 && op->type == GGML_TYPE_F32 && + dk % 32 == 0 && dv % 32 == 0; - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offset2 = extra2->offset + src2->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + // A7X (Adreno 740, compiler E031.41) SIGSEGVs inside clBuildProgram + // building the flash_attn programs whose KV path is mixed-type or + // dequantized — f32_f16, q8_0, q4_0 (reproduced at DK=40 and DK=64; it + // is DK-independent). It is a driver crash, not codegen-wrong-output, so + // it cannot be caught in-process (fatal=false only handles clean compile + // errors). The uniform f16_f16 / f32_f32 programs compile fine on this + // compiler, so decline only the KV-convert variants; ggml then runs + // those (f16-KV / quant-KV) attention layers on the CPU backend. + // Negative compiler carve-out, same idiom as the Intel DK=512 decline + // below and the X1E driver-quirk guards. + if (backend_ctx && backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && + (is_f32_f16 || is_f32_q8_0 || is_f32_q4_0)) { + return false; + } - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + // Asymmetric KV: host-dequants both sides to F32, uses f32 kernel. + auto is_kv_type_ok = [](ggml_type t) { + return t == GGML_TYPE_F16 || t == GGML_TYPE_F32 || + t == GGML_TYPE_Q4_0 || t == GGML_TYPE_Q8_0; + }; + const bool is_f32_asym = q->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && + k->type != v->type && + is_kv_type_ok(k->type) && is_kv_type_ok(v->type); - float eps; - memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); + const bool kv_combo_ok = is_f32_f32 || is_f16_f16 || is_f32_f16 || + is_f32_q8_0 || is_f32_q4_0 || is_f32_asym; + if (!kv_combo_ok) { + return false; + } - const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; - const cl_ulong nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; - const int ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3]; - const cl_ulong nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; - const int ne20 = src2->ne[0], ne21 = src2->ne[1], ne22 = src2->ne[2], ne23 = src2->ne[3]; - const cl_ulong nb21 = src2->nb[1], nb22 = src2->nb[2], nb23 = src2->nb[3]; - const cl_ulong nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3]; + // Some compilers for A7x (Adreno 740, compiler E031.41) crashes when + // building FA kernels with mixed or quant types (f32_f16, f32_q8_0, f32_q4_0) + // Here we skip all A7x for these kernels to avoid crash + if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && + (is_f32_f16 || is_f32_q8_0 || is_f32_q4_0)) { + return false; + } - GGML_ASSERT(ne00 % 4 == 0); + if (dk == 512) { + if (backend_ctx->gpu_family == INTEL) { + return false; + } + if (!is_f32_f16) { + return false; + } + if (q->ne[1] == 1) { + const char * decode_env = getenv("GGML_OPENCL_FA_DK512_DECODE"); + if ((decode_env && decode_env[0] == '0') || + backend_ctx->gpu_family != ADRENO || k->ne[2] <= 0 || + (q->ne[2] / k->ne[2] != 4 && q->ne[2] / k->ne[2] != 8) || q->ne[2] % k->ne[2] != 0 || + !ggml_opencl_ensure_fa_f32_f16_vec_512(backend_ctx)) { + return false; + } + } else { + // prefill, BM-tile in its own FA_PREFILL_ONLY program + if (!ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/false)) { + return false; + } + } + } + return true; + } + default: + return false; + } +} - size_t sgs; - if (backend_ctx->gpu_family == ADRENO) sgs = 64; - else if (backend_ctx->gpu_family == INTEL) sgs = 32; - else GGML_ASSERT(false && "Unsupported GPU"); +// Forward declaration - implementation appears later in the file. +static const char * ggml_backend_opencl_buffer_type_get_name(ggml_backend_buffer_type_t buffer_type); - cl_kernel kernel = backend_ctx->kernel_rms_norm_mul_add; +static ggml_guid_t ggml_backend_opencl_guid() { + static ggml_guid guid = { 0xde, 0xe0, 0x70, 0xa2, 0x73, 0x4e, 0x4d, 0xbc, 0xb0, 0xc7, 0x4f, 0xd4, 0x6d, 0x4e, 0x90, 0xfe }; + return &guid; +} - int nth = sgs; - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - while (nth < ne00 && nth < max_workgroup_size) nth *= 2; - nth = MIN(nth, max_workgroup_size); - nth = MIN(nth, ne00); +static ggml_backend_i ggml_backend_opencl_i = { + /* .get_name = */ ggml_backend_opencl_name, + /* .free = */ ggml_backend_opencl_free, + /* .set_tensor_async = */ NULL, /* ggml_backend_opencl_set_tensor_async */ + /* .get_tensor_async = */ NULL, /* ggml_backend_opencl_get_tensor_async */ + /* .set_tensor_2d_async = */ NULL, + /* .get_tensor_2d_async = */ NULL, + /* .cpy_tensor_async = */ NULL, /* ggml_backend_opencl_cpy_tensor_async */ + /* .synchronize = */ ggml_backend_opencl_synchronize, + /* .graph_plan_create = */ NULL, + /* .graph_plan_free = */ NULL, + /* .graph_plan_update = */ NULL, + /* .graph_plan_compute = */ NULL, + /* .graph_compute = */ ggml_backend_opencl_graph_compute, + /* .event_record = */ NULL, + /* .event_wait = */ NULL, + /* .graph_optimize = */ NULL, +}; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; +ggml_backend_t ggml_backend_opencl_init(void) { + ggml_backend_dev_t dev = ggml_backend_reg_dev_get(ggml_backend_opencl_reg(), 0); + ggml_backend_opencl_context *backend_ctx = ggml_cl_init(dev); + backend_ctx->ref_count++; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne20)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne21)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne22)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne23)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb21)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb22)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb23)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 32, sizeof(float), &eps)); - CL_CHECK(clSetKernelArg(kernel, 33, sizeof(float)*sgs, NULL)); + ggml_backend_t backend = new ggml_backend { + /* .guid = */ ggml_backend_opencl_guid(), + /* .iface = */ ggml_backend_opencl_i, + /* .device = */ dev, + /* .context = */ backend_ctx + }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return backend; } -static ggml_status ggml_backend_opencl_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; +bool ggml_backend_is_opencl(ggml_backend_t backend) { + return backend && backend->iface.get_name == ggml_backend_opencl_name; +} - for (int i = 0; i < cgraph->n_nodes; i++) { - ggml_tensor * node = cgraph->nodes[i]; +// +// buffer +// +struct ggml_backend_opencl_buffer_context { + // A buffer context can hold multiple cl_mem objects. This is for flattening + // quantized weights and should be used with GGML_OPENCL_SMALL_ALLOC where + // each tensor is allocated a separate buffer. When flattening is enabled + // with small allocation, each tensor is backed by two cl_mem objects (for + // quants and scales) packed into a backend_opencl_buffer. + ggml_backend_opencl_buffer_context(cl_mem buf) + : name("OpenCL") { + buffer.push_back(buf); + } - // NOTE: this may oversynchronize by synchronizing with - // backends/devices which don't compute 'cgraph's - // dependencies. - sync_with_other_backends(backend); + ~ggml_backend_opencl_buffer_context() { + for (cl_mem buf : buffer) { + CL_CHECK(clReleaseMemObject(buf)); + } + for (cl_mem im : img) { + CL_CHECK(clReleaseMemObject(im)); + } - if (ggml_is_empty(node) || node->op == GGML_OP_RESHAPE || node->op == GGML_OP_TRANSPOSE || node->op == GGML_OP_VIEW || node->op == GGML_OP_PERMUTE || node->op == GGML_OP_NONE) { - continue; + // Delete all extras to trigger their destructors + for (ggml_tensor_extra_cl * e : temp_tensor_extras) { + delete e; + } + for (ggml_tensor_extra_cl * e : temp_tensor_extras_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0) { + delete e; + } + for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1) { + delete e; + } + for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0) { + delete e; + } + for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1) { + delete e; + } + for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4) { + delete e; + } + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0) { + delete e; + } + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0) { + delete e; + } + for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl) { + delete e; + } + for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl_in_use) { + delete e; } - - if ((node->flags & GGML_TENSOR_FLAG_COMPUTE) == 0) { - continue; + for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K) { + delete e; } - - if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { - ggml_opencl_op_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); - i += 2; - continue; + for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K_in_use) { + delete e; } - if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_GROUP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { - ggml_opencl_op_group_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); - i += 2; - continue; + for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K) { + delete e; } - // Fuse the MoE combine: router-weight mul + cross-expert add chain -> - // one weighted-sum-across-experts kernel. - // Fold the gpt-oss MoE bias epilogue: add_id(gate_bias) + add_id(up_bias) + - // glu(swiglu_oai) -> one kernel, leaving the two matmuls as their own dispatches. - // Both add_ids are in-place passes over a tensor the GLU reads again, so this - // drops two full read+write passes per layer. Opt out GGML_OPENCL_FUSE_MOE_BIAS_GLU=0. - if (backend_ctx->fuse_moe_bias_glu && !backend_ctx->disable_fusion && - ggml_opencl_can_fuse_moe_bias_glu(cgraph, i)) { - ggml_cl_moe_bias_glu_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2], - cgraph->nodes[i+3], cgraph->nodes[i+4]); - i += 4; - continue; + for (ggml_tensor_extra_cl_q2_K * e : temp_tensor_extras_q2_K) { + delete e; } - - // Fold the MoE down-projection bias into the combine: add_id(down_bias) + the whole - // combine subgraph -> one kernel. Checked before the plain combine arm so the longer - // pattern wins. Opt out GGML_OPENCL_FUSE_MOE_BIAS_COMBINE=0. - if (backend_ctx->fuse_moe_bias_combine && backend_ctx->fuse_moe_combine && - !backend_ctx->disable_fusion) { - const ggml_tensor * bias_combine_out = nullptr; - if (ggml_opencl_can_fuse_moe_bias_combine(cgraph, i, &bias_combine_out)) { - ggml_cl_moe_bias_combine_fused(backend, node, cgraph->nodes[i+1], bias_combine_out); - i += 2 * (int)node->ne[1]; // ADD_ID + MUL + k VIEWs + (k-1) ADDs - continue; - } + for (ggml_tensor_extra_cl_q3_K * e : temp_tensor_extras_q3_K) { + delete e; } - - if (backend_ctx->fuse_moe_combine && !backend_ctx->disable_fusion) { - const ggml_tensor * combine_out = nullptr; - if (ggml_opencl_can_fuse_moe_combine(cgraph, i, &combine_out)) { - ggml_cl_moe_combine_fused(backend, node, combine_out); - i += 2 * (int)node->ne[1] - 1; // skip the k VIEWs + (k-1) ADDs - continue; - } + for (ggml_tensor_extra_cl_iq2_s * e : temp_tensor_extras_iq2_s) { + delete e; } - - // Fuse rms_norm + mul(weight) + add(residual). Checked before the - // rms_norm+mul fuse so the 3-op pattern wins over its 2-op prefix. - // Default on, opt-out GGML_OPENCL_FUSE_RMS_ADD=0. - if (!backend_ctx->disable_fusion && backend_ctx->fuse_rms_add && - ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL, GGML_OP_ADD })) { - ggml_opencl_op_rms_norm_mul_add_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); - i += 2; - continue; + for (ggml_tensor_extra_cl_iq2_xs * e : temp_tensor_extras_iq2_xs) { + delete e; } - if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) { - ggml_opencl_op_rms_norm_fused(backend, node, cgraph->nodes[i+1]); - i++; - continue; + for (ggml_tensor_extra_cl_iq2_xxs * e : temp_tensor_extras_iq2_xxs) { + delete e; } - // Fuse mul_mat(Wg,x) + mul_mat(Wu,x) + glu — fold the FFN's two decode - // GEMVs and the GLU into one dispatch. q4_K only (guarded below); the - // fused kernel uses the same accumulation/reduction order and the same - // scalar GLU formula -> coherent. Default on, opt-out GGML_OPENCL_FUSE_MM_GLU=0. -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // The fused executor (ggml_cl_mul_mat_q4_k_glu_fused) is image-path / - // Adreno-only (GGML_ABORT on the non-Adreno #else); gate the dispatch to - // match so the FFN GLU subgraph stays dormant on Intel/other drivers. - if (backend_ctx->fuse_mm_glu && !backend_ctx->disable_fusion && - ggml_opencl_can_fuse(backend_ctx, cgraph, i, { GGML_OP_MUL_MAT, GGML_OP_MUL_MAT, GGML_OP_GLU })) { - ggml_cl_mul_mat_q4_k_glu_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); - i += 2; - continue; + for (ggml_tensor_extra_cl_q2_0 * e : temp_tensor_extras_q2_0) { + delete e; } -#endif - - bool ok = ggml_cl_compute_forward(backend, node); - if (!ok) { - GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); + for (ggml_tensor_extra_cl_iq1_m * e : temp_tensor_extras_iq1_m) { + delete e; + } + for (ggml_tensor_extra_cl_iq1_s * e : temp_tensor_extras_iq1_s) { + delete e; + } + for (ggml_tensor_extra_cl_iq3_s * e : temp_tensor_extras_iq3_s) { + delete e; + } + for (ggml_tensor_extra_cl_iq3_xxs * e : temp_tensor_extras_iq3_xxs) { + delete e; + } + for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q2_K * e : temp_tensor_extras_q2_K_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q3_K * e : temp_tensor_extras_q3_K_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq2_s * e : temp_tensor_extras_iq2_s_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq2_xs * e : temp_tensor_extras_iq2_xs_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq2_xxs * e : temp_tensor_extras_iq2_xxs_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q2_0 * e : temp_tensor_extras_q2_0_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq1_m * e : temp_tensor_extras_iq1_m_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq1_s * e : temp_tensor_extras_iq1_s_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq3_s * e : temp_tensor_extras_iq3_s_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_iq3_xxs * e : temp_tensor_extras_iq3_xxs_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K) { + delete e; + } + for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K_in_use) { + delete e; } - GGML_ASSERT(ok); } - return GGML_STATUS_SUCCESS; -} - -// The optimized gemm and gemv kernels are used for large matrices without batch. -// tensor is the quantized weights matrix. -inline bool use_adreno_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - int64_t threshold_ne0 = 512; - int64_t threshold_ne1 = 512; - if (!backend_ctx->adreno_cl_compiler_version.newer_than_or_same(E031, 38, 11, 0) && - backend_ctx->adreno_cl_compiler_version.type != DX) { - threshold_ne0 = 128; - threshold_ne1 = 128; - } - bool threashold_ok = tensor->ne[0] >= threshold_ne0 && tensor->ne[1] >= threshold_ne1 && - tensor->ne[2] == 1 && tensor->ne[3] == 1; + ggml_tensor_extra_cl * ggml_opencl_alloc_temp_tensor_extra() { + ggml_tensor_extra_cl * extra; + if (temp_tensor_extras.empty()) { + extra = new ggml_tensor_extra_cl(); + } else { + extra = temp_tensor_extras.back(); + temp_tensor_extras.pop_back(); + } - // the transposed layout needs K % 32 == 0 and M % 4 == 0 - if (tensor->ne[0] % 32 != 0 || tensor->ne[1] % 4 != 0) { - return false; - } + temp_tensor_extras_in_use.push_back(extra); - // The noshuffle layout packs 2 rows per 32-bit texel and the GEMV reads it at an - // ne1/2 texel stride with an exact-cover dispatch, so it is only addressable when - // ne1 is a multiple of 64; an unaligned ne1 truncates the stride and the weight is - // read misaligned. That is a property of the layout, not of one quant -- q4_K, q5_K - // and q8_0 read the same packing as q6_K. The bound is 64, not 128: a q8_0 attention - // weight of ne1 = 2880 is a multiple of 64 but not 128 and is correct. - switch (tensor->type) { - case GGML_TYPE_Q4_K: - case GGML_TYPE_Q5_K: - case GGML_TYPE_Q6_K: - case GGML_TYPE_Q8_0: - return threashold_ok && tensor->ne[1] % 64 == 0; - default: - break; + extra->reset(); + return extra; } - return threashold_ok; -} -static bool adreno_e17_compiler_quirks(const ggml_backend_opencl_context *backend_ctx) { - if (!backend_ctx || backend_ctx->gpu_family != GPU_FAMILY::ADRENO || - backend_ctx->adreno_cl_compiler_version.type != ADRENO_CL_COMPILER_TYPE::E17) { - return false; - } - const char * env = getenv("GGML_OPENCL_ADRENO_E17_QUIRKS"); - return !(env && env[0] == '0'); -} + ggml_tensor_extra_cl_q1_0 * ggml_opencl_alloc_temp_tensor_extra_q1_0() { + ggml_tensor_extra_cl_q1_0 * extra; + if (temp_tensor_extras_q1_0.empty()) { + extra = new ggml_tensor_extra_cl_q1_0(); + } else { + extra = temp_tensor_extras_q1_0.back(); + temp_tensor_extras_q1_0.pop_back(); + } -inline bool use_adreno_moe_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - // The moe weight repack kernels *_trans4_ns alias a private ushort8 through a uchar*. - // Certain compilers (found with some A7x and A6x) miscompiles this, corrupting the weights. - // So, exclude A6x and A7x from using Adreno MoE kernels for now. - // The quants that have a general mul_mat_id kernel fallback to the general version; the - // rest fallback to CPU. - if (backend_ctx && (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A6X || - backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X || - backend_ctx->adreno_gen == ADRENO_GPU_GEN::ADRENO_UNKNOWN)) { - return false; - } + temp_tensor_extras_q1_0_in_use.push_back(extra); - if (adreno_e17_compiler_quirks(backend_ctx)) { - return false; + extra->reset(); + return extra; } - int ne01 = tensor->ne[1]; - return (((strstr(tensor->name, "ffn") != NULL) && (strstr(tensor->name, "exps") != NULL)) || (strstr(tensor->name, "as") != NULL)) && (ne01 % 32 == 0); -} + ggml_tensor_extra_cl_q4_0 * ggml_opencl_alloc_temp_tensor_extra_q4_0() { + ggml_tensor_extra_cl_q4_0 * extra; + if (temp_tensor_extras_q4_0.empty()) { + extra = new ggml_tensor_extra_cl_q4_0(); + } else { + extra = temp_tensor_extras_q4_0.back(); + temp_tensor_extras_q4_0.pop_back(); + } -// Device default for the tiled-wide lm_head/embed GEMV layout: ON for X2E and A8X. -// -// These kernels were previously off everywhere on the grounds that they compute -// wrong values at multi-superblock K. They do not: that NMSE ~2 came from the -// backend having no get_tensor restore path for the tiled layout, so -// test-backend-ops (which builds its CPU reference by copying the weights back -// out of the backend) compared a correct GPU result against a reference -// dequantized from tiled bytes. With the restore path added, MUL_MAT passes with -// the tiled kernels on, unmodified, on both devices. -// -// Perf, Qwen3-4B-Q4_K_M (q6_K lm_head 151936x2560), tg128, matched pairs with -// alternating lead, tiled vs o4: -// -// A8X +11.9% 6/6 pairs positive, order bias -0.06% (16.93 vs 15.14 tok/s) -// X2E +6.9% 4/4 pairs positive, order bias -0.03% (35.24 vs 32.87 tok/s) -// -// Measure this one on a COLD device. These kernels are far more clock-sensitive -// than the o4 route they replace: on a heat-soaked A8X (CPU cap at 1.5-1.9 GHz) -// tiled pins at ~14.2 tok/s while o4 still makes ~14.9, which reads as a 4-5% -// LOSS and inverts the ranking. The same box, after a reboot and a gate that -// waits for policy6 to return to 4396800, reports the +11.9% above with no -// order bias. A7X regresses hard on this layout and stays off. -// GGML_OPENCL_{Q4K,Q6K}_GEMV_TILED forces either way (=0 off, any other value on). -inline bool tiled_gemv_default_on(const ggml_backend_opencl_context *backend_ctx) { - return backend_ctx && (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || - backend_ctx->adreno_gen == ADRENO_GPU_GEN::A8X); -} + temp_tensor_extras_q4_0_in_use.push_back(extra); -// Tiled-wide q6_K GEMV (default OFF; GGML_OPENCL_Q6K_GEMV_TILED forces either -// way: =0 off everywhere, any other value on everywhere). -// Both the convert (set_tensor) and the GEMV dispatch must agree on this so the -// buffer layout matches the kernel. -inline bool q6k_gemv_tiled_enabled(const ggml_backend_opencl_context *backend_ctx) { - static const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_TILED"); - if (e && e[0] != '\0') { - return e[0] != '0'; + extra->reset(); + return extra; } - return tiled_gemv_default_on(backend_ctx); -} -// Only the long-vocab lm_head/embed shapes use the tiled layout; ne01 % 64 == 0 -// is required by the 64-row tiling (no row padding in the buffers). -// use_adreno_kernels is required: only the Adreno GEMV path can read the tiled -// layout, so converting a weight it would decline (e.g. ne00 < 512) leaves the -// generic kernel reading tiled bytes as plain SOA. -inline bool use_q6k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - return q6k_gemv_tiled_enabled(backend_ctx) && tensor->type == GGML_TYPE_Q6_K && - tensor->ne[1] >= 32768 && tensor->ne[1] % 64 == 0 && - use_adreno_kernels(backend_ctx, tensor); -} + ggml_tensor_extra_cl_q4_1 * ggml_opencl_alloc_temp_tensor_extra_q4_1() { + ggml_tensor_extra_cl_q4_1 * extra; + if (temp_tensor_extras_q4_1.empty()) { + extra = new ggml_tensor_extra_cl_q4_1(); + } else { + extra = temp_tensor_extras_q4_1.back(); + temp_tensor_extras_q4_1.pop_back(); + } + + temp_tensor_extras_q4_1_in_use.push_back(extra); -// q4_K analog of the tiled-wide lm_head/embed GEMV (default OFF; -// GGML_OPENCL_Q4K_GEMV_TILED forces either way: =0 off, else on). Same gate. -inline bool q4k_gemv_tiled_enabled(const ggml_backend_opencl_context *backend_ctx) { - static const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_TILED"); - if (e && e[0] != '\0') { - return e[0] != '0'; + extra->reset(); + return extra; } - return tiled_gemv_default_on(backend_ctx); -} -inline bool use_q4k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - return q4k_gemv_tiled_enabled(backend_ctx) && tensor->type == GGML_TYPE_Q4_K && - tensor->ne[1] >= 32768 && tensor->ne[1] % 64 == 0 && - use_adreno_kernels(backend_ctx, tensor); -} -inline bool enable_adreno_trans_weight(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { + ggml_tensor_extra_cl_q5_0 * ggml_opencl_alloc_temp_tensor_extra_q5_0() { + ggml_tensor_extra_cl_q5_0 * extra; + if (temp_tensor_extras_q5_0.empty()) { + extra = new ggml_tensor_extra_cl_q5_0(); + } else { + extra = temp_tensor_extras_q5_0.back(); + temp_tensor_extras_q5_0.pop_back(); + } - bool adreno_kernel = use_adreno_kernels(backend_ctx, tensor); + temp_tensor_extras_q5_0_in_use.push_back(extra); - size_t elem_num = tensor->ne[0] * tensor->ne[1] * tensor->ne[2] * tensor->ne[3]; + extra->reset(); + return extra; + } - // The 2D weight transpose (transpose_2d_as_*) tiles rows by 4 over a 2D matrix, - // so it requires K(ne0)%32==0, M(ne1)%4==0 and ne2==ne3==1. - const bool shape_ok = (tensor->ne[0] % 32 == 0) && (tensor->ne[1] % 4 == 0) && - (tensor->ne[2] == 1) && (tensor->ne[3] == 1); + ggml_tensor_extra_cl_q5_1 * ggml_opencl_alloc_temp_tensor_extra_q5_1() { + ggml_tensor_extra_cl_q5_1 * extra; + if (temp_tensor_extras_q5_1.empty()) { + extra = new ggml_tensor_extra_cl_q5_1(); + } else { + extra = temp_tensor_extras_q5_1.back(); + temp_tensor_extras_q5_1.pop_back(); + } - return ((elem_num < 128 * 1024 * 1024) && adreno_kernel && shape_ok); // max element num: 2**27 -} + temp_tensor_extras_q5_1_in_use.push_back(extra); -inline bool enable_adreno_trans_weight_q5_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - if (!use_adreno_kernels(backend_ctx, tensor)) { - return false; + extra->reset(); + return extra; } - const size_t elem_num = ggml_nelements(tensor); - const size_t q_img_width = elem_num / 8; - const size_t qh_img_width = elem_num / 16; - const bool shape_ok = tensor->ne[0] % 32 == 0 && tensor->ne[1] % 4 == 0 && - tensor->ne[2] == 1 && tensor->ne[3] == 1; + ggml_tensor_extra_cl_mxfp4 * ggml_opencl_alloc_temp_tensor_extra_mxfp4() { + ggml_tensor_extra_cl_mxfp4 * extra; + if (temp_tensor_extras_mxfp4.empty()) { + extra = new ggml_tensor_extra_cl_mxfp4(); + } else { + extra = temp_tensor_extras_mxfp4.back(); + temp_tensor_extras_mxfp4.pop_back(); + } - return shape_ok && q_img_width <= backend_ctx->image_max_buffer_size && - qh_img_width <= backend_ctx->image_max_buffer_size; -} + temp_tensor_extras_mxfp4_in_use.push_back(extra); -inline bool use_q4_0_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (!backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans || - !backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin) { - return false; + extra->reset(); + return extra; } - // bin kernels require ne2 == 1 and ne3 == 1 for weights - return tensor->ne[2] == 1 && tensor->ne[3] == 1 && - (tensor->ne[0] % 32 == 0) && (tensor->ne[1] % 64 == 0); -#else - GGML_UNUSED(backend_ctx); - GGML_UNUSED(tensor); - return false; -#endif -} + ggml_tensor_extra_cl_q8_0 * ggml_opencl_alloc_temp_tensor_extra_q8_0() { + ggml_tensor_extra_cl_q8_0 * extra; + if (temp_tensor_extras_q8_0.empty()) { + extra = new ggml_tensor_extra_cl_q8_0(); + } else { + extra = temp_tensor_extras_q8_0.back(); + temp_tensor_extras_q8_0.pop_back(); + } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static bool use_fa_bin_kernels_prefill(const ggml_backend_opencl_context * backend_ctx, const ggml_tensor * q, const ggml_tensor * k, const ggml_tensor * v) { - if (backend_ctx->fa.kernel_flash_attn_f32_f16_bin == nullptr) { - return false; + temp_tensor_extras_q8_0_in_use.push_back(extra); + + extra->reset(); + return extra; } - const bool is_mixed = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && v->type == GGML_TYPE_F16; - const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; + ggml_tensor_extra_cl_iq4_nl * ggml_opencl_alloc_temp_tensor_extra_iq4_nl() { + ggml_tensor_extra_cl_iq4_nl * extra; + if (temp_tensor_extras_iq4_nl.empty()) { + extra = new ggml_tensor_extra_cl_iq4_nl(); + } else { + extra = temp_tensor_extras_iq4_nl.back(); + temp_tensor_extras_iq4_nl.pop_back(); + } - const int n_q = q->ne[1]; - const int dk = q->ne[0]; - const int dv = v->ne[0]; + temp_tensor_extras_iq4_nl_in_use.push_back(extra); - constexpr bool prefill_only = true; + extra->reset(); + return extra; + } - return (backend_ctx->gpu_family == GPU_FAMILY::ADRENO && - (is_mixed || is_q8_0) && (dk == dv) - && (dk == 64 || dk == 128 || dk == 256 || dk == 512) - && (!prefill_only || n_q != 1)); -} -#endif + ggml_tensor_extra_cl_q4_K * ggml_opencl_alloc_temp_tensor_extra_q4_K() { + ggml_tensor_extra_cl_q4_K * extra; + if (temp_tensor_extras_q4_K.empty()) { + extra = new ggml_tensor_extra_cl_q4_K(); + } else { + extra = temp_tensor_extras_q4_K.back(); + temp_tensor_extras_q4_K.pop_back(); + } -// The flat-GEMV large-m escape is OPT-IN (GGML_OPENCL_FLAT_LARGE_M=1) because it -// is SLOWER than the route it replaces, not because it is unsafe. It was first -// parked on the theory that it out-of-bounds-writes at vocab-scale shapes; that -// was a misattribution (the test-backend-ops dst sentinel was tripped by the o4 -// GEMV's unguarded tail store, fixed separately - and at the shape it was blamed -// for, k=1536, this predicate returns false anyway, so the flat route never ran). -// -// The escape's original rationale, "gemv_noshuffle perf drops for large M", -// predates the o4 kernel, which now covers the same long-vocab shapes and beats -// this route on every device measured (Qwen3-4B-Q4_K_M, q6_K lm_head -// 151936x2560, tg128, matched pairs vs o4): A8X -10.3% (0/3 pairs), X2E -3.7% -// (0/3). Keep it reachable for shapes o4 declines, but do not default it on. -static inline bool flat_large_m_enabled() { - static const char * e = getenv("GGML_OPENCL_FLAT_LARGE_M"); - static const bool en = e != nullptr && atoi(e) != 0; - return en; -} + temp_tensor_extras_q4_K_in_use.push_back(extra); -// The noshuffle Q4_K weight image stores eight weights per uint texel. -static inline bool q4_K_weight_image_fits(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - const size_t texels = (size_t) ggml_nelements(tensor) / 8; - return texels != 0 && texels <= backend_ctx->image_max_buffer_size; -} + extra->reset(); + return extra; + } -static inline bool use_flat_gemv_for_large_m_q4_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - if (tensor->ne[1] % 4 != 0 && tensor->ne[2] == 1 && tensor->ne[3] == 1) { - return true; + ggml_tensor_extra_cl_q5_K * ggml_opencl_alloc_temp_tensor_extra_q5_K() { + ggml_tensor_extra_cl_q5_K * extra; + if (temp_tensor_extras_q5_K.empty()) { + extra = new ggml_tensor_extra_cl_q5_K(); + } else { + extra = temp_tensor_extras_q5_K.back(); + temp_tensor_extras_q5_K.pop_back(); + } + + temp_tensor_extras_q5_K_in_use.push_back(extra); + + extra->reset(); + return extra; } - if (tensor->ne[2] != 1 || tensor->ne[3] != 1 || use_q4k_tiled(backend_ctx, tensor)) { - return false; + ggml_tensor_extra_cl_q2_K * ggml_opencl_alloc_temp_tensor_extra_q2_K() { + ggml_tensor_extra_cl_q2_K * extra; + if (temp_tensor_extras_q2_K.empty()) { + extra = new ggml_tensor_extra_cl_q2_K(); + } else { + extra = temp_tensor_extras_q2_K.back(); + temp_tensor_extras_q2_K.pop_back(); + } + + temp_tensor_extras_q2_K_in_use.push_back(extra); + + extra->reset(); + return extra; } - // The image limit is a correctness guard, independent of the large-M opt-in. - if (!q4_K_weight_image_fits(backend_ctx, tensor)) { - return true; + ggml_tensor_extra_cl_q3_K * ggml_opencl_alloc_temp_tensor_extra_q3_K() { + ggml_tensor_extra_cl_q3_K * extra; + if (temp_tensor_extras_q3_K.empty()) { + extra = new ggml_tensor_extra_cl_q3_K(); + } else { + extra = temp_tensor_extras_q3_K.back(); + temp_tensor_extras_q3_K.pop_back(); + } + + temp_tensor_extras_q3_K_in_use.push_back(extra); + + extra->reset(); + return extra; } - // gemv_noshuffle variant perf drops for large M, use flat variant for large M. - // threshold is well above typical hidden/FFN dims, but below typical vocab sizes. - // note that this forces large M weights to use LM GEMM. - return flat_large_m_enabled() && tensor->ne[1] >= 32768; -} + ggml_tensor_extra_cl_iq2_s * ggml_opencl_alloc_temp_tensor_extra_iq2_s() { + ggml_tensor_extra_cl_iq2_s * extra; + if (temp_tensor_extras_iq2_s.empty()) { + extra = new ggml_tensor_extra_cl_iq2_s(); + } else { + extra = temp_tensor_extras_iq2_s.back(); + temp_tensor_extras_iq2_s.pop_back(); + } -static inline bool use_flat_gemv_for_large_m_q6_K(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { - // NOTE on ordering: the ne01 % 128 escape below is a CORRECTNESS guard, not a - // performance one, so it must be reachable regardless of flat_large_m_enabled(). - // The opt-in gate therefore sits after it, and after the tiled deferral. - // gemv_noshuffle variant perf drops for large M, use flat variant for large M. - // threshold is well above typical hidden/FFN dims, but below typical vocab sizes. - // q6_K flat gemv is worse for smaller K; 2048 seems to be a reasonable threshold. - // note that this forces large M weights to use LM GEMM. - // When this branch's tiled-canonical lm_head/embed layout is active, the weight is - // converted to the 64-row tiled layout, which the flat gemv would misread as - // garbage. use_q6k_tiled owns these large-M weights (it requires ne01 % 64 == 0, - // so it never claims an odd-vocab weight), so defer to it first. - if (use_q6k_tiled(backend_ctx, tensor)) { - return false; + temp_tensor_extras_iq2_s_in_use.push_back(extra); + + extra->reset(); + return extra; } - // The noshuffle (transposed-weight) layout packs 2 rows per 32-bit texel and the - // gemv reads it with a ne01/2 texel stride and an exact-cover dispatch of - // ceil(ne01/2 / 64)*64 work-items with no store guard; the gemm uses 4-row tiles. - // It is therefore only correct for ne01 % 128 == 0: an odd ne01 (e.g. granitemoe - // lm_head [1536, 49155] -- odd vocab) truncates the texel stride, misaligning every - // odd column of the transposed layout (gross garbage) and dropping the last row; - // other non-multiples over-dispatch and write past the end of dst. Route such - // tensors to the flat GEMV + regular convert; the matching GEMM (ne1>1) falls back - // to CPU (see supports_op). All standard even-vocab/hidden dims are multiples of - // 128 and keep the noshuffle path. - if ((tensor->ne[1] % 128 != 0) && tensor->ne[2] == 1 && tensor->ne[3] == 1) { - return true; + + ggml_tensor_extra_cl_iq2_xs * ggml_opencl_alloc_temp_tensor_extra_iq2_xs() { + ggml_tensor_extra_cl_iq2_xs * extra; + if (temp_tensor_extras_iq2_xs.empty()) { + extra = new ggml_tensor_extra_cl_iq2_xs(); + } else { + extra = temp_tensor_extras_iq2_xs.back(); + temp_tensor_extras_iq2_xs.pop_back(); + } + + temp_tensor_extras_iq2_xs_in_use.push_back(extra); + + extra->reset(); + return extra; } - if (!flat_large_m_enabled()) { - return false; + ggml_tensor_extra_cl_iq2_xxs * ggml_opencl_alloc_temp_tensor_extra_iq2_xxs() { + ggml_tensor_extra_cl_iq2_xxs * extra; + if (temp_tensor_extras_iq2_xxs.empty()) { + extra = new ggml_tensor_extra_cl_iq2_xxs(); + } else { + extra = temp_tensor_extras_iq2_xxs.back(); + temp_tensor_extras_iq2_xxs.pop_back(); + } + + temp_tensor_extras_iq2_xxs_in_use.push_back(extra); + + extra->reset(); + return extra; } - // The gemv_noshuffle slowdown tracks TOTAL weight size, not ne0 alone; ne0 >= 2048 is a - // proxy for "large weight" that misses a narrow-hidden vocab-scale lm_head. - // Add a direct size escape so such weights also take the flat path, without changing - // which weights ne0 >= 2048 already routes there. - // The size escape is not taken on the A7X since its compiler miscompiles the flat K-quant GEMV - return tensor->ne[1] >= 32768 - && (tensor->ne[0] >= 2048 || (backend_ctx->adreno_gen != ADRENO_GPU_GEN::A7X && ggml_nbytes(tensor) >= (256ull << 20))) - && tensor->ne[2] == 1 && tensor->ne[3] == 1; -} + ggml_tensor_extra_cl_q2_0 * ggml_opencl_alloc_temp_tensor_extra_q2_0() { + ggml_tensor_extra_cl_q2_0 * extra; + if (temp_tensor_extras_q2_0.empty()) { + extra = new ggml_tensor_extra_cl_q2_0(); + } else { + extra = temp_tensor_extras_q2_0.back(); + temp_tensor_extras_q2_0.pop_back(); + } -inline bool use_q6_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (!backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans || - !backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin) { - return false; + temp_tensor_extras_q2_0_in_use.push_back(extra); + + extra->reset(); + return extra; } - // bin kernels require ne2 == 1 and ne3 == 1 for weights - return tensor->ne[2] == 1 && tensor->ne[3] == 1 && - (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0) && - !use_q6k_tiled(backend_ctx, tensor) && !use_flat_gemv_for_large_m_q6_K(backend_ctx, tensor); -#else - GGML_UNUSED(backend_ctx); - GGML_UNUSED(tensor); - return false; -#endif -} -inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (!backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans || - !backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin) { - return false; + ggml_tensor_extra_cl_iq1_m * ggml_opencl_alloc_temp_tensor_extra_iq1_m() { + ggml_tensor_extra_cl_iq1_m * extra; + if (temp_tensor_extras_iq1_m.empty()) { + extra = new ggml_tensor_extra_cl_iq1_m(); + } else { + extra = temp_tensor_extras_iq1_m.back(); + temp_tensor_extras_iq1_m.pop_back(); + } + + temp_tensor_extras_iq1_m_in_use.push_back(extra); + + extra->reset(); + return extra; } - // bin kernels require ne2 == 1 and ne3 == 1 for weights - return tensor->ne[2] == 1 && tensor->ne[3] == 1 && - (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0) && - !use_q4k_tiled(backend_ctx, tensor) && !use_flat_gemv_for_large_m_q4_K(backend_ctx, tensor); -#else - GGML_UNUSED(backend_ctx); - GGML_UNUSED(tensor); - return false; -#endif -} -inline bool use_q5_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (!backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans || - !backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin) { - return false; + ggml_tensor_extra_cl_iq1_s * ggml_opencl_alloc_temp_tensor_extra_iq1_s() { + ggml_tensor_extra_cl_iq1_s * extra; + if (temp_tensor_extras_iq1_s.empty()) { + extra = new ggml_tensor_extra_cl_iq1_s(); + } else { + extra = temp_tensor_extras_iq1_s.back(); + temp_tensor_extras_iq1_s.pop_back(); + } + + temp_tensor_extras_iq1_s_in_use.push_back(extra); + + extra->reset(); + return extra; } - return (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0); -#else - GGML_UNUSED(backend_ctx); - GGML_UNUSED(tensor); - return false; -#endif -} -static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *)dev->context; - ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx; + ggml_tensor_extra_cl_iq3_s * ggml_opencl_alloc_temp_tensor_extra_iq3_s() { + ggml_tensor_extra_cl_iq3_s * extra; + if (temp_tensor_extras_iq3_s.empty()) { + extra = new ggml_tensor_extra_cl_iq3_s(); + } else { + extra = temp_tensor_extras_iq3_s.back(); + temp_tensor_extras_iq3_s.pop_back(); + } - // reject ops that match the opfilter regex - if (dev_ctx->opfilter && std::regex_match(std::string(ggml_op_desc(op)), *dev_ctx->opfilter)) { - return false; + temp_tensor_extras_iq3_s_in_use.push_back(extra); + + extra->reset(); + return extra; } - switch (op->op) { - case GGML_OP_NONE: - return true; - case GGML_OP_GET_ROWS: - switch (op->src[0]->type) { - case GGML_TYPE_F32: - case GGML_TYPE_F16: - return true; - case GGML_TYPE_Q4_0: -#ifdef GGML_OPENCL_SOA_Q - // We do not support flattened Q4_0 (and possibly other Q's) - return false; -#else // GGML_OPENCL_SOA_Q - return true; -#endif // GGML_OPENCL_SOA_Q - default: - return false; - } - case GGML_OP_SET_ROWS: - { - // TODO: add support - // ref: https://github.com/ggml-org/llama.cpp/pull/14274 -#pragma message("TODO: implement BF16, Q4_0, Q4_1, Q5_0, Q5_1, Q8_0, IQ4_NL support (https://github.com/ggml-org/llama.cpp/pull/14661)") - if (op->src[0]->type != GGML_TYPE_F32) { - return false; - } - switch (op->type) { - case GGML_TYPE_F16: - case GGML_TYPE_F32: - case GGML_TYPE_Q8_0: - case GGML_TYPE_Q4_0: - return (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); - default: - return false; - } - } - case GGML_OP_CPY: - case GGML_OP_DUP: - case GGML_OP_CONT: - switch (op->src[0]->type) { - case GGML_TYPE_F32: - switch (op->type) { - case GGML_TYPE_F16: - case GGML_TYPE_F32: - return true; - default: - return false; - } - case GGML_TYPE_F16: - switch (op->type) { - case GGML_TYPE_F16: - case GGML_TYPE_F32: - return true; - default: - return false; - } - case GGML_TYPE_I32: - switch (op->type) { - case GGML_TYPE_I32: - return true; - default: - return false; - } - default: - return false; - } - case GGML_OP_SET: { - return (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_I32) && - op->type == op->src[0]->type && - op->type == op->src[1]->type; + ggml_tensor_extra_cl_iq3_xxs * ggml_opencl_alloc_temp_tensor_extra_iq3_xxs() { + ggml_tensor_extra_cl_iq3_xxs * extra; + if (temp_tensor_extras_iq3_xxs.empty()) { + extra = new ggml_tensor_extra_cl_iq3_xxs(); + } else { + extra = temp_tensor_extras_iq3_xxs.back(); + temp_tensor_extras_iq3_xxs.pop_back(); } - case GGML_OP_SCALE: - return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); - case GGML_OP_ADD: - if (op->type == GGML_TYPE_F16) { - const bool src0_ok = op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32; - const bool src1_ok = op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32; - if (src0_ok && src1_ok) { - return true; - } - } - case GGML_OP_MUL: - case GGML_OP_DIV: - case GGML_OP_SUB: - return (op->src[0]->type == op->src[1]->type) && - (op->src[0]->type == op->type) && - (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16); - case GGML_OP_ADD_ID: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_SQR: - case GGML_OP_SQRT: - return (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16) && - ggml_is_contiguous(op->src[0]); - case GGML_OP_UNARY: - switch (ggml_get_unary_op(op)) { - case GGML_UNARY_OP_GELU: - case GGML_UNARY_OP_SILU: - case GGML_UNARY_OP_RELU: - case GGML_UNARY_OP_GELU_ERF: - case GGML_UNARY_OP_GELU_QUICK: - return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; - case GGML_UNARY_OP_SIGMOID: - return ggml_is_contiguous(op->src[0]); - case GGML_UNARY_OP_TANH: - case GGML_UNARY_OP_NEG: - case GGML_UNARY_OP_EXP: - // Adreno F16 exp/expm1 overflow even post-half->float convert. - return op->src[0]->type == GGML_TYPE_F32; - case GGML_UNARY_OP_EXPM1: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_UNARY_OP_ABS: - case GGML_UNARY_OP_SGN: - case GGML_UNARY_OP_STEP: - case GGML_UNARY_OP_ELU: - case GGML_UNARY_OP_HARDSWISH: - case GGML_UNARY_OP_HARDSIGMOID: - case GGML_UNARY_OP_FLOOR: - case GGML_UNARY_OP_CEIL: - case GGML_UNARY_OP_ROUND: - case GGML_UNARY_OP_TRUNC: - return op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16; - case GGML_UNARY_OP_SOFTPLUS: - return op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16; - default: - return false; - } - case GGML_OP_GLU: - switch (ggml_get_glu_op(op)) { - case GGML_GLU_OP_GEGLU: - case GGML_GLU_OP_REGLU: - case GGML_GLU_OP_SWIGLU: - case GGML_GLU_OP_SWIGLU_OAI: - case GGML_GLU_OP_GEGLU_ERF: - case GGML_GLU_OP_GEGLU_QUICK: - case GGML_GLU_OP_SWIGLU_CLAMP: - return ggml_is_contiguous_1(op->src[0]) && (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16); - default: - return false; - } - case GGML_OP_TRI: - return op->type == GGML_TYPE_F32 && ggml_is_contiguous(op); - case GGML_OP_FILL: - return op->type == GGML_TYPE_F32 && ggml_is_contiguous(op); - case GGML_OP_CLAMP: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_SOFT_MAX: - case GGML_OP_NORM: - return true; - case GGML_OP_RMS_NORM: - return op->ne[0] % 4 == 0 && ggml_is_contiguous_rows(op->src[0]); - case GGML_OP_L2_NORM: - return ggml_is_contiguous_rows(op->src[0]); - case GGML_OP_REPEAT: - return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; // Assuming F32 for now, can be expanded - case GGML_OP_PAD: - // TODO: add circular padding support for opencl, see https://github.com/ggml-org/llama.cpp/pull/16985 - if (ggml_get_op_params_i32(op, 8) != 0) { - return false; - } - return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; - case GGML_OP_UPSCALE: { - ggml_scale_mode mode = (ggml_scale_mode)(ggml_get_op_params_i32(op, 0) & 0xFF); - const bool antialias = (ggml_scale_mode)(ggml_get_op_params_i32(op, 0) & GGML_SCALE_FLAG_ANTIALIAS); - return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && - (mode == GGML_SCALE_MODE_NEAREST || mode == GGML_SCALE_MODE_BILINEAR) && !antialias; + + temp_tensor_extras_iq3_xxs_in_use.push_back(extra); + + extra->reset(); + return extra; + } + + ggml_tensor_extra_cl_q6_K * ggml_opencl_alloc_temp_tensor_extra_q6_K() { + ggml_tensor_extra_cl_q6_K * extra; + if (temp_tensor_extras_q6_K.empty()) { + extra = new ggml_tensor_extra_cl_q6_K(); + } else { + extra = temp_tensor_extras_q6_K.back(); + temp_tensor_extras_q6_K.pop_back(); } - case GGML_OP_CONV_2D: - return (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16) || - (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32) || - (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32); - case GGML_OP_SSM_CONV: - // the channels-major input layout is only implemented on CPU/CUDA - return (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && ggml_ssm_conv_get_layout(op) == GGML_SSM_CONV_LAYOUT_TIME_MAJOR); - case GGML_OP_SSM_SCAN: { - if (op->type != GGML_TYPE_F32 || op->src[0]->type != GGML_TYPE_F32 || - op->src[1]->type != GGML_TYPE_F32 || op->src[2]->type != GGML_TYPE_F32 || - op->src[3]->type != GGML_TYPE_F32 || op->src[4]->type != GGML_TYPE_F32 || - op->src[5]->type != GGML_TYPE_F32 || op->src[6]->type != GGML_TYPE_I32) { - return false; - } - const int64_t d_state = op->src[0]->ne[0]; - return d_state >= 1 && d_state <= 256 && (d_state & (d_state - 1)) == 0; - } - case GGML_OP_GATED_DELTA_NET: - { - // Match the Vulkan backend: only F32 -> F32, S_v in {16, 32, 64, 128}. - if (op->src[0]->type != GGML_TYPE_F32 || op->type != GGML_TYPE_F32) { - return false; - } - const int64_t S_v = op->src[2]->ne[0]; - return S_v == 16 || S_v == 32 || S_v == 64 || S_v == 128; - } - case GGML_OP_CONCAT: - { - const ggml_type t = op->src[0]->type; - return op->src[1]->type == t && op->type == t && - !ggml_is_quantized(t) && ggml_blck_size(t) == 1 && - (ggml_type_size(t) == 1 || ggml_type_size(t) == 2 || - ggml_type_size(t) == 4 || ggml_type_size(t) == 8); - } - case GGML_OP_TIMESTEP_EMBEDDING: - return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; - case GGML_OP_GROUP_NORM: - return ggml_is_contiguous(op->src[0]); - case GGML_OP_MUL_MAT: - if (op->src[0]->type == GGML_TYPE_F16) { - return true; - } else if (op->src[0]->type == GGML_TYPE_BF16) { - return true; - } else if (op->src[0]->type == GGML_TYPE_F32) { - return op->src[1]->type == GGML_TYPE_F32; - } else if (op->src[0]->type == GGML_TYPE_Q1_0) { - return op->src[1]->type == GGML_TYPE_F32; - } else if (op->src[0]->type == GGML_TYPE_Q4_0) { - // Non-contig src0 routes through on-device dequant-to-f16. - return op->src[1]->type == GGML_TYPE_F32; - } else if (op->src[0]->type == GGML_TYPE_Q4_1 || - op->src[0]->type == GGML_TYPE_Q5_0 || op->src[0]->type == GGML_TYPE_Q5_1 || - op->src[0]->type == GGML_TYPE_MXFP4 || - op->src[0]->type == GGML_TYPE_IQ4_NL || - op->src[0]->type == GGML_TYPE_Q4_K || - op->src[0]->type == GGML_TYPE_Q5_K || - op->src[0]->type == GGML_TYPE_Q6_K) { - // The E031.41 compiler (usually with A7x) miscompiles the flat K-quant - // GEMV kernels (kernel_mul_mv_q*_K_f32_flat) and makes lm_head run much - // slower than it should. So, make it fallback to CPU to preserve performance - // for this compiler series. - static const char * a7x_lmhead_env = getenv("GGML_OPENCL_A7X_LMHEAD_CPU"); - static const bool a7x_lmhead_cpu = (a7x_lmhead_env == nullptr || a7x_lmhead_env[0] != '0'); - if (a7x_lmhead_cpu && - backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && - (op->src[0]->type == GGML_TYPE_Q4_K || op->src[0]->type == GGML_TYPE_Q5_K || - op->src[0]->type == GGML_TYPE_Q6_K) && - op->src[0]->ne[1] >= 32768) { // vocab-scale weight; no FFN/attn weight is this tall - return false; - } - // The generic mul_mv (GEMV) kernels are wrong for large-batch prefill on - // Adreno. A quant mul_mat only avoids the GEMV when it reaches the Adreno - // trans-weight GEMM, which needs both a GEMM kernel for the type and - // use_adreno_kernels(). Decline the large-N shapes that would otherwise - // fall through to the GEMV. - { - const ggml_type t = op->src[0]->type; - const bool type_has_gemm = (t == GGML_TYPE_Q4_0 || t == GGML_TYPE_Q4_1 || - t == GGML_TYPE_IQ4_NL || t == GGML_TYPE_Q8_0 || - t == GGML_TYPE_Q4_K || t == GGML_TYPE_Q5_K || - t == GGML_TYPE_Q6_K); - const bool uses_gemm = type_has_gemm && use_adreno_kernels(backend_ctx, op->src[0]); - if (!uses_gemm && op->src[1]->ne[1] >= 512) { - return false; - } - } - return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); - } else if (op->src[0]->type == GGML_TYPE_Q8_0) { - // ggml_cl_mul_mat_q8_0_f32_adreno now honors src1/dst view_offs (the - // activation sub-buffer starts at offset1 and the kernels take offsetd), - // so a broadcast q8_0 matmul (src1 batch > src0 batch, e.g. Qwen3.5-9B-UD - // / Qwen3.6-35B q8_0 GDN ssm_out) runs on GPU via the per-slice broadcast - // iteration in ggml_cl_mul_mat. No special-casing needed. - return op->src[1]->type == GGML_TYPE_F32; - } - return false; - case GGML_OP_MUL_MAT_ID: -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (ggml_get_op_params_i32(op, 3) == GGML_PREC_F32 && - use_adreno_moe_kernels(backend_ctx, op->src[0])) { - return false; - } -#endif - if (op->src[0]->type == GGML_TYPE_Q4_0 || - op->src[0]->type == GGML_TYPE_Q8_0 || - op->src[0]->type == GGML_TYPE_MXFP4) { - if (op->src[1]->type == GGML_TYPE_F32) { - return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); - } - } - // q4_0, q8_0 and mxfp4 have general MUL_MAT_ID support, - // the quantizations here currently do not - they are only supported by Adreno with certain shapes - if (op->src[0]->type == GGML_TYPE_Q4_1 || - op->src[0]->type == GGML_TYPE_Q5_0 || - op->src[0]->type == GGML_TYPE_Q5_1 || - op->src[0]->type == GGML_TYPE_Q4_K || - op->src[0]->type == GGML_TYPE_Q5_K || - op->src[0]->type == GGML_TYPE_Q6_K) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (op->src[1]->type == GGML_TYPE_F32) { - return use_adreno_moe_kernels(backend_ctx, op->src[0]) - && ggml_is_contiguous(op->src[0]) - && ggml_is_contiguous(op->src[1]); - } -#endif - return false; - } - return false; - case GGML_OP_RESHAPE: - case GGML_OP_VIEW: - case GGML_OP_PERMUTE: - case GGML_OP_TRANSPOSE: - return true; - case GGML_OP_DIAG: - return true; - case GGML_OP_DIAG_MASK_INF: - return op->ne[3] == 1; - case GGML_OP_ROPE: { - const int mode = ((const int32_t *) op->op_params)[2]; - const bool is_mrope = mode & GGML_ROPE_TYPE_MROPE; - const bool is_vision = mode == GGML_ROPE_TYPE_VISION; - if (is_mrope && !is_vision) { - if (op->src[0]->type == GGML_TYPE_F32 || - op->src[0]->type == GGML_TYPE_F16) { - return true; - } - return false; - } - if (is_vision) { - if (op->src[0]->type == GGML_TYPE_F32 || - op->src[0]->type == GGML_TYPE_F16) { - return true; - } - return false; - } - return true; + temp_tensor_extras_q6_K_in_use.push_back(extra); + + extra->reset(); + return extra; + } + + void reset() { + for (ggml_tensor_extra_cl * e : temp_tensor_extras_in_use) { + temp_tensor_extras.push_back(e); } - case GGML_OP_SOLVE_TRI: - return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); - case GGML_OP_IM2COL: - return true; - case GGML_OP_ARGSORT: { - load_cl_kernels_argsort(backend_ctx); + temp_tensor_extras_in_use.clear(); + + for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0_in_use) { + temp_tensor_extras_q1_0.push_back(e); + } + temp_tensor_extras_q1_0_in_use.clear(); + + for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0_in_use) { + temp_tensor_extras_q4_0.push_back(e); + } + temp_tensor_extras_q4_0_in_use.clear(); + + for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1_in_use) { + temp_tensor_extras_q4_1.push_back(e); + } + temp_tensor_extras_q4_1_in_use.clear(); + + for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0_in_use) { + temp_tensor_extras_q5_0.push_back(e); + } + temp_tensor_extras_q5_0_in_use.clear(); + + for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1_in_use) { + temp_tensor_extras_q5_1.push_back(e); + } + temp_tensor_extras_q5_1_in_use.clear(); + + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { + temp_tensor_extras_mxfp4.push_back(e); + } + temp_tensor_extras_mxfp4_in_use.clear(); + + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { + temp_tensor_extras_q8_0.push_back(e); + } + temp_tensor_extras_q8_0_in_use.clear(); + + for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl_in_use) { + temp_tensor_extras_iq4_nl.push_back(e); + } + temp_tensor_extras_iq4_nl_in_use.clear(); + + for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K_in_use) { + temp_tensor_extras_q4_K.push_back(e); + } + temp_tensor_extras_q4_K_in_use.clear(); + + for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K_in_use) { + temp_tensor_extras_q5_K.push_back(e); + } + temp_tensor_extras_q5_K_in_use.clear(); + + for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K_in_use) { + temp_tensor_extras_q6_K.push_back(e); + } + temp_tensor_extras_q6_K_in_use.clear(); + + for (ggml_tensor_extra_cl_q2_K * e : temp_tensor_extras_q2_K_in_use) { + temp_tensor_extras_q2_K.push_back(e); + } + temp_tensor_extras_q2_K_in_use.clear(); + + for (ggml_tensor_extra_cl_q3_K * e : temp_tensor_extras_q3_K_in_use) { + temp_tensor_extras_q3_K.push_back(e); + } + temp_tensor_extras_q3_K_in_use.clear(); + + for (ggml_tensor_extra_cl_iq2_s * e : temp_tensor_extras_iq2_s_in_use) { + temp_tensor_extras_iq2_s.push_back(e); + } + temp_tensor_extras_iq2_s_in_use.clear(); + + for (ggml_tensor_extra_cl_iq2_xs * e : temp_tensor_extras_iq2_xs_in_use) { + temp_tensor_extras_iq2_xs.push_back(e); + } + temp_tensor_extras_iq2_xs_in_use.clear(); + + for (ggml_tensor_extra_cl_iq2_xxs * e : temp_tensor_extras_iq2_xxs_in_use) { + temp_tensor_extras_iq2_xxs.push_back(e); + } + temp_tensor_extras_iq2_xxs_in_use.clear(); + + for (ggml_tensor_extra_cl_q2_0 * e : temp_tensor_extras_q2_0_in_use) { + temp_tensor_extras_q2_0.push_back(e); + } + temp_tensor_extras_q2_0_in_use.clear(); + + for (ggml_tensor_extra_cl_iq1_m * e : temp_tensor_extras_iq1_m_in_use) { + temp_tensor_extras_iq1_m.push_back(e); + } + temp_tensor_extras_iq1_m_in_use.clear(); + + for (ggml_tensor_extra_cl_iq1_s * e : temp_tensor_extras_iq1_s_in_use) { + temp_tensor_extras_iq1_s.push_back(e); + } + temp_tensor_extras_iq1_s_in_use.clear(); + + for (ggml_tensor_extra_cl_iq3_s * e : temp_tensor_extras_iq3_s_in_use) { + temp_tensor_extras_iq3_s.push_back(e); + } + temp_tensor_extras_iq3_s_in_use.clear(); + + for (ggml_tensor_extra_cl_iq3_xxs * e : temp_tensor_extras_iq3_xxs_in_use) { + temp_tensor_extras_iq3_xxs.push_back(e); + } + temp_tensor_extras_iq3_xxs_in_use.clear(); + + q8_0_soa_tensors.clear(); + q4_0_soa_tensors.clear(); + } + + // Pools for extras. Available extras are in `temp_tensor_extras`. Extras + // being used are in `temp_tensor_extras_in_use`. At the first run, new + // extras get created and put in `in_use`. When the buffer is reset via + // the `reset` callback, all extras in `in_use` get moved to available extras + // for reuse. + std::vector temp_tensor_extras; + std::vector temp_tensor_extras_in_use; + std::vector temp_tensor_extras_q1_0; + std::vector temp_tensor_extras_q1_0_in_use; + std::vector temp_tensor_extras_q4_0; + std::vector temp_tensor_extras_q4_0_in_use; + std::vector temp_tensor_extras_q4_1; + std::vector temp_tensor_extras_q4_1_in_use; + std::vector temp_tensor_extras_q5_0; + std::vector temp_tensor_extras_q5_0_in_use; + std::vector temp_tensor_extras_q5_1; + std::vector temp_tensor_extras_q5_1_in_use; + std::vector temp_tensor_extras_mxfp4; + std::vector temp_tensor_extras_mxfp4_in_use; + std::vector temp_tensor_extras_q8_0; + std::vector temp_tensor_extras_q8_0_in_use; + std::vector temp_tensor_extras_iq4_nl; + std::vector temp_tensor_extras_iq4_nl_in_use; + std::vector temp_tensor_extras_q4_K; + std::vector temp_tensor_extras_q4_K_in_use; + std::vector temp_tensor_extras_q5_K; + std::vector temp_tensor_extras_q5_K_in_use; + std::vector temp_tensor_extras_q2_K; + std::vector temp_tensor_extras_q3_K; + std::vector temp_tensor_extras_iq2_s; + std::vector temp_tensor_extras_iq2_xs; + std::vector temp_tensor_extras_iq2_xxs; + std::vector temp_tensor_extras_iq3_xxs; + std::vector temp_tensor_extras_q2_K_in_use; + std::vector temp_tensor_extras_q3_K_in_use; + std::vector temp_tensor_extras_iq2_s_in_use; + std::vector temp_tensor_extras_iq2_xs_in_use; + std::vector temp_tensor_extras_iq2_xxs_in_use; + std::vector temp_tensor_extras_q2_0; + std::vector temp_tensor_extras_q2_0_in_use; + std::vector temp_tensor_extras_iq1_s; + std::vector temp_tensor_extras_iq1_m; + std::vector temp_tensor_extras_iq1_m_in_use; + std::vector temp_tensor_extras_iq1_s_in_use; + std::vector temp_tensor_extras_iq3_s; + std::vector temp_tensor_extras_iq3_s_in_use; + std::vector temp_tensor_extras_iq3_xxs_in_use; + std::vector temp_tensor_extras_q6_K; + std::vector temp_tensor_extras_q6_K_in_use; - cl_kernel kernel = backend_ctx->kernel_argsort_f32_i32; - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + // q8_0 tensors with AoS->SoA layout conversion installed by set_tensor. + // Two types of tensors get SOA'ed - normal weights and MoE weights. + // In Q8_0's case, we only have normal weights. If we ever have Q8_0 as MoE + // weights, they need to be added to this set in `set_tensors`. + std::unordered_set q8_0_soa_tensors; - int cols = 1; - while (cols < op->ne[0]) { - cols *= 2; - } + // Same for q4_0. KV-cache q4_0 tensors are allocated but never pass + // through set_tensor, so they stay AoS and aren't in this set. + // In Q4_0's case, in addition to normal weights, we have MoE weights. + std::unordered_set q4_0_soa_tensors; - return cols <= max_workgroup_size && op->src[0]->type == GGML_TYPE_F32; + // The buffer_context is initially created by ggml_backend_buft_alloc_buffer + // before any tensor is initialized (at the beginning of alloc_tensor_range). + // Hence, there is always a buffer object in this vector. When each tensor is + // being initialized, this original buffer object will be released if both + // flattening and small allocation are enabled, and additional buffer + // objects will be created in init_tensor to represent flattened quantized + // weights. + std::vector buffer; + // These are image1d_buffer_t objects that wrap around the quants and scales. + // For Q4_0 quantization, there should be two of them - one for quants and + // one for scales. They should be populated only when flattening and small + // allocation are enabled. + std::vector img; + std::string name; +}; + +static void ggml_backend_opencl_buffer_free_buffer(ggml_backend_buffer_t buffer) { + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + delete ctx; +} + +static void * ggml_backend_opencl_buffer_get_base(ggml_backend_buffer_t buffer) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; + return (void *) (uintptr_t) dev_ctx->backend_ctx->alignment; +} + +static enum ggml_status ggml_backend_opencl_buffer_init_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor) { + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + + if (tensor->view_src != nullptr) { + GGML_ASSERT(tensor->view_src->buffer->buft == buffer->buft); + + ggml_tensor_extra_cl * view_extra = (ggml_tensor_extra_cl *) tensor->view_src->extra; + GGML_ASSERT(view_extra && "view_extra is nullptr?"); + + // Reuse extra of the parent tensor. The offset of this view tensor + // becomes `extra->offset + view_offs` and needs to be calculated when + // it is used. This changes is needed because of the change to + // ggml_alloc.c in https://github.com/ggml-org/llama.cpp/pull/7640. + // `buffer` passed in here will always be `tensor->buffer`. It is OK + // to allocate extras from the same buffer context for ordinary + // intermediate tensors. But for views into kv cache tensors, doing so + // would mess up the extras used by kv cache. + // Before #7640, `buffer` is for intermediate tensors, which is always + // different from that of kv cache tensors. + // + // NB: now extra->offset no longer accounts for view_offs. + // NB: this should not apply to weight tensors (for end-to-end runs, but + // may apply for test-backend-ops). + // FIXME: if any unexpected results are seen, double check the offset - + // there could be other places that need fix. + tensor->extra = view_extra; + } else { + { + size_t offset = (char *) tensor->data - (char *) ggml_backend_opencl_buffer_get_base(buffer); + + ggml_tensor_extra_cl * extra = ctx->ggml_opencl_alloc_temp_tensor_extra(); + extra->offset = offset; + extra->data_device = ctx->buffer[0]; + extra->actual_size = ggml_nbytes(tensor); + + tensor->extra = extra; } - case GGML_OP_SUM_ROWS: - case GGML_OP_CUMSUM: - return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); - case GGML_OP_MEAN: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_FLASH_ATTN_EXT: { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (use_fa_bin_kernels_prefill(backend_ctx, op->src[0], op->src[1], op->src[2])) { - return true; - } -#endif - // The E17 compilers segfault while building FA kernels, skip E17 for now - if (adreno_e17_compiler_quirks(backend_ctx)) { - return false; - } - const ggml_tensor * q = op->src[0]; - const ggml_tensor * k = op->src[1]; - const ggml_tensor * v = op->src[2]; + } + return GGML_STATUS_SUCCESS; +} - const int dk = q->ne[0]; - const int dv = v->ne[0]; +// Allocate a temporary upload buffer of `nbytes` and populate it with `data` +// from host. On Adreno X1-85 the device-only pool intermittently fails to +// allocate at hundreds of MB once model weights fragment the heap (observed +// on Qwen3.5-9B output.weight Q6_K at 834 MB). Three-step retry: +// 1. CL_MEM_READ_WRITE alloc + clEnqueueWriteBuffer (normal fast path). +// 2. clFinish + retry (drains in-flight allocs that may be holding heap; +// mirrors the proven pattern at the FD-split partial buffer alloc). +// 3. CL_MEM_ALLOC_HOST_PTR + map(WRITE_INVALIDATE) + memcpy + unmap — +// different memory pool (host-pinned); true zero-copy on Adreno per +// QCOM guidance. (CL_MEM_USE_HOST_PTR is NOT zero-copy on Adreno: the +// driver triggers an internal copy because arbitrary host pages aren't +// guaranteed mappable/coherent, AND it draws from the same exhausted +// device pool — so it doesn't solve the problem.) +// Returns the ready-to-read buffer (caller must clReleaseMemObject) or NULL +// if all three strategies fail. The buffer is opaque to the caller — it can +// be passed as a kernel argument like any normal cl_mem. +static cl_mem ggml_cl_create_temp_upload_buffer( + cl_context context, cl_command_queue queue, + size_t nbytes, const void * data, + const char * tensor_name_for_log) +{ + cl_int err; + cl_mem buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); + if (err != CL_SUCCESS) { + clFinish(queue); + buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); + } + if (err == CL_SUCCESS) { + const cl_int werr = clEnqueueWriteBuffer(queue, buf, CL_TRUE, 0, nbytes, data, 0, NULL, NULL); + if (werr == CL_SUCCESS) { + return buf; + } + clReleaseMemObject(buf); + } + buf = clCreateBuffer(context, + CL_MEM_READ_ONLY | CL_MEM_ALLOC_HOST_PTR | CL_MEM_HOST_WRITE_ONLY, + nbytes, NULL, &err); + if (err != CL_SUCCESS) { + return NULL; + } + void * mapped = clEnqueueMapBuffer(queue, buf, CL_TRUE, + CL_MAP_WRITE_INVALIDATE_REGION, 0, nbytes, 0, NULL, NULL, &err); + if (err != CL_SUCCESS) { + clReleaseMemObject(buf); + return NULL; + } + memcpy(mapped, data, nbytes); + const cl_int uerr = clEnqueueUnmapMemObject(queue, buf, mapped, 0, NULL, NULL); + if (uerr != CL_SUCCESS) { + clReleaseMemObject(buf); + return NULL; + } + if (tensor_name_for_log) { + GGML_LOG_INFO("ggml_opencl: %s (%.1f MiB) — device alloc failed, using CL_MEM_ALLOC_HOST_PTR fallback\n", + tensor_name_for_log, nbytes / 1024.0 / 1024.0); + } + return buf; +} - const struct { int dk; int dv; } supported_dims[] = { - { 40, 40}, { 64, 64}, { 80, 80}, { 96, 96}, - {112, 112}, {128, 128}, {192, 128}, - {192, 192}, {256, 256}, - {512, 512}, - }; +// Allocate a temporary download buffer of `nbytes`. The caller runs a kernel +// that writes into it, then reads it back to host via clEnqueueReadBuffer (or +// equivalent). Mirrors ggml_cl_create_temp_upload_buffer; the host-pinned +// fallback flags are flipped (CL_MEM_WRITE_ONLY | HOST_READ_ONLY) and the +// helper doesn't populate the buffer. +static cl_mem ggml_cl_create_temp_download_buffer( + cl_context context, cl_command_queue queue, + size_t nbytes, const char * tensor_name_for_log) +{ + cl_int err; + cl_mem buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); + if (err != CL_SUCCESS) { + clFinish(queue); + buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); + } + if (err == CL_SUCCESS) { + return buf; + } + buf = clCreateBuffer(context, + CL_MEM_WRITE_ONLY | CL_MEM_ALLOC_HOST_PTR | CL_MEM_HOST_READ_ONLY, + nbytes, NULL, &err); + if (err != CL_SUCCESS) { + return NULL; + } + if (tensor_name_for_log) { + GGML_LOG_INFO("ggml_opencl: %s download (%.1f MiB) — device alloc failed, using CL_MEM_ALLOC_HOST_PTR fallback\n", + tensor_name_for_log, nbytes / 1024.0 / 1024.0); + } + return buf; +} - bool dims_supported = false; - for (size_t i = 0; i < sizeof(supported_dims)/sizeof(supported_dims[0]); ++i) { - if (supported_dims[i].dk == dk && supported_dims[i].dv == dv) { - dims_supported = true; - break; - } - } - if (!dims_supported) { - return false; - } +static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; + ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx; - const bool is_f32_f32 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F32 && - v->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; - const bool is_f16_f16 = q->type == GGML_TYPE_F16 && k->type == GGML_TYPE_F16 && - v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16; - const bool is_f32_f16 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && - v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F32; + cl_context context = backend_ctx->context; + cl_command_queue queue = backend_ctx->queue; - const bool is_f32_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && - v->type == GGML_TYPE_Q8_0 && op->type == GGML_TYPE_F32 && - dk % 32 == 0 && dv % 32 == 0; - const bool is_f32_q4_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q4_0 && - v->type == GGML_TYPE_Q4_0 && op->type == GGML_TYPE_F32 && - dk % 32 == 0 && dv % 32 == 0; +#ifdef GGML_OPENCL_SOA_Q + if (tensor->type == GGML_TYPE_Q2_K) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); + + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_q2_K * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_q2_K(); + extra->noshuffle = ggml_cl_q2_k_use_noshuffle(backend_ctx, tensor); + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; + + const size_t size_qs = n_blk * (blck/4); + const size_t size_sc = n_blk * (blck/16); + const size_t size_dm = n_blk * 2 * sizeof(ggml_fp16_t); + GGML_ASSERT(size_qs + size_sc + size_dm == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + auto previous_origin = region.origin; + + region.origin = align_to(previous_origin + size_qs, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + previous_origin = region.origin; - // A7X (Adreno 740, compiler E031.41) SIGSEGVs inside clBuildProgram - // building the flash_attn programs whose KV path is mixed-type or - // dequantized — f32_f16, q8_0, q4_0 (reproduced at DK=40 and DK=64; it - // is DK-independent). It is a driver crash, not codegen-wrong-output, so - // it cannot be caught in-process (fatal=false only handles clean compile - // errors). The uniform f16_f16 / f32_f32 programs compile fine on this - // compiler, so decline only the KV-convert variants; ggml then runs - // those (f16-KV / quant-KV) attention layers on the CPU backend. - // Negative compiler carve-out, same idiom as the Intel DK=512 decline - // below and the X1E driver-quirk guards. - if (backend_ctx && backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && - (is_f32_f16 || is_f32_q8_0 || is_f32_q4_0)) { - return false; - } + region.origin = align_to(previous_origin + size_sc, backend_ctx->alignment); + region.size = size_dm; + CL_CHECK((extra->dm = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // Asymmetric KV: host-dequants both sides to F32, uses f32 kernel. - auto is_kv_type_ok = [](ggml_type t) { - return t == GGML_TYPE_F16 || t == GGML_TYPE_F32 || - t == GGML_TYPE_Q4_0 || t == GGML_TYPE_Q8_0; - }; - const bool is_f32_asym = q->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && - k->type != v->type && - is_kv_type_ok(k->type) && is_kv_type_ok(v->type); + cl_kernel kernel = extra->noshuffle ? backend_ctx->kernel_convert_block_q2_k_noshuffle + : backend_ctx->kernel_convert_block_q2_K; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); - const bool kv_combo_ok = is_f32_f32 || is_f16_f16 || is_f32_f16 || - is_f32_q8_0 || is_f32_q4_0 || is_f32_asym; - if (!kv_combo_ok) { - return false; - } + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; - // Some compilers for A7x (Adreno 740, compiler E031.41) crashes when - // building FA kernels with mixed or quant types (f32_f16, f32_q8_0, f32_q4_0) - // Here we skip all A7x for these kernels to avoid crash - if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X && - (is_f32_f16 || is_f32_q8_0 || is_f32_q4_0)) { - return false; - } + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); - if (dk == 512) { - if (backend_ctx->gpu_family == INTEL) { - return false; - } - if (!is_f32_f16) { - return false; - } - if (q->ne[1] == 1) { - const char * decode_env = getenv("GGML_OPENCL_FA_DK512_DECODE"); - if ((decode_env && decode_env[0] == '0') || - backend_ctx->gpu_family != ADRENO || k->ne[2] <= 0 || - (q->ne[2] / k->ne[2] != 4 && q->ne[2] / k->ne[2] != 8) || q->ne[2] % k->ne[2] != 0 || - !ggml_opencl_ensure_fa_f32_f16_vec_512(backend_ctx)) { - return false; - } - } else { - // prefill, BM-tile in its own FA_PREFILL_ONLY program - if (!ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/false)) { - return false; - } - } - } - return true; + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/4, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, extra->sc, size_sc, k/16, m, true, true); + transpose_2d_as_32b(backend_ctx, extra->dm, extra->dm, size_dm, k/(int)blck, m, true, true); } - default: - return false; +#endif + + extra->size_qs = size_qs; + extra->size_sc = size_sc; + extra->size_dm = size_dm; + + tensor->extra = extra; + return; } -} -// Forward declaration - implementation appears later in the file. -static const char * ggml_backend_opencl_buffer_type_get_name(ggml_backend_buffer_type_t buffer_type); + if (tensor->type == GGML_TYPE_Q3_K) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); -static ggml_guid_t ggml_backend_opencl_guid() { - static ggml_guid guid = { 0xde, 0xe0, 0x70, 0xa2, 0x73, 0x4e, 0x4d, 0xbc, 0xb0, 0xc7, 0x4f, 0xd4, 0x6d, 0x4e, 0x90, 0xfe }; - return &guid; -} + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_q3_K * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_q3_K(); + extra->noshuffle = ggml_cl_q3_k_use_noshuffle(backend_ctx, tensor); -static ggml_backend_i ggml_backend_opencl_i = { - /* .get_name = */ ggml_backend_opencl_name, - /* .free = */ ggml_backend_opencl_free, - /* .set_tensor_async = */ NULL, /* ggml_backend_opencl_set_tensor_async */ - /* .get_tensor_async = */ NULL, /* ggml_backend_opencl_get_tensor_async */ - /* .set_tensor_2d_async = */ NULL, - /* .get_tensor_2d_async = */ NULL, - /* .cpy_tensor_async = */ NULL, /* ggml_backend_opencl_cpy_tensor_async */ - /* .synchronize = */ ggml_backend_opencl_synchronize, - /* .graph_plan_create = */ NULL, - /* .graph_plan_free = */ NULL, - /* .graph_plan_update = */ NULL, - /* .graph_plan_compute = */ NULL, - /* .graph_compute = */ ggml_backend_opencl_graph_compute, - /* .event_record = */ NULL, - /* .event_wait = */ NULL, - /* .graph_optimize = */ NULL, -}; + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; -ggml_backend_t ggml_backend_opencl_init(void) { - ggml_backend_dev_t dev = ggml_backend_reg_dev_get(ggml_backend_opencl_reg(), 0); - ggml_backend_opencl_context *backend_ctx = ggml_cl_init(dev); - backend_ctx->ref_count++; + const size_t size_qs = n_blk * (blck/4); + const size_t size_hm = n_blk * (blck/8); + const size_t size_sc = n_blk * 12; + const size_t size_d = n_blk * sizeof(ggml_fp16_t); + GGML_ASSERT(size_qs + size_hm + size_sc + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); - ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_opencl_guid(), - /* .iface = */ ggml_backend_opencl_i, - /* .device = */ dev, - /* .context = */ backend_ctx - }; + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); - return backend; -} + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + auto previous_origin = region.origin; -bool ggml_backend_is_opencl(ggml_backend_t backend) { - return backend && backend->iface.get_name == ggml_backend_opencl_name; -} + region.origin = align_to(previous_origin + size_qs, backend_ctx->alignment); + region.size = size_hm; + CL_CHECK((extra->hm = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + previous_origin = region.origin; -// -// buffer -// -struct ggml_backend_opencl_buffer_context { - // A buffer context can hold multiple cl_mem objects. This is for flattening - // quantized weights and should be used with GGML_OPENCL_SMALL_ALLOC where - // each tensor is allocated a separate buffer. When flattening is enabled - // with small allocation, each tensor is backed by two cl_mem objects (for - // quants and scales) packed into a backend_opencl_buffer. - ggml_backend_opencl_buffer_context(cl_mem buf) - : name("OpenCL") { - buffer.push_back(buf); - } + region.origin = align_to(previous_origin + size_hm, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + previous_origin = region.origin; - ~ggml_backend_opencl_buffer_context() { - for (cl_mem buf : buffer) { - CL_CHECK(clReleaseMemObject(buf)); - } - for (cl_mem im : img) { - CL_CHECK(clReleaseMemObject(im)); - } + region.origin = align_to(previous_origin + size_sc, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // Delete all extras to trigger their destructors - for (ggml_tensor_extra_cl * e : temp_tensor_extras) { - delete e; - } - for (ggml_tensor_extra_cl * e : temp_tensor_extras_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0) { - delete e; - } - for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1) { - delete e; - } - for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0) { - delete e; - } - for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1) { - delete e; - } - for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4) { - delete e; - } - for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0) { - delete e; - } - for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0) { - delete e; - } - for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl) { - delete e; - } - for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K) { - delete e; - } - for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K) { - delete e; - } - for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K_in_use) { - delete e; - } - for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K) { - delete e; - } - for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K_in_use) { - delete e; + cl_kernel kernel = extra->noshuffle ? backend_ctx->kernel_convert_block_q3_k_noshuffle + : backend_ctx->kernel_convert_block_q3_K; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->hm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb_arg)); + + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/4, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->hm, extra->hm, size_hm, k/8, m, true, true); + transpose_2d_as_32b(backend_ctx, extra->sc, extra->sc, size_sc, 3*k/(int)blck, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/(int)blck, m, true, true); } +#endif + + extra->size_qs = size_qs; + extra->size_hm = size_hm; + extra->size_sc = size_sc; + extra->size_d = size_d; + + tensor->extra = extra; + return; } - ggml_tensor_extra_cl * ggml_opencl_alloc_temp_tensor_extra() { - ggml_tensor_extra_cl * extra; - if (temp_tensor_extras.empty()) { - extra = new ggml_tensor_extra_cl(); - } else { - extra = temp_tensor_extras.back(); - temp_tensor_extras.pop_back(); - } + if (tensor->type == GGML_TYPE_IQ3_S) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); + + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq3_s * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq3_s(); + extra->noshuffle = ggml_cl_iq3_s_use_noshuffle(backend_ctx, tensor); + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; + + const size_t size_qs = n_blk * 64; + const size_t size_sg = n_blk * 32; + const size_t size_qh = n_blk * 8; + const size_t size_sc = n_blk * 4; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_sg + size_qh + size_sc + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); - temp_tensor_extras_in_use.push_back(extra); + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - extra->reset(); - return extra; - } + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_sg; + CL_CHECK((extra->sg = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl_q1_0 * ggml_opencl_alloc_temp_tensor_extra_q1_0() { - ggml_tensor_extra_cl_q1_0 * extra; - if (temp_tensor_extras_q1_0.empty()) { - extra = new ggml_tensor_extra_cl_q1_0(); - } else { - extra = temp_tensor_extras_q1_0.back(); - temp_tensor_extras_q1_0.pop_back(); - } + region.origin = align_to(region.origin + size_sg, backend_ctx->alignment); + region.size = size_qh; + CL_CHECK((extra->qh = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - temp_tensor_extras_q1_0_in_use.push_back(extra); + region.origin = align_to(region.origin + size_qh, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - extra->reset(); - return extra; - } + region.origin = align_to(region.origin + size_sc, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl_q4_0 * ggml_opencl_alloc_temp_tensor_extra_q4_0() { - ggml_tensor_extra_cl_q4_0 * extra; - if (temp_tensor_extras_q4_0.empty()) { - extra = new ggml_tensor_extra_cl_q4_0(); - } else { - extra = temp_tensor_extras_q4_0.back(); - temp_tensor_extras_q4_0.pop_back(); - } + cl_kernel kernel = backend_ctx->kernel_convert_block_iq3_s; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sg)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->qh)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb_arg)); - temp_tensor_extras_q4_0_in_use.push_back(extra); + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; - extra->reset(); - return extra; - } + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); - ggml_tensor_extra_cl_q4_1 * ggml_opencl_alloc_temp_tensor_extra_q4_1() { - ggml_tensor_extra_cl_q4_1 * extra; - if (temp_tensor_extras_q4_1.empty()) { - extra = new ggml_tensor_extra_cl_q4_1(); - } else { - extra = temp_tensor_extras_q4_1.back(); - temp_tensor_extras_q4_1.pop_back(); +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/4, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sg, extra->sg, size_sg, k/8, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, extra->qh, size_qh, k/32, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, extra->sc, size_sc, k/64, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/256, m, true, true); } +#endif - temp_tensor_extras_q4_1_in_use.push_back(extra); + extra->size_qs = size_qs; + extra->size_sg = size_sg; + extra->size_qh = size_qh; + extra->size_sc = size_sc; + extra->size_d = size_d; - extra->reset(); - return extra; + tensor->extra = extra; + return; } - ggml_tensor_extra_cl_q5_0 * ggml_opencl_alloc_temp_tensor_extra_q5_0() { - ggml_tensor_extra_cl_q5_0 * extra; - if (temp_tensor_extras_q5_0.empty()) { - extra = new ggml_tensor_extra_cl_q5_0(); - } else { - extra = temp_tensor_extras_q5_0.back(); - temp_tensor_extras_q5_0.pop_back(); - } + if (tensor->type == GGML_TYPE_IQ3_XXS) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); - temp_tensor_extras_q5_0_in_use.push_back(extra); + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq3_xxs * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq3_xxs(); + extra->noshuffle = ggml_cl_iq3_xxs_use_noshuffle(backend_ctx, tensor); - extra->reset(); - return extra; - } + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; - ggml_tensor_extra_cl_q5_1 * ggml_opencl_alloc_temp_tensor_extra_q5_1() { - ggml_tensor_extra_cl_q5_1 * extra; - if (temp_tensor_extras_q5_1.empty()) { - extra = new ggml_tensor_extra_cl_q5_1(); - } else { - extra = temp_tensor_extras_q5_1.back(); - temp_tensor_extras_q5_1.pop_back(); - } + const size_t size_qs = n_blk * 64; + const size_t size_sas = n_blk * 32; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_sas + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); - temp_tensor_extras_q5_1_in_use.push_back(extra); + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); - extra->reset(); - return extra; - } + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl_mxfp4 * ggml_opencl_alloc_temp_tensor_extra_mxfp4() { - ggml_tensor_extra_cl_mxfp4 * extra; - if (temp_tensor_extras_mxfp4.empty()) { - extra = new ggml_tensor_extra_cl_mxfp4(); - } else { - extra = temp_tensor_extras_mxfp4.back(); - temp_tensor_extras_mxfp4.pop_back(); - } + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_sas; + CL_CHECK((extra->sas = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - temp_tensor_extras_mxfp4_in_use.push_back(extra); + region.origin = align_to(region.origin + size_sas, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - extra->reset(); - return extra; - } + cl_kernel kernel = backend_ctx->kernel_convert_block_iq3_xxs; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sas)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); - ggml_tensor_extra_cl_q8_0 * ggml_opencl_alloc_temp_tensor_extra_q8_0() { - ggml_tensor_extra_cl_q8_0 * extra; - if (temp_tensor_extras_q8_0.empty()) { - extra = new ggml_tensor_extra_cl_q8_0(); - } else { - extra = temp_tensor_extras_q8_0.back(); - temp_tensor_extras_q8_0.pop_back(); + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/4, m, true, true); + transpose_2d_as_32b(backend_ctx, extra->sas, extra->sas, size_sas, k/32, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/256, m, true, true); } +#endif - temp_tensor_extras_q8_0_in_use.push_back(extra); + extra->size_qs = size_qs; + extra->size_sas = size_sas; + extra->size_d = size_d; - extra->reset(); - return extra; + tensor->extra = extra; + return; } - ggml_tensor_extra_cl_iq4_nl * ggml_opencl_alloc_temp_tensor_extra_iq4_nl() { - ggml_tensor_extra_cl_iq4_nl * extra; - if (temp_tensor_extras_iq4_nl.empty()) { - extra = new ggml_tensor_extra_cl_iq4_nl(); - } else { - extra = temp_tensor_extras_iq4_nl.back(); - temp_tensor_extras_iq4_nl.pop_back(); - } + if (tensor->type == GGML_TYPE_IQ1_M) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); - temp_tensor_extras_iq4_nl_in_use.push_back(extra); + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq1_m * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq1_m(); + extra->noshuffle = ggml_cl_iq1_m_use_noshuffle(backend_ctx, tensor); - extra->reset(); - return extra; - } + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; - ggml_tensor_extra_cl_q4_K * ggml_opencl_alloc_temp_tensor_extra_q4_K() { - ggml_tensor_extra_cl_q4_K * extra; - if (temp_tensor_extras_q4_K.empty()) { - extra = new ggml_tensor_extra_cl_q4_K(); - } else { - extra = temp_tensor_extras_q4_K.back(); - temp_tensor_extras_q4_K.pop_back(); - } + const size_t size_qs = n_blk * 32; + const size_t size_qh = n_blk * 16; + const size_t size_sc = n_blk * 8; + GGML_ASSERT(size_qs + size_qh + size_sc == ggml_nbytes(tensor) && "Incorrect tensor size"); - temp_tensor_extras_q4_K_in_use.push_back(extra); + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); - extra->reset(); - return extra; - } + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl_q5_K * ggml_opencl_alloc_temp_tensor_extra_q5_K() { - ggml_tensor_extra_cl_q5_K * extra; - if (temp_tensor_extras_q5_K.empty()) { - extra = new ggml_tensor_extra_cl_q5_K(); - } else { - extra = temp_tensor_extras_q5_K.back(); - temp_tensor_extras_q5_K.pop_back(); - } + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_qh; + CL_CHECK((extra->qh = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - temp_tensor_extras_q5_K_in_use.push_back(extra); + region.origin = align_to(region.origin + size_qh, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - extra->reset(); - return extra; - } + cl_kernel kernel = backend_ctx->kernel_convert_block_iq1_m; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); - ggml_tensor_extra_cl_q6_K * ggml_opencl_alloc_temp_tensor_extra_q6_K() { - ggml_tensor_extra_cl_q6_K * extra; - if (temp_tensor_extras_q6_K.empty()) { - extra = new ggml_tensor_extra_cl_q6_K(); - } else { - extra = temp_tensor_extras_q6_K.back(); - temp_tensor_extras_q6_K.pop_back(); + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/8, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, extra->qh, size_qh, k/16, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->sc, extra->sc, size_sc, k/64, m, true, true); } +#endif - temp_tensor_extras_q6_K_in_use.push_back(extra); + extra->size_qs = size_qs; + extra->size_qh = size_qh; + extra->size_sc = size_sc; - extra->reset(); - return extra; + tensor->extra = extra; + return; } - void reset() { - for (ggml_tensor_extra_cl * e : temp_tensor_extras_in_use) { - temp_tensor_extras.push_back(e); - } - temp_tensor_extras_in_use.clear(); + if (tensor->type == GGML_TYPE_IQ1_S) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); - for (ggml_tensor_extra_cl_q1_0 * e : temp_tensor_extras_q1_0_in_use) { - temp_tensor_extras_q1_0.push_back(e); - } - temp_tensor_extras_q1_0_in_use.clear(); + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq1_s * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq1_s(); + extra->noshuffle = ggml_cl_iq1_s_use_noshuffle(backend_ctx, tensor); - for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0_in_use) { - temp_tensor_extras_q4_0.push_back(e); - } - temp_tensor_extras_q4_0_in_use.clear(); + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; - for (ggml_tensor_extra_cl_q4_1 * e : temp_tensor_extras_q4_1_in_use) { - temp_tensor_extras_q4_1.push_back(e); - } - temp_tensor_extras_q4_1_in_use.clear(); + const size_t size_qs = n_blk * 32; + const size_t size_qh = n_blk * 16; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_qh + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); - for (ggml_tensor_extra_cl_q5_0 * e : temp_tensor_extras_q5_0_in_use) { - temp_tensor_extras_q5_0.push_back(e); - } - temp_tensor_extras_q5_0_in_use.clear(); + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); - for (ggml_tensor_extra_cl_q5_1 * e : temp_tensor_extras_q5_1_in_use) { - temp_tensor_extras_q5_1.push_back(e); - } - temp_tensor_extras_q5_1_in_use.clear(); + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { - temp_tensor_extras_mxfp4.push_back(e); - } - temp_tensor_extras_mxfp4_in_use.clear(); + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_qh; + CL_CHECK((extra->qh = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { - temp_tensor_extras_q8_0.push_back(e); - } - temp_tensor_extras_q8_0_in_use.clear(); + region.origin = align_to(region.origin + size_qh, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - for (ggml_tensor_extra_cl_iq4_nl * e : temp_tensor_extras_iq4_nl_in_use) { - temp_tensor_extras_iq4_nl.push_back(e); - } - temp_tensor_extras_iq4_nl_in_use.clear(); + cl_kernel kernel = backend_ctx->kernel_convert_block_iq1_s; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); - for (ggml_tensor_extra_cl_q4_K * e : temp_tensor_extras_q4_K_in_use) { - temp_tensor_extras_q4_K.push_back(e); - } - temp_tensor_extras_q4_K_in_use.clear(); + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; - for (ggml_tensor_extra_cl_q5_K * e : temp_tensor_extras_q5_K_in_use) { - temp_tensor_extras_q5_K.push_back(e); - } - temp_tensor_extras_q5_K_in_use.clear(); + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); - for (ggml_tensor_extra_cl_q6_K * e : temp_tensor_extras_q6_K_in_use) { - temp_tensor_extras_q6_K.push_back(e); +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/8, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->qh, extra->qh, size_qh, k/32, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/(int)blck, m, true, true); } - temp_tensor_extras_q6_K_in_use.clear(); +#endif - q8_0_soa_tensors.clear(); - q4_0_soa_tensors.clear(); + extra->size_qs = size_qs; + extra->size_qh = size_qh; + extra->size_d = size_d; + + tensor->extra = extra; + return; } - // Pools for extras. Available extras are in `temp_tensor_extras`. Extras - // being used are in `temp_tensor_extras_in_use`. At the first run, new - // extras get created and put in `in_use`. When the buffer is reset via - // the `reset` callback, all extras in `in_use` get moved to available extras - // for reuse. - std::vector temp_tensor_extras; - std::vector temp_tensor_extras_in_use; - std::vector temp_tensor_extras_q1_0; - std::vector temp_tensor_extras_q1_0_in_use; - std::vector temp_tensor_extras_q4_0; - std::vector temp_tensor_extras_q4_0_in_use; - std::vector temp_tensor_extras_q4_1; - std::vector temp_tensor_extras_q4_1_in_use; - std::vector temp_tensor_extras_q5_0; - std::vector temp_tensor_extras_q5_0_in_use; - std::vector temp_tensor_extras_q5_1; - std::vector temp_tensor_extras_q5_1_in_use; - std::vector temp_tensor_extras_mxfp4; - std::vector temp_tensor_extras_mxfp4_in_use; - std::vector temp_tensor_extras_q8_0; - std::vector temp_tensor_extras_q8_0_in_use; - std::vector temp_tensor_extras_iq4_nl; - std::vector temp_tensor_extras_iq4_nl_in_use; - std::vector temp_tensor_extras_q4_K; - std::vector temp_tensor_extras_q4_K_in_use; - std::vector temp_tensor_extras_q5_K; - std::vector temp_tensor_extras_q5_K_in_use; - std::vector temp_tensor_extras_q6_K; - std::vector temp_tensor_extras_q6_K_in_use; + if (tensor->type == GGML_TYPE_IQ2_S) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); - // q8_0 tensors with AoS->SoA layout conversion installed by set_tensor. - // Two types of tensors get SOA'ed - normal weights and MoE weights. - // In Q8_0's case, we only have normal weights. If we ever have Q8_0 as MoE - // weights, they need to be added to this set in `set_tensors`. - std::unordered_set q8_0_soa_tensors; + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq2_s * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq2_s(); + extra->noshuffle = ggml_cl_iq2_s_use_noshuffle(backend_ctx, tensor); - // Same for q4_0. KV-cache q4_0 tensors are allocated but never pass - // through set_tensor, so they stay AoS and aren't in this set. - // In Q4_0's case, in addition to normal weights, we have MoE weights. - std::unordered_set q4_0_soa_tensors; + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; - // The buffer_context is initially created by ggml_backend_buft_alloc_buffer - // before any tensor is initialized (at the beginning of alloc_tensor_range). - // Hence, there is always a buffer object in this vector. When each tensor is - // being initialized, this original buffer object will be released if both - // flattening and small allocation are enabled, and additional buffer - // objects will be created in init_tensor to represent flattened quantized - // weights. - std::vector buffer; - // These are image1d_buffer_t objects that wrap around the quants and scales. - // For Q4_0 quantization, there should be two of them - one for quants and - // one for scales. They should be populated only when flattening and small - // allocation are enabled. - std::vector img; - std::string name; -}; + const size_t size_qs = n_blk * 32; + const size_t size_sg = n_blk * 32; + const size_t size_qh = n_blk * 8; + const size_t size_sc = n_blk * 8; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_sg + size_qh + size_sc + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); -static void ggml_backend_opencl_buffer_free_buffer(ggml_backend_buffer_t buffer) { - ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; - delete ctx; -} + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); -static void * ggml_backend_opencl_buffer_get_base(ggml_backend_buffer_t buffer) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; - return (void *) (uintptr_t) dev_ctx->backend_ctx->alignment; -} + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); -static enum ggml_status ggml_backend_opencl_buffer_init_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor) { - ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_sg; + CL_CHECK((extra->sg = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - if (tensor->view_src != nullptr) { - GGML_ASSERT(tensor->view_src->buffer->buft == buffer->buft); + region.origin = align_to(region.origin + size_sg, backend_ctx->alignment); + region.size = size_qh; + CL_CHECK((extra->qh = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl * view_extra = (ggml_tensor_extra_cl *) tensor->view_src->extra; - GGML_ASSERT(view_extra && "view_extra is nullptr?"); + region.origin = align_to(region.origin + size_qh, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // Reuse extra of the parent tensor. The offset of this view tensor - // becomes `extra->offset + view_offs` and needs to be calculated when - // it is used. This changes is needed because of the change to - // ggml_alloc.c in https://github.com/ggml-org/llama.cpp/pull/7640. - // `buffer` passed in here will always be `tensor->buffer`. It is OK - // to allocate extras from the same buffer context for ordinary - // intermediate tensors. But for views into kv cache tensors, doing so - // would mess up the extras used by kv cache. - // Before #7640, `buffer` is for intermediate tensors, which is always - // different from that of kv cache tensors. - // - // NB: now extra->offset no longer accounts for view_offs. - // NB: this should not apply to weight tensors (for end-to-end runs, but - // may apply for test-backend-ops). - // FIXME: if any unexpected results are seen, double check the offset - - // there could be other places that need fix. - tensor->extra = view_extra; - } else { - { - size_t offset = (char *) tensor->data - (char *) ggml_backend_opencl_buffer_get_base(buffer); + region.origin = align_to(region.origin + size_sc, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_tensor_extra_cl * extra = ctx->ggml_opencl_alloc_temp_tensor_extra(); - extra->offset = offset; - extra->data_device = ctx->buffer[0]; - extra->actual_size = ggml_nbytes(tensor); + cl_kernel kernel = backend_ctx->kernel_convert_block_iq2_s; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sg)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->qh)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb_arg)); - tensor->extra = extra; - } - } - return GGML_STATUS_SUCCESS; -} + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; -// Allocate a temporary upload buffer of `nbytes` and populate it with `data` -// from host. On Adreno X1-85 the device-only pool intermittently fails to -// allocate at hundreds of MB once model weights fragment the heap (observed -// on Qwen3.5-9B output.weight Q6_K at 834 MB). Three-step retry: -// 1. CL_MEM_READ_WRITE alloc + clEnqueueWriteBuffer (normal fast path). -// 2. clFinish + retry (drains in-flight allocs that may be holding heap; -// mirrors the proven pattern at the FD-split partial buffer alloc). -// 3. CL_MEM_ALLOC_HOST_PTR + map(WRITE_INVALIDATE) + memcpy + unmap — -// different memory pool (host-pinned); true zero-copy on Adreno per -// QCOM guidance. (CL_MEM_USE_HOST_PTR is NOT zero-copy on Adreno: the -// driver triggers an internal copy because arbitrary host pages aren't -// guaranteed mappable/coherent, AND it draws from the same exhausted -// device pool — so it doesn't solve the problem.) -// Returns the ready-to-read buffer (caller must clReleaseMemObject) or NULL -// if all three strategies fail. The buffer is opaque to the caller — it can -// be passed as a kernel argument like any normal cl_mem. -static cl_mem ggml_cl_create_temp_upload_buffer( - cl_context context, cl_command_queue queue, - size_t nbytes, const void * data, - const char * tensor_name_for_log) -{ - cl_int err; - cl_mem buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); - if (err != CL_SUCCESS) { - clFinish(queue); - buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); - } - if (err == CL_SUCCESS) { - const cl_int werr = clEnqueueWriteBuffer(queue, buf, CL_TRUE, 0, nbytes, data, 0, NULL, NULL); - if (werr == CL_SUCCESS) { - return buf; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/8, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sg, extra->sg, size_sg, k/8, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, extra->qh, size_qh, k/32, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, extra->sc, size_sc, k/32, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/(int)blck, m, true, true); } - clReleaseMemObject(buf); - } - buf = clCreateBuffer(context, - CL_MEM_READ_ONLY | CL_MEM_ALLOC_HOST_PTR | CL_MEM_HOST_WRITE_ONLY, - nbytes, NULL, &err); - if (err != CL_SUCCESS) { - return NULL; - } - void * mapped = clEnqueueMapBuffer(queue, buf, CL_TRUE, - CL_MAP_WRITE_INVALIDATE_REGION, 0, nbytes, 0, NULL, NULL, &err); - if (err != CL_SUCCESS) { - clReleaseMemObject(buf); - return NULL; - } - memcpy(mapped, data, nbytes); - const cl_int uerr = clEnqueueUnmapMemObject(queue, buf, mapped, 0, NULL, NULL); - if (uerr != CL_SUCCESS) { - clReleaseMemObject(buf); - return NULL; - } - if (tensor_name_for_log) { - GGML_LOG_INFO("ggml_opencl: %s (%.1f MiB) — device alloc failed, using CL_MEM_ALLOC_HOST_PTR fallback\n", - tensor_name_for_log, nbytes / 1024.0 / 1024.0); - } - return buf; -} +#endif -// Allocate a temporary download buffer of `nbytes`. The caller runs a kernel -// that writes into it, then reads it back to host via clEnqueueReadBuffer (or -// equivalent). Mirrors ggml_cl_create_temp_upload_buffer; the host-pinned -// fallback flags are flipped (CL_MEM_WRITE_ONLY | HOST_READ_ONLY) and the -// helper doesn't populate the buffer. -static cl_mem ggml_cl_create_temp_download_buffer( - cl_context context, cl_command_queue queue, - size_t nbytes, const char * tensor_name_for_log) -{ - cl_int err; - cl_mem buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); - if (err != CL_SUCCESS) { - clFinish(queue); - buf = clCreateBuffer(context, CL_MEM_READ_WRITE, nbytes, NULL, &err); - } - if (err == CL_SUCCESS) { - return buf; - } - buf = clCreateBuffer(context, - CL_MEM_WRITE_ONLY | CL_MEM_ALLOC_HOST_PTR | CL_MEM_HOST_READ_ONLY, - nbytes, NULL, &err); - if (err != CL_SUCCESS) { - return NULL; + extra->size_qs = size_qs; + extra->size_sg = size_sg; + extra->size_qh = size_qh; + extra->size_sc = size_sc; + extra->size_d = size_d; + + tensor->extra = extra; + return; } - if (tensor_name_for_log) { - GGML_LOG_INFO("ggml_opencl: %s download (%.1f MiB) — device alloc failed, using CL_MEM_ALLOC_HOST_PTR fallback\n", - tensor_name_for_log, nbytes / 1024.0 / 1024.0); + + if (tensor->type == GGML_TYPE_IQ2_XS) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); + + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq2_xs * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq2_xs(); + extra->noshuffle = ggml_cl_iq2_xs_use_noshuffle(backend_ctx, tensor); + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; + + const size_t size_qs = n_blk * 64; + const size_t size_sc = n_blk * 8; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_sc + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_sc; + CL_CHECK((extra->sc = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + region.origin = align_to(region.origin + size_sc, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_kernel kernel = backend_ctx->kernel_convert_block_iq2_xs; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_16b(backend_ctx, extra->qs, extra->qs, size_qs, k/8, m, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, extra->sc, size_sc, k/32, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/(int)blck, m, true, true); + } +#endif + + extra->size_qs = size_qs; + extra->size_sc = size_sc; + extra->size_d = size_d; + + tensor->extra = extra; + return; } - return buf; -} -static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; - ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx; + if (tensor->type == GGML_TYPE_IQ2_XXS) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); - cl_context context = backend_ctx->context; - cl_command_queue queue = backend_ctx->queue; + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_iq2_xxs * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_iq2_xxs(); + extra->noshuffle = ggml_cl_iq2_xxs_use_noshuffle(backend_ctx, tensor); + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; + + const size_t size_qs = n_blk * 32; + const size_t size_sas = n_blk * 32; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_sas + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_sas; + CL_CHECK((extra->sas = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + region.origin = align_to(region.origin + size_sas, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_kernel kernel = backend_ctx->kernel_convert_block_iq2_xxs; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->sas)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/8, m, true, true); + transpose_2d_as_32b(backend_ctx, extra->sas, extra->sas, size_sas, k/32, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/(int)blck, m, true, true); + } +#endif + + extra->size_qs = size_qs; + extra->size_sas = size_sas; + extra->size_d = size_d; + + tensor->extra = extra; + return; + } -#ifdef GGML_OPENCL_SOA_Q if (tensor->type == GGML_TYPE_Q1_0) { ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; GGML_ASSERT(extra_orig && "Tesnors in OpenCL backend should have been allocated and initialized"); @@ -10188,6 +13624,72 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, return; } + + if (tensor->type == GGML_TYPE_Q2_0) { + GGML_ASSERT(offset == 0 && size == ggml_nbytes(tensor)); + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tensors in OpenCL backend should have been allocated and initialized"); + + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_q2_0 * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_q2_0(); + extra->noshuffle = ggml_cl_q2_0_use_noshuffle(backend_ctx, tensor); + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + const size_t n_blk = ggml_nelements(tensor) / blck; + + const size_t size_qs = n_blk * 16; + const size_t size_d = n_blk * 2; + GGML_ASSERT(size_qs + size_d == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + cl_buffer_region region; + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_qs; + CL_CHECK((extra->qs = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + region.origin = align_to(region.origin + size_qs, backend_ctx->alignment); + region.size = size_d; + CL_CHECK((extra->d = clCreateSubBuffer(extra_orig->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_kernel kernel = backend_ctx->kernel_convert_block_q2_0; + cl_ulong nb_arg = (cl_ulong)n_blk; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->qs)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &nb_arg)); + + size_t global_work_size[] = { (size_t)CEIL_DIV(n_blk, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clReleaseMemObject(data_device)); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (extra->noshuffle) { + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, extra->qs, size_qs, k/4, m, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, k/64, m, true, true); + } +#endif + + extra->size_qs = size_qs; + extra->size_d = size_d; + + tensor->extra = extra; + return; + } + // We separate the quantized bits and scale from block_q4_0 by using an // additional kernel, where each thread handles a block. We first read the // original weights into a temporary buffer, then create two separate @@ -10195,7 +13697,16 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, // conversion kernel. if (tensor->type == GGML_TYPE_Q4_0) { // Views can't SoA-ify here — parent owns the layout (see q8_0 guard). + // A view of an AoS tensor (the KV cache, written by a state restore) + // is written in place. if (tensor->view_src != nullptr || !ggml_is_contiguous(tensor)) { + if (!ggml_cl_is_q4_0_soa(tensor)) { + ggml_tensor_extra_cl * extra_aos = (ggml_tensor_extra_cl *) tensor->extra; + CL_CHECK(clEnqueueWriteBuffer( + queue, extra_aos->data_device, CL_TRUE, + extra_aos->offset + tensor->view_offs + offset, + size, data, 0, NULL, NULL)); + } return; } // Tensors should have been preallocated, therefore they should @@ -10899,7 +14410,16 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, } if (tensor->type == GGML_TYPE_Q8_0) { // Views share the parent's buffer; parent owns SoA conversion. + // A view of an AoS tensor (the KV cache, written by a state restore) + // is written in place. if (tensor->view_src != nullptr || !ggml_is_contiguous(tensor)) { + if (!ggml_cl_is_q8_0_soa(tensor)) { + ggml_tensor_extra_cl * extra_aos = (ggml_tensor_extra_cl *) tensor->extra; + CL_CHECK(clEnqueueWriteBuffer( + queue, extra_aos->data_device, CL_TRUE, + extra_aos->offset + tensor->view_offs + offset, + size, data, 0, NULL, NULL)); + } return; } @@ -11720,68 +15240,530 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer, transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, K/256, M); } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + return; + } +#endif // GGML_OPENCL_SOA_Q + + // convert bf16 to f16 and store as f16 in device buffer + if (tensor->type == GGML_TYPE_BF16) { + GGML_ASSERT(offset % sizeof(ggml_fp16_t) == 0 && size % sizeof(ggml_fp16_t) == 0 + && "Offset and size must be multiples of 2 for bf16 tensors"); + + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra); + + cl_ulong n_elements = size / sizeof(ggml_fp16_t); + cl_ulong off_dst = (extra->offset + tensor->view_offs + offset) / sizeof(ggml_fp16_t); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, + size, const_cast(data), &err); + CL_CHECK(err); + + cl_kernel kernel = backend_ctx->kernel_convert_bf16_to_f16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->data_device)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &off_dst)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &n_elements)); + + size_t global_work_size[] = { (size_t)CEIL_DIV(n_elements, 64)*64, 1, 1 }; + size_t local_work_size[] = { 64, 1, 1 }; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseMemObject(data_device)); + CL_CHECK(clReleaseEvent(evt)); + + return; + } + + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra); + + // a view reuses its parent's extra, whose offset does not include view_offs + CL_CHECK(clEnqueueWriteBuffer( + queue, extra->data_device, CL_TRUE, extra->offset + tensor->view_offs + offset, + size, data, 0, NULL, NULL)); + + GGML_UNUSED(buffer); +} + +static void ggml_backend_opencl_buffer_get_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { + GGML_ASSERT(tensor->extra); + + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; + ggml_backend_opencl_context *backend_ctx = dev_ctx->backend_ctx; + + cl_context context = backend_ctx->context; + cl_command_queue queue = backend_ctx->queue; + + // Make sure all previously submitted commands in other devices are finished. + sync_with_other_backends(backend_ctx); + +#ifdef GGML_OPENCL_SOA_Q + if (tensor->type == GGML_TYPE_Q2_K) { + ggml_tensor_extra_cl_q2_K * extra = (ggml_tensor_extra_cl_q2_K *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, sc = extra->sc, dm = extra->dm; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sc, buf_dm; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + buf_sc.allocate(context, extra->size_sc); + buf_dm.allocate(context, extra->size_dm); + qs = buf_qs.buffer; + sc = buf_sc.buffer; + dm = buf_dm.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/4, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, sc, extra->size_sc, m, k/16, true, true); + transpose_2d_as_32b(backend_ctx, extra->dm, dm, extra->size_dm, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = extra->noshuffle ? backend_ctx->kernel_restore_block_q2_k_noshuffle + : backend_ctx->kernel_restore_block_q2_K; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_Q3_K) { + ggml_tensor_extra_cl_q3_K * extra = (ggml_tensor_extra_cl_q3_K *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, hm = extra->hm, sc = extra->sc, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_hm, buf_sc, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + buf_hm.allocate(context, extra->size_hm); + buf_sc.allocate(context, extra->size_sc); + buf_d.allocate(context, extra->size_d); + qs = buf_qs.buffer; + hm = buf_hm.buffer; + sc = buf_sc.buffer; + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/4, true, true); + transpose_2d_as_8b(backend_ctx, extra->hm, hm, extra->size_hm, m, k/8, true, true); + transpose_2d_as_32b(backend_ctx, extra->sc, sc, extra->size_sc, m, 3*k/(int)blck, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = extra->noshuffle ? backend_ctx->kernel_restore_block_q3_k_noshuffle + : backend_ctx->kernel_restore_block_q3_K; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &hm)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_IQ3_S) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq3_s * extra = (ggml_tensor_extra_cl_iq3_s *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, sg = extra->sg, qh = extra->qh, sc = extra->sc, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sg, buf_qh, buf_sc, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + buf_sg.allocate(context, extra->size_sg); + buf_qh.allocate(context, extra->size_qh); + buf_sc.allocate(context, extra->size_sc); + buf_d.allocate(context, extra->size_d); + + qs = buf_qs.buffer; + sg = buf_sg.buffer; + qh = buf_qh.buffer; + sc = buf_sc.buffer; + d = buf_d.buffer; + + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/4, true, true); + transpose_2d_as_8b(backend_ctx, extra->sg, sg, extra->size_sg, m, k/8, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, qh, extra->size_qh, m, k/32, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, sc, extra->size_sc, m, k/64, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/256, true, true); + } +#endif + + cl_kernel kernel = backend_ctx->kernel_restore_block_iq3_s; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_IQ3_XXS) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq3_xxs * extra = (ggml_tensor_extra_cl_iq3_xxs *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, sas = extra->sas, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sas, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + buf_sas.allocate(context, extra->size_sas); + buf_d.allocate(context, extra->size_d); + + qs = buf_qs.buffer; + sas = buf_sas.buffer; + d = buf_d.buffer; + + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/4, true, true); + transpose_2d_as_32b(backend_ctx, extra->sas, sas, extra->size_sas, m, k/32, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/256, true, true); + } +#endif + + cl_kernel kernel = backend_ctx->kernel_restore_block_iq3_xxs; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_IQ1_M) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq1_m * extra = (ggml_tensor_extra_cl_iq1_m *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, qh = extra->qh, sc = extra->sc; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_qh, buf_sc; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_qh.allocate(context, extra->size_qh); + qh = buf_qh.buffer; + buf_sc.allocate(context, extra->size_sc); + sc = buf_sc.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/8, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, qh, extra->size_qh, m, k/16, true, true); + transpose_2d_as_16b(backend_ctx, extra->sc, sc, extra->size_sc, m, k/64, true, true); + } +#endif + cl_kernel kernel = backend_ctx->kernel_restore_block_iq1_m; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_IQ1_S) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq1_s * extra = (ggml_tensor_extra_cl_iq1_s *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, qh = extra->qh, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_qh, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_qh.allocate(context, extra->size_qh); + qh = buf_qh.buffer; + buf_d.allocate(context, extra->size_d); + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/8, true, true); + transpose_2d_as_16b(backend_ctx, extra->qh, qh, extra->size_qh, m, k/32, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = backend_ctx->kernel_restore_block_iq1_s; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + + if (tensor->type == GGML_TYPE_IQ2_S) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq2_s * extra = (ggml_tensor_extra_cl_iq2_s *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, sg = extra->sg, qh = extra->qh, sc = extra->sc, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sg, buf_qh, buf_sc, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_sg.allocate(context, extra->size_sg); + sg = buf_sg.buffer; + buf_qh.allocate(context, extra->size_qh); + qh = buf_qh.buffer; + buf_sc.allocate(context, extra->size_sc); + sc = buf_sc.buffer; + buf_d.allocate(context, extra->size_d); + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/8, true, true); + transpose_2d_as_8b(backend_ctx, extra->sg, sg, extra->size_sg, m, k/8, true, true); + transpose_2d_as_8b(backend_ctx, extra->qh, qh, extra->size_qh, m, k/32, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, sc, extra->size_sc, m, k/32, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = backend_ctx->kernel_restore_block_iq2_s; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); return; } -#endif // GGML_OPENCL_SOA_Q - - // convert bf16 to f16 and store as f16 in device buffer - if (tensor->type == GGML_TYPE_BF16) { - GGML_ASSERT(offset % sizeof(ggml_fp16_t) == 0 && size % sizeof(ggml_fp16_t) == 0 - && "Offset and size must be multiples of 2 for bf16 tensors"); - - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra); - cl_ulong n_elements = size / sizeof(ggml_fp16_t); - cl_ulong off_dst = (extra->offset + offset) / sizeof(ggml_fp16_t); + if (tensor->type == GGML_TYPE_IQ2_XS) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq2_xs * extra = (ggml_tensor_extra_cl_iq2_xs *)tensor->extra; - cl_int err; - cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, - size, const_cast(data), &err); - CL_CHECK(err); + const size_t blck = (size_t)ggml_blck_size(tensor->type); - cl_kernel kernel = backend_ctx->kernel_convert_bf16_to_f16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->data_device)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &off_dst)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &n_elements)); + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); - size_t global_work_size[] = { (size_t)CEIL_DIV(n_elements, 64)*64, 1, 1 }; - size_t local_work_size[] = { 64, 1, 1 }; + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + cl_mem qs = extra->qs, sc = extra->sc, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sc, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_sc.allocate(context, extra->size_sc); + sc = buf_sc.buffer; + buf_d.allocate(context, extra->size_d); + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_16b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/8, true, true); + transpose_2d_as_8b(backend_ctx, extra->sc, sc, extra->size_sc, m, k/32, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = backend_ctx->kernel_restore_block_iq2_xs; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; cl_event evt; - CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); CL_CHECK(clWaitForEvents(1, &evt)); - CL_CHECK(clReleaseMemObject(data_device)); CL_CHECK(clReleaseEvent(evt)); - + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); return; } - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra); - - CL_CHECK(clEnqueueWriteBuffer( - queue, extra->data_device, CL_TRUE, extra->offset + offset, - size, data, 0, NULL, NULL)); - - GGML_UNUSED(buffer); -} + if (tensor->type == GGML_TYPE_IQ2_XXS) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_iq2_xxs * extra = (ggml_tensor_extra_cl_iq2_xxs *)tensor->extra; -static void ggml_backend_opencl_buffer_get_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { - GGML_ASSERT(tensor->extra); + const size_t blck = (size_t)ggml_blck_size(tensor->type); - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer->buft->device->context; - ggml_backend_opencl_context *backend_ctx = dev_ctx->backend_ctx; + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); - cl_context context = backend_ctx->context; - cl_command_queue queue = backend_ctx->queue; + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; - // Make sure all previously submitted commands in other devices are finished. - sync_with_other_backends(backend_ctx); + cl_mem qs = extra->qs, sas = extra->sas, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_sas, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_sas.allocate(context, extra->size_sas); + sas = buf_sas.buffer; + buf_d.allocate(context, extra->size_d); + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/8, true, true); + transpose_2d_as_32b(backend_ctx, extra->sas, sas, extra->size_sas, m, k/32, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/(int)blck, true, true); + } +#endif + cl_kernel kernel = backend_ctx->kernel_restore_block_iq2_xxs; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } -#ifdef GGML_OPENCL_SOA_Q if (tensor->type == GGML_TYPE_Q1_0) { ggml_tensor_extra_cl_q1_0 * extra = (ggml_tensor_extra_cl_q1_0 *)tensor->extra; @@ -11839,6 +15821,53 @@ static void ggml_backend_opencl_buffer_get_tensor(ggml_backend_buffer_t buffer, CL_CHECK(clReleaseMemObject(data_device)); return; } + + if (tensor->type == GGML_TYPE_Q2_0) { + if (tensor->view_src) { + offset += tensor->view_offs; + tensor = tensor->view_src; + } + ggml_tensor_extra_cl_q2_0 * extra = (ggml_tensor_extra_cl_q2_0 *)tensor->extra; + + const size_t blck = (size_t)ggml_blck_size(tensor->type); + + ggml_cl_buffer buf_unpacked; + buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor)); + + const size_t n_blk = (size_t)ggml_nelements(tensor) / blck; + cl_ulong nb_arg = (cl_ulong)n_blk; + + cl_mem qs = extra->qs, d = extra->d; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + ggml_cl_buffer buf_qs, buf_d; + if (extra->noshuffle) { + buf_qs.allocate(context, extra->size_qs); + qs = buf_qs.buffer; + buf_d.allocate(context, extra->size_d); + d = buf_d.buffer; + const int m = tensor->ne[1]; + const int k = tensor->ne[0]; + transpose_2d_as_8b(backend_ctx, extra->qs, qs, extra->size_qs, m, k/4, true, true); + transpose_2d_as_16b(backend_ctx, extra->d, d, extra->size_d, m, k/64, true, true); + } +#endif + + cl_kernel kernel = backend_ctx->kernel_restore_block_q2_0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &buf_unpacked.buffer)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &nb_arg)); + + size_t gws[] = { (n_blk + 63) / 64 * 64 }; + size_t lws[] = { 64 }; + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, gws, lws, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseEvent(evt)); + CL_CHECK(clEnqueueReadBuffer(queue, buf_unpacked.buffer, CL_TRUE, offset, size, data, 0, NULL, NULL)); + return; + } + // In end-to-end runs, get_tensor is usually used to get back the logits, // where we can simply do clEnqueueReadBuffer since they are f32. // However, in test-backend-ops, the GPU graph is copied to the CPU backend, @@ -12997,6 +17026,9 @@ static ggml_backend_buffer_i ggml_backend_opencl_buffer_interface = { /* .cpy_tensor = */ NULL, /* .clear = */ ggml_backend_opencl_buffer_clear, /* .reset = */ ggml_backend_opencl_buffer_reset, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; // @@ -13058,497 +17090,952 @@ static ggml_backend_buffer_t ggml_backend_opencl_buffer_type_alloc_buffer(ggml_b } } - if (err != CL_SUCCESS) { - GGML_LOG_ERROR("%s: failed to allocate %.2f MiB (err=%d). " - "Consider reducing -ngl, lowering -c / -ub, or using quantized KV cache.\n", - __func__, size / 1024.0 / 1024.0, err); - return nullptr; - } + if (err != CL_SUCCESS) { + GGML_LOG_ERROR("%s: failed to allocate %.2f MiB (err=%d). " + "Consider reducing -ngl, lowering -c / -ub, or using quantized KV cache.\n", + __func__, size / 1024.0 / 1024.0, err); + return nullptr; + } + + ggml_backend_opencl_buffer_context * ctx = new ggml_backend_opencl_buffer_context(mem); + + return ggml_backend_buffer_init(buffer_type, ggml_backend_opencl_buffer_interface, ctx, size); +} + +static size_t ggml_backend_opencl_buffer_type_get_alignment(ggml_backend_buffer_type_t buffer_type) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer_type->device->context; + return dev_ctx->backend_ctx->alignment; +} + +static size_t ggml_backend_opencl_buffer_type_get_max_size(ggml_backend_buffer_type_t buffer_type) { + static size_t max_size = -1; + if (max_size == (size_t)-1) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer_type->device->context; + max_size = dev_ctx->backend_ctx->max_alloc_size; + } + return max_size; +} + +static bool ggml_backend_opencl_buffer_type_supports_backend(ggml_backend_buffer_type_t buft, ggml_backend_t backend) { + return ggml_backend_is_opencl(backend); + + UNUSED(buft); +} + +static size_t ggml_backend_opencl_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { + size_t size = ggml_nbytes(tensor); +#ifdef GGML_OPENCL_SOA_Q + // set_tensor carves quantized weights into per-component subbuffers (d/q, + // ql/qh/s/d, ...) whose origins are each rounded up to the device base + // alignment. When a component's size is not a multiple of the alignment + // (e.g. q6_K [1536,49155]: size_s = 49155*96 leaves a 96-byte gap at 128-byte + // alignment), the aligned carve extends past ggml_nbytes and the last + // subbuffer would overlap the next tensor in the pool. Reserve the worst-case + // carve slack: at most 5 components (q5_K), i.e. 4 aligned gaps. + if (ggml_is_quantized(tensor->type)) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buft->device->context; + size += 4 * dev_ctx->backend_ctx->alignment; + } +#endif // GGML_OPENCL_SOA_Q + return size; +} + +static ggml_backend_buffer_type_i ggml_backend_opencl_buffer_type_interface = { + /* .get_name = */ ggml_backend_opencl_buffer_type_get_name, + /* .alloc_buffer = */ ggml_backend_opencl_buffer_type_alloc_buffer, + /* .alloc_buffer_n = */ NULL, + /* .get_alignment = */ ggml_backend_opencl_buffer_type_get_alignment, + /* .get_max_size = */ ggml_backend_opencl_buffer_type_get_max_size, + /* .get_alloc_size = */ ggml_backend_opencl_buffer_type_get_alloc_size, + /* .get_alloc_size_n = */ NULL, + /* .is_host = */ NULL, +}; + +// +// backend device +// + +static const char * ggml_backend_opencl_device_get_name(ggml_backend_dev_t dev) { + return "GPUOpenCL"; + + GGML_UNUSED(dev); +} + +static const char * ggml_backend_opencl_device_get_description(ggml_backend_dev_t dev) { + ggml_backend_opencl_device_context *dev_ctx = (ggml_backend_opencl_device_context *) dev->context; + return dev_ctx->device_name.c_str(); +} + +static void ggml_backend_opencl_device_get_memory(ggml_backend_dev_t dev, size_t * free, size_t * total) { + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; + + static const size_t opencl_extra_margin = 1024ull*1024ull*1024ull; + + // OpenCL does not provide reliable currently-free device memory. + // Use total/global memory as a best-effort upper bound. + // Improved safety: Reduce by a 1GiB extra margin for common --fit + *total = dev_ctx->global_mem_size; + *free = *total > opencl_extra_margin ? *total - opencl_extra_margin : 0; +} + +static enum ggml_backend_dev_type ggml_backend_opencl_device_get_type(ggml_backend_dev_t dev) { + return GGML_BACKEND_DEVICE_TYPE_GPU; + + GGML_UNUSED(dev); +} + +static void ggml_backend_opencl_device_get_props(ggml_backend_dev_t dev, struct ggml_backend_dev_props * props) { + props->name = ggml_backend_opencl_device_get_name(dev); + props->description = ggml_backend_opencl_device_get_description(dev); + props->type = ggml_backend_opencl_device_get_type(dev); + ggml_backend_opencl_device_get_memory(dev, &props->memory_free, &props->memory_total); + props->caps = ggml_backend_dev_caps { + /* .async = */ false, + /* .host_buffer = */ false, + /* .buffer_from_host_ptr = */ false, + /* .events = */ false, + /* .mmap_support = */ false, + }; +} + +static ggml_backend_t ggml_backend_opencl_device_init(ggml_backend_dev_t dev, const char * params) { + ggml_backend_opencl_context * backend_ctx = ggml_cl_init(dev); + // Getting a new reference to the backend, increase ref_count + backend_ctx->ref_count++; + + ggml_backend_t backend = new ggml_backend { + /* .guid = */ ggml_backend_opencl_guid(), + /* .interface = */ ggml_backend_opencl_i, + /* .device = */ dev, + /* .context = */ backend_ctx, + }; + + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; + ggml_opencl_print_backend_info(dev_ctx); + return backend; + + GGML_UNUSED(params); +} + +static ggml_backend_buffer_type_t ggml_backend_opencl_device_get_buffer_type(ggml_backend_dev_t dev) { + auto * dev_ctx = static_cast(dev->context); + + dev_ctx->buffer_type = ggml_backend_buffer_type{ + /* .iface = */ ggml_backend_opencl_buffer_type_interface, + /* .device = */ dev, + /* .context = */ nullptr, + }; + + return &dev_ctx->buffer_type; +} + +static ggml_backend_buffer_t ggml_backend_opencl_device_buffer_from_ptr(ggml_backend_dev_t dev, void * ptr, size_t size, size_t max_tensor_size) { + GGML_UNUSED(dev); + GGML_UNUSED(ptr); + GGML_UNUSED(size); + GGML_UNUSED(max_tensor_size); + return nullptr; +} + +static bool ggml_backend_opencl_device_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { + ggml_cl_init(dev); + return ggml_opencl_supports_op(dev, op); +} + +static bool ggml_backend_opencl_device_supports_buft(ggml_backend_dev_t dev, ggml_backend_buffer_type_t buft) { + // Check 'dev' and 'buffer_type' are not objects belonging to this backend. + if (dev->iface.get_name != ggml_backend_opencl_device_get_name || + buft->iface.get_name != ggml_backend_opencl_buffer_type_get_name) { + return false; + } + + // Check cl_context is the same. clEnqueue* commands may not use + // buffers from another cl_context. + ggml_backend_opencl_context * backend_ctx0 = ggml_cl_init(dev); + ggml_backend_opencl_context * backend_ctx1 = ggml_cl_init(buft->device); + return backend_ctx0->context == backend_ctx1->context; +} + +namespace /* anonymous */ { +struct ggml_backend_device_i ggml_backend_opencl_device_i = { + /* .get_name = */ ggml_backend_opencl_device_get_name, + /* .get_description = */ ggml_backend_opencl_device_get_description, + /* .get_memory = */ ggml_backend_opencl_device_get_memory, + /* .get_type = */ ggml_backend_opencl_device_get_type, + /* .get_props = */ ggml_backend_opencl_device_get_props, + /* .init_backend = */ ggml_backend_opencl_device_init, + /* .get_buffer_type = */ ggml_backend_opencl_device_get_buffer_type, + /* .get_host_buffer_type = */ NULL, + /* .buffer_from_host_ptr = */ ggml_backend_opencl_device_buffer_from_ptr, + /* .supports_op = */ ggml_backend_opencl_device_supports_op, + /* .supports_buft = */ ggml_backend_opencl_device_supports_buft, + /* .offload_op = */ NULL, + /* .event_new = */ NULL, + /* .event_free = */ NULL, + /* .event_synchronize = */ NULL, +}; +} + +// Backend registry - ggml_backend_opencl_buffer_context * ctx = new ggml_backend_opencl_buffer_context(mem); +static const char * ggml_backend_opencl_reg_get_name(ggml_backend_reg_t reg) { + return "OpenCL"; - return ggml_backend_buffer_init(buffer_type, ggml_backend_opencl_buffer_interface, ctx, size); + GGML_UNUSED(reg); } -static size_t ggml_backend_opencl_buffer_type_get_alignment(ggml_backend_buffer_type_t buffer_type) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer_type->device->context; - return dev_ctx->backend_ctx->alignment; -} +static size_t ggml_backend_opencl_reg_device_count(ggml_backend_reg_t reg) { + return g_ggml_backend_opencl_devices.size(); -static size_t ggml_backend_opencl_buffer_type_get_max_size(ggml_backend_buffer_type_t buffer_type) { - static size_t max_size = -1; - if (max_size == (size_t)-1) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buffer_type->device->context; - max_size = dev_ctx->backend_ctx->max_alloc_size; - } - return max_size; + GGML_UNUSED(reg); } -static bool ggml_backend_opencl_buffer_type_supports_backend(ggml_backend_buffer_type_t buft, ggml_backend_t backend) { - return ggml_backend_is_opencl(backend); +static ggml_backend_dev_t ggml_backend_opencl_reg_device_get(ggml_backend_reg_t reg, size_t index) { + GGML_ASSERT(index < ggml_backend_opencl_reg_device_count(reg)); - UNUSED(buft); -} + return &g_ggml_backend_opencl_devices[index]; -static size_t ggml_backend_opencl_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { - size_t size = ggml_nbytes(tensor); -#ifdef GGML_OPENCL_SOA_Q - // set_tensor carves quantized weights into per-component subbuffers (d/q, - // ql/qh/s/d, ...) whose origins are each rounded up to the device base - // alignment. When a component's size is not a multiple of the alignment - // (e.g. q6_K [1536,49155]: size_s = 49155*96 leaves a 96-byte gap at 128-byte - // alignment), the aligned carve extends past ggml_nbytes and the last - // subbuffer would overlap the next tensor in the pool. Reserve the worst-case - // carve slack: at most 5 components (q5_K), i.e. 4 aligned gaps. - if (ggml_is_quantized(tensor->type)) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) buft->device->context; - size += 4 * dev_ctx->backend_ctx->alignment; - } -#endif // GGML_OPENCL_SOA_Q - return size; + GGML_UNUSED(reg); + GGML_UNUSED(index); } -static ggml_backend_buffer_type_i ggml_backend_opencl_buffer_type_interface = { - /* .get_name = */ ggml_backend_opencl_buffer_type_get_name, - /* .alloc_buffer = */ ggml_backend_opencl_buffer_type_alloc_buffer, - /* .alloc_buffer_n = */ NULL, - /* .get_alignment = */ ggml_backend_opencl_buffer_type_get_alignment, - /* .get_max_size = */ ggml_backend_opencl_buffer_type_get_max_size, - /* .get_alloc_size = */ ggml_backend_opencl_buffer_type_get_alloc_size, - /* .get_alloc_size_n = */ NULL, - /* .is_host = */ NULL, +static struct ggml_backend_reg_i ggml_backend_opencl_reg_i = { + /* .get_name = */ ggml_backend_opencl_reg_get_name, + /* .device_count = */ ggml_backend_opencl_reg_device_count, + /* .device_get = */ ggml_backend_opencl_reg_device_get, + /* .get_proc_address = */ NULL, }; -// -// backend device -// +ggml_backend_reg_t ggml_backend_opencl_reg(void) { + static std::mutex mutex; + static ggml_backend_reg reg; + static bool initialized = false; + std::lock_guard lock(mutex); -static const char * ggml_backend_opencl_device_get_name(ggml_backend_dev_t dev) { - return "GPUOpenCL"; + if (initialized) { + return ® + } + initialized = true; - GGML_UNUSED(dev); -} + g_ggml_backend_opencl_devices = ggml_opencl_probe_devices(®); -static const char * ggml_backend_opencl_device_get_description(ggml_backend_dev_t dev) { - ggml_backend_opencl_device_context *dev_ctx = (ggml_backend_opencl_device_context *) dev->context; - return dev_ctx->device_name.c_str(); + reg = ggml_backend_reg{ + /* .api_version = */ GGML_BACKEND_API_VERSION, + /* .iface = */ ggml_backend_opencl_reg_i, + /* .context = */ NULL, + }; + + return ® } -static void ggml_backend_opencl_device_get_memory(ggml_backend_dev_t dev, size_t * free, size_t * total) { - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; +GGML_BACKEND_DL_IMPL(ggml_backend_opencl_reg) - static const size_t opencl_extra_margin = 1024ull*1024ull*1024ull; +//------------------------------------------------------------------------------ +// Debugging utils +//------------------------------------------------------------------------------ +#if 0 +#define QK4_0 32 +typedef struct { + ggml_fp16_t d; // delta + uint8_t qs[QK4_0 / 2]; // nibbles / quants +} block_q4_0; +static_assert(sizeof(block_q4_0) == sizeof(ggml_fp16_t) + QK4_0 / 2, + "wrong q4_0 block size/padding"); - // OpenCL does not provide reliable currently-free device memory. - // Use total/global memory as a best-effort upper bound. - // Improved safety: Reduce by a 1GiB extra margin for common --fit - *total = dev_ctx->global_mem_size; - *free = *total > opencl_extra_margin ? *total - opencl_extra_margin : 0; +#define QK_MXFP4 32 + +#include +#ifdef __cplusplus +#include "half.hpp" +#endif + +static void dump_tensor(ggml_backend_t backend, const struct ggml_tensor * tensor) { + void * buf = malloc(ggml_nbytes(tensor)); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + cl_command_queue queue = backend_ctx->queue; +#ifdef GGML_OPENCL_SOA_Q + void * buf_q; + void * buf_d; +#endif + + // Make sure everything is done. + CL_CHECK(clFinish(queue)); + +#ifdef GGML_OPENCL_SOA_Q + if (tensor->type == GGML_TYPE_Q4_0) { + ggml_tensor_extra_cl_q4_0 * extra = (ggml_tensor_extra_cl_q4_0 *) tensor->extra; + GGML_ASSERT(extra); + + size_t size_q = ggml_nelements(tensor)/QK4_0 * QK4_0/2; + size_t size_d = ggml_nelements(tensor)/QK4_0 * sizeof(ggml_fp16_t); + GGML_ASSERT(size_q + size_d == ggml_nbytes(tensor)); + buf_q = malloc(size_q); + buf_d = malloc(size_d); + + CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); + CL_CHECK(clEnqueueReadBuffer(queue, extra->d, CL_TRUE, 0, size_d, buf_d, 0, NULL, NULL)); + CL_CHECK(clFinish(queue)); + } else if (tensor->type == GGML_TYPE_MXFP4) { + ggml_tensor_extra_cl_mxfp4 * extra = (ggml_tensor_extra_cl_mxfp4 *) tensor->extra; + GGML_ASSERT(extra); + + size_t size_q = ggml_nelements(tensor)/QK_MXFP4 * QK_MXFP4/2; + size_t size_e = ggml_nelements(tensor)/QK_MXFP4 * sizeof(char); + GGML_ASSERT(size_q + size_e == ggml_nbytes(tensor)); + buf_q = malloc(size_q); + buf_d = malloc(size_e); + + CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); + CL_CHECK(clEnqueueReadBuffer(queue, extra->e, CL_TRUE, 0, size_e, buf_d, 0, NULL, NULL)); + CL_CHECK(clFinish(queue)); + } else { + // Read out the tensor from GPU memory. + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra); + + CL_CHECK(clEnqueueReadBuffer(queue, extra->data_device, CL_TRUE, + extra->offset, ggml_nbytes(tensor), buf, 0, NULL, NULL)); + CL_CHECK(clFinish(queue)); + } +#else + // Read out the tensor from GPU memory. + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra); + + CL_CHECK(clEnqueueReadBuffer(queue, extra->data_device, CL_TRUE, + extra->offset, ggml_nbytes(tensor), buf, 0, NULL, NULL)); + CL_CHECK(clFinish(queue)); +#endif // GGML_OPENCL_SOA_Q + + // Open file and dump. + char fname[512]; + snprintf(fname, sizeof(fname), "./tensor-dumps/%s.txt", tensor->name); + FILE * f = fopen(fname, "w"); + if (!f) { + printf("Failed to open %s\n", fname); + return; + } + + if (tensor->type == GGML_TYPE_F32) { + float * data = (float *) buf; + for (int i = 0; i < ggml_nelements(tensor); ++i) { + if (isnan(data[i])) { + printf("NaN found: %s\n", tensor->name); + break; + } + fprintf(f, "%f\n", data[i]); + } + } else if (tensor->type == GGML_TYPE_I32) { + int * data = (int *) buf; + for (int i = 0; i < ggml_nelements(tensor); ++i) { + if (isnan(data[i])) { + printf("NaN found: %s\n", tensor->name); + break; + } + fprintf(f, "%d\n", data[i]); + } + } else if (tensor->type == GGML_TYPE_F16) { +#ifdef __cplusplus + half_float::half * data = (half_float::half *) buf; + for (int i = 0; i < ggml_nelements(tensor); ++i) { + if (std::isnan(data[i])) { + printf("NaN found: %s\n", tensor->name); + break; + } + fprintf(f, "%f\n", float(data[i])); + } +#endif + } else if (tensor->type == GGML_TYPE_Q4_0) { +#ifdef GGML_OPENCL_SOA_Q + ggml_fp16_t * data_d = (ggml_fp16_t *)buf_d; + unsigned char * data_q = (unsigned char *)buf_q; + + for (int i = 0; i < ggml_nelements(tensor)/QK4_0; ++i) { + fprintf(f, "%04x, ", data_d[i]); + for (int k = 0; k < QK4_0/2; ++k) { + fprintf(f, "%02x, ", data_q[k]); + } + fprintf(f, "\n"); + data_q += QK4_0/2; + } + free(buf_d); + free(buf_q); +#else + block_q4_0 * data = (block_q4_0 *) buf; + for (int i = 0; i < ggml_nelements(tensor)/QK4_0; ++i) { + fprintf(f, "%04x, ", data[i].d); + for (int k = 0; k < QK4_0/2; ++k) { + fprintf(f, "%02x, ", data[i].qs[k]); + } + fprintf(f, "\n"); + } +#endif // GGML_OPENCL_SOA_Q + } + free(buf); + fflush(f); + fclose(f); } +#else +#define dump_tensor(tensor) +#endif + +//------------------------------------------------------------------------------ +// Ops +//------------------------------------------------------------------------------ -static enum ggml_backend_dev_type ggml_backend_opencl_device_get_type(ggml_backend_dev_t dev) { - return GGML_BACKEND_DEVICE_TYPE_GPU; +static bool ggml_cl_can_mul_mat(const struct ggml_tensor * src0, const struct ggml_tensor * src1, struct ggml_tensor * dst) { + const int64_t ne10 = src1->ne[0]; - GGML_UNUSED(dev); -} + const int64_t ne0 = dst->ne[0]; + const int64_t ne1 = dst->ne[1]; -static void ggml_backend_opencl_device_get_props(ggml_backend_dev_t dev, struct ggml_backend_dev_props * props) { - props->name = ggml_backend_opencl_device_get_name(dev); - props->description = ggml_backend_opencl_device_get_description(dev); - props->type = ggml_backend_opencl_device_get_type(dev); - ggml_backend_opencl_device_get_memory(dev, &props->memory_free, &props->memory_total); - props->caps = ggml_backend_dev_caps { - /* .async = */ false, - /* .host_buffer = */ false, - /* .buffer_from_host_ptr = */ false, - /* .events = */ false, - /* .mmap_support = */ false, - }; + // TODO: find the optimal values for these + return (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && + src1->type == GGML_TYPE_F32 && + dst->type == GGML_TYPE_F32 && + (ne0 >= 32 && ne1 >= 32 && ne10 >= 32); } -static ggml_backend_t ggml_backend_opencl_device_init(ggml_backend_dev_t dev, const char * params) { - ggml_backend_opencl_context * backend_ctx = ggml_cl_init(dev); - // Getting a new reference to the backend, increase ref_count - backend_ctx->ref_count++; +// Copy a noncontiguous tensor to contiguous tensor. ne[] remains the same but +// nb[] is recalculated such that tensor is contiguous. +static void ggml_cl_copy_to_contiguous(ggml_backend_t backend, const ggml_tensor * src, cl_mem dst, + cl_ulong &nb0, cl_ulong &nb1, cl_ulong &nb2, cl_ulong &nb3) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_opencl_guid(), - /* .interface = */ ggml_backend_opencl_i, - /* .device = */ dev, - /* .context = */ backend_ctx, - }; + const int tensor_type_size = ggml_type_size(src->type); - ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *) dev->context; - ggml_opencl_print_backend_info(dev_ctx); - return backend; + const int ne00 = src->ne[0]; + const int ne01 = src->ne[1]; + const int ne02 = src->ne[2]; + const int ne03 = src->ne[3]; - GGML_UNUSED(params); -} + const cl_ulong nb00 = src->nb[0]; + const cl_ulong nb01 = src->nb[1]; + const cl_ulong nb02 = src->nb[2]; + const cl_ulong nb03 = src->nb[3]; -static ggml_backend_buffer_type_t ggml_backend_opencl_device_get_buffer_type(ggml_backend_dev_t dev) { - auto * dev_ctx = static_cast(dev->context); + const int ne0 = src->ne[0]; + const int ne1 = src->ne[1]; + const int ne2 = src->ne[2]; + const int ne3 = src->ne[3]; - dev_ctx->buffer_type = ggml_backend_buffer_type{ - /* .iface = */ ggml_backend_opencl_buffer_type_interface, - /* .device = */ dev, - /* .context = */ nullptr, - }; + nb0 = tensor_type_size; + nb1 = tensor_type_size*ne00; + nb2 = tensor_type_size*ne00*ne01; + nb3 = tensor_type_size*ne00*ne01*ne02; - return &dev_ctx->buffer_type; -} + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *)src->extra; -static ggml_backend_buffer_t ggml_backend_opencl_device_buffer_from_ptr(ggml_backend_dev_t dev, void * ptr, size_t size, size_t max_tensor_size) { - GGML_UNUSED(dev); - GGML_UNUSED(ptr); - GGML_UNUSED(size); - GGML_UNUSED(max_tensor_size); - return nullptr; -} + cl_ulong offset0 = extra->offset + src->view_offs; + cl_ulong offsetd = 0; -static bool ggml_backend_opencl_device_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { - ggml_cl_init(dev); - return ggml_opencl_supports_op(dev, op); -} + cl_kernel kernel; -static bool ggml_backend_opencl_device_supports_buft(ggml_backend_dev_t dev, ggml_backend_buffer_type_t buft) { - // Check 'dev' and 'buffer_type' are not objects belonging to this backend. - if (dev->iface.get_name != ggml_backend_opencl_device_get_name || - buft->iface.get_name != ggml_backend_opencl_buffer_type_get_name) { - return false; + switch (src->type) { + case GGML_TYPE_F32: + kernel = backend_ctx->kernel_cpy_f32_f32; + break; + case GGML_TYPE_F16: + case GGML_TYPE_BF16: // stored as f16 on device + kernel = backend_ctx->kernel_cpy_f16_f16; + break; + default: + GGML_ASSERT(false && "not implemented"); } - // Check cl_context is the same. clEnqueue* commands may not use - // buffers from another cl_context. - ggml_backend_opencl_context * backend_ctx0 = ggml_cl_init(dev); - ggml_backend_opencl_context * backend_ctx1 = ggml_cl_init(buft->device); - return backend_ctx0->context == backend_ctx1->context; -} + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &dst)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb3)); -namespace /* anonymous */ { -struct ggml_backend_device_i ggml_backend_opencl_device_i = { - /* .get_name = */ ggml_backend_opencl_device_get_name, - /* .get_description = */ ggml_backend_opencl_device_get_description, - /* .get_memory = */ ggml_backend_opencl_device_get_memory, - /* .get_type = */ ggml_backend_opencl_device_get_type, - /* .get_props = */ ggml_backend_opencl_device_get_props, - /* .init_backend = */ ggml_backend_opencl_device_init, - /* .get_buffer_type = */ ggml_backend_opencl_device_get_buffer_type, - /* .get_host_buffer_type = */ NULL, - /* .buffer_from_host_ptr = */ ggml_backend_opencl_device_buffer_from_ptr, - /* .supports_op = */ ggml_backend_opencl_device_supports_op, - /* .supports_buft = */ ggml_backend_opencl_device_supports_buft, - /* .offload_op = */ NULL, - /* .event_new = */ NULL, - /* .event_free = */ NULL, - /* .event_synchronize = */ NULL, -}; -} + const int nth = MIN(64, ne00); -// Backend registry + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; -static const char * ggml_backend_opencl_reg_get_name(ggml_backend_reg_t reg) { - return "OpenCL"; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, src); +} - GGML_UNUSED(reg); +static void ggml_cl_nop(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + UNUSED(backend); + UNUSED(src0); + UNUSED(src1); + UNUSED(dst); } -static size_t ggml_backend_opencl_reg_device_count(ggml_backend_reg_t reg) { - return g_ggml_backend_opencl_devices.size(); +static void ggml_cl_get_rows(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - GGML_UNUSED(reg); -} + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + GGML_TENSOR_LOCALS(int, ne1, src1, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); + GGML_TENSOR_LOCALS(int, ne, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); -static ggml_backend_dev_t ggml_backend_opencl_reg_device_get(ggml_backend_reg_t reg, size_t index) { - GGML_ASSERT(index < ggml_backend_opencl_reg_device_count(reg)); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - return &g_ggml_backend_opencl_devices[index]; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - GGML_UNUSED(reg); - GGML_UNUSED(index); -} + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; -static struct ggml_backend_reg_i ggml_backend_opencl_reg_i = { - /* .get_name = */ ggml_backend_opencl_reg_get_name, - /* .device_count = */ ggml_backend_opencl_reg_device_count, - /* .device_get = */ ggml_backend_opencl_reg_device_get, - /* .get_proc_address = */ NULL, -}; + cl_kernel kernel; -ggml_backend_reg_t ggml_backend_opencl_reg(void) { - static std::mutex mutex; - static ggml_backend_reg reg; - static bool initialized = false; - std::lock_guard lock(mutex); + switch (src0->type) { + case GGML_TYPE_F32: + kernel = backend_ctx->kernel_get_rows_f32; + break; + case GGML_TYPE_I32: + kernel = backend_ctx->kernel_get_rows_i32; + break; + case GGML_TYPE_F16: + kernel = backend_ctx->kernel_get_rows_f16; + break; + case GGML_TYPE_Q4_0: + kernel = backend_ctx->kernel_get_rows_q4_0; + break; + default: + GGML_ASSERT(false && "not implemented"); + } - if (initialized) { - return ® + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb3)); + + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + int nth = 1; + while (nth < ne00 && 2*nth <= max_workgroup_size) { + nth *= 2; } - initialized = true; - g_ggml_backend_opencl_devices = ggml_opencl_probe_devices(®); + int nchunks = 1; + if (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_I32) { + const int chunk_target = nth * 4; + nchunks = (ne00 + chunk_target - 1) / chunk_target; + nchunks = MAX(1, MIN(nchunks, 64)); + } + + size_t global_work_size[] = {(size_t)ne10*nth*nchunks, (size_t)ne11, (size_t)ne12}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} - reg = ggml_backend_reg{ - /* .api_version = */ GGML_BACKEND_API_VERSION, - /* .iface = */ ggml_backend_opencl_reg_i, - /* .context = */ NULL, - }; +// check if a Q8_0 tensor has been SOA'ed in set_tensor +// we store SOA'ed tensors in a map in set_tensor, check against that map +static bool ggml_cl_is_q8_0_soa(const ggml_tensor * tensor) { + if (tensor == nullptr || tensor->type != GGML_TYPE_Q8_0 || tensor->buffer == nullptr) { + return false; + } + auto * ctx = (ggml_backend_opencl_buffer_context *) tensor->buffer->context; + if (ctx == nullptr) { + return false; + } + const ggml_tensor * key = tensor->view_src != nullptr ? tensor->view_src : tensor; + return ctx->q8_0_soa_tensors.count(key) > 0; +} - return ® +// check if a Q4_0 tensor has been SOA'ed in set_tensor +// we store SOA'ed tensors in a map in set_tensor, check against that map +static bool ggml_cl_is_q4_0_soa(const ggml_tensor * tensor) { + if (tensor == nullptr || tensor->type != GGML_TYPE_Q4_0 || tensor->buffer == nullptr) { + return false; + } + auto * ctx = (ggml_backend_opencl_buffer_context *) tensor->buffer->context; + if (ctx == nullptr) { + return false; + } + const ggml_tensor * key = tensor->view_src != nullptr ? tensor->view_src : tensor; + return ctx->q4_0_soa_tensors.count(key) > 0; } -GGML_BACKEND_DL_IMPL(ggml_backend_opencl_reg) +static void ggml_cl_set_rows(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + GGML_ASSERT(src1->type == GGML_TYPE_I64 || src1->type == GGML_TYPE_I32); -//------------------------------------------------------------------------------ -// Debugging utils -//------------------------------------------------------------------------------ -#if 0 -#define QK4_0 32 -typedef struct { - ggml_fp16_t d; // delta - uint8_t qs[QK4_0 / 2]; // nibbles / quants -} block_q4_0; -static_assert(sizeof(block_q4_0) == sizeof(ggml_fp16_t) + QK4_0 / 2, - "wrong q4_0 block size/padding"); + // ne0 = ne00 + // ne2 = ne02 + // ne3 = ne03 -#define QK_MXFP4 32 + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); -#include -#ifdef __cplusplus -#include "half.hpp" -#endif + GGML_TENSOR_LOCALS(int, ne1, src1, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); -static void dump_tensor(ggml_backend_t backend, const struct ggml_tensor * tensor) { - void * buf = malloc(ggml_nbytes(tensor)); + GGML_TENSOR_LOCALS(int, ne, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - cl_command_queue queue = backend_ctx->queue; -#ifdef GGML_OPENCL_SOA_Q - void * buf_q; - void * buf_d; -#endif + const int nblk0 = ne0/ggml_blck_size(dst->type); - // Make sure everything is done. - CL_CHECK(clFinish(queue)); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; -#ifdef GGML_OPENCL_SOA_Q - if (tensor->type == GGML_TYPE_Q4_0) { - ggml_tensor_extra_cl_q4_0 * extra = (ggml_tensor_extra_cl_q4_0 *) tensor->extra; - GGML_ASSERT(extra); + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - size_t size_q = ggml_nelements(tensor)/QK4_0 * QK4_0/2; - size_t size_d = ggml_nelements(tensor)/QK4_0 * sizeof(ggml_fp16_t); - GGML_ASSERT(size_q + size_d == ggml_nbytes(tensor)); - buf_q = malloc(size_q); - buf_d = malloc(size_d); + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; - CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); - CL_CHECK(clEnqueueReadBuffer(queue, extra->d, CL_TRUE, 0, size_d, buf_d, 0, NULL, NULL)); - CL_CHECK(clFinish(queue)); - } else if (tensor->type == GGML_TYPE_MXFP4) { - ggml_tensor_extra_cl_mxfp4 * extra = (ggml_tensor_extra_cl_mxfp4 *) tensor->extra; - GGML_ASSERT(extra); + const bool q8_0_soa = dst->type == GGML_TYPE_Q8_0 && ggml_cl_is_q8_0_soa(dst); + const bool q4_0_soa = dst->type == GGML_TYPE_Q4_0 && ggml_cl_is_q4_0_soa(dst); + const bool is_soa = q8_0_soa || q4_0_soa; - size_t size_q = ggml_nelements(tensor)/QK_MXFP4 * QK_MXFP4/2; - size_t size_e = ggml_nelements(tensor)/QK_MXFP4 * sizeof(char); - GGML_ASSERT(size_q + size_e == ggml_nbytes(tensor)); - buf_q = malloc(size_q); - buf_d = malloc(size_e); + cl_kernel kernel; - CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); - CL_CHECK(clEnqueueReadBuffer(queue, extra->e, CL_TRUE, 0, size_e, buf_d, 0, NULL, NULL)); - CL_CHECK(clFinish(queue)); + if (q8_0_soa) { + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_q8_0_soa_i64 + : backend_ctx->kernel_set_rows_q8_0_soa_i32; + } else if (q4_0_soa) { + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_q4_0_soa_i64 + : backend_ctx->kernel_set_rows_q4_0_soa_i32; } else { - // Read out the tensor from GPU memory. - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra); - - CL_CHECK(clEnqueueReadBuffer(queue, extra->data_device, CL_TRUE, - extra->offset, ggml_nbytes(tensor), buf, 0, NULL, NULL)); - CL_CHECK(clFinish(queue)); + switch (dst->type) { + case GGML_TYPE_F32: + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_f32_i64 + : backend_ctx->kernel_set_rows_f32_i32; + break; + case GGML_TYPE_F16: + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_f16_i64 + : backend_ctx->kernel_set_rows_f16_i32; + break; + case GGML_TYPE_Q8_0: + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_q8_0_i64 + : backend_ctx->kernel_set_rows_q8_0_i32; + break; + case GGML_TYPE_Q4_0: + kernel = (src1->type == GGML_TYPE_I64) + ? backend_ctx->kernel_set_rows_q4_0_i64 + : backend_ctx->kernel_set_rows_q4_0_i32; + break; + default: + GGML_ABORT("not implemented"); + } } -#else - // Read out the tensor from GPU memory. - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra); - CL_CHECK(clEnqueueReadBuffer(queue, extra->data_device, CL_TRUE, - extra->offset, ggml_nbytes(tensor), buf, 0, NULL, NULL)); - CL_CHECK(clFinish(queue)); -#endif // GGML_OPENCL_SOA_Q + fastdiv_vals ne11_ = init_fastdiv_values(ne11); + fastdiv_vals ne12_ = init_fastdiv_values(ne12); - // Open file and dump. - char fname[512]; - snprintf(fname, sizeof(fname), "./tensor-dumps/%s.txt", tensor->name); - FILE * f = fopen(fname, "w"); - if (!f) { - printf("Failed to open %s\n", fname); - return; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - if (tensor->type == GGML_TYPE_F32) { - float * data = (float *) buf; - for (int i = 0; i < ggml_nelements(tensor); ++i) { - if (isnan(data[i])) { - printf("NaN found: %s\n", tensor->name); - break; - } - fprintf(f, "%f\n", data[i]); - } - } else if (tensor->type == GGML_TYPE_I32) { - int * data = (int *) buf; - for (int i = 0; i < ggml_nelements(tensor); ++i) { - if (isnan(data[i])) { - printf("NaN found: %s\n", tensor->name); - break; - } - fprintf(f, "%d\n", data[i]); - } - } else if (tensor->type == GGML_TYPE_F16) { -#ifdef __cplusplus - half_float::half * data = (half_float::half *) buf; - for (int i = 0; i < ggml_nelements(tensor); ++i) { - if (std::isnan(data[i])) { - printf("NaN found: %s\n", tensor->name); - break; - } - fprintf(f, "%f\n", float(data[i])); + if (is_soa) { + // The q/d subbuffers in q8_0/q4_0 extras are interchangeable here. + // For views (e.g. ggml_set_rows' `out`), follow view_src for the SoA extra. + const ggml_tensor * soa_src = dst->view_src != nullptr ? dst->view_src : dst; + cl_mem q_mem = nullptr; + cl_mem d_mem = nullptr; + if (q8_0_soa) { + ggml_tensor_extra_cl_q8_0 * e = (ggml_tensor_extra_cl_q8_0 *)soa_src->extra; + q_mem = e->q; + d_mem = e->d; + } else { + ggml_tensor_extra_cl_q4_0 * e = (ggml_tensor_extra_cl_q4_0 *)soa_src->extra; + q_mem = e->q; + d_mem = e->d; } -#endif - } else if (tensor->type == GGML_TYPE_Q4_0) { -#ifdef GGML_OPENCL_SOA_Q - ggml_fp16_t * data_d = (ggml_fp16_t *)buf_d; - unsigned char * data_q = (unsigned char *)buf_q; + cl_ulong offset_q = 0; + cl_ulong offset_d = 0; + const int ne1_dst = dst->ne[1]; + const int ne2_dst = dst->ne[2]; + const int ne3_dst = dst->ne[3]; + + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &q_mem)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset_q)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &d_mem)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset_d)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(fastdiv_vals), &ne11_)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(fastdiv_vals), &ne12_)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &nblk0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1_dst)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne2_dst)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne3_dst)); + } else { + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(fastdiv_vals), &ne11_)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(fastdiv_vals), &ne12_)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &nblk0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb3)); + } - for (int i = 0; i < ggml_nelements(tensor)/QK4_0; ++i) { - fprintf(f, "%04x, ", data_d[i]); - for (int k = 0; k < QK4_0/2; ++k) { - fprintf(f, "%02x, ", data_q[k]); - } - fprintf(f, "\n"); - data_q += QK4_0/2; - } - free(buf_d); - free(buf_q); -#else - block_q4_0 * data = (block_q4_0 *) buf; - for (int i = 0; i < ggml_nelements(tensor)/QK4_0; ++i) { - fprintf(f, "%04x, ", data[i].d); - for (int k = 0; k < QK4_0/2; ++k) { - fprintf(f, "%02x, ", data[i].qs[k]); - } - fprintf(f, "\n"); - } -#endif // GGML_OPENCL_SOA_Q + int nth0 = 64; + if (backend_ctx->gpu_family == INTEL) { + nth0 = 32; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; } - free(buf); - fflush(f); - fclose(f); -} -#else -#define dump_tensor(tensor) -#endif -//------------------------------------------------------------------------------ -// Ops -//------------------------------------------------------------------------------ + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth0 < nblk0 && nth0 < max_workgroup_size) { + nth0 *= 2; + } -static bool ggml_cl_can_mul_mat(const struct ggml_tensor * src0, const struct ggml_tensor * src1, struct ggml_tensor * dst) { - const int64_t ne10 = src1->ne[0]; + int rows_per_workgroup = 1; + if (nth0 > nblk0) { + rows_per_workgroup = nth0 / nblk0; + nth0 = nblk0; + } - const int64_t ne0 = dst->ne[0]; - const int64_t ne1 = dst->ne[1]; + size_t global_work_size[] = { + (size_t)(ne01 + rows_per_workgroup - 1)/rows_per_workgroup*nth0, + (size_t)ne02*rows_per_workgroup, + (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth0, (size_t)rows_per_workgroup, 1}; - // TODO: find the optimal values for these - return (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && - src1->type == GGML_TYPE_F32 && - dst->type == GGML_TYPE_F32 && - (ne0 >= 32 && ne1 >= 32 && ne10 >= 32); + // ne01 == 0 makes global_work_size[0] zero here; enqueue_ndrange_kernel drops the empty range. + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -// Copy a noncontiguous tensor to contiguous tensor. ne[] remains the same but -// nb[] is recalculated such that tensor is contiguous. -static void ggml_cl_copy_to_contiguous(ggml_backend_t backend, const ggml_tensor * src, cl_mem dst, - cl_ulong &nb0, cl_ulong &nb1, cl_ulong &nb2, cl_ulong &nb3) { - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; +static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - const int tensor_type_size = ggml_type_size(src->type); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const int ne00 = src->ne[0]; - const int ne01 = src->ne[1]; - const int ne02 = src->ne[2]; - const int ne03 = src->ne[3]; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb00 = src->nb[0]; - const cl_ulong nb01 = src->nb[1]; - const cl_ulong nb02 = src->nb[2]; - const cl_ulong nb03 = src->nb[3]; + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; - const int ne0 = src->ne[0]; - const int ne1 = src->ne[1]; - const int ne2 = src->ne[2]; - const int ne3 = src->ne[3]; + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; - nb0 = tensor_type_size; - nb1 = tensor_type_size*ne00; - nb2 = tensor_type_size*ne00*ne01; - nb3 = tensor_type_size*ne00*ne01*ne02; + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *)src->extra; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - cl_ulong offset0 = extra->offset + src->view_offs; - cl_ulong offsetd = 0; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; cl_kernel kernel; - switch (src->type) { - case GGML_TYPE_F32: - kernel = backend_ctx->kernel_cpy_f32_f32; - break; - case GGML_TYPE_F16: - case GGML_TYPE_BF16: // stored as f16 on device - kernel = backend_ctx->kernel_cpy_f16_f16; - break; - default: - GGML_ASSERT(false && "not implemented"); + const bool bcast_row = ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0; + + if (bcast_row) { + GGML_ASSERT(ggml_is_contiguous(src0)); + GGML_ASSERT(ne11 == 1); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &dst)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb3)); + if (dst->type == GGML_TYPE_F32) { + GGML_ASSERT(src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + } else { + kernel = backend_ctx->kernel_add; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + } + } else if (dst->type == GGML_TYPE_F16) { + GGML_ASSERT(src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); + const int type_src0 = (src0->type == GGML_TYPE_F32); + const int type_src1 = (src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row_f16; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &type_src1)); + } else { + kernel = backend_ctx->kernel_add_f16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(int), &type_src1)); + } + } else { + GGML_ASSERT(false && "unsupported data types for add"); + } - const int nth = MIN(64, ne00); + if (bcast_row) { + int n = ggml_nelements(dst)/4; + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, src); -} + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size_ptr, dst); + } else { + unsigned int nth = MIN(64, ne0); + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {nth, 1, 1}; -static void ggml_cl_nop(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - UNUSED(backend); - UNUSED(src0); - UNUSED(src1); - UNUSED(dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_cl_get_rows(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_add_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -13556,273 +18043,204 @@ static void ggml_cl_get_rows(ggml_backend_t backend, const ggml_tensor * src0, c GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - GGML_TENSOR_LOCALS(int, ne1, src1, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); - GGML_TENSOR_LOCALS(int, ne, dst, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); + const ggml_tensor * src2 = dst->src[2]; + GGML_ASSERT(src2); + GGML_ASSERT(src2->extra); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + + const cl_ulong nb11 = src1->nb[1]; + + const cl_ulong nb21 = src2->nb[1]; + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel; - - switch (src0->type) { - case GGML_TYPE_F32: - kernel = backend_ctx->kernel_get_rows_f32; - break; - case GGML_TYPE_F16: - kernel = backend_ctx->kernel_get_rows_f16; - break; - case GGML_TYPE_Q4_0: - kernel = backend_ctx->kernel_get_rows_q4_0; - break; - default: - GGML_ASSERT(false && "not implemented"); - } + cl_kernel kernel = backend_ctx->kernel_add_id; CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb3)); - - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - int nth = 1; - while (nth < ne00 && 2*nth <= max_workgroup_size) { - nth *= 2; - } - - int nchunks = 1; - if (src0->type == GGML_TYPE_F32) { - const int chunk_target = nth * 4; - nchunks = (ne00 + chunk_target - 1) / chunk_target; - nchunks = MAX(1, MIN(nchunks, 64)); - } + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); - size_t global_work_size[] = {(size_t)ne10*nth*nchunks, (size_t)ne11, (size_t)ne12}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + int nth = MIN(ne00, (int) backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global_work_size[] = { (size_t)ne01*nth, (size_t)ne02, 1 }; + size_t local_work_size[] = { (size_t)nth, 1, 1 }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -// check if a Q8_0 tensor has been SOA'ed in set_tensor -// we store SOA'ed tensors in a map in set_tensor, check against that map -static bool ggml_cl_is_q8_0_soa(const ggml_tensor * tensor) { - if (tensor == nullptr || tensor->type != GGML_TYPE_Q8_0 || tensor->buffer == nullptr) { - return false; - } - auto * ctx = (ggml_backend_opencl_buffer_context *) tensor->buffer->context; - if (ctx == nullptr) { - return false; - } - const ggml_tensor * key = tensor->view_src != nullptr ? tensor->view_src : tensor; - return ctx->q8_0_soa_tensors.count(key) > 0; -} - -// check if a Q4_0 tensor has been SOA'ed in set_tensor -// we store SOA'ed tensors in a map in set_tensor, check against that map -static bool ggml_cl_is_q4_0_soa(const ggml_tensor * tensor) { - if (tensor == nullptr || tensor->type != GGML_TYPE_Q4_0 || tensor->buffer == nullptr) { - return false; - } - auto * ctx = (ggml_backend_opencl_buffer_context *) tensor->buffer->context; - if (ctx == nullptr) { - return false; - } - const ggml_tensor * key = tensor->view_src != nullptr ? tensor->view_src : tensor; - return ctx->q4_0_soa_tensors.count(key) > 0; -} - -static void ggml_cl_set_rows(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(src1->type == GGML_TYPE_I64 || src1->type == GGML_TYPE_I32); - // ne0 = ne00 - // ne2 = ne02 - // ne3 = ne03 + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - GGML_TENSOR_LOCALS(int, ne1, src1, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - GGML_TENSOR_LOCALS(int, ne, dst, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; UNUSED(ne13); - const int nblk0 = ne0/ggml_blck_size(dst->type); + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; UNUSED(nb13); + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; + + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - const bool q8_0_soa = dst->type == GGML_TYPE_Q8_0 && ggml_cl_is_q8_0_soa(dst); - const bool q4_0_soa = dst->type == GGML_TYPE_Q4_0 && ggml_cl_is_q4_0_soa(dst); - const bool is_soa = q8_0_soa || q4_0_soa; - + bool bcast_row = false; cl_kernel kernel; - if (q8_0_soa) { - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_q8_0_soa_i64 - : backend_ctx->kernel_set_rows_q8_0_soa_i32; - } else if (q4_0_soa) { - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_q4_0_soa_i64 - : backend_ctx->kernel_set_rows_q4_0_soa_i32; - } else { - switch (dst->type) { - case GGML_TYPE_F32: - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_f32_i64 - : backend_ctx->kernel_set_rows_f32_i32; - break; - case GGML_TYPE_F16: - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_f16_i64 - : backend_ctx->kernel_set_rows_f16_i32; - break; - case GGML_TYPE_Q8_0: - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_q8_0_i64 - : backend_ctx->kernel_set_rows_q8_0_i32; - break; - case GGML_TYPE_Q4_0: - kernel = (src1->type == GGML_TYPE_I64) - ? backend_ctx->kernel_set_rows_q4_0_i64 - : backend_ctx->kernel_set_rows_q4_0_i32; - break; - default: - GGML_ABORT("not implemented"); - } - } + if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { + GGML_ASSERT(ggml_is_contiguous(src0)); - fastdiv_vals ne11_ = init_fastdiv_values(ne11); - fastdiv_vals ne12_ = init_fastdiv_values(ne12); + // src1 is a row + GGML_ASSERT(ne11 == 1); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + bcast_row = true; + int ne = ne00 / 4; - if (is_soa) { - // The q/d subbuffers in q8_0/q4_0 extras are interchangeable here. - // For views (e.g. ggml_set_rows' `out`), follow view_src for the SoA extra. - const ggml_tensor * soa_src = dst->view_src != nullptr ? dst->view_src : dst; - cl_mem q_mem = nullptr; - cl_mem d_mem = nullptr; - if (q8_0_soa) { - ggml_tensor_extra_cl_q8_0 * e = (ggml_tensor_extra_cl_q8_0 *)soa_src->extra; - q_mem = e->q; - d_mem = e->d; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul_row; } else { - ggml_tensor_extra_cl_q4_0 * e = (ggml_tensor_extra_cl_q4_0 *)soa_src->extra; - q_mem = e->q; - d_mem = e->d; + kernel = backend_ctx->kernel_mul_row_f16; } - cl_ulong offset_q = 0; - cl_ulong offset_d = 0; - const int ne1_dst = dst->ne[1]; - const int ne2_dst = dst->ne[2]; - const int ne3_dst = dst->ne[3]; - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &q_mem)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset_q)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &d_mem)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset_d)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(fastdiv_vals), &ne11_)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(fastdiv_vals), &ne12_)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &nblk0)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1_dst)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne2_dst)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne3_dst)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - cl_ulong offsetd = extrad->offset + dst->view_offs; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul; + } else { + kernel = backend_ctx->kernel_mul_f16; + } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(fastdiv_vals), &ne11_)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(fastdiv_vals), &ne12_)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &nblk0)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb3)); - } - - int nth0 = 64; - if (backend_ctx->gpu_family == INTEL) { - nth0 = 32; - } else if (backend_ctx->gpu_family == ADRENO) { - nth0 = 64; + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); } - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - while (nth0 < nblk0 && nth0 < max_workgroup_size) { - nth0 *= 2; - } + if (bcast_row) { + int n = ggml_nelements(dst)/4; + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - int rows_per_workgroup = 1; - if (nth0 > nblk0) { - rows_per_workgroup = nth0 / nblk0; - nth0 = nblk0; - } + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + } - size_t global_work_size[] = { - (size_t)(ne01 + rows_per_workgroup - 1)/rows_per_workgroup*nth0, - (size_t)ne02*rows_per_workgroup, - (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth0, (size_t)rows_per_workgroup, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + } else { + unsigned int nth = MIN(64, ne0); + size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {nth, 1, 1}; - // ne01 == 0 makes global_work_size[0] zero here; enqueue_ndrange_kernel drops the empty range. - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -13830,6 +18248,10 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; @@ -13851,9 +18273,6 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const const cl_ulong nb13 = src1->nb[3]; const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; - const int ne2 = dst->ne[2]; - const int ne3 = dst->ne[3]; const cl_ulong nb0 = dst->nb[0]; const cl_ulong nb1 = dst->nb[1]; @@ -13870,114 +18289,61 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; + bool bcast_row = false; cl_kernel kernel; - const bool bcast_row = ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0; - - if (bcast_row) { + if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { GGML_ASSERT(ggml_is_contiguous(src0)); + + // src1 is a row GGML_ASSERT(ne11 == 1); - } - if (dst->type == GGML_TYPE_F32) { - GGML_ASSERT(src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32); - if (bcast_row) { - kernel = backend_ctx->kernel_add_row; - const int ne = ne00 / 4; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + bcast_row = true; + int ne = ne00 / 4; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div_row; } else { - kernel = backend_ctx->kernel_add; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + kernel = backend_ctx->kernel_div_row_f16; } - } else if (dst->type == GGML_TYPE_F16) { - GGML_ASSERT(src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_F32); - GGML_ASSERT(src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); - const int type_src0 = (src0->type == GGML_TYPE_F32); - const int type_src1 = (src1->type == GGML_TYPE_F32); - if (bcast_row) { - kernel = backend_ctx->kernel_add_row_f16; - const int ne = ne00 / 4; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &type_src0)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &type_src1)); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div; } else { - kernel = backend_ctx->kernel_add_f16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &type_src0)); - CL_CHECK(clSetKernelArg(kernel, 31, sizeof(int), &type_src1)); + kernel = backend_ctx->kernel_div_f16; } - } else { - GGML_ASSERT(false && "unsupported data types for add"); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); } if (bcast_row) { @@ -13985,22 +18351,17 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const size_t global_work_size[] = {(size_t)n, 1, 1}; size_t local_work_size[] = {64, 1, 1}; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } - - backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } else { unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {nth, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } } -static void ggml_cl_add_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_sub(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -14008,204 +18369,420 @@ static void ggml_cl_add_id(ggml_backend_t backend, const ggml_tensor * src0, con GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - const ggml_tensor * src2 = dst->src[2]; - GGML_ASSERT(src2); - GGML_ASSERT(src2->extra); - - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(src1->type == GGML_TYPE_F32); - GGML_ASSERT(src2->type == GGML_TYPE_I32); - GGML_ASSERT(dst->type == GGML_TYPE_F32); - - GGML_ASSERT(ggml_is_contiguous_rows(src0)); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + const cl_ulong nb00 = src0->nb[0]; const cl_ulong nb01 = src0->nb[1]; const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; + + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; + const cl_ulong nb10 = src1->nb[0]; const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; - const cl_ulong nb21 = src2->nb[1]; + const int ne0 = dst->ne[0]; - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel = backend_ctx->kernel_add_id; + bool bcast_row = false; + cl_kernel kernel; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb21)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { + GGML_ASSERT(ggml_is_contiguous(src0)); - int nth = MIN(ne00, (int) backend_ctx->get_kernel_workgroup_size(kernel)); - size_t global_work_size[] = { (size_t)ne01*nth, (size_t)ne02, 1 }; - size_t local_work_size[] = { (size_t)nth, 1, 1 }; + // src1 is a row + GGML_ASSERT(ne11 == 1); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + bcast_row = true; + int ne = ne00 / 4; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub_row; + } else { + kernel = backend_ctx->kernel_sub_row_f16; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub; + } else { + kernel = backend_ctx->kernel_sub_f16; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + } + + if (bcast_row) { + int n = ggml_nelements(dst)/4; + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } else { + unsigned int nth = MIN(64, ne0); + size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_sqr(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + UNUSED(src1); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + cl_kernel kernel; + + // Currently assumes src0 is contiguous + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sqr_cont_f32_4; + } else { + kernel = backend_ctx->kernel_sqr_cont_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sqr_cont_f32; + } else { + kernel = backend_ctx->kernel_sqr_cont_f16; + } + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); +} + +static void ggml_cl_sqrt(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + UNUSED(src1); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + cl_kernel kernel; + + // Currently assumes src0 is contiguous + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sqrt_cont_f32_4; + } else { + kernel = backend_ctx->kernel_sqrt_cont_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sqrt_cont_f32; + } else { + kernel = backend_ctx->kernel_sqrt_cont_f16; + } + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); +} + +static void ggml_cl_mean(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_UNUSED(src1); + + GGML_ASSERT(src0->nb[0] == ggml_type_size(src0->type)); - GGML_ASSERT(src0->type == src1->type); - GGML_ASSERT(src0->type == dst->type); - GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; const int ne03 = src0->ne[3]; - const cl_ulong nb00 = src0->nb[0]; const cl_ulong nb01 = src0->nb[1]; const cl_ulong nb02 = src0->nb[2]; const cl_ulong nb03 = src0->nb[3]; - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int ne13 = src1->ne[3]; UNUSED(ne13); - - const cl_ulong nb10 = src1->nb[0]; - const cl_ulong nb11 = src1->nb[1]; - const cl_ulong nb12 = src1->nb[2]; - const cl_ulong nb13 = src1->nb[3]; UNUSED(nb13); - - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; - const int ne2 = dst->ne[2]; - const int ne3 = dst->ne[3]; - - const cl_ulong nb0 = dst->nb[0]; const cl_ulong nb1 = dst->nb[1]; const cl_ulong nb2 = dst->nb[2]; const cl_ulong nb3 = dst->nb[3]; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + cl_kernel kernel; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const bool is_c4 = ne00 % 4 == 0; + if (is_c4) { + kernel = backend_ctx->kernel_mean_f32_4; + } else { + kernel = backend_ctx->kernel_mean_f32; + } - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb3)); - bool bcast_row = false; - cl_kernel kernel; + size_t global_work_size[] = {64 * (size_t)ne01, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)64, 1, 1}; - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { - GGML_ASSERT(ggml_is_contiguous(src0)); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} - // src1 is a row - GGML_ASSERT(ne11 == 1); +static void ggml_cl_ssm_scan(ggml_backend_t backend, ggml_tensor * dst) { + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + GGML_ASSERT(dst->src[0]); + GGML_ASSERT(dst->src[0]->extra); + GGML_ASSERT(dst->src[1]); + GGML_ASSERT(dst->src[1]->extra); + GGML_ASSERT(dst->src[2]); + GGML_ASSERT(dst->src[2]->extra); + GGML_ASSERT(dst->src[3]); + GGML_ASSERT(dst->src[3]->extra); + GGML_ASSERT(dst->src[4]); + GGML_ASSERT(dst->src[4]->extra); + GGML_ASSERT(dst->src[5]); + GGML_ASSERT(dst->src[5]->extra); + GGML_ASSERT(dst->src[6]); + GGML_ASSERT(dst->src[6]->extra); - bcast_row = true; - int ne = ne00 / 4; + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_mul_row; - } else { - kernel = backend_ctx->kernel_mul_row_f16; - } + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) dst->src[0]->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *) dst->src[1]->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *) dst->src[2]->extra; + ggml_tensor_extra_cl * extra3 = (ggml_tensor_extra_cl *) dst->src[3]->extra; + ggml_tensor_extra_cl * extra4 = (ggml_tensor_extra_cl *) dst->src[4]->extra; + ggml_tensor_extra_cl * extra5 = (ggml_tensor_extra_cl *) dst->src[5]->extra; + ggml_tensor_extra_cl * extra6 = (ggml_tensor_extra_cl *) dst->src[6]->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_mul; - } else { - kernel = backend_ctx->kernel_mul_f16; - } + const cl_ulong offset0 = extra0->offset + dst->src[0]->view_offs; + const cl_ulong offset1 = extra1->offset + dst->src[1]->view_offs; + const cl_ulong offset2 = extra2->offset + dst->src[2]->view_offs; + const cl_ulong offset3 = extra3->offset + dst->src[3]->view_offs; + const cl_ulong offset4 = extra4->offset + dst->src[4]->view_offs; + const cl_ulong offset5 = extra5->offset + dst->src[5]->view_offs; + const cl_ulong offset6 = extra6->offset + dst->src[6]->view_offs; + const cl_ulong offsetd = extrad->offset + dst->view_offs; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); - } + const ggml_tensor * s = dst->src[0]; + const ggml_tensor * x = dst->src[1]; + const ggml_tensor * dt = dst->src[2]; + const ggml_tensor * A = dst->src[3]; + const ggml_tensor * B = dst->src[4]; + const ggml_tensor * C = dst->src[5]; - if (bcast_row) { - int n = ggml_nelements(dst)/4; - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + const cl_ulong s_nb1 = s->nb[1]; + const cl_ulong s_nb2 = s->nb[2]; + const cl_ulong s_nb3 = s->nb[3]; + const cl_ulong x_nb1 = x->nb[1]; + const cl_ulong x_nb2 = x->nb[2]; + const cl_ulong x_nb3 = x->nb[3]; + const cl_ulong dt_nb1 = dt->nb[1]; + const cl_ulong dt_nb2 = dt->nb[2]; + const cl_ulong A_nb1 = A->nb[1]; + const cl_ulong B_nb1 = B->nb[1]; + const cl_ulong B_nb2 = B->nb[2]; + const cl_ulong B_nb3 = B->nb[3]; + const cl_ulong C_nb1 = C->nb[1]; + const cl_ulong C_nb2 = C->nb[2]; + const cl_ulong C_nb3 = C->nb[3]; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + const cl_uint A_ne0 = A->ne[0]; + const cl_uint d_state = s->ne[0]; + const cl_int head_dim = x->ne[0]; + const cl_int n_head = x->ne[1]; + const cl_int n_group = B->ne[1]; + const cl_int n_tokens = x->ne[2]; + const cl_uint n_seqs = x->ne[3]; + const cl_uint K = ggml_get_op_params_i32(dst, 0); + const cl_ulong s_off_bytes = (cl_ulong) ggml_nelements(x) * sizeof(float); + + cl_kernel kernel = backend_ctx->kernel_ssm_scan_f32; + size_t nth = d_state; + if (A_ne0 == 1 && K == 1) { + cl_kernel kernel_mamba2 = nullptr; + if (d_state == 128) { + kernel_mamba2 = backend_ctx->kernel_ssm_scan_f32_mamba2_d128; + } else if (d_state == 256) { + kernel_mamba2 = backend_ctx->kernel_ssm_scan_f32_mamba2_d256; + } + if (kernel_mamba2 != nullptr) { + kernel = kernel_mamba2; + nth = 64; } + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); - } else { - unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {nth, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra3->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extra4->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offset4)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_mem), &extra5->data_device)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &offset5)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_mem), &extra6->data_device)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &offset6)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &s_nb2)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &s_nb3)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &x_nb2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &x_nb3)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &dt_nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &dt_nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &A_nb1)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &B_nb2)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &B_nb3)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(cl_ulong), &C_nb2)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &C_nb3)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &s_off_bytes)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_int), &head_dim)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_int), &n_group)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_int), &n_tokens)); + + if (kernel == backend_ctx->kernel_ssm_scan_f32) { + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &s_nb1)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &x_nb1)); + CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &B_nb1)); + CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &C_nb1)); + CL_CHECK(clSetKernelArg(kernel, 36, sizeof(cl_uint), &A_ne0)); + CL_CHECK(clSetKernelArg(kernel, 37, sizeof(cl_uint), &d_state)); + CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_uint), &n_seqs)); + CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_uint), &K)); + CL_CHECK(clSetKernelArg(kernel, 40, d_state * sizeof(float), nullptr)); + } + + size_t global_work_size[] = { + (size_t) head_dim * (size_t) n_head * nth, + (size_t) n_seqs, + }; + size_t local_work_size[] = { nth, 1 }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); } -static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_ssm_conv(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -14213,37 +18790,6 @@ static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == src1->type); - GGML_ASSERT(src0->type == dst->type); - GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; - - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; - - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int ne13 = src1->ne[3]; - - const cl_ulong nb10 = src1->nb[0]; - const cl_ulong nb11 = src1->nb[1]; - const cl_ulong nb12 = src1->nb[2]; - const cl_ulong nb13 = src1->nb[3]; - - const int ne0 = dst->ne[0]; - - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; @@ -14254,204 +18800,134 @@ static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - bool bcast_row = false; - cl_kernel kernel; - - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { - GGML_ASSERT(ggml_is_contiguous(src0)); - - // src1 is a row - GGML_ASSERT(ne11 == 1); + int ne01 = src0->ne[1]; + cl_ulong nb00 = src0->nb[0]; + cl_ulong nb01 = src0->nb[1]; + cl_ulong nb02 = src0->nb[2]; - bcast_row = true; - int ne = ne00 / 4; + int ne10 = src1->ne[0]; + cl_ulong nb11 = src1->nb[1]; - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_div_row; - } else { - kernel = backend_ctx->kernel_div_row_f16; - } + int ne1 = dst->ne[1]; + int ne2 = dst->ne[2]; + cl_ulong nb0 = dst->nb[0]; + cl_ulong nb1 = dst->nb[1]; + cl_ulong nb2 = dst->nb[2]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_div; - } else { - kernel = backend_ctx->kernel_div_f16; - } + cl_kernel kernel = backend_ctx->kernel_ssm_conv_f32_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + if (ne10 % 4 == 0) { + kernel = backend_ctx->kernel_ssm_conv_f32_f32_4; } - if (bcast_row) { - int n = ggml_nelements(dst)/4; - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb2)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } else { - unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {nth, 1, 1}; + size_t global_work_size[] = {(size_t)ne01, (size_t)ne1, (size_t)ne2}; + size_t local_work_size[] = {64, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t * local_work_size_ptr = local_work_size; + if (ne01 % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_sub(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_gelu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == src1->type); - GGML_ASSERT(src0->type == dst->type); - GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + UNUSED(src1); - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int ne13 = src1->ne[3]; + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - const cl_ulong nb10 = src1->nb[0]; - const cl_ulong nb11 = src1->nb[1]; - const cl_ulong nb12 = src1->nb[2]; - const cl_ulong nb13 = src1->nb[3]; + cl_kernel kernel; - const int ne0 = dst->ne[0]; + int n = ggml_nelements(dst); - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + if (n % 4 == 0) { + kernel = backend_ctx->kernel_gelu_4; + n /= 4; + } else { + kernel = backend_ctx->kernel_gelu; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_cl_gelu_erf(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + UNUSED(src1); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - bool bcast_row = false; cl_kernel kernel; - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { - GGML_ASSERT(ggml_is_contiguous(src0)); - - // src1 is a row - GGML_ASSERT(ne11 == 1); - - bcast_row = true; - int ne = ne00 / 4; - - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sub_row; - } else { - kernel = backend_ctx->kernel_sub_row_f16; - } + int n = ggml_nelements(dst); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + if (n % 4 == 0) { + kernel = backend_ctx->kernel_gelu_erf_4; + n /= 4; } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sub; - } else { - kernel = backend_ctx->kernel_sub_f16; - } - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + kernel = backend_ctx->kernel_gelu_erf; } - if (bcast_row) { - int n = ggml_nelements(dst)/4; - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } else { - unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {nth, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_sqr(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_gelu_quick(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + UNUSED(src1); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -14464,21 +18940,13 @@ static void ggml_cl_sqr(ggml_backend_t backend, const ggml_tensor * src0, const cl_kernel kernel; - // Currently assumes src0 is contiguous int n = ggml_nelements(dst); + if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sqr_cont_f32_4; - } else { - kernel = backend_ctx->kernel_sqr_cont_f16_4; - } + kernel = backend_ctx->kernel_gelu_quick_4; n /= 4; } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sqr_cont_f32; - } else { - kernel = backend_ctx->kernel_sqr_cont_f16; - } + kernel = backend_ctx->kernel_gelu_quick; } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); @@ -14489,19 +18957,15 @@ static void ggml_cl_sqr(ggml_backend_t backend, const ggml_tensor * src0, const size_t global_work_size[] = {(size_t)n, 1, 1}; size_t local_work_size[] = {64, 1, 1}; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_sqrt(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_silu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + UNUSED(src1); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -14514,21 +18978,13 @@ static void ggml_cl_sqrt(ggml_backend_t backend, const ggml_tensor * src0, const cl_kernel kernel; - // Currently assumes src0 is contiguous int n = ggml_nelements(dst); + if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sqrt_cont_f32_4; - } else { - kernel = backend_ctx->kernel_sqrt_cont_f16_4; - } + kernel = backend_ctx->kernel_silu_4; n /= 4; } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sqrt_cont_f32; - } else { - kernel = backend_ctx->kernel_sqrt_cont_f16; - } + kernel = backend_ctx->kernel_silu; } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); @@ -14541,20 +18997,19 @@ static void ggml_cl_sqrt(ggml_backend_t backend, const ggml_tensor * src0, const size_t * local_work_size_ptr = local_work_size; if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; + local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. } backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_mean(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_relu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_UNUSED(src1); - GGML_ASSERT(src0->nb[0] == ggml_type_size(src0->type)); + UNUSED(src1); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -14564,292 +19019,141 @@ static void ggml_cl_mean(ggml_backend_t backend, const ggml_tensor * src0, const cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + cl_kernel kernel = backend_ctx->kernel_relu; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + const int64_t n = ggml_nelements(dst); - cl_kernel kernel; + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - const bool is_c4 = ne00 % 4 == 0; - if (is_c4) { - kernel = backend_ctx->kernel_mean_f32_4; - } else { - kernel = backend_ctx->kernel_mean_f32; + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb3)); - - size_t global_work_size[] = {64 * (size_t)ne01, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)64, 1, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_ssm_scan(ggml_backend_t backend, ggml_tensor * dst) { +static void ggml_cl_sigmoid(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(dst->src[0]); - GGML_ASSERT(dst->src[0]->extra); - GGML_ASSERT(dst->src[1]); - GGML_ASSERT(dst->src[1]->extra); - GGML_ASSERT(dst->src[2]); - GGML_ASSERT(dst->src[2]->extra); - GGML_ASSERT(dst->src[3]); - GGML_ASSERT(dst->src[3]->extra); - GGML_ASSERT(dst->src[4]); - GGML_ASSERT(dst->src[4]->extra); - GGML_ASSERT(dst->src[5]); - GGML_ASSERT(dst->src[5]->extra); - GGML_ASSERT(dst->src[6]); - GGML_ASSERT(dst->src[6]->extra); - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; - - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) dst->src[0]->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *) dst->src[1]->extra; - ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *) dst->src[2]->extra; - ggml_tensor_extra_cl * extra3 = (ggml_tensor_extra_cl *) dst->src[3]->extra; - ggml_tensor_extra_cl * extra4 = (ggml_tensor_extra_cl *) dst->src[4]->extra; - ggml_tensor_extra_cl * extra5 = (ggml_tensor_extra_cl *) dst->src[5]->extra; - ggml_tensor_extra_cl * extra6 = (ggml_tensor_extra_cl *) dst->src[6]->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; - - const cl_ulong offset0 = extra0->offset + dst->src[0]->view_offs; - const cl_ulong offset1 = extra1->offset + dst->src[1]->view_offs; - const cl_ulong offset2 = extra2->offset + dst->src[2]->view_offs; - const cl_ulong offset3 = extra3->offset + dst->src[3]->view_offs; - const cl_ulong offset4 = extra4->offset + dst->src[4]->view_offs; - const cl_ulong offset5 = extra5->offset + dst->src[5]->view_offs; - const cl_ulong offset6 = extra6->offset + dst->src[6]->view_offs; - const cl_ulong offsetd = extrad->offset + dst->view_offs; + UNUSED(src1); - const ggml_tensor * s = dst->src[0]; - const ggml_tensor * x = dst->src[1]; - const ggml_tensor * dt = dst->src[2]; - const ggml_tensor * A = dst->src[3]; - const ggml_tensor * B = dst->src[4]; - const ggml_tensor * C = dst->src[5]; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - const cl_ulong s_nb1 = s->nb[1]; - const cl_ulong s_nb2 = s->nb[2]; - const cl_ulong s_nb3 = s->nb[3]; - const cl_ulong x_nb1 = x->nb[1]; - const cl_ulong x_nb2 = x->nb[2]; - const cl_ulong x_nb3 = x->nb[3]; - const cl_ulong dt_nb1 = dt->nb[1]; - const cl_ulong dt_nb2 = dt->nb[2]; - const cl_ulong A_nb1 = A->nb[1]; - const cl_ulong B_nb1 = B->nb[1]; - const cl_ulong B_nb2 = B->nb[2]; - const cl_ulong B_nb3 = B->nb[3]; - const cl_ulong C_nb1 = C->nb[1]; - const cl_ulong C_nb2 = C->nb[2]; - const cl_ulong C_nb3 = C->nb[3]; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - const cl_uint A_ne0 = A->ne[0]; - const cl_uint d_state = s->ne[0]; - const cl_int head_dim = x->ne[0]; - const cl_int n_head = x->ne[1]; - const cl_int n_group = B->ne[1]; - const cl_int n_tokens = x->ne[2]; - const cl_uint n_seqs = x->ne[3]; - const cl_uint K = ggml_get_op_params_i32(dst, 0); - const cl_ulong s_off_bytes = (cl_ulong) ggml_nelements(x) * sizeof(float); + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel = backend_ctx->kernel_ssm_scan_f32; - size_t nth = d_state; - if (A_ne0 == 1 && K == 1) { - cl_kernel kernel_mamba2 = nullptr; - if (d_state == 128) { - kernel_mamba2 = backend_ctx->kernel_ssm_scan_f32_mamba2_d128; - } else if (d_state == 256) { - kernel_mamba2 = backend_ctx->kernel_ssm_scan_f32_mamba2_d256; - } - if (kernel_mamba2 != nullptr) { - kernel = kernel_mamba2; - nth = 64; - } + cl_kernel kernel; + if (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sigmoid_f32; + } else if (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_sigmoid_f16; + } else if (src0->type == GGML_TYPE_BF16 && dst->type == GGML_TYPE_BF16) { + // bf16 converted to f16 + kernel = backend_ctx->kernel_sigmoid_f16; + } else { + GGML_ASSERT(false && "Unsupported data types for sigmoid (input and output must be both f32 or f16)"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra3->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset3)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extra4->data_device)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offset4)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_mem), &extra5->data_device)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &offset5)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_mem), &extra6->data_device)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &offset6)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &s_nb2)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &s_nb3)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &x_nb2)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &x_nb3)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &dt_nb1)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &dt_nb2)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &A_nb1)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &B_nb2)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &B_nb3)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(cl_ulong), &C_nb2)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &C_nb3)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &s_off_bytes)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_int), &head_dim)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_int), &n_group)); - CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_int), &n_tokens)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - if (kernel == backend_ctx->kernel_ssm_scan_f32) { - CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &s_nb1)); - CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &x_nb1)); - CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &B_nb1)); - CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &C_nb1)); - CL_CHECK(clSetKernelArg(kernel, 36, sizeof(cl_uint), &A_ne0)); - CL_CHECK(clSetKernelArg(kernel, 37, sizeof(cl_uint), &d_state)); - CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_uint), &n_seqs)); - CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_uint), &K)); - CL_CHECK(clSetKernelArg(kernel, 40, d_state * sizeof(float), nullptr)); - } + const int64_t n = ggml_nelements(dst); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - size_t global_work_size[] = { - (size_t) head_dim * (size_t) n_head * nth, - (size_t) n_seqs, - }; - size_t local_work_size[] = { nth, 1 }; + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + } - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_ssm_conv(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_tri(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + UNUSED(src1); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - int ne01 = src0->ne[1]; - cl_ulong nb00 = src0->nb[0]; - cl_ulong nb01 = src0->nb[1]; - cl_ulong nb02 = src0->nb[2]; - - int ne10 = src1->ne[0]; - cl_ulong nb11 = src1->nb[1]; - - int ne1 = dst->ne[1]; - int ne2 = dst->ne[2]; - cl_ulong nb0 = dst->nb[0]; - cl_ulong nb1 = dst->nb[1]; - cl_ulong nb2 = dst->nb[2]; - - cl_kernel kernel = backend_ctx->kernel_ssm_conv_f32_f32; - - if (ne10 % 4 == 0) { - kernel = backend_ctx->kernel_ssm_conv_f32_f32_4; - } + const int tri_type = ggml_get_op_params_i32(dst, 0); + const int64_t n = ggml_nelements(dst); + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb2)); + cl_kernel kernel = backend_ctx->kernel_tri; - size_t global_work_size[] = {(size_t)ne01, (size_t)ne1, (size_t)ne2}; - size_t local_work_size[] = {64, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &tri_type)); - size_t * local_work_size_ptr = local_work_size; - if (ne01 % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } + size_t local_work_size[1] = { 256 }; + size_t global_work_size[1] = { ((size_t)n + local_work_size[0] - 1) / local_work_size[0] * local_work_size[0] }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); } -static void ggml_cl_gelu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); +static void ggml_cl_fill(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + UNUSED(src0); UNUSED(src1); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - - cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel; + float v = 0.0f; + memcpy(&v, ((int32_t *) dst->op_params), sizeof(float)); - int n = ggml_nelements(dst); + const int64_t n = ggml_nelements(dst); - if (n % 4 == 0) { - kernel = backend_ctx->kernel_gelu_4; - n /= 4; - } else { - kernel = backend_ctx->kernel_gelu; - } + cl_kernel kernel = backend_ctx->kernel_fill; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(float), &v)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(float), &n)); - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + size_t local_work_size[1] = { 256 }; + size_t global_work_size[1] = { ((size_t)n + local_work_size[0] - 1) / local_work_size[0] * local_work_size[0] }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); } -static void ggml_cl_gelu_erf(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_clamp(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -14865,29 +19169,74 @@ static void ggml_cl_gelu_erf(ggml_backend_t backend, const ggml_tensor * src0, c cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel; + float min; + float max; + memcpy(&min, ((int32_t *) dst->op_params) + 0, sizeof(float)); + memcpy(&max, ((int32_t *) dst->op_params) + 1, sizeof(float)); - int n = ggml_nelements(dst); + if (!ggml_is_contiguous(src0)) { + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - if (n % 4 == 0) { - kernel = backend_ctx->kernel_gelu_erf_4; - n /= 4; - } else { - kernel = backend_ctx->kernel_gelu_erf; + cl_kernel kernel = backend_ctx->kernel_clamp_nc; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(float), &min)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(float), &max)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb3)); + + const int nth = 64; + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; } + cl_kernel kernel = backend_ctx->kernel_clamp; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(float), &min)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(float), &max)); + + const int64_t n = ggml_nelements(dst); size_t global_work_size[] = {(size_t)n, 1, 1}; size_t local_work_size[] = {64, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_gelu_quick(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -14903,29 +19252,41 @@ static void ggml_cl_gelu_quick(ggml_backend_t backend, const ggml_tensor * src0, cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel; + float eps; + memcpy(&eps, dst->op_params, sizeof(float)); - int n = ggml_nelements(dst); + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - if (n % 4 == 0) { - kernel = backend_ctx->kernel_gelu_quick_4; - n /= 4; - } else { - kernel = backend_ctx->kernel_gelu_quick; + int nth = 1; + while (nth < ne00 && nth < 64) { + nth *= 2; } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + cl_kernel kernel = backend_ctx->kernel_norm; - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float)*nth, NULL)); + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_silu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_rms_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -14935,190 +19296,317 @@ static void ggml_cl_silu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + //ggml_backend_opencl_device_context * dev_ctx = + // (ggml_backend_opencl_device_context *)backend->device->context; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel; + float eps; + memcpy(&eps, dst->op_params, sizeof(float)); - int n = ggml_nelements(dst); + const int ne00 = src0 ? src0->ne[0] : 0; + const int ne01 = src0 ? src0->ne[1] : 0; + const int ne02 = src0 ? src0->ne[2] : 0; + const int ne03 = src0 ? src0->ne[3] : 0; - if (n % 4 == 0) { - kernel = backend_ctx->kernel_silu_4; - n /= 4; + const cl_ulong nb01 = src0 ? src0->nb[1] : 0; + const cl_ulong nb02 = src0 ? src0->nb[2] : 0; + const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + + GGML_ASSERT(ne00 % 4 == 0); + + const int nth = 64; + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + cl_kernel kernel = backend_ctx->kernel_rms_norm; + + // Note, this kernel declares local memory in kernel args and the size + // depends on subgroup size. + // Note, this requires OpenCL 2.1 and above + // For now we use fixed subgroup size to simplify support for OpenCL 2.0. + size_t sgs; + //CL_CHECK(clGetKernelSubGroupInfo(kernel, dev_ctx->device, + // CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE, + // sizeof(local_work_size), local_work_size, + // sizeof(size_t), &sgs, NULL)); + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; } else { - kernel = backend_ctx->kernel_silu; + GGML_ASSERT(false && "Unsupported GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(float), &eps)); + // This is local memory - the size depends on subgroup size. + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float)*nth/sgs, NULL)); - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. - } +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor) { + GGML_ASSERT(mul_tensor); + GGML_ASSERT(rms_norm_tensor); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); -} + // src0 is the src of rms_norm, src1 is the other src of mul (one being rms_norm) + const ggml_tensor * src0 = rms_norm_tensor->src[0]; + const ggml_tensor * src1; + if (mul_tensor->src[0] == rms_norm_tensor) { + src1 = mul_tensor->src[1]; + } else if (mul_tensor->src[1] == rms_norm_tensor) { + src1 = mul_tensor->src[0]; + } else { + GGML_ASSERT(false && "Invalid args for rms_norm and mul"); + } + const ggml_tensor * dst = mul_tensor; -static void ggml_cl_relu(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - UNUSED(src1); - - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel = backend_ctx->kernel_relu; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - - const int64_t n = ggml_nelements(dst); - - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. - } + float eps; + memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); -} + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; -static void ggml_cl_sigmoid(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - UNUSED(src1); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + GGML_ASSERT(ne00 % 4 == 0); - cl_kernel kernel; - if (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_sigmoid_f32; - } else if (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F16) { - kernel = backend_ctx->kernel_sigmoid_f16; - } else if (src0->type == GGML_TYPE_BF16 && dst->type == GGML_TYPE_BF16) { - // bf16 converted to f16 - kernel = backend_ctx->kernel_sigmoid_f16; + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; } else { - GGML_ASSERT(false && "Unsupported data types for sigmoid (input and output must be both f32 or f16)"); + GGML_ASSERT(false && "Unsupported GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + cl_kernel kernel = backend_ctx->kernel_rms_norm_mul; - const int64_t n = ggml_nelements(dst); + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00 && nth < max_workgroup_size) { + nth *= 2; + } + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00); - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float)*sgs, NULL)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_tri(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - - UNUSED(src1); +static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { + GGML_ASSERT(norm_tensor && mul_tensor && add_tensor); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const ggml_tensor * src0 = norm_tensor->src[0]; + const ggml_tensor * src1 = mul_tensor->src[0] == norm_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; + const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; + const ggml_tensor * dst = add_tensor; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int tri_type = ggml_get_op_params_i32(dst, 0); - const int64_t n = ggml_nelements(dst); - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - cl_kernel kernel = backend_ctx->kernel_tri; + float eps; + memcpy(&eps, norm_tensor->op_params, sizeof(float)); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &tri_type)); + const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; + const cl_ulong nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; + const int ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3]; + const cl_ulong nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; + const int ne20 = src2->ne[0], ne21 = src2->ne[1], ne22 = src2->ne[2], ne23 = src2->ne[3]; + const cl_ulong nb21 = src2->nb[1], nb22 = src2->nb[2], nb23 = src2->nb[3]; + const cl_ulong nbd1 = dst->nb[1], nbd2 = dst->nb[2], nbd3 = dst->nb[3]; - size_t local_work_size[1] = { 256 }; - size_t global_work_size[1] = { ((size_t)n + local_work_size[0] - 1) / local_work_size[0] * local_work_size[0] }; + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) sgs = 64; + else if (backend_ctx->gpu_family == INTEL) sgs = 32; + else GGML_ASSERT(false && "Unsupported GPU"); + + cl_kernel kernel = backend_ctx->kernel_norm_mul_add; + + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00/4 && nth < max_workgroup_size) nth *= 2; + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00/4); + + size_t gws[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t lws[] = {(size_t)nth, 1, 1}; + size_t num_subgroups = (nth + sgs - 1) / sgs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne22)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne23)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb22)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb23)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nbd1)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &nbd2)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nbd3)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_float2) * num_subgroups, NULL)); - backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); } -static void ggml_cl_fill(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - - UNUSED(src0); - UNUSED(src1); +static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { + GGML_ASSERT(gn_tensor && mul_tensor && add_tensor); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const ggml_tensor * src0 = gn_tensor->src[0]; + const ggml_tensor * src1 = mul_tensor->src[0] == gn_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; + const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; + const ggml_tensor * dst = add_tensor; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - float v = 0.0f; - memcpy(&v, ((int32_t *) dst->op_params), sizeof(float)); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - const int64_t n = ggml_nelements(dst); + int groups; + float eps; + memcpy(&groups, gn_tensor->op_params, sizeof(int)); + memcpy(&eps, (char *)gn_tensor->op_params + sizeof(int), sizeof(float)); - cl_kernel kernel = backend_ctx->kernel_fill; + cl_kernel kernel = backend_ctx->kernel_group_norm_mul_add; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + int ne = ggml_nelements(src0); + int group_size = ne / groups; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(float), &v)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(float), &n)); + size_t lws[] = { (size_t)MIN(max_workgroup_size, group_size) }; + size_t gws[] = { (size_t)groups * lws[0] }; - size_t local_work_size[1] = { 256 }; - size_t global_work_size[1] = { ((size_t)n + local_work_size[0] - 1) / local_work_size[0] * local_work_size[0] }; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &group_size)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(float), &eps)); - backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, gws, lws, dst); } -static void ggml_cl_clamp(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_group_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -15134,74 +19622,41 @@ static void ggml_cl_clamp(ggml_backend_t backend, const ggml_tensor * src0, cons cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - float min; - float max; - memcpy(&min, ((int32_t *) dst->op_params) + 0, sizeof(float)); - memcpy(&max, ((int32_t *) dst->op_params) + 1, sizeof(float)); - - if (!ggml_is_contiguous(src0)) { - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; - - cl_kernel kernel = backend_ctx->kernel_clamp_nc; + int32_t n_groups = ((const int32_t *) dst->op_params)[0]; + int32_t group_size = src0->ne[0] * src0->ne[1] * ((src0->ne[2] + n_groups - 1) / n_groups); + float eps = ((const float *) dst->op_params)[1]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(float), &min)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(float), &max)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb3)); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne = ne00*ne01*ne02; - const int nth = 64; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + cl_kernel kernel = backend_ctx->kernel_group_norm; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + size_t sgs = 64; + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; + } else { + GGML_ASSERT(false && "Unsupported GPU"); } - cl_kernel kernel = backend_ctx->kernel_clamp; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(float), &min)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(float), &max)); - - const int64_t n = ggml_nelements(dst); - - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &group_size)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(float), &eps)); - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. - } + size_t global_work_size[] = {(size_t)n_groups*sgs, 1, 1}; + size_t local_work_size[] = {(size_t)sgs, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_l2_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -15223,12 +19678,21 @@ static void ggml_cl_norm(ggml_backend_t backend, const ggml_tensor * src0, const GGML_TENSOR_LOCALS(int, ne0, src0, ne); GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - int nth = 1; - while (nth < ne00 && nth < 64) { - nth *= 2; + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; + } else { + GGML_ASSERT(false && "Unsupported GPU"); } - cl_kernel kernel = backend_ctx->kernel_norm; + cl_kernel kernel = backend_ctx->kernel_l2_norm_f32; + + int nth = sgs; + while (nth < ne00 && nth < (int)backend_ctx->get_kernel_workgroup_size(kernel)) { + nth *= 2; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -15238,12 +19702,11 @@ static void ggml_cl_norm(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &eps)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float)*nth, NULL)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float)*nth/sgs, NULL)); size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {(size_t)nth, 1, 1}; @@ -15251,7 +19714,7 @@ static void ggml_cl_norm(ggml_backend_t backend, const ggml_tensor * src0, const backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } -static void ggml_cl_rms_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -15261,317 +19724,353 @@ static void ggml_cl_rms_norm(ggml_backend_t backend, const ggml_tensor * src0, c ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - //ggml_backend_opencl_device_context * dev_ctx = - // (ggml_backend_opencl_device_context *)backend->device->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - float eps; - memcpy(&eps, dst->op_params, sizeof(float)); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const int ne00 = src0 ? src0->ne[0] : 0; - const int ne01 = src0 ? src0->ne[1] : 0; - const int ne02 = src0 ? src0->ne[2] : 0; - const int ne03 = src0 ? src0->ne[3] : 0; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb01 = src0 ? src0->nb[1] : 0; - const cl_ulong nb02 = src0 ? src0->nb[2] : 0; - const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - GGML_ASSERT(ne00 % 4 == 0); + cl_kernel kernel; - const int nth = 64; + if (ggml_is_contiguous(src0)) { + // Handle contiguous input + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_tanh_f32_4; + } else { + kernel = backend_ctx->kernel_tanh_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_tanh_f32; + } else { + kernel = backend_ctx->kernel_tanh_f16; + } + } - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - cl_kernel kernel = backend_ctx->kernel_rms_norm; + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - // Note, this kernel declares local memory in kernel args and the size - // depends on subgroup size. - // Note, this requires OpenCL 2.1 and above - // For now we use fixed subgroup size to simplify support for OpenCL 2.0. - size_t sgs; - //CL_CHECK(clGetKernelSubGroupInfo(kernel, dev_ctx->device, - // CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE, - // sizeof(local_work_size), local_work_size, - // sizeof(size_t), &sgs, NULL)); - if (backend_ctx->gpu_family == ADRENO) { - sgs = 64; - } else if (backend_ctx->gpu_family == INTEL) { - sgs = 32; - } else { - GGML_ASSERT(false && "Unsupported GPU"); - } + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(float), &eps)); - // This is local memory - the size depends on subgroup size. - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float)*nth/sgs, NULL)); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + } else { + // Handle non-contiguous input + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_tanh_f32_nc; + } else { + kernel = backend_ctx->kernel_tanh_f16_nc; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); -} + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); -static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor) { - GGML_ASSERT(mul_tensor); - GGML_ASSERT(rms_norm_tensor); + int nth = 64; - // src0 is the src of rms_norm, src1 is the other src of mul (one being rms_norm) - const ggml_tensor * src0 = rms_norm_tensor->src[0]; - const ggml_tensor * src1; - if (mul_tensor->src[0] == rms_norm_tensor) { - src1 = mul_tensor->src[1]; - } else if (mul_tensor->src[1] == rms_norm_tensor) { - src1 = mul_tensor->src[0]; - } else { - GGML_ASSERT(false && "Invalid args for rms_norm and mul"); + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } - const ggml_tensor * dst = mul_tensor; +} +static void ggml_cl_neg(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + UNUSED(src1); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - float eps; - memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; - - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + GGML_TENSOR_LOCALS(int, ne, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - const int ne13 = src1->ne[3]; + cl_kernel kernel; - const cl_ulong nb11 = src1->nb[1]; - const cl_ulong nb12 = src1->nb[2]; - const cl_ulong nb13 = src1->nb[3]; + if (ggml_is_contiguous(src0)) { + // Handle contiguous input + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_neg_f32_4; + } else { + kernel = backend_ctx->kernel_neg_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_neg_f32; + } else { + kernel = backend_ctx->kernel_neg_f16; + } + } - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &n)); - GGML_ASSERT(ne00 % 4 == 0); + size_t global_work_size[] = {(size_t)CEIL_DIV(n, 64)*64, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - size_t sgs; - if (backend_ctx->gpu_family == ADRENO) { - sgs = 64; - } else if (backend_ctx->gpu_family == INTEL) { - sgs = 32; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } else { - GGML_ASSERT(false && "Unsupported GPU"); - } - - cl_kernel kernel = backend_ctx->kernel_rms_norm_mul; + // Handle non-contiguous input + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_neg_f32_nc; + } else { + kernel = backend_ctx->kernel_neg_f16_nc; + } - int nth = sgs; - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - while (nth < ne00 && nth < max_workgroup_size) { - nth *= 2; - } - nth = MIN(nth, max_workgroup_size); - nth = MIN(nth, ne00); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + int nth = 64; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &eps)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float)*sgs, NULL)); + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { - GGML_ASSERT(norm_tensor && mul_tensor && add_tensor); +static void ggml_cl_exp(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - const ggml_tensor * src0 = norm_tensor->src[0]; - const ggml_tensor * src1 = mul_tensor->src[0] == norm_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; - const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; - const ggml_tensor * dst = add_tensor; + UNUSED(src1); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + GGML_TENSOR_LOCALS(int, ne, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); - float eps; - memcpy(&eps, norm_tensor->op_params, sizeof(float)); + cl_kernel kernel; - const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; - const cl_ulong nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; - const int ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3]; - const cl_ulong nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; - const int ne20 = src2->ne[0], ne21 = src2->ne[1], ne22 = src2->ne[2], ne23 = src2->ne[3]; - const cl_ulong nb21 = src2->nb[1], nb22 = src2->nb[2], nb23 = src2->nb[3]; - const cl_ulong nbd1 = dst->nb[1], nbd2 = dst->nb[2], nbd3 = dst->nb[3]; + if (ggml_is_contiguous(src0)) { + // Handle contiguous input + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_exp_f32_4; + } else { + kernel = backend_ctx->kernel_exp_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_exp_f32; + } else { + kernel = backend_ctx->kernel_exp_f16; + } + } - size_t sgs; - if (backend_ctx->gpu_family == ADRENO) sgs = 64; - else if (backend_ctx->gpu_family == INTEL) sgs = 32; - else GGML_ASSERT(false && "Unsupported GPU"); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &n)); - cl_kernel kernel = backend_ctx->kernel_norm_mul_add; + size_t global_work_size[] = {(size_t)CEIL_DIV(n, 64)*64, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; - int nth = sgs; - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - while (nth < ne00/4 && nth < max_workgroup_size) nth *= 2; - nth = MIN(nth, max_workgroup_size); - nth = MIN(nth, ne00/4); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } else { + // Handle non-contiguous input + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_exp_f32_nc; + } else { + kernel = backend_ctx->kernel_exp_f16_nc; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - size_t gws[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t lws[] = {(size_t)nth, 1, 1}; - size_t num_subgroups = (nth + sgs - 1) / sgs; + int nth = 64; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne20)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne21)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne22)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne23)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb21)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb22)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb23)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nbd1)); - CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &nbd2)); - CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nbd3)); - CL_CHECK(clSetKernelArg(kernel, 32, sizeof(float), &eps)); - CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_float2) * num_subgroups, NULL)); + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { - GGML_ASSERT(gn_tensor && mul_tensor && add_tensor); +static void ggml_cl_expm1(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - const ggml_tensor * src0 = gn_tensor->src[0]; - const ggml_tensor * src1 = mul_tensor->src[0] == gn_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; - const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; - const ggml_tensor * dst = add_tensor; + UNUSED(src1); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - int groups; - float eps; - memcpy(&groups, gn_tensor->op_params, sizeof(int)); - memcpy(&eps, (char *)gn_tensor->op_params + sizeof(int), sizeof(float)); + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - cl_kernel kernel = backend_ctx->kernel_group_norm_mul_add; - int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); - int ne = ggml_nelements(src0); - int group_size = ne / groups; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - size_t lws[] = { (size_t)MIN(max_workgroup_size, group_size) }; - size_t gws[] = { (size_t)groups * lws[0] }; + cl_kernel kernel; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &group_size)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(float), &eps)); + if (ggml_is_contiguous(src0)) { + // Handle contiguous input + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_expm1_f32_4; + } else { + kernel = backend_ctx->kernel_expm1_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_expm1_f32; + } else { + kernel = backend_ctx->kernel_expm1_f16; + } + } - backend_ctx->enqueue_ndrange_kernel(kernel, 1, gws, lws, dst); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + } else { + // Handle non-contiguous input + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_expm1_f32_nc; + } else { + kernel = backend_ctx->kernel_expm1_f16_nc; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); + + int nth = 64; + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_cl_group_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_abs(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -15587,48 +20086,97 @@ static void ggml_cl_group_norm(ggml_backend_t backend, const ggml_tensor * src0, cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - int32_t n_groups = ((const int32_t *) dst->op_params)[0]; - int32_t group_size = src0->ne[0] * src0->ne[1] * ((src0->ne[2] + n_groups - 1) / n_groups); - float eps = ((const float *) dst->op_params)[1]; - const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; - const int ne = ne00*ne01*ne02; + const int ne03 = src0->ne[3]; - cl_kernel kernel = backend_ctx->kernel_group_norm; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - size_t sgs = 64; - if (backend_ctx->gpu_family == ADRENO) { - sgs = 64; - } else if (backend_ctx->gpu_family == INTEL) { - sgs = 32; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; + + cl_kernel kernel; + + if (ggml_is_contiguous(src0)) { + // Handle contiguous input + int n = ggml_nelements(dst); + if (n % 4 == 0) { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_abs_f32_4; + } else { + kernel = backend_ctx->kernel_abs_f16_4; + } + n /= 4; + } else { + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_abs_f32; + } else { + kernel = backend_ctx->kernel_abs_f16; + } + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } else { - GGML_ASSERT(false && "Unsupported GPU"); - } + // Handle non-contiguous input + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_abs_f32_nc; + } else { + kernel = backend_ctx->kernel_abs_f16_nc; + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &group_size)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - size_t global_work_size[] = {(size_t)n_groups*sgs, 1, 1}; - size_t local_work_size[] = {(size_t)sgs, 1, 1}; + int nth = 64; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } } -static void ggml_cl_l2_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +// Shared driver for the extended unary ops (unary_ext.cl), same selection as +// ggml_cl_abs: contiguous picks the vec4 kernel when the element count is a +// multiple of 4 (else scalar); non-contiguous uses the stride-addressed kernel. +static void ggml_cl_unary_ext(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst, + cl_kernel k_f32, cl_kernel k_f32_4, cl_kernel k_f32_nc, + cl_kernel k_f16, cl_kernel k_f16_4, cl_kernel k_f16_nc) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - UNUSED(src1); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; @@ -15637,49 +20185,79 @@ static void ggml_cl_l2_norm(ggml_backend_t backend, const ggml_tensor * src0, co cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - float eps; - memcpy(&eps, dst->op_params, sizeof(float)); + const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; + const cl_ulong nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; + const cl_ulong nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3]; - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + const bool is_f16 = (src0->type == GGML_TYPE_F16); + cl_kernel kernel; - size_t sgs; - if (backend_ctx->gpu_family == ADRENO) { - sgs = 64; - } else if (backend_ctx->gpu_family == INTEL) { - sgs = 32; + if (ggml_is_contiguous(src0)) { + int n = ggml_nelements(dst); + if (n % 4 == 0) { + kernel = is_f16 ? k_f16_4 : k_f32_4; + n /= 4; + } else { + kernel = is_f16 ? k_f16 : k_f32; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + + size_t global_work_size[] = {(size_t)n, 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + size_t * local_work_size_ptr = local_work_size; + if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; + } + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } else { - GGML_ASSERT(false && "Unsupported GPU"); - } + kernel = is_f16 ? k_f16_nc : k_f32_nc; - cl_kernel kernel = backend_ctx->kernel_l2_norm_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - int nth = sgs; - while (nth < ne00 && nth < (int)backend_ctx->get_kernel_workgroup_size(kernel)) { - nth *= 2; + int nth = 64; + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } +} - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(float), &eps)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float)*nth/sgs, NULL)); +#define GGML_CL_UNARY_EXT_WRAP(FN, OP) \ +static void FN(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { \ + UNUSED(src1); \ + ggml_backend_opencl_context *c = (ggml_backend_opencl_context *)backend->context; \ + ggml_cl_unary_ext(backend, src0, dst, c->kernel_##OP##_f32, c->kernel_##OP##_f32_4, c->kernel_##OP##_f32_nc, \ + c->kernel_##OP##_f16, c->kernel_##OP##_f16_4, c->kernel_##OP##_f16_nc); \ +} - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; +GGML_CL_UNARY_EXT_WRAP(ggml_cl_sgn, sgn) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_step, step) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_elu, elu) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_hardswish, hardswish) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_hardsigmoid, hardsigmoid) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_floor, floor) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_ceil, ceil) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_round, round) +GGML_CL_UNARY_EXT_WRAP(ggml_cl_trunc, trunc) - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); -} +#undef GGML_CL_UNARY_EXT_WRAP -static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_softplus(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); @@ -15705,10 +20283,10 @@ static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const const cl_ulong nb02 = src0->nb[2]; const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; cl_kernel kernel; @@ -15717,16 +20295,16 @@ static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const int n = ggml_nelements(dst); if (n % 4 == 0) { if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_tanh_f32_4; + kernel = backend_ctx->kernel_softplus_f32_4; } else { - kernel = backend_ctx->kernel_tanh_f16_4; + kernel = backend_ctx->kernel_softplus_f16_4; } n /= 4; } else { if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_tanh_f32; + kernel = backend_ctx->kernel_softplus_f32; } else { - kernel = backend_ctx->kernel_tanh_f16; + kernel = backend_ctx->kernel_softplus_f16; } } @@ -15747,9 +20325,9 @@ static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const } else { // Handle non-contiguous input if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_tanh_f32_nc; + kernel = backend_ctx->kernel_softplus_f32_nc; } else { - kernel = backend_ctx->kernel_tanh_f16_nc; + kernel = backend_ctx->kernel_softplus_f16_nc; } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); @@ -15766,3758 +20344,4463 @@ static void ggml_cl_tanh(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - int nth = 64; + int nth = 64; + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } +} + +static void ggml_cl_repeat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1_shape_def, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + GGML_ASSERT(dst->type == src0->type); + + UNUSED(src1_shape_def); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; + + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; + + cl_kernel kernel = backend_ctx->kernel_repeat_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb3)); + + int nth = 64; + + size_t global_work_size[] = {(size_t)ne1*nth, (size_t)ne2, (size_t)ne3}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_cl_pad(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + if (backend_ctx->kernel_pad == nullptr) { + GGML_LOG_WARN("%s: pad kernel not available, skipping OpenCL execution.\n", __func__); + return; + } + + ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong off_src0 = extra_src0->offset + src0->view_offs; + cl_ulong off_dst = extra_dst->offset + dst->view_offs; + + const int s_ne0 = src0->ne[0]; + const int s_ne1 = src0->ne[1]; + const int s_ne2 = src0->ne[2]; + const int s_ne3 = src0->ne[3]; + + const int s_nb0 = src0->nb[0]; + const int s_nb1 = src0->nb[1]; + const int s_nb2 = src0->nb[2]; + const int s_nb3 = src0->nb[3]; + + const int d_ne0 = dst->ne[0]; + const int d_ne1 = dst->ne[1]; + const int d_ne2 = dst->ne[2]; + const int d_ne3 = dst->ne[3]; + + const int d_nb0 = dst->nb[0]; + const int d_nb1 = dst->nb[1]; + const int d_nb2 = dst->nb[2]; + const int d_nb3 = dst->nb[3]; + + const int lp0 = ((const int*)(dst->op_params))[0]; + const int rp0 = ((const int*)(dst->op_params))[1]; + const int lp1 = ((const int*)(dst->op_params))[2]; + const int rp1 = ((const int*)(dst->op_params))[3]; + const int lp2 = ((const int*)(dst->op_params))[4]; + const int rp2 = ((const int*)(dst->op_params))[5]; + const int lp3 = ((const int*)(dst->op_params))[6]; + const int rp3 = ((const int*)(dst->op_params))[7]; + + cl_kernel kernel = backend_ctx->kernel_pad; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &s_ne0)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &s_ne1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &s_ne2)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &s_ne3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &s_nb0)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &s_nb1)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &s_nb2)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &s_nb3)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &d_ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &d_ne1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &d_ne2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &d_ne3)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &d_nb0)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &d_nb1)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &d_nb2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &d_nb3)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &lp0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &rp0)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &lp1)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &rp1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &lp2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &rp2)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(int), &lp3)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(int), &rp3)); + + size_t lws0 = 64; + size_t gws0 = (( (size_t)d_ne0 + lws0 - 1 ) / lws0) * lws0; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + size_t global_work_size[] = { gws0, (size_t)d_ne1, (size_t)d_ne2*d_ne3 }; + size_t local_work_size[] = { lws0, 1, 1 }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t * local_work_size_ptr = local_work_size; + if (d_ne0 % lws0 != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_neg(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_upscale(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - - UNUSED(src1); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const int mode_flags = (ggml_scale_mode) ggml_get_op_params_i32(dst, 0); + const ggml_scale_mode mode = (ggml_scale_mode) (mode_flags & 0xFF); + cl_kernel kernel = nullptr; - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + if (mode == GGML_SCALE_MODE_NEAREST) { + kernel = backend_ctx->kernel_upscale; + if (kernel == nullptr) { + GGML_LOG_WARN("%s: nearest upscale kernel not available, skipping OpenCL execution.\n", __func__); + return; + } + } else if (mode == GGML_SCALE_MODE_BILINEAR) { + kernel = backend_ctx->kernel_upscale_bilinear; + if (kernel == nullptr) { + GGML_LOG_WARN("%s: bilinear upscale kernel not available, skipping OpenCL execution.\n", __func__); + return; + } + } else { + GGML_LOG_WARN("%s: unsupported upscale mode %d, skipping OpenCL execution.\n", __func__, mode); + return; + } - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - GGML_TENSOR_LOCALS(int, ne, dst, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); + ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; - cl_kernel kernel; + cl_ulong off_src0 = extra_src0->offset + src0->view_offs; + cl_ulong off_dst = extra_dst->offset + dst->view_offs; - if (ggml_is_contiguous(src0)) { - // Handle contiguous input - int n = ggml_nelements(dst); - if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_neg_f32_4; - } else { - kernel = backend_ctx->kernel_neg_f16_4; - } - n /= 4; - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_neg_f32; - } else { - kernel = backend_ctx->kernel_neg_f16; - } - } + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &n)); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - size_t global_work_size[] = {(size_t)CEIL_DIV(n, 64)*64, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } else { - // Handle non-contiguous input - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_neg_f32_nc; - } else { - kernel = backend_ctx->kernel_neg_f16_nc; + float sf0 = (float)ne0 / ne00; + float sf1 = (float)ne1 / ne01; + float sf2 = (float)ne2 / ne02; + float sf3 = (float)ne3 / ne03; + + float pixel_offset = 0.5f; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb03)); + + if (mode == GGML_SCALE_MODE_NEAREST) { + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &sf0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float), &sf1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(float), &sf2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(float), &sf3)); + } else if (mode == GGML_SCALE_MODE_BILINEAR) { + if (mode_flags & GGML_SCALE_FLAG_ALIGN_CORNERS) { + sf0 = ne0 > 1 && ne00 > 1 ? (float)(ne0 - 1) / (ne00 - 1) : sf0; + sf1 = ne1 > 1 && ne01 > 1 ? (float)(ne1 - 1) / (ne01 - 1) : sf1; + pixel_offset = 0.0f; } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(float), &sf0)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(float), &sf1)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(float), &sf2)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(float), &sf3)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(float), &pixel_offset)); + } - int nth = 64; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + size_t dst_total_elements = (size_t)ne0 * ne1 * ne2 * ne3; + if (dst_total_elements == 0) { + return; + } + size_t global_work_size[] = { dst_total_elements, 1, 1 }; + size_t local_work_size_pref = 256; + size_t local_work_size[] = { MIN(local_work_size_pref, dst_total_elements), 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t * local_work_size_ptr = local_work_size; + if (dst_total_elements % local_work_size[0] != 0 && !backend_ctx->non_uniform_workgroups) { + local_work_size_ptr = nullptr; } + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); } -static void ggml_cl_exp(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_concat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - - UNUSED(src1); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - GGML_TENSOR_LOCALS(int, ne, dst, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - cl_kernel kernel; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - if (ggml_is_contiguous(src0)) { - // Handle contiguous input - int n = ggml_nelements(dst); - if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_exp_f32_4; - } else { - kernel = backend_ctx->kernel_exp_f16_4; - } - n /= 4; - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_exp_f32; - } else { - kernel = backend_ctx->kernel_exp_f16; - } - } + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &n)); + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; - size_t global_work_size[] = {(size_t)CEIL_DIV(n, 64)*64, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + const cl_int dim = ((const int32_t *) dst->op_params)[0]; + GGML_ASSERT(dim >= 0 && dim <= 3); + + int nth = MIN(64, ne0); + + const size_t ts = ggml_type_size(dst->type); + // the pack kernel copies 4-byte elements, so it is only valid for those. + const bool concat_pack = (dim == 0 && ne0 < 32 && ts == 4); + cl_kernel kernel; + if (concat_pack) { + kernel = backend_ctx->kernel_concat_b4_pack; } else { - // Handle non-contiguous input - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_exp_f32_nc; - } else { - kernel = backend_ctx->kernel_exp_f16_nc; + switch (ts) { + case 1: kernel = backend_ctx->kernel_concat_b1; break; + case 2: kernel = backend_ctx->kernel_concat_b2; break; + case 4: kernel = backend_ctx->kernel_concat_b4; break; + case 8: kernel = backend_ctx->kernel_concat_b8; break; + default: GGML_ABORT("unsupported concat element size: %zu", ts); } + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_int), &dim)); - int nth = 64; + if (concat_pack) { + // packed kernel needs the dst dims to unflatten its 1-D row index. + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(int), &ne3)); - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + const int maxwg = (int)backend_ctx->get_kernel_workgroup_size(kernel); + const int base = MIN(64, maxwg); + const int tpr = MIN(ne0, base); // threads per row + const int rpw = MAX(1, base / tpr); // rows per workgroup + const int lsz = tpr * rpw; + const int nrows = ne1*ne2*ne3; + const int nwg = (nrows + rpw - 1) / rpw; + size_t global_work_size[] = {(size_t)nwg*lsz, 1, 1}; + size_t local_work_size[] = {(size_t)lsz, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); + } else { + size_t global_work_size[] = {(size_t)ne1*nth, (size_t)ne2, (size_t)ne3}; size_t local_work_size[] = {(size_t)nth, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } } -static void ggml_cl_expm1(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_timestep_embedding(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - - UNUSED(src1); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + if (backend_ctx->kernel_timestep_embedding == nullptr) { + GGML_LOG_WARN("%s: timestep_embedding kernel not available, skipping OpenCL execution.\n", __func__); + return; + } - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + cl_ulong off_src0 = extra_src0->offset + src0->view_offs; + cl_ulong off_dst = extra_dst->offset + dst->view_offs; - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + const int logical_dim = dst->op_params[0]; + const int max_period = dst->op_params[1]; + const int dst_nb1_bytes = dst->nb[1]; - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + cl_kernel kernel = backend_ctx->kernel_timestep_embedding; - cl_kernel kernel; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &dst_nb1_bytes)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &logical_dim)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &max_period)); - if (ggml_is_contiguous(src0)) { - // Handle contiguous input - int n = ggml_nelements(dst); - if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_expm1_f32_4; - } else { - kernel = backend_ctx->kernel_expm1_f16_4; - } - n /= 4; - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_expm1_f32; - } else { - kernel = backend_ctx->kernel_expm1_f16; - } - } + size_t gws0 = (size_t)(((logical_dim + 1) / 2) + 1); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + size_t gws1 = (size_t)src0->ne[0]; - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + size_t global_work_size[] = {gws0, gws1, 1}; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, NULL, dst); +} - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); - } else { - // Handle non-contiguous input - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_expm1_f32_nc; - } else { - kernel = backend_ctx->kernel_expm1_f16_nc; +struct ggml_cl_flash_attn_temp_buffer { + cl_mem data = nullptr; + + ~ggml_cl_flash_attn_temp_buffer() { + if (data != nullptr) { + CL_CHECK(clReleaseMemObject(data)); + data = nullptr; } + } +}; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); +// Resolve the source buffer + strides for an FA KV tensor: keep the +// caller-supplied AoS buffer if non-NULL, else fall back to tensor->extra. +static void ggml_cl_flash_attn_resolve_src( + const ggml_tensor * tensor, + cl_mem & buf, + cl_ulong & offset, + cl_ulong & nb1, + cl_ulong & nb2, + cl_ulong & nb3) { + if (buf != NULL) { + return; + } + ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra && extra->data_device); + buf = extra->data_device; + offset = extra->offset + tensor->view_offs; + nb1 = tensor->nb[1]; + nb2 = tensor->nb[2]; + nb3 = tensor->nb[3]; +} - int nth = 64; +// Read a (possibly strided-view) tensor from device into a tight host buffer. +// dim 0 is always tight; a strided view is gathered row-by-row. +static void ggml_cl_flash_attn_read_tensor_host( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + cl_mem src_buffer, cl_ulong src_offset, + cl_ulong src_nb1, cl_ulong src_nb2, cl_ulong src_nb3, + size_t row_bytes, void * dst, size_t total_bytes +) { + const bool contiguous_layout = + src_nb1 == row_bytes && + src_nb2 == row_bytes * (cl_ulong) tensor->ne[1] && + src_nb3 == src_nb2 * (cl_ulong) tensor->ne[2]; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + if (contiguous_layout) { + CL_CHECK(clEnqueueReadBuffer(backend_ctx->queue, src_buffer, CL_TRUE, + src_offset, total_bytes, dst, 0, NULL, NULL)); + return; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + size_t dst_off = 0; + for (int64_t i3 = 0; i3 < tensor->ne[3]; ++i3) { + for (int64_t i2 = 0; i2 < tensor->ne[2]; ++i2) { + for (int64_t i1 = 0; i1 < tensor->ne[1]; ++i1) { + const cl_ulong row_src_off = src_offset + + (cl_ulong) i3 * src_nb3 + + (cl_ulong) i2 * src_nb2 + + (cl_ulong) i1 * src_nb1; + CL_CHECK(clEnqueueReadBuffer(backend_ctx->queue, src_buffer, CL_TRUE, + row_src_off, row_bytes, + (uint8_t *) dst + dst_off, 0, NULL, NULL)); + dst_off += row_bytes; + } + } + } + GGML_ASSERT(dst_off == total_bytes); +} + +// forward decl: used by the FA decode dispatch (K-image variant) below. +static cl_mem ggml_cl_img_pool_get_or_create( + ggml_backend_opencl_context * backend_ctx, + std::map & pool, + cl_mem data_device, + cl_ulong offset0, + size_t required_bytes, + cl_channel_type channel_data_type); + +// Rebuild AoS q8_0/q4_0 bytes from a SoA tensor into a temp buffer. +// Returns false if the tensor is not SoA-quantised (already AoS). +static bool ggml_cl_flash_attn_reconstruct_aos( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + ggml_cl_flash_attn_temp_buffer & temp, + cl_mem & out_buf, + cl_ulong & out_offset, + cl_ulong & out_nb1, + cl_ulong & out_nb2, + cl_ulong & out_nb3 +) { + if (tensor == nullptr) { + return false; + } + const bool is_q8_0 = tensor->type == GGML_TYPE_Q8_0 && ggml_cl_is_q8_0_soa(tensor); + const bool is_q4_0 = tensor->type == GGML_TYPE_Q4_0 && ggml_cl_is_q4_0_soa(tensor); + if (!is_q8_0 && !is_q4_0) { + return false; } -} - -static void ggml_cl_abs(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - - UNUSED(src1); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + // For views, SoA extra is on view_src (view->extra is pre-SoA). + // Noshuffle layout only applies to 2D weights, as determined by `use_adreno_kernels`, + // where ne2 == 1 and ne3 == 1 -- these are never FA inputs. + // Therefore, we use `restore_block_qk_0` kernels, not `restore_block_qk_0_noshuffle`. + const ggml_tensor * soa_src = tensor->view_src ? tensor->view_src : tensor; + cl_mem extra_q = NULL; + cl_mem extra_d = NULL; + if (is_q8_0) { + auto * e = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; + GGML_ASSERT(e && e->q && e->d); + extra_q = e->q; + extra_d = e->d; + } else { + auto * e = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; + GGML_ASSERT(e && e->q && e->d); + extra_q = e->q; + extra_d = e->d; + } - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + // Reconstruct the whole parent; view offsets then work naturally. + const size_t parent_nbytes = ggml_nbytes(soa_src); + cl_int err; + temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, parent_nbytes, NULL, &err); + CL_CHECK(err); - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + cl_kernel kernel = is_q8_0 ? backend_ctx->kernel_restore_block_q8_0 + : backend_ctx->kernel_restore_block_q4_0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra_d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &temp.data)); - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + const size_t n_blocks = (size_t) ggml_nelements(soa_src) / ggml_blck_size(soa_src->type); + size_t global_work_size[] = { n_blocks, 1, 1 }; + size_t local_work_size[] = { 1, 1, 1 }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, + global_work_size, local_work_size, 0, NULL, NULL)); - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + out_buf = temp.data; + out_offset = tensor->view_offs; + out_nb1 = tensor->nb[1]; + out_nb2 = tensor->nb[2]; + out_nb3 = tensor->nb[3]; + return true; +} - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; +// GPU dequant of a contiguous q4_0/q8_0 KV tensor to f16/f32. Caller supplies +// src_buf when reconstructing from SoA. Returns false for non-contig layouts +// (the kernel indexes blocks tightly within ne[0]) so the caller can fall back +// to the host path. +static bool ggml_cl_flash_attn_dequant_kv_gpu( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + ggml_type target_type, + cl_mem in_src_buf, + cl_ulong in_src_offset, + cl_ulong in_src_nb1, + cl_ulong in_src_nb2, + cl_ulong in_src_nb3, + ggml_cl_flash_attn_temp_buffer & temp, + cl_mem & out_buf, + cl_ulong & out_offset, + cl_ulong & out_nb1, + cl_ulong & out_nb2, + cl_ulong & out_nb3 +) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q8_0 || tensor->type == GGML_TYPE_Q4_0); + GGML_ASSERT(target_type == GGML_TYPE_F16 || target_type == GGML_TYPE_F32); - cl_kernel kernel; + const bool is_q8_0 = tensor->type == GGML_TYPE_Q8_0; - if (ggml_is_contiguous(src0)) { - // Handle contiguous input - int n = ggml_nelements(dst); - if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_abs_f32_4; - } else { - kernel = backend_ctx->kernel_abs_f16_4; - } - n /= 4; - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_abs_f32; - } else { - kernel = backend_ctx->kernel_abs_f16; - } - } + cl_mem src_buf = in_src_buf; + cl_ulong src_offset = in_src_offset; + cl_ulong src_nb1 = in_src_nb1; + cl_ulong src_nb2 = in_src_nb2; + cl_ulong src_nb3 = in_src_nb3; + ggml_cl_flash_attn_resolve_src(tensor, src_buf, src_offset, src_nb1, src_nb2, src_nb3); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + if (tensor->nb[0] != (cl_ulong) ggml_type_size(tensor->type)) { + return false; + } - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; + const size_t n_blocks = (size_t) ggml_nelements(tensor) / 32; // block size is 32 + const size_t elem_size = ggml_type_size(target_type); + const size_t out_bytes = n_blocks * 32 * elem_size; + const cl_int nblk0_arg = (cl_int) (tensor->ne[0] / 32); + const cl_int ne1_arg = (cl_int) tensor->ne[1]; + const cl_int ne2_arg = (cl_int) tensor->ne[2]; + const cl_int ne3_arg = (cl_int) tensor->ne[3]; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } + cl_int err; + temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, out_bytes, NULL, &err); + CL_CHECK(err); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + cl_kernel kernel; + if (target_type == GGML_TYPE_F16) { + kernel = is_q8_0 ? backend_ctx->kernel_dequant_q8_0_f16_view_aos + : backend_ctx->kernel_dequant_q4_0_f16_view_aos; } else { - // Handle non-contiguous input - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_abs_f32_nc; - } else { - kernel = backend_ctx->kernel_abs_f16_nc; - } - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); - - int nth = 64; - - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + kernel = is_q8_0 ? backend_ctx->kernel_dequant_q8_0_f32_view_aos + : backend_ctx->kernel_dequant_q4_0_f32_view_aos; } -} -// Shared driver for the extended unary ops (unary_ext.cl), same selection as -// ggml_cl_abs: contiguous picks the vec4 kernel when the element count is a -// multiple of 4 (else scalar); non-contiguous uses the stride-addressed kernel. -static void ggml_cl_unary_ext(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst, - cl_kernel k_f32, cl_kernel k_f32_4, cl_kernel k_f32_nc, - cl_kernel k_f16, cl_kernel k_f16_4, cl_kernel k_f16_nc) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &src_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &src_offset)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &src_nb1)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &src_nb2)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &src_nb3)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &nblk0_arg)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne1_arg)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne2_arg)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne3_arg)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_mem), &temp.data)); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + size_t global_ws[3] = { (size_t) nblk0_arg, (size_t) ne1_arg, (size_t) ne2_arg * (size_t) ne3_arg }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, + global_ws, NULL, 0, NULL, NULL)); - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + out_buf = temp.data; + out_offset = 0; + out_nb1 = (cl_ulong) tensor->ne[0] * elem_size; + out_nb2 = out_nb1 * (cl_ulong) tensor->ne[1]; + out_nb3 = out_nb2 * (cl_ulong) tensor->ne[2]; + return true; +} - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; +static bool ggml_cl_flash_attn_prepare_quantized_tensor( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + ggml_type target_type, + ggml_cl_flash_attn_temp_buffer & temp, + cl_mem & data_device, + cl_ulong & offset, + cl_ulong & nb1, + cl_ulong & nb2, + cl_ulong & nb3 +) { + if (!ggml_is_quantized(tensor->type)) { + return false; + } - const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; - const cl_ulong nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; - const cl_ulong nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3]; + // Caller-supplied AoS buffer wins over tensor->extra when present. + cl_mem src_buffer = data_device; + cl_ulong src_offset = offset; + cl_ulong src_nb1 = nb1; + cl_ulong src_nb2 = nb2; + cl_ulong src_nb3 = nb3; + ggml_cl_flash_attn_resolve_src(tensor, src_buffer, src_offset, src_nb1, src_nb2, src_nb3); - const bool is_f16 = (src0->type == GGML_TYPE_F16); - cl_kernel kernel; + const int64_t n = ggml_nelements(tensor); + const size_t row_bytes = (size_t) (tensor->ne[0] / ggml_blck_size(tensor->type)) * ggml_type_size(tensor->type); + // tight-packed byte count (ggml_nbytes includes stride gaps). + const size_t total_bytes = (size_t) (n / ggml_blck_size(tensor->type)) * ggml_type_size(tensor->type); + std::vector host_quant(total_bytes); - if (ggml_is_contiguous(src0)) { - int n = ggml_nelements(dst); - if (n % 4 == 0) { - kernel = is_f16 ? k_f16_4 : k_f32_4; - n /= 4; - } else { - kernel = is_f16 ? k_f16 : k_f32; - } + sync_with_other_backends(backend_ctx); + ggml_cl_flash_attn_read_tensor_host(backend_ctx, tensor, src_buffer, src_offset, + src_nb1, src_nb2, src_nb3, + row_bytes, host_quant.data(), total_bytes); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + std::vector host_f32(n); + ggml_get_type_traits(tensor->type)->to_float(host_quant.data(), host_f32.data(), n); - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + const size_t bytes_per_elem = ggml_type_size(target_type); + const size_t buffer_size = (size_t) n * bytes_per_elem; + + std::vector host_linear(buffer_size); + if (target_type == GGML_TYPE_F32) { + memcpy(host_linear.data(), host_f32.data(), buffer_size); } else { - kernel = is_f16 ? k_f16_nc : k_f32_nc; + GGML_ASSERT(target_type == GGML_TYPE_F16); + ggml_fp32_to_fp16_row(host_f32.data(), (ggml_fp16_t *) host_linear.data(), n); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); + cl_int err; + temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, buffer_size, NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer(backend_ctx->queue, temp.data, CL_TRUE, 0, buffer_size, host_linear.data(), 0, NULL, NULL)); - int nth = 64; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + data_device = temp.data; + offset = 0; + nb1 = (cl_ulong) (tensor->ne[0] * bytes_per_elem); + nb2 = (cl_ulong) (tensor->ne[1] * nb1); + nb3 = (cl_ulong) (tensor->ne[2] * nb2); + + static bool warned = false; + if (!warned) { + GGML_LOG_WARN("ggml_opencl: OpenCL flash attention dequantizes GPU-resident quantized KV cache into temporary linear buffers; performance may be poor\n"); + warned = true; } -} -#define GGML_CL_UNARY_EXT_WRAP(FN, OP) \ -static void FN(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { \ - UNUSED(src1); \ - ggml_backend_opencl_context *c = (ggml_backend_opencl_context *)backend->context; \ - ggml_cl_unary_ext(backend, src0, dst, c->kernel_##OP##_f32, c->kernel_##OP##_f32_4, c->kernel_##OP##_f32_nc, \ - c->kernel_##OP##_f16, c->kernel_##OP##_f16_4, c->kernel_##OP##_f16_nc); \ + return true; } -GGML_CL_UNARY_EXT_WRAP(ggml_cl_sgn, sgn) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_step, step) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_elu, elu) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_hardswish, hardswish) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_hardsigmoid, hardsigmoid) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_floor, floor) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_ceil, ceil) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_round, round) -GGML_CL_UNARY_EXT_WRAP(ggml_cl_trunc, trunc) +// Host-side F16 -> F32 for the asymmetric-KV F32 fallback path. +static bool ggml_cl_flash_attn_convert_f16_to_f32( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + ggml_cl_flash_attn_temp_buffer & temp, + cl_mem & data_device, + cl_ulong & offset, + cl_ulong & nb1, + cl_ulong & nb2, + cl_ulong & nb3 +) { + if (tensor->type != GGML_TYPE_F16) { + return false; + } -#undef GGML_CL_UNARY_EXT_WRAP + cl_mem src_buffer = data_device; + cl_ulong src_offset = offset; + cl_ulong src_nb1 = nb1; + cl_ulong src_nb2 = nb2; + cl_ulong src_nb3 = nb3; + ggml_cl_flash_attn_resolve_src(tensor, src_buffer, src_offset, src_nb1, src_nb2, src_nb3); -static void ggml_cl_softplus(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); + const int64_t n = ggml_nelements(tensor); + const size_t row_bytes = (size_t) tensor->ne[0] * sizeof(ggml_fp16_t); + const size_t total_bytes = (size_t) n * sizeof(ggml_fp16_t); + std::vector host_f16(total_bytes); - UNUSED(src1); + sync_with_other_backends(backend_ctx); + ggml_cl_flash_attn_read_tensor_host(backend_ctx, tensor, src_buffer, src_offset, + src_nb1, src_nb2, src_nb3, + row_bytes, host_f16.data(), total_bytes); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + std::vector host_f32(n); + ggml_fp16_to_fp32_row((const ggml_fp16_t *) host_f16.data(), host_f32.data(), n); - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const size_t f32_bytes = (size_t) n * sizeof(float); + cl_int err; + temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, f32_bytes, NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer(backend_ctx->queue, temp.data, CL_TRUE, 0, + f32_bytes, host_f32.data(), 0, NULL, NULL)); - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + data_device = temp.data; + offset = 0; + nb1 = (cl_ulong) (tensor->ne[0] * sizeof(float)); + nb2 = (cl_ulong) (tensor->ne[1] * nb1); + nb3 = (cl_ulong) (tensor->ne[2] * nb2); - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + static bool warned = false; + if (!warned) { + GGML_LOG_WARN("ggml_opencl: OpenCL flash attention asymmetric KV converts an F16 cache to F32 host-side; performance may be poor\n"); + warned = true; + } - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + return true; +} - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; +// Flash-Decoding (K-split) dispatch thresholds. FD fires for non-causal +// attention with n_kv >= FD_MIN_N_KV and d_head <= FD_MAX_DK; the KV range is +// split into ~n_kv/FD_KV_PER_SPLIT partials, clamped to [FD_MIN_SPLITS, +// FD_MAX_SPLITS]. Multi-query FD is restricted to small heads +// (d_head <= FD_MAX_DK_MULTI) and capped at FD_MAX_N_Q_MULTI queries. +static constexpr int FD_MIN_N_KV = 2048; +static constexpr int FD_KV_PER_SPLIT = 2048; +// f16 KV decode wants more splits than the 2048 default; quantized KV keeps 2048. +static constexpr int FD_KV_PER_SPLIT_F16 = 512; +static constexpr int FD_MIN_SPLITS = 2; +static constexpr int FD_MAX_SPLITS = 16; +static constexpr int FD_MAX_DK = 128; +static constexpr int FD_MAX_DK_MULTI = 64; +static constexpr int FD_MAX_N_Q_MULTI = 8; +// MQ FD split-groups have few subgroups (MQ_NSG_SPLIT), so use a smaller +// kv_per_split to keep the softmax recurrence short; non-MQ keeps FD_KV_PER_SPLIT. +static constexpr int FD_MQ_KV_PER_SPLIT = 256; +static constexpr int FD_MQ_MAX_SPLITS = 128; - cl_kernel kernel; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +struct ggml_cl_adreno_xmem_attn_schedule { + int qk_lws0 = 256; + int qk_lws2 = 1; + int softmax_reduce_lws0 = 256; + int softmax_apply_lws0 = 64; + int softmax_apply_lws2 = 4; + int pv_lws0 = 64; + int pv_lws2 = 4; +}; - if (ggml_is_contiguous(src0)) { - // Handle contiguous input - int n = ggml_nelements(dst); - if (n % 4 == 0) { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_softplus_f32_4; - } else { - kernel = backend_ctx->kernel_softplus_f16_4; - } - n /= 4; - } else { - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_softplus_f32; - } else { - kernel = backend_ctx->kernel_softplus_f16; - } - } +static inline size_t ggml_cl_round_up(size_t x, size_t a) { + return ((x + a - 1) / a) * a; +} - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); +static inline int ggml_cl_round_up_div(int x, int y) { + return (x + y - 1) / y; +} - size_t global_work_size[] = {(size_t)n, 1, 1}; - size_t local_work_size[] = {64, 1, 1}; +static inline void ggml_cl_set_arg_int4(cl_kernel kernel, cl_uint index, int x, int y, int z, int w) { + struct { int x, y, z, w; } value { x, y, z, w }; + CL_CHECK(clSetKernelArg(kernel, index, sizeof(value), &value)); +} + +static cl_mem ggml_cl_make_image2d_half4(cl_context context, cl_mem_flags flags, size_t width, size_t height) { + cl_int err = CL_SUCCESS; + cl_image_format format = { CL_RGBA, CL_HALF_FLOAT }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE2D; + desc.image_width = width; + desc.image_height = height; + cl_mem image = clCreateImage(context, flags, &format, &desc, nullptr, &err); + CL_CHECK(err); + return image; +} + +static cl_mem ggml_cl_make_image1d_buffer_half4(cl_context context, cl_mem_flags flags, size_t width, cl_mem backing_buffer) { + cl_int err = CL_SUCCESS; + cl_image_format format = { CL_RGBA, CL_HALF_FLOAT }; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = width; + desc.buffer = backing_buffer; + cl_mem image = clCreateImage(context, flags, &format, &desc, nullptr, &err); + CL_CHECK(err); + return image; +} + +static void ggml_cl_release_mem(cl_mem & mem) { + if (mem != nullptr) { + CL_CHECK(clReleaseMemObject(mem)); + mem = nullptr; + } +} + +static void ggml_cl_adreno_xmem_attn_release_scratch(ggml_backend_opencl_context * backend_ctx) { + auto & s = backend_ctx->adreno_xmem_attn.scratch; + ggml_cl_release_mem(s.q_img); + ggml_cl_release_mem(s.k_img); + ggml_cl_release_mem(s.v_img); + ggml_cl_release_mem(s.out_img); + ggml_cl_release_mem(s.k_transpose_img1d); + ggml_cl_release_mem(s.k_transpose_buf); + ggml_cl_release_mem(s.k_packed_buf); + ggml_cl_release_mem(s.v_packed_buf); + ggml_cl_release_mem(s.score_img1d); + ggml_cl_release_mem(s.prob_img1d); + ggml_cl_release_mem(s.score_buf); + ggml_cl_release_mem(s.prob_buf); + ggml_cl_release_mem(s.softmax_stats_img2d); + ggml_cl_release_mem(s.xmem_qk); + ggml_cl_release_mem(s.xmem_pv); + s = {}; +} - size_t * local_work_size_ptr = local_work_size; - if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } +static ggml_cl_adreno_xmem_attn_schedule ggml_cl_adreno_xmem_attn_select_schedule( + const ggml_backend_opencl_context * backend_ctx, + int n_q, + int n_kv, + int heads_total, + int q_width, + int gqa_ratio) { + const bool big_h = heads_total >= 8; + ggml_cl_adreno_xmem_attn_schedule sched; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + if (gqa_ratio == 1) { + if (n_q >= 512) { sched.qk_lws0 = 512; } + else if (n_q >= 256) { sched.qk_lws0 = 128; } + else { sched.qk_lws0 = 64; } + sched.qk_lws2 = (big_h && n_q >= 512) ? 2 : 1; } else { - // Handle non-contiguous input - if (src0->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_softplus_f32_nc; - } else { - kernel = backend_ctx->kernel_softplus_f16_nc; - } + if (q_width >= 2048) { sched.qk_lws0 = 512; } + else if (q_width >= 256) { sched.qk_lws0 = 128; } + else { sched.qk_lws0 = 64; } + sched.qk_lws2 = MIN(8, (int) backend_ctx->max_workgroup_size / sched.qk_lws0); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb3)); + if (n_kv >= 2048) { sched.softmax_reduce_lws0 = 1024; } + else if (n_kv >= 512) { sched.softmax_reduce_lws0 = big_h ? 256 : 512; } + else { sched.softmax_reduce_lws0 = 256; } - int nth = 64; + if (n_kv < 256) { sched.softmax_apply_lws0 = 64; } + else { sched.softmax_apply_lws0 = big_h ? 128 : 64; } + sched.softmax_apply_lws2 = n_kv >= 512 ? 8 : 4; - size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + if (n_q < 256) { sched.pv_lws0 = 64; } + else { sched.pv_lws0 = big_h ? 128 : 64; } + sched.pv_lws2 = big_h ? 8 : (n_q <= 256 ? 8 : 4); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + const int max_wg = (int) backend_ctx->max_workgroup_size; + auto fix = [&](int & l0, int & l2) { + while (l0 * l2 > max_wg) { + if (l2 > 1) { l2 /= 2; } + else if (l0 > 32) { l0 /= 2; } + else { break; } + } + }; + fix(sched.qk_lws0, sched.qk_lws2); + fix(sched.softmax_apply_lws0, sched.softmax_apply_lws2); + fix(sched.pv_lws0, sched.pv_lws2); + while (sched.softmax_reduce_lws0 > max_wg) { + sched.softmax_reduce_lws0 /= 2; } + + return sched; } -static void ggml_cl_repeat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1_shape_def, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - GGML_ASSERT(dst->type == src0->type); +static bool ggml_cl_adreno_xmem_attn_prepare( + ggml_backend_opencl_context * backend_ctx, + int n_q, + int n_kv, + int d_head_q, + int d_head_v, + int n_head, + int n_head_kv, + int n_batch) { + auto & s = backend_ctx->adreno_xmem_attn.scratch; + const int gqa_ratio = n_head / n_head_kv; + const int q_width = n_q * gqa_ratio; + const int kv_heads_total = n_head_kv * n_batch; + const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); + if (s.q_img != nullptr && + s.n_q == n_q && + s.n_kv == n_kv && + s.n_kv_padded == n_kv_padded && + s.d_head_q == d_head_q && + s.d_head_v == d_head_v && + s.q_width == q_width && + s.kv_heads_total == kv_heads_total) { + return true; + } - UNUSED(src1_shape_def); + ggml_cl_adreno_xmem_attn_release_scratch(backend_ctx); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const int qpack = d_head_q / 4; + const int vpack = d_head_v / 4; + const int npack = n_kv_padded / 4; + const size_t q_img_h = (size_t) kv_heads_total * qpack; + const size_t v_img_h = (size_t) kv_heads_total * vpack; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + s.q_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) q_width, q_img_h); + s.k_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) n_kv_padded, q_img_h); + s.v_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) n_kv_padded, v_img_h); + s.out_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) q_width, v_img_h); - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + const size_t k_transpose_half4_elems = (size_t) npack * kv_heads_total * d_head_q; + s.k_transpose_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_transpose_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); + GGML_ASSERT(s.k_transpose_buf != nullptr); + s.k_transpose_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, k_transpose_half4_elems, s.k_transpose_buf); - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + const size_t k_groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_q, 16); + const size_t v_groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_v, 16); + const size_t k_packed_half4_elems = (size_t) n_kv_padded * k_groups16 * 4; + const size_t v_packed_half4_elems = (size_t) n_kv_padded * v_groups16 * 4; + s.k_packed_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_packed_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); + s.v_packed_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, v_packed_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); + GGML_ASSERT(s.k_packed_buf != nullptr && s.v_packed_buf != nullptr); - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + const size_t score_half4_elems = (size_t) npack * kv_heads_total * q_width; + const size_t score_bytes = score_half4_elems * sizeof(uint16_t) * 4; + s.score_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, score_bytes, nullptr, nullptr); + s.prob_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, score_bytes, nullptr, nullptr); + GGML_ASSERT(s.score_buf != nullptr && s.prob_buf != nullptr); + s.score_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, score_half4_elems, s.score_buf); + s.prob_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, score_half4_elems, s.prob_buf); + s.softmax_stats_img2d = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, + (size_t) q_width, (size_t) kv_heads_total); + s.xmem_qk = clCreateBuffer(backend_ctx->context, CL_MEM_READ_ONLY, 6144, nullptr, nullptr); + s.xmem_pv = clCreateBuffer(backend_ctx->context, CL_MEM_READ_ONLY, 6144, nullptr, nullptr); + GGML_ASSERT(s.softmax_stats_img2d != nullptr && s.xmem_qk != nullptr && s.xmem_pv != nullptr); - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; - const int ne2 = dst->ne[2]; - const int ne3 = dst->ne[3]; + s.n_q = n_q; + s.n_kv = n_kv; + s.n_kv_padded = n_kv_padded; + s.d_head_q = d_head_q; + s.d_head_v = d_head_v; + s.q_width = q_width; + s.kv_heads_total = kv_heads_total; + return true; +} - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; +static bool ggml_cl_adreno_xmem_attn_can_use( + const ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * q, + const ggml_tensor * k, + const ggml_tensor * dst) { + static const char * xmem_sdpa_env = getenv("GGML_OPENCL_XMEM_SDPA"); + if (xmem_sdpa_env == nullptr || xmem_sdpa_env[0] == '0') { + return false; + } - cl_kernel kernel = backend_ctx->kernel_repeat_f32; + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb3)); + if (!backend_ctx->adreno_xmem_attn.compiled || backend_ctx->gpu_family != GPU_FAMILY::ADRENO) { + return false; + } + if (q->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || + (k->type != GGML_TYPE_F16 && k->type != GGML_TYPE_F32) || + (v->type != GGML_TYPE_F16 && v->type != GGML_TYPE_F32)) { + return false; + } + if (sinks != nullptr) { + return false; + } + if (q->nb[0] != ggml_type_size(q->type) || k->nb[0] != ggml_type_size(k->type) || + v->nb[0] != ggml_type_size(v->type) || dst->nb[0] != ggml_type_size(dst->type)) { + return false; + } + if (mask != nullptr && (mask->type != GGML_TYPE_F16 || mask->nb[0] != sizeof(ggml_fp16_t))) { + return false; + } - int nth = 64; + const int n_q = q->ne[1]; + const int n_kv = k->ne[1]; + const int d_head_q = q->ne[0]; + const int d_head_v = v->ne[0]; + const int n_head = q->ne[2]; + const int n_head_kv = k->ne[2]; + const int n_batch = q->ne[3]; + + if (n_q <= 1 || n_kv <= 0 || n_kv > 8192) { + return false; + } + if (d_head_q != k->ne[0] || d_head_v != v->ne[0] || k->ne[1] != v->ne[1] || k->ne[3] != v->ne[3]) { + return false; + } + if (q->ne[3] != k->ne[3]) { + return false; + } + if (n_head_kv <= 0 || n_head % n_head_kv != 0 || k->ne[2] != v->ne[2]) { + return false; + } + if (dst->ne[0] != d_head_v || dst->ne[1] != n_head || dst->ne[2] != n_q || dst->ne[3] != n_batch) { + return false; + } + if ((d_head_q % 8) != 0 || (d_head_v % 32) != 0) { + return false; + } + if (mask != nullptr && + (mask->ne[0] < n_kv || mask->ne[1] < n_q || mask->ne[2] <= 0 || mask->ne[3] <= 0)) { + return false; + } + + float params[3]; + memcpy(params, dst->op_params, sizeof(params)); + if (params[1] != 0.0f || params[2] != 0.0f) { + return false; + } + + const int gqa_ratio = n_head / n_head_kv; + const int q_width = n_q * gqa_ratio; + const int kv_heads_total = n_head_kv * n_batch; + const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); + const int qpack = d_head_q / 4; + const int vpack = d_head_v / 4; + const int npack = n_kv_padded / 4; - size_t global_work_size[] = {(size_t)ne1*nth, (size_t)ne2, (size_t)ne3}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + if ((size_t) q_width > backend_ctx->image2d_max_width || + (size_t) n_kv_padded > backend_ctx->image2d_max_width) { + return false; + } + if ((size_t) kv_heads_total * (size_t) qpack > backend_ctx->image2d_max_height || + (size_t) kv_heads_total * (size_t) vpack > backend_ctx->image2d_max_height) { + return false; + } + if ((size_t) npack * (size_t) kv_heads_total * (size_t) d_head_q > backend_ctx->image_max_buffer_size || + (size_t) npack * (size_t) kv_heads_total * (size_t) q_width > backend_ctx->image_max_buffer_size) { + return false; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return true; } -static void ggml_cl_pad(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(dst->type == GGML_TYPE_F32); - - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - if (backend_ctx->kernel_pad == nullptr) { - GGML_LOG_WARN("%s: pad kernel not available, skipping OpenCL execution.\n", __func__); - return; +static void ggml_cl_adreno_xmem_attn_run( + ggml_backend_t backend, + const ggml_tensor * q, + const ggml_tensor * k, + ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; + auto & xstate = backend_ctx->adreno_xmem_attn; + auto & s = xstate.scratch; + if (!xstate.logged) { + GGML_LOG_INFO("ggml_opencl: using Adreno xmem attention path\n"); + xstate.logged = true; } - ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; - cl_ulong off_src0 = extra_src0->offset + src0->view_offs; - cl_ulong off_dst = extra_dst->offset + dst->view_offs; + ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *) q->extra; + ggml_tensor_extra_cl * extra_k = (ggml_tensor_extra_cl *) k->extra; + ggml_tensor_extra_cl * extra_v = (ggml_tensor_extra_cl *) v->extra; + ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *) dst->extra; + ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *) mask->extra : nullptr; - const int s_ne0 = src0->ne[0]; - const int s_ne1 = src0->ne[1]; - const int s_ne2 = src0->ne[2]; - const int s_ne3 = src0->ne[3]; + const cl_ulong offset_q = extra_q->offset + q->view_offs; + const cl_ulong offset_k = extra_k->offset + k->view_offs; + const cl_ulong offset_v = extra_v->offset + v->view_offs; + const cl_ulong offset_o = extra_o->offset + dst->view_offs; + const cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; - const int s_nb0 = src0->nb[0]; - const int s_nb1 = src0->nb[1]; - const int s_nb2 = src0->nb[2]; - const int s_nb3 = src0->nb[3]; + const int n_q = q->ne[1]; + const int n_kv = k->ne[1]; + const int d_head_q = q->ne[0]; + const int d_head_v = v->ne[0]; + const int n_head = q->ne[2]; + const int n_head_kv = k->ne[2]; + const int n_batch = q->ne[3]; + const int heads_total = n_head * n_batch; + const int gqa_ratio = n_head / n_head_kv; + const int q_width = n_q * gqa_ratio; + const int kv_heads_total = n_head_kv * n_batch; + const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); + const int qpack = d_head_q / 4; + const int opack = d_head_v / 4; + const int npack = n_kv_padded / 4; + const float scale = ((const float *) dst->op_params)[0]; - const int d_ne0 = dst->ne[0]; - const int d_ne1 = dst->ne[1]; - const int d_ne2 = dst->ne[2]; - const int d_ne3 = dst->ne[3]; + GGML_ASSERT(ggml_cl_adreno_xmem_attn_prepare( + backend_ctx, n_q, n_kv, d_head_q, d_head_v, n_head, n_head_kv, n_batch)); + const ggml_cl_adreno_xmem_attn_schedule sched = + ggml_cl_adreno_xmem_attn_select_schedule( + backend_ctx, n_q, n_kv_padded, heads_total, q_width, gqa_ratio); - const int d_nb0 = dst->nb[0]; - const int d_nb1 = dst->nb[1]; - const int d_nb2 = dst->nb[2]; - const int d_nb3 = dst->nb[3]; + { + size_t gws[3] = {ggml_cl_round_up((size_t) n_q, 8), (size_t) heads_total, (size_t) qpack}; + size_t lws[3] = {8, 1, (size_t) ((qpack <= 32) ? qpack : 1)}; + cl_kernel kernel = xstate.kernel_q_f32_to_img_scaled; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_q)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.q_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &d_head_q)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &n_batch)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &q->nb[1])); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &q->nb[2])); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &q->nb[3])); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - const int lp0 = ((const int*)(dst->op_params))[0]; - const int rp0 = ((const int*)(dst->op_params))[1]; - const int lp1 = ((const int*)(dst->op_params))[2]; - const int rp1 = ((const int*)(dst->op_params))[3]; - const int lp2 = ((const int*)(dst->op_params))[4]; - const int rp2 = ((const int*)(dst->op_params))[5]; - const int lp3 = ((const int*)(dst->op_params))[6]; - const int rp3 = ((const int*)(dst->op_params))[7]; + { + size_t gws[3] = {(size_t) n_kv_padded, (size_t) kv_heads_total, (size_t) qpack}; + size_t lws[3] = {8, 1, (size_t) ((qpack <= 32) ? qpack : 1)}; + cl_kernel kernel = k->type == GGML_TYPE_F16 ? + xstate.kernel_kv_f16_to_img_gqa : xstate.kernel_kv_f32_to_img_gqa; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_k->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_k)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.k_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_q)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_kv_padded)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &k->nb[1])); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &k->nb[2])); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &k->nb[3])); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - cl_kernel kernel = backend_ctx->kernel_pad; + { + size_t gws[3] = {(size_t) n_kv_padded, (size_t) kv_heads_total, (size_t) opack}; + size_t lws[3] = {8, 1, (size_t) ((opack <= 32) ? opack : 1)}; + cl_kernel kernel = v->type == GGML_TYPE_F16 ? + xstate.kernel_kv_f16_to_img_gqa : xstate.kernel_kv_f32_to_img_gqa; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_v->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_v)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.v_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_v)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_kv_padded)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &v->nb[1])); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &v->nb[2])); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &v->nb[3])); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &s_ne0)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &s_ne1)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &s_ne2)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &s_ne3)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &s_nb0)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &s_nb1)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &s_nb2)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &s_nb3)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &d_ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &d_ne1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &d_ne2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &d_ne3)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &d_nb0)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &d_nb1)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &d_nb2)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &d_nb3)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &lp0)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &rp0)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &lp1)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &rp1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &lp2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &rp2)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(int), &lp3)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(int), &rp3)); + { + size_t gws[3] = {(size_t) d_head_q, (size_t) kv_heads_total, (size_t) npack}; + size_t lws[3] = {(size_t) MIN(64, d_head_q), (size_t) (kv_heads_total >= 2 ? 2 : 1), (size_t) MIN(8, npack)}; + if (lws[0] * lws[1] * lws[2] > backend_ctx->max_workgroup_size) { + lws[1] = 1; + } + cl_kernel kernel = xstate.kernel_k_gather; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.k_transpose_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_img)); + ggml_cl_set_arg_int4(kernel, 2, n_kv_padded, kv_heads_total, npack, d_head_q); + ggml_cl_set_arg_int4(kernel, 3, qpack, 0, 0, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } + { + const size_t groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_q, 16); + const size_t packed_linear = (size_t) n_kv_padded * groups16; + const size_t lws0 = MIN((size_t) 1024, backend_ctx->max_workgroup_size); + size_t gws[3] = {ggml_cl_round_up(packed_linear, lws0), 1, 1}; + size_t lws[3] = {lws0, 1, 1}; + cl_kernel kernel = xstate.kernel_pack_k; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.k_packed_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_transpose_img1d)); + ggml_cl_set_arg_int4(kernel, 2, 8, (int) packed_linear, qpack, d_head_q); + ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, kv_heads_total, kv_heads_total, npack); + ggml_cl_set_arg_int4(kernel, 4, d_head_q, 0, 0, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - size_t lws0 = 64; - size_t gws0 = (( (size_t)d_ne0 + lws0 - 1 ) / lws0) * lws0; + { + size_t lws[3] = {(size_t) sched.qk_lws0, 1, (size_t) sched.qk_lws2}; + const int slices_per_group = sched.qk_lws2 * 8; + const size_t groups_z = (size_t) ggml_cl_round_up_div(npack, slices_per_group); + const size_t groups_x = (size_t) ggml_cl_round_up_div(q_width, sched.qk_lws0); + size_t gws[3] = { + lws[0] * groups_z, + groups_x, + (size_t) kv_heads_total * lws[2], + }; - size_t global_work_size[] = { gws0, (size_t)d_ne1, (size_t)d_ne2*d_ne3 }; - size_t local_work_size[] = { lws0, 1, 1 }; + cl_kernel kernel = xstate.kernel_qk_gemm; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.score_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_packed_buf)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.xmem_qk)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &s.q_img)); + ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, npack, q_width, 32); + ggml_cl_set_arg_int4(kernel, 5, qpack, 0, 0, kv_heads_total); + ggml_cl_set_arg_int4(kernel, 6, qpack, 1, 1, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } + cl_mem softmax_input_img = s.score_img1d; + cl_mem softmax_output_buf = s.prob_buf; + cl_mem pv_prob_img = s.prob_img1d; + + if (mask != nullptr) { + const cl_ulong mask_nb1 = mask->nb[1]; + const cl_ulong mask_nb2 = mask->nb[2]; + const cl_ulong mask_nb3 = mask->nb[3]; + const int mask_ne2 = mask->ne[2]; + const int mask_ne3 = mask->ne[3]; + size_t lws[3] = {(size_t) sched.softmax_apply_lws0, 1, (size_t) sched.softmax_apply_lws2}; + size_t gws[3] = { + ggml_cl_round_up((size_t) q_width, lws[0]), + (size_t) kv_heads_total, + ggml_cl_round_up((size_t) npack, lws[2]), + }; + cl_kernel kernel = xstate.kernel_mask_scores; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.prob_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.score_img1d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_mask->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &q_width)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_kv_padded)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &kv_heads_total)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &mask_ne3)); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - size_t * local_work_size_ptr = local_work_size; - if (d_ne0 % lws0 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; + softmax_input_img = s.prob_img1d; + softmax_output_buf = s.score_buf; + pv_prob_img = s.score_img1d; } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); -} - -static void ggml_cl_upscale(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(dst->type == GGML_TYPE_F32); + { + size_t lws[3] = {(size_t) sched.softmax_reduce_lws0, 1, 1}; + size_t gws[3] = {ggml_cl_round_up((size_t) q_width, lws[0]), (size_t) kv_heads_total, 1}; + cl_kernel kernel = xstate.kernel_softmax_reduce_basic; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &softmax_input_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.softmax_stats_img2d)); + ggml_cl_set_arg_int4(kernel, 2, kv_heads_total, 1, q_width, n_kv); + ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, q_width, 0, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } + { + size_t lws[3] = {(size_t) sched.softmax_apply_lws0, 1, (size_t) sched.softmax_apply_lws2}; + size_t gws[3] = { + ggml_cl_round_up((size_t) q_width, lws[0]), + (size_t) kv_heads_total, + ggml_cl_round_up((size_t) npack, lws[2]), + }; + cl_kernel kernel = xstate.kernel_softmax_apply_basic; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &softmax_output_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &softmax_input_img)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.softmax_stats_img2d)); + ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, npack, q_width, 1); + ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, q_width, n_kv, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } + { + const size_t groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_v, 16); + const size_t packed_linear = (size_t) n_kv_padded * groups16; + const size_t lws0 = MIN((size_t) 1024, backend_ctx->max_workgroup_size); + size_t gws[3] = {ggml_cl_round_up(packed_linear, lws0), 1, 1}; + size_t lws[3] = {lws0, 1, 1}; + cl_kernel kernel = xstate.kernel_pack_v; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.v_packed_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.v_img)); + ggml_cl_set_arg_int4(kernel, 2, 8, (int) packed_linear, npack, n_kv_padded); + ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, kv_heads_total, opack, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + { + size_t lws[3] = {(size_t) sched.pv_lws0, 1, (size_t) sched.pv_lws2}; + const int blocks = ggml_cl_round_up_div(opack, 8); + const size_t groups_z = (size_t) ggml_cl_round_up_div(blocks, sched.pv_lws2); + const size_t groups_x = (size_t) ggml_cl_round_up_div(q_width, sched.pv_lws0); + size_t gws[3] = { + lws[0] * groups_z, + groups_x, + (size_t) kv_heads_total * lws[2], + }; - const int mode_flags = (ggml_scale_mode) ggml_get_op_params_i32(dst, 0); - const ggml_scale_mode mode = (ggml_scale_mode) (mode_flags & 0xFF); - cl_kernel kernel = nullptr; + cl_kernel kernel = xstate.kernel_pv_gemm; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.v_packed_buf)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.xmem_pv)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &pv_prob_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &s.out_img)); + ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, opack, q_width, 32); + ggml_cl_set_arg_int4(kernel, 5, npack, 0, 0, kv_heads_total); + ggml_cl_set_arg_int4(kernel, 6, kv_heads_total * q_width, npack, q_width, 1); + ggml_cl_set_arg_int4(kernel, 7, 1, 0, 0, 0); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } - if (mode == GGML_SCALE_MODE_NEAREST) { - kernel = backend_ctx->kernel_upscale; - if (kernel == nullptr) { - GGML_LOG_WARN("%s: nearest upscale kernel not available, skipping OpenCL execution.\n", __func__); - return; - } - } else if (mode == GGML_SCALE_MODE_BILINEAR) { - kernel = backend_ctx->kernel_upscale_bilinear; - if (kernel == nullptr) { - GGML_LOG_WARN("%s: bilinear upscale kernel not available, skipping OpenCL execution.\n", __func__); - return; - } - } else { - GGML_LOG_WARN("%s: unsupported upscale mode %d, skipping OpenCL execution.\n", __func__, mode); - return; + { + size_t gws[3] = {ggml_cl_round_up((size_t) n_q, 8), (size_t) heads_total, (size_t) opack}; + size_t lws[3] = {8, 1, (size_t) ((opack <= 32) ? opack : 1)}; + cl_kernel kernel = xstate.kernel_img_to_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_o->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_o)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.out_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_v)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &dst->nb[1])); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &dst->nb[2])); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &dst->nb[3])); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); } +} - ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - cl_ulong off_src0 = extra_src0->offset + src0->view_offs; - cl_ulong off_dst = extra_dst->offset + dst->view_offs; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static void ggml_cl_flash_attn_prefill_bin(ggml_backend_t backend, const ggml_tensor * q, const ggml_tensor * k, ggml_tensor * dst) { + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + GGML_ASSERT(q->extra); + GGML_ASSERT(k->extra); + GGML_ASSERT(v->extra); + GGML_ASSERT(dst->extra); + if (mask) { + GGML_ASSERT(mask->extra); + } + if (sinks) { + GGML_ASSERT(sinks->extra); + } - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + cl_context context = backend_ctx->context; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + const int n_q = q->ne[1]; + const int n_kv = k->ne[1]; + const int d_head_q = q->ne[0]; + const int d_head_v = v->ne[0]; + const int n_head = q->ne[2]; + const int n_head_kv = k->ne[2]; + const int n_batch = q->ne[3]; - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; - const int ne2 = dst->ne[2]; - const int ne3 = dst->ne[3]; + const std::pair dk_dv = {d_head_q, d_head_v}; + cl_kernel kernel = backend_ctx->fa.kernel_flash_attn_f32_f16_bin; + GGML_ASSERT(kernel != NULL); - float sf0 = (float)ne0 / ne00; - float sf1 = (float)ne1 / ne01; - float sf2 = (float)ne2 / ne02; - float sf3 = (float)ne3 / ne03; + ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *)q->extra; + ggml_tensor_extra_cl * extra_k = (ggml_tensor_extra_cl *)k->extra; + ggml_tensor_extra_cl * extra_v = (ggml_tensor_extra_cl *)v->extra; + ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *)mask->extra : NULL; + ggml_tensor_extra_cl * extra_sinks = sinks ? (ggml_tensor_extra_cl *)sinks->extra : NULL; - float pixel_offset = 0.5f; + cl_ulong offset_q = extra_q->offset + q->view_offs; + cl_ulong offset_o = extra_o->offset + dst->view_offs; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb03)); + cl_mem mask_buffer = extra_mask ? extra_mask->data_device : NULL; + cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; + cl_mem sinks_buffer = extra_sinks ? extra_sinks->data_device : NULL; + cl_ulong offset_sinks = extra_sinks ? extra_sinks->offset + sinks->view_offs : 0; - if (mode == GGML_SCALE_MODE_NEAREST) { - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &sf0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float), &sf1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(float), &sf2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(float), &sf3)); - } else if (mode == GGML_SCALE_MODE_BILINEAR) { - if (mode_flags & GGML_SCALE_FLAG_ALIGN_CORNERS) { - sf0 = ne0 > 1 && ne00 > 1 ? (float)(ne0 - 1) / (ne00 - 1) : sf0; - sf1 = ne1 > 1 && ne01 > 1 ? (float)(ne1 - 1) / (ne01 - 1) : sf1; - pixel_offset = 0.0f; - } + const cl_ulong q_nb1 = q->nb[1]; + const cl_ulong q_nb2 = q->nb[2]; + const cl_ulong q_nb3 = q->nb[3]; - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(float), &sf0)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(float), &sf1)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(float), &sf2)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(float), &sf3)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(float), &pixel_offset)); - } + cl_mem k_data_device = extra_k->data_device; + cl_ulong offset_k = extra_k->offset + k->view_offs; + cl_ulong k_nb1 = k->nb[1]; + cl_ulong k_nb2 = k->nb[2]; + cl_ulong k_nb3 = k->nb[3]; + cl_mem v_data_device = extra_v->data_device; + cl_ulong offset_v = extra_v->offset + v->view_offs; + cl_ulong v_nb1 = v->nb[1]; + cl_ulong v_nb2 = v->nb[2]; + cl_ulong v_nb3 = v->nb[3]; - size_t dst_total_elements = (size_t)ne0 * ne1 * ne2 * ne3; - if (dst_total_elements == 0) { - return; - } - size_t global_work_size[] = { dst_total_elements, 1, 1 }; - size_t local_work_size_pref = 256; - size_t local_work_size[] = { MIN(local_work_size_pref, dst_total_elements), 1, 1}; + const cl_ulong o_nb1 = dst->nb[1]; + const cl_ulong o_nb2 = dst->nb[2]; + const cl_ulong o_nb3 = dst->nb[3]; - size_t * local_work_size_ptr = local_work_size; - if (dst_total_elements % local_work_size[0] != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; - } + const cl_ulong mask_nb1 = mask ? mask->nb[1] : 0; + const cl_ulong mask_nb2 = mask ? mask->nb[2] : 0; + const cl_ulong mask_nb3 = mask ? mask->nb[3] : 0; + const int mask_ne2 = mask ? mask->ne[2] : 0; + const int mask_ne3 = mask ? mask->ne[3] : 0; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); -} + float * params = (float *)dst->op_params; + float scale = params[0]; + float max_bias = params[1]; + float logit_softcap = params[2]; -static void ggml_cl_concat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == src1->type); - GGML_ASSERT(src0->type == dst->type); + const int is_causal = (mask == NULL && n_q > 1 && n_q == n_kv); // redundant n_q > 1 check ? - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const int n_head_log2_val = n_head > 0 ? 1u << (int)floorf(log2f((float)n_head)) : 0; + const float n_head_log2_f = n_head_log2_val > 0 ? (float)n_head_log2_val : 1.0f; + const float m0 = powf(2.0f, -(max_bias) / n_head_log2_f); + const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2_f); - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + ggml_cl_flash_attn_temp_buffer temp_k; + ggml_cl_flash_attn_temp_buffer temp_v; + ggml_cl_flash_attn_temp_buffer temp_k_aos; + ggml_cl_flash_attn_temp_buffer temp_v_aos; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne03 = src0->ne[3]; + if (is_q8_0) { + ggml_cl_flash_attn_reconstruct_aos( + backend_ctx, k, temp_k_aos, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - const cl_ulong nb00 = src0->nb[0]; - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - const cl_ulong nb03 = src0->nb[3]; + ggml_cl_flash_attn_reconstruct_aos( + backend_ctx, v, temp_v_aos, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); - const cl_ulong nb10 = src1->nb[0]; - const cl_ulong nb11 = src1->nb[1]; - const cl_ulong nb12 = src1->nb[2]; - const cl_ulong nb13 = src1->nb[3]; + bool k_done = ggml_cl_flash_attn_dequant_kv_gpu( + backend_ctx, k, GGML_TYPE_F16, k_data_device, offset_k, k_nb1, k_nb2, k_nb3, + temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; - const int ne2 = dst->ne[2]; - const int ne3 = dst->ne[3]; + bool v_done = ggml_cl_flash_attn_dequant_kv_gpu( + backend_ctx, v, GGML_TYPE_F16, v_data_device, offset_v, v_nb1, v_nb2, v_nb3, + temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); - const cl_ulong nb0 = dst->nb[0]; - const cl_ulong nb1 = dst->nb[1]; - const cl_ulong nb2 = dst->nb[2]; - const cl_ulong nb3 = dst->nb[3]; + GGML_ASSERT(k_done && v_done); + } - const cl_int dim = ((const int32_t *) dst->op_params)[0]; - GGML_ASSERT(dim >= 0 && dim <= 3); + // Allocate input/output memory buffers + cl_mem mem_matrixQ; + cl_mem mem_matrixK; + cl_mem mem_matrixV; + cl_mem mem_matrixO; + cl_buffer_region region; + cl_int err; - int nth = MIN(64, ne0); + region.origin = offset_q; + region.size = ggml_nbytes(q); + mem_matrixQ = clCreateSubBuffer(extra_q->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - const size_t ts = ggml_type_size(dst->type); - // the pack kernel copies 4-byte elements, so it is only valid for those. - const bool concat_pack = (dim == 0 && ne0 < 32 && ts == 4); - cl_kernel kernel; - if (concat_pack) { - kernel = backend_ctx->kernel_concat_b4_pack; - } else { - switch (ts) { - case 1: kernel = backend_ctx->kernel_concat_b1; break; - case 2: kernel = backend_ctx->kernel_concat_b2; break; - case 4: kernel = backend_ctx->kernel_concat_b4; break; - case 8: kernel = backend_ctx->kernel_concat_b8; break; - default: GGML_ABORT("unsupported concat element size: %zu", ts); - } - } + region.origin = offset_k; + region.size = is_q8_0 ? (size_t) k_nb3 * (size_t) k->ne[3] : ggml_nbytes(k); + mem_matrixK = clCreateSubBuffer(k_data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_int), &dim)); + region.origin = offset_v; + region.size = is_q8_0 ? (size_t) v_nb3 * (size_t) v->ne[3] : ggml_nbytes(v); + mem_matrixV = clCreateSubBuffer(v_data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - if (concat_pack) { - // packed kernel needs the dst dims to unflatten its 1-D row index. - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(int), &ne3)); + region.origin = offset_o; + region.size = ggml_nbytes(dst); + mem_matrixO = clCreateSubBuffer(extra_o->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - const int maxwg = (int)backend_ctx->get_kernel_workgroup_size(kernel); - const int base = MIN(64, maxwg); - const int tpr = MIN(ne0, base); // threads per row - const int rpw = MAX(1, base / tpr); // rows per workgroup - const int lsz = tpr * rpw; - const int nrows = ne1*ne2*ne3; - const int nwg = (nrows + rpw - 1) / rpw; - size_t global_work_size[] = {(size_t)nwg*lsz, 1, 1}; - size_t local_work_size[] = {(size_t)lsz, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); - } else { - size_t global_work_size[] = {(size_t)ne1*nth, (size_t)ne2, (size_t)ne3}; - size_t local_work_size[] = {(size_t)nth, 1, 1}; + cl_image_format img_fmt_1d = { CL_RGBA, CL_FLOAT}; + cl_image_desc img_desc_1d; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } -} + // use image 1d buffer used as fallback when on mask is applied + cl_mem mem_tex_mask_fallback_1dbuf; + img_fmt_1d = { CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc_1d, 0, sizeof(img_desc_1d)); + img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_1d.image_width = 1; + img_desc_1d.buffer = mem_matrixK; + mem_tex_mask_fallback_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &err); + CL_CHECK(err); -static void ggml_cl_timestep_embedding(ggml_backend_t backend, const ggml_tensor * src0, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(dst->type == GGML_TYPE_F32); + cl_mem mem_tex_matrixO_1dbuf; + img_fmt_1d = { CL_RGBA, CL_FLOAT}; + memset(&img_desc_1d, 0, sizeof(img_desc_1d)); + img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_1d.image_width = ggml_nbytes(dst) / 4 / 4; + img_desc_1d.buffer = mem_matrixO; + mem_tex_matrixO_1dbuf = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &err); + CL_CHECK(err); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + // The bin kernel requires 2d (or 3d) buffers packed for data loading/multiplication. + // These repack kernels launch across all buffers to ensure compatibility + cl_mem mem_tex_matrixMask_1dbuf = NULL; + cl_mem mem_matrixMask = NULL; + cl_mem mem_matrixMask_padded = NULL; + cl_ulong mask_nb1_padded = mask_nb1, mask_nb2_padded = mask_nb2, mask_nb3_padded = mask_nb3; + if (extra_mask) { + // allocate mem_matrixMask w/ new padded size + size_t n_kv_padded = GGML_PAD(n_kv, 4); + size_t mask_nb_padded = n_kv_padded * sizeof(cl_half) * mask->ne[1] * mask->ne[2] * mask->ne[3]; - if (backend_ctx->kernel_timestep_embedding == nullptr) { - GGML_LOG_WARN("%s: timestep_embedding kernel not available, skipping OpenCL execution.\n", __func__); - return; - } + // apply offset and create subBuffer for mask + region.origin = offset_mask; + region.size = ggml_nbytes(mask); + mem_matrixMask = clCreateSubBuffer(extra_mask->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - ggml_tensor_extra_cl * extra_src0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra_dst = (ggml_tensor_extra_cl *)dst->extra; + { + // create padded mask to contain all data + mem_matrixMask_padded = clCreateBuffer(context, CL_MEM_ALLOC_HOST_PTR, mask_nb_padded, NULL, &err); + CL_CHECK(err); - cl_ulong off_src0 = extra_src0->offset + src0->view_offs; - cl_ulong off_dst = extra_dst->offset + dst->view_offs; + // pass extra_mask->data_device, mem_matrixMask to kernel for copying/padding + mask_nb1_padded = (cl_ulong)n_kv_padded * sizeof(cl_half); + mask_nb2_padded = mask_nb1_padded * (cl_ulong)mask->ne[1]; + mask_nb3_padded = mask_nb2_padded * (cl_ulong)mask->ne[2]; - const int logical_dim = dst->op_params[0]; - const int max_period = dst->op_params[1]; - const int dst_nb1_bytes = dst->nb[1]; + cl_kernel repack_mask = backend_ctx->fa.kernel_repack_mask_for_wmm; + CL_CHECK(clSetKernelArg(repack_mask, 0, sizeof(cl_mem), &mem_matrixMask)); + CL_CHECK(clSetKernelArg(repack_mask, 1, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(repack_mask, 2, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(repack_mask, 3, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(repack_mask, 4, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(repack_mask, 5, sizeof(cl_mem), &mem_matrixMask_padded)); + CL_CHECK(clSetKernelArg(repack_mask, 6, sizeof(cl_ulong), &mask_nb1_padded)); + CL_CHECK(clSetKernelArg(repack_mask, 7, sizeof(cl_ulong), &mask_nb2_padded)); + CL_CHECK(clSetKernelArg(repack_mask, 8, sizeof(cl_ulong), &mask_nb3_padded)); - cl_kernel kernel = backend_ctx->kernel_timestep_embedding; + size_t repack_mask_gws[3] = {(size_t)n_kv, (size_t)mask->ne[1], (size_t)mask_ne2 * (size_t)mask->ne[3]}; + backend_ctx->enqueue_ndrange_kernel(repack_mask, 3, repack_mask_gws, NULL, dst); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &off_src0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &off_dst)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &dst_nb1_bytes)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &logical_dim)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &max_period)); + // use image 1d buffer for matrix Mask (padded row stride) + cl_image_format img_fmt_mask_1d = { CL_RGBA, CL_HALF_FLOAT}; + cl_image_desc img_desc_mask_1d; + memset(&img_desc_mask_1d, 0, sizeof(img_desc_mask_1d)); + img_desc_mask_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_mask_1d.image_width = mask_nb_padded / 2 / 4; + img_desc_mask_1d.buffer = mem_matrixMask_padded; + mem_tex_matrixMask_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_mask_1d, &img_desc_mask_1d, NULL, &err); + CL_CHECK(err); + } - size_t gws0 = (size_t)(((logical_dim + 1) / 2) + 1); + // WMM QK uses repacked 3D images. + // Q image: rows, heads, packed depth. + cl_image_format img_fmt_3d = { CL_RGBA, CL_HALF_FLOAT }; + cl_image_desc img_desc_3d; + + memset(&img_desc_3d, 0, sizeof(img_desc_3d)); + img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; + img_desc_3d.image_width = (size_t)n_q; + img_desc_3d.image_height = (size_t)n_batch * (size_t)n_head; + img_desc_3d.image_depth = (size_t)d_head_q / 4; + cl_mem img_q_wmm = NULL; + img_q_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); + CL_CHECK(err); - size_t gws1 = (size_t)src0->ne[0]; + { + cl_kernel repack_q = backend_ctx->fa.kernel_repack_q_for_wmm; + CL_CHECK(clSetKernelArg(repack_q, 0, sizeof(cl_mem), &mem_matrixQ)); + CL_CHECK(clSetKernelArg(repack_q, 1, sizeof(cl_ulong), &q_nb1)); + CL_CHECK(clSetKernelArg(repack_q, 2, sizeof(cl_ulong), &q_nb2)); + CL_CHECK(clSetKernelArg(repack_q, 3, sizeof(cl_ulong), &q_nb3)); + CL_CHECK(clSetKernelArg(repack_q, 4, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(repack_q, 5, sizeof(cl_mem), &img_q_wmm)); - size_t global_work_size[] = {gws0, gws1, 1}; + size_t repack_q_gws[3] = {(size_t)d_head_q / 4, (size_t)n_q, (size_t)n_batch * (size_t)n_head}; + backend_ctx->enqueue_ndrange_kernel(repack_q, 3, repack_q_gws, NULL, dst); + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, NULL, dst); -} + // K image: columns, row groups, KV heads. + const size_t n_kv_row4 = ((size_t)n_kv + 3) / 4; -struct ggml_cl_flash_attn_temp_buffer { - cl_mem data = nullptr; + memset(&img_desc_3d, 0, sizeof(img_desc_3d)); + img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; + img_desc_3d.image_width = (size_t)d_head_q; + img_desc_3d.image_height = n_kv_row4; + img_desc_3d.image_depth = (size_t)n_batch * (size_t)n_head_kv; + cl_mem img_k_wmm = NULL; + img_k_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); + CL_CHECK(err); - ~ggml_cl_flash_attn_temp_buffer() { - if (data != nullptr) { - CL_CHECK(clReleaseMemObject(data)); - data = nullptr; - } - } -}; + { + cl_kernel repack_k = backend_ctx->fa.kernel_repack_k_for_wmm; + CL_CHECK(clSetKernelArg(repack_k, 0, sizeof(cl_mem), &mem_matrixK)); + CL_CHECK(clSetKernelArg(repack_k, 1, sizeof(cl_ulong), &k_nb1)); + CL_CHECK(clSetKernelArg(repack_k, 2, sizeof(cl_ulong), &k_nb2)); + CL_CHECK(clSetKernelArg(repack_k, 3, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(repack_k, 4, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(repack_k, 5, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(repack_k, 6, sizeof(cl_mem), &img_k_wmm)); -// Resolve the source buffer + strides for an FA KV tensor: keep the -// caller-supplied AoS buffer if non-NULL, else fall back to tensor->extra. -static void ggml_cl_flash_attn_resolve_src( - const ggml_tensor * tensor, - cl_mem & buf, - cl_ulong & offset, - cl_ulong & nb1, - cl_ulong & nb2, - cl_ulong & nb3) { - if (buf != NULL) { - return; + size_t repack_k_gws[3] = {(size_t)d_head_q, n_kv_row4, (size_t)n_batch * (size_t)n_head_kv}; + backend_ctx->enqueue_ndrange_kernel(repack_k, 3, repack_k_gws, NULL, dst); } - ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra && extra->data_device); - buf = extra->data_device; - offset = extra->offset + tensor->view_offs; - nb1 = tensor->nb[1]; - nb2 = tensor->nb[2]; - nb3 = tensor->nb[3]; -} -// Read a (possibly strided-view) tensor from device into a tight host buffer. -// dim 0 is always tight; a strided view is gathered row-by-row. -static void ggml_cl_flash_attn_read_tensor_host( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - cl_mem src_buffer, cl_ulong src_offset, - cl_ulong src_nb1, cl_ulong src_nb2, cl_ulong src_nb3, - size_t row_bytes, void * dst, size_t total_bytes -) { - const bool contiguous_layout = - src_nb1 == row_bytes && - src_nb2 == row_bytes * (cl_ulong) tensor->ne[1] && - src_nb3 == src_nb2 * (cl_ulong) tensor->ne[2]; + // V image: kv-rows (contracted), packed head-dim groups, KV heads. + memset(&img_desc_3d, 0, sizeof(img_desc_3d)); + img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; + img_desc_3d.image_width = (size_t)n_kv; + img_desc_3d.image_height = (size_t)d_head_v / 4; + img_desc_3d.image_depth = (size_t)n_batch * (size_t)n_head_kv; + cl_mem img_v_wmm = NULL; + img_v_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); + CL_CHECK(err); - if (contiguous_layout) { - CL_CHECK(clEnqueueReadBuffer(backend_ctx->queue, src_buffer, CL_TRUE, - src_offset, total_bytes, dst, 0, NULL, NULL)); - return; - } + { + cl_kernel repack_v = backend_ctx->fa.kernel_repack_v_for_wmm; + CL_CHECK(clSetKernelArg(repack_v, 0, sizeof(cl_mem), &mem_matrixV)); + CL_CHECK(clSetKernelArg(repack_v, 1, sizeof(cl_ulong), &v_nb1)); + CL_CHECK(clSetKernelArg(repack_v, 2, sizeof(cl_ulong), &v_nb2)); + CL_CHECK(clSetKernelArg(repack_v, 3, sizeof(cl_ulong), &v_nb3)); + CL_CHECK(clSetKernelArg(repack_v, 4, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(repack_v, 5, sizeof(cl_mem), &img_v_wmm)); - size_t dst_off = 0; - for (int64_t i3 = 0; i3 < tensor->ne[3]; ++i3) { - for (int64_t i2 = 0; i2 < tensor->ne[2]; ++i2) { - for (int64_t i1 = 0; i1 < tensor->ne[1]; ++i1) { - const cl_ulong row_src_off = src_offset + - (cl_ulong) i3 * src_nb3 + - (cl_ulong) i2 * src_nb2 + - (cl_ulong) i1 * src_nb1; - CL_CHECK(clEnqueueReadBuffer(backend_ctx->queue, src_buffer, CL_TRUE, - row_src_off, row_bytes, - (uint8_t *) dst + dst_off, 0, NULL, NULL)); - dst_off += row_bytes; - } - } + size_t repack_v_gws[3] = {(size_t)d_head_v / 4, (size_t)n_kv, (size_t)n_batch * (size_t)n_head_kv}; + backend_ctx->enqueue_ndrange_kernel(repack_v, 3, repack_v_gws, NULL, dst); } - GGML_ASSERT(dst_off == total_bytes); -} -// forward decl: used by the FA decode dispatch (K-image variant) below. -static cl_mem ggml_cl_img_pool_get_or_create( - ggml_backend_opencl_context * backend_ctx, - std::map & pool, - cl_mem data_device, - cl_ulong offset0, - size_t required_bytes, - cl_channel_type channel_data_type); + cl_int enable_mask = (extra_mask) ? 1 : 0; + mask_buffer = extra_mask ? mem_tex_matrixMask_1dbuf : mem_tex_mask_fallback_1dbuf; -// Rebuild AoS q8_0/q4_0 bytes from a SoA tensor into a temp buffer. -// Returns false if the tensor is not SoA-quantised (already AoS). -static bool ggml_cl_flash_attn_reconstruct_aos( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - ggml_cl_flash_attn_temp_buffer & temp, - cl_mem & out_buf, - cl_ulong & out_offset, - cl_ulong & out_nb1, - cl_ulong & out_nb2, - cl_ulong & out_nb3 -) { - if (tensor == nullptr) { - return false; - } - const bool is_q8_0 = tensor->type == GGML_TYPE_Q8_0 && ggml_cl_is_q8_0_soa(tensor); - const bool is_q4_0 = tensor->type == GGML_TYPE_Q4_0 && ggml_cl_is_q4_0_soa(tensor); - if (!is_q8_0 && !is_q4_0) { - return false; - } + cl_mem mem_sinksBuf = NULL; + cl_mem mem_tex_sinks_1dbuf = NULL; + cl_int enable_sinks = (sinks_buffer != NULL) ? 1 : 0; + if (enable_sinks) { + region.origin = offset_sinks; + region.size = ggml_nbytes(sinks); + mem_sinksBuf = clCreateSubBuffer(extra_sinks->data_device, CL_MEM_READ_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // For views, SoA extra is on view_src (view->extra is pre-SoA). - // Noshuffle layout only applies to 2D weights, as determined by `use_adreno_kernels`, - // where ne2 == 1 and ne3 == 1 -- these are never FA inputs. - // Therefore, we use `restore_block_qk_0` kernels, not `restore_block_qk_0_noshuffle`. - const ggml_tensor * soa_src = tensor->view_src ? tensor->view_src : tensor; - cl_mem extra_q = NULL; - cl_mem extra_d = NULL; - if (is_q8_0) { - auto * e = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; - GGML_ASSERT(e && e->q && e->d); - extra_q = e->q; - extra_d = e->d; + cl_image_format img_fmt_sinks_1d = { CL_R, CL_FLOAT }; + cl_image_desc img_desc_sinks_1d; + memset(&img_desc_sinks_1d, 0, sizeof(img_desc_sinks_1d)); + img_desc_sinks_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_sinks_1d.image_width = (size_t)n_head; + img_desc_sinks_1d.buffer = mem_sinksBuf; + mem_tex_sinks_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_sinks_1d, &img_desc_sinks_1d, NULL, &err); + CL_CHECK(err); } else { - auto * e = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; - GGML_ASSERT(e && e->q && e->d); - extra_q = e->q; - extra_d = e->d; + // The image obj cannot be null so we back with buffer of size 1 and use matrixK to back because it always exists + cl_image_format img_fmt_sinks_fallback = { CL_R, CL_FLOAT }; + cl_image_desc img_desc_sinks_fallback; + memset(&img_desc_sinks_fallback, 0, sizeof(img_desc_sinks_fallback)); + img_desc_sinks_fallback.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_sinks_fallback.image_width = 1; + img_desc_sinks_fallback.buffer = mem_matrixK; + mem_tex_sinks_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_sinks_fallback, &img_desc_sinks_fallback, NULL, &err); + CL_CHECK(err); } - // Reconstruct the whole parent; view offsets then work naturally. - const size_t parent_nbytes = ggml_nbytes(soa_src); - cl_int err; - temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, parent_nbytes, NULL, &err); - CL_CHECK(err); + cl_uint arg = 0; - cl_kernel kernel = is_q8_0 ? backend_ctx->kernel_restore_block_q8_0 - : backend_ctx->kernel_restore_block_q4_0; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra_d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &temp.data)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mem_tex_matrixO_1dbuf)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &is_causal)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb1)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb2)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb3)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb1)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb2)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb1)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb2)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb3)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb1)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb2)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb3)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head_log2_val)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &logit_softcap)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &enable_mask)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb1_padded)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb2_padded)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb3_padded)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &mask_ne3)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mem_tex_sinks_1dbuf)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &enable_sinks)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_q_wmm)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_k_wmm)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_v_wmm)); + CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &d_head_q)); - const size_t n_blocks = (size_t) ggml_nelements(soa_src) / ggml_blck_size(soa_src->type); - size_t global_work_size[] = { n_blocks, 1, 1 }; - size_t local_work_size[] = { 1, 1, 1 }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, - global_work_size, local_work_size, 0, NULL, NULL)); + size_t global_work_size[3], local_work_size[3]; - out_buf = temp.data; - out_offset = tensor->view_offs; - out_nb1 = tensor->nb[1]; - out_nb2 = tensor->nb[2]; - out_nb3 = tensor->nb[3]; - return true; -} + const int n_waves_v = d_head_q / 64; + + local_work_size[0] = 64; + local_work_size[1] = n_waves_v; + local_work_size[2] = 1; -// GPU dequant of a contiguous q4_0/q8_0 KV tensor to f16/f32. Caller supplies -// src_buf when reconstructing from SoA. Returns false for non-contig layouts -// (the kernel indexes blocks tightly within ne[0]) so the caller can fall back -// to the host path. -static bool ggml_cl_flash_attn_dequant_kv_gpu( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - ggml_type target_type, - cl_mem in_src_buf, - cl_ulong in_src_offset, - cl_ulong in_src_nb1, - cl_ulong in_src_nb2, - cl_ulong in_src_nb3, - ggml_cl_flash_attn_temp_buffer & temp, - cl_mem & out_buf, - cl_ulong & out_offset, - cl_ulong & out_nb1, - cl_ulong & out_nb2, - cl_ulong & out_nb3 -) { - GGML_ASSERT(tensor->type == GGML_TYPE_Q8_0 || tensor->type == GGML_TYPE_Q4_0); - GGML_ASSERT(target_type == GGML_TYPE_F16 || target_type == GGML_TYPE_F32); + global_work_size[0] = 64; + global_work_size[1] = ((n_q + 64 - 1) / 64) * n_waves_v; + global_work_size[2] = n_batch * n_head; - const bool is_q8_0 = tensor->type == GGML_TYPE_Q8_0; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - cl_mem src_buf = in_src_buf; - cl_ulong src_offset = in_src_offset; - cl_ulong src_nb1 = in_src_nb1; - cl_ulong src_nb2 = in_src_nb2; - cl_ulong src_nb3 = in_src_nb3; - ggml_cl_flash_attn_resolve_src(tensor, src_buf, src_offset, src_nb1, src_nb2, src_nb3); + CL_CHECK(clReleaseMemObject(mem_tex_matrixO_1dbuf)); + CL_CHECK(clReleaseMemObject(img_q_wmm)); + CL_CHECK(clReleaseMemObject(img_k_wmm)); + CL_CHECK(clReleaseMemObject(img_v_wmm)); - if (tensor->nb[0] != (cl_ulong) ggml_type_size(tensor->type)) { - return false; + if (mem_tex_matrixMask_1dbuf) { + CL_CHECK(clReleaseMemObject(mem_tex_matrixMask_1dbuf)); + } + if (mem_matrixMask) { + CL_CHECK(clReleaseMemObject(mem_matrixMask)); + } + if (mem_matrixMask_padded) { + CL_CHECK(clReleaseMemObject(mem_matrixMask_padded)); + } + if (mem_tex_sinks_1dbuf) { + CL_CHECK(clReleaseMemObject(mem_tex_sinks_1dbuf)); + } + if (mem_sinksBuf) { + CL_CHECK(clReleaseMemObject(mem_sinksBuf)); } + CL_CHECK(clReleaseMemObject(mem_matrixQ)); + CL_CHECK(clReleaseMemObject(mem_matrixK)); + CL_CHECK(clReleaseMemObject(mem_matrixV)); + CL_CHECK(clReleaseMemObject(mem_matrixO)); +} +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - const size_t n_blocks = (size_t) ggml_nelements(tensor) / 32; // block size is 32 - const size_t elem_size = ggml_type_size(target_type); - const size_t out_bytes = n_blocks * 32 * elem_size; - const cl_int nblk0_arg = (cl_int) (tensor->ne[0] / 32); - const cl_int ne1_arg = (cl_int) tensor->ne[1]; - const cl_int ne2_arg = (cl_int) tensor->ne[2]; - const cl_int ne3_arg = (cl_int) tensor->ne[3]; +static void ggml_cl_flash_attn(ggml_backend_t backend, const ggml_tensor * q, const ggml_tensor * k, ggml_tensor * dst) { + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; - cl_int err; - temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, out_bytes, NULL, &err); - CL_CHECK(err); + GGML_ASSERT(q->extra); + GGML_ASSERT(k->extra); + GGML_ASSERT(v->extra); + GGML_ASSERT(dst->extra); - cl_kernel kernel; - if (target_type == GGML_TYPE_F16) { - kernel = is_q8_0 ? backend_ctx->kernel_dequant_q8_0_f16_view_aos - : backend_ctx->kernel_dequant_q4_0_f16_view_aos; - } else { - kernel = is_q8_0 ? backend_ctx->kernel_dequant_q8_0_f32_view_aos - : backend_ctx->kernel_dequant_q4_0_f32_view_aos; + if (mask) { + GGML_ASSERT(mask->extra); + } + if (sinks) { + GGML_ASSERT(sinks->extra); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &src_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &src_offset)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &src_nb1)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &src_nb2)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &src_nb3)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &nblk0_arg)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne1_arg)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne2_arg)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne3_arg)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_mem), &temp.data)); - - size_t global_ws[3] = { (size_t) nblk0_arg, (size_t) ne1_arg, (size_t) ne2_arg * (size_t) ne3_arg }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, - global_ws, NULL, 0, NULL, NULL)); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - out_buf = temp.data; - out_offset = 0; - out_nb1 = (cl_ulong) tensor->ne[0] * elem_size; - out_nb2 = out_nb1 * (cl_ulong) tensor->ne[1]; - out_nb3 = out_nb2 * (cl_ulong) tensor->ne[2]; - return true; -} + const int n_q = q->ne[1]; + const int n_kv = k->ne[1]; + const int d_head_q = q->ne[0]; + const int d_head_v = v->ne[0]; + const int n_head = q->ne[2]; + const int n_head_kv = k->ne[2]; + const int n_batch = q->ne[3]; -static bool ggml_cl_flash_attn_prepare_quantized_tensor( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - ggml_type target_type, - ggml_cl_flash_attn_temp_buffer & temp, - cl_mem & data_device, - cl_ulong & offset, - cl_ulong & nb1, - cl_ulong & nb2, - cl_ulong & nb3 -) { - if (!ggml_is_quantized(tensor->type)) { - return false; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (ggml_cl_adreno_xmem_attn_can_use(backend_ctx, q, k, dst)) { + ggml_cl_adreno_xmem_attn_run(backend, q, k, dst); + return; } +#endif - // Caller-supplied AoS buffer wins over tensor->extra when present. - cl_mem src_buffer = data_device; - cl_ulong src_offset = offset; - cl_ulong src_nb1 = nb1; - cl_ulong src_nb2 = nb2; - cl_ulong src_nb3 = nb3; - ggml_cl_flash_attn_resolve_src(tensor, src_buffer, src_offset, src_nb1, src_nb2, src_nb3); + // Compile DK512 decode separately from the prefill programs. + const bool fa_decode_only_512 = (d_head_q == 512); - const int64_t n = ggml_nelements(tensor); - const size_t row_bytes = (size_t) (tensor->ne[0] / ggml_blck_size(tensor->type)) * ggml_type_size(tensor->type); - // tight-packed byte count (ggml_nbytes includes stride gaps). - const size_t total_bytes = (size_t) (n / ggml_blck_size(tensor->type)) * ggml_type_size(tensor->type); - std::vector host_quant(total_bytes); + // per-variant lazy compile for this (dk, dv) + // DK=512 decode (n_q==1) needs no prepass + // DK=512 prefill (n_q>1) does, so compile it only when needed + if (!fa_decode_only_512 || n_q > 1) { + ggml_opencl_ensure_fa_pre_kernels(backend_ctx, d_head_q, d_head_v); + } - sync_with_other_backends(backend_ctx); - ggml_cl_flash_attn_read_tensor_host(backend_ctx, tensor, src_buffer, src_offset, - src_nb1, src_nb2, src_nb3, - row_bytes, host_quant.data(), total_bytes); + cl_kernel kernel = NULL; + bool use_prefill_k_img = false; // K is image1d_buffer_t for DK=512 prefill - std::vector host_f32(n); - ggml_get_type_traits(tensor->type)->to_float(host_quant.data(), host_f32.data(), n); + const bool is_f16 = q->type == GGML_TYPE_F16; + const bool is_mixed = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && v->type == GGML_TYPE_F16; + const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; + const bool is_q4_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q4_0 && v->type == GGML_TYPE_Q4_0; - const size_t bytes_per_elem = ggml_type_size(target_type); - const size_t buffer_size = (size_t) n * bytes_per_elem; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (use_fa_bin_kernels_prefill(backend_ctx, q, k, v)) { + // We support the prefill path of flash attn with a specialized d_head = 64/128/256 + ggml_cl_flash_attn_prefill_bin(backend, q, k, dst); + return; + } +#endif - std::vector host_linear(buffer_size); - if (target_type == GGML_TYPE_F32) { - memcpy(host_linear.data(), host_f32.data(), buffer_size); + if (is_f16) { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F16); + } else if (is_mixed) { + if (fa_decode_only_512 && n_q == 1) { + GGML_ASSERT(ggml_opencl_ensure_fa_f32_f16_vec_512(backend_ctx)); + } else { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32_F16); + } + if (fa_decode_only_512) { + // DK=512: the BM-tile prefill kernels are specifically compiled from + // FA_PREFILL_ONLY + if (n_q > 1) { + ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/false); + ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/true); + } + } else { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32_F16_SPLIT); + } + } else if (is_q8_0) { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q8_0); + if (d_head_q == 96 && d_head_v == 96) { + ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 96, 96, /*quant_bm=*/16, /*quant_n_split=*/3, /*is_q8_0=*/true); + } else if (d_head_q == 256 && d_head_v == 256) { + ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 256, 256, /*quant_bm=*/16, /*quant_n_split=*/8, /*is_q8_0=*/true); + } else { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q8_0_SPLIT); + } + } else if (is_q4_0) { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q4_0); + if (d_head_q == 96 && d_head_v == 96) { + ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 96, 96, /*quant_bm=*/16, /*quant_n_split=*/3, /*is_q8_0=*/false); + } else if (d_head_q == 256 && d_head_v == 256) { + ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 256, 256, /*quant_bm=*/16, /*quant_n_split=*/8, /*is_q8_0=*/false); + } else { + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q4_0_SPLIT); + } } else { - GGML_ASSERT(target_type == GGML_TYPE_F16); - ggml_fp32_to_fp16_row(host_f32.data(), (ggml_fp16_t *) host_linear.data(), n); + ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32); } - cl_int err; - temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, buffer_size, NULL, &err); - CL_CHECK(err); - CL_CHECK(clEnqueueWriteBuffer(backend_ctx->queue, temp.data, CL_TRUE, 0, buffer_size, host_linear.data(), 0, NULL, NULL)); + const std::pair dk_dv = {d_head_q, d_head_v}; + const int mq_gqa = n_head_kv > 0 ? n_head / n_head_kv : 0; + const std::tuple mq_decode_key = {d_head_q, d_head_v, mq_gqa}; + const bool mq_decode_shape = backend_ctx->gpu_family == ADRENO && is_mixed && n_q == 1 && + d_head_q == d_head_v && n_head_kv > 0 && n_head % n_head_kv == 0 && + ((((d_head_q == 64 && mq_gqa == 8) || (d_head_q == 128 && mq_gqa == 4)) && + backend_ctx->has_subgroup_shuffle) || + ((d_head_q == 256 || d_head_q == 512) && (mq_gqa == 4 || mq_gqa == 8))); + if (mq_decode_shape && n_kv >= 32) { + ggml_opencl_ensure_fa_f32_f16_mq_decode(backend_ctx, d_head_q, d_head_v, mq_gqa); + } + const bool use_native_q8_0_q1 = is_q8_0 && n_q == 1 && + backend_ctx->fa.f32_q8_0_q1.count(dk_dv) > 0; + // Native q8_0 prefill — reads q8_0 directly, wg_size = cfg->bm. + const bool use_native_q8_0 = is_q8_0 && n_q > 1 && + backend_ctx->fa.f32_q8_0.count(dk_dv) > 0; + const bool use_native_q4_0_q1 = is_q4_0 && n_q == 1 && + backend_ctx->fa.f32_q4_0_q1.count(dk_dv) > 0; + const bool use_native_q4_0 = is_q4_0 && n_q > 1 && + backend_ctx->fa.f32_q4_0.count(dk_dv) > 0; + const int block_m = n_q > 1 + ? (is_mixed ? backend_ctx->fa.f32_f16_bm.at(dk_dv) : backend_ctx->fa.bm.at(dk_dv)) + : 0; + // block_n is only used by the n_q > 1 prefill path; its map is not + // populated for DK=512 decode, so do not read it for decode. + const int block_n = (n_q > 1) + ? (is_mixed ? backend_ctx->fa.f32_f16_bn.at(dk_dv) + : backend_ctx->fa.bn.at(dk_dv)) + : 0; + // Pick split variant only when n_kv crosses the per-(dk,dv) threshold. + // the N_SPLIT>1 prefill tile reduces DK partials via subgroup shuffle, + // on Intel it uses the non-split BM tile and does not depend on subgroup size + const bool use_split_kernel = (n_q > 1 && is_mixed && + backend_ctx->gpu_family != INTEL && + backend_ctx->fa.f32_f16_split.count(dk_dv) > 0 && + n_kv >= backend_ctx->fa.f32_f16_split_nkv_threshold.at(dk_dv)); + const bool use_split_q8_0 = (use_native_q8_0 && backend_ctx->gpu_family != INTEL && + backend_ctx->fa.f32_q8_0_split.count(dk_dv) > 0 && + n_kv >= backend_ctx->fa.f32_q8_0_split_nkv_threshold.at(dk_dv)); + const bool use_split_q4_0 = (use_native_q4_0 && backend_ctx->gpu_family != INTEL && + backend_ctx->fa.f32_q4_0_split.count(dk_dv) > 0 && + n_kv >= backend_ctx->fa.f32_q4_0_split_nkv_threshold.at(dk_dv)); + const int wg_size_fa = (n_q > 1 && is_mixed) + ? (use_split_kernel + ? backend_ctx->fa.f32_f16_split_wg_size.at(dk_dv) + : backend_ctx->fa.f32_f16_wg_size.at(dk_dv)) + : block_m; - data_device = temp.data; - offset = 0; - nb1 = (cl_ulong) (tensor->ne[0] * bytes_per_elem); - nb2 = (cl_ulong) (tensor->ne[1] * nb1); - nb3 = (cl_ulong) (tensor->ne[2] * nb2); + ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *)q->extra; + ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *)mask->extra : NULL; + ggml_tensor_extra_cl * extra_sinks = sinks ? (ggml_tensor_extra_cl *)sinks->extra : NULL; - static bool warned = false; - if (!warned) { - GGML_LOG_WARN("ggml_opencl: OpenCL flash attention dequantizes GPU-resident quantized KV cache into temporary linear buffers; performance may be poor\n"); - warned = true; - } + // SoA q8_0/q4_0 K/V: data_device aliases the `q` subbuffer; reconstruct + // AoS into a temp buffer below. AoS tensors use extra_k/v->data_device. + const bool k_soa = ggml_cl_is_q8_0_soa(k) || ggml_cl_is_q4_0_soa(k); + const bool v_soa = ggml_cl_is_q8_0_soa(v) || ggml_cl_is_q4_0_soa(v); + ggml_tensor_extra_cl * extra_k = k_soa ? nullptr : (ggml_tensor_extra_cl *)k->extra; + ggml_tensor_extra_cl * extra_v = v_soa ? nullptr : (ggml_tensor_extra_cl *)v->extra; - return true; -} + cl_ulong offset_q = extra_q->offset + q->view_offs; + cl_ulong offset_k = k_soa ? 0 : extra_k->offset + k->view_offs; + cl_ulong offset_v = v_soa ? 0 : extra_v->offset + v->view_offs; + cl_ulong offset_o = extra_o->offset + dst->view_offs; + cl_mem mask_buffer = extra_mask ? extra_mask->data_device : NULL; + cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; + cl_mem sinks_buffer = extra_sinks ? extra_sinks->data_device : NULL; + cl_ulong offset_sinks = extra_sinks ? extra_sinks->offset + sinks->view_offs : 0; -// Host-side F16 -> F32 for the asymmetric-KV F32 fallback path. -static bool ggml_cl_flash_attn_convert_f16_to_f32( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - ggml_cl_flash_attn_temp_buffer & temp, - cl_mem & data_device, - cl_ulong & offset, - cl_ulong & nb1, - cl_ulong & nb2, - cl_ulong & nb3 -) { - if (tensor->type != GGML_TYPE_F16) { - return false; - } + const cl_ulong q_nb1 = q->nb[1]; + const cl_ulong q_nb2 = q->nb[2]; + const cl_ulong q_nb3 = q->nb[3]; - cl_mem src_buffer = data_device; - cl_ulong src_offset = offset; - cl_ulong src_nb1 = nb1; - cl_ulong src_nb2 = nb2; - cl_ulong src_nb3 = nb3; - ggml_cl_flash_attn_resolve_src(tensor, src_buffer, src_offset, src_nb1, src_nb2, src_nb3); + cl_ulong k_nb1 = k->nb[1]; + cl_ulong k_nb2 = k->nb[2]; + cl_ulong k_nb3 = k->nb[3]; - const int64_t n = ggml_nelements(tensor); - const size_t row_bytes = (size_t) tensor->ne[0] * sizeof(ggml_fp16_t); - const size_t total_bytes = (size_t) n * sizeof(ggml_fp16_t); - std::vector host_f16(total_bytes); + cl_ulong v_nb1 = v->nb[1]; + cl_ulong v_nb2 = v->nb[2]; + cl_ulong v_nb3 = v->nb[3]; - sync_with_other_backends(backend_ctx); - ggml_cl_flash_attn_read_tensor_host(backend_ctx, tensor, src_buffer, src_offset, - src_nb1, src_nb2, src_nb3, - row_bytes, host_f16.data(), total_bytes); + const cl_ulong o_nb1 = dst->nb[1]; + const cl_ulong o_nb2 = dst->nb[2]; + const cl_ulong o_nb3 = dst->nb[3]; - std::vector host_f32(n); - ggml_fp16_to_fp32_row((const ggml_fp16_t *) host_f16.data(), host_f32.data(), n); + const cl_ulong mask_nb1 = mask ? mask->nb[1] : 0; + const cl_ulong mask_nb2 = mask ? mask->nb[2] : 0; + const cl_ulong mask_nb3 = mask ? mask->nb[3] : 0; + const int mask_ne2 = mask ? mask->ne[2] : 0; + const int mask_ne3 = mask ? mask->ne[3] : 0; - const size_t f32_bytes = (size_t) n * sizeof(float); - cl_int err; - temp.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, f32_bytes, NULL, &err); - CL_CHECK(err); - CL_CHECK(clEnqueueWriteBuffer(backend_ctx->queue, temp.data, CL_TRUE, 0, - f32_bytes, host_f32.data(), 0, NULL, NULL)); + float scale; + float max_bias; + float logit_softcap; - data_device = temp.data; - offset = 0; - nb1 = (cl_ulong) (tensor->ne[0] * sizeof(float)); - nb2 = (cl_ulong) (tensor->ne[1] * nb1); - nb3 = (cl_ulong) (tensor->ne[2] * nb2); + const float * params = (const float *)dst->op_params; + scale = params[0]; + max_bias = params[1]; + logit_softcap = params[2]; - static bool warned = false; - if (!warned) { - GGML_LOG_WARN("ggml_opencl: OpenCL flash attention asymmetric KV converts an F16 cache to F32 host-side; performance may be poor\n"); - warned = true; + bool use_q1_vec = false; + bool use_q1_vec_mq = false; + bool use_local_tile = false; + // KV-head-coalesced gate: gqa_ratio == compile-time MQ_GQA + // restricts to DK=DV=256 for now due to local memory size + const int gqa_ratio_dispatch = n_head_kv > 0 ? (n_head / n_head_kv) : 0; + if (n_q == 1) { + if (use_native_q8_0_q1) { + if (d_head_v >= 256 && + backend_ctx->fa.f32_q8_0_q1_vec.count(dk_dv) > 0) { + kernel = backend_ctx->fa.f32_q8_0_q1_vec.at(dk_dv); + use_q1_vec = true; + } else { + kernel = backend_ctx->fa.f32_q8_0_q1.at(dk_dv); + } + } else if (use_native_q4_0_q1) { + // q4_0 vec kernel uses per-lane dp4a (cl_khr_integer_dot_product) + const char * q4vec_env = getenv("GGML_OPENCL_FA_Q4_VEC"); + const bool q4vec_off = (q4vec_env != NULL) && (q4vec_env[0] == '0'); + if (!q4vec_off && d_head_v >= 256 && + backend_ctx->fa.f32_q4_0_q1_vec.count(dk_dv) > 0) { + kernel = backend_ctx->fa.f32_q4_0_q1_vec.at(dk_dv); + use_q1_vec = true; + } else { + kernel = backend_ctx->fa.f32_q4_0_q1.at(dk_dv); + } + } else if (is_mixed) { + static const char * lt_env = getenv("GGML_OPENCL_FA_LOCAL_TILE"); + static const bool lt_on = (lt_env != NULL) && (lt_env[0] != '0'); + if (lt_on && d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_f16_q1_local_tile.count(dk_dv) > 0) { + kernel = backend_ctx->fa.f32_f16_q1_local_tile.at(dk_dv); + use_local_tile = true; + } else { + static const char * f16_vec_dk128_env = getenv("GGML_OPENCL_FA_F16_VEC_DK128"); + static const bool f16_vec_dk128_off = (f16_vec_dk128_env != NULL) && (f16_vec_dk128_env[0] == '0'); + const int dv_gate = f16_vec_dk128_off ? 256 : 128; + if (d_head_v >= dv_gate && + backend_ctx->fa.f32_f16_q1_vec.count(dk_dv) > 0) { + kernel = backend_ctx->fa.f32_f16_q1_vec.at(dk_dv); + use_q1_vec = true; + } else { + kernel = backend_ctx->fa.f32_f16_q1.at(dk_dv); + } + } + } else if (is_f16) { + kernel = backend_ctx->fa.f16_q1.at(dk_dv); + } else { + kernel = backend_ctx->fa.f32_q1.at(dk_dv); + } + } else { + if (use_native_q8_0) { + kernel = use_split_q8_0 + ? backend_ctx->fa.f32_q8_0_split.at(dk_dv) + : backend_ctx->fa.f32_q8_0.at(dk_dv); + } else if (use_native_q4_0) { + kernel = use_split_q4_0 + ? backend_ctx->fa.f32_q4_0_split.at(dk_dv) + : backend_ctx->fa.f32_q4_0.at(dk_dv); + } else if (is_mixed) { + if (use_split_kernel) { + // DK=512 prefill: opt-in texture-cache K reads (image1d_buffer_t). + static const char * pkimg_env = getenv("GGML_OPENCL_FA_PREFILL_K_IMG"); + const bool pkimg_on = (pkimg_env != NULL) && (pkimg_env[0] != '0'); + if (d_head_q == 512 && pkimg_on && + backend_ctx->fa.f32_f16_split_k_img.count(dk_dv) > 0) { + kernel = backend_ctx->fa.f32_f16_split_k_img.at(dk_dv); + use_prefill_k_img = true; + } else { + kernel = backend_ctx->fa.f32_f16_split.at(dk_dv); + } + } else { + kernel = backend_ctx->fa.f32_f16.at(dk_dv); + } + } else if (is_f16) { + kernel = backend_ctx->fa.f16.at(dk_dv); + } else { + kernel = backend_ctx->fa.f32.at(dk_dv); + } } - return true; -} + // Intel goes to the basic q1 kernel + if (backend_ctx->gpu_family == INTEL && n_q == 1) { + use_q1_vec = use_q1_vec_mq = use_local_tile = false; + if (is_mixed && backend_ctx->fa.f32_f16_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_f16_q1.at(dk_dv); } + else if (is_f16 && backend_ctx->fa.f16_q1.count(dk_dv)) { kernel = backend_ctx->fa.f16_q1.at(dk_dv); } + else if (is_q8_0 && backend_ctx->fa.f32_q8_0_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q8_0_q1.at(dk_dv); } + else if (is_q4_0 && backend_ctx->fa.f32_q4_0_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q4_0_q1.at(dk_dv); } + else if (backend_ctx->fa.f32_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q1.at(dk_dv); } + } + GGML_ASSERT(kernel != NULL); -// Flash-Decoding (K-split) dispatch thresholds. FD fires for non-causal -// attention with n_kv >= FD_MIN_N_KV and d_head <= FD_MAX_DK; the KV range is -// split into ~n_kv/FD_KV_PER_SPLIT partials, clamped to [FD_MIN_SPLITS, -// FD_MAX_SPLITS]. Multi-query FD is restricted to small heads -// (d_head <= FD_MAX_DK_MULTI) and capped at FD_MAX_N_Q_MULTI queries. -static constexpr int FD_MIN_N_KV = 2048; -static constexpr int FD_KV_PER_SPLIT = 2048; -// f16 KV decode wants more splits than the 2048 default; quantized KV keeps 2048. -static constexpr int FD_KV_PER_SPLIT_F16 = 512; -static constexpr int FD_MIN_SPLITS = 2; -static constexpr int FD_MAX_SPLITS = 16; -static constexpr int FD_MAX_DK = 128; -static constexpr int FD_MAX_DK_MULTI = 64; -static constexpr int FD_MAX_N_Q_MULTI = 8; -// MQ FD split-groups have few subgroups (MQ_NSG_SPLIT), so use a smaller -// kv_per_split to keep the softmax recurrence short; non-MQ keeps FD_KV_PER_SPLIT. -static constexpr int FD_MQ_KV_PER_SPLIT = 256; -static constexpr int FD_MQ_MAX_SPLITS = 128; + ggml_cl_flash_attn_temp_buffer temp_k; + ggml_cl_flash_attn_temp_buffer temp_v; + ggml_cl_flash_attn_temp_buffer temp_k_pad; + ggml_cl_flash_attn_temp_buffer temp_v_pad; + ggml_cl_flash_attn_temp_buffer temp_mask_pad; + ggml_cl_flash_attn_temp_buffer temp_blk; + const ggml_type kv_target_type = is_f16 ? GGML_TYPE_F16 : GGML_TYPE_F32; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -struct ggml_cl_adreno_xmem_attn_schedule { - int qk_lws0 = 256; - int qk_lws2 = 1; - int softmax_reduce_lws0 = 256; - int softmax_apply_lws0 = 64; - int softmax_apply_lws2 = 4; - int pv_lws0 = 64; - int pv_lws2 = 4; -}; + cl_mem k_data_device = k_soa ? NULL : extra_k->data_device; + cl_mem v_data_device = v_soa ? NULL : extra_v->data_device; -static inline size_t ggml_cl_round_up(size_t x, size_t a) { - return ((x + a - 1) / a) * a; -} + // SoA q8_0/q4_0 -> reconstruct AoS for downstream kernels that expect + // tight records (no-op when k/v is already AoS). + ggml_cl_flash_attn_temp_buffer temp_k_aos; + ggml_cl_flash_attn_temp_buffer temp_v_aos; + ggml_cl_flash_attn_reconstruct_aos(backend_ctx, k, temp_k_aos, + k_data_device, offset_k, k_nb1, k_nb2, k_nb3); + ggml_cl_flash_attn_reconstruct_aos(backend_ctx, v, temp_v_aos, + v_data_device, offset_v, v_nb1, v_nb2, v_nb3); -static inline int ggml_cl_round_up_div(int x, int y) { - return (x + y - 1) / y; -} + // currently FA kernels support KV cache with f16, f32, q4_0 and q8_0. + // there two cases that these kernels cannot cover, + // 1. KV cache types are q4_0 or q8_0, but the FA kernels fail to compile + // 2. KV cache types not currently supported by an FA kernel, e.g., q4_1 + // these two cases are supported here by dequantizing to f32/f16 and this + // causes performance degradation. + // For q4_0 or q8_0 cases that fail kernel compilation, dequant happens in GPU; + // for types that do not have FA kernels, dequant happens on host. + if (!use_native_q8_0_q1 && !use_native_q8_0 && + !use_native_q4_0_q1 && !use_native_q4_0) { + // for q4_0, q8_0 FA kernels that fail to compile + bool k_done = false; + bool v_done = false; + if (k->type == GGML_TYPE_Q8_0 || k->type == GGML_TYPE_Q4_0) { + k_done = ggml_cl_flash_attn_dequant_kv_gpu( + backend_ctx, k, kv_target_type, k_data_device, offset_k, k_nb1, k_nb2, k_nb3, + temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); + } + if (v->type == GGML_TYPE_Q8_0 || v->type == GGML_TYPE_Q4_0) { + v_done = ggml_cl_flash_attn_dequant_kv_gpu( + backend_ctx, v, kv_target_type, v_data_device, offset_v, v_nb1, v_nb2, v_nb3, + temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + } + if (!k_done) { + ggml_cl_flash_attn_prepare_quantized_tensor( + backend_ctx, k, kv_target_type, temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); + } + if (!v_done) { + ggml_cl_flash_attn_prepare_quantized_tensor( + backend_ctx, v, kv_target_type, temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + } + // Asymmetric KV on the F32 fallback path: convert the F16 side to F32 + // too. (Symmetric F16 / mixed paths handle F16 directly.) + if (kv_target_type == GGML_TYPE_F32 && !is_mixed && !is_f16) { + ggml_cl_flash_attn_convert_f16_to_f32(backend_ctx, k, temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); + ggml_cl_flash_attn_convert_f16_to_f32(backend_ctx, v, temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + } + } -static inline void ggml_cl_set_arg_int4(cl_kernel kernel, cl_uint index, int x, int y, int z, int w) { - struct { int x, y, z, w; } value { x, y, z, w }; - CL_CHECK(clSetKernelArg(kernel, index, sizeof(value), &value)); -} + cl_mem k_pad_buffer = NULL; + cl_mem v_pad_buffer = NULL; + cl_mem mask_pad_buffer = NULL; + cl_mem blk_buffer = NULL; + cl_ulong mask_pad_nb1 = 0; + cl_ulong mask_pad_nb2 = 0; + cl_ulong mask_pad_nb3 = 0; -static cl_mem ggml_cl_make_image2d_half4(cl_context context, cl_mem_flags flags, size_t width, size_t height) { - cl_int err = CL_SUCCESS; - cl_image_format format = { CL_RGBA, CL_HALF_FLOAT }; - cl_image_desc desc = {}; - desc.image_type = CL_MEM_OBJECT_IMAGE2D; - desc.image_width = width; - desc.image_height = height; - cl_mem image = clCreateImage(context, flags, &format, &desc, nullptr, &err); - CL_CHECK(err); - return image; -} + // Flash-Decoding K-split decision. Resolved here, before the prefill + // prepass, because KV-pad and blk prepass are pure overhead when FD fires. + // Do not infer causality from tensor shapes: a NULL mask means full + // (bidirectional) attention, e.g. ViT encoders, where n_q == n_kv as well. + // Causal attention in llama.cpp always comes with an explicit KQ mask. + // Inferring is_causal here corrupted mmproj output on OpenCL (see #23800). + const int is_causal = 0; + const int fd_max_n_q = (d_head_q <= FD_MAX_DK_MULTI) ? FD_MAX_N_Q_MULTI : 1; + cl_kernel fd_k_split = NULL; + bool use_fd_mq = false; + bool use_fd_mq_decode = false; + int fd_head_sub = 1; + size_t fd_mq_wg = 256; // MQ_GQA=4 kernel: Q1_WG_SIZE(64) * MQ_NSG_SPLIT(4) + bool use_fa_k_img = false; // K bound as image1d_buffer_t instead of (buf, offset) -static cl_mem ggml_cl_make_image1d_buffer_half4(cl_context context, cl_mem_flags flags, size_t width, cl_mem backing_buffer) { - cl_int err = CL_SUCCESS; - cl_image_format format = { CL_RGBA, CL_HALF_FLOAT }; - cl_image_desc desc = {}; - desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - desc.image_width = width; - desc.buffer = backing_buffer; - cl_mem image = clCreateImage(context, flags, &format, &desc, nullptr, &err); - CL_CHECK(err); - return image; -} + { + const char * mq_env = getenv("GGML_OPENCL_FA_MQ"); + const bool mq_enabled = (mq_env == NULL) ? true : (mq_env[0] != '0'); + const bool mq_kv_ok = is_mixed || is_q8_0 || is_q4_0; -static void ggml_cl_release_mem(cl_mem & mem) { - if (mem != nullptr) { - CL_CHECK(clReleaseMemObject(mem)); - mem = nullptr; - } -} + const char * lmq_env = getenv("GGML_OPENCL_FA_LOCAL_MQ_SPLIT"); + const bool lmq_on = (lmq_env != NULL) && (lmq_env[0] != '0'); -static void ggml_cl_adreno_xmem_attn_release_scratch(ggml_backend_opencl_context * backend_ctx) { - auto & s = backend_ctx->adreno_xmem_attn.scratch; - ggml_cl_release_mem(s.q_img); - ggml_cl_release_mem(s.k_img); - ggml_cl_release_mem(s.v_img); - ggml_cl_release_mem(s.out_img); - ggml_cl_release_mem(s.k_transpose_img1d); - ggml_cl_release_mem(s.k_transpose_buf); - ggml_cl_release_mem(s.k_packed_buf); - ggml_cl_release_mem(s.v_packed_buf); - ggml_cl_release_mem(s.score_img1d); - ggml_cl_release_mem(s.prob_img1d); - ggml_cl_release_mem(s.score_buf); - ggml_cl_release_mem(s.prob_buf); - ggml_cl_release_mem(s.softmax_stats_img2d); - ggml_cl_release_mem(s.xmem_qk); - ggml_cl_release_mem(s.xmem_pv); - s = {}; -} + static const char * vec_nq_env = getenv("GGML_OPENCL_FA_VEC_NQ"); + static const int N_MAX_VEC_NQ = (vec_nq_env != NULL && vec_nq_env[0] != '\0') + ? atoi(vec_nq_env) : 1; -static ggml_cl_adreno_xmem_attn_schedule ggml_cl_adreno_xmem_attn_select_schedule( - const ggml_backend_opencl_context * backend_ctx, - int n_q, - int n_kv, - int heads_total, - int q_width, - int gqa_ratio) { - const bool big_h = heads_total >= 8; - ggml_cl_adreno_xmem_attn_schedule sched; + const bool nq_in_vec_range = (n_q >= 1) && (n_q <= N_MAX_VEC_NQ); + const bool nq1_only = (n_q == 1); - if (gqa_ratio == 1) { - if (n_q >= 512) { sched.qk_lws0 = 512; } - else if (n_q >= 256) { sched.qk_lws0 = 128; } - else { sched.qk_lws0 = 64; } - sched.qk_lws2 = (big_h && n_q >= 512) ? 2 : 1; - } else { - if (q_width >= 2048) { sched.qk_lws0 = 512; } - else if (q_width >= 256) { sched.qk_lws0 = 128; } - else { sched.qk_lws0 = 64; } - sched.qk_lws2 = MIN(8, (int) backend_ctx->max_workgroup_size / sched.qk_lws0); + // Cluster-parallel decode default on for Adreno X2E/X1E + static const int c8_env_state = []{ + const char * e = getenv("GGML_OPENCL_FA_C8"); + if (e == NULL || e[0] == '\0') { return -1; } + return (e[0] != '0') ? 1 : 0; + }(); + const bool c8_default_on = backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E; + const bool c8_f16_on = (c8_env_state >= 0) ? (c8_env_state == 1) : c8_default_on; + // Quant-KV (q4_0/q8_0) GQA4 c8: default-on X2E + X1E + const bool c8_quant_on = (c8_env_state >= 0) ? (c8_env_state == 1) : c8_default_on; + if (mq_enabled && mq_kv_ok && nq_in_vec_range && !is_causal && + backend_ctx->gpu_family != INTEL && + !use_local_tile && + n_kv >= (mq_decode_shape ? 32 : FD_MIN_N_KV) && + backend_ctx->fa.f32_merge.count(dk_dv) > 0) { + if (mq_decode_shape && backend_ctx->fa.f32_f16_mq_decode.count(mq_decode_key) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_mq_decode.at(mq_decode_key); + fd_mq_wg = backend_ctx->fa.f32_f16_mq_decode_wg.at(mq_decode_key); + fd_head_sub = backend_ctx->fa.f32_f16_mq_decode_hs.at(mq_decode_key); + use_fd_mq = true; + use_fd_mq_decode = true; + } else if (nq1_only && lmq_on && is_mixed && d_head_q == 128 && d_head_v == 128 && + gqa_ratio_dispatch == 8 && + backend_ctx->fa.f32_f16_q1_local_mq_split_g8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_local_mq_split_g8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 64; + } else if (nq1_only && lmq_on && is_mixed && d_head_q == 128 && d_head_v == 128 && + gqa_ratio_dispatch == 4 && + backend_ctx->fa.f32_f16_q1_local_mq_split.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_local_mq_split.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 64; + } else if (nq1_only && is_mixed && gqa_ratio_dispatch == 4 && + ((d_head_q == 256 && d_head_v == 256) || + (d_head_q == 128 && d_head_v == 128)) && + backend_ctx->fa.f32_f16_q1_vec_mq_split.count(dk_dv) > 0) { + const bool k_img_on = d_head_q == 128 && d_head_v == 128 && + getenv("GGML_OPENCL_FA_K_IMG") != NULL && + getenv("GGML_OPENCL_FA_K_IMG")[0] != '0' && + backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img.count(dk_dv) > 0; + // Cluster-parallel decode + const bool c8_env = d_head_q == 128 && d_head_v == 128 && c8_f16_on; + if (c8_env && backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.at(dk_dv); + use_fd_mq = true; + } else if (c8_env && backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 128; + } else if (k_img_on) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img.at(dk_dv); + use_fd_mq = true; + use_fa_k_img = true; + } else { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split.at(dk_dv); + use_fd_mq = true; + } + // Cluster-parallel decode, DK=DV=256 GQA=8 + } else if (nq1_only && is_mixed && gqa_ratio_dispatch == 8 && + d_head_q == 256 && d_head_v == 256 && + c8_env_state == 1 && + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 128; + // Cluster-parallel decode for the g8 + } else if (is_mixed && gqa_ratio_dispatch == 8 && + d_head_q == 128 && d_head_v == 128 && + c8_f16_on && + (backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count(dk_dv) > 0 || + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8_ns2.count(dk_dv) > 0)) { + if (backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.at(dk_dv); + fd_mq_wg = 192; + } else { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8_ns2.at(dk_dv); + fd_mq_wg = 128; + } + use_fd_mq = true; + } else if (is_mixed && gqa_ratio_dispatch == 8 && + d_head_q == 128 && d_head_v == 128 && + getenv("GGML_OPENCL_FA_K_IMG") != NULL && + getenv("GGML_OPENCL_FA_K_IMG")[0] != '0' && + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 192; + use_fa_k_img = true; + } else if (is_mixed && gqa_ratio_dispatch == 8 && + d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 192; + } else if (nq1_only && is_q8_0 && gqa_ratio_dispatch == 8 && + d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 192; + } else if (nq1_only && is_q8_0 && gqa_ratio_dispatch == 4 && + d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_q8_0_q1_vec_mq_split.count(dk_dv) > 0) { + // Cluster-parallel q8_0 GQA4 + if (c8_quant_on && + backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8.at(dk_dv); + fd_mq_wg = 128; + } else { + fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split.at(dk_dv); + } + use_fd_mq = true; + } else if (nq1_only && is_q4_0) { + const char * q4_mq_env = getenv("GGML_OPENCL_FA_Q4_MQ"); + const bool q4_mq_on = (q4_mq_env != NULL) && (q4_mq_env[0] != '0'); + // Cluster-parallel q4_0 + const bool q4_c8_on = c8_env_state == 1 && + backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8.count(dk_dv) > 0; + if (q4_c8_on && gqa_ratio_dispatch == 8 && + d_head_q == 64 && d_head_v == 64) { + fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 128; + } else if (q4_mq_on && gqa_ratio_dispatch == 8 && + d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 192; + } else if (gqa_ratio_dispatch == 4 && + d_head_q == 128 && d_head_v == 128 && + backend_ctx->fa.f32_q4_0_q1_vec_mq_split.count(dk_dv) > 0) { + // Cluster-parallel q4_0 GQA4 + if (c8_quant_on && + backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8.at(dk_dv); + fd_mq_wg = 128; + } else { + fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split.at(dk_dv); + } + use_fd_mq = true; + } + } + } } - - if (n_kv >= 2048) { sched.softmax_reduce_lws0 = 1024; } - else if (n_kv >= 512) { sched.softmax_reduce_lws0 = big_h ? 256 : 512; } - else { sched.softmax_reduce_lws0 = 256; } - - if (n_kv < 256) { sched.softmax_apply_lws0 = 64; } - else { sched.softmax_apply_lws0 = big_h ? 128 : 64; } - sched.softmax_apply_lws2 = n_kv >= 512 ? 8 : 4; - - if (n_q < 256) { sched.pv_lws0 = 64; } - else { sched.pv_lws0 = big_h ? 128 : 64; } - sched.pv_lws2 = big_h ? 8 : (n_q <= 256 ? 8 : 4); - - const int max_wg = (int) backend_ctx->max_workgroup_size; - auto fix = [&](int & l0, int & l2) { - while (l0 * l2 > max_wg) { - if (l2 > 1) { l2 /= 2; } - else if (l0 > 32) { l0 /= 2; } - else { break; } + // Intel cluster-parallel decode FA + if (fd_k_split == NULL && backend_ctx->gpu_family == INTEL && n_q == 1 && !is_causal && + is_mixed && gqa_ratio_dispatch == 4 && d_head_q == 128 && d_head_v == 128 && + n_kv >= FD_MIN_N_KV && + getenv("GGML_OPENCL_FA_C8") != NULL && getenv("GGML_OPENCL_FA_C8")[0] != '0' && + backend_ctx->fa.f32_merge.count(dk_dv) > 0) { + if (backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 128; + } else if (backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.at(dk_dv); + use_fd_mq = true; + fd_mq_wg = 64; } - }; - fix(sched.qk_lws0, sched.qk_lws2); - fix(sched.softmax_apply_lws0, sched.softmax_apply_lws2); - fix(sched.pv_lws0, sched.pv_lws2); - while (sched.softmax_reduce_lws0 > max_wg) { - sched.softmax_reduce_lws0 /= 2; } - - return sched; -} - -static bool ggml_cl_adreno_xmem_attn_prepare( - ggml_backend_opencl_context * backend_ctx, - int n_q, - int n_kv, - int d_head_q, - int d_head_v, - int n_head, - int n_head_kv, - int n_batch) { - auto & s = backend_ctx->adreno_xmem_attn.scratch; - const int gqa_ratio = n_head / n_head_kv; - const int q_width = n_q * gqa_ratio; - const int kv_heads_total = n_head_kv * n_batch; - const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); - if (s.q_img != nullptr && - s.n_q == n_q && - s.n_kv == n_kv && - s.n_kv_padded == n_kv_padded && - s.d_head_q == d_head_q && - s.d_head_v == d_head_v && - s.q_width == q_width && - s.kv_heads_total == kv_heads_total) { - return true; + if (fd_k_split == NULL && + n_q >= 1 && n_q <= fd_max_n_q && n_kv >= FD_MIN_N_KV && !is_causal && + d_head_q <= FD_MAX_DK && + backend_ctx->fa.f32_merge.count(dk_dv) > 0) { + if (is_mixed && backend_ctx->fa.f32_f16_q1_split.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_f16_q1_split.at(dk_dv); + } else if (is_q8_0 && backend_ctx->fa.f32_q8_0_q1_split.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q8_0_q1_split.at(dk_dv); + } else if (is_q4_0 && backend_ctx->fa.f32_q4_0_q1_split.count(dk_dv) > 0) { + fd_k_split = backend_ctx->fa.f32_q4_0_q1_split.at(dk_dv); + } } + const bool use_fd = (fd_k_split != NULL); - ggml_cl_adreno_xmem_attn_release_scratch(backend_ctx); - - const int qpack = d_head_q / 4; - const int vpack = d_head_v / 4; - const int npack = n_kv_padded / 4; - const size_t q_img_h = (size_t) kv_heads_total * qpack; - const size_t v_img_h = (size_t) kv_heads_total * vpack; - - s.q_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) q_width, q_img_h); - s.k_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) n_kv_padded, q_img_h); - s.v_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) n_kv_padded, v_img_h); - s.out_img = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, (size_t) q_width, v_img_h); - - const size_t k_transpose_half4_elems = (size_t) npack * kv_heads_total * d_head_q; - s.k_transpose_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_transpose_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); - GGML_ASSERT(s.k_transpose_buf != nullptr); - s.k_transpose_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, k_transpose_half4_elems, s.k_transpose_buf); - - const size_t k_groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_q, 16); - const size_t v_groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_v, 16); - const size_t k_packed_half4_elems = (size_t) n_kv_padded * k_groups16 * 4; - const size_t v_packed_half4_elems = (size_t) n_kv_padded * v_groups16 * 4; - s.k_packed_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_packed_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); - s.v_packed_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, v_packed_half4_elems * sizeof(uint16_t) * 4, nullptr, nullptr); - GGML_ASSERT(s.k_packed_buf != nullptr && s.v_packed_buf != nullptr); - - const size_t score_half4_elems = (size_t) npack * kv_heads_total * q_width; - const size_t score_bytes = score_half4_elems * sizeof(uint16_t) * 4; - s.score_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, score_bytes, nullptr, nullptr); - s.prob_buf = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, score_bytes, nullptr, nullptr); - GGML_ASSERT(s.score_buf != nullptr && s.prob_buf != nullptr); - s.score_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, score_half4_elems, s.score_buf); - s.prob_img1d = ggml_cl_make_image1d_buffer_half4(backend_ctx->context, CL_MEM_READ_ONLY, score_half4_elems, s.prob_buf); - s.softmax_stats_img2d = ggml_cl_make_image2d_half4(backend_ctx->context, CL_MEM_READ_WRITE, - (size_t) q_width, (size_t) kv_heads_total); - s.xmem_qk = clCreateBuffer(backend_ctx->context, CL_MEM_READ_ONLY, 6144, nullptr, nullptr); - s.xmem_pv = clCreateBuffer(backend_ctx->context, CL_MEM_READ_ONLY, 6144, nullptr, nullptr); - GGML_ASSERT(s.softmax_stats_img2d != nullptr && s.xmem_qk != nullptr && s.xmem_pv != nullptr); + const int n_q_blocks = n_q > 1 ? (n_q + block_m - 1) / block_m : 0; + const int n_kv_blocks = (n_kv > 0 && block_n > 0) ? (n_kv + block_n - 1) / block_n : 0; + // KV pad + blk prepass are pure overhead when FD will fire — skip them. + const bool use_mixed_prepass = is_mixed && n_q > 1 && !use_fd; + // make sure prepass kernels are compiled + const bool have_kv_pad = backend_ctx->fa.kv_pad_f16.count(dk_dv) > 0; + const bool have_blk = backend_ctx->fa.blk_f16.count(dk_dv) > 0; + const bool use_kv_pad = use_mixed_prepass && (n_kv % block_n != 0) && have_kv_pad; + // blk prepass: per-KV-tile mask class (0=masked, 1=mixed, 2=unmasked). + // Consumed identically by f32_f16, q8_0 and q4_0 prefill kernels. + const bool use_quant_prepass = (use_native_q8_0 || use_native_q4_0) && !use_fd; + const bool use_blk_mask = (use_mixed_prepass || use_quant_prepass) && mask_buffer != NULL && have_blk; - s.n_q = n_q; - s.n_kv = n_kv; - s.n_kv_padded = n_kv_padded; - s.d_head_q = d_head_q; - s.d_head_v = d_head_v; - s.q_width = q_width; - s.kv_heads_total = kv_heads_total; - return true; -} + if (use_kv_pad) { + cl_int err; -static bool ggml_cl_adreno_xmem_attn_can_use( - const ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * q, - const ggml_tensor * k, - const ggml_tensor * dst) { - static const char * xmem_sdpa_env = getenv("GGML_OPENCL_XMEM_SDPA"); - if (xmem_sdpa_env == nullptr || xmem_sdpa_env[0] == '0') { - return false; - } + const size_t k_pad_size = (size_t) k_nb1 * (size_t) block_n * (size_t) n_head_kv * (size_t) n_batch; + temp_k_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_pad_size, NULL, &err); + CL_CHECK(err); + k_pad_buffer = temp_k_pad.data; - const ggml_tensor * v = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; - const ggml_tensor * sinks = dst->src[4]; + const size_t v_pad_size = (size_t) v_nb1 * (size_t) block_n * (size_t) n_head_kv * (size_t) n_batch; + temp_v_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, v_pad_size, NULL, &err); + CL_CHECK(err); + v_pad_buffer = temp_v_pad.data; - if (!backend_ctx->adreno_xmem_attn.compiled || backend_ctx->gpu_family != GPU_FAMILY::ADRENO) { - return false; - } - if (q->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || - (k->type != GGML_TYPE_F16 && k->type != GGML_TYPE_F32) || - (v->type != GGML_TYPE_F16 && v->type != GGML_TYPE_F32)) { - return false; - } - if (sinks != nullptr) { - return false; - } - if (q->nb[0] != ggml_type_size(q->type) || k->nb[0] != ggml_type_size(k->type) || - v->nb[0] != ggml_type_size(v->type) || dst->nb[0] != ggml_type_size(dst->type)) { - return false; - } - if (mask != nullptr && (mask->type != GGML_TYPE_F16 || mask->nb[0] != sizeof(ggml_fp16_t))) { - return false; - } + cl_kernel kernel_kv_pad = backend_ctx->fa.kv_pad_f16.at(dk_dv); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 0, sizeof(cl_mem), &k_data_device)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 1, sizeof(cl_ulong), &offset_k)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 2, sizeof(cl_mem), &v_data_device)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 3, sizeof(cl_ulong), &offset_v)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 4, sizeof(cl_mem), &k_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 5, sizeof(cl_mem), &v_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 6, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 7, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 8, sizeof(int), &n_batch)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 9, sizeof(cl_ulong), &k_nb1)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 10, sizeof(cl_ulong), &k_nb2)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 11, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 12, sizeof(cl_ulong), &v_nb1)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 13, sizeof(cl_ulong), &v_nb2)); + CL_CHECK(clSetKernelArg(kernel_kv_pad, 14, sizeof(cl_ulong), &v_nb3)); - const int n_q = q->ne[1]; - const int n_kv = k->ne[1]; - const int d_head_q = q->ne[0]; - const int d_head_v = v->ne[0]; - const int n_head = q->ne[2]; - const int n_head_kv = k->ne[2]; - const int n_batch = q->ne[3]; + size_t global_work_size[] = { (size_t) block_n, (size_t) n_head_kv, (size_t) n_batch }; + backend_ctx->enqueue_ndrange_kernel(kernel_kv_pad, 3, global_work_size, NULL, dst); - if (n_q <= 1 || n_kv <= 0 || n_kv > 8192) { - return false; - } - if (d_head_q != k->ne[0] || d_head_v != v->ne[0] || k->ne[1] != v->ne[1] || k->ne[3] != v->ne[3]) { - return false; - } - if (q->ne[3] != k->ne[3]) { - return false; - } - if (n_head_kv <= 0 || n_head % n_head_kv != 0 || k->ne[2] != v->ne[2]) { - return false; - } - if (dst->ne[0] != d_head_v || dst->ne[1] != n_head || dst->ne[2] != n_q || dst->ne[3] != n_batch) { - return false; - } - if ((d_head_q % 8) != 0 || (d_head_v % 32) != 0) { - return false; - } - if (mask != nullptr && - (mask->ne[0] < n_kv || mask->ne[1] < n_q || mask->ne[2] <= 0 || mask->ne[3] <= 0)) { - return false; - } + if (mask_buffer != NULL) { + mask_pad_nb1 = (cl_ulong) block_n * (cl_ulong) sizeof(ggml_fp16_t); + mask_pad_nb2 = (cl_ulong) n_q * mask_pad_nb1; + mask_pad_nb3 = (cl_ulong) mask_ne2 * mask_pad_nb2; - float params[3]; - memcpy(params, dst->op_params, sizeof(params)); - if (params[1] != 0.0f || params[2] != 0.0f) { - return false; - } + const size_t mask_pad_size = (size_t) mask_ne3 * (size_t) mask_pad_nb3; + temp_mask_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, mask_pad_size, NULL, &err); + CL_CHECK(err); + mask_pad_buffer = temp_mask_pad.data; - const int gqa_ratio = n_head / n_head_kv; - const int q_width = n_q * gqa_ratio; - const int kv_heads_total = n_head_kv * n_batch; - const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); - const int qpack = d_head_q / 4; - const int vpack = d_head_v / 4; - const int npack = n_kv_padded / 4; + cl_kernel kernel_mask_pad = backend_ctx->fa.mask_pad_f16.at(dk_dv); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 0, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 1, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 2, sizeof(cl_mem), &mask_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 3, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 4, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 5, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 6, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 7, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 8, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel_mask_pad, 9, sizeof(int), &mask_ne3)); - if ((size_t) q_width > backend_ctx->image2d_max_width || - (size_t) n_kv_padded > backend_ctx->image2d_max_width) { - return false; - } - if ((size_t) kv_heads_total * (size_t) qpack > backend_ctx->image2d_max_height || - (size_t) kv_heads_total * (size_t) vpack > backend_ctx->image2d_max_height) { - return false; - } - if ((size_t) npack * (size_t) kv_heads_total * (size_t) d_head_q > backend_ctx->image_max_buffer_size || - (size_t) npack * (size_t) kv_heads_total * (size_t) q_width > backend_ctx->image_max_buffer_size) { - return false; + size_t global_work_size_mask[] = { (size_t) block_n, (size_t) n_q, (size_t) (mask_ne2 * mask_ne3) }; + backend_ctx->enqueue_ndrange_kernel(kernel_mask_pad, 3, global_work_size_mask, NULL, dst); + } } - return true; -} + if (use_blk_mask) { + cl_int err; + const size_t blk_size = (size_t) n_kv_blocks * (size_t) n_q_blocks * (size_t) mask_ne2 * (size_t) mask_ne3; + temp_blk.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, blk_size, NULL, &err); + if (err != CL_SUCCESS) { + // Flush before retry — reclaim deferred driver deallocations. + CL_CHECK(clFinish(backend_ctx->queue)); + temp_blk.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, blk_size, NULL, &err); + } + CL_CHECK(err); + blk_buffer = temp_blk.data; -static void ggml_cl_adreno_xmem_attn_run( - ggml_backend_t backend, - const ggml_tensor * q, - const ggml_tensor * k, - ggml_tensor * dst) { - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; - auto & xstate = backend_ctx->adreno_xmem_attn; - auto & s = xstate.scratch; - if (!xstate.logged) { - GGML_LOG_INFO("ggml_opencl: using Adreno xmem attention path\n"); - xstate.logged = true; + cl_kernel kernel_blk = backend_ctx->fa.blk_f16.at(dk_dv); + CL_CHECK(clSetKernelArg(kernel_blk, 0, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(kernel_blk, 1, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(kernel_blk, 2, sizeof(cl_mem), &blk_buffer)); + CL_CHECK(clSetKernelArg(kernel_blk, 3, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel_blk, 4, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel_blk, 5, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(kernel_blk, 6, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(kernel_blk, 7, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(kernel_blk, 8, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel_blk, 9, sizeof(int), &mask_ne3)); + + size_t global_work_size_blk[] = { (size_t) n_kv_blocks, (size_t) n_q_blocks, (size_t) (mask_ne2 * mask_ne3) }; + backend_ctx->enqueue_ndrange_kernel(kernel_blk, 3, global_work_size_blk, NULL, dst); } - const ggml_tensor * v = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; + const int n_head_log2_val = n_head > 0 ? 1u << (int)floorf(log2f((float)n_head)) : 0; + const float n_head_log2_f = n_head_log2_val > 0 ? (float)n_head_log2_val : 1.0f; + const float m0 = powf(2.0f, -(max_bias) / n_head_log2_f); + const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2_f); - ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *) q->extra; - ggml_tensor_extra_cl * extra_k = (ggml_tensor_extra_cl *) k->extra; - ggml_tensor_extra_cl * extra_v = (ggml_tensor_extra_cl *) v->extra; - ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *) dst->extra; - ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *) mask->extra : nullptr; + if (use_fd) { + static const int fd_env_kv_per_split = []{ + const char * e = getenv("GGML_OPENCL_FD_KV_PER_SPLIT"); + return (e && e[0]) ? atoi(e) : 0; + }(); + static const int fd_env_max_splits = []{ + const char * e = getenv("GGML_OPENCL_FD_MAX_SPLITS"); + return (e && e[0]) ? atoi(e) : 0; + }(); - const cl_ulong offset_q = extra_q->offset + q->view_offs; - const cl_ulong offset_k = extra_k->offset + k->view_offs; - const cl_ulong offset_v = extra_v->offset + v->view_offs; - const cl_ulong offset_o = extra_o->offset + dst->view_offs; - const cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; + int fd_kv_per_split = use_fd_mq ? FD_MQ_KV_PER_SPLIT + : (is_mixed ? FD_KV_PER_SPLIT_F16 : FD_KV_PER_SPLIT); + int fd_max_splits = use_fd_mq ? FD_MQ_MAX_SPLITS : FD_MAX_SPLITS; + if (fd_env_kv_per_split > 0) { fd_kv_per_split = fd_env_kv_per_split; } + if (fd_env_max_splits > 0) { fd_max_splits = fd_env_max_splits; } + int n_splits = (n_kv + fd_kv_per_split - 1) / fd_kv_per_split; + if (n_splits < FD_MIN_SPLITS) { n_splits = FD_MIN_SPLITS; } + if (n_splits > fd_max_splits) { n_splits = fd_max_splits; } + if (use_fd_mq_decode) { + const size_t wg_per_split = (size_t) n_head_kv * n_batch; + const size_t wg_target = 4 * (size_t) backend_ctx->fa.compute_units; + while (wg_per_split * n_splits < wg_target && n_splits < fd_max_splits && + n_kv / (n_splits + 1) >= 32) { + n_splits++; + } + } + const int kv_per_split = (n_kv + n_splits - 1) / n_splits; - const int n_q = q->ne[1]; - const int n_kv = k->ne[1]; - const int d_head_q = q->ne[0]; - const int d_head_v = v->ne[0]; - const int n_head = q->ne[2]; - const int n_head_kv = k->ne[2]; - const int n_batch = q->ne[3]; - const int heads_total = n_head * n_batch; - const int gqa_ratio = n_head / n_head_kv; - const int q_width = n_q * gqa_ratio; - const int kv_heads_total = n_head_kv * n_batch; - const int n_kv_padded = (int) ggml_cl_round_up((size_t) n_kv, 32); - const int qpack = d_head_q / 4; - const int opack = d_head_v / 4; - const int npack = n_kv_padded / 4; - const float scale = ((const float *) dst->op_params)[0]; + const int fa_partial_floats = 2 + d_head_v; + const size_t partial_size_bytes = + (size_t) n_batch * n_head * n_q * n_splits * fa_partial_floats * sizeof(float); - GGML_ASSERT(ggml_cl_adreno_xmem_attn_prepare( - backend_ctx, n_q, n_kv, d_head_q, d_head_v, n_head, n_head_kv, n_batch)); - const ggml_cl_adreno_xmem_attn_schedule sched = - ggml_cl_adreno_xmem_attn_select_schedule( - backend_ctx, n_q, n_kv_padded, heads_total, q_width, gqa_ratio); + ggml_cl_flash_attn_temp_buffer temp_partial; + cl_mem partial_buffer; + cl_int err; + if (use_fd_mq_decode) { + auto & pool = backend_ctx->fa.fd_partial; + if (partial_size_bytes > pool.size) { + CL_CHECK(clFinish(backend_ctx->queue)); + pool.allocate(backend_ctx->context, partial_size_bytes); + } + partial_buffer = pool.buffer; + } else { + temp_partial.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, + partial_size_bytes, NULL, &err); + if (err != CL_SUCCESS) { + CL_CHECK(clFinish(backend_ctx->queue)); + temp_partial.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, + partial_size_bytes, NULL, &err); + } + CL_CHECK(err); + partial_buffer = temp_partial.data; + } + + cl_kernel k_split = fd_k_split; + int argi = 0; + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &extra_q->data_device)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_q)); + if (use_fa_k_img) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t k_bytes_span = + (size_t)(n_kv > 0 ? n_kv - 1 : 0) * (size_t)k_nb1 + + (size_t)(n_head_kv > 0 ? n_head_kv - 1 : 0) * (size_t)k_nb2 + + (size_t)(n_batch > 0 ? n_batch - 1 : 0) * (size_t)k_nb3 + + (size_t)d_head_q * nb00_bytes; + const size_t k_bytes = (k_bytes_span + 7) & ~(size_t)7; + const size_t k_pixels = k_bytes >> 3; + cl_mem k_img = nullptr; + if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { + k_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kq_img_pool, + k_data_device, offset_k, k_bytes, CL_HALF_FLOAT); + } + + // if image creation fails, fallback to buffer based kernels + if (k_img == nullptr) { + if (gqa_ratio_dispatch == 4 && + backend_ctx->fa.f32_f16_q1_vec_mq_split.count(dk_dv) > 0) { + k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split.at(dk_dv); + } else { + k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.at(dk_dv); + } + use_fa_k_img = false; + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_data_device)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_k)); + } else { + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_img)); + } + } else { + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_data_device)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_k)); + } + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &v_data_device)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_v)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb1)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb2)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb3)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb1)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb2)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb1)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb2)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb3)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head_log2_val)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &logit_softcap)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &mask_ne3)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &partial_buffer)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_splits)); + CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &kv_per_split)); + + // MQ split kernel uses MQ_NSG_SPLIT subgroups and one WG per (kv_head, batch, split) + // matches Q1_WG_SIZE * NSG (MQ_GQA=4 -> 256; MQ_GQA=8 -> 192) + const size_t fd_wg = use_fd_mq ? fd_mq_wg : 64; + const size_t fd_head_dim = use_fd_mq + ? (size_t)(n_head_kv * fd_head_sub * n_batch) + : (size_t)(n_head * n_batch); + size_t fd_lws[3] = { fd_wg, 1, 1 }; + // gid(2) packs q_idx * n_splits + split_idx. + size_t fd_gws[3] = { fd_wg, fd_head_dim, (size_t)(n_splits * n_q) }; + backend_ctx->enqueue_ndrange_kernel(k_split, 3, fd_gws, fd_lws, dst); + + cl_kernel k_merge = backend_ctx->fa.f32_merge.at(dk_dv); + argi = 0; + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &partial_buffer)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &extra_o->data_device)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &offset_o)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_splits)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb1)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb2)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb3)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &sinks_buffer)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &offset_sinks)); + CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_q)); - { - size_t gws[3] = {ggml_cl_round_up((size_t) n_q, 8), (size_t) heads_total, (size_t) qpack}; - size_t lws[3] = {8, 1, (size_t) ((qpack <= 32) ? qpack : 1)}; - cl_kernel kernel = xstate.kernel_q_f32_to_img_scaled; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_q)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.q_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &d_head_q)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &n_batch)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &q->nb[1])); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &q->nb[2])); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &q->nb[3])); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + const size_t merge_wg = (size_t) (d_head_v / 4); // one lane per float4 + size_t merge_lws[3] = { merge_wg, 1, 1 }; + size_t merge_gws[3] = { merge_wg, (size_t)(n_head * n_batch), (size_t) n_q }; + backend_ctx->enqueue_ndrange_kernel(k_merge, 3, merge_gws, merge_lws, dst); + return; } - { - size_t gws[3] = {(size_t) n_kv_padded, (size_t) kv_heads_total, (size_t) qpack}; - size_t lws[3] = {8, 1, (size_t) ((qpack <= 32) ? qpack : 1)}; - cl_kernel kernel = k->type == GGML_TYPE_F16 ? - xstate.kernel_kv_f16_to_img_gqa : xstate.kernel_kv_f32_to_img_gqa; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_k->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_k)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.k_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_q)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_kv_padded)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &k->nb[1])); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &k->nb[2])); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &k->nb[3])); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + cl_mem prefill_k_img = nullptr; + if (use_prefill_k_img) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t k_bytes_span = + (size_t)(n_kv > 0 ? n_kv - 1 : 0) * (size_t)k_nb1 + + (size_t)(n_head_kv > 0 ? n_head_kv - 1 : 0) * (size_t)k_nb2 + + (size_t)(n_batch > 0 ? n_batch - 1 : 0) * (size_t)k_nb3 + + (size_t)d_head_q * nb00_bytes; + const size_t k_bytes = (k_bytes_span + 7) & ~(size_t)7; + const size_t k_pixels = k_bytes >> 3; + if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { + prefill_k_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kq_img_pool, + k_data_device, offset_k, k_bytes, CL_HALF_FLOAT); + } + if (prefill_k_img == nullptr) { + kernel = backend_ctx->fa.f32_f16_split.at(dk_dv); + use_prefill_k_img = false; + } } - { - size_t gws[3] = {(size_t) n_kv_padded, (size_t) kv_heads_total, (size_t) opack}; - size_t lws[3] = {8, 1, (size_t) ((opack <= 32) ? opack : 1)}; - cl_kernel kernel = v->type == GGML_TYPE_F16 ? - xstate.kernel_kv_f16_to_img_gqa : xstate.kernel_kv_f32_to_img_gqa; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_v->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_v)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.v_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_v)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_kv_padded)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &v->nb[1])); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &v->nb[2])); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &v->nb[3])); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_q)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), use_prefill_k_img ? &prefill_k_img : &k_data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_k)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &v_data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset_v)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra_o->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset_o)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &is_causal)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &q_nb1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &q_nb2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &q_nb3)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &k_nb1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &k_nb2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &v_nb1)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &v_nb2)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &v_nb3)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &o_nb1)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &o_nb2)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &o_nb3)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(int), &n_head_log2_val)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(float), &logit_softcap)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(kernel, 36, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel, 37, sizeof(int), &mask_ne3)); + CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_mem), &sinks_buffer)); + CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_ulong), &offset_sinks)); + if (n_q > 1 && is_mixed) { + CL_CHECK(clSetKernelArg(kernel, 40, sizeof(cl_mem), &k_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel, 41, sizeof(cl_mem), &v_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel, 42, sizeof(cl_mem), &mask_pad_buffer)); + CL_CHECK(clSetKernelArg(kernel, 43, sizeof(cl_mem), &blk_buffer)); + CL_CHECK(clSetKernelArg(kernel, 44, sizeof(int), &n_kv_blocks)); + CL_CHECK(clSetKernelArg(kernel, 45, sizeof(cl_ulong), &mask_pad_nb1)); + CL_CHECK(clSetKernelArg(kernel, 46, sizeof(cl_ulong), &mask_pad_nb2)); + CL_CHECK(clSetKernelArg(kernel, 47, sizeof(cl_ulong), &mask_pad_nb3)); + } else if (use_native_q8_0 || use_native_q4_0) { + // arg 40 = blk classification buffer (NULL disables prepass opt). + CL_CHECK(clSetKernelArg(kernel, 40, sizeof(cl_mem), &blk_buffer)); } - { - size_t gws[3] = {(size_t) d_head_q, (size_t) kv_heads_total, (size_t) npack}; - size_t lws[3] = {(size_t) MIN(64, d_head_q), (size_t) (kv_heads_total >= 2 ? 2 : 1), (size_t) MIN(8, npack)}; - if (lws[0] * lws[1] * lws[2] > backend_ctx->max_workgroup_size) { - lws[1] = 1; + if (n_q == 1) { + if (use_local_tile) { + const size_t lt_wg = 128; + size_t local_work_size[] = { lt_wg, 1, 1 }; + size_t global_work_size[] = { lt_wg, (size_t) n_head, (size_t) n_batch }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + } else { + // q1_vec dispatches with NSG subgroups + const size_t q1_wg = backend_ctx->gpu_family == INTEL ? 32 : 64; + const size_t wg_size = use_q1_vec ? 256 : q1_wg; + const size_t head_dim_global = use_q1_vec_mq + ? (size_t)(n_head_kv * n_batch) + : (size_t)(n_head * n_batch); + size_t local_work_size[] = { wg_size, 1 }; + size_t global_work_size[] = { wg_size, head_dim_global }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); } - cl_kernel kernel = xstate.kernel_k_gather; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.k_transpose_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_img)); - ggml_cl_set_arg_int4(kernel, 2, n_kv_padded, kv_heads_total, npack, d_head_q); - ggml_cl_set_arg_int4(kernel, 3, qpack, 0, 0, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } - { - const size_t groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_q, 16); - const size_t packed_linear = (size_t) n_kv_padded * groups16; - const size_t lws0 = MIN((size_t) 1024, backend_ctx->max_workgroup_size); - size_t gws[3] = {ggml_cl_round_up(packed_linear, lws0), 1, 1}; - size_t lws[3] = {lws0, 1, 1}; - cl_kernel kernel = xstate.kernel_pack_k; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.k_packed_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_transpose_img1d)); - ggml_cl_set_arg_int4(kernel, 2, 8, (int) packed_linear, qpack, d_head_q); - ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, kv_heads_total, kv_heads_total, npack); - ggml_cl_set_arg_int4(kernel, 4, d_head_q, 0, 0, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + } else if (use_native_q8_0 || use_native_q4_0) { + // Native quant prefill. The split variant may override BLOCK_M + // (e.g. DK=96 quant uses BM=16). + const bool use_split = use_native_q8_0 ? use_split_q8_0 : use_split_q4_0; + int bm; + size_t wg_size; + if (use_split) { + bm = use_native_q8_0 ? backend_ctx->fa.f32_q8_0_split_bm.at(dk_dv) + : backend_ctx->fa.f32_q4_0_split_bm.at(dk_dv); + wg_size = use_native_q8_0 ? backend_ctx->fa.f32_q8_0_split_wg_size.at(dk_dv) + : backend_ctx->fa.f32_q4_0_split_wg_size.at(dk_dv); + } else { + bm = backend_ctx->fa.bm.at(dk_dv); + wg_size = (size_t) bm; + } + size_t local_work_size[] = { wg_size, 1 }; + size_t global_work_size[] = { (size_t)((n_q + bm - 1) / bm) * wg_size, (size_t)(n_head * n_batch) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + } else { + const size_t wg_size = (size_t) wg_size_fa; + size_t local_work_size[] = { wg_size, 1 }; + size_t global_work_size[] = { (size_t)((n_q + block_m - 1) / block_m) * wg_size, (size_t)(n_head * n_batch) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); } +} - { - size_t lws[3] = {(size_t) sched.qk_lws0, 1, (size_t) sched.qk_lws2}; - const int slices_per_group = sched.qk_lws2 * 8; - const size_t groups_z = (size_t) ggml_cl_round_up_div(npack, slices_per_group); - const size_t groups_x = (size_t) ggml_cl_round_up_div(q_width, sched.qk_lws0); - size_t gws[3] = { - lws[0] * groups_z, - groups_x, - (size_t) kv_heads_total * lws[2], - }; - - cl_kernel kernel = xstate.kernel_qk_gemm; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.score_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.k_packed_buf)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.xmem_qk)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &s.q_img)); - ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, npack, q_width, 32); - ggml_cl_set_arg_int4(kernel, 5, qpack, 0, 0, kv_heads_total); - ggml_cl_set_arg_int4(kernel, 6, qpack, 1, 1, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } - cl_mem softmax_input_img = s.score_img1d; - cl_mem softmax_output_buf = s.prob_buf; - cl_mem pv_prob_img = s.prob_img1d; +static void ggml_cl_mul_mat_f16_f32_tiled(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - if (mask != nullptr) { - const cl_ulong mask_nb1 = mask->nb[1]; - const cl_ulong mask_nb2 = mask->nb[2]; - const cl_ulong mask_nb3 = mask->nb[3]; - const int mask_ne2 = mask->ne[2]; - const int mask_ne3 = mask->ne[3]; - size_t lws[3] = {(size_t) sched.softmax_apply_lws0, 1, (size_t) sched.softmax_apply_lws2}; - size_t gws[3] = { - ggml_cl_round_up((size_t) q_width, lws[0]), - (size_t) kv_heads_total, - ggml_cl_round_up((size_t) npack, lws[2]), - }; - cl_kernel kernel = xstate.kernel_mask_scores; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.prob_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.score_img1d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_mask->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_mask)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &q_width)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_kv_padded)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &kv_heads_total)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &mask_ne3)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - softmax_input_img = s.prob_img1d; - softmax_output_buf = s.score_buf; - pv_prob_img = s.score_img1d; - } + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - { - size_t lws[3] = {(size_t) sched.softmax_reduce_lws0, 1, 1}; - size_t gws[3] = {ggml_cl_round_up((size_t) q_width, lws[0]), (size_t) kv_heads_total, 1}; - cl_kernel kernel = xstate.kernel_softmax_reduce_basic; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &softmax_input_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.softmax_stats_img2d)); - ggml_cl_set_arg_int4(kernel, 2, kv_heads_total, 1, q_width, n_kv); - ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, q_width, 0, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } - { - size_t lws[3] = {(size_t) sched.softmax_apply_lws0, 1, (size_t) sched.softmax_apply_lws2}; - size_t gws[3] = { - ggml_cl_round_up((size_t) q_width, lws[0]), - (size_t) kv_heads_total, - ggml_cl_round_up((size_t) npack, lws[2]), - }; - cl_kernel kernel = xstate.kernel_softmax_apply_basic; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &softmax_output_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &softmax_input_img)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.softmax_stats_img2d)); - ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, npack, q_width, 1); - ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, q_width, n_kv, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } - { - const size_t groups16 = (size_t) ggml_cl_round_up_div(kv_heads_total * d_head_v, 16); - const size_t packed_linear = (size_t) n_kv_padded * groups16; - const size_t lws0 = MIN((size_t) 1024, backend_ctx->max_workgroup_size); - size_t gws[3] = {ggml_cl_round_up(packed_linear, lws0), 1, 1}; - size_t lws[3] = {lws0, 1, 1}; - cl_kernel kernel = xstate.kernel_pack_v; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.v_packed_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.v_img)); - ggml_cl_set_arg_int4(kernel, 2, 8, (int) packed_linear, npack, n_kv_padded); - ggml_cl_set_arg_int4(kernel, 3, kv_heads_total, kv_heads_total, opack, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } + const int M = src0->ne[1]; + const int N = src1->ne[1]; + const int K = src0->ne[0]; - { - size_t lws[3] = {(size_t) sched.pv_lws0, 1, (size_t) sched.pv_lws2}; - const int blocks = ggml_cl_round_up_div(opack, 8); - const size_t groups_z = (size_t) ggml_cl_round_up_div(blocks, sched.pv_lws2); - const size_t groups_x = (size_t) ggml_cl_round_up_div(q_width, sched.pv_lws0); - size_t gws[3] = { - lws[0] * groups_z, - groups_x, - (size_t) kv_heads_total * lws[2], - }; + cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_tiled; - cl_kernel kernel = xstate.kernel_pv_gemm; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &s.v_packed_buf)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s.xmem_pv)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &pv_prob_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &s.out_img)); - ggml_cl_set_arg_int4(kernel, 4, kv_heads_total, opack, q_width, 32); - ggml_cl_set_arg_int4(kernel, 5, npack, 0, 0, kv_heads_total); - ggml_cl_set_arg_int4(kernel, 6, kv_heads_total * q_width, npack, q_width, 1); - ggml_cl_set_arg_int4(kernel, 7, 1, 0, 0, 0); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); - { - size_t gws[3] = {ggml_cl_round_up((size_t) n_q, 8), (size_t) heads_total, (size_t) opack}; - size_t lws[3] = {8, 1, (size_t) ((opack <= 32) ? opack : 1)}; - cl_kernel kernel = xstate.kernel_img_to_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_o->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_o)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &s.out_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &d_head_v)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &n_batch)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &dst->nb[1])); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &dst->nb[2])); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &dst->nb[3])); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); - } -} + // Tiling parameters. These need to be tuned for optimal performance. + // They must match the #defines in the kernel mul_mat_f16_f32.cl. + // + // OPWM / OPWN: Output tile size per Work-Group. A work-group computes a tile of size OPWM x OPWN. + // TPWM / TPWN: Threads per Work-group. This is the work-group size. + // OPTM / OPTN: Output elements per Thread. Each thread computes OPTM x OPTN elements. + // + // The following relationships must hold: + // OPWM = TPWM * OPTM + // OPWN = TPWN * OPTN + // + const int OPWM = 64; + const int OPWN = 64; + const int TPWM = 16; + const int TPWN = 8; -#endif // GGML_OPENCL_USE_ADRENO_KERNELS + size_t local_work_size[2] = { TPWM, TPWN }; + size_t global_work_size[2] = { + (size_t) ((M + OPWM - 1) / OPWM) * TPWM, + (size_t) ((N + OPWN - 1) / OPWN) * TPWN, + }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); +} #ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_flash_attn_prefill_bin(ggml_backend_t backend, const ggml_tensor * q, const ggml_tensor * k, ggml_tensor * dst) { - const ggml_tensor * v = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; - const ggml_tensor * sinks = dst->src[4]; - GGML_ASSERT(q->extra); - GGML_ASSERT(k->extra); - GGML_ASSERT(v->extra); - GGML_ASSERT(dst->extra); - if (mask) { - GGML_ASSERT(mask->extra); +static bool ggml_cl_can_use_adreno_xmem_gemm_f16_f32( + const ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * src0, + const ggml_tensor * src1, + const ggml_tensor * dst) { + if (!backend_ctx->adreno_xmem_gemm_enabled) { + return false; } - if (sinks) { - GGML_ASSERT(sinks->extra); + if (backend_ctx->gpu_family != GPU_FAMILY::ADRENO) { + return false; } + if ((src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_BF16) || + src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { + return false; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1) || !ggml_is_contiguous(dst)) { + return false; + } + if (src0->ne[2] != 1 || src0->ne[3] != 1 || + src1->ne[2] != 1 || src1->ne[3] != 1 || + dst->ne[2] != 1 || dst->ne[3] != 1) { + return false; + } + const int K = src0->ne[0]; + const int M = src0->ne[1]; + const int N = src1->ne[1]; + if (src1->ne[0] != K || dst->ne[0] != M || dst->ne[1] != N) { + return false; + } + if (N <= 1 || M < 64 || N < 16 || K < 64) { + return false; + } + if ((K % 8) != 0) { + return false; + } + const int kpack = K / 4; + const int npack = CEIL_DIV(M, 4); + if (static_cast(N) > backend_ctx->image2d_max_width || + static_cast(kpack) > backend_ctx->image2d_max_height) { + return false; + } + if (static_cast(N) > backend_ctx->image2d_max_width || + static_cast(npack) > backend_ctx->image2d_max_height) { + return false; + } + return true; +} - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - cl_context context = backend_ctx->context; - - const int n_q = q->ne[1]; - const int n_kv = k->ne[1]; - const int d_head_q = q->ne[0]; - const int d_head_v = v->ne[0]; - const int n_head = q->ne[2]; - const int n_head_kv = k->ne[2]; - const int n_batch = q->ne[3]; +static void ggml_cl_mul_mat_f16_f32_adreno_xmem( + ggml_backend_t backend, + const ggml_tensor * src0, + const ggml_tensor * src1, + ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; - const std::pair dk_dv = {d_head_q, d_head_v}; - cl_kernel kernel = backend_ctx->fa.kernel_flash_attn_f32_f16_bin; - GGML_ASSERT(kernel != NULL); + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *)q->extra; - ggml_tensor_extra_cl * extra_k = (ggml_tensor_extra_cl *)k->extra; - ggml_tensor_extra_cl * extra_v = (ggml_tensor_extra_cl *)v->extra; - ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *)mask->extra : NULL; - ggml_tensor_extra_cl * extra_sinks = sinks ? (ggml_tensor_extra_cl *)sinks->extra : NULL; + const cl_ulong offset0 = extra0->offset + src0->view_offs; + const cl_ulong offset1 = extra1->offset + src1->view_offs; + const cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_ulong offset_q = extra_q->offset + q->view_offs; - cl_ulong offset_o = extra_o->offset + dst->view_offs; + const int K = src0->ne[0]; + const int M = src0->ne[1]; + const int N = src1->ne[1]; + const int kpack = K / 4; + const int npack = CEIL_DIV(M, 4); + const int os = 8; + // Pad weights to the 32-row tiles read by the xmem kernel. + const int npack_padded = CEIL_DIV(npack, os)*os; - cl_mem mask_buffer = extra_mask ? extra_mask->data_device : NULL; - cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; - cl_mem sinks_buffer = extra_sinks ? extra_sinks->data_device : NULL; - cl_ulong offset_sinks = extra_sinks ? extra_sinks->offset + sinks->view_offs : 0; + const size_t xmem_bytes = 6144; + const size_t weight_bytes = static_cast(kpack) * static_cast(npack_padded) * 4u * sizeof(cl_half4); - const cl_ulong q_nb1 = q->nb[1]; - const cl_ulong q_nb2 = q->nb[2]; - const cl_ulong q_nb3 = q->nb[3]; + backend_ctx->prealloc_adreno_xmem_const.allocate(backend_ctx->context, xmem_bytes); - cl_mem k_data_device = extra_k->data_device; - cl_ulong offset_k = extra_k->offset + k->view_offs; - cl_ulong k_nb1 = k->nb[1]; - cl_ulong k_nb2 = k->nb[2]; - cl_ulong k_nb3 = k->nb[3]; + cl_int err = CL_SUCCESS; + cl_image_format fmt = {}; + fmt.image_channel_order = CL_RGBA; + fmt.image_channel_data_type = CL_HALF_FLOAT; - cl_mem v_data_device = extra_v->data_device; - cl_ulong offset_v = extra_v->offset + v->view_offs; - cl_ulong v_nb1 = v->nb[1]; - cl_ulong v_nb2 = v->nb[2]; - cl_ulong v_nb3 = v->nb[3]; + cl_image_desc desc_src = {}; + desc_src.image_type = CL_MEM_OBJECT_IMAGE2D; + desc_src.image_width = static_cast(N); + desc_src.image_height = static_cast(kpack); + cl_mem src_img = clCreateImage(backend_ctx->context, CL_MEM_READ_WRITE, &fmt, &desc_src, nullptr, &err); + CL_CHECK(err); - const cl_ulong o_nb1 = dst->nb[1]; - const cl_ulong o_nb2 = dst->nb[2]; - const cl_ulong o_nb3 = dst->nb[3]; + cl_image_desc desc_dst = {}; + desc_dst.image_type = CL_MEM_OBJECT_IMAGE2D; + desc_dst.image_width = static_cast(N); + desc_dst.image_height = static_cast(npack); + cl_mem dst_img = clCreateImage(backend_ctx->context, CL_MEM_READ_WRITE, &fmt, &desc_dst, nullptr, &err); + CL_CHECK(err); - const cl_ulong mask_nb1 = mask ? mask->nb[1] : 0; - const cl_ulong mask_nb2 = mask ? mask->nb[2] : 0; - const cl_ulong mask_nb3 = mask ? mask->nb[3] : 0; - const int mask_ne2 = mask ? mask->ne[2] : 0; - const int mask_ne3 = mask ? mask->ne[3] : 0; + cl_mem weights = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, weight_bytes, nullptr, &err); + CL_CHECK(err); - float * params = (float *)dst->op_params; - float scale = params[0]; - float max_bias = params[1]; - float logit_softcap = params[2]; + cl_kernel prepack = backend_ctx->kernel_adreno_xmem_prepack_weight_f16; + CL_CHECK(clSetKernelArg(prepack, 0, sizeof(cl_mem), &weights)); + CL_CHECK(clSetKernelArg(prepack, 1, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(prepack, 2, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(prepack, 3, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(prepack, 4, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(prepack, 5, sizeof(int), &kpack)); + CL_CHECK(clSetKernelArg(prepack, 6, sizeof(int), &npack_padded)); + CL_CHECK(clSetKernelArg(prepack, 7, sizeof(int), &os)); + size_t lws = 256; + size_t max_wg = backend_ctx->get_kernel_workgroup_size(prepack); + if (lws > max_wg) { + lws = max_wg; + } + size_t gws = CEIL_DIV(static_cast(kpack) * static_cast(npack_padded), lws) * lws; + backend_ctx->enqueue_ndrange_kernel(prepack, 1, &gws, &lws, dst); - const int is_causal = (mask == NULL && n_q > 1 && n_q == n_kv); // redundant n_q > 1 check ? + cl_kernel pack_src = backend_ctx->kernel_adreno_xmem_pack_src_f32; + CL_CHECK(clSetKernelArg(pack_src, 0, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(pack_src, 1, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(pack_src, 2, sizeof(cl_mem), &src_img)); + CL_CHECK(clSetKernelArg(pack_src, 3, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(pack_src, 4, sizeof(int), &N)); + size_t pack_src_lws[2] = { 16, 16 }; + size_t pack_src_gws[2] = { + CEIL_DIV(static_cast(N), pack_src_lws[0])*pack_src_lws[0], + CEIL_DIV(static_cast(kpack), pack_src_lws[1])*pack_src_lws[1] + }; + backend_ctx->enqueue_ndrange_kernel(pack_src, 2, pack_src_gws, pack_src_lws, dst); - const int n_head_log2_val = n_head > 0 ? 1u << (int)floorf(log2f((float)n_head)) : 0; - const float n_head_log2_f = n_head_log2_val > 0 ? (float)n_head_log2_val : 1.0f; - const float m0 = powf(2.0f, -(max_bias) / n_head_log2_f); - const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2_f); + cl_kernel gemm = backend_ctx->kernel_gemm_xmem_f16_f32_os8; + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &weights)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &backend_ctx->prealloc_adreno_xmem_const.buffer)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &src_img)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &dst_img)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(int), &npack)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(int), &kpack)); + const size_t z_values = CEIL_DIV(static_cast(npack), static_cast(os)); + size_t gemm_lws[3] = { 64, 1, 1 }; + size_t gemm_gws[3] = { + z_values*gemm_lws[0], + CEIL_DIV(static_cast(N), gemm_lws[0]), + 1 + }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, gemm_gws, gemm_lws, dst); - const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; + cl_kernel store_dst = backend_ctx->kernel_adreno_xmem_store_dst_f32; + CL_CHECK(clSetKernelArg(store_dst, 0, sizeof(cl_mem), &dst_img)); + CL_CHECK(clSetKernelArg(store_dst, 1, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(store_dst, 2, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(store_dst, 3, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(store_dst, 4, sizeof(int), &N)); + size_t store_lws[2] = { 16, 16 }; + size_t store_gws[2] = { + CEIL_DIV(static_cast(N), store_lws[0])*store_lws[0], + CEIL_DIV(static_cast(npack), store_lws[1])*store_lws[1] + }; + backend_ctx->enqueue_ndrange_kernel(store_dst, 2, store_gws, store_lws, dst); - ggml_cl_flash_attn_temp_buffer temp_k; - ggml_cl_flash_attn_temp_buffer temp_v; - ggml_cl_flash_attn_temp_buffer temp_k_aos; - ggml_cl_flash_attn_temp_buffer temp_v_aos; + CL_CHECK(clReleaseMemObject(weights)); + CL_CHECK(clReleaseMemObject(dst_img)); + CL_CHECK(clReleaseMemObject(src_img)); +} +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - if (is_q8_0) { - ggml_cl_flash_attn_reconstruct_aos( - backend_ctx, k, temp_k_aos, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); +static void ggml_cl_conv_2d(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_TENSOR_BINARY_OP_LOCALS; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_cl_flash_attn_reconstruct_aos( - backend_ctx, v, temp_v_aos, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - bool k_done = ggml_cl_flash_attn_dequant_kv_gpu( - backend_ctx, k, GGML_TYPE_F16, k_data_device, offset_k, k_nb1, k_nb2, k_nb3, - temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - bool v_done = ggml_cl_flash_attn_dequant_kv_gpu( - backend_ctx, v, GGML_TYPE_F16, v_data_device, offset_v, v_nb1, v_nb2, v_nb3, - temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + const cl_uint Cout = ne03; + const cl_uint Cin = ne02; + const cl_uint N = ne13; + const cl_uint KW = ne00; + const cl_uint KH = ne01; + const cl_uint W = ne10; + const cl_uint H = ne11; + const cl_uint OW = ne0; + const cl_uint OH = ne1; - GGML_ASSERT(k_done && v_done); - } + const cl_uint s0 = dst->op_params[0]; + const cl_uint s1 = dst->op_params[1]; + const cl_uint p0 = dst->op_params[2]; + const cl_uint p1 = dst->op_params[3]; + const cl_uint d0 = dst->op_params[4]; + const cl_uint d1 = dst->op_params[5]; - // Allocate input/output memory buffers - cl_mem mem_matrixQ; - cl_mem mem_matrixK; - cl_mem mem_matrixV; - cl_mem mem_matrixO; - cl_buffer_region region; - cl_int err; + const cl_uint cl_nb00 = nb00/ggml_type_size(src0->type); + const cl_uint cl_nb01 = nb01/ggml_type_size(src0->type); + const cl_uint cl_nb02 = nb02/ggml_type_size(src0->type); + const cl_uint cl_nb03 = nb03/ggml_type_size(src0->type); + const cl_uint cl_nb10 = nb10/ggml_type_size(src1->type); + const cl_uint cl_nb11 = nb11/ggml_type_size(src1->type); + const cl_uint cl_nb12 = nb12/ggml_type_size(src1->type); + const cl_uint cl_nb13 = nb13/ggml_type_size(src1->type); + const cl_uint cl_nb1 = nb1/ggml_type_size(dst->type); + const cl_uint cl_nb2 = nb2/ggml_type_size(dst->type); + const cl_uint cl_nb3 = nb3/ggml_type_size(dst->type); - region.origin = offset_q; - region.size = ggml_nbytes(q); - mem_matrixQ = clCreateSubBuffer(extra_q->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + const int64_t NPQ = (int64_t)N * OW * OH; - region.origin = offset_k; - region.size = is_q8_0 ? (size_t) k_nb3 * (size_t) k->ne[3] : ggml_nbytes(k); - mem_matrixK = clCreateSubBuffer(k_data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + const uint32_t BS_K = 64; + const uint32_t BS_NPQ = 64; + const uint32_t BS_CRS = 16; + const uint32_t VEC_SIZE = 4; - region.origin = offset_v; - region.size = is_q8_0 ? (size_t) v_nb3 * (size_t) v->ne[3] : ggml_nbytes(v); - mem_matrixV = clCreateSubBuffer(v_data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + const uint32_t TS_K = 4; + const uint32_t TS_NPQ = 8; - region.origin = offset_o; - region.size = ggml_nbytes(dst); - mem_matrixO = clCreateSubBuffer(extra_o->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + const uint32_t WG_K = BS_K / TS_K; + const uint32_t WG_NPQ = BS_NPQ / TS_NPQ; - cl_image_format img_fmt_1d = { CL_RGBA, CL_FLOAT}; - cl_image_desc img_desc_1d; + auto splitWork = [](uint32_t work_size, uint32_t block_size) { return (block_size + work_size - 1) / block_size; }; + const uint32_t NB_K = splitWork(Cout, BS_K); + const uint32_t NB_NPQ = splitWork(NPQ, BS_NPQ); - // use image 1d buffer used as fallback when on mask is applied - cl_mem mem_tex_mask_fallback_1dbuf; - img_fmt_1d = { CL_RGBA, CL_HALF_FLOAT}; - memset(&img_desc_1d, 0, sizeof(img_desc_1d)); - img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_1d.image_width = 1; - img_desc_1d.buffer = mem_matrixK; - mem_tex_mask_fallback_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &err); - CL_CHECK(err); + cl_kernel kernel; + size_t shmem_size; - cl_mem mem_tex_matrixO_1dbuf; - img_fmt_1d = { CL_RGBA, CL_FLOAT}; - memset(&img_desc_1d, 0, sizeof(img_desc_1d)); - img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_1d.image_width = ggml_nbytes(dst) / 4 / 4; - img_desc_1d.buffer = mem_matrixO; - mem_tex_matrixO_1dbuf = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &err); - CL_CHECK(err); + if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_conv_2d_f16; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_half4)); + } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_float) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f16_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else { + GGML_ASSERT(false && "Unsupported data type combination for conv2d"); + } - // The bin kernel requires 2d (or 3d) buffers packed for data loading/multiplication. - // These repack kernels launch across all buffers to ensure compatibility - cl_mem mem_tex_matrixMask_1dbuf = NULL; - cl_mem mem_matrixMask = NULL; - cl_mem mem_matrixMask_padded = NULL; - cl_ulong mask_nb1_padded = mask_nb1, mask_nb2_padded = mask_nb2, mask_nb3_padded = mask_nb3; - if (extra_mask) { - // allocate mem_matrixMask w/ new padded size - size_t n_kv_padded = GGML_PAD(n_kv, 4); - size_t mask_nb_padded = n_kv_padded * sizeof(cl_half) * mask->ne[1] * mask->ne[2] * mask->ne[3]; + cl_uint idx = 0; + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, idx++, shmem_size, NULL)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cout)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cin)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &N)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KW)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &W)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &H)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OW)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb00)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb01)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb02)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb03)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb10)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb11)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb12)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb13)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb2)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb3)); - // apply offset and create subBuffer for mask - region.origin = offset_mask; - region.size = ggml_nbytes(mask); - mem_matrixMask = clCreateSubBuffer(extra_mask->data_device, CL_MEM_READ_WRITE, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + size_t global_work_size[] = { (size_t)NB_K * WG_K, (size_t)NB_NPQ * WG_NPQ, 1 }; + size_t local_work_size[] = { (size_t)WG_K, (size_t)WG_NPQ, 1 }; - { - // create padded mask to contain all data - mem_matrixMask_padded = clCreateBuffer(context, CL_MEM_ALLOC_HOST_PTR, mask_nb_padded, NULL, &err); - CL_CHECK(err); + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); +} - // pass extra_mask->data_device, mem_matrixMask to kernel for copying/padding - mask_nb1_padded = (cl_ulong)n_kv_padded * sizeof(cl_half); - mask_nb2_padded = mask_nb1_padded * (cl_ulong)mask->ne[1]; - mask_nb3_padded = mask_nb2_padded * (cl_ulong)mask->ne[2]; +static void ggml_cl_conv2_dw(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_TENSOR_BINARY_OP_LOCALS; + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; - cl_kernel repack_mask = backend_ctx->fa.kernel_repack_mask_for_wmm; - CL_CHECK(clSetKernelArg(repack_mask, 0, sizeof(cl_mem), &mem_matrixMask)); - CL_CHECK(clSetKernelArg(repack_mask, 1, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(repack_mask, 2, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(repack_mask, 3, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(repack_mask, 4, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(repack_mask, 5, sizeof(cl_mem), &mem_matrixMask_padded)); - CL_CHECK(clSetKernelArg(repack_mask, 6, sizeof(cl_ulong), &mask_nb1_padded)); - CL_CHECK(clSetKernelArg(repack_mask, 7, sizeof(cl_ulong), &mask_nb2_padded)); - CL_CHECK(clSetKernelArg(repack_mask, 8, sizeof(cl_ulong), &mask_nb3_padded)); + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *) src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; - size_t repack_mask_gws[3] = {(size_t)n_kv, (size_t)mask->ne[1], (size_t)mask_ne2 * (size_t)mask->ne[3]}; - backend_ctx->enqueue_ndrange_kernel(repack_mask, 3, repack_mask_gws, NULL, dst); - } + const cl_long offset0 = extra0->offset + src0->view_offs; + const cl_long offset1 = extra1->offset + src1->view_offs; + const cl_long offsetd = extrad->offset + dst->view_offs; + + const cl_long C = ne12; + const cl_long N = ne13; + const cl_long KW = ne00; + const cl_long KH = ne01; + const cl_long W = ne10; + const cl_long H = ne11; + const cl_long OW = ne0; + const cl_long OH = ne1; + + const cl_int s0 = dst->op_params[0]; + const cl_int s1 = dst->op_params[1]; + const cl_int p0 = dst->op_params[2]; + const cl_int p1 = dst->op_params[3]; + const cl_int d0 = dst->op_params[4]; + const cl_int d1 = dst->op_params[5]; + + const cl_long cl_nb01 = nb01/ggml_type_size(src0->type); + const cl_long cl_nb03 = nb03/ggml_type_size(src0->type); + const cl_long cl_nb11 = nb11/ggml_type_size(src1->type); + const cl_long cl_nb12 = nb12/ggml_type_size(src1->type); + const cl_long cl_nb13 = nb13/ggml_type_size(src1->type); + const cl_long cl_nb1 = nb1/ggml_type_size(dst->type); + const cl_long cl_nb2 = nb2/ggml_type_size(dst->type); + const cl_long cl_nb3 = nb3/ggml_type_size(dst->type); - // use image 1d buffer for matrix Mask (padded row stride) - cl_image_format img_fmt_mask_1d = { CL_RGBA, CL_HALF_FLOAT}; - cl_image_desc img_desc_mask_1d; - memset(&img_desc_mask_1d, 0, sizeof(img_desc_mask_1d)); - img_desc_mask_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_mask_1d.image_width = mask_nb_padded / 2 / 4; - img_desc_mask_1d.buffer = mem_matrixMask_padded; - mem_tex_matrixMask_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_mask_1d, &img_desc_mask_1d, NULL, &err); - CL_CHECK(err); + cl_kernel kernel; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv2d_dw_f32_f32; + } else if (src0->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_conv2d_dwf16_f32; + } else { + GGML_ASSERT(false && "Unsupported data type combination for conv2_dw"); } - // WMM QK uses repacked 3D images. - // Q image: rows, heads, packed depth. - cl_image_format img_fmt_3d = { CL_RGBA, CL_HALF_FLOAT }; - cl_image_desc img_desc_3d; + cl_uint idx = 0; + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &offset0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &offset1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &C)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &N)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &KW)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &KH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &W)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &H)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &OW)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &OH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &s0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &s1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &p0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &p1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &d0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_int), &d1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb01)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb03)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb11)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb12)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb13)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb2)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_long), &cl_nb3)); + + const size_t total = (size_t) N * C * OH * OW; + const size_t local_size = MIN((size_t) 256, backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global_work_size[] = { CEIL_DIV(total, local_size) * local_size }; + size_t local_work_size[] = { local_size }; - memset(&img_desc_3d, 0, sizeof(img_desc_3d)); - img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; - img_desc_3d.image_width = (size_t)n_q; - img_desc_3d.image_height = (size_t)n_batch * (size_t)n_head; - img_desc_3d.image_depth = (size_t)d_head_q / 4; - cl_mem img_q_wmm = NULL; - img_q_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); - CL_CHECK(err); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size, dst); +} - { - cl_kernel repack_q = backend_ctx->fa.kernel_repack_q_for_wmm; - CL_CHECK(clSetKernelArg(repack_q, 0, sizeof(cl_mem), &mem_matrixQ)); - CL_CHECK(clSetKernelArg(repack_q, 1, sizeof(cl_ulong), &q_nb1)); - CL_CHECK(clSetKernelArg(repack_q, 2, sizeof(cl_ulong), &q_nb2)); - CL_CHECK(clSetKernelArg(repack_q, 3, sizeof(cl_ulong), &q_nb3)); - CL_CHECK(clSetKernelArg(repack_q, 4, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(repack_q, 5, sizeof(cl_mem), &img_q_wmm)); +// is_kq selects which of the two products this call is, and it is decided by the +// CALLER -- the two admission arms in ggml_cl_mul_mat, each of which knows which +// one it matched. It used to be re-derived here from nb01 > nb02, i.e. "K is +// head-major, V^T is not". That discriminator COLLAPSES at n_head_kv == 1, where +// the two strides are equal because there is only one head to order, so nothing +// here could tell a KQ from a KQV. Pass it in rather than infer it. +static void ggml_cl_mul_mat_kq_kqv_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, bool is_kq) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - size_t repack_q_gws[3] = {(size_t)d_head_q / 4, (size_t)n_q, (size_t)n_batch * (size_t)n_head}; - backend_ctx->enqueue_ndrange_kernel(repack_q, 3, repack_q_gws, NULL, dst); - } + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - // K image: columns, row groups, KV heads. - const size_t n_kv_row4 = ((size_t)n_kv + 3) / 4; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; - memset(&img_desc_3d, 0, sizeof(img_desc_3d)); - img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; - img_desc_3d.image_width = (size_t)d_head_q; - img_desc_3d.image_height = n_kv_row4; - img_desc_3d.image_depth = (size_t)n_batch * (size_t)n_head_kv; - cl_mem img_k_wmm = NULL; - img_k_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); - CL_CHECK(err); + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; - { - cl_kernel repack_k = backend_ctx->fa.kernel_repack_k_for_wmm; - CL_CHECK(clSetKernelArg(repack_k, 0, sizeof(cl_mem), &mem_matrixK)); - CL_CHECK(clSetKernelArg(repack_k, 1, sizeof(cl_ulong), &k_nb1)); - CL_CHECK(clSetKernelArg(repack_k, 2, sizeof(cl_ulong), &k_nb2)); - CL_CHECK(clSetKernelArg(repack_k, 3, sizeof(cl_ulong), &k_nb3)); - CL_CHECK(clSetKernelArg(repack_k, 4, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(repack_k, 5, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(repack_k, 6, sizeof(cl_mem), &img_k_wmm)); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; - size_t repack_k_gws[3] = {(size_t)d_head_q, n_kv_row4, (size_t)n_batch * (size_t)n_head_kv}; - backend_ctx->enqueue_ndrange_kernel(repack_k, 3, repack_k_gws, NULL, dst); - } + const cl_ulong nb10 = src1->nb[0]; - // V image: kv-rows (contracted), packed head-dim groups, KV heads. - memset(&img_desc_3d, 0, sizeof(img_desc_3d)); - img_desc_3d.image_type = CL_MEM_OBJECT_IMAGE3D; - img_desc_3d.image_width = (size_t)n_kv; - img_desc_3d.image_height = (size_t)d_head_v / 4; - img_desc_3d.image_depth = (size_t)n_batch * (size_t)n_head_kv; - cl_mem img_v_wmm = NULL; - img_v_wmm = clCreateImage(context, CL_MEM_READ_WRITE, &img_fmt_3d, &img_desc_3d, NULL, &err); - CL_CHECK(err); + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; - { - cl_kernel repack_v = backend_ctx->fa.kernel_repack_v_for_wmm; - CL_CHECK(clSetKernelArg(repack_v, 0, sizeof(cl_mem), &mem_matrixV)); - CL_CHECK(clSetKernelArg(repack_v, 1, sizeof(cl_ulong), &v_nb1)); - CL_CHECK(clSetKernelArg(repack_v, 2, sizeof(cl_ulong), &v_nb2)); - CL_CHECK(clSetKernelArg(repack_v, 3, sizeof(cl_ulong), &v_nb3)); - CL_CHECK(clSetKernelArg(repack_v, 4, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(repack_v, 5, sizeof(cl_mem), &img_v_wmm)); + GGML_ASSERT(ne00 == ne10); - size_t repack_v_gws[3] = {(size_t)d_head_v / 4, (size_t)n_kv, (size_t)n_batch * (size_t)n_head_kv}; - backend_ctx->enqueue_ndrange_kernel(repack_v, 3, repack_v_gws, NULL, dst); - } + cl_kernel kernel; + cl_context context = backend_ctx->context; - cl_int enable_mask = (extra_mask) ? 1 : 0; - mask_buffer = extra_mask ? mem_tex_matrixMask_1dbuf : mem_tex_mask_fallback_1dbuf; + cl_int status; + cl_image_format img_fmt_1d; + cl_image_desc img_desc_1d; + cl_buffer_region region; + cl_mem A_image1d; + cl_mem A_sub_buffer; + cl_mem B_sub_buffer; + cl_mem D_image1d; + cl_mem D_sub_buffer; - cl_mem mem_sinksBuf = NULL; - cl_mem mem_tex_sinks_1dbuf = NULL; - cl_int enable_sinks = (sinks_buffer != NULL) ? 1 : 0; - if (enable_sinks) { - region.origin = offset_sinks; - region.size = ggml_nbytes(sinks); - mem_sinksBuf = clCreateSubBuffer(extra_sinks->data_device, CL_MEM_READ_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); - CL_CHECK(err); + int M = ne01; + int N = ne1; + int K = ne00; - cl_image_format img_fmt_sinks_1d = { CL_R, CL_FLOAT }; - cl_image_desc img_desc_sinks_1d; - memset(&img_desc_sinks_1d, 0, sizeof(img_desc_sinks_1d)); - img_desc_sinks_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_sinks_1d.image_width = (size_t)n_head; - img_desc_sinks_1d.buffer = mem_sinksBuf; - mem_tex_sinks_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_sinks_1d, &img_desc_sinks_1d, NULL, &err); - CL_CHECK(err); + kernel = is_kq ? backend_ctx->kernel_mul_mm_f16_f32_kq + : backend_ctx->kernel_mul_mm_f16_f32_kqv; + // create sub-buffer for A + // <--------------------------------------------> // + extra0 = src0->view_src ? (ggml_tensor_extra_cl *)src0->view_src->extra : (ggml_tensor_extra_cl *)src0->extra; + + region.origin = (extra0->offset + src0->view_offs); + if (is_kq) { + // KQ + region.size = nb01 * ne01; } else { - // The image obj cannot be null so we back with buffer of size 1 and use matrixK to back because it always exists - cl_image_format img_fmt_sinks_fallback = { CL_R, CL_FLOAT }; - cl_image_desc img_desc_sinks_fallback; - memset(&img_desc_sinks_fallback, 0, sizeof(img_desc_sinks_fallback)); - img_desc_sinks_fallback.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_sinks_fallback.image_width = 1; - img_desc_sinks_fallback.buffer = mem_matrixK; - mem_tex_sinks_1dbuf = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_sinks_fallback, &img_desc_sinks_fallback, NULL, &err); - CL_CHECK(err); + // KQV + region.size = nb02 * ne02; } - cl_uint arg = 0; + A_sub_buffer = clCreateSubBuffer((extra0->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); + CL_CHECK(status); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mem_tex_matrixO_1dbuf)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &is_causal)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb1)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb2)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &q_nb3)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb1)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb2)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &k_nb3)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb1)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb2)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &v_nb3)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb1)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb2)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &o_nb3)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &max_bias)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &m0)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &m1)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head_log2_val)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(float), &logit_softcap)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mask_buffer)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &enable_mask)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb1_padded)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb2_padded)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_ulong), &mask_nb3_padded)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &mask_ne3)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &mem_tex_sinks_1dbuf)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &enable_sinks)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_q_wmm)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_k_wmm)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(cl_mem), &img_v_wmm)); - CL_CHECK(clSetKernelArg(kernel, arg++, sizeof(int), &d_head_q)); + // <--------------------------------------------> // - size_t global_work_size[3], local_work_size[3]; + // create sub-buffer for B + // <--------------------------------------------> // + region.origin = (extra1->offset + src1->view_offs); + region.size = nb10 * ne10 * ne11 * ne12; + B_sub_buffer = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); + CL_CHECK(status); + // <--------------------------------------------> // + + img_fmt_1d = {CL_RGBA, CL_FLOAT}; + memset(&img_desc_1d, 0, sizeof(img_desc_1d)); + img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + if (is_kq) { + img_desc_1d.image_width = (nb01 * ne01 / 4)/4; + } + else { + img_desc_1d.image_width = (nb02 * ne02 / 4)/4; + } + img_desc_1d.buffer = A_sub_buffer; + A_image1d = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &status); + CL_CHECK(status); + + // create sub-buffer for output C + // <--------------------------------------------> // + region.origin = (extrad->offset + dst->view_offs); + region.size = ne0 * ne1 * dst->ne[2] * dst->nb[0]; // size of C in bytes + D_sub_buffer = clCreateSubBuffer((extrad->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); + CL_CHECK(status); + // <--------------------------------------------> // + + // create image for C output + // <--------------------------------------------> // + img_fmt_1d = {CL_R, CL_FLOAT}; + memset(&img_desc_1d, 0, sizeof(img_desc_1d)); + img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc_1d.image_width = ne0 * ne1 * dst->ne[2] * dst->nb[0] / 4; + img_desc_1d.buffer = D_sub_buffer; + D_image1d = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &status); + CL_CHECK(status); + // <--------------------------------------------> // - const int n_waves_v = d_head_q / 64; + int offset_src0 = 0; + int offset_src1 = 0; - local_work_size[0] = 64; - local_work_size[1] = n_waves_v; - local_work_size[2] = 1; + // set kernel args + // <--------------------------------------------> // + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &A_image1d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &offset_src0)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &B_sub_buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &offset_src1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &D_image1d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &extrad->offset)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &nb01)); - global_work_size[0] = 64; - global_work_size[1] = ((n_q + 64 - 1) / 64) * n_waves_v; - global_work_size[2] = n_batch * n_head; + size_t global_work_size[3] = {64, static_cast(((M+63)/64)), static_cast(((N+31)/32)*ne12)}; + size_t local_work_size[3] = {64, 1, 2}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(mem_tex_matrixO_1dbuf)); - CL_CHECK(clReleaseMemObject(img_q_wmm)); - CL_CHECK(clReleaseMemObject(img_k_wmm)); - CL_CHECK(clReleaseMemObject(img_v_wmm)); - - if (mem_tex_matrixMask_1dbuf) { - CL_CHECK(clReleaseMemObject(mem_tex_matrixMask_1dbuf)); - } - if (mem_matrixMask) { - CL_CHECK(clReleaseMemObject(mem_matrixMask)); - } - if (mem_matrixMask_padded) { - CL_CHECK(clReleaseMemObject(mem_matrixMask_padded)); - } - if (mem_tex_sinks_1dbuf) { - CL_CHECK(clReleaseMemObject(mem_tex_sinks_1dbuf)); - } - if (mem_sinksBuf) { - CL_CHECK(clReleaseMemObject(mem_sinksBuf)); - } - CL_CHECK(clReleaseMemObject(mem_matrixQ)); - CL_CHECK(clReleaseMemObject(mem_matrixK)); - CL_CHECK(clReleaseMemObject(mem_matrixV)); - CL_CHECK(clReleaseMemObject(mem_matrixO)); + // deallocate sub buffers and images + // <--------------------------------------------> // + CL_CHECK(clReleaseMemObject(A_image1d)); + CL_CHECK(clReleaseMemObject(D_image1d)); + CL_CHECK(clReleaseMemObject(A_sub_buffer)); + CL_CHECK(clReleaseMemObject(B_sub_buffer)); + CL_CHECK(clReleaseMemObject(D_sub_buffer)); } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS - -static void ggml_cl_flash_attn(ggml_backend_t backend, const ggml_tensor * q, const ggml_tensor * k, ggml_tensor * dst) { - const ggml_tensor * v = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; - const ggml_tensor * sinks = dst->src[4]; - GGML_ASSERT(q->extra); - GGML_ASSERT(k->extra); - GGML_ASSERT(v->extra); +static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - if (mask) { - GGML_ASSERT(mask->extra); - } - if (sinks) { - GGML_ASSERT(sinks->extra); - } + GGML_ASSERT(src0->type == GGML_TYPE_Q1_0); + GGML_ASSERT(src1->type == GGML_TYPE_F32); ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - const int n_q = q->ne[1]; - const int n_kv = k->ne[1]; - const int d_head_q = q->ne[0]; - const int d_head_v = v->ne[0]; - const int n_head = q->ne[2]; - const int n_head_kv = k->ne[2]; - const int n_batch = q->ne[3]; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q1_0 * extra0_q1_0 = (ggml_tensor_extra_cl_q1_0 *)src0->extra; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (ggml_cl_adreno_xmem_attn_can_use(backend_ctx, q, k, dst)) { - ggml_cl_adreno_xmem_attn_run(backend, q, k, dst); - return; - } -#endif + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - // Compile DK512 decode separately from the prefill programs. - const bool fa_decode_only_512 = (d_head_q == 512); + GGML_ASSERT(src1->view_offs == 0); + GGML_ASSERT(dst->view_offs == 0); - // per-variant lazy compile for this (dk, dv) - // DK=512 decode (n_q==1) needs no prepass - // DK=512 prefill (n_q>1) does, so compile it only when needed - if (!fa_decode_only_512 || n_q > 1) { - ggml_opencl_ensure_fa_pre_kernels(backend_ctx, d_head_q, d_head_v); - } + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; - cl_kernel kernel = NULL; - bool use_prefill_k_img = false; // K is image1d_buffer_t for DK=512 prefill + const int ne10 = src1->ne[0]; + const int ne12 = src1->ne[2]; - const bool is_f16 = q->type == GGML_TYPE_F16; - const bool is_mixed = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && v->type == GGML_TYPE_F16; - const bool is_q8_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q8_0 && v->type == GGML_TYPE_Q8_0; - const bool is_q4_0 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_Q4_0 && v->type == GGML_TYPE_Q4_0; + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (use_fa_bin_kernels_prefill(backend_ctx, q, k, v)) { - // We support the prefill path of flash attn with a specialized d_head = 64/128/256 - ggml_cl_flash_attn_prefill_bin(backend, q, k, dst); - return; - } -#endif + GGML_ASSERT(ne00 == ne10); + GGML_ASSERT((ne00 % 128) == 0); + GGML_ASSERT(ne0 == ne01); - if (is_f16) { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F16); - } else if (is_mixed) { - if (fa_decode_only_512 && n_q == 1) { - GGML_ASSERT(ggml_opencl_ensure_fa_f32_f16_vec_512(backend_ctx)); - } else { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32_F16); - } - if (fa_decode_only_512) { - // DK=512: the BM-tile prefill kernels are specifically compiled from - // FA_PREFILL_ONLY - if (n_q > 1) { - ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/false); - ggml_opencl_ensure_fa_f32_f16_prefill_512(backend_ctx, /*split=*/true); - } - } else { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32_F16_SPLIT); - } - } else if (is_q8_0) { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q8_0); - if (d_head_q == 96 && d_head_v == 96) { - ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 96, 96, /*quant_bm=*/16, /*quant_n_split=*/3, /*is_q8_0=*/true); - } else if (d_head_q == 256 && d_head_v == 256) { - ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 256, 256, /*quant_bm=*/16, /*quant_n_split=*/8, /*is_q8_0=*/true); - } else { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q8_0_SPLIT); - } - } else if (is_q4_0) { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q4_0); - if (d_head_q == 96 && d_head_v == 96) { - ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 96, 96, /*quant_bm=*/16, /*quant_n_split=*/3, /*is_q8_0=*/false); - } else if (d_head_q == 256 && d_head_v == 256) { - ggml_opencl_ensure_fa_quant_split_override(backend_ctx, 256, 256, /*quant_bm=*/16, /*quant_n_split=*/8, /*is_q8_0=*/false); - } else { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_Q4_0_SPLIT); - } - } else { - ggml_opencl_ensure_fa_variant(backend_ctx, d_head_q, d_head_v, FA_VARIANT_F32); - } + cl_context context = backend_ctx->context; + cl_kernel kernel; - const std::pair dk_dv = {d_head_q, d_head_v}; - const int mq_gqa = n_head_kv > 0 ? n_head / n_head_kv : 0; - const std::tuple mq_decode_key = {d_head_q, d_head_v, mq_gqa}; - const bool mq_decode_shape = backend_ctx->gpu_family == ADRENO && is_mixed && n_q == 1 && - d_head_q == d_head_v && n_head_kv > 0 && n_head % n_head_kv == 0 && - ((((d_head_q == 64 && mq_gqa == 8) || (d_head_q == 128 && mq_gqa == 4)) && - backend_ctx->has_subgroup_shuffle) || - ((d_head_q == 256 || d_head_q == 512) && (mq_gqa == 4 || mq_gqa == 8))); - if (mq_decode_shape && n_kv >= 32) { - ggml_opencl_ensure_fa_f32_f16_mq_decode(backend_ctx, d_head_q, d_head_v, mq_gqa); - } - const bool use_native_q8_0_q1 = is_q8_0 && n_q == 1 && - backend_ctx->fa.f32_q8_0_q1.count(dk_dv) > 0; - // Native q8_0 prefill — reads q8_0 directly, wg_size = cfg->bm. - const bool use_native_q8_0 = is_q8_0 && n_q > 1 && - backend_ctx->fa.f32_q8_0.count(dk_dv) > 0; - const bool use_native_q4_0_q1 = is_q4_0 && n_q == 1 && - backend_ctx->fa.f32_q4_0_q1.count(dk_dv) > 0; - const bool use_native_q4_0 = is_q4_0 && n_q > 1 && - backend_ctx->fa.f32_q4_0.count(dk_dv) > 0; - const int block_m = n_q > 1 - ? (is_mixed ? backend_ctx->fa.f32_f16_bm.at(dk_dv) : backend_ctx->fa.bm.at(dk_dv)) - : 0; - // block_n is only used by the n_q > 1 prefill path; its map is not - // populated for DK=512 decode, so do not read it for decode. - const int block_n = (n_q > 1) - ? (is_mixed ? backend_ctx->fa.f32_f16_bn.at(dk_dv) - : backend_ctx->fa.bn.at(dk_dv)) - : 0; - // Pick split variant only when n_kv crosses the per-(dk,dv) threshold. - // the N_SPLIT>1 prefill tile reduces DK partials via subgroup shuffle, - // on Intel it uses the non-split BM tile and does not depend on subgroup size - const bool use_split_kernel = (n_q > 1 && is_mixed && - backend_ctx->gpu_family != INTEL && - backend_ctx->fa.f32_f16_split.count(dk_dv) > 0 && - n_kv >= backend_ctx->fa.f32_f16_split_nkv_threshold.at(dk_dv)); - const bool use_split_q8_0 = (use_native_q8_0 && backend_ctx->gpu_family != INTEL && - backend_ctx->fa.f32_q8_0_split.count(dk_dv) > 0 && - n_kv >= backend_ctx->fa.f32_q8_0_split_nkv_threshold.at(dk_dv)); - const bool use_split_q4_0 = (use_native_q4_0 && backend_ctx->gpu_family != INTEL && - backend_ctx->fa.f32_q4_0_split.count(dk_dv) > 0 && - n_kv >= backend_ctx->fa.f32_q4_0_split_nkv_threshold.at(dk_dv)); - const int wg_size_fa = (n_q > 1 && is_mixed) - ? (use_split_kernel - ? backend_ctx->fa.f32_f16_split_wg_size.at(dk_dv) - : backend_ctx->fa.f32_f16_wg_size.at(dk_dv)) - : block_m; + cl_int err; + cl_image_format img_fmt; + cl_image_desc img_desc; + cl_buffer_region region; - ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *)q->extra; - ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *)mask->extra : NULL; - ggml_tensor_extra_cl * extra_sinks = sinks ? (ggml_tensor_extra_cl *)sinks->extra : NULL; + int M = ne01; + int N = ne1; + int K = ne00; - // SoA q8_0/q4_0 K/V: data_device aliases the `q` subbuffer; reconstruct - // AoS into a temp buffer below. AoS tensors use extra_k/v->data_device. - const bool k_soa = ggml_cl_is_q8_0_soa(k) || ggml_cl_is_q4_0_soa(k); - const bool v_soa = ggml_cl_is_q8_0_soa(v) || ggml_cl_is_q4_0_soa(v); - ggml_tensor_extra_cl * extra_k = k_soa ? nullptr : (ggml_tensor_extra_cl *)k->extra; - ggml_tensor_extra_cl * extra_v = v_soa ? nullptr : (ggml_tensor_extra_cl *)v->extra; + if (ne1 == 1) { + cl_mem q_img = nullptr; + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; - cl_ulong offset_q = extra_q->offset + q->view_offs; - cl_ulong offset_k = k_soa ? 0 : extra_k->offset + k->view_offs; - cl_ulong offset_v = v_soa ? 0 : extra_v->offset + v->view_offs; - cl_ulong offset_o = extra_o->offset + dst->view_offs; - cl_mem mask_buffer = extra_mask ? extra_mask->data_device : NULL; - cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; - cl_mem sinks_buffer = extra_sinks ? extra_sinks->data_device : NULL; - cl_ulong offset_sinks = extra_sinks ? extra_sinks->offset + sinks->view_offs : 0; + // image for q (uint32: each texel packs 32 sign bits) + img_fmt = { CL_R, CL_UNSIGNED_INT32}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 32; + img_desc.buffer = extra0_q1_0->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - const cl_ulong q_nb1 = q->nb[1]; - const cl_ulong q_nb2 = q->nb[2]; - const cl_ulong q_nb3 = q->nb[3]; + // create a sub_buffer for B + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - cl_ulong k_nb1 = k->nb[1]; - cl_ulong k_nb2 = k->nb[2]; - cl_ulong k_nb3 = k->nb[3]; + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - cl_ulong v_nb1 = v->nb[1]; - cl_ulong v_nb2 = v->nb[2]; - cl_ulong v_nb3 = v->nb[3]; + // Tall M has enough row parallelism to skip the K split and its reduction. + const bool use_nsg1 = backend_ctx->min_m_gemv_nsg1_q1_0 > 0 && M >= backend_ctx->min_m_gemv_nsg1_q1_0; + kernel = use_nsg1 ? backend_ctx->kernel_gemv_noshuffle_q1_0_f32_nsg1 : backend_ctx->kernel_gemv_noshuffle_q1_0_f32; - const cl_ulong o_nb1 = dst->nb[1]; - const cl_ulong o_nb2 = dst->nb[2]; - const cl_ulong o_nb3 = dst->nb[3]; + int r2 = 1; + int r3 = 1; - const cl_ulong mask_nb1 = mask ? mask->nb[1] : 0; - const cl_ulong mask_nb2 = mask ? mask->nb[2] : 0; - const cl_ulong mask_nb3 = mask ? mask->nb[3] : 0; - const int mask_ne2 = mask ? mask->ne[2] : 0; - const int mask_ne3 = mask ? mask->ne[3] : 0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &extra1->offset)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &extrad->offset)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); - float scale; - float max_bias; - float logit_softcap; + size_t wavesize = backend_ctx->adreno_wave_size; + const size_t nsg = use_nsg1 ? 1 : 4; + size_t local_work_size[] = { wavesize, nsg, 1 }; + size_t global_work_size[] = { CEIL_DIV(M, wavesize)*wavesize, nsg, 1 }; - const float * params = (const float *)dst->op_params; - scale = params[0]; - max_bias = params[1]; - logit_softcap = params[2]; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - bool use_q1_vec = false; - bool use_q1_vec_mq = false; - bool use_local_tile = false; - // KV-head-coalesced gate: gqa_ratio == compile-time MQ_GQA - // restricts to DK=DV=256 for now due to local memory size - const int gqa_ratio_dispatch = n_head_kv > 0 ? (n_head / n_head_kv) : 0; - if (n_q == 1) { - if (use_native_q8_0_q1) { - if (d_head_v >= 256 && - backend_ctx->fa.f32_q8_0_q1_vec.count(dk_dv) > 0) { - kernel = backend_ctx->fa.f32_q8_0_q1_vec.at(dk_dv); - use_q1_vec = true; - } else { - kernel = backend_ctx->fa.f32_q8_0_q1.at(dk_dv); - } - } else if (use_native_q4_0_q1) { - // q4_0 vec kernel uses per-lane dp4a (cl_khr_integer_dot_product) - const char * q4vec_env = getenv("GGML_OPENCL_FA_Q4_VEC"); - const bool q4vec_off = (q4vec_env != NULL) && (q4vec_env[0] == '0'); - if (!q4vec_off && d_head_v >= 256 && - backend_ctx->fa.f32_q4_0_q1_vec.count(dk_dv) > 0) { - kernel = backend_ctx->fa.f32_q4_0_q1_vec.at(dk_dv); - use_q1_vec = true; - } else { - kernel = backend_ctx->fa.f32_q4_0_q1.at(dk_dv); - } - } else if (is_mixed) { - static const char * lt_env = getenv("GGML_OPENCL_FA_LOCAL_TILE"); - static const bool lt_on = (lt_env != NULL) && (lt_env[0] != '0'); - if (lt_on && d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_f16_q1_local_tile.count(dk_dv) > 0) { - kernel = backend_ctx->fa.f32_f16_q1_local_tile.at(dk_dv); - use_local_tile = true; - } else { - static const char * f16_vec_dk128_env = getenv("GGML_OPENCL_FA_F16_VEC_DK128"); - static const bool f16_vec_dk128_off = (f16_vec_dk128_env != NULL) && (f16_vec_dk128_env[0] == '0'); - const int dv_gate = f16_vec_dk128_off ? 256 : 128; - if (d_head_v >= dv_gate && - backend_ctx->fa.f32_f16_q1_vec.count(dk_dv) > 0) { - kernel = backend_ctx->fa.f32_f16_q1_vec.at(dk_dv); - use_q1_vec = true; - } else { - kernel = backend_ctx->fa.f32_f16_q1.at(dk_dv); - } - } - } else if (is_f16) { - kernel = backend_ctx->fa.f16_q1.at(dk_dv); - } else { - kernel = backend_ctx->fa.f32_q1.at(dk_dv); - } + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); } else { - if (use_native_q8_0) { - kernel = use_split_q8_0 - ? backend_ctx->fa.f32_q8_0_split.at(dk_dv) - : backend_ctx->fa.f32_q8_0.at(dk_dv); - } else if (use_native_q4_0) { - kernel = use_split_q4_0 - ? backend_ctx->fa.f32_q4_0_split.at(dk_dv) - : backend_ctx->fa.f32_q4_0.at(dk_dv); - } else if (is_mixed) { - if (use_split_kernel) { - // DK=512 prefill: opt-in texture-cache K reads (image1d_buffer_t). - static const char * pkimg_env = getenv("GGML_OPENCL_FA_PREFILL_K_IMG"); - const bool pkimg_on = (pkimg_env != NULL) && (pkimg_env[0] != '0'); - if (d_head_q == 512 && pkimg_on && - backend_ctx->fa.f32_f16_split_k_img.count(dk_dv) > 0) { - kernel = backend_ctx->fa.f32_f16_split_k_img.at(dk_dv); - use_prefill_k_img = true; - } else { - kernel = backend_ctx->fa.f32_f16_split.at(dk_dv); - } - } else { - kernel = backend_ctx->fa.f32_f16.at(dk_dv); - } - } else if (is_f16) { - kernel = backend_ctx->fa.f16.at(dk_dv); - } else { - kernel = backend_ctx->fa.f32.at(dk_dv); - } - } + cl_mem b_sub_buf = nullptr; + cl_mem b_sub_buf_trans = nullptr; + cl_mem b_img = nullptr; + cl_mem b_img_trans = nullptr; - // Intel goes to the basic q1 kernel - if (backend_ctx->gpu_family == INTEL && n_q == 1) { - use_q1_vec = use_q1_vec_mq = use_local_tile = false; - if (is_mixed && backend_ctx->fa.f32_f16_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_f16_q1.at(dk_dv); } - else if (is_f16 && backend_ctx->fa.f16_q1.count(dk_dv)) { kernel = backend_ctx->fa.f16_q1.at(dk_dv); } - else if (is_q8_0 && backend_ctx->fa.f32_q8_0_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q8_0_q1.at(dk_dv); } - else if (is_q4_0 && backend_ctx->fa.f32_q4_0_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q4_0_q1.at(dk_dv); } - else if (backend_ctx->fa.f32_q1.count(dk_dv)) { kernel = backend_ctx->fa.f32_q1.at(dk_dv); } - } - GGML_ASSERT(kernel != NULL); + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - ggml_cl_flash_attn_temp_buffer temp_k; - ggml_cl_flash_attn_temp_buffer temp_v; - ggml_cl_flash_attn_temp_buffer temp_k_pad; - ggml_cl_flash_attn_temp_buffer temp_v_pad; - ggml_cl_flash_attn_temp_buffer temp_mask_pad; - ggml_cl_flash_attn_temp_buffer temp_blk; - const ggml_type kv_target_type = is_f16 ? GGML_TYPE_F16 : GGML_TYPE_F32; + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - cl_mem k_data_device = k_soa ? NULL : extra_k->data_device; - cl_mem v_data_device = v_soa ? NULL : extra_v->data_device; + // pad N to multiple of 8 + int extra_elements = N % 8; + int padding = 0; + if (extra_elements > 0){ + padding = 8 - extra_elements; + } - // SoA q8_0/q4_0 -> reconstruct AoS for downstream kernels that expect - // tight records (no-op when k/v is already AoS). - ggml_cl_flash_attn_temp_buffer temp_k_aos; - ggml_cl_flash_attn_temp_buffer temp_v_aos; - ggml_cl_flash_attn_reconstruct_aos(backend_ctx, k, temp_k_aos, - k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - ggml_cl_flash_attn_reconstruct_aos(backend_ctx, v, temp_v_aos, - v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + // subbuffer for transposed activations + region.origin = 0; + region.size = K * (N + padding) * sizeof(float)/2; + backend_ctx->prealloc_act_trans.allocate(context, region.size); + CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // currently FA kernels support KV cache with f16, f32, q4_0 and q8_0. - // there two cases that these kernels cannot cover, - // 1. KV cache types are q4_0 or q8_0, but the FA kernels fail to compile - // 2. KV cache types not currently supported by an FA kernel, e.g., q4_1 - // these two cases are supported here by dequantizing to f32/f16 and this - // causes performance degradation. - // For q4_0 or q8_0 cases that fail kernel compilation, dequant happens in GPU; - // for types that do not have FA kernels, dequant happens on host. - if (!use_native_q8_0_q1 && !use_native_q8_0 && - !use_native_q4_0_q1 && !use_native_q4_0) { - // for q4_0, q8_0 FA kernels that fail to compile - bool k_done = false; - bool v_done = false; - if (k->type == GGML_TYPE_Q8_0 || k->type == GGML_TYPE_Q4_0) { - k_done = ggml_cl_flash_attn_dequant_kv_gpu( - backend_ctx, k, kv_target_type, k_data_device, offset_k, k_nb1, k_nb2, k_nb3, - temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - } - if (v->type == GGML_TYPE_Q8_0 || v->type == GGML_TYPE_Q4_0) { - v_done = ggml_cl_flash_attn_dequant_kv_gpu( - backend_ctx, v, kv_target_type, v_data_device, offset_v, v_nb1, v_nb2, v_nb3, - temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); - } - if (!k_done) { - ggml_cl_flash_attn_prepare_quantized_tensor( - backend_ctx, k, kv_target_type, temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - } - if (!v_done) { - ggml_cl_flash_attn_prepare_quantized_tensor( - backend_ctx, v, kv_target_type, temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); - } - // Asymmetric KV on the F32 fallback path: convert the F16 side to F32 - // too. (Symmetric F16 / mixed paths handle F16 directly.) - if (kv_target_type == GGML_TYPE_F32 && !is_mixed && !is_f16) { - ggml_cl_flash_attn_convert_f16_to_f32(backend_ctx, k, temp_k, k_data_device, offset_k, k_nb1, k_nb2, k_nb3); - ggml_cl_flash_attn_convert_f16_to_f32(backend_ctx, v, temp_v, v_data_device, offset_v, v_nb1, v_nb2, v_nb3); + // image for transposed activations + img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * (N + padding) / 4; + img_desc.buffer = b_sub_buf_trans; + CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + + // transpose activations + int height_B = N/4; + if (height_B == 0) { + height_B = 1; } - } + int width_B = K/4; + int padded_height_B = (N + padding)/4; - cl_mem k_pad_buffer = NULL; - cl_mem v_pad_buffer = NULL; - cl_mem mask_pad_buffer = NULL; - cl_mem blk_buffer = NULL; - cl_ulong mask_pad_nb1 = 0; - cl_ulong mask_pad_nb2 = 0; - cl_ulong mask_pad_nb3 = 0; + kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - // Flash-Decoding K-split decision. Resolved here, before the prefill - // prepass, because KV-pad and blk prepass are pure overhead when FD fires. - // Do not infer causality from tensor shapes: a NULL mask means full - // (bidirectional) attention, e.g. ViT encoders, where n_q == n_kv as well. - // Causal attention in llama.cpp always comes with an explicit KQ mask. - // Inferring is_causal here corrupted mmproj output on OpenCL (see #23800). - const int is_causal = 0; - const int fd_max_n_q = (d_head_q <= FD_MAX_DK_MULTI) ? FD_MAX_N_Q_MULTI : 1; - cl_kernel fd_k_split = NULL; - bool use_fd_mq = false; - bool use_fd_mq_decode = false; - int fd_head_sub = 1; - size_t fd_mq_wg = 256; // MQ_GQA=4 kernel: Q1_WG_SIZE(64) * MQ_NSG_SPLIT(4) - bool use_fa_k_img = false; // K bound as image1d_buffer_t instead of (buf, offset) + size_t local_work_size_t[2] = { 1, 16 }; + size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - { - const char * mq_env = getenv("GGML_OPENCL_FA_MQ"); - const bool mq_enabled = (mq_env == NULL) ? true : (mq_env[0] != '0'); - const bool mq_kv_ok = is_mixed || is_q8_0 || is_q4_0; + // gemm + kernel = backend_ctx->kernel_gemm_noshuffle_q1_0_f32; + int padded_N = N + padding; - const char * lmq_env = getenv("GGML_OPENCL_FA_LOCAL_MQ_SPLIT"); - const bool lmq_on = (lmq_env != NULL) && (lmq_env[0] != '0'); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); - static const char * vec_nq_env = getenv("GGML_OPENCL_FA_VEC_NQ"); - static const int N_MAX_VEC_NQ = (vec_nq_env != NULL && vec_nq_env[0] != '\0') - ? atoi(vec_nq_env) : 1; + size_t global_work_size[] = { (size_t)CEIL_DIV(N, 8), (size_t)CEIL_DIV(M, 4), 1 }; + size_t local_work_size[] = { 2, 128, 1 }; - const bool nq_in_vec_range = (n_q >= 1) && (n_q <= N_MAX_VEC_NQ); - const bool nq1_only = (n_q == 1); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - // Cluster-parallel decode default on for Adreno X2E/X1E - static const int c8_env_state = []{ - const char * e = getenv("GGML_OPENCL_FA_C8"); - if (e == NULL || e[0] == '\0') { return -1; } - return (e[0] != '0') ? 1 : 0; - }(); - const bool c8_default_on = backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || - backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E; - const bool c8_f16_on = (c8_env_state >= 0) ? (c8_env_state == 1) : c8_default_on; - // Quant-KV (q4_0/q8_0) GQA4 c8: default-on X2E + X1E - const bool c8_quant_on = (c8_env_state >= 0) ? (c8_env_state == 1) : c8_default_on; - if (mq_enabled && mq_kv_ok && nq_in_vec_range && !is_causal && - backend_ctx->gpu_family != INTEL && - !use_local_tile && - n_kv >= (mq_decode_shape ? 32 : FD_MIN_N_KV) && - backend_ctx->fa.f32_merge.count(dk_dv) > 0) { - if (mq_decode_shape && backend_ctx->fa.f32_f16_mq_decode.count(mq_decode_key) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_mq_decode.at(mq_decode_key); - fd_mq_wg = backend_ctx->fa.f32_f16_mq_decode_wg.at(mq_decode_key); - fd_head_sub = backend_ctx->fa.f32_f16_mq_decode_hs.at(mq_decode_key); - use_fd_mq = true; - use_fd_mq_decode = true; - } else if (nq1_only && lmq_on && is_mixed && d_head_q == 128 && d_head_v == 128 && - gqa_ratio_dispatch == 8 && - backend_ctx->fa.f32_f16_q1_local_mq_split_g8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_local_mq_split_g8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 64; - } else if (nq1_only && lmq_on && is_mixed && d_head_q == 128 && d_head_v == 128 && - gqa_ratio_dispatch == 4 && - backend_ctx->fa.f32_f16_q1_local_mq_split.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_local_mq_split.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 64; - } else if (nq1_only && is_mixed && gqa_ratio_dispatch == 4 && - ((d_head_q == 256 && d_head_v == 256) || - (d_head_q == 128 && d_head_v == 128)) && - backend_ctx->fa.f32_f16_q1_vec_mq_split.count(dk_dv) > 0) { - const bool k_img_on = d_head_q == 128 && d_head_v == 128 && - getenv("GGML_OPENCL_FA_K_IMG") != NULL && - getenv("GGML_OPENCL_FA_K_IMG")[0] != '0' && - backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img.count(dk_dv) > 0; - // Cluster-parallel decode - const bool c8_env = d_head_q == 128 && d_head_v == 128 && c8_f16_on; - if (c8_env && backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.at(dk_dv); - use_fd_mq = true; - } else if (c8_env && backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 128; - } else if (k_img_on) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_k_img.at(dk_dv); - use_fd_mq = true; - use_fa_k_img = true; - } else { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split.at(dk_dv); - use_fd_mq = true; - } - // Cluster-parallel decode, DK=DV=256 GQA=8 - } else if (nq1_only && is_mixed && gqa_ratio_dispatch == 8 && - d_head_q == 256 && d_head_v == 256 && - c8_env_state == 1 && - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c32.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 128; - // Cluster-parallel decode for the g8 - } else if (is_mixed && gqa_ratio_dispatch == 8 && - d_head_q == 128 && d_head_v == 128 && - c8_f16_on && - (backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count(dk_dv) > 0 || - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8_ns2.count(dk_dv) > 0)) { - if (backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8.at(dk_dv); - fd_mq_wg = 192; - } else { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_c8_ns2.at(dk_dv); - fd_mq_wg = 128; - } - use_fd_mq = true; - } else if (is_mixed && gqa_ratio_dispatch == 8 && - d_head_q == 128 && d_head_v == 128 && - getenv("GGML_OPENCL_FA_K_IMG") != NULL && - getenv("GGML_OPENCL_FA_K_IMG")[0] != '0' && - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8_k_img.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 192; - use_fa_k_img = true; - } else if (is_mixed && gqa_ratio_dispatch == 8 && - d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 192; - } else if (nq1_only && is_q8_0 && gqa_ratio_dispatch == 8 && - d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split_g8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 192; - } else if (nq1_only && is_q8_0 && gqa_ratio_dispatch == 4 && - d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_q8_0_q1_vec_mq_split.count(dk_dv) > 0) { - // Cluster-parallel q8_0 GQA4 - if (c8_quant_on && - backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split_c8.at(dk_dv); - fd_mq_wg = 128; - } else { - fd_k_split = backend_ctx->fa.f32_q8_0_q1_vec_mq_split.at(dk_dv); - } - use_fd_mq = true; - } else if (nq1_only && is_q4_0) { - const char * q4_mq_env = getenv("GGML_OPENCL_FA_Q4_MQ"); - const bool q4_mq_on = (q4_mq_env != NULL) && (q4_mq_env[0] != '0'); - // Cluster-parallel q4_0 - const bool q4_c8_on = c8_env_state == 1 && - backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8.count(dk_dv) > 0; - if (q4_c8_on && gqa_ratio_dispatch == 8 && - d_head_q == 64 && d_head_v == 64) { - fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8_c8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 128; - } else if (q4_mq_on && gqa_ratio_dispatch == 8 && - d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_g8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 192; - } else if (gqa_ratio_dispatch == 4 && - d_head_q == 128 && d_head_v == 128 && - backend_ctx->fa.f32_q4_0_q1_vec_mq_split.count(dk_dv) > 0) { - // Cluster-parallel q4_0 GQA4 - if (c8_quant_on && - backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split_c8.at(dk_dv); - fd_mq_wg = 128; - } else { - fd_k_split = backend_ctx->fa.f32_q4_0_q1_vec_mq_split.at(dk_dv); - } - use_fd_mq = true; - } - } - } + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); } - // Intel cluster-parallel decode FA - if (fd_k_split == NULL && backend_ctx->gpu_family == INTEL && n_q == 1 && !is_causal && - is_mixed && gqa_ratio_dispatch == 4 && d_head_q == 128 && d_head_v == 128 && - n_kv >= FD_MIN_N_KV && - getenv("GGML_OPENCL_FA_C8") != NULL && getenv("GGML_OPENCL_FA_C8")[0] != '0' && - backend_ctx->fa.f32_merge.count(dk_dv) > 0) { - if (backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 128; - } else if (backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_c8_ns2.at(dk_dv); - use_fd_mq = true; - fd_mq_wg = 64; - } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif +} + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static bool ggml_cl_mul_mat_q2_0_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q2_0 * extra0 = (ggml_tensor_extra_cl_q2_0 *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_q2_0_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_q2_0_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_Q2_0_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; } - if (fd_k_split == NULL && - n_q >= 1 && n_q <= fd_max_n_q && n_kv >= FD_MIN_N_KV && !is_causal && - d_head_q <= FD_MAX_DK && - backend_ctx->fa.f32_merge.count(dk_dv) > 0) { - if (is_mixed && backend_ctx->fa.f32_f16_q1_split.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_f16_q1_split.at(dk_dv); - } else if (is_q8_0 && backend_ctx->fa.f32_q8_0_q1_split.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q8_0_q1_split.at(dk_dv); - } else if (is_q4_0 && backend_ctx->fa.f32_q4_0_q1_split.count(dk_dv) > 0) { - fd_k_split = backend_ctx->fa.f32_q4_0_q1_split.at(dk_dv); - } + + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} + +static void ggml_cl_mul_mat_q2_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q2_0 * extra0 = (ggml_tensor_extra_cl_q2_0 *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_q2_0_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->q2_0_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; } - const bool use_fd = (fd_k_split != NULL); - const int n_q_blocks = n_q > 1 ? (n_q + block_m - 1) / block_m : 0; - const int n_kv_blocks = (n_kv > 0 && block_n > 0) ? (n_kv + block_n - 1) / block_n : 0; - // KV pad + blk prepass are pure overhead when FD will fire — skip them. - const bool use_mixed_prepass = is_mixed && n_q > 1 && !use_fd; - // make sure prepass kernels are compiled - const bool have_kv_pad = backend_ctx->fa.kv_pad_f16.count(dk_dv) > 0; - const bool have_blk = backend_ctx->fa.blk_f16.count(dk_dv) > 0; - const bool use_kv_pad = use_mixed_prepass && (n_kv % block_n != 0) && have_kv_pad; - // blk prepass: per-KV-tile mask class (0=masked, 1=mixed, 2=unmasked). - // Consumed identically by f32_f16, q8_0 and q4_0 prefill kernels. - const bool use_quant_prepass = (use_native_q8_0 || use_native_q4_0) && !use_fd; - const bool use_blk_mask = (use_mixed_prepass || use_quant_prepass) && mask_buffer != NULL && have_blk; + if (ggml_cl_mul_mat_q2_0_dp4a(backend, src0, src1, dst)) { + return; + } + + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - if (use_kv_pad) { - cl_int err; + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - const size_t k_pad_size = (size_t) k_nb1 * (size_t) block_n * (size_t) n_head_kv * (size_t) n_batch; - temp_k_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, k_pad_size, NULL, &err); - CL_CHECK(err); - k_pad_buffer = temp_k_pad.data; + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - const size_t v_pad_size = (size_t) v_nb1 * (size_t) block_n * (size_t) n_head_kv * (size_t) n_batch; - temp_v_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, v_pad_size, NULL, &err); - CL_CHECK(err); - v_pad_buffer = temp_v_pad.data; + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_q2_0_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - cl_kernel kernel_kv_pad = backend_ctx->fa.kv_pad_f16.at(dk_dv); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 0, sizeof(cl_mem), &k_data_device)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 1, sizeof(cl_ulong), &offset_k)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 2, sizeof(cl_mem), &v_data_device)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 3, sizeof(cl_ulong), &offset_v)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 4, sizeof(cl_mem), &k_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 5, sizeof(cl_mem), &v_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 6, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 7, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 8, sizeof(int), &n_batch)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 9, sizeof(cl_ulong), &k_nb1)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 10, sizeof(cl_ulong), &k_nb2)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 11, sizeof(cl_ulong), &k_nb3)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 12, sizeof(cl_ulong), &v_nb1)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 13, sizeof(cl_ulong), &v_nb2)); - CL_CHECK(clSetKernelArg(kernel_kv_pad, 14, sizeof(cl_ulong), &v_nb3)); +static void ggml_cl_mul_mat_q4_0_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, + const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - size_t global_work_size[] = { (size_t) block_n, (size_t) n_head_kv, (size_t) n_batch }; - backend_ctx->enqueue_ndrange_kernel(kernel_kv_pad, 3, global_work_size, NULL, dst); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - if (mask_buffer != NULL) { - mask_pad_nb1 = (cl_ulong) block_n * (cl_ulong) sizeof(ggml_fp16_t); - mask_pad_nb2 = (cl_ulong) n_q * mask_pad_nb1; - mask_pad_nb3 = (cl_ulong) mask_ne2 * mask_pad_nb2; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; - const size_t mask_pad_size = (size_t) mask_ne3 * (size_t) mask_pad_nb3; - temp_mask_pad.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, mask_pad_size, NULL, &err); - CL_CHECK(err); - mask_pad_buffer = temp_mask_pad.data; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - cl_kernel kernel_mask_pad = backend_ctx->fa.mask_pad_f16.at(dk_dv); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 0, sizeof(cl_mem), &mask_buffer)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 1, sizeof(cl_ulong), &offset_mask)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 2, sizeof(cl_mem), &mask_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 3, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 4, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 5, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 6, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 7, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 8, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(kernel_mask_pad, 9, sizeof(int), &mask_ne3)); + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; - size_t global_work_size_mask[] = { (size_t) block_n, (size_t) n_q, (size_t) (mask_ne2 * mask_ne3) }; - backend_ctx->enqueue_ndrange_kernel(kernel_mask_pad, 3, global_work_size_mask, NULL, dst); - } - } + const int ne1 = dst->ne[1]; - if (use_blk_mask) { - cl_int err; - const size_t blk_size = (size_t) n_kv_blocks * (size_t) n_q_blocks * (size_t) mask_ne2 * (size_t) mask_ne3; - temp_blk.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, blk_size, NULL, &err); - if (err != CL_SUCCESS) { - // Flush before retry — reclaim deferred driver deallocations. - CL_CHECK(clFinish(backend_ctx->queue)); - temp_blk.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, blk_size, NULL, &err); - } - CL_CHECK(err); - blk_buffer = temp_blk.data; + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - cl_kernel kernel_blk = backend_ctx->fa.blk_f16.at(dk_dv); - CL_CHECK(clSetKernelArg(kernel_blk, 0, sizeof(cl_mem), &mask_buffer)); - CL_CHECK(clSetKernelArg(kernel_blk, 1, sizeof(cl_ulong), &offset_mask)); - CL_CHECK(clSetKernelArg(kernel_blk, 2, sizeof(cl_mem), &blk_buffer)); - CL_CHECK(clSetKernelArg(kernel_blk, 3, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel_blk, 4, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel_blk, 5, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(kernel_blk, 6, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(kernel_blk, 7, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(kernel_blk, 8, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(kernel_blk, 9, sizeof(int), &mask_ne3)); + cl_context context = backend_ctx->context; + cl_kernel kernel; - size_t global_work_size_blk[] = { (size_t) n_kv_blocks, (size_t) n_q_blocks, (size_t) (mask_ne2 * mask_ne3) }; - backend_ctx->enqueue_ndrange_kernel(kernel_blk, 3, global_work_size_blk, NULL, dst); - } + cl_int err; + cl_image_format img_fmt; + cl_image_desc img_desc; + cl_buffer_region region; - const int n_head_log2_val = n_head > 0 ? 1u << (int)floorf(log2f((float)n_head)) : 0; - const float n_head_log2_f = n_head_log2_val > 0 ? (float)n_head_log2_val : 1.0f; - const float m0 = powf(2.0f, -(max_bias) / n_head_log2_f); - const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2_f); + int M = ne01; + int N = ne1; + int K = ne00; - if (use_fd) { - static const int fd_env_kv_per_split = []{ - const char * e = getenv("GGML_OPENCL_FD_KV_PER_SPLIT"); - return (e && e[0]) ? atoi(e) : 0; - }(); - static const int fd_env_max_splits = []{ - const char * e = getenv("GGML_OPENCL_FD_MAX_SPLITS"); - return (e && e[0]) ? atoi(e) : 0; - }(); + if (ne1 == 1) { + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; - int fd_kv_per_split = use_fd_mq ? FD_MQ_KV_PER_SPLIT - : (is_mixed ? FD_KV_PER_SPLIT_F16 : FD_KV_PER_SPLIT); - int fd_max_splits = use_fd_mq ? FD_MQ_MAX_SPLITS : FD_MAX_SPLITS; - if (fd_env_kv_per_split > 0) { fd_kv_per_split = fd_env_kv_per_split; } - if (fd_env_max_splits > 0) { fd_max_splits = fd_env_max_splits; } - int n_splits = (n_kv + fd_kv_per_split - 1) / fd_kv_per_split; - if (n_splits < FD_MIN_SPLITS) { n_splits = FD_MIN_SPLITS; } - if (n_splits > fd_max_splits) { n_splits = fd_max_splits; } - if (use_fd_mq_decode) { - const size_t wg_per_split = (size_t) n_head_kv * n_batch; - const size_t wg_target = 4 * (size_t) backend_ctx->fa.compute_units; - while (wg_per_split * n_splits < wg_target && n_splits < fd_max_splits && - n_kv / (n_splits + 1) >= 32) { - n_splits++; - } - } - const int kv_per_split = (n_kv + n_splits - 1) / n_splits; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const int fa_partial_floats = 2 + d_head_v; - const size_t partial_size_bytes = - (size_t) n_batch * n_head * n_q * n_splits * fa_partial_floats * sizeof(float); + img_fmt = { CL_RGBA, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - ggml_cl_flash_attn_temp_buffer temp_partial; - cl_mem partial_buffer; - cl_int err; - if (use_fd_mq_decode) { - auto & pool = backend_ctx->fa.fd_partial; - if (partial_size_bytes > pool.size) { - CL_CHECK(clFinish(backend_ctx->queue)); - pool.allocate(backend_ctx->context, partial_size_bytes); - } - partial_buffer = pool.buffer; - } else { - temp_partial.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, - partial_size_bytes, NULL, &err); - if (err != CL_SUCCESS) { - CL_CHECK(clFinish(backend_ctx->queue)); - temp_partial.data = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, - partial_size_bytes, NULL, &err); - } - CL_CHECK(err); - partial_buffer = temp_partial.data; - } + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &K)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &M)); + + size_t wavesize = backend_ctx->adreno_wave_size; + size_t local_work_size[3] = { wavesize, 4, 1 }; + size_t global_work_size[3] = { (size_t)CEIL_DIV(M, 64) * 64, 4, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); + } else { + const int gemm_tile_n = 64; + int N_pad = (N + gemm_tile_n - 1) & ~(gemm_tile_n - 1); + + cl_mem a_img = extra0_q4_0->q_img; + cl_mem s_img = extra0_q4_0->d_img; + GGML_ASSERT(a_img && s_img && "ILA Q4_0 weight images missing; set_tensor should have built them"); + + static const char * q4_0_bin_dp4a_env = getenv("GGML_OPENCL_Q4_0_BIN_DP4A"); + bool q4_0_bin_dp4a_on = q4_0_bin_dp4a_env + ? (atoi(q4_0_bin_dp4a_env) != 0) + : true; + // dot prod has to be available + q4_0_bin_dp4a_on = backend_ctx->has_integer_dot && q4_0_bin_dp4a_on; + + if (q4_0_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin) { + const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; + const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); + + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + + cl_mem b_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_int tb = (cl_int)((size_t)N * (K / 32)); + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + + cl_mem d_sub = nullptr; + cl_mem d_img = nullptr; + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin; - cl_kernel k_split = fd_k_split; - int argi = 0; - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &extra_q->data_device)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_q)); - if (use_fa_k_img) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t k_bytes_span = - (size_t)(n_kv > 0 ? n_kv - 1 : 0) * (size_t)k_nb1 + - (size_t)(n_head_kv > 0 ? n_head_kv - 1 : 0) * (size_t)k_nb2 + - (size_t)(n_batch > 0 ? n_batch - 1 : 0) * (size_t)k_nb3 + - (size_t)d_head_q * nb00_bytes; - const size_t k_bytes = (k_bytes_span + 7) & ~(size_t)7; - const size_t k_pixels = k_bytes >> 3; - cl_mem k_img = nullptr; - if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { - k_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kq_img_pool, - k_data_device, offset_k, k_bytes, CL_HALF_FLOAT); - } + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &a_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); - // if image creation fails, fallback to buffer based kernels - if (k_img == nullptr) { - if (gqa_ratio_dispatch == 4 && - backend_ctx->fa.f32_f16_q1_vec_mq_split.count(dk_dv) > 0) { - k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split.at(dk_dv); - } else { - k_split = backend_ctx->fa.f32_f16_q1_vec_mq_split_g8.at(dk_dv); - } - use_fa_k_img = false; - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_data_device)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_k)); - } else { - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_img)); - } + size_t local_work_size[3] = { 64, 1, 1 }; + size_t global_work_size[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub)); + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub)); + return; + } + + // Pad B through a zero-filled scratch buffer when N needs + // padding, since the GEMM kernel always reads a full N-tile. + const bool need_pad = N_pad > N; + cl_mem b_sub_buf = nullptr; + cl_mem b_padded = nullptr; + if (need_pad) { + CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, + (size_t)K * N_pad * sizeof(float), NULL, &err), err)); + const float zero = 0.0f; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), + 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, + offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); } else { - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &k_data_device)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_k)); + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); } - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &v_data_device)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_v)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb1)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb2)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &q_nb3)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb1)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb2)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &k_nb3)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb1)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb2)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &v_nb3)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &max_bias)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &m0)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &m1)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head_log2_val)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(float), &logit_softcap)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &mask_buffer)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &offset_mask)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &mask_ne3)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(cl_mem), &partial_buffer)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &n_splits)); - CL_CHECK(clSetKernelArg(k_split, argi++, sizeof(int), &kv_per_split)); - // MQ split kernel uses MQ_NSG_SPLIT subgroups and one WG per (kv_head, batch, split) - // matches Q1_WG_SIZE * NSG (MQ_GQA=4 -> 256; MQ_GQA=8 -> 192) - const size_t fd_wg = use_fd_mq ? fd_mq_wg : 64; - const size_t fd_head_dim = use_fd_mq - ? (size_t)(n_head_kv * fd_head_sub * n_batch) - : (size_t)(n_head * n_batch); - size_t fd_lws[3] = { fd_wg, 1, 1 }; - // gid(2) packs q_idx * n_splits + split_idx. - size_t fd_gws[3] = { fd_wg, fd_head_dim, (size_t)(n_splits * n_q) }; - backend_ctx->enqueue_ndrange_kernel(k_split, 3, fd_gws, fd_lws, dst); + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = need_pad ? (size_t)K * N_pad : (size_t)K * N; + img_desc.buffer = need_pad ? b_padded : b_sub_buf; + cl_mem b_img; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - cl_kernel k_merge = backend_ctx->fa.f32_merge.at(dk_dv); - argi = 0; - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &partial_buffer)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &extra_o->data_device)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &offset_o)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_splits)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb1)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb2)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &o_nb3)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_mem), &sinks_buffer)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(cl_ulong), &offset_sinks)); - CL_CHECK(clSetKernelArg(k_merge, argi++, sizeof(int), &n_q)); + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + cl_mem d_sub_buf; + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const size_t merge_wg = (size_t) (d_head_v / 4); // one lane per float4 - size_t merge_lws[3] = { merge_wg, 1, 1 }; - size_t merge_gws[3] = { merge_wg, (size_t)(n_head * n_batch), (size_t) n_q }; - backend_ctx->enqueue_ndrange_kernel(k_merge, 3, merge_gws, merge_lws, dst); - return; - } + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub_buf; + cl_mem d_img; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - cl_mem prefill_k_img = nullptr; - if (use_prefill_k_img) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t k_bytes_span = - (size_t)(n_kv > 0 ? n_kv - 1 : 0) * (size_t)k_nb1 + - (size_t)(n_head_kv > 0 ? n_head_kv - 1 : 0) * (size_t)k_nb2 + - (size_t)(n_batch > 0 ? n_batch - 1 : 0) * (size_t)k_nb3 + - (size_t)d_head_q * nb00_bytes; - const size_t k_bytes = (k_bytes_span + 7) & ~(size_t)7; - const size_t k_pixels = k_bytes >> 3; - if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { - prefill_k_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kq_img_pool, - k_data_device, offset_k, k_bytes, CL_HALF_FLOAT); - } - if (prefill_k_img == nullptr) { - kernel = backend_ctx->fa.f32_f16_split.at(dk_dv); - use_prefill_k_img = false; - } - } + int line_stride_matrix_A_in_bytes = M * 4; + int line_stride_matrix_S_in_bytes = M * 2; + int line_stride_matrix_B_in_bytes = K * 4; + int line_stride_matrix_C_in_bytes = M * 4; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_q)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), use_prefill_k_img ? &prefill_k_img : &k_data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_k)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &v_data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset_v)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra_o->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset_o)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n_q)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n_kv)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &is_causal)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &n_head)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &q_nb1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &q_nb2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &q_nb3)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &k_nb1)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &k_nb2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &k_nb3)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &v_nb1)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &v_nb2)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &v_nb3)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &o_nb1)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &o_nb2)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &o_nb3)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(float), &max_bias)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(float), &m0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(float), &m1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(int), &n_head_log2_val)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(float), &logit_softcap)); - CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &n_head_kv)); - CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_mem), &mask_buffer)); - CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &offset_mask)); - CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &mask_nb1)); - CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &mask_nb2)); - CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &mask_nb3)); - CL_CHECK(clSetKernelArg(kernel, 36, sizeof(int), &mask_ne2)); - CL_CHECK(clSetKernelArg(kernel, 37, sizeof(int), &mask_ne3)); - CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_mem), &sinks_buffer)); - CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_ulong), &offset_sinks)); - if (n_q > 1 && is_mixed) { - CL_CHECK(clSetKernelArg(kernel, 40, sizeof(cl_mem), &k_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel, 41, sizeof(cl_mem), &v_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel, 42, sizeof(cl_mem), &mask_pad_buffer)); - CL_CHECK(clSetKernelArg(kernel, 43, sizeof(cl_mem), &blk_buffer)); - CL_CHECK(clSetKernelArg(kernel, 44, sizeof(int), &n_kv_blocks)); - CL_CHECK(clSetKernelArg(kernel, 45, sizeof(cl_ulong), &mask_pad_nb1)); - CL_CHECK(clSetKernelArg(kernel, 46, sizeof(cl_ulong), &mask_pad_nb2)); - CL_CHECK(clSetKernelArg(kernel, 47, sizeof(cl_ulong), &mask_pad_nb3)); - } else if (use_native_q8_0 || use_native_q4_0) { - // arg 40 = blk classification buffer (NULL disables prepass opt). - CL_CHECK(clSetKernelArg(kernel, 40, sizeof(cl_mem), &blk_buffer)); - } + int c_offset_for_kernel = 0; + int b_offset_for_kernel = 0; - if (n_q == 1) { - if (use_local_tile) { - const size_t lt_wg = 128; - size_t local_work_size[] = { lt_wg, 1, 1 }; - size_t global_work_size[] = { lt_wg, (size_t) n_head, (size_t) n_batch }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } else { - // q1_vec dispatches with NSG subgroups - const size_t q1_wg = backend_ctx->gpu_family == INTEL ? 32 : 64; - const size_t wg_size = use_q1_vec ? 256 : q1_wg; - const size_t head_dim_global = use_q1_vec_mq - ? (size_t)(n_head_kv * n_batch) - : (size_t)(n_head * n_batch); - size_t local_work_size[] = { wg_size, 1 }; - size_t global_work_size[] = { wg_size, head_dim_global }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin; + + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &a_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &s_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &b_offset_for_kernel)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &c_offset_for_kernel)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_A_in_bytes)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_S_in_bytes)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_B_in_bytes)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_C_in_bytes)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); + + size_t local_work_size[3] = { 64, 2, 2 }; + size_t m_tiles = (size_t)CEIL_DIV(M, 64); + size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_img)); + if (b_sub_buf) { + CL_CHECK(clReleaseMemObject(b_sub_buf)); } - } else if (use_native_q8_0 || use_native_q4_0) { - // Native quant prefill. The split variant may override BLOCK_M - // (e.g. DK=96 quant uses BM=16). - const bool use_split = use_native_q8_0 ? use_split_q8_0 : use_split_q4_0; - int bm; - size_t wg_size; - if (use_split) { - bm = use_native_q8_0 ? backend_ctx->fa.f32_q8_0_split_bm.at(dk_dv) - : backend_ctx->fa.f32_q4_0_split_bm.at(dk_dv); - wg_size = use_native_q8_0 ? backend_ctx->fa.f32_q8_0_split_wg_size.at(dk_dv) - : backend_ctx->fa.f32_q4_0_split_wg_size.at(dk_dv); - } else { - bm = backend_ctx->fa.bm.at(dk_dv); - wg_size = (size_t) bm; + if (b_padded) { + CL_CHECK(clReleaseMemObject(b_padded)); } - size_t local_work_size[] = { wg_size, 1 }; - size_t global_work_size[] = { (size_t)((n_q + bm - 1) / bm) * wg_size, (size_t)(n_head * n_batch) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); - } else { - const size_t wg_size = (size_t) wg_size_fa; - size_t local_work_size[] = { wg_size, 1 }; - size_t global_work_size[] = { (size_t)((n_q + block_m - 1) / block_m) * wg_size, (size_t)(n_head * n_batch) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); } } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + +static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); -static void ggml_cl_mul_mat_f16_f32_tiled(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; - cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int M = src0->ne[1]; - const int N = src1->ne[1]; - const int K = src0->ne[0]; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; - cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_tiled; + const int ne10 = src1->ne[0]; + const int ne12 = src1->ne[2]; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; - // Tiling parameters. These need to be tuned for optimal performance. - // They must match the #defines in the kernel mul_mat_f16_f32.cl. - // - // OPWM / OPWN: Output tile size per Work-Group. A work-group computes a tile of size OPWM x OPWN. - // TPWM / TPWN: Threads per Work-group. This is the work-group size. - // OPTM / OPTN: Output elements per Thread. Each thread computes OPTM x OPTN elements. - // - // The following relationships must hold: - // OPWM = TPWM * OPTM - // OPWN = TPWN * OPTN - // - const int OPWM = 64; - const int OPWN = 64; - const int TPWM = 16; - const int TPWN = 8; + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - size_t local_work_size[2] = { TPWM, TPWN }; - size_t global_work_size[2] = { - (size_t) ((M + OPWM - 1) / OPWM) * TPWM, - (size_t) ((N + OPWN - 1) / OPWN) * TPWN, - }; + cl_context context = backend_ctx->context; + cl_kernel kernel; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); -} + cl_int err; + cl_image_format img_fmt; + cl_image_desc img_desc; + cl_buffer_region region; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static bool ggml_cl_can_use_adreno_xmem_gemm_f16_f32( - const ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * src0, - const ggml_tensor * src1, - const ggml_tensor * dst) { - if (!backend_ctx->adreno_xmem_gemm_enabled) { - return false; - } - if (backend_ctx->gpu_family != GPU_FAMILY::ADRENO) { - return false; - } - if ((src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_BF16) || - src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) { - return false; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1) || !ggml_is_contiguous(dst)) { - return false; - } - if (src0->ne[2] != 1 || src0->ne[3] != 1 || - src1->ne[2] != 1 || src1->ne[3] != 1 || - dst->ne[2] != 1 || dst->ne[3] != 1) { - return false; - } - const int K = src0->ne[0]; - const int M = src0->ne[1]; - const int N = src1->ne[1]; - if (src1->ne[0] != K || dst->ne[0] != M || dst->ne[1] != N) { - return false; - } - if (N <= 1 || M < 64 || N < 16 || K < 64) { - return false; - } - if ((K % 8) != 0) { - return false; - } - const int kpack = K / 4; - const int npack = CEIL_DIV(M, 4); - if (static_cast(N) > backend_ctx->image2d_max_width || - static_cast(kpack) > backend_ctx->image2d_max_height) { - return false; - } - if (static_cast(N) > backend_ctx->image2d_max_width || - static_cast(npack) > backend_ctx->image2d_max_height) { - return false; + int M = ne01; + int N = ne1; + int K = ne00; + + // Multi-column (N=3) verify GEMV for q4_0: route the spec/MTP verify batch + // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- + // zone (gemm_noshuffle_q4_0 is ~50% of MTP decode on a Q4_0 model since q4_0 + // weights have no cok/mc3, unlike q4_K). Reuses the ne1==1 GEMV image setup + // (activation image already sized by N=ne1). Byte-identical. Opt-in via + // GGML_OPENCL_Q40_MC3=1. Per-layer only (ne01 < 32768); q4_0 lm_head doesn't + // occur (token_embd/output stay Q6_K), guard kept for parity with q4_K mc3. + static const bool q40_mc3 = (getenv("GGML_OPENCL_Q40_MC3") != nullptr); + const bool use_q40_mc3 = q40_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); + + const bool use_bin = use_q4_0_bin_kernels(backend_ctx, src0); + + if (use_bin) { + if (use_q40_mc3) { + static bool warned = false; + if (!warned) { + GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q40_MC3 is bypassed by Q4_0 binary kernels\n"); + warned = true; + } + } + // This bin layout is not supported by CoopK. + ggml_cl_mul_mat_q4_0_f32_adreno_ila(backend, src0, src1, dst); + return; } - return true; -} -static void ggml_cl_mul_mat_f16_f32_adreno_xmem( - ggml_backend_t backend, - const ggml_tensor * src0, - const ggml_tensor * src1, - ggml_tensor * dst) { - ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + if (ne1 == 1 || use_q40_mc3) { + cl_mem q_img = nullptr; + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + // image for q + img_fmt = { CL_R, CL_UNSIGNED_INT32}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q4_0->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - const cl_ulong offset0 = extra0->offset + src0->view_offs; - const cl_ulong offset1 = extra1->offset + src1->view_offs; - const cl_ulong offsetd = extrad->offset + dst->view_offs; + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const int K = src0->ne[0]; - const int M = src0->ne[1]; - const int N = src1->ne[1]; - const int kpack = K / 4; - const int npack = CEIL_DIV(M, 4); - const int os = 8; - // Pad weights to the 32-row tiles read by the xmem kernel. - const int npack_padded = CEIL_DIV(npack, os)*os; + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - const size_t xmem_bytes = 6144; - const size_t weight_bytes = static_cast(kpack) * static_cast(npack_padded) * 4u * sizeof(cl_half4); + if (use_q40_mc3) { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_mc3; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne1)); + } else { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32; + if (M == 4096 && K == 4096) { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_4096; + } else if (M == 4096 && K == 11008) { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_11008; + } else if (M == 11008 && K == 4096) { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_11008_1_4096; + } else if (M == 32000 && K == 4096) { + kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32000_1_4096; + } + + int r2 = 1; + int r3 = 1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + } - backend_ctx->prealloc_adreno_xmem_const.allocate(backend_ctx->context, xmem_bytes); + // Small-M mc3 verify is occupancy/latency-bound (too few WGs at small M, so + // its bandwidth falls well short of the FFN matmuls'). Use 8 subgroups (512-WI WGs, half the + // per-lane K-walk) for small M. Layout stride is fixed (4 uints/block), so only + // the K-split count changes; the mc3 kernel reads it via get_local_size(1). The + // ne1==1 base kernel hardcodes N_SIMDGROUP=4, so it always stays at 4. + int mc3_nsg = (use_q40_mc3 && ne01 < 4096) ? 8 : 4; + if (use_q40_mc3) { + // Register pressure can lower the kernel limit below the device limit. + const size_t max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (mc3_nsg > 1 && (size_t)(64 * mc3_nsg) > max_workgroup_size) { + mc3_nsg /= 2; + } + } + size_t local_work_size[3] = {64, (size_t)mc3_nsg, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, (size_t)mc3_nsg, 1}; - cl_int err = CL_SUCCESS; - cl_image_format fmt = {}; - fmt.image_channel_order = CL_RGBA; - fmt.image_channel_data_type = CL_HALF_FLOAT; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - cl_image_desc desc_src = {}; - desc_src.image_type = CL_MEM_OBJECT_IMAGE2D; - desc_src.image_width = static_cast(N); - desc_src.image_height = static_cast(kpack); - cl_mem src_img = clCreateImage(backend_ctx->context, CL_MEM_READ_WRITE, &fmt, &desc_src, nullptr, &err); - CL_CHECK(err); + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); + } else { + // CoopK uses the same untiled weight layout as gemm_noshuffle_q4_0_f32, with K-major Q8_1 activations (K contiguous). + if (ggml_cl_coopk_dp4a_narrow_on(backend_ctx, dst, backend_ctx->rows_coopk_dp4a_q4_0) + && backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c4 != nullptr + && ((N <= 2) ? backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c4) != nullptr) { + cl_mem b_sub_buf = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - cl_image_desc desc_dst = {}; - desc_dst.image_type = CL_MEM_OBJECT_IMAGE2D; - desc_dst.image_width = static_cast(N); - desc_dst.image_height = static_cast(npack); - cl_mem dst_img = clCreateImage(backend_ctx->context, CL_MEM_READ_WRITE, &fmt, &desc_dst, nullptr, &err); - CL_CHECK(err); + const int cols = (N <= 2) ? 2 : 4; + const size_t n_blocks_padded = (size_t)cols * (K / 32); + const size_t size_qa = (size_t)cols * K * sizeof(cl_char); + const size_t size_qa_prev = backend_ctx->prealloc_moe_qa.size; + const size_t size_da_prev = backend_ctx->prealloc_moe_da.size; + backend_ctx->prealloc_moe_qa.allocate(context, size_qa); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks_padded * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_padded * sizeof(cl_half)); + if (backend_ctx->prealloc_moe_qa.size != size_qa_prev) { + const cl_char z8 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_qa.buffer, + &z8, sizeof(z8), 0, backend_ctx->prealloc_moe_qa.size, 0, NULL, NULL)); + } + if (backend_ctx->prealloc_moe_da.size != size_da_prev) { + const cl_half z16 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_da.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_da.size, 0, NULL, NULL)); + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_sa.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_sa.size, 0, NULL, NULL)); + } + + cl_int n_blocks = (cl_int)((size_t)N * (K / 32)); + cl_kernel kernel_quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(kernel_quant, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(kernel_quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 4, sizeof(cl_int), &n_blocks)); + size_t local_work_size_quant[1] = { 64 }; + size_t global_work_size_quant[1] = { (size_t)((((size_t)n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(kernel_quant, 1, global_work_size_quant, local_work_size_quant, dst); + + cl_kernel kernel_coopk = (N <= 2) ? backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q4_0_q8_1_dp4a_c4; + const cl_int n_padded = cols; + CL_CHECK(clSetKernelArg(kernel_coopk, 0, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(kernel_coopk, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel_coopk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_coopk, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_coopk, 6, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(kernel_coopk, 7, sizeof(cl_int), &n_padded)); + CL_CHECK(clSetKernelArg(kernel_coopk, 8, sizeof(cl_int), &K)); + CL_CHECK(clSetKernelArg(kernel_coopk, 9, sizeof(cl_int), &N)); + + const size_t nsg = (size_t)backend_ctx->nsg_coopk_dp4a_q4_0; + size_t local_work_size[3] = { 64, nsg, 1 }; + size_t global_work_size[3] = { (size_t)(M / backend_ctx->rows_coopk_dp4a_q4_0), nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel_coopk, 3, global_work_size, local_work_size, dst); - cl_mem weights = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, weight_bytes, nullptr, &err); - CL_CHECK(err); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } - cl_kernel prepack = backend_ctx->kernel_adreno_xmem_prepack_weight_f16; - CL_CHECK(clSetKernelArg(prepack, 0, sizeof(cl_mem), &weights)); - CL_CHECK(clSetKernelArg(prepack, 1, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(prepack, 2, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(prepack, 3, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(prepack, 4, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(prepack, 5, sizeof(int), &kpack)); - CL_CHECK(clSetKernelArg(prepack, 6, sizeof(int), &npack_padded)); - CL_CHECK(clSetKernelArg(prepack, 7, sizeof(int), &os)); - size_t lws = 256; - size_t max_wg = backend_ctx->get_kernel_workgroup_size(prepack); - if (lws > max_wg) { - lws = max_wg; - } - size_t gws = CEIL_DIV(static_cast(kpack) * static_cast(npack_padded), lws) * lws; - backend_ctx->enqueue_ndrange_kernel(prepack, 1, &gws, &lws, dst); + static const char * q4_0_act_vload4_env = getenv("GGML_OPENCL_Q4_0_DP4A_ACT_VLOAD4"); + const bool q4_0_act_vload4_on = q4_0_act_vload4_env == nullptr || atoi(q4_0_act_vload4_env) != 0; + // Enable dense prefill by default on X2E when the uint4 activation tile is enabled. + static const char * q4_0_dense_dp4a_env = getenv("GGML_OPENCL_Q4_0_DENSE_DP4A"); + bool q4_0_dense_dp4a_on = q4_0_dense_dp4a_env + ? (atoi(q4_0_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E && q4_0_act_vload4_on); + // dot prod has to be available + q4_0_dense_dp4a_on = backend_ctx->has_integer_dot && q4_0_dense_dp4a_on; - cl_kernel pack_src = backend_ctx->kernel_adreno_xmem_pack_src_f32; - CL_CHECK(clSetKernelArg(pack_src, 0, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(pack_src, 1, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(pack_src, 2, sizeof(cl_mem), &src_img)); - CL_CHECK(clSetKernelArg(pack_src, 3, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(pack_src, 4, sizeof(int), &N)); - size_t pack_src_lws[2] = { 16, 16 }; - size_t pack_src_gws[2] = { - CEIL_DIV(static_cast(N), pack_src_lws[0])*pack_src_lws[0], - CEIL_DIV(static_cast(kpack), pack_src_lws[1])*pack_src_lws[1] - }; - backend_ctx->enqueue_ndrange_kernel(pack_src, 2, pack_src_gws, pack_src_lws, dst); + if (q4_0_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a + && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { + cl_mem a_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - cl_kernel gemm = backend_ctx->kernel_gemm_xmem_f16_f32_os8; - CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &weights)); - CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &backend_ctx->prealloc_adreno_xmem_const.buffer)); - CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &src_img)); - CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &dst_img)); - CL_CHECK(clSetKernelArg(gemm, 4, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(gemm, 5, sizeof(int), &npack)); - CL_CHECK(clSetKernelArg(gemm, 6, sizeof(int), &kpack)); - const size_t z_values = CEIL_DIV(static_cast(npack), static_cast(os)); - size_t gemm_lws[3] = { 64, 1, 1 }; - size_t gemm_gws[3] = { - z_values*gemm_lws[0], - CEIL_DIV(static_cast(N), gemm_lws[0]), - 1 - }; - backend_ctx->enqueue_ndrange_kernel(gemm, 3, gemm_gws, gemm_lws, dst); + const size_t n_blocks = (size_t)N * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - cl_kernel store_dst = backend_ctx->kernel_adreno_xmem_store_dst_f32; - CL_CHECK(clSetKernelArg(store_dst, 0, sizeof(cl_mem), &dst_img)); - CL_CHECK(clSetKernelArg(store_dst, 1, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(store_dst, 2, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(store_dst, 3, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(store_dst, 4, sizeof(int), &N)); - size_t store_lws[2] = { 16, 16 }; - size_t store_gws[2] = { - CEIL_DIV(static_cast(N), store_lws[0])*store_lws[0], - CEIL_DIV(static_cast(npack), store_lws[1])*store_lws[1] - }; - backend_ctx->enqueue_ndrange_kernel(store_dst, 2, store_gws, store_lws, dst); + cl_int tb = (cl_int)n_blocks; + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - CL_CHECK(clReleaseMemObject(weights)); - CL_CHECK(clReleaseMemObject(dst_img)); - CL_CHECK(clReleaseMemObject(src_img)); -} -#endif // GGML_OPENCL_USE_ADRENO_KERNELS + cl_kernel dk = q4_0_act_vload4_on + ? backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_act_vload4 + : backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a; + int ai = 0; + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); -static void ggml_cl_conv_2d(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_TENSOR_BINARY_OP_LOCALS; - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + CL_CHECK(clReleaseMemObject(a_sub)); + return; + } - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + cl_mem b_sub_buf = nullptr; + cl_mem b_sub_buf_trans = nullptr; + cl_mem b_img = nullptr; + cl_mem b_img_trans = nullptr; + cl_mem d_sub_buf = nullptr; - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const cl_uint Cout = ne03; - const cl_uint Cin = ne02; - const cl_uint N = ne13; - const cl_uint KW = ne00; - const cl_uint KH = ne01; - const cl_uint W = ne10; - const cl_uint H = ne11; - const cl_uint OW = ne0; - const cl_uint OH = ne1; + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - const cl_uint s0 = dst->op_params[0]; - const cl_uint s1 = dst->op_params[1]; - const cl_uint p0 = dst->op_params[2]; - const cl_uint p1 = dst->op_params[3]; - const cl_uint d0 = dst->op_params[4]; - const cl_uint d1 = dst->op_params[5]; + // pad N to multiple of 8 + int extra_elements = N % 8; + int padding = 0; + if (extra_elements > 0){ + padding = 8 - extra_elements; + } - const cl_uint cl_nb00 = nb00/ggml_type_size(src0->type); - const cl_uint cl_nb01 = nb01/ggml_type_size(src0->type); - const cl_uint cl_nb02 = nb02/ggml_type_size(src0->type); - const cl_uint cl_nb03 = nb03/ggml_type_size(src0->type); - const cl_uint cl_nb10 = nb10/ggml_type_size(src1->type); - const cl_uint cl_nb11 = nb11/ggml_type_size(src1->type); - const cl_uint cl_nb12 = nb12/ggml_type_size(src1->type); - const cl_uint cl_nb13 = nb13/ggml_type_size(src1->type); - const cl_uint cl_nb1 = nb1/ggml_type_size(dst->type); - const cl_uint cl_nb2 = nb2/ggml_type_size(dst->type); - const cl_uint cl_nb3 = nb3/ggml_type_size(dst->type); + // subbuffer for transposed activations + region.origin = 0; + region.size = K * (N + padding) * sizeof(float)/2; + backend_ctx->prealloc_act_trans.allocate(context, region.size); + CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const int64_t NPQ = (int64_t)N * OW * OH; + // image for transposed activations + img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * (N + padding) / 4; + img_desc.buffer = b_sub_buf_trans; + CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - const uint32_t BS_K = 64; - const uint32_t BS_NPQ = 64; - const uint32_t BS_CRS = 16; - const uint32_t VEC_SIZE = 4; + // subbuffer for output + region.origin = extrad->offset; // Specify the starting offset (in bytes) + region.size = M * N * sizeof(float); // Specify the size of the sub-buffer + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, CL_MEM_WRITE_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const uint32_t TS_K = 4; - const uint32_t TS_NPQ = 8; + // transpose activations + int height_B = N/4; + if (height_B == 0) { + height_B = 1; + } + int width_B = K/4; + int padded_height_B = (N + padding)/4; - const uint32_t WG_K = BS_K / TS_K; - const uint32_t WG_NPQ = BS_NPQ / TS_NPQ; + kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - auto splitWork = [](uint32_t work_size, uint32_t block_size) { return (block_size + work_size - 1) / block_size; }; - const uint32_t NB_K = splitWork(Cout, BS_K); - const uint32_t NB_NPQ = splitWork(NPQ, BS_NPQ); + size_t local_work_size_t[2] = { 1, 16 }; + size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; + if (ne0 == 4096 && ne1 == 128 && ne10 == 4096) { + local_work_size_t[0]=4; + local_work_size_t[1]=8; + } else if (ne0 == 11008 && ne1 == 128 && ne10 == 4096) { + local_work_size_t[0]=2; + local_work_size_t[1]=8; + } else if(ne0 == 4096 && ne1 == 128 && ne10 == 11008) { + local_work_size_t[0]=1; + local_work_size_t[1]=8; + } else if(ne0 == 32000 && ne1 == 128 && ne10 == 4096) { + local_work_size_t[0]=2; + local_work_size_t[1]=8; + } + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - cl_kernel kernel; - size_t shmem_size; + // gemm + kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_f32; + int padded_N = N + padding; - if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { - kernel = backend_ctx->kernel_conv_2d_f16; - shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_half4)); - } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_conv_2d_f32; - shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_float) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); - } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { - kernel = backend_ctx->kernel_conv_2d_f16_f32; - shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); - } else { - GGML_ASSERT(false && "Unsupported data type combination for conv2d"); - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &d_sub_buf)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne1)); - cl_uint idx = 0; - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, idx++, shmem_size, NULL)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cout)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cin)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &N)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KW)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KH)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &W)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &H)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OW)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OH)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s0)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s1)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p0)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p1)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d0)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d1)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb00)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb01)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb02)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb03)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb10)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb11)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb12)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb13)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb1)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb2)); - CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb3)); + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; + size_t local_work_size[3] = {1, 128, 1}; + if (ne0 == 4096 && ne1 == 128 && ne10 == 4096) { + local_work_size[0] = 1; + local_work_size[1] = 128; + } else if (ne0 == 11008 && ne1 == 128 && ne10 == 4096) { + local_work_size[0] = 2; + local_work_size[1] = 64; + } else if (ne0 == 4096 && ne1 == 128 && ne10 == 11008) { + local_work_size[0] = 2; + local_work_size[1] = 64; + } else if (ne0 == 32000 && ne1 == 128 && ne10 == 4096) { + local_work_size[0] = 2; + local_work_size[1] = 64; + } - size_t global_work_size[] = { (size_t)NB_K * WG_K, (size_t)NB_NPQ * WG_NPQ, 1 }; - size_t local_work_size[] = { (size_t)WG_K, (size_t)WG_NPQ, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); + } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif } -// is_kq selects which of the two products this call is, and it is decided by the -// CALLER -- the two admission arms in ggml_cl_mul_mat, each of which knows which -// one it matched. It used to be re-derived here from nb01 > nb02, i.e. "K is -// head-major, V^T is not". That discriminator COLLAPSES at n_head_kv == 1, where -// the two strides are equal because there is only one head to order, so nothing -// here could tell a KQ from a KQV. Pass it in rather than infer it. -static void ggml_cl_mul_mat_kq_kqv_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, bool is_kq) { +static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q4_1 * extra0_q4_1 = (ggml_tensor_extra_cl_q4_1 *)src0->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - - const cl_ulong nb01 = src0->nb[1]; - const cl_ulong nb02 = src0->nb[2]; - - const int ne10 = src1->ne[0]; - const int ne11 = src1->ne[1]; - const int ne12 = src1->ne[2]; - - const cl_ulong nb10 = src1->nb[0]; - const int ne0 = dst->ne[0]; const int ne1 = dst->ne[1]; - GGML_ASSERT(ne00 == ne10); + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - cl_kernel kernel; cl_context context = backend_ctx->context; + cl_kernel kernel; - cl_int status; - cl_image_format img_fmt_1d; - cl_image_desc img_desc_1d; + cl_int err; + cl_image_format img_fmt; + cl_image_desc img_desc; cl_buffer_region region; - cl_mem A_image1d; - cl_mem A_sub_buffer; - cl_mem B_sub_buffer; - cl_mem D_image1d; - cl_mem D_sub_buffer; int M = ne01; int N = ne1; int K = ne00; - kernel = is_kq ? backend_ctx->kernel_mul_mm_f16_f32_kq - : backend_ctx->kernel_mul_mm_f16_f32_kqv; - // create sub-buffer for A - // <--------------------------------------------> // - extra0 = src0->view_src ? (ggml_tensor_extra_cl *)src0->view_src->extra : (ggml_tensor_extra_cl *)src0->extra; + // Multi-column (N=3) verify GEMV for q4_1: route the spec/MTP verify batch + // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- + // zone (gemm_noshuffle_q4_1). Reuses the ne1==1 GEMV image setup. Opt-in via + // GGML_OPENCL_Q41_MC3=1. Per-layer only (ne01 < 32768). + static const bool q41_mc3 = (getenv("GGML_OPENCL_Q41_MC3") != nullptr); + const bool use_q41_mc3 = q41_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); - region.origin = (extra0->offset + src0->view_offs); - if (is_kq) { - // KQ - region.size = nb01 * ne01; + if (ne1 == 1 || use_q41_mc3) { + cl_mem q_img = nullptr; + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; + + // image for q + img_fmt = { CL_R, CL_UNSIGNED_INT32}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q4_1->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + kernel = use_q41_mc3 ? backend_ctx->kernel_gemv_noshuffle_q4_1_f32_mc3 + : backend_ctx->kernel_gemv_noshuffle_q4_1_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); + if (use_q41_mc3) { + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); // n_cols + } + + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); } else { - // KQV - region.size = nb02 * ne02; - } + cl_mem b_sub_buf = nullptr; + cl_mem b_sub_buf_trans = nullptr; + cl_mem b_img = nullptr; + cl_mem b_img_trans = nullptr; - A_sub_buffer = clCreateSubBuffer((extra0->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); - CL_CHECK(status); + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // <--------------------------------------------> // + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // create sub-buffer for B - // <--------------------------------------------> // - region.origin = (extra1->offset + src1->view_offs); - region.size = nb10 * ne10 * ne11 * ne12; - B_sub_buffer = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); - CL_CHECK(status); - // <--------------------------------------------> // + // pad N to multiple of 8 + int extra_elements = N % 8; + int padding = 0; + if (extra_elements > 0){ + padding = 8 - extra_elements; + } - img_fmt_1d = {CL_RGBA, CL_FLOAT}; - memset(&img_desc_1d, 0, sizeof(img_desc_1d)); - img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - if (is_kq) { - img_desc_1d.image_width = (nb01 * ne01 / 4)/4; - } - else { - img_desc_1d.image_width = (nb02 * ne02 / 4)/4; - } - img_desc_1d.buffer = A_sub_buffer; - A_image1d = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &status); - CL_CHECK(status); + // subbuffer for transposed activations + region.origin = 0; + region.size = K * (N + padding) * sizeof(float)/2; + backend_ctx->prealloc_act_trans.allocate(context, region.size); + CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // create sub-buffer for output C - // <--------------------------------------------> // - region.origin = (extrad->offset + dst->view_offs); - region.size = ne0 * ne1 * dst->ne[2] * dst->nb[0]; // size of C in bytes - D_sub_buffer = clCreateSubBuffer((extrad->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); - CL_CHECK(status); - // <--------------------------------------------> // + // image for transposed activations + img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * (N + padding) / 4; + img_desc.buffer = b_sub_buf_trans; + CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - // create image for C output - // <--------------------------------------------> // - img_fmt_1d = {CL_R, CL_FLOAT}; - memset(&img_desc_1d, 0, sizeof(img_desc_1d)); - img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_1d.image_width = ne0 * ne1 * dst->ne[2] * dst->nb[0] / 4; - img_desc_1d.buffer = D_sub_buffer; - D_image1d = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt_1d, &img_desc_1d, NULL, &status); - CL_CHECK(status); - // <--------------------------------------------> // + // transpose activations + int height_B = N/4; + if (height_B == 0) { + height_B = 1; + } + int width_B = K/4; + int padded_height_B = (N + padding)/4; - int offset_src0 = 0; - int offset_src1 = 0; + kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - // set kernel args - // <--------------------------------------------> // - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &A_image1d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &offset_src0)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &B_sub_buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &offset_src1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &D_image1d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &extrad->offset)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &nb01)); + size_t local_work_size_t[2] = { 1, 16 }; + size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - size_t global_work_size[3] = {64, static_cast(((M+63)/64)), static_cast(((N+31)/32)*ne12)}; - size_t local_work_size[3] = {64, 1, 2}; + // gemm + kernel = backend_ctx->kernel_gemm_noshuffle_q4_1_f32; + int padded_N = N + padding; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne1)); - // deallocate sub buffers and images - // <--------------------------------------------> // - CL_CHECK(clReleaseMemObject(A_image1d)); - CL_CHECK(clReleaseMemObject(D_image1d)); - CL_CHECK(clReleaseMemObject(A_sub_buffer)); - CL_CHECK(clReleaseMemObject(B_sub_buffer)); - CL_CHECK(clReleaseMemObject(D_sub_buffer)); + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; + size_t local_work_size[3] = {1, 128, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_img_trans)); + } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif } -static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -19526,34 +24809,21 @@ static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_t GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == GGML_TYPE_Q1_0); - GGML_ASSERT(src1->type == GGML_TYPE_F32); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q1_0 * extra0_q1_0 = (ggml_tensor_extra_cl_q1_0 *)src0->extra; + ggml_tensor_extra_cl_q5_0 * extra0_q5_0 = (ggml_tensor_extra_cl_q5_0 *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - GGML_ASSERT(src1->view_offs == 0); - GGML_ASSERT(dst->view_offs == 0); - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - - const int ne10 = src1->ne[0]; - const int ne12 = src1->ne[2]; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; - const int ne0 = dst->ne[0]; - const int ne1 = dst->ne[1]; + const int ne1 = dst->ne[1]; - GGML_ASSERT(ne00 == ne10); - GGML_ASSERT((ne00 % 128) == 0); - GGML_ASSERT(ne0 == ne01); + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); cl_context context = backend_ctx->context; cl_kernel kernel; @@ -19568,22 +24838,22 @@ static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_t int K = ne00; if (ne1 == 1) { - cl_mem q_img = nullptr; + cl_mem qs_img = nullptr; cl_mem b_sub_buf = nullptr; cl_mem b_img = nullptr; - // image for q (uint32: each texel packs 32 sign bits) - img_fmt = { CL_R, CL_UNSIGNED_INT32}; + // image for qs + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 32; - img_desc.buffer = extra0_q1_0->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q5_0->qs; + CL_CHECK((qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // create a sub_buffer for B + // subbuffer for activations region.origin = offset1; region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); // image for activations img_fmt = {CL_RGBA, CL_FLOAT}; @@ -19593,41 +24863,112 @@ static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemv_noshuffle_q1_0_f32; - - int r2 = 1; - int r3 = 1; + kernel = backend_ctx->kernel_gemv_noshuffle_q5_0_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &extra1->offset)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &extrad->offset)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); - size_t wavesize = backend_ctx->adreno_wave_size; - size_t local_work_size[] = { wavesize, 4, 1 }; - size_t global_work_size[] = { CEIL_DIV(M, wavesize)*wavesize, 4, 1 }; + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } else { + CL_CHECK(clReleaseMemObject(qs_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); + } else { + // dp4a (int8) dense q5_0 prefill GEMM, default off + static const char * q5_dense_dp4a_env = getenv("GGML_OPENCL_Q5_DENSE_DP4A"); + static const char * q5_dense_wimg_env = getenv("GGML_OPENCL_Q5_DENSE_DP4A_WIMG"); + const bool q5_dense_wimg_on = q5_dense_wimg_env && (atoi(q5_dense_wimg_env) != 0); + bool q5_dense_dp4a_on = q5_dense_wimg_on + ? true + : (q5_dense_dp4a_env && (atoi(q5_dense_dp4a_env) != 0)); + // dot prod has to be available + q5_dense_dp4a_on = backend_ctx->has_integer_dot && q5_dense_dp4a_on; + + if (q5_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a + && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { + cl_mem a_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + const size_t n_blocks = (size_t)N * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + + cl_int tb = (cl_int)n_blocks; + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + + // optional qs texture (image1d_buffer over the nibble plane; the same + // CL_R/UINT32 view, width M*K/8, the GEMV path builds). + cl_mem q5_qs_img = nullptr; + bool use_wimg = q5_dense_wimg_on; + if (use_wimg) { + const size_t tex = (size_t)M * (size_t)K / 8; // uint32 texels (2 ushorts/texel) + if (tex == 0 || tex > backend_ctx->image_max_buffer_size) { + use_wimg = false; + } else { + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = tex; + img_desc.buffer = extra0_q5_0->qs; + q5_qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); + if (err != CL_SUCCESS || q5_qs_img == nullptr) { use_wimg = false; q5_qs_img = nullptr; } + } + } + + cl_kernel dk = use_wimg ? backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg + : backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a; + int ai = 0; + if (use_wimg) { + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q5_qs_img)); + } else { + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->qs)); + } + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->qh)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + + if (q5_qs_img != nullptr) { + CL_CHECK(clReleaseMemObject(q5_qs_img)); + } + CL_CHECK(clReleaseMemObject(a_sub)); + return; + } + cl_mem b_sub_buf = nullptr; cl_mem b_sub_buf_trans = nullptr; cl_mem b_img = nullptr; cl_mem b_img_trans = nullptr; + cl_mem d_sub_buf = nullptr; // subbuffer for activations region.origin = offset1; @@ -19663,6 +25004,11 @@ static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf_trans; CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + // subbuffer for output + region.origin = extrad->offset; + region.size = M * N * sizeof(float); + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, CL_MEM_WRITE_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + // transpose activations int height_B = N/4; if (height_B == 0) { @@ -19683,264 +25029,39 @@ static void ggml_cl_mul_mat_q1_0_f32_adreno(ggml_backend_t backend, const ggml_t backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q1_0_f32; + kernel = backend_ctx->kernel_gemm_noshuffle_q5_0_f32; int padded_N = N + padding; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); - - size_t global_work_size[] = { (size_t)CEIL_DIV(N, 8), (size_t)CEIL_DIV(M, 4), 1 }; - size_t local_work_size[] = { 2, 128, 1 }; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(b_img_trans)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); -#endif -} - -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q4_0_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, - const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; - - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; - - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - - const int ne1 = dst->ne[1]; - - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - - cl_context context = backend_ctx->context; - cl_kernel kernel; - - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; - - int M = ne01; - int N = ne1; - int K = ne00; - - if (ne1 == 1) { - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; - - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - img_fmt = { CL_RGBA, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &K)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &M)); - - size_t wavesize = backend_ctx->adreno_wave_size; - size_t local_work_size[3] = { wavesize, 4, 1 }; - size_t global_work_size[3] = { (size_t)CEIL_DIV(M, 64) * 64, 4, 1 }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { - const int gemm_tile_n = 64; - int N_pad = (N + gemm_tile_n - 1) & ~(gemm_tile_n - 1); - - cl_mem a_img = extra0_q4_0->q_img; - cl_mem s_img = extra0_q4_0->d_img; - GGML_ASSERT(a_img && s_img && "ILA Q4_0 weight images missing; set_tensor should have built them"); - - static const char * q4_0_bin_dp4a_env = getenv("GGML_OPENCL_Q4_0_BIN_DP4A"); - bool q4_0_bin_dp4a_on = q4_0_bin_dp4a_env - ? (atoi(q4_0_bin_dp4a_env) != 0) - : true; - // dot prod has to be available - q4_0_bin_dp4a_on = backend_ctx->has_integer_dot && q4_0_bin_dp4a_on; - - if (q4_0_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin) { - const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; - const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); - - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - - cl_mem b_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - cl_int tb = (cl_int)((size_t)N * (K / 32)); - cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); - CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - - cl_mem d_sub = nullptr; - cl_mem d_img = nullptr; - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a_ila_a8_bin; - - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &a_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); - - size_t local_work_size[3] = { 64, 1, 1 }; - size_t global_work_size[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(b_sub)); - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub)); - return; - } - - // Pad B through a zero-filled scratch buffer when N needs - // padding, since the GEMM kernel always reads a full N-tile. - const bool need_pad = N_pad > N; - cl_mem b_sub_buf = nullptr; - cl_mem b_padded = nullptr; - if (need_pad) { - CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, - (size_t)K * N_pad * sizeof(float), NULL, &err), err)); - const float zero = 0.0f; - CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), - 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, - offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); - } else { - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - } - - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = need_pad ? (size_t)K * N_pad : (size_t)K * N; - img_desc.buffer = need_pad ? b_padded : b_sub_buf; - cl_mem b_img; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - cl_mem d_sub_buf; - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub_buf; - cl_mem d_img; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - int line_stride_matrix_A_in_bytes = M * 4; - int line_stride_matrix_S_in_bytes = M * 2; - int line_stride_matrix_B_in_bytes = K * 4; - int line_stride_matrix_C_in_bytes = M * 4; - - int c_offset_for_kernel = 0; - int b_offset_for_kernel = 0; - - kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_sub_buf)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &a_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &s_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &b_offset_for_kernel)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &c_offset_for_kernel)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_A_in_bytes)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_S_in_bytes)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_B_in_bytes)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &line_stride_matrix_C_in_bytes)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; + size_t local_work_size[3] = {1, 128, 1}; - size_t local_work_size[3] = { 64, 2, 2 }; - size_t m_tiles = (size_t)CEIL_DIV(M, 64); - size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - if (b_sub_buf) { - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } - if (b_padded) { - CL_CHECK(clReleaseMemObject(b_padded)); - } - CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(b_img_trans)); CL_CHECK(clReleaseMemObject(d_sub_buf)); } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_q5_1_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -19953,19 +25074,14 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; + ggml_tensor_extra_cl_q5_1 * extra0_q5_1 = (ggml_tensor_extra_cl_q5_1 *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - - const int ne10 = src1->ne[0]; - const int ne12 = src1->ne[2]; - const int ne0 = dst->ne[0]; const int ne1 = dst->ne[1]; GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); @@ -19982,42 +25098,18 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t int N = ne1; int K = ne00; - // Multi-column (N=3) verify GEMV for q4_0: route the spec/MTP verify batch - // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- - // zone (gemm_noshuffle_q4_0 is ~50% of MTP decode on a Q4_0 model since q4_0 - // weights have no cok/mc3, unlike q4_K). Reuses the ne1==1 GEMV image setup - // (activation image already sized by N=ne1). Byte-identical. Opt-in via - // GGML_OPENCL_Q40_MC3=1. Per-layer only (ne01 < 32768); q4_0 lm_head doesn't - // occur (token_embd/output stay Q6_K), guard kept for parity with q4_K mc3. - static const bool q40_mc3 = (getenv("GGML_OPENCL_Q40_MC3") != nullptr); - const bool use_q40_mc3 = q40_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); - - const bool use_bin = use_q4_0_bin_kernels(backend_ctx, src0); - - if (use_bin) { - if (use_q40_mc3) { - static bool warned = false; - if (!warned) { - GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q40_MC3 is bypassed by Q4_0 binary kernels\n"); - warned = true; - } - } - ggml_cl_mul_mat_q4_0_f32_adreno_ila(backend, src0, src1, dst); - return; - } - - if (ne1 == 1 || use_q40_mc3) { - cl_mem q_img = nullptr; + if (ne1 == 1) { + cl_mem qs_img = nullptr; cl_mem b_sub_buf = nullptr; cl_mem b_img = nullptr; - // image for q - img_fmt = { CL_R, CL_UNSIGNED_INT32}; + // image for qs + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q4_0->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_desc.buffer = extra0_q5_1->qs; + CL_CHECK((qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); // subbuffer for activations region.origin = offset1; @@ -20032,114 +25124,27 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - if (use_q40_mc3) { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_mc3; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne1)); - } else { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32; - if (M == 4096 && K == 4096) { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_4096; - } else if (M == 4096 && K == 11008) { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_4096_1_11008; - } else if (M == 11008 && K == 4096) { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_11008_1_4096; - } else if (M == 32000 && K == 4096) { - kernel = backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32000_1_4096; - } - - int r2 = 1; - int r3 = 1; + kernel = backend_ctx->kernel_gemv_noshuffle_q5_1_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); - // Small-M mc3 verify is occupancy/latency-bound (too few WGs at small M, so - // its bandwidth falls well short of the FFN matmuls'). Use 8 subgroups (512-WI WGs, half the - // per-lane K-walk) for small M. Layout stride is fixed (4 uints/block), so only - // the K-split count changes; the mc3 kernel reads it via get_local_size(1). The - // ne1==1 base kernel hardcodes N_SIMDGROUP=4, so it always stays at 4. - const int mc3_nsg = (use_q40_mc3 && ne01 < 4096) ? 8 : 4; - size_t local_work_size[3] = {64, (size_t)mc3_nsg, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, (size_t)mc3_nsg, 1}; + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(qs_img)); CL_CHECK(clReleaseMemObject(b_sub_buf)); CL_CHECK(clReleaseMemObject(b_img)); } else { - // dp4a (int8) dense prefill GEMM, default off - static const char * q4_0_dense_dp4a_env = getenv("GGML_OPENCL_Q4_0_DENSE_DP4A"); - bool q4_0_dense_dp4a_on = q4_0_dense_dp4a_env - ? (atoi(q4_0_dense_dp4a_env) != 0) - : false; - // dot prod has to be available - q4_0_dense_dp4a_on = backend_ctx->has_integer_dot && q4_0_dense_dp4a_on; - - if (q4_0_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a - && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { - cl_mem a_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - const size_t n_blocks = (size_t)N * (K / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - - cl_int tb = (cl_int)n_blocks; - cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); - CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - - cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q4_0_q8_1_dp4a; - int ai = 0; - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_0->q)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); - - CL_CHECK(clReleaseMemObject(a_sub)); - return; - } - cl_mem b_sub_buf = nullptr; cl_mem b_sub_buf_trans = nullptr; cl_mem b_img = nullptr; @@ -20181,8 +25186,8 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); // subbuffer for output - region.origin = extrad->offset; // Specify the starting offset (in bytes) - region.size = M * N * sizeof(float); // Specify the size of the sub-buffer + region.origin = extrad->offset; + region.size = M * N * sizeof(float); CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, CL_MEM_WRITE_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); // transpose activations @@ -20202,49 +25207,25 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t size_t local_work_size_t[2] = { 1, 16 }; size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - if (ne0 == 4096 && ne1 == 128 && ne10 == 4096) { - local_work_size_t[0]=4; - local_work_size_t[1]=8; - } else if (ne0 == 11008 && ne1 == 128 && ne10 == 4096) { - local_work_size_t[0]=2; - local_work_size_t[1]=8; - } else if(ne0 == 4096 && ne1 == 128 && ne10 == 11008) { - local_work_size_t[0]=1; - local_work_size_t[1]=8; - } else if(ne0 == 32000 && ne1 == 128 && ne10 == 4096) { - local_work_size_t[0]=2; - local_work_size_t[1]=8; - } backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q4_0_f32; + kernel = backend_ctx->kernel_gemm_noshuffle_q5_1_f32; int padded_N = N + padding; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &d_sub_buf)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_sub_buf)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne1)); size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; size_t local_work_size[3] = {1, 128, 1}; - if (ne0 == 4096 && ne1 == 128 && ne10 == 4096) { - local_work_size[0] = 1; - local_work_size[1] = 128; - } else if (ne0 == 11008 && ne1 == 128 && ne10 == 4096) { - local_work_size[0] = 2; - local_work_size[1] = 64; - } else if (ne0 == 4096 && ne1 == 128 && ne10 == 11008) { - local_work_size[0] = 2; - local_work_size[1] = 64; - } else if (ne0 == 32000 && ne1 == 128 && ne10 == 4096) { - local_work_size[0] = 2; - local_work_size[1] = 64; - } backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); @@ -20262,7 +25243,7 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t #endif } -static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_iq4_nl_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -20275,7 +25256,7 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_1 * extra0_q4_1 = (ggml_tensor_extra_cl_q4_1 *)src0->extra; + ggml_tensor_extra_cl_iq4_nl * extra0_iq4_nl = (ggml_tensor_extra_cl_iq4_nl *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; @@ -20285,7 +25266,7 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t const int ne1 = dst->ne[1]; - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + GGML_ASSERT(ne00 % 32 == 0); cl_context context = backend_ctx->context; cl_kernel kernel; @@ -20299,14 +25280,7 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t int N = ne1; int K = ne00; - // Multi-column (N=3) verify GEMV for q4_1: route the spec/MTP verify batch - // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- - // zone (gemm_noshuffle_q4_1). Reuses the ne1==1 GEMV image setup. Opt-in via - // GGML_OPENCL_Q41_MC3=1. Per-layer only (ne01 < 32768). - static const bool q41_mc3 = (getenv("GGML_OPENCL_Q41_MC3") != nullptr); - const bool use_q41_mc3 = q41_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); - - if (ne1 == 1 || use_q41_mc3) { + if (ne1 == 1) { cl_mem q_img = nullptr; cl_mem b_sub_buf = nullptr; cl_mem b_img = nullptr; @@ -20316,7 +25290,7 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q4_1->q; + img_desc.buffer = extra0_iq4_nl->q; CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); // subbuffer for activations @@ -20332,20 +25306,15 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = use_q41_mc3 ? backend_ctx->kernel_gemv_noshuffle_q4_1_f32_mc3 - : backend_ctx->kernel_gemv_noshuffle_q4_1_f32; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); - if (use_q41_mc3) { - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); // n_cols - } + kernel = backend_ctx->kernel_gemv_noshuffle_iq4_nl_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); size_t local_work_size[3] = {64, 4, 1}; size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; @@ -20356,6 +25325,58 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t CL_CHECK(clReleaseMemObject(b_sub_buf)); CL_CHECK(clReleaseMemObject(b_img)); } else { + // dp4a (int8) dense IQ4_NL prefill GEMM. Quantizes the [N,K] activations to + // q8_1 and runs the int8 dot instead of the f16 half-dot. Large-batch + // (ne1>8) only + static const char * iq4nl_dense_dp4a_env = getenv("GGML_OPENCL_IQ4NL_DENSE_DP4A"); + bool iq4nl_dense_dp4a_on = iq4nl_dense_dp4a_env + ? (atoi(iq4nl_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + // dot prod has to be available + iq4nl_dense_dp4a_on = backend_ctx->has_integer_dot && iq4nl_dense_dp4a_on; + + if (iq4nl_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a + && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { + cl_mem a_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + const size_t n_blocks = (size_t)N * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + + cl_int tb = (cl_int)n_blocks; + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + + cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a; + int ai = 0; + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_iq4_nl->q)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_iq4_nl->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + + CL_CHECK(clReleaseMemObject(a_sub)); + return; + } + cl_mem b_sub_buf = nullptr; cl_mem b_sub_buf_trans = nullptr; cl_mem b_img = nullptr; @@ -20415,19 +25436,18 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q4_1_f32; + kernel = backend_ctx->kernel_gemm_noshuffle_iq4_nl_f32; int padded_N = N + padding; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; size_t local_work_size[3] = {1, 128, 1}; @@ -20447,7 +25467,7 @@ static void ggml_cl_mul_mat_q4_1_f32_adreno(ggml_backend_t backend, const ggml_t #endif } -static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -20456,21 +25476,33 @@ static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_t GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == GGML_TYPE_Q8_0); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q5_0 * extra0_q5_0 = (ggml_tensor_extra_cl_q5_0 *)src0->extra; + // SoA extra lives on view_src (view->extra is pre-SoA). + const ggml_tensor * soa0_src = src0->view_src != nullptr ? src0->view_src : src0; + ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)soa0_src->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; - const int ne1 = dst->ne[1]; + const int ne10 = src1->ne[0]; + const int ne12 = src1->ne[2]; - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + + GGML_ASSERT(ne00 == ne10); + GGML_ASSERT((ne00 % 32) == 0); + GGML_ASSERT(ne0 == ne01); cl_context context = backend_ctx->context; cl_kernel kernel; @@ -20485,62 +25517,215 @@ static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_t int K = ne00; if (ne1 == 1) { - cl_mem qs_img = nullptr; + cl_mem q_img = nullptr; cl_mem b_sub_buf = nullptr; cl_mem b_img = nullptr; - // image for qs - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; + // image for q + img_fmt = { CL_R, CL_UNSIGNED_INT32}; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q5_0->qs; - CL_CHECK((qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_desc.image_width = M * K / 4; + img_desc.buffer = extra0_q8_0->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + // create a sub_buffer for B + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + // Split-K for small-M decode GEMVs. The base kernel puts one output row + // per lane and splits K only inside one workgroup, so M is the sole source + // of workgroup parallelism: gpt-oss's K and V projections are M=512 = 8 + // workgroups on a 16-CU X2, and the kernel measures 48 GB/s where the + // M=2880/4096 projections in the same decode graph reach 122-123. Mirrors + // the q4_0/q4_K split-K above and reuses their reduce kernel. + // + // Enabled where it is measured to win, like the q4_K gate: X2-90 +2.8% + // tg32 @d4096 on gpt-oss; Adreno 840 (12 CU) NEUTRAL on Llama-3.2-3B-Q8_0 + // (0.0% @d4096 -- its K/V proj is M=1024 = 16 workgroups, which already + // fills 12 CUs). Unmeasured on X1E/A7X/A6X and the q4_K split-K measured + // -0.7% on X1E, so the default is not widened on absence of evidence. + static const bool q8_splitk_env_set = []{ + const char * e = std::getenv("GGML_OPENCL_Q8_GEMV_SPLITK"); + return e && e[0] != '\0'; + }(); + static const bool q8_splitk_env_on = []{ + const char * e = std::getenv("GGML_OPENCL_Q8_GEMV_SPLITK"); + return !(e && e[0] == '0'); + }(); + const bool q8_splitk_on = q8_splitk_env_set + ? q8_splitk_env_on + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + if (q8_splitk_on && backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk && + ne01 <= 1024 && ne01 % 64 == 0) { + const int nsg = 8; + const int ksplit = 8; // -> 8 * M/64 workgroups + const size_t gx = (size_t) CEIL_DIV(ne01, 64) * 64; + + backend_ctx->prealloc_splitk_partial.allocate( + backend_ctx->context, (size_t) ksplit * ne01 * sizeof(float)); + cl_mem partial = backend_ctx->prealloc_splitk_partial.buffer; + + cl_kernel ks = backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk; + CL_CHECK(clSetKernelArg(ks, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(ks, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(ks, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(ks, 3, sizeof(cl_mem), &partial)); + CL_CHECK(clSetKernelArg(ks, 4, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(ks, 5, sizeof(cl_int), &ne01)); + size_t lsk[3] = { 64, (size_t) nsg, 1 }; + size_t gsk[3] = { gx, (size_t) (nsg * ksplit), 1 }; + backend_ctx->enqueue_ndrange_kernel(ks, 3, gsk, lsk, dst); + + cl_kernel kr = backend_ctx->kernel_gemv_splitk_reduce_f32; + CL_CHECK(clSetKernelArg(kr, 0, sizeof(cl_mem), &partial)); + CL_CHECK(clSetKernelArg(kr, 1, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kr, 2, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kr, 3, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kr, 4, sizeof(cl_int), &ksplit)); + size_t lr[3] = { 64, 1, 1 }; + size_t gr[3] = { (size_t) CEIL_DIV(ne01, 64) * 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(kr, 3, gr, lr, dst); + + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } + + kernel = backend_ctx->kernel_gemv_noshuffle_q8_0_f32; + + int r2 = 1; + int r3 = 1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + + size_t wavesize = backend_ctx->adreno_wave_size; + size_t local_work_size[] = { wavesize, 4, 1 }; + size_t global_work_size[] = { CEIL_DIV(M, wavesize)*wavesize, 4, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + } else { + static const char * q8_bin_dp4a_env = getenv("GGML_OPENCL_Q8_0_BIN_DP4A"); + const bool q8_bin_dp4a_on = backend_ctx->has_integer_dot && + (q8_bin_dp4a_env ? (atoi(q8_bin_dp4a_env) != 0) : true); + + if (q8_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin + && M % 64 == 0) { + cl_mem a_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + const size_t n_blocks = (size_t)N * (K / 32); + + const size_t N_pad = ((size_t)N + 31) / 32 * 32; + const size_t n_blocks_pad = N_pad * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N_pad * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks_pad * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_pad * sizeof(cl_half)); + + cl_int tb = (cl_int)n_blocks; + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + + cl_mem q_img = nullptr; + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * (size_t)K / 4; + img_desc.buffer = extra0_q8_0->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_mem d_sub_buf = nullptr; + cl_mem d_img = nullptr; + region.origin = extrad->offset; + region.size = (size_t)M * N * sizeof(float); + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub_buf; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemv_noshuffle_q5_0_f32; + cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin; + cl_uint ne00_u = (cl_uint)K; + cl_uint ne01_u = (cl_uint)M; + CL_CHECK(clSetKernelArg(dk, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(dk, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(dk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, 4, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(dk, 5, sizeof(cl_uint), &ne00_u)); + CL_CHECK(clSetKernelArg(dk, 6, sizeof(cl_uint), &ne01_u)); + CL_CHECK(clSetKernelArg(dk, 7, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); + CL_CHECK(clReleaseMemObject(a_sub)); + return; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + // dp4a dense q8_0 prefill GEMM. Quantizes the [N,K] activations to + // q8_1 and runs the int8 dot instead of the f16 half-dot. Large-batch + // (ne1>8) only; q8_0 weights are already int8 (no requant) and symmetric + // (no min term) + static const char * q8_dense_dp4a_env = getenv("GGML_OPENCL_Q8_DENSE_DP4A"); + static const char * q8_dense_wimg_env = getenv("GGML_OPENCL_Q8_DENSE_DP4A_WIMG"); + const bool q8_dense_wimg_on = q8_dense_wimg_env && (atoi(q8_dense_wimg_env) != 0); - CL_CHECK(clReleaseMemObject(qs_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { - // dp4a (int8) dense q5_0 prefill GEMM, default off - static const char * q5_dense_dp4a_env = getenv("GGML_OPENCL_Q5_DENSE_DP4A"); - static const char * q5_dense_wimg_env = getenv("GGML_OPENCL_Q5_DENSE_DP4A_WIMG"); - const bool q5_dense_wimg_on = q5_dense_wimg_env && (atoi(q5_dense_wimg_env) != 0); - bool q5_dense_dp4a_on = q5_dense_wimg_on + const bool q8_bin_loaded = (backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin != nullptr); + // bin kernel takes precedence + bool q8_dense_dp4a_on = q8_dense_wimg_on ? true - : (q5_dense_dp4a_env && (atoi(q5_dense_dp4a_env) != 0)); + : q8_dense_dp4a_env + ? (atoi(q8_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E && !q8_bin_loaded); // dot prod has to be available - q5_dense_dp4a_on = backend_ctx->has_integer_dot && q5_dense_dp4a_on; + q8_dense_dp4a_on = backend_ctx->has_integer_dot && q8_dense_dp4a_on; - if (q5_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a + if (q8_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { cl_mem a_sub = nullptr; region.origin = offset1; @@ -20563,12 +25748,11 @@ static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_t size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - // optional qs texture (image1d_buffer over the nibble plane; the same - // CL_R/UINT32 view, width M*K/8, the GEMV path builds). - cl_mem q5_qs_img = nullptr; - bool use_wimg = q5_dense_wimg_on; + // optional weight texture, the same CL_R/UINT32 view, width M*K/4 + cl_mem q8_q_img = nullptr; + bool use_wimg = q8_dense_wimg_on; if (use_wimg) { - const size_t tex = (size_t)M * (size_t)K / 8; // uint32 texels (2 ushorts/texel) + const size_t tex = (size_t)M * (size_t)K / 4; // uint32 texels if (tex == 0 || tex > backend_ctx->image_max_buffer_size) { use_wimg = false; } else { @@ -20576,25 +25760,28 @@ static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_t memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; img_desc.image_width = tex; - img_desc.buffer = extra0_q5_0->qs; - q5_qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); - if (err != CL_SUCCESS || q5_qs_img == nullptr) { use_wimg = false; q5_qs_img = nullptr; } + img_desc.buffer = extra0_q8_0->q; + q8_q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); + if (err != CL_SUCCESS || q8_q_img == nullptr) { use_wimg = false; q8_q_img = nullptr; } } } - cl_kernel dk = use_wimg ? backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a_wimg - : backend_ctx->kernel_gemm_noshuffle_q5_0_q8_1_dp4a; + static const char * q8_0_act_vload4_env = getenv("GGML_OPENCL_Q8_0_DP4A_ACT_VLOAD4"); + const bool q8_0_act_vload4_on = q8_0_act_vload4_env == nullptr || atoi(q8_0_act_vload4_env) != 0; + cl_kernel dk = use_wimg + ? backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg + : q8_0_act_vload4_on + ? backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_act_vload4 + : backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a; int ai = 0; if (use_wimg) { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q5_qs_img)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q8_q_img)); } else { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->qs)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q8_0->q)); } - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->qh)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q8_0->d)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); @@ -20604,199 +25791,110 @@ static void ggml_cl_mul_mat_q5_0_f32_adreno(ggml_backend_t backend, const ggml_t size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); - if (q5_qs_img != nullptr) { - CL_CHECK(clReleaseMemObject(q5_qs_img)); + if (q8_q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q8_q_img)); } CL_CHECK(clReleaseMemObject(a_sub)); return; } - cl_mem b_sub_buf = nullptr; - cl_mem b_sub_buf_trans = nullptr; - cl_mem b_img = nullptr; - cl_mem b_img_trans = nullptr; - cl_mem d_sub_buf = nullptr; - - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // pad N to multiple of 8 - int extra_elements = N % 8; - int padding = 0; - if (extra_elements > 0){ - padding = 8 - extra_elements; - } - - // subbuffer for transposed activations - region.origin = 0; - region.size = K * (N + padding) * sizeof(float)/2; - backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // image for transposed activations - img_fmt = {CL_RGBA, CL_HALF_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * (N + padding) / 4; - img_desc.buffer = b_sub_buf_trans; - CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - - // subbuffer for output - region.origin = extrad->offset; - region.size = M * N * sizeof(float); - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, CL_MEM_WRITE_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // transpose activations - int height_B = N/4; - if (height_B == 0) { - height_B = 1; - } - int width_B = K/4; - int padded_height_B = (N + padding)/4; - - kernel = backend_ctx->kernel_transpose_32_16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - - size_t local_work_size_t[2] = { 1, 16 }; - size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - - // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q5_0_f32; - int padded_N = N + padding; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_sub_buf)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); - - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; - size_t local_work_size[3] = {1, 128, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); - } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); -#endif -} - -static void ggml_cl_mul_mat_q5_1_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q5_1 * extra0_q5_1 = (ggml_tensor_extra_cl_q5_1 *)src0->extra; + // use bin kernel if available + if (backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin) { + int K_pad = K; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + cl_mem b_sub_buf = nullptr; + cl_mem d_sub_buf = nullptr; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; + cl_mem a_img = nullptr; + cl_mem s_img = nullptr; + cl_mem b_img = nullptr; + cl_mem d_img = nullptr; - const int ne1 = dst->ne[1]; + // subbuffer for activations + region.origin = offset1; + region.size = K_pad * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + // Create subbuffer and image1d_buffer for dst + region.origin = (extrad->offset); // + dst->view_offs; + region.size = M * N * sizeof(float); + CL_CHECK((d_sub_buf = clCreateSubBuffer((extrad->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - cl_context context = backend_ctx->context; - cl_kernel kernel; + // create an image for A + img_fmt = { CL_R, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 4; // Divide by 4 for char -> float + img_desc.buffer = extra0_q8_0->q; + CL_CHECK((a_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; + // create an image for Scale + img_fmt = { CL_R, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 32; // Block size is 32 + img_desc.buffer = extra0_q8_0->d; + CL_CHECK((s_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - int M = ne01; - int N = ne1; - int K = ne00; + // create an image for B from sub_buffer + img_fmt = {CL_R, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K_pad * N; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - if (ne1 == 1) { - cl_mem qs_img = nullptr; - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + // img for d + img_fmt = {CL_R, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * N; + img_desc.buffer = d_sub_buf; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // image for qs - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q5_1->qs; - CL_CHECK((qs_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + // gemm + kernel = backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin; - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + bool layoutA_Mfirst = true; + bool layoutS_Mfirst = true; + bool layoutB_Nfirst = false; + bool layoutC_Mfirst = true; - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + cl_uint lineStrideMatrixAinBytes = layoutA_Mfirst ? M * 4 : K; // int8 + cl_uint lineStrideMatrixSinBytes = layoutS_Mfirst ? M * 2 : (K / 32) * 2; // fp16 + cl_uint lineStrideMatrixBinBytes = layoutB_Nfirst ? N * 4 : K_pad * 4; // fp32 + cl_uint lineStrideMatrixCinBytes = layoutC_Mfirst ? M * 4 : N * 4; // fp32 - kernel = backend_ctx->kernel_gemv_noshuffle_q5_1_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &a_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s_img)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &extra1->offset)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &extrad->offset)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &lineStrideMatrixAinBytes)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &lineStrideMatrixSinBytes)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &lineStrideMatrixBinBytes)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &lineStrideMatrixCinBytes)); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &qs_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + size_t global_work_size[] = { 64, (size_t)CEIL_DIV(M, 64), (size_t)CEIL_DIV(N, 64)}; + size_t local_work_size[] = { 64, 2, 2 }; - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); + CL_CHECK(clReleaseMemObject(a_img)); + CL_CHECK(clReleaseMemObject(s_img)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(d_img)); + return; + } - CL_CHECK(clReleaseMemObject(qs_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { cl_mem b_sub_buf = nullptr; cl_mem b_sub_buf_trans = nullptr; cl_mem b_img = nullptr; cl_mem b_img_trans = nullptr; - cl_mem d_sub_buf = nullptr; // subbuffer for activations region.origin = offset1; @@ -20832,11 +25930,6 @@ static void ggml_cl_mul_mat_q5_1_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf_trans; CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - // subbuffer for output - region.origin = extrad->offset; - region.size = M * N * sizeof(float); - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, CL_MEM_WRITE_ONLY, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // transpose activations int height_B = N/4; if (height_B == 0) { @@ -20857,30 +25950,28 @@ static void ggml_cl_mul_mat_q5_1_f32_adreno(ggml_backend_t backend, const ggml_t backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q5_1_f32; + kernel = backend_ctx->kernel_gemm_noshuffle_q8_0_f32; int padded_N = N + padding; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_sub_buf)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; - size_t local_work_size[3] = {1, 128, 1}; + size_t global_work_size[] = { (size_t)CEIL_DIV(N, 8), (size_t)CEIL_DIV(M, 4), 1 }; + size_t local_work_size[] = { 2, 128, 1 }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img_trans)); CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); } #else GGML_UNUSED(backend); @@ -20890,8 +25981,9 @@ static void ggml_cl_mul_mat_q5_1_f32_adreno(ggml_backend_t backend, const ggml_t #endif } -static void ggml_cl_mul_mat_iq4_nl_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, + const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -20903,17 +25995,17 @@ static void ggml_cl_mul_mat_iq4_nl_f32_adreno(ggml_backend_t backend, const ggml ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_iq4_nl * extra0_iq4_nl = (ggml_tensor_extra_cl_iq4_nl *)src0->extra; + ggml_tensor_extra_cl_q4_K * extra0_q4_k = (ggml_tensor_extra_cl_q4_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; - const int ne1 = dst->ne[1]; + const int ne1 = dst->ne[1]; - GGML_ASSERT(ne00 % 32 == 0); + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); cl_context context = backend_ctx->context; cl_kernel kernel; @@ -20927,194 +26019,257 @@ static void ggml_cl_mul_mat_iq4_nl_f32_adreno(ggml_backend_t backend, const ggml int N = ne1; int K = ne00; - if (ne1 == 1) { - cl_mem q_img = nullptr; + // CoopK handles with _bin use the bin weight layout (uint-transposed q), with K-major Q8_1 activations (K contiguous). + // This switch disables only this bin-layout path; weight conversion is unchanged. + static const char * env_coopk_bin = getenv("GGML_OPENCL_COOPK_Q4_K_BIN"); + const bool use_coopk_bin = !env_coopk_bin || !*env_coopk_bin || atoi(env_coopk_bin) != 0; + if (use_coopk_bin && ne1 >= 2 && ne1 <= 4 && + ggml_cl_coopk_dp4a_narrow_on(backend_ctx, dst, backend_ctx->rows_coopk_dp4a_q4_k) && + backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c4 != nullptr && + ((ne1 <= 2) ? backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c2 + : backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c4) != nullptr) { cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for q - img_fmt = { CL_R, CL_UNSIGNED_INT32}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_iq4_nl->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + // Allocate all kernel columns; padded columns have independent accumulators and are not stored. + const int cols = (ne1 <= 2) ? 2 : 4; + const size_t size_qa = (size_t)cols * K * sizeof(cl_char); + const size_t n_blocks_padded = (size_t)cols * (K / 32); + const size_t size_qa_prev = backend_ctx->prealloc_moe_qa.size; + const size_t size_da_prev = backend_ctx->prealloc_moe_da.size; + backend_ctx->prealloc_moe_qa.allocate(context, size_qa); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks_padded * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_padded * sizeof(cl_half)); + if (backend_ctx->prealloc_moe_qa.size != size_qa_prev) { + const cl_char z8 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_qa.buffer, + &z8, sizeof(z8), 0, backend_ctx->prealloc_moe_qa.size, 0, NULL, NULL)); + } + if (backend_ctx->prealloc_moe_da.size != size_da_prev) { + const cl_half z16 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_da.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_da.size, 0, NULL, NULL)); + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_sa.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_sa.size, 0, NULL, NULL)); + } + + cl_int n_blocks = (cl_int)((size_t)N * (K / 32)); + cl_kernel kernel_quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(kernel_quant, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(kernel_quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 4, sizeof(cl_int), &n_blocks)); + size_t local_work_size_quant[1] = { 64 }; + size_t global_work_size_quant[1] = { (size_t)((((size_t)n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(kernel_quant, 1, global_work_size_quant, local_work_size_quant, dst); + + cl_kernel kernel_coopk = (ne1 <= 2) ? backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c2 + : backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_bin_c4; + const int nsg_selected = (ne1 <= 2) ? backend_ctx->nsg_coopk_dp4a_q4_k_bin_c2 + : backend_ctx->nsg_coopk_dp4a_q4_k_bin_c4; + const cl_uchar mask_d6 = 0x3F, mask_d4 = 0x0F, mask_hi2 = 0xC0; + const cl_int n_padded = cols; + CL_CHECK(clSetKernelArg(kernel_coopk, 0, sizeof(cl_mem), &extra0_q4_k->q)); + CL_CHECK(clSetKernelArg(kernel_coopk, 1, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel_coopk, 2, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel_coopk, 3, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel_coopk, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 6, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_coopk, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_coopk, 9, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel_coopk, 10, sizeof(cl_int), &n_padded)); + CL_CHECK(clSetKernelArg(kernel_coopk, 11, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel_coopk, 12, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel_coopk, 13, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel_coopk, 14, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel_coopk, 15, sizeof(cl_uchar), &mask_hi2)); + + // Each width can compile with a different subgroup count. + const size_t nsg = (size_t)nsg_selected; + size_t local_work_size[3] = { 64, nsg, 1 }; + size_t global_work_size[3] = { (size_t)(ne01 / backend_ctx->rows_coopk_dp4a_q4_k), nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel_coopk, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } + + if (ne1 == 1) { + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; - // subbuffer for activations region.origin = offset1; - region.size = K * N * sizeof(float); + region.size = (size_t)K * N * sizeof(float); CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; + img_fmt = { CL_RGBA, CL_FLOAT }; memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N / 4; + img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemv_noshuffle_iq4_nl_f32; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &ne01)); - - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; + kernel = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + size_t local_work_size[3] = { 64, 8, 1 }; + size_t global_work_size[3] = { (size_t)ne01, 8, 1 }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(q_img)); CL_CHECK(clReleaseMemObject(b_sub_buf)); CL_CHECK(clReleaseMemObject(b_img)); } else { - // dp4a (int8) dense IQ4_NL prefill GEMM. Quantizes the [N,K] activations to - // q8_1 and runs the int8 dot instead of the f16 half-dot. Large-batch - // (ne1>8) only - static const char * iq4nl_dense_dp4a_env = getenv("GGML_OPENCL_IQ4NL_DENSE_DP4A"); - bool iq4nl_dense_dp4a_on = iq4nl_dense_dp4a_env - ? (atoi(iq4nl_dense_dp4a_env) != 0) - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + const int gemm_tile_n = 64; + int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n; + + static const char * q4_k_bin_dp4a_env = getenv("GGML_OPENCL_Q4_K_BIN_DP4A"); + bool q4_k_bin_dp4a_on = q4_k_bin_dp4a_env + ? (atoi(q4_k_bin_dp4a_env) != 0) + : true; // dot prod has to be available - iq4nl_dense_dp4a_on = backend_ctx->has_integer_dot && iq4nl_dense_dp4a_on; + q4_k_bin_dp4a_on = backend_ctx->has_integer_dot && q4_k_bin_dp4a_on; - if (iq4nl_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a - && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { - cl_mem a_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + if (q4_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin) { + const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; + const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); - const size_t n_blocks = (size_t)N * (K / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - cl_int tb = (cl_int)n_blocks; + cl_mem b_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_int tb = (cl_int)((size_t)N * (K / 32)); cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_iq4_nl_q8_1_dp4a; - int ai = 0; - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_iq4_nl->q)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_iq4_nl->d)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + cl_mem d_sub = nullptr; + cl_mem d_img = nullptr; + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + kernel = backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin; - CL_CHECK(clReleaseMemObject(a_sub)); + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_int), &N)); + + size_t local_work_size[3] = { 64, 1, 1 }; + size_t global_work_size[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub)); + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub)); return; } cl_mem b_sub_buf = nullptr; - cl_mem b_sub_buf_trans = nullptr; - cl_mem b_img = nullptr; - cl_mem b_img_trans = nullptr; - - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_mem b_padded = nullptr; + cl_mem b_buf = nullptr; + if (N_pad == N) { + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + b_buf = b_sub_buf; + } else { + CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, (size_t)K * N_pad * sizeof(float), NULL, &err), err)); + const float zero = 0.0f; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); + b_buf = b_padded; + } - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; + img_fmt = { CL_R, CL_FLOAT }; memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N_pad; + img_desc.buffer = b_buf; + cl_mem b_img; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // pad N to multiple of 8 - int extra_elements = N % 8; - int padding = 0; - if (extra_elements > 0){ - padding = 8 - extra_elements; - } - - // subbuffer for transposed activations - region.origin = 0; - region.size = K * (N + padding) * sizeof(float)/2; - backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // image for transposed activations - img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + cl_mem d_sub_buf; + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + img_fmt = { CL_R, CL_FLOAT }; memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * (N + padding) / 4; - img_desc.buffer = b_sub_buf_trans; - CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - - // transpose activations - int height_B = N/4; - if (height_B == 0) { - height_B = 1; - } - int width_B = K/4; - int padded_height_B = (N + padding)/4; - - kernel = backend_ctx->kernel_transpose_32_16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - - size_t local_work_size_t[2] = { 1, 16 }; - size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - - // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_iq4_nl_f32; - int padded_N = N + padding; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne1)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub_buf; + cl_mem d_img; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; - size_t local_work_size[3] = {1, 128, 1}; + kernel = backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_uint), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_uint), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &N)); + size_t local_work_size[3] = { 64, 2, 2 }; + size_t m_tiles = (size_t)CEIL_DIV(M, 64); + size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); + if (b_sub_buf) { + CL_CHECK(clReleaseMemObject(b_sub_buf)); + } + if (b_padded) { + CL_CHECK(clReleaseMemObject(b_padded)); + } + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); -#endif } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -21123,33 +26278,21 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - GGML_ASSERT(src0->type == GGML_TYPE_Q8_0); - GGML_ASSERT(src1->type == GGML_TYPE_F32); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - // SoA extra lives on view_src (view->extra is pre-SoA). - const ggml_tensor * soa0_src = src0->view_src != nullptr ? src0->view_src : src0; - ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)soa0_src->extra; + ggml_tensor_extra_cl_q4_K * extra0_q4_k = (ggml_tensor_extra_cl_q4_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; - const int ne02 = src0->ne[2]; - const int ne10 = src1->ne[0]; - const int ne12 = src1->ne[2]; - - const int ne0 = dst->ne[0]; const int ne1 = dst->ne[1]; - GGML_ASSERT(ne00 == ne10); - GGML_ASSERT((ne00 % 32) == 0); - GGML_ASSERT(ne0 == ne01); + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); cl_context context = backend_ctx->context; cl_kernel kernel; @@ -21163,23 +26306,56 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t int N = ne1; int K = ne00; - if (ne1 == 1) { + cl_uchar mask_d6 = 0x3F; + cl_uchar mask_d4 = 0x0F; + cl_uchar mask_hi2 = 0xC0; + + // Multi-column verify GEMV: route the spec/MTP verify batch (ne1==3 = 2 + // drafts + 1 bonus) onto the efficient GEMV path (subgroup-broadcast, no + // transpose) instead of the transposed-GEMM dead-zone. Reuses the ne1==1 + // GEMV setup (the activation image is already sized by N=ne1). Byte- + // identical. Opt-in via GGML_OPENCL_Q4K_MC3=1 while validating. + static const bool q4k_mc3 = (getenv("GGML_OPENCL_Q4K_MC3") != nullptr); + // Per-layer only (ne01 < 32768): the batched large-vocab lm_head at ne1==3 + // is left to the existing routing (corrupts on the Adreno GEMV path; x2- + // unified routes batched Q6_K lm_head to CPU). Per-layer mc3 is byte-identical. + const bool use_mc3 = q4k_mc3 && (ne1 == 3) && (ne01 < 32768); + + const bool use_bin = use_q4_k_bin_kernels(backend_ctx, src0); + + if (use_bin) { + if (use_mc3) { + static bool warned = false; + if (!warned) { + GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q4K_MC3 is bypassed by Q4_K binary kernels\n"); + warned = true; + } + } + ggml_cl_mul_mat_q4_k_f32_adreno_ila(backend, src0, src1, dst); + return; + } + + if (ne1 == 1 || use_mc3) { cl_mem q_img = nullptr; cl_mem b_sub_buf = nullptr; cl_mem b_img = nullptr; - // image for q - img_fmt = { CL_R, CL_UNSIGNED_INT32}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 4; - img_desc.buffer = extra0_q8_0->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + const bool use_tiled = !use_mc3 && use_q4k_tiled(backend_ctx, src0); - // create a sub_buffer for B + // image for q (not needed for the tiled path, which reads __global) + if (!use_tiled) { + img_fmt = { CL_R, CL_UNSIGNED_INT32}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q4_k->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + } + + // subbuffer for activations region.origin = offset1; region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer((extra1->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); // image for activations img_fmt = {CL_RGBA, CL_FLOAT}; @@ -21189,48 +26365,91 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // Split-K for small-M decode GEMVs. The base kernel puts one output row - // per lane and splits K only inside one workgroup, so M is the sole source - // of workgroup parallelism: gpt-oss's K and V projections are M=512 = 8 - // workgroups on a 16-CU X2, and the kernel measures 48 GB/s where the - // M=2880/4096 projections in the same decode graph reach 122-123. Mirrors - // the q4_0/q4_K split-K above and reuses their reduce kernel. + // 4-output-per-WI o4 variant for the long-vocab lm_head/embed GEMV + // (ne01 = vocab ~256K on Gemma): shares one activation read across 4 + // output rows. Gated to large ne01 (lm_head/embed). Default on; opt-out + // GGML_OPENCL_Q4K_GEMV_O4=0. (Skipped when mc3 handles the ne1==3 verify.) + static const bool q4k_o4_env = []{ + const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_O4"); + return !e || e[0] == '\0' || e[0] != '0'; + }(); + const bool use_q4k_o4 = !use_tiled && !use_mc3 && q4k_o4_env && (ne01 % 4 == 0) && (ne01 >= 32768); + // Split-K across workgroups for small-M decode GEMVs. A single-token GEMV + // makes only CEIL_DIV(M/2,64) workgroups; even with the wide intra-WG split + // (16 subgroups) those all land on ONE CU, so small-M matmuls under-fill the + // 16 CUs and their bandwidth falls well short of what the large-M FFN matmuls + // reach. Adding a `ksplit` second grid dim that spreads K across WGs (+ a + // reduce pass) fills the CUs. Gate is M<=2560: the tiny M<=1024 ones only + // break even (the reduce dispatch eats the kernel win), but the big-K M=2560 + // cases (ffn_down, attn_output) make the per-call win dwarf the reduce, and + // are byte-identical. ffn_gate/up (large M) fill the CUs already and are excluded. // - // Enabled where it is measured to win, like the q4_K gate: X2-90 +2.8% - // tg32 @d4096 on gpt-oss; Adreno 840 (12 CU) NEUTRAL on Llama-3.2-3B-Q8_0 - // (0.0% @d4096 -- its K/V proj is M=1024 = 16 workgroups, which already - // fills 12 CUs). Unmeasured on X1E/A7X/A6X and the q4_K split-K measured - // -0.7% on X1E, so the default is not widened on absence of evidence. - static const bool q8_splitk_env_set = []{ - const char * e = std::getenv("GGML_OPENCL_Q8_GEMV_SPLITK"); + // DEVICE-GATED. Split-K buys GPU time by spending an extra kernel LAUNCH (the + // reduce), so it only pays where launches are cheap. That is a per-device + // property and it does not travel from the X2-90 this was tuned on. Measured + // with one binary, env A/B (tg32, GGML_OPENCL_Q4K_GEMV_SPLITK=0/1): + // + // X2-90 +3.36% gemma-4 E4B (the number this gate was built on) + // 840 -1.3% Qwen3.5-4B-Q4_K_M 14.00 -> 13.85 + // 850 -20.0% Qwen3-1.7B-Q4_K_M 6.97 -> 5.58 (6 interleaved reps) + // + // The kernel is not the problem. On the 850 split-K makes the GPU strictly + // faster -- total busy 537 -> 485 ms, this GEMV 43.7 -> 34.0 us/call (-22%) -- + // and still costs a fifth of decode, because the +3696 reduce dispatches cost + // ~550 us of HOST round-trip each against 2.7 us of GPU work (~200x; that part + // is ~95% host-bound at decode). The 840 pays the same tax at ~42 us/dispatch. + // Break-even needs launch cost below the ~9.7 us/call the split actually saves, + // so this is not a "the 850 is slow" adjustment that a faster part would fix -- + // the 840 is 13x cheaper per launch and still loses. + // + // Enabled where it is measured to win, i.e. X2E only. The X1-85 was measured + // afterwards and is NOT a win either: Qwen3.5-4B-Q4_K_M tg32, split-K off + // 17.98/18.10/18.19 vs on 18.03/17.91/17.97 = -0.7%, so X1E stays excluded on + // evidence rather than on absence of it. Do not widen this without a NEW + // measurement. The env still forces either way so every device stays measurable. + static const bool splitk_env_set = []{ + const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_SPLITK"); return e && e[0] != '\0'; }(); - static const bool q8_splitk_env_on = []{ - const char * e = std::getenv("GGML_OPENCL_Q8_GEMV_SPLITK"); + static const bool splitk_env_on = []{ + const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_SPLITK"); return !(e && e[0] == '0'); }(); - const bool q8_splitk_on = q8_splitk_env_set - ? q8_splitk_env_on + const bool splitk_wg_env = splitk_env_set + ? splitk_env_on : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); - if (q8_splitk_on && backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk && - ne01 <= 1024 && ne01 % 64 == 0) { + // Gate: small-M decode GEMVs that under-fill the 16 CUs even with the wide + // intra-WG split (all 16 subgroups land on one CU). M<=2560 covers Kcur/Vcur + // (M=1024), Qcur (2048), attn_output + ffn_down (2560). The tiny ones + // (M<=1024) only break even (reduce dispatch eats the kernel win), but the + // big-K M=2560 cases (ffn_down K=10240 @182us, attn_output @42us) have a + // large per-call win that dwarfs the ~5us reduce, so extending to 2560 nets + // positive end-to-end. ffn_gate/up (M=10240) already fill the CUs -> excluded. + const bool use_splitk = splitk_wg_env && !use_tiled && !use_q4k_o4 && !use_mc3 && ne01 <= 2560; + + if (use_splitk) { const int nsg = 8; - const int ksplit = 8; // -> 8 * M/64 workgroups - const size_t gx = (size_t) CEIL_DIV(ne01, 64) * 64; + const int ksplit = (ne01 <= 512) ? 8 : 4; // -> ~32 total WGs + const size_t gx = (size_t)CEIL_DIV(ne01/2, 64) * 64; backend_ctx->prealloc_splitk_partial.allocate( - backend_ctx->context, (size_t) ksplit * ne01 * sizeof(float)); + backend_ctx->context, (size_t)ksplit * ne01 * sizeof(float)); cl_mem partial = backend_ctx->prealloc_splitk_partial.buffer; - cl_kernel ks = backend_ctx->kernel_gemv_noshuffle_q8_0_f32_splitk; - CL_CHECK(clSetKernelArg(ks, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(ks, 1, sizeof(cl_mem), &extra0_q8_0->d)); - CL_CHECK(clSetKernelArg(ks, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(ks, 3, sizeof(cl_mem), &partial)); - CL_CHECK(clSetKernelArg(ks, 4, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(ks, 5, sizeof(cl_int), &ne01)); - size_t lsk[3] = { 64, (size_t) nsg, 1 }; - size_t gsk[3] = { gx, (size_t) (nsg * ksplit), 1 }; + cl_kernel ks = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_splitk; + CL_CHECK(clSetKernelArg(ks, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(ks, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(ks, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(ks, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(ks, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(ks, 5, sizeof(cl_mem), &partial)); + CL_CHECK(clSetKernelArg(ks, 6, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(ks, 7, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(ks, 8, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(ks, 9, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(ks, 10, sizeof(cl_uchar), &mask_hi2)); + size_t lsk[3] = {64, (size_t)nsg, 1}; + size_t gsk[3] = {gx, (size_t)(nsg * ksplit), 1}; backend_ctx->enqueue_ndrange_kernel(ks, 3, gsk, lsk, dst); cl_kernel kr = backend_ctx->kernel_gemv_splitk_reduce_f32; @@ -21239,146 +26458,271 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t CL_CHECK(clSetKernelArg(kr, 2, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kr, 3, sizeof(cl_int), &ne01)); CL_CHECK(clSetKernelArg(kr, 4, sizeof(cl_int), &ksplit)); - size_t lr[3] = { 64, 1, 1 }; - size_t gr[3] = { (size_t) CEIL_DIV(ne01, 64) * 64, 1, 1 }; + size_t lr[3] = {64, 1, 1}; + size_t gr[3] = {(size_t)CEIL_DIV(ne01, 64) * 64, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kr, 3, gr, lr, dst); - CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_img)); + if (q_img) CL_CHECK(clReleaseMemObject(q_img)); CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); return; } - kernel = backend_ctx->kernel_gemv_noshuffle_q8_0_f32; - - int r2 = 1; - int r3 = 1; + kernel = use_mc3 ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3 + : use_tiled ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_tiled + : use_q4k_o4 ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_o4 + : backend_ctx->kernel_gemv_noshuffle_q4_k_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + if (use_tiled) { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + } else { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_hi2)); + } - size_t wavesize = backend_ctx->adreno_wave_size; - size_t local_work_size[] = { wavesize, 4, 1 }; - size_t global_work_size[] = { CEIL_DIV(M, wavesize)*wavesize, 4, 1 }; + // Wide K-split for the decode GEMV: the default 4-subgroup K-split leaves + // each Adreno SP with only ~4 waves, too few to hide LPDDR weight-load + // latency, so even the large FFN matmuls run well below the achievable + // bandwidth. Widen to 16 subgroups/WG (= the 1024-lane Adreno WG max) so + // each SP holds enough in-flight memory requests. Prefill is unaffected (the + // GEMM path is separate) and coherence-identical (greedy output unchanged). + // Applies to the plain base + // GEMV only; tiled/o4/mc3 keep 4 (their reductions are hard-coded to 4). + // Layout-safe: the base kernel derives its K-split from get_local_size(1) + // and the packed block stride is a physical constant (independent of it). + // Opt-out: GGML_OPENCL_Q4K_GEMV_WIDE=0. + static const bool splitk_wide_env = []{ + const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_WIDE"); + return !e || e[0] == '\0' || e[0] != '0'; + }(); + const bool splitk_wide = splitk_wide_env && !use_tiled && !use_q4k_o4 && !use_mc3; + size_t nsg_y = splitk_wide ? 16 : 4; + // Cap the wide K-split by the kernel's real max WG. X1-class drivers cap + // this GEMV at 768 (< 64*16 = 1024), so an uncapped lws aborts the + // dispatch with CL_INVALID_WORK_GROUP_SIZE (-54) and breaks ALL q4_K + // decode for M>2560. nsg_y is a pure K-split (the base kernel reads it + // from get_local_size(1); the packed block stride is a physical constant), + // so halving it stays coherent — just a narrower split. X2 keeps 16 + // (maxwg 1024); X1 falls to 8. + if (splitk_wide) { + const size_t maxwg = backend_ctx->get_kernel_workgroup_size(kernel); + while (nsg_y > 4 && 64 * nsg_y > maxwg) { nsg_y >>= 1; } + } + size_t local_work_size[3] = {64, nsg_y, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(use_tiled ? ne01 : (use_q4k_o4 ? ne01/4 : ne01/2), 64)*64, nsg_y, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_img)); + if (q_img) CL_CHECK(clReleaseMemObject(q_img)); CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); } else { - static const char * q8_bin_dp4a_env = getenv("GGML_OPENCL_Q8_0_BIN_DP4A"); - const bool q8_bin_dp4a_on = backend_ctx->has_integer_dot && - (q8_bin_dp4a_env ? (atoi(q8_bin_dp4a_env) != 0) : true); - if (q8_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin - && M % 64 == 0) { - cl_mem a_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_mem b_sub_buf = nullptr; + cl_mem b_sub_buf_trans = nullptr; + cl_mem b_img = nullptr; + cl_mem b_img_trans = nullptr; - const size_t n_blocks = (size_t)N * (K / 32); + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - const size_t N_pad = ((size_t)N + 31) / 32 * 32; - const size_t n_blocks_pad = N_pad * (K / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N_pad * K * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks_pad * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_pad * sizeof(cl_half)); + // Only the tiled kernels can read the tiled layout (use_q4k_tiled). + if (use_q4k_tiled(backend_ctx, src0)) { + const size_t n_blocks = (size_t)N * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - cl_int tb = (cl_int)n_blocks; + cl_int tbq = (cl_int)n_blocks; cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tbq)); size_t q_local[1] = { 64 }; size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - cl_mem q_img = nullptr; - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * (size_t)K / 4; - img_desc.buffer = extra0_q8_0->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q4_K_f32_tiled_dp4a; + CL_CHECK(clSetKernelArg(dk, 0, sizeof(cl_mem), &extra0_q4_k->q)); + CL_CHECK(clSetKernelArg(dk, 1, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(dk, 2, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(dk, 3, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(dk, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, 6, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(dk, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, 9, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(dk, 10, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(dk, 11, sizeof(cl_int), &ne1)); + + const int WROWS_D = 4 * 64; + const int BN_DP = 8; + size_t dlocal[3] = {64, 4, 1}; + size_t dglobal[3] = {(size_t)CEIL_DIV(ne01, WROWS_D) * 64, 4, (size_t)CEIL_DIV(ne1, BN_DP)}; + backend_ctx->enqueue_ndrange_kernel(dk, 3, dglobal, dlocal, dst); - cl_mem d_sub_buf = nullptr; - cl_mem d_img = nullptr; - region.origin = extrad->offset; - region.size = (size_t)M * N * sizeof(float); - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub_buf; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + // CoopK handles without _bin use the same untiled weight layout as gemm_noshuffle_q4_k_f32. + // Activations use K-major Q8_1 SoA (K contiguous). + if (ggml_cl_coopk_dp4a_narrow_on(backend_ctx, dst, backend_ctx->rows_coopk_dp4a_q4_k) + && backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c4 != nullptr + && ((N <= 2) ? backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c4) != nullptr) { + const int cols = (N <= 2) ? 2 : 4; + const size_t size_qa = (size_t)cols * K * sizeof(cl_char); + const size_t n_blocks_padded = (size_t)cols * (K / 32); + const size_t size_qa_prev = backend_ctx->prealloc_moe_qa.size; + const size_t size_da_prev = backend_ctx->prealloc_moe_da.size; + backend_ctx->prealloc_moe_qa.allocate(context, size_qa); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks_padded * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_padded * sizeof(cl_half)); + if (backend_ctx->prealloc_moe_qa.size != size_qa_prev) { + const cl_char z8 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_qa.buffer, + &z8, sizeof(z8), 0, backend_ctx->prealloc_moe_qa.size, 0, NULL, NULL)); + } + if (backend_ctx->prealloc_moe_da.size != size_da_prev) { + const cl_half z16 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_da.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_da.size, 0, NULL, NULL)); + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_sa.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_sa.size, 0, NULL, NULL)); + } + + cl_int n_blocks = (cl_int)((size_t)N * (K / 32)); + cl_kernel kernel_quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(kernel_quant, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(kernel_quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 4, sizeof(cl_int), &n_blocks)); + size_t local_work_size_quant[1] = { 64 }; + size_t global_work_size_quant[1] = { (size_t)((((size_t)n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(kernel_quant, 1, global_work_size_quant, local_work_size_quant, dst); + + cl_kernel kernel_coopk = (N <= 2) ? backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q4_k_q8_1_dp4a_c4; + const cl_uchar mask_d6 = 0x3F, mask_d4 = 0x0F, mask_hi2 = 0xC0; + const cl_int n_padded = cols; + CL_CHECK(clSetKernelArg(kernel_coopk, 0, sizeof(cl_mem), &extra0_q4_k->q)); + CL_CHECK(clSetKernelArg(kernel_coopk, 1, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel_coopk, 2, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel_coopk, 3, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel_coopk, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 6, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_coopk, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_coopk, 9, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(kernel_coopk, 10, sizeof(cl_int), &n_padded)); + CL_CHECK(clSetKernelArg(kernel_coopk, 11, sizeof(cl_int), &K)); + CL_CHECK(clSetKernelArg(kernel_coopk, 12, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(kernel_coopk, 13, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel_coopk, 14, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel_coopk, 15, sizeof(cl_uchar), &mask_hi2)); + + const size_t nsg = (size_t)backend_ctx->nsg_coopk_dp4a_q4_k; + size_t local_work_size[3] = { 64, nsg, 1 }; + size_t global_work_size[3] = { (size_t)(M / backend_ctx->rows_coopk_dp4a_q4_k), nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel_coopk, 3, global_work_size, local_work_size, dst); - cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_ila_a8_bin; - cl_uint ne00_u = (cl_uint)K; - cl_uint ne01_u = (cl_uint)M; - CL_CHECK(clSetKernelArg(dk, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(dk, 1, sizeof(cl_mem), &extra0_q8_0->d)); - CL_CHECK(clSetKernelArg(dk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, 4, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(dk, 5, sizeof(cl_uint), &ne00_u)); - CL_CHECK(clSetKernelArg(dk, 6, sizeof(cl_uint), &ne01_u)); - CL_CHECK(clSetKernelArg(dk, 7, sizeof(int), &N)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } + + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + // pad N to multiple of 8 + int extra_elements = N % 8; + int padding = 0; + if (extra_elements > 0){ + padding = 8 - extra_elements; + } - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + // subbuffer for transposed activations + region.origin = 0; + region.size = K * (N + padding) * sizeof(float)/2; + backend_ctx->prealloc_act_trans.allocate(context, region.size); + CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); - CL_CHECK(clReleaseMemObject(a_sub)); - return; + // image for transposed activations + img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * (N + padding) / 4; + img_desc.buffer = b_sub_buf_trans; + CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + + // transpose activations + int height_B = N/4; + if (height_B == 0) { + height_B = 1; } + int width_B = K/4; + int padded_height_B = (N + padding)/4; - // dp4a dense q8_0 prefill GEMM. Quantizes the [N,K] activations to - // q8_1 and runs the int8 dot instead of the f16 half-dot. Large-batch - // (ne1>8) only; q8_0 weights are already int8 (no requant) and symmetric - // (no min term) - static const char * q8_dense_dp4a_env = getenv("GGML_OPENCL_Q8_DENSE_DP4A"); - static const char * q8_dense_wimg_env = getenv("GGML_OPENCL_Q8_DENSE_DP4A_WIMG"); - const bool q8_dense_wimg_on = q8_dense_wimg_env && (atoi(q8_dense_wimg_env) != 0); + kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - const bool q8_bin_loaded = (backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin != nullptr); - // bin kernel takes precedence - bool q8_dense_dp4a_on = q8_dense_wimg_on + size_t local_work_size_t[2] = { 1, 16 }; + size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); + + // dp4a (int8) dense prefill GEMM and weight via texture + static const char * q4k_dense_dp4a_env = getenv("GGML_OPENCL_Q4K_DENSE_DP4A"); + static const char * q4k_dense_wimg_env = getenv("GGML_OPENCL_Q4K_DENSE_DP4A_WIMG"); + + const bool q4k_dense_wimg_on = q4k_dense_wimg_env && (atoi(q4k_dense_wimg_env) != 0); + bool q4k_dense_dp4a_on = q4k_dense_wimg_on ? true - : q8_dense_dp4a_env - ? (atoi(q8_dense_dp4a_env) != 0) - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E && !q8_bin_loaded); - // dot prod has to be available - q8_dense_dp4a_on = backend_ctx->has_integer_dot && q8_dense_dp4a_on; + : q4k_dense_dp4a_env + ? (atoi(q4k_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); - if (q8_dense_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a - && N > 8 && (K % 32 == 0) && (M % 64 == 0)) { - cl_mem a_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((a_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + // dp4 has to be available + q4k_dense_dp4a_on = backend_ctx->has_integer_dot && q4k_dense_dp4a_on; + // Min N for the dp4a prefill GEMM, default 9, i.e., ne1 > 8 + static const char * q4k_dp4a_minn_env = getenv("GGML_OPENCL_Q4K_DP4A_MINN"); + const int q4k_dp4a_minn = q4k_dp4a_minn_env ? atoi(q4k_dp4a_minn_env) : 9; + + if (q4k_dense_dp4a_on && N >= q4k_dp4a_minn && (K % 32 == 0) && (M % 64 == 0)) { const size_t n_blocks = (size_t)N * (K / 32); backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); @@ -21386,7 +26730,7 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t cl_int tb = (cl_int)n_blocks; cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &a_sub)); + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); @@ -21395,11 +26739,11 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - // optional weight texture, the same CL_R/UINT32 view, width M*K/4 - cl_mem q8_q_img = nullptr; - bool use_wimg = q8_dense_wimg_on; + // check if weights go through texture + cl_mem q4k_q_img = nullptr; + bool use_wimg = q4k_dense_wimg_on; if (use_wimg) { - const size_t tex = (size_t)M * (size_t)K / 4; // uint32 texels + const size_t tex = (size_t)M * (size_t)K / 8; // uint32 texels = bytes/4 if (tex == 0 || tex > backend_ctx->image_max_buffer_size) { use_wimg = false; } else { @@ -21407,213 +26751,158 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; img_desc.image_width = tex; - img_desc.buffer = extra0_q8_0->q; - q8_q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); - if (err != CL_SUCCESS || q8_q_img == nullptr) { use_wimg = false; q8_q_img = nullptr; } + img_desc.buffer = extra0_q4_k->q; + q4k_q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); + if (err != CL_SUCCESS || q4k_q_img == nullptr) { + use_wimg = false; + q4k_q_img = nullptr; + } } } - cl_kernel dk = use_wimg ? backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg - : backend_ctx->kernel_gemm_noshuffle_q8_0_q8_1_dp4a; + const bool use_narrow = backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow != nullptr + && N <= backend_ctx->max_n_dp4a_narrow_q4_k; + static const char * q4_k_act_vload4_env = getenv("GGML_OPENCL_Q4_K_DP4A_ACT_VLOAD4"); + const bool q4_k_act_vload4_on = q4_k_act_vload4_env == nullptr || atoi(q4_k_act_vload4_env) != 0; + cl_kernel dk = use_narrow + ? (use_wimg ? backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow_wimg + : backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_narrow) + : use_wimg + ? backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg + : q4_k_act_vload4_on + ? backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_act_vload4 + : backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a; int ai = 0; if (use_wimg) { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q8_q_img)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q4k_q_img)); } else { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->q)); } - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->dm)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_hi2)); + const int tile_n = use_narrow ? backend_ctx->tile_n_dp4a_narrow_q4_k : backend_ctx->tile_n_dp4a_q4_k; size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, tile_n) }; backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); - if (q8_q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q8_q_img)); + if (q4k_q_img != nullptr) { + CL_CHECK(clReleaseMemObject(q4k_q_img)); } - CL_CHECK(clReleaseMemObject(a_sub)); - return; - } - - // use bin kernel if available - if (backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin) { - int K_pad = K; - - cl_mem b_sub_buf = nullptr; - cl_mem d_sub_buf = nullptr; - - cl_mem a_img = nullptr; - cl_mem s_img = nullptr; - cl_mem b_img = nullptr; - cl_mem d_img = nullptr; - - // subbuffer for activations - region.origin = offset1; - region.size = K_pad * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // Create subbuffer and image1d_buffer for dst - region.origin = (extrad->offset); // + dst->view_offs; - region.size = M * N * sizeof(float); - CL_CHECK((d_sub_buf = clCreateSubBuffer((extrad->data_device), 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // create an image for A - img_fmt = { CL_R, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 4; // Divide by 4 for char -> float - img_desc.buffer = extra0_q8_0->q; - CL_CHECK((a_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // create an image for Scale - img_fmt = { CL_R, CL_HALF_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 32; // Block size is 32 - img_desc.buffer = extra0_q8_0->d; - CL_CHECK((s_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // create an image for B from sub_buffer - img_fmt = {CL_R, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K_pad * N; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // img for d - img_fmt = {CL_R, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * N; - img_desc.buffer = d_sub_buf; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q8_0_f32_bin; - - bool layoutA_Mfirst = true; - bool layoutS_Mfirst = true; - bool layoutB_Nfirst = false; - bool layoutC_Mfirst = true; - - cl_uint lineStrideMatrixAinBytes = layoutA_Mfirst ? M * 4 : K; // int8 - cl_uint lineStrideMatrixSinBytes = layoutS_Mfirst ? M * 2 : (K / 32) * 2; // fp16 - cl_uint lineStrideMatrixBinBytes = layoutB_Nfirst ? N * 4 : K_pad * 4; // fp32 - cl_uint lineStrideMatrixCinBytes = layoutC_Mfirst ? M * 4 : N * 4; // fp32 - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &a_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &s_img)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &extra1->offset)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &extrad->offset)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &lineStrideMatrixAinBytes)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &lineStrideMatrixSinBytes)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &lineStrideMatrixBinBytes)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &lineStrideMatrixCinBytes)); - - size_t global_work_size[] = { 64, (size_t)CEIL_DIV(M, 64), (size_t)CEIL_DIV(N, 64)}; - size_t local_work_size[] = { 64, 2, 2 }; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); - CL_CHECK(clReleaseMemObject(a_img)); - CL_CHECK(clReleaseMemObject(s_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(b_img_trans)); return; } - cl_mem b_sub_buf = nullptr; - cl_mem b_sub_buf_trans = nullptr; - cl_mem b_img = nullptr; - cl_mem b_img_trans = nullptr; - - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - // pad N to multiple of 8 - int extra_elements = N % 8; - int padding = 0; - if (extra_elements > 0){ - padding = 8 - extra_elements; - } - - // subbuffer for transposed activations - region.origin = 0; - region.size = K * (N + padding) * sizeof(float)/2; - backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - // image for transposed activations - img_fmt = {CL_RGBA, CL_HALF_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * (N + padding) / 4; - img_desc.buffer = b_sub_buf_trans; - CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + // gemm + // Small-batch (medium n_q) occupancy fix: at ne1<=8 the 2x8 grid is + // (1, ceil(M/2)) -> ~M/256 workgroups, which under-occupies the SP and + // makes the GEMM much slower than the ne1==1 GEMV at the same weight + // traffic. The _r1 (1-row) kernel doubles the M-axis workgroup count + // and removes the accumulator spill. Opt-in via env while validating. + static const bool q4k_gemm_r1 = (getenv("GGML_OPENCL_Q4K_GEMM_R1") != nullptr); + static const bool q4k_gemm_kimg = (getenv("GGML_OPENCL_Q4K_GEMM_KIMG") != nullptr); + // Cooperative-K (intra-WG K-split + reduction) for the small-batch + // (n_q in [2..8]) path: DEFAULT ON, opt out with GGML_OPENCL_Q4K_GEMM_COK=0. + // Byte-identical greedy output; large-batch (ne1>8) untouched. + static const char * q4k_cok_env = getenv("GGML_OPENCL_Q4K_GEMM_COK"); + static const bool q4k_gemm_cok = (q4k_cok_env == nullptr) || (atoi(q4k_cok_env) != 0); + const bool use_cok = q4k_gemm_cok && (ne1 <= 8); + const bool use_r1 = !use_cok && q4k_gemm_r1 && (ne1 <= 8); + // Weights-as-image (L1/TPL1) for the small-batch weight-read-bound path. + const bool use_kimg = !use_cok && !use_r1 && q4k_gemm_kimg && (ne1 <= 8); - // transpose activations - int height_B = N/4; - if (height_B == 0) { - height_B = 1; + cl_mem q_img = nullptr; + if (use_kimg) { + img_fmt = { CL_R, CL_UNSIGNED_INT32 }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q4_k->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); } - int width_B = K/4; - int padded_height_B = (N + padding)/4; - - kernel = backend_ctx->kernel_transpose_32_16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - - size_t local_work_size_t[2] = { 1, 16 }; - size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); - // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q8_0_f32; + kernel = use_cok ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_cok + : use_r1 ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_r1 + : use_kimg ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_kimg + : backend_ctx->kernel_gemm_noshuffle_q4_k_f32; int padded_N = N + padding; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &N)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); + if (use_kimg) { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + } else { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q)); + } + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->s)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_uchar), &mask_hi2)); - size_t global_work_size[] = { (size_t)CEIL_DIV(N, 8), (size_t)CEIL_DIV(M, 4), 1 }; - size_t local_work_size[] = { 2, 128, 1 }; + size_t global_work_size[3]; + size_t local_work_size[3]; + if (use_cok) { + // (COK_SG lanes x COK_NSG subgroups): one row per lane, K split + // across the COK_NSG subgroups. ne01 is a multiple of 64. + global_work_size[0] = (size_t)ne01; // rows + global_work_size[1] = 8; // COK_NSG + global_work_size[2] = 1; + local_work_size[0] = 64; // COK_SG + local_work_size[1] = 8; // COK_NSG + local_work_size[2] = 1; + } else if (use_r1) { + // 1 row per WI (opt-in occupancy experiment). + global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); + global_work_size[1] = (size_t)ne01; + global_work_size[2] = 1; + local_work_size[0] = 1; + local_work_size[1] = 128; + local_work_size[2] = 1; + } else if (use_kimg) { + // kimg is a 2-row tile (opt-in weights-as-image experiment). + global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); + global_work_size[1] = (size_t)CEIL_DIV(ne01, 2); + global_work_size[2] = 1; + local_work_size[0] = 1; + local_work_size[1] = 128; + local_work_size[2] = 1; + } else { + // Default: x2-unified base kernel is the 4-row (gx<<2) tile. + global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); + global_work_size[1] = (size_t)CEIL_DIV(ne01, 4); + global_work_size[2] = 1; + local_work_size[0] = 1; + local_work_size[1] = 128; + local_work_size[2] = 1; + } backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - - CL_CHECK(clReleaseMemObject(b_img_trans)); + if (q_img) CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img_trans)); } #else GGML_UNUSED(backend); @@ -21624,7 +26913,7 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t } #ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, +static void ggml_cl_mul_mat_q6_K_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -21635,9 +26924,9 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_K * extra0_q4_k = (ggml_tensor_extra_cl_q4_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; @@ -21652,18 +26941,18 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg cl_context context = backend_ctx->context; cl_kernel kernel; - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; + cl_int err; + cl_buffer_region region; + cl_image_format img_fmt; + cl_image_desc img_desc; - int M = ne01; - int N = ne1; - int K = ne00; + const int M = ne01; + const int N = ne1; + const int K = ne00; if (ne1 == 1) { - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; region.origin = offset1; region.size = (size_t)K * N * sizeof(float); @@ -21676,11 +26965,11 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + kernel = backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh_img)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); @@ -21691,20 +26980,20 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg size_t global_work_size[3] = { (size_t)ne01, 8, 1 }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(b_sub_buf)); CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); } else { const int gemm_tile_n = 64; int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n; - static const char * q4_k_bin_dp4a_env = getenv("GGML_OPENCL_Q4_K_BIN_DP4A"); - bool q4_k_bin_dp4a_on = q4_k_bin_dp4a_env - ? (atoi(q4_k_bin_dp4a_env) != 0) + static const char * q6_k_bin_dp4a_env = getenv("GGML_OPENCL_Q6_K_BIN_DP4A"); + bool q6_k_bin_dp4a_on = q6_k_bin_dp4a_env + ? (atoi(q6_k_bin_dp4a_env) != 0) : true; // dot prod has to be available - q4_k_bin_dp4a_on = backend_ctx->has_integer_dot && q4_k_bin_dp4a_on; + q6_k_bin_dp4a_on = backend_ctx->has_integer_dot && q6_k_bin_dp4a_on; - if (q4_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin) { + if (q6_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin) { const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); @@ -21741,20 +27030,19 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg img_desc.buffer = d_sub; CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_ila_a8_bin; + kernel = backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin; cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->ql_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); size_t local_work_size[3] = { 64, 1, 1 }; size_t global_work_size[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; @@ -21802,11 +27090,11 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg cl_mem d_img; CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); + kernel = backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_img)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_uint), &ne00)); @@ -21831,7 +27119,7 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const gg } #endif // GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +static void ggml_cl_mul_mat_q6_K_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -21842,308 +27130,372 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_t ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q4_K * extra0_q4_k = (ggml_tensor_extra_cl_q4_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; - const int ne1 = dst->ne[1]; + const int ne1 = dst->ne[1]; GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); cl_context context = backend_ctx->context; cl_kernel kernel; - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; - - int M = ne01; - int N = ne1; - int K = ne00; - - cl_uchar mask_d6 = 0x3F; - cl_uchar mask_d4 = 0x0F; - cl_uchar mask_hi2 = 0xC0; + cl_int err; + cl_buffer_region region; + cl_image_format img_fmt; + cl_image_desc img_desc; - // Multi-column verify GEMV: route the spec/MTP verify batch (ne1==3 = 2 - // drafts + 1 bonus) onto the efficient GEMV path (subgroup-broadcast, no - // transpose) instead of the transposed-GEMM dead-zone. Reuses the ne1==1 - // GEMV setup (the activation image is already sized by N=ne1). Byte- - // identical. Opt-in via GGML_OPENCL_Q4K_MC3=1 while validating. - static const bool q4k_mc3 = (getenv("GGML_OPENCL_Q4K_MC3") != nullptr); - // Per-layer only (ne01 < 32768): the batched large-vocab lm_head at ne1==3 - // is left to the existing routing (corrupts on the Adreno GEMV path; x2- - // unified routes batched Q6_K lm_head to CPU). Per-layer mc3 is byte-identical. - const bool use_mc3 = q4k_mc3 && (ne1 == 3) && (ne01 < 32768); + // subbuffer and image for activation + // Multi-column verify GEMV: route the spec/MTP verify q6_K matmuls (ne1==3) + // onto the efficient GEMV path instead of the transposed-GEMM dead-zone. + // Reuses the ne1==1 image setup (activation image sized by N=ne1). Byte- + // identical. Opt-in via GGML_OPENCL_Q6K_MC3=1 while validating. + static const bool q6k_mc3 = (getenv("GGML_OPENCL_Q6K_MC3") != nullptr); + // Per-layer only (ne01 < 32768): batched large-vocab lm_head stays on the + // existing path (x2-unified routes batched Q6_K lm_head to CPU; the Adreno + // GEMV corrupts it). Per-layer mc3 is byte-identical. + const bool use_q6k_mc3 = q6k_mc3 && (ne1 == 3) && (ne01 < 32768); + // Batched verify lm_head/embed (ne1==3, tiled layout): multi-column tiled + // GEMV — streams the large lm_head weight once across the 3 verify columns + // (the #1 MTP bottleneck; mc3 above can't, it reads the noshuffle layout). + const bool use_q6k_tiled_mc = q6k_mc3 && (ne1 == 3) && (ne01 >= 32768) && use_q6k_tiled(backend_ctx, src0); - const bool use_bin = use_q4_k_bin_kernels(backend_ctx, src0); + const bool use_bin = use_q6_k_bin_kernels(backend_ctx, src0); if (use_bin) { - if (use_mc3) { + if (use_q6k_mc3 || use_q6k_tiled_mc) { static bool warned = false; if (!warned) { - GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q4K_MC3 is bypassed by Q4_K binary kernels\n"); + GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q6K_MC3 is bypassed by Q6_K binary kernels\n"); warned = true; } } - ggml_cl_mul_mat_q4_k_f32_adreno_ila(backend, src0, src1, dst); + // This bin layout is not supported by CoopK. + ggml_cl_mul_mat_q6_K_f32_adreno_ila(backend, src0, src1, dst); return; } - if (ne1 == 1 || use_mc3) { - cl_mem q_img = nullptr; - cl_mem b_sub_buf = nullptr; + if (ne1 == 1 || use_q6k_mc3 || use_q6k_tiled_mc) { + cl_mem ql_img = nullptr; + cl_mem qh_img = nullptr; + cl_mem b_sub_buffer = nullptr; cl_mem b_img = nullptr; - const bool use_tiled = !use_mc3 && use_q4k_tiled(backend_ctx, src0); + // o4 = 4-output-per-WI variant for long-vocab lm_head/embed; gated to + // ne01 >= 32768 so per-layer q6_K (ne01=hidden 2-8K) keeps the 2-output + // kernel (o4 regresses there). o4_global reads the weights from __global + // coalesced instead of image1d_buffer -- the texture cache caps the + // read-once-per-token lm_head bandwidth, while __global reaches the higher + // rate the rest of the model gets. Both default ON; opt out via + // GGML_OPENCL_Q6K_GEMV_O4 / GGML_OPENCL_Q6K_GEMV_O4_GLOBAL = 0. + static const bool gemv_o4_env = []{ + const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_O4"); + return !e || e[0] == '\0' || e[0] != '0'; + }(); + static const bool o4_global_env = []{ + const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_O4_GLOBAL"); + return !e || e[0] == '\0' || e[0] != '0'; + }(); + const bool use_tiled = !use_q6k_mc3 && use_q6k_tiled(backend_ctx, src0); + const bool use_o4 = !use_tiled && !use_q6k_mc3 && gemv_o4_env && (ne01 % 4 == 0) && (ne01 >= 32768); + const bool use_o4_global = use_o4 && o4_global_env; + + // ql/qh image views are only needed when NOT reading weights from global. + if (!use_o4_global && !use_tiled) { + // image for ql + img_fmt.image_channel_order = CL_R; + img_fmt.image_channel_data_type = CL_FLOAT; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = ne01 * ne00 / 8; + img_desc.buffer = extra0_q6_K->ql; + CL_CHECK((ql_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // image for q (not needed for the tiled path, which reads __global) - if (!use_tiled) { - img_fmt = { CL_R, CL_UNSIGNED_INT32}; + // image for qh + img_fmt.image_channel_order = CL_R; + img_fmt.image_channel_data_type = CL_HALF_FLOAT; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q4_k->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_desc.image_width = ne01 * ne00 / 8; + img_desc.buffer = extra0_q6_K->qh; + CL_CHECK((qh_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); } - // subbuffer for activations region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + region.size = ne00 * ne1 * sizeof(float); + CL_CHECK((b_sub_buffer = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; + img_fmt.image_channel_order = CL_RGBA; + img_fmt.image_channel_data_type = CL_FLOAT; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; + img_desc.image_width = ne00 * ne1 / 4; + img_desc.buffer = b_sub_buffer; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // 4-output-per-WI o4 variant for the long-vocab lm_head/embed GEMV - // (ne01 = vocab ~256K on Gemma): shares one activation read across 4 - // output rows. Gated to large ne01 (lm_head/embed). Default on; opt-out - // GGML_OPENCL_Q4K_GEMV_O4=0. (Skipped when mc3 handles the ne1==3 verify.) - static const bool q4k_o4_env = []{ - const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_O4"); - return !e || e[0] == '\0' || e[0] != '0'; - }(); - const bool use_q4k_o4 = !use_tiled && !use_mc3 && q4k_o4_env && (ne01 % 4 == 0) && (ne01 >= 32768); - // Split-K across workgroups for small-M decode GEMVs. A single-token GEMV - // makes only CEIL_DIV(M/2,64) workgroups; even with the wide intra-WG split - // (16 subgroups) those all land on ONE CU, so small-M matmuls under-fill the - // 16 CUs and their bandwidth falls well short of what the large-M FFN matmuls - // reach. Adding a `ksplit` second grid dim that spreads K across WGs (+ a - // reduce pass) fills the CUs. Gate is M<=2560: the tiny M<=1024 ones only - // break even (the reduce dispatch eats the kernel win), but the big-K M=2560 - // cases (ffn_down, attn_output) make the per-call win dwarf the reduce, and - // are byte-identical. ffn_gate/up (large M) fill the CUs already and are excluded. - // - // DEVICE-GATED. Split-K buys GPU time by spending an extra kernel LAUNCH (the - // reduce), so it only pays where launches are cheap. That is a per-device - // property and it does not travel from the X2-90 this was tuned on. Measured - // with one binary, env A/B (tg32, GGML_OPENCL_Q4K_GEMV_SPLITK=0/1): - // - // X2-90 +3.36% gemma-4 E4B (the number this gate was built on) - // 840 -1.3% Qwen3.5-4B-Q4_K_M 14.00 -> 13.85 - // 850 -20.0% Qwen3-1.7B-Q4_K_M 6.97 -> 5.58 (6 interleaved reps) - // - // The kernel is not the problem. On the 850 split-K makes the GPU strictly - // faster -- total busy 537 -> 485 ms, this GEMV 43.7 -> 34.0 us/call (-22%) -- - // and still costs a fifth of decode, because the +3696 reduce dispatches cost - // ~550 us of HOST round-trip each against 2.7 us of GPU work (~200x; that part - // is ~95% host-bound at decode). The 840 pays the same tax at ~42 us/dispatch. - // Break-even needs launch cost below the ~9.7 us/call the split actually saves, - // so this is not a "the 850 is slow" adjustment that a faster part would fix -- - // the 840 is 13x cheaper per launch and still loses. - // - // Enabled where it is measured to win, i.e. X2E only. The X1-85 was measured - // afterwards and is NOT a win either: Qwen3.5-4B-Q4_K_M tg32, split-K off - // 17.98/18.10/18.19 vs on 18.03/17.91/17.97 = -0.7%, so X1E stays excluded on - // evidence rather than on absence of it. Do not widen this without a NEW - // measurement. The env still forces either way so every device stays measurable. - static const bool splitk_env_set = []{ - const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_SPLITK"); - return e && e[0] != '\0'; - }(); - static const bool splitk_env_on = []{ - const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_SPLITK"); - return !(e && e[0] == '0'); - }(); - const bool splitk_wg_env = splitk_env_set - ? splitk_env_on - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); - // Gate: small-M decode GEMVs that under-fill the 16 CUs even with the wide - // intra-WG split (all 16 subgroups land on one CU). M<=2560 covers Kcur/Vcur - // (M=1024), Qcur (2048), attn_output + ffn_down (2560). The tiny ones - // (M<=1024) only break even (reduce dispatch eats the kernel win), but the - // big-K M=2560 cases (ffn_down K=10240 @182us, attn_output @42us) have a - // large per-call win that dwarfs the ~5us reduce, so extending to 2560 nets - // positive end-to-end. ffn_gate/up (M=10240) already fill the CUs -> excluded. - const bool use_splitk = splitk_wg_env && !use_tiled && !use_q4k_o4 && !use_mc3 && ne01 <= 2560; - - if (use_splitk) { - const int nsg = 8; - const int ksplit = (ne01 <= 512) ? 8 : 4; // -> ~32 total WGs - const size_t gx = (size_t)CEIL_DIV(ne01/2, 64) * 64; + kernel = use_q6k_mc3 ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3 + : use_q6k_tiled_mc ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled_mc3 + : use_tiled ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled + : use_o4_global ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4_global + : use_o4 ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4 + : backend_ctx->kernel_gemv_noshuffle_q6_K_f32; - backend_ctx->prealloc_splitk_partial.allocate( - backend_ctx->context, (size_t)ksplit * ne01 * sizeof(float)); - cl_mem partial = backend_ctx->prealloc_splitk_partial.buffer; + if (use_o4_global || use_tiled) { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + } else { + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &ql_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh_img)); + } + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); - cl_kernel ks = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_splitk; - CL_CHECK(clSetKernelArg(ks, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(ks, 1, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(ks, 2, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(ks, 3, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(ks, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(ks, 5, sizeof(cl_mem), &partial)); - CL_CHECK(clSetKernelArg(ks, 6, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(ks, 7, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(ks, 8, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(ks, 9, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(ks, 10, sizeof(cl_uchar), &mask_hi2)); - size_t lsk[3] = {64, (size_t)nsg, 1}; - size_t gsk[3] = {gx, (size_t)(nsg * ksplit), 1}; - backend_ctx->enqueue_ndrange_kernel(ks, 3, gsk, lsk, dst); + const size_t gws_x = use_tiled + ? (size_t) CEIL_DIV(ne01, 64) * 64 + : use_o4 + ? (size_t) CEIL_DIV(ne01/4, 64) * 64 + : (size_t) CEIL_DIV(ne01/2, 64) * 64; + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {gws_x, 4, 1}; - cl_kernel kr = backend_ctx->kernel_gemv_splitk_reduce_f32; - CL_CHECK(clSetKernelArg(kr, 0, sizeof(cl_mem), &partial)); - CL_CHECK(clSetKernelArg(kr, 1, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kr, 2, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kr, 3, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kr, 4, sizeof(cl_int), &ksplit)); - size_t lr[3] = {64, 1, 1}; - size_t gr[3] = {(size_t)CEIL_DIV(ne01, 64) * 64, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kr, 3, gr, lr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - if (q_img) CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - return; - } + if (ql_img) CL_CHECK(clReleaseMemObject(ql_img)); + if (qh_img) CL_CHECK(clReleaseMemObject(qh_img)); + CL_CHECK(clReleaseMemObject(b_sub_buffer)); + CL_CHECK(clReleaseMemObject(b_img)); + } else { + // Tiled-layout batched GEMM. When the weight was converted to the 64-row + // tiled canonical layout (use_q6k_tiled — the default for lm_head/embed), + // the plain noshuffle GEMM below reads it as plain-transposed and produces + // garbage. Use the batched GEMM that matches the decode tiled GEMV's + // layout; it reads the f32 activation directly (column-major, no transpose). + if (use_q6k_tiled(backend_ctx, src0)) { + cl_mem b_sub_buf_t = nullptr; + cl_mem b_img_t = nullptr; - kernel = use_mc3 ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_mc3 - : use_tiled ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_tiled - : use_q4k_o4 ? backend_ctx->kernel_gemv_noshuffle_q4_k_f32_o4 - : backend_ctx->kernel_gemv_noshuffle_q4_k_f32; + region.origin = offset1; + region.size = ne00 * ne1 * sizeof(float); + CL_CHECK((b_sub_buf_t = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - if (use_tiled) { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); - } else { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_hi2)); - } + img_fmt.image_channel_order = CL_RGBA; + img_fmt.image_channel_data_type = CL_FLOAT; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = ne00 * ne1 / 4; + img_desc.buffer = b_sub_buf_t; + CL_CHECK((b_img_t = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - // Wide K-split for the decode GEMV: the default 4-subgroup K-split leaves - // each Adreno SP with only ~4 waves, too few to hide LPDDR weight-load - // latency, so even the large FFN matmuls run well below the achievable - // bandwidth. Widen to 16 subgroups/WG (= the 1024-lane Adreno WG max) so - // each SP holds enough in-flight memory requests. Prefill is unaffected (the - // GEMM path is separate) and coherence-identical (greedy output unchanged). - // Applies to the plain base - // GEMV only; tiled/o4/mc3 keep 4 (their reductions are hard-coded to 4). - // Layout-safe: the base kernel derives its K-split from get_local_size(1) - // and the packed block stride is a physical constant (independent of it). - // Opt-out: GGML_OPENCL_Q4K_GEMV_WIDE=0. - static const bool splitk_wide_env = []{ - const char * e = std::getenv("GGML_OPENCL_Q4K_GEMV_WIDE"); - return !e || e[0] == '\0' || e[0] != '0'; - }(); - const bool splitk_wide = splitk_wide_env && !use_tiled && !use_q4k_o4 && !use_mc3; - size_t nsg_y = splitk_wide ? 16 : 4; - // Cap the wide K-split by the kernel's real max WG. X1-class drivers cap - // this GEMV at 768 (< 64*16 = 1024), so an uncapped lws aborts the - // dispatch with CL_INVALID_WORK_GROUP_SIZE (-54) and breaks ALL q4_K - // decode for M>2560. nsg_y is a pure K-split (the base kernel reads it - // from get_local_size(1); the packed block stride is a physical constant), - // so halving it stays coherent — just a narrower split. X2 keeps 16 - // (maxwg 1024); X1 falls to 8. - if (splitk_wide) { - const size_t maxwg = backend_ctx->get_kernel_workgroup_size(kernel); - while (nsg_y > 4 && 64 * nsg_y > maxwg) { nsg_y >>= 1; } - } - size_t local_work_size[3] = {64, nsg_y, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(use_tiled ? ne01 : (use_q4k_o4 ? ne01/4 : ne01/2), 64)*64, nsg_y, 1}; + cl_kernel kt = backend_ctx->kernel_gemm_noshuffle_q6_K_f32_tiled; + CL_CHECK(clSetKernelArg(kt, 0, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(kt, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kt, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kt, 3, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(kt, 4, sizeof(cl_mem), &b_img_t)); + CL_CHECK(clSetKernelArg(kt, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kt, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kt, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kt, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kt, 9, sizeof(int), &ne1)); - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + // Must match the kernel: NTILES=4 64-row tiles per work-group (256 rows), + // BN=8 output columns per work-group. + const int BN_T = 16; + const int WROWS = 4 * 64; // NTILES * TILE_ROWS + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01, WROWS) * 64, 4, (size_t)CEIL_DIV(ne1, BN_T)}; + backend_ctx->enqueue_ndrange_kernel(kt, 3, global_work_size, local_work_size, dst); - if (q_img) CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { + CL_CHECK(clReleaseMemObject(b_img_t)); + CL_CHECK(clReleaseMemObject(b_sub_buf_t)); + return; + } - cl_mem b_sub_buf = nullptr; - cl_mem b_sub_buf_trans = nullptr; - cl_mem b_img = nullptr; - cl_mem b_img_trans = nullptr; + cl_mem b_sub_buf; + cl_mem b_buf_trans; + cl_mem b_img; + cl_mem b_img_trans; - // subbuffer for activations + // subbuffer for activation region.origin = offset1; - region.size = K * N * sizeof(float); + region.size = ne00 * ne1 * sizeof(float); CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; + // CoopK uses the same untiled weight layout as gemm_noshuffle_q6_K_f32, with K-major Q8_1 activations (K contiguous). + // Keep output and embedding weights on the existing path for logit stability. + if (ggml_cl_coopk_dp4a_narrow_on(backend_ctx, dst, backend_ctx->rows_coopk_dp4a_q6_k) + && backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c4 != nullptr + && strncmp(src0->name, "output", 6) != 0 + && strncmp(src0->name, "token_embd", 10) != 0 + && ((ne1 <= 2) ? backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c4) != nullptr) { + const int N = (int)ne1, K = (int)ne00; + const int cols = (N <= 2) ? 2 : 4; + const size_t n_blocks_padded = (size_t)cols * (K / 32); + const size_t size_qa = (size_t)cols * K * sizeof(cl_char); + const size_t size_qa_prev = backend_ctx->prealloc_moe_qa.size; + const size_t size_da_prev = backend_ctx->prealloc_moe_da.size; + backend_ctx->prealloc_moe_qa.allocate(context, size_qa); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks_padded * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks_padded * sizeof(cl_half)); + if (backend_ctx->prealloc_moe_qa.size != size_qa_prev) { + const cl_char z8 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_qa.buffer, + &z8, sizeof(z8), 0, backend_ctx->prealloc_moe_qa.size, 0, NULL, NULL)); + } + if (backend_ctx->prealloc_moe_da.size != size_da_prev) { + const cl_half z16 = 0; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_da.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_da.size, 0, NULL, NULL)); + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, backend_ctx->prealloc_moe_sa.buffer, + &z16, sizeof(z16), 0, backend_ctx->prealloc_moe_sa.size, 0, NULL, NULL)); + } + + cl_int n_blocks = (cl_int)((size_t)N * (K / 32)); + cl_kernel kernel_quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(kernel_quant, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(kernel_quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel_quant, 4, sizeof(cl_int), &n_blocks)); + size_t local_work_size_quant[1] = { 64 }; + size_t global_work_size_quant[1] = { (size_t)((((size_t)n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(kernel_quant, 1, global_work_size_quant, local_work_size_quant, dst); + + cl_kernel kernel_coopk = (N <= 2) ? backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c2 + : backend_ctx->kernel_gemm_coopk_q6_k_q8_1_dp4a_c4; + const cl_ushort mask_f000 = 0xF000; + const cl_uchar mask_c0 = 0xC0; + const cl_int n_padded = cols; + const cl_int m = (cl_int)ne01, k = (cl_int)ne00, n = (cl_int)ne1; + CL_CHECK(clSetKernelArg(kernel_coopk, 0, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(kernel_coopk, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kernel_coopk, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel_coopk, 3, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(kernel_coopk, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel_coopk, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_coopk, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_coopk, 8, sizeof(cl_int), &m)); + CL_CHECK(clSetKernelArg(kernel_coopk, 9, sizeof(cl_int), &n_padded)); + CL_CHECK(clSetKernelArg(kernel_coopk, 10, sizeof(cl_int), &k)); + CL_CHECK(clSetKernelArg(kernel_coopk, 11, sizeof(cl_int), &n)); + CL_CHECK(clSetKernelArg(kernel_coopk, 12, sizeof(cl_ushort), &mask_f000)); + CL_CHECK(clSetKernelArg(kernel_coopk, 13, sizeof(cl_uchar), &mask_c0)); + + const size_t nsg = (size_t)backend_ctx->nsg_coopk_dp4a_q6_k; + size_t local_work_size[3] = { 64, nsg, 1 }; + size_t global_work_size[3] = { (size_t)(ne01 / backend_ctx->rows_coopk_dp4a_q6_k), nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel_coopk, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } + + // dp4a (int8) dense q6_K prefill GEMM + static const char * q6k_dense_dp4a_env = getenv("GGML_OPENCL_Q6K_DENSE_DP4A"); + bool q6k_dense_dp4a_on = (q6k_dense_dp4a_env != nullptr) + ? (atoi(q6k_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen != ADRENO_GPU_GEN::X1E); + // dot prod has to be available + q6k_dense_dp4a_on = backend_ctx->has_integer_dot && q6k_dense_dp4a_on; + + const bool is_output_w_dp4a = strncmp(src0->name, "output", 6) == 0 || + strncmp(src0->name, "token_embd", 10) == 0; + + if (q6k_dense_dp4a_on && !is_output_w_dp4a && ne1 > 8 && (ne00 % 32 == 0) && (ne01 % 64 == 0)) { + const int M = ne01, N = ne1, K = ne00; + const size_t n_blocks = (size_t)N * (K / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + + cl_int tb = (cl_int)n_blocks; + cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + + static const char * q6_k_act_vload4_env = getenv("GGML_OPENCL_Q6_K_DP4A_ACT_VLOAD4"); + const bool q6_k_act_vload4_on = q6_k_act_vload4_env == nullptr || atoi(q6_k_act_vload4_env) != 0; + cl_kernel dk = q6_k_act_vload4_on + ? backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_act_vload4 + : backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a; + int ai = 0; + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + return; + } + + // image for activation + img_fmt.image_channel_order = CL_RGBA; + img_fmt.image_channel_data_type = CL_FLOAT; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; + img_desc.image_width = ne00 * ne1 / 4; img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); // pad N to multiple of 8 - int extra_elements = N % 8; + int extra_elements = ne1 % 8; int padding = 0; if (extra_elements > 0){ padding = 8 - extra_elements; } - // subbuffer for transposed activations + // subbuffer for transposed activation region.origin = 0; - region.size = K * (N + padding) * sizeof(float)/2; + region.size = ne00 * (ne1 + padding) * sizeof(float)/2; backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + CL_CHECK((b_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - // image for transposed activations - img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + // image for transposed activation + img_fmt.image_channel_order = CL_RGBA; + img_fmt.image_channel_data_type = CL_HALF_FLOAT; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * (N + padding) / 4; - img_desc.buffer = b_sub_buf_trans; + img_desc.image_width = ne00 * (ne1 + padding) / 4; + img_desc.buffer = b_buf_trans; CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); - // transpose activations - int height_B = N/4; + // transpose activation + int height_B = ne1/4; if (height_B == 0) { height_B = 1; } - int width_B = K/4; - int padded_height_B = (N + padding)/4; + int width_B = ne00/4; + int padded_height_B = (ne1 + padding) / 4; kernel = backend_ctx->kernel_transpose_32_16; CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); @@ -22152,214 +27504,288 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_t CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); - size_t local_work_size_t[2] = { 1, 16 }; - size_t global_work_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); + size_t local_size_t[2] = { 1, 16 }; + size_t global_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_size_t, local_size_t, dst); - // dp4a (int8) dense prefill GEMM and weight via texture - static const char * q4k_dense_dp4a_env = getenv("GGML_OPENCL_Q4K_DENSE_DP4A"); - static const char * q4k_dense_wimg_env = getenv("GGML_OPENCL_Q4K_DENSE_DP4A_WIMG"); + // gemm + // Cooperative-K small-batch (n_q in [2..8]) path: intra-WG K-split, + // mirrors the q4_K _cok path (batched serving). OPT-IN + // (GGML_OPENCL_Q6K_GEMM_COK=1), DEFAULT OFF: q6_K is the tied lm_head/ + // output projection, so the K-reassociation perturbs final logits and + // greedy is NOT byte-identical (op-tests pass, output coherent, but not + // bit-exact). It is also NEUTRAL on end-to-end MTP (q4_K cok already + // captured that; the MTP bottleneck moved off the GEMMs). Keep opt-in + // for batched serving until PPL-validated on a non-GDN q6_K model. + static const char * q6k_cok_env = getenv("GGML_OPENCL_Q6K_GEMM_COK"); + static const bool q6k_gemm_cok = (q6k_cok_env != nullptr) && (atoi(q6k_cok_env) != 0); + const bool use_q6k_cok = q6k_gemm_cok && (ne1 <= 8); + kernel = use_q6k_cok ? backend_ctx->kernel_gemm_noshuffle_q6_K_f32_cok + : backend_ctx->kernel_gemm_noshuffle_q6_K_f32; + int padded_N = ne1 + padding; + + cl_ushort mask_f000 = 0xF000; + cl_uchar mask_c0 = 0xC0; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ushort),&mask_f000)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_c0)); + + size_t global_work_size[3]; + size_t local_work_size[3]; + if (use_q6k_cok) { + global_work_size[0] = (size_t)ne01; // rows (1 per lane) + global_work_size[1] = 8; // COK_NSG + global_work_size[2] = 1; + local_work_size[0] = 64; // COK_SG + local_work_size[1] = 8; // COK_NSG + local_work_size[2] = 1; + } else { + global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); + global_work_size[1] = (size_t)CEIL_DIV(ne01, 4); + global_work_size[2] = 1; + local_work_size[0] = 2; + local_work_size[1] = 128; + local_work_size[2] = 1; + } + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img_trans)); + } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif +} + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static void ggml_cl_mul_mat_q5_K_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, + const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl_q5_K * extra0_q5_k = (ggml_tensor_extra_cl_q5_K *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + + const int ne1 = dst->ne[1]; + + GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + + cl_context context = backend_ctx->context; + cl_kernel kernel; + + cl_int err; + cl_buffer_region region; + cl_image_format img_fmt; + cl_image_desc img_desc; + + const int M = ne01; + const int N = ne1; + const int K = ne00; + + if (ne1 == 1) { + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; + + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + img_fmt = { CL_RGBA, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + kernel = backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne01)); - const bool q4k_dense_wimg_on = q4k_dense_wimg_env && (atoi(q4k_dense_wimg_env) != 0); - bool q4k_dense_dp4a_on = q4k_dense_wimg_on - ? true - : q4k_dense_dp4a_env - ? (atoi(q4k_dense_dp4a_env) != 0) - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + size_t local_work_size[3] = { 64, 8, 1 }; + size_t global_work_size[3] = { (size_t)ne01, 8, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - // dp4 has to be available - q4k_dense_dp4a_on = backend_ctx->has_integer_dot && q4k_dense_dp4a_on; + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + } else { + static const char * q5_k_bin_dp4a_env = getenv("GGML_OPENCL_Q5_K_BIN_DP4A"); + bool q5_k_bin_dp4a_on = q5_k_bin_dp4a_env + ? (atoi(q5_k_bin_dp4a_env) != 0) + : true; + // dot prod has to be available + q5_k_bin_dp4a_on = backend_ctx->has_integer_dot && q5_k_bin_dp4a_on; - // Min N for the dp4a prefill GEMM, default 9, i.e., ne1 > 8 - static const char * q4k_dp4a_minn_env = getenv("GGML_OPENCL_Q4K_DP4A_MINN"); - const int q4k_dp4a_minn = q4k_dp4a_minn_env ? atoi(q4k_dp4a_minn_env) : 9; + if (q5_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin) { + const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; + const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); - if (q4k_dense_dp4a_on && N >= q4k_dp4a_minn && (K % 32 == 0) && (M % 64 == 0)) { - const size_t n_blocks = (size_t)N * (K / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - cl_int tb = (cl_int)n_blocks; + cl_mem b_sub = nullptr; + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + cl_int tb = (cl_int)((size_t)N * (K / 32)); cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - // check if weights go through texture - cl_mem q4k_q_img = nullptr; - bool use_wimg = q4k_dense_wimg_on; - if (use_wimg) { - const size_t tex = (size_t)M * (size_t)K / 8; // uint32 texels = bytes/4 - if (tex == 0 || tex > backend_ctx->image_max_buffer_size) { - use_wimg = false; - } else { - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = tex; - img_desc.buffer = extra0_q4_k->q; - q4k_q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err); - if (err != CL_SUCCESS || q4k_q_img == nullptr) { - use_wimg = false; - q4k_q_img = nullptr; - } - } - } + cl_mem d_sub = nullptr; + cl_mem d_img = nullptr; + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - cl_kernel dk = use_wimg ? backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg - : backend_ctx->kernel_gemm_noshuffle_q4_k_q8_1_dp4a; - int ai = 0; - if (use_wimg) { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &q4k_q_img)); - } else { - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->q)); - } - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_hi2)); - // Must match the compile-time TILESIZE_N chosen at program build (per-device, - // X1E=8 else 32; env override). Same inputs -> same value. - int q4k_dp4a_ts = (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E) ? 8 : 32; - if (const char * e = getenv("GGML_OPENCL_Q4K_DP4A_TS")) q4k_dp4a_ts = atoi(e); - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, q4k_dp4a_ts) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - if (q4k_q_img != nullptr) { - CL_CHECK(clReleaseMemObject(q4k_q_img)); - } - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); - return; - } + kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin; - // gemm - // Small-batch (medium n_q) occupancy fix: at ne1<=8 the 2x8 grid is - // (1, ceil(M/2)) -> ~M/256 workgroups, which under-occupies the SP and - // makes the GEMM much slower than the ne1==1 GEMV at the same weight - // traffic. The _r1 (1-row) kernel doubles the M-axis workgroup count - // and removes the accumulator spill. Opt-in via env while validating. - static const bool q4k_gemm_r1 = (getenv("GGML_OPENCL_Q4K_GEMM_R1") != nullptr); - static const bool q4k_gemm_kimg = (getenv("GGML_OPENCL_Q4K_GEMM_KIMG") != nullptr); - // Cooperative-K (intra-WG K-split + reduction) for the small-batch - // (n_q in [2..8]) path: DEFAULT ON, opt out with GGML_OPENCL_Q4K_GEMM_COK=0. - // Byte-identical greedy output; large-batch (ne1>8) untouched. - static const char * q4k_cok_env = getenv("GGML_OPENCL_Q4K_GEMM_COK"); - static const bool q4k_gemm_cok = (q4k_cok_env == nullptr) || (atoi(q4k_cok_env) != 0); - const bool use_cok = q4k_gemm_cok && (ne1 <= 8); - const bool use_r1 = !use_cok && q4k_gemm_r1 && (ne1 <= 8); - // Weights-as-image (L1/TPL1) for the small-batch weight-read-bound path. - const bool use_kimg = !use_cok && !use_r1 && q4k_gemm_kimg && (ne1 <= 8); + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->qh)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_int), &N)); - cl_mem q_img = nullptr; - if (use_kimg) { - img_fmt = { CL_R, CL_UNSIGNED_INT32 }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q4_k->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + size_t local_work_size_dp4a[3] = { 64, 1, 1 }; + size_t global_work_size_dp4a[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size_dp4a, local_work_size_dp4a, dst); + + CL_CHECK(clReleaseMemObject(b_sub)); + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub)); + return; } - kernel = use_cok ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_cok - : use_r1 ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_r1 - : use_kimg ? backend_ctx->kernel_gemm_noshuffle_q4_k_f32_kimg - : backend_ctx->kernel_gemm_noshuffle_q4_k_f32; - int padded_N = N + padding; + const int gemm_tile_n = 64; + int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n; - if (use_kimg) { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + cl_mem b_sub_buf = nullptr; + cl_mem b_padded = nullptr; + cl_mem b_buf = nullptr; + if (N_pad == N) { + region.origin = offset1; + region.size = (size_t)K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + b_buf = b_sub_buf; } else { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q)); + CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, (size_t)K * N_pad * sizeof(float), NULL, &err), err)); + const float zero = 0.0f; + CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); + CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); + b_buf = b_padded; } - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->s)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_uchar), &mask_hi2)); - size_t global_work_size[3]; - size_t local_work_size[3]; - if (use_cok) { - // (COK_SG lanes x COK_NSG subgroups): one row per lane, K split - // across the COK_NSG subgroups. ne01 is a multiple of 64. - global_work_size[0] = (size_t)ne01; // rows - global_work_size[1] = 8; // COK_NSG - global_work_size[2] = 1; - local_work_size[0] = 64; // COK_SG - local_work_size[1] = 8; // COK_NSG - local_work_size[2] = 1; - } else if (use_r1) { - // 1 row per WI (opt-in occupancy experiment). - global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); - global_work_size[1] = (size_t)ne01; - global_work_size[2] = 1; - local_work_size[0] = 1; - local_work_size[1] = 128; - local_work_size[2] = 1; - } else if (use_kimg) { - // kimg is a 2-row tile (opt-in weights-as-image experiment). - global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); - global_work_size[1] = (size_t)CEIL_DIV(ne01, 2); - global_work_size[2] = 1; - local_work_size[0] = 1; - local_work_size[1] = 128; - local_work_size[2] = 1; - } else { - // Default: x2-unified base kernel is the 4-row (gx<<2) tile. - global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); - global_work_size[1] = (size_t)CEIL_DIV(ne01, 4); - global_work_size[2] = 1; - local_work_size[0] = 1; - local_work_size[1] = 128; - local_work_size[2] = 1; - } + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)K * N_pad; + img_desc.buffer = b_buf; + cl_mem b_img; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + region.origin = offsetd; + region.size = (size_t)M * N * sizeof(float); + cl_mem d_sub_buf; + CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + img_fmt = { CL_R, CL_FLOAT }; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)M * N; + img_desc.buffer = d_sub_buf; + cl_mem d_img; + CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &d_img)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_uint), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_uint), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &N)); + size_t local_work_size[3] = { 64, 2, 2 }; + size_t m_tiles = (size_t)CEIL_DIV(M, 64); + size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - if (q_img) CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); + if (b_sub_buf) { + CL_CHECK(clReleaseMemObject(b_sub_buf)); + } + if (b_padded) { + CL_CHECK(clReleaseMemObject(b_padded)); + } + CL_CHECK(clReleaseMemObject(d_img)); + CL_CHECK(clReleaseMemObject(d_sub_buf)); } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); -#endif } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS +static void ggml_cl_mul_mat_q5_K_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { #ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q6_K_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, - const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); GGML_ASSERT(src1); @@ -22369,17 +27795,16 @@ static void ggml_cl_mul_mat_q6_K_f32_adreno_ila(ggml_backend_t backend, const gg ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl_q5_K * extra0_q5_k = (ggml_tensor_extra_cl_q5_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; - - const int ne1 = dst->ne[1]; + const int ne1 = dst->ne[1]; GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); @@ -22387,1877 +27812,3060 @@ static void ggml_cl_mul_mat_q6_K_f32_adreno_ila(ggml_backend_t backend, const gg cl_kernel kernel; cl_int err; - cl_buffer_region region; cl_image_format img_fmt; cl_image_desc img_desc; + cl_buffer_region region; - const int M = ne01; - const int N = ne1; - const int K = ne00; + int M = ne01; + int N = ne1; + int K = ne00; - if (ne1 == 1) { - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + cl_uchar mask_d6 = 0x3F; + cl_uchar mask_d4 = 0x0F; + cl_uchar mask_hi2 = 0xC0; + + // Multi-column (N=3) verify GEMV for q5_K: route the spec/MTP verify batch + // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- + // zone (gemm_noshuffle_q5_k, the #2 chunk of MTP decode on a Q4_0-mix model + // after q4_0 mc3). Reuses the ne1==1 GEMV image setup (q + qh + activations). + // Opt-in via GGML_OPENCL_Q5K_MC3=1. Per-layer only (ne01 < 32768). + static const bool q5k_mc3 = (getenv("GGML_OPENCL_Q5K_MC3") != nullptr); + const bool use_q5k_mc3 = q5k_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); + + const bool use_bin = use_q5_k_bin_kernels(backend_ctx, src0); + + if (use_bin) { + if (use_q5k_mc3) { + static bool warned = false; + if (!warned) { + GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q5K_MC3 is bypassed by Q5_K binary kernels\n"); + warned = true; + } + } + ggml_cl_mul_mat_q5_K_f32_adreno_ila(backend, src0, src1, dst); + return; + } + + if (ne1 == 1 || use_q5k_mc3) { + cl_mem q_img = nullptr; + cl_mem qh_img = nullptr; + cl_mem b_sub_buf = nullptr; + cl_mem b_img = nullptr; + + // image for q (CL_R, CL_UNSIGNED_INT32): width = M*K/2/4 + img_fmt = {CL_R, CL_UNSIGNED_INT32}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 2 / 4; + img_desc.buffer = extra0_q5_k->q; + CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + + // image for qh (CL_R, CL_HALF_FLOAT): width = M*K/16 + img_fmt = {CL_R, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = M * K / 16; + img_desc.buffer = extra0_q5_k->qh; + CL_CHECK((qh_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + // subbuffer for activations region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); + region.size = K * N * sizeof(float); CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - img_fmt = { CL_RGBA, CL_FLOAT }; + // image for activations (CL_RGBA, CL_FLOAT): width = K*N/4 + img_fmt = {CL_RGBA, CL_FLOAT}; memset(&img_desc, 0, sizeof(img_desc)); img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N / 4; + img_desc.image_width = K * N / 4; img_desc.buffer = b_sub_buf; CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - kernel = backend_ctx->kernel_gemv_noshuffle_q6_k_f32_32b_trans; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh_img)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + kernel = use_q5k_mc3 ? backend_ctx->kernel_gemv_noshuffle_q5_k_f32_mc3 + : backend_ctx->kernel_gemv_noshuffle_q5_k_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh_img)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_hi2)); + if (use_q5k_mc3) { + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_int), &ne1)); // n_cols + } + + size_t local_work_size[3] = {64, 4, 1}; + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; - size_t local_work_size[3] = { 64, 8, 1 }; - size_t global_work_size[3] = { (size_t)ne01, 8, 1 }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(q_img)); + CL_CHECK(clReleaseMemObject(qh_img)); CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img)); } else { - const int gemm_tile_n = 64; - int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n; + cl_mem b_sub_buf = nullptr; + cl_mem b_sub_buf_trans = nullptr; + cl_mem b_img = nullptr; + cl_mem b_img_trans = nullptr; - static const char * q6_k_bin_dp4a_env = getenv("GGML_OPENCL_Q6_K_BIN_DP4A"); - bool q6_k_bin_dp4a_on = q6_k_bin_dp4a_env - ? (atoi(q6_k_bin_dp4a_env) != 0) - : true; - // dot prod has to be available - q6_k_bin_dp4a_on = backend_ctx->has_integer_dot && q6_k_bin_dp4a_on; + // subbuffer for activations + region.origin = offset1; + region.size = K * N * sizeof(float); + CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - if (q6_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin) { - const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; - const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); + // image for activations + img_fmt = {CL_RGBA, CL_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * N / 4; + img_desc.buffer = b_sub_buf; + CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); + // pad N to multiple of 8 + int extra_elements = N % 8; + int padding = 0; + if (extra_elements > 0) { + padding = 8 - extra_elements; + } + + // subbuffer for transposed activations + region.origin = 0; + region.size = K * (N + padding) * sizeof(float) / 2; + backend_ctx->prealloc_act_trans.allocate(context, region.size); + CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + + // image for transposed activations + img_fmt = {CL_RGBA, CL_HALF_FLOAT}; + memset(&img_desc, 0, sizeof(img_desc)); + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = K * (N + padding) / 4; + img_desc.buffer = b_sub_buf_trans; + CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + + // transpose activations + int height_B = N / 4; + if (height_B == 0) height_B = 1; + int width_B = K / 4; + int padded_height_B = (N + padding) / 4; + + kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); + + size_t local_work_size_t[2] = {1, 16}; + size_t global_work_size_t[2] = {(size_t)width_B, (size_t)padded_height_B}; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); + + // dp4a (int8) dense q5_K prefill GEMM + static const char * q5k_dense_dp4a_env = getenv("GGML_OPENCL_Q5K_DENSE_DP4A"); + bool q5k_dense_dp4a_on = q5k_dense_dp4a_env + ? (atoi(q5k_dense_dp4a_env) != 0) + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + // dot prod has to be available + q5k_dense_dp4a_on = backend_ctx->has_integer_dot && q5k_dense_dp4a_on; + + if (q5k_dense_dp4a_on && ne1 > 8 && (ne00 % 32 == 0) && (ne01 % 64 == 0)) { + const int Mm = ne01, Nn = ne1, Kk = ne00; + const size_t n_blocks = (size_t)Nn * (Kk / 32); + backend_ctx->prealloc_moe_qa.allocate(context, (size_t)Nn * Kk * sizeof(cl_char)); backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); - cl_mem b_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - cl_int tb = (cl_int)((size_t)N * (K / 32)); + cl_int tb = (cl_int)n_blocks; cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); + CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - - cl_mem d_sub = nullptr; - cl_mem d_img = nullptr; - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); - - kernel = backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a_ila_a8_bin; - - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->ql_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &K)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &M)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &N)); + CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); + size_t q_local[1] = { 64 }; + size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; + backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); - size_t local_work_size[3] = { 64, 1, 1 }; - size_t global_work_size[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + static const char * q5_k_act_vload4_env = getenv("GGML_OPENCL_Q5_K_DP4A_ACT_VLOAD4"); + const bool q5_k_act_vload4_on = q5_k_act_vload4_env == nullptr || atoi(q5_k_act_vload4_env) != 0; + cl_kernel dk = q5_k_act_vload4_on + ? backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_act_vload4 + : backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a; + int ai = 0; + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->q)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->qh)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Mm)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Nn)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Kk)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_hi2)); + size_t d_local[3] = { 64, 1, 1 }; + size_t d_global[3] = { 64, (size_t)(Mm / 64), (size_t)CEIL_DIV(Nn, 32) }; + backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); - CL_CHECK(clReleaseMemObject(b_sub)); - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_img_trans)); return; } - cl_mem b_sub_buf = nullptr; - cl_mem b_padded = nullptr; - cl_mem b_buf = nullptr; - if (N_pad == N) { - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - b_buf = b_sub_buf; - } else { - CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, (size_t)K * N_pad * sizeof(float), NULL, &err), err)); - const float zero = 0.0f; - CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); - b_buf = b_padded; - } - - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N_pad; - img_desc.buffer = b_buf; - cl_mem b_img; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + // gemm + kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_f32; + int padded_N = N + padding; - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - cl_mem d_sub_buf; - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub_buf; - cl_mem d_img; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->dm)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &padded_N)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_d6)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_uchar), &mask_d4)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_uchar), &mask_hi2)); - kernel = backend_ctx->kernel_gemm_noshuffle_q6_k_f32_32b_trans_ila_a8_bin; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_uint), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_uint), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &N)); + size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; + size_t local_work_size[3] = {1, 128, 1}; - size_t local_work_size[3] = { 64, 2, 2 }; - size_t m_tiles = (size_t)CEIL_DIV(M, 64); - size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clReleaseMemObject(b_sub_buf)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); CL_CHECK(clReleaseMemObject(b_img)); - if (b_sub_buf) { - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } - if (b_padded) { - CL_CHECK(clReleaseMemObject(b_padded)); - } - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); + CL_CHECK(clReleaseMemObject(b_img_trans)); } +#else + GGML_UNUSED(backend); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + GGML_UNUSED(dst); +#endif } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS - -static void ggml_cl_mul_mat_q6_K_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - - ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; +// Dequant a possibly-strided q4_0/q8_0 tensor to tight-packed f16. Returns a +// temp cl_mem the caller must release. SoA inputs are reconstructed into a +// temp AoS buffer reported via *extra_reconstruct (also caller-released). +// this is for quantized K cache without FA. +static cl_mem ggml_cl_mul_mat_dequant_quant_to_f16( + ggml_backend_opencl_context * backend_ctx, + const ggml_tensor * tensor, + cl_mem * extra_reconstruct /* out, may be NULL */ +) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0 || tensor->type == GGML_TYPE_Q8_0); - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + if (extra_reconstruct) { + *extra_reconstruct = NULL; + } - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; + cl_mem src_buf; + cl_ulong src_offset; + cl_ulong src_nb1; + cl_ulong src_nb2; + cl_ulong src_nb3; - const int ne1 = dst->ne[1]; + uintptr_t pool_key_buf = 0; + cl_ulong pool_key_off = (cl_ulong) tensor->view_offs; - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + const bool is_soa = tensor->type == GGML_TYPE_Q4_0 + ? ggml_cl_is_q4_0_soa(tensor) + : ggml_cl_is_q8_0_soa(tensor); - cl_context context = backend_ctx->context; - cl_kernel kernel; + cl_mem aos = nullptr; + if (is_soa) { + // Reconstruct full parent AoS; view's own nb[] then index it correctly. + const ggml_tensor * parent = tensor->view_src ? tensor->view_src : tensor; + const ggml_tensor * soa_src = parent; + const size_t block_bytes = (size_t) ggml_type_size(tensor->type); + const size_t blck_size = (size_t) ggml_blck_size(tensor->type); + const size_t parent_row_blocks = (size_t) parent->ne[0] / blck_size; + const size_t parent_row_bytes = parent_row_blocks * block_bytes; + const size_t parent_nbytes = (size_t) ggml_nelements(parent) / blck_size * block_bytes; - cl_int err; - cl_buffer_region region; - cl_image_format img_fmt; - cl_image_desc img_desc; + cl_int err; + aos = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, parent_nbytes, NULL, &err); + CL_CHECK(err); - // subbuffer and image for activation - // Multi-column verify GEMV: route the spec/MTP verify q6_K matmuls (ne1==3) - // onto the efficient GEMV path instead of the transposed-GEMM dead-zone. - // Reuses the ne1==1 image setup (activation image sized by N=ne1). Byte- - // identical. Opt-in via GGML_OPENCL_Q6K_MC3=1 while validating. - static const bool q6k_mc3 = (getenv("GGML_OPENCL_Q6K_MC3") != nullptr); - // Per-layer only (ne01 < 32768): batched large-vocab lm_head stays on the - // existing path (x2-unified routes batched Q6_K lm_head to CPU; the Adreno - // GEMV corrupts it). Per-layer mc3 is byte-identical. - const bool use_q6k_mc3 = q6k_mc3 && (ne1 == 3) && (ne01 < 32768); - // Batched verify lm_head/embed (ne1==3, tiled layout): multi-column tiled - // GEMV — streams the large lm_head weight once across the 3 verify columns - // (the #1 MTP bottleneck; mc3 above can't, it reads the noshuffle layout). - const bool use_q6k_tiled_mc = q6k_mc3 && (ne1 == 3) && (ne01 >= 32768) && use_q6k_tiled(backend_ctx, src0); + // large q4_0/q8_0 WEIGHTS are stored transposed and small weights + // (and the AoS KV-cache, handled in the else branch above) are not. + // choose a proper restore kernel based on this. + bool restored = false; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + const int p_ne00 = (int) parent->ne[0]; + const int p_ne01 = (int) parent->ne[1]; + if (tensor->type == GGML_TYPE_Q8_0 && enable_adreno_trans_weight(backend_ctx, parent)) { + auto * extra = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; + pool_key_buf = (uintptr_t) extra->q; + cl_kernel kernel = backend_ctx->kernel_restore_block_q8_0_trans; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_int), &p_ne00)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &p_ne01)); + size_t gws[] = { (size_t)(((p_ne01 + 63) / 64) * 64), 1, 1 }; + size_t lws[] = { 64, 1, 1 }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws, lws, 0, NULL, NULL)); + restored = true; + } else if (tensor->type == GGML_TYPE_Q4_0 && + use_adreno_kernels(backend_ctx, parent) && + !use_adreno_moe_kernels(backend_ctx, parent)) { + auto * extra = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; + pool_key_buf = (uintptr_t) extra->q; + const size_t size_q = (size_t) ggml_nelements(parent) / blck_size * (blck_size / 2); + const size_t size_d = (size_t) ggml_nelements(parent) / blck_size * sizeof(ggml_fp16_t); + cl_int err2 = CL_SUCCESS; + cl_mem buf_tq = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, size_q, NULL, &err2); CL_CHECK(err2); + cl_mem buf_td = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, size_d, NULL, &err2); CL_CHECK(err2); + transpose_2d_as_16b(backend_ctx, extra->q, buf_tq, size_q, p_ne01, p_ne00 / 4); + transpose_2d_as_16b(backend_ctx, extra->d, buf_td, size_d, p_ne01, p_ne00 / 32); + cl_uchar mask_0F = 0x0F, mask_F0 = 0xF0; + cl_kernel kernel = backend_ctx->kernel_restore_block_q4_0_noshuffle; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &buf_tq)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &buf_td)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_uchar), &mask_0F)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_uchar), &mask_F0)); + const size_t n_blk = parent_nbytes / block_bytes; + size_t gws[] = { n_blk, 1, 1 }; + size_t lws[] = { 1, 1, 1 }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws, lws, 0, NULL, NULL)); - const bool use_bin = use_q6_k_bin_kernels(backend_ctx, src0); + CL_CHECK(clReleaseMemObject(buf_tq)); + CL_CHECK(clReleaseMemObject(buf_td)); + restored = true; + } +#endif // GGML_OPENCL_USE_ADRENO_KERNELS - if (use_bin) { - if (use_q6k_mc3 || use_q6k_tiled_mc) { - static bool warned = false; - if (!warned) { - GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q6K_MC3 is bypassed by Q6_K binary kernels\n"); - warned = true; + if (!restored) { + cl_kernel kernel; + if (tensor->type == GGML_TYPE_Q8_0) { + auto * extra = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; + kernel = backend_ctx->kernel_restore_block_q8_0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); + pool_key_buf = (uintptr_t) extra->q; + } else { + auto * extra = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; + kernel = backend_ctx->kernel_restore_block_q4_0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); + pool_key_buf = (uintptr_t) extra->q; } - } - ggml_cl_mul_mat_q6_K_f32_adreno_ila(backend, src0, src1, dst); - return; - } - - if (ne1 == 1 || use_q6k_mc3 || use_q6k_tiled_mc) { - cl_mem ql_img = nullptr; - cl_mem qh_img = nullptr; - cl_mem b_sub_buffer = nullptr; - cl_mem b_img = nullptr; - // o4 = 4-output-per-WI variant for long-vocab lm_head/embed; gated to - // ne01 >= 32768 so per-layer q6_K (ne01=hidden 2-8K) keeps the 2-output - // kernel (o4 regresses there). o4_global reads the weights from __global - // coalesced instead of image1d_buffer -- the texture cache caps the - // read-once-per-token lm_head bandwidth, while __global reaches the higher - // rate the rest of the model gets. Both default ON; opt out via - // GGML_OPENCL_Q6K_GEMV_O4 / GGML_OPENCL_Q6K_GEMV_O4_GLOBAL = 0. - static const bool gemv_o4_env = []{ - const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_O4"); - return !e || e[0] == '\0' || e[0] != '0'; - }(); - static const bool o4_global_env = []{ - const char * e = std::getenv("GGML_OPENCL_Q6K_GEMV_O4_GLOBAL"); - return !e || e[0] == '\0' || e[0] != '0'; - }(); - const bool use_tiled = !use_q6k_mc3 && use_q6k_tiled(backend_ctx, src0); - const bool use_o4 = !use_tiled && !use_q6k_mc3 && gemv_o4_env && (ne01 % 4 == 0) && (ne01 >= 32768); - const bool use_o4_global = use_o4 && o4_global_env; + const size_t n_blocks = parent_nbytes / block_bytes; + size_t gws_rec[] = { n_blocks, 1, 1 }; + size_t lws_rec[] = { 1, 1, 1 }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws_rec, lws_rec, 0, NULL, NULL)); + } - // ql/qh image views are only needed when NOT reading weights from global. - if (!use_o4_global && !use_tiled) { - // image for ql - img_fmt.image_channel_order = CL_R; - img_fmt.image_channel_data_type = CL_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne01 * ne00 / 8; - img_desc.buffer = extra0_q6_K->ql; - CL_CHECK((ql_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + (void) parent_row_blocks; + (void) parent_row_bytes; + src_buf = aos; + src_offset = tensor->view_offs; + src_nb1 = tensor->nb[1]; + src_nb2 = tensor->nb[2]; + src_nb3 = tensor->nb[3]; - // image for qh - img_fmt.image_channel_order = CL_R; - img_fmt.image_channel_data_type = CL_HALF_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne01 * ne00 / 8; - img_desc.buffer = extra0_q6_K->qh; - CL_CHECK((qh_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + if (extra_reconstruct) { + *extra_reconstruct = aos; } + } else { + auto * extra = (ggml_tensor_extra_cl *) tensor->extra; + GGML_ASSERT(extra && extra->data_device); + src_buf = extra->data_device; + src_offset = extra->offset + tensor->view_offs; + src_nb1 = tensor->nb[1]; + src_nb2 = tensor->nb[2]; + src_nb3 = tensor->nb[3]; + pool_key_buf = (uintptr_t) extra->data_device; + pool_key_off = (cl_ulong) src_offset; + } - region.origin = offset1; - region.size = ne00 * ne1 * sizeof(float); - CL_CHECK((b_sub_buffer = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - - img_fmt.image_channel_order = CL_RGBA; - img_fmt.image_channel_data_type = CL_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne00 * ne1 / 4; - img_desc.buffer = b_sub_buffer; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + const cl_int nblk0 = (cl_int) (tensor->ne[0] / ggml_blck_size(tensor->type)); + const cl_int ne1_ = (cl_int) tensor->ne[1]; + const cl_int ne2_ = (cl_int) tensor->ne[2]; + const cl_int ne3_ = (cl_int) tensor->ne[3]; - kernel = use_q6k_mc3 ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_mc3 - : use_q6k_tiled_mc ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled_mc3 - : use_tiled ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_tiled - : use_o4_global ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4_global - : use_o4 ? backend_ctx->kernel_gemv_noshuffle_q6_K_f32_o4 - : backend_ctx->kernel_gemv_noshuffle_q6_K_f32; + const size_t out_bytes = (size_t) ggml_nelements(tensor) * sizeof(ggml_fp16_t); - if (use_o4_global || use_tiled) { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + // reuse a pooled f16 buffer for this KV-cache view across decode steps instead of + // allocating new one per attention op + cl_mem out = nullptr; + { + auto & pool = backend_ctx->dequant_f16_pool; + ggml_backend_opencl_context::ImagePoolKey key{pool_key_buf, (uint64_t) pool_key_off}; + auto it = pool.find(key); + if (it != pool.end() && it->second.k_bytes >= out_bytes && it->second.image) { + out = it->second.image; } else { - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &ql_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh_img)); + if (it != pool.end()) { + if (it->second.image) { CL_CHECK(clReleaseMemObject(it->second.image)); } + pool.erase(it); + } + cl_int err = CL_SUCCESS; + out = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, out_bytes, NULL, &err); + CL_CHECK(err); + ggml_backend_opencl_context::ImagePoolEntry entry; + entry.image = out; + entry.k_bytes = out_bytes; + pool[key] = entry; } - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); + } - const size_t gws_x = use_tiled - ? (size_t) CEIL_DIV(ne01, 64) * 64 - : use_o4 - ? (size_t) CEIL_DIV(ne01/4, 64) * 64 - : (size_t) CEIL_DIV(ne01/2, 64) * 64; - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {gws_x, 4, 1}; + cl_kernel dq_kernel = tensor->type == GGML_TYPE_Q8_0 + ? backend_ctx->kernel_dequant_q8_0_f16_view_aos + : backend_ctx->kernel_dequant_q4_0_f16_view_aos; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clSetKernelArg(dq_kernel, 0, sizeof(cl_mem), &src_buf)); + CL_CHECK(clSetKernelArg(dq_kernel, 1, sizeof(cl_ulong), &src_offset)); + CL_CHECK(clSetKernelArg(dq_kernel, 2, sizeof(cl_ulong), &src_nb1)); + CL_CHECK(clSetKernelArg(dq_kernel, 3, sizeof(cl_ulong), &src_nb2)); + CL_CHECK(clSetKernelArg(dq_kernel, 4, sizeof(cl_ulong), &src_nb3)); + CL_CHECK(clSetKernelArg(dq_kernel, 5, sizeof(cl_int), &nblk0)); + CL_CHECK(clSetKernelArg(dq_kernel, 6, sizeof(cl_int), &ne1_)); + CL_CHECK(clSetKernelArg(dq_kernel, 7, sizeof(cl_int), &ne2_)); + CL_CHECK(clSetKernelArg(dq_kernel, 8, sizeof(cl_int), &ne3_)); + CL_CHECK(clSetKernelArg(dq_kernel, 9, sizeof(cl_mem), &out)); - if (ql_img) CL_CHECK(clReleaseMemObject(ql_img)); - if (qh_img) CL_CHECK(clReleaseMemObject(qh_img)); - CL_CHECK(clReleaseMemObject(b_sub_buffer)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { - // Tiled-layout batched GEMM. When the weight was converted to the 64-row - // tiled canonical layout (use_q6k_tiled — the default for lm_head/embed), - // the plain noshuffle GEMM below reads it as plain-transposed and produces - // garbage. Use the batched GEMM that matches the decode tiled GEMV's - // layout; it reads the f32 activation directly (column-major, no transpose). - if (use_q6k_tiled(backend_ctx, src0)) { - cl_mem b_sub_buf_t = nullptr; - cl_mem b_img_t = nullptr; + size_t gws[3] = { (size_t) nblk0, (size_t) ne1_, (size_t) (ne2_ * ne3_) }; + size_t lws[3] = { 1, 1, 1 }; + CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, dq_kernel, 3, NULL, gws, lws, 0, NULL, NULL)); - region.origin = offset1; - region.size = ne00 * ne1 * sizeof(float); - CL_CHECK((b_sub_buf_t = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + // release the reconstructed aos if + // 1. it was actually reconstructed + // 2. the caller didn't request it to be returned + // src_buf may refer to aos, so we should release after this enqueue + if (aos && !extra_reconstruct) { + CL_CHECK(clReleaseMemObject(aos)); + } + return out; +} - img_fmt.image_channel_order = CL_RGBA; - img_fmt.image_channel_data_type = CL_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne00 * ne1 / 4; - img_desc.buffer = b_sub_buf_t; - CL_CHECK((b_img_t = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); +// look up or create a pooled image1d_buffer over a KV-cache view. +static cl_mem ggml_cl_img_pool_get_or_create( + ggml_backend_opencl_context * backend_ctx, + std::map & pool, + cl_mem data_device, + cl_ulong offset0, + size_t required_bytes, + cl_channel_type channel_data_type +) { + ggml_backend_opencl_context::ImagePoolKey key{(uintptr_t)data_device, (uint64_t)offset0}; + auto it = pool.find(key); + if (it != pool.end() + && it->second.k_bytes >= required_bytes + && it->second.channel_data_type == channel_data_type + && it->second.image != nullptr) { + return it->second.image; + } - cl_kernel kt = backend_ctx->kernel_gemm_noshuffle_q6_K_f32_tiled; - CL_CHECK(clSetKernelArg(kt, 0, sizeof(cl_mem), &extra0_q6_K->ql)); - CL_CHECK(clSetKernelArg(kt, 1, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(kt, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kt, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kt, 4, sizeof(cl_mem), &b_img_t)); - CL_CHECK(clSetKernelArg(kt, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kt, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kt, 7, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kt, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kt, 9, sizeof(int), &ne1)); + // need to create or recreate and release any stale entry first. + if (it != pool.end()) { + if (it->second.image) { CL_CHECK(clReleaseMemObject(it->second.image)); } + if (it->second.sub_buffer) {CL_CHECK(clReleaseMemObject(it->second.sub_buffer)); } + pool.erase(it); + } - // Must match the kernel: NTILES=4 64-row tiles per work-group (256 rows), - // BN=8 output columns per work-group. - const int BN_T = 16; - const int WROWS = 4 * 64; // NTILES * TILE_ROWS - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01, WROWS) * 64, 4, (size_t)CEIL_DIV(ne1, BN_T)}; - backend_ctx->enqueue_ndrange_kernel(kt, 3, global_work_size, local_work_size, dst); + cl_int status = CL_SUCCESS; + cl_buffer_region region = {}; + region.origin = (size_t)offset0; + region.size = required_bytes; + cl_mem sub = clCreateSubBuffer(data_device, 0, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); + if (status != CL_SUCCESS) { + return nullptr; + } + + const size_t pixel_size = (channel_data_type == CL_HALF_FLOAT) ? 8 : 16; + cl_image_format fmt = {CL_RGBA, channel_data_type}; + cl_image_desc desc = {}; + desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + desc.image_width = required_bytes / pixel_size; + desc.buffer = sub; + cl_mem img = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, + &fmt, &desc, NULL, &status); + if (status != CL_SUCCESS) { + CL_CHECK(clReleaseMemObject(sub)); + return nullptr; + } - CL_CHECK(clReleaseMemObject(b_img_t)); - CL_CHECK(clReleaseMemObject(b_sub_buf_t)); - return; - } + ggml_backend_opencl_context::ImagePoolEntry entry; + entry.sub_buffer = sub; + entry.image = img; + entry.k_bytes = required_bytes; + entry.channel_data_type = channel_data_type; + pool[key] = entry; + return img; +} - cl_mem b_sub_buf; - cl_mem b_buf_trans; - cl_mem b_img; - cl_mem b_img_trans; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS +static bool ggml_cl_mul_mat_q2_K_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q2_K * extra0 = (ggml_tensor_extra_cl_q2_K *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - // subbuffer for activation - region.origin = offset1; - region.size = ne00 * ne1 * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 16 ? 8 : 32; + cl_kernel gemm = n <= 16 ? backend_ctx->kernel_gemm_noshuffle_q2_k_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_q2_k_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_Q2_K_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - // dp4a (int8) dense q6_K prefill GEMM - static const char * q6k_dense_dp4a_env = getenv("GGML_OPENCL_Q6K_DENSE_DP4A"); - bool q6k_dense_dp4a_on = (q6k_dense_dp4a_env != nullptr) - ? (atoi(q6k_dense_dp4a_env) != 0) - : (backend_ctx->adreno_gen != ADRENO_GPU_GEN::X1E); - // dot prod has to be available - q6k_dense_dp4a_on = backend_ctx->has_integer_dot && q6k_dense_dp4a_on; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->dm)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - const bool is_output_w_dp4a = strncmp(src0->name, "output", 6) == 0 || - strncmp(src0->name, "token_embd", 10) == 0; +static bool ggml_cl_mul_mat_q3_K_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q3_K * extra0 = (ggml_tensor_extra_cl_q3_K *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - if (q6k_dense_dp4a_on && !is_output_w_dp4a && ne1 > 8 && (ne00 % 32 == 0) && (ne01 % 64 == 0)) { - const int M = ne01, N = ne1, K = ne00; - const size_t n_blocks = (size_t)N * (K / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)N * K * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 16 ? 8 : 32; + cl_kernel gemm = n <= 16 ? backend_ctx->kernel_gemm_noshuffle_q3_k_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_q3_k_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_Q3_K_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - cl_int tb = (cl_int)n_blocks; - cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); - CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->hm)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 10, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q6_k_q8_1_dp4a; - int ai = 0; - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->ql)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &M)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &N)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &K)); - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(M / 64), (size_t)CEIL_DIV(N, 32) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); +static bool ggml_cl_mul_mat_iq3_s_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq3_s * extra0 = (ggml_tensor_extra_cl_iq3_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - CL_CHECK(clReleaseMemObject(b_sub_buf)); - return; - } + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq3_s_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq3_s_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ3_S_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - // image for activation - img_fmt.image_channel_order = CL_RGBA; - img_fmt.image_channel_data_type = CL_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne00 * ne1 / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 10, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 11, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - // pad N to multiple of 8 - int extra_elements = ne1 % 8; - int padding = 0; - if (extra_elements > 0){ - padding = 8 - extra_elements; - } +static bool ggml_cl_mul_mat_iq3_xxs_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq3_xxs * extra0 = (ggml_tensor_extra_cl_iq3_xxs *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - // subbuffer for transposed activation - region.origin = 0; - region.size = ne00 * (ne1 + padding) * sizeof(float)/2; - backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ3_XXS_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - // image for transposed activation - img_fmt.image_channel_order = CL_RGBA; - img_fmt.image_channel_data_type = CL_HALF_FLOAT; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = ne00 * (ne1 + padding) / 4; - img_desc.buffer = b_buf_trans; - CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - // transpose activation - int height_B = ne1/4; - if (height_B == 0) { - height_B = 1; - } - int width_B = ne00/4; - int padded_height_B = (ne1 + padding) / 4; +static bool ggml_cl_mul_mat_iq1_m_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq1_m * extra0 = (ggml_tensor_extra_cl_iq1_m *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - kernel = backend_ctx->kernel_transpose_32_16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq1_m_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq1_m_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ1_M_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - size_t local_size_t[2] = { 1, 16 }; - size_t global_size_t[2] = { (size_t)width_B, (size_t)padded_height_B }; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_size_t, local_size_t, dst); + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - // gemm - // Cooperative-K small-batch (n_q in [2..8]) path: intra-WG K-split, - // mirrors the q4_K _cok path (batched serving). OPT-IN - // (GGML_OPENCL_Q6K_GEMM_COK=1), DEFAULT OFF: q6_K is the tied lm_head/ - // output projection, so the K-reassociation perturbs final logits and - // greedy is NOT byte-identical (op-tests pass, output coherent, but not - // bit-exact). It is also NEUTRAL on end-to-end MTP (q4_K cok already - // captured that; the MTP bottleneck moved off the GEMMs). Keep opt-in - // for batched serving until PPL-validated on a non-GDN q6_K model. - static const char * q6k_cok_env = getenv("GGML_OPENCL_Q6K_GEMM_COK"); - static const bool q6k_gemm_cok = (q6k_cok_env != nullptr) && (atoi(q6k_cok_env) != 0); - const bool use_q6k_cok = q6k_gemm_cok && (ne1 <= 8); - kernel = use_q6k_cok ? backend_ctx->kernel_gemm_noshuffle_q6_K_f32_cok - : backend_ctx->kernel_gemm_noshuffle_q6_K_f32; - int padded_N = ne1 + padding; +static bool ggml_cl_mul_mat_iq1_s_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq1_s * extra0 = (ggml_tensor_extra_cl_iq1_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - cl_ushort mask_f000 = 0xF000; - cl_uchar mask_c0 = 0xC0; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq1_s_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq1_s_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ1_S_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ushort),&mask_f000)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_c0)); + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 10, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - size_t global_work_size[3]; - size_t local_work_size[3]; - if (use_q6k_cok) { - global_work_size[0] = (size_t)ne01; // rows (1 per lane) - global_work_size[1] = 8; // COK_NSG - global_work_size[2] = 1; - local_work_size[0] = 64; // COK_SG - local_work_size[1] = 8; // COK_NSG - local_work_size[2] = 1; - } else { - global_work_size[0] = (size_t)CEIL_DIV(ne1, 8); - global_work_size[1] = (size_t)CEIL_DIV(ne01, 4); - global_work_size[2] = 1; - local_work_size[0] = 2; - local_work_size[1] = 128; - local_work_size[2] = 1; - } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +static bool ggml_cl_mul_mat_iq2_s_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_s * extra0 = (ggml_tensor_extra_cl_iq2_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img_trans)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq2_s_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq2_s_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ2_S_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); -#endif + + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 10, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 11, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q5_K_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0, - const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); +static bool ggml_cl_mul_mat_iq2_xs_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_xs * extra0 = (ggml_tensor_extra_cl_iq2_xs *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ2_XS_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - ggml_tensor_extra_cl_q5_K * extra0_q5_k = (ggml_tensor_extra_cl_q5_K *)src0->extra; +static bool ggml_cl_mul_mat_iq2_xxs_dp4a(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_xxs * extra0 = (ggml_tensor_extra_cl_iq2_xxs *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + const int tile_n = n <= 8 ? 8 : 32; + cl_kernel gemm = n <= 8 ? backend_ctx->kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a_narrow + : backend_ctx->kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a; + const char * env = getenv("GGML_OPENCL_IQ2_XXS_DENSE_DP4A"); + if (!gemm || !backend_ctx->has_integer_dot || (env && env[0] == '0') || + n <= 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + return false; + } - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - - const int ne1 = dst->ne[1]; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem activation = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + const size_t n_blocks = (size_t)n*(k/32); + backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, (size_t)n*k); + backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks*sizeof(cl_half)); + + cl_int nb = n_blocks; + cl_kernel quant = backend_ctx->kernel_quant_a_q8_1; + CL_CHECK(clSetKernelArg(quant, 0, sizeof(cl_mem), &activation)); + CL_CHECK(clSetKernelArg(quant, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(quant, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(quant, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); + CL_CHECK(clSetKernelArg(quant, 4, sizeof(cl_int), &nb)); + size_t q_global[] = { CEIL_DIV(n_blocks, 64)*64 }; + size_t q_local[] = { 64 }; + backend_ctx->enqueue_ndrange_kernel(quant, 1, q_global, q_local, dst); + + CL_CHECK(clSetKernelArg(gemm, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemm, 1, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(gemm, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemm, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(gemm, 4, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(gemm, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemm, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemm, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemm, 8, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(gemm, 9, sizeof(int), &k)); + size_t global[] = { 64, (size_t)CEIL_DIV(m, 64), (size_t)CEIL_DIV(n, tile_n) }; + size_t local[] = { 64, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemm, 3, global, local, dst); + CL_CHECK(clReleaseMemObject(activation)); + return true; +} - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); +static void ggml_cl_mul_mat_q2_k_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q2_K * extra0 = (ggml_tensor_extra_cl_q2_K *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - cl_context context = backend_ctx->context; - cl_kernel kernel; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_q2_k_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->dm)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_d)); + const size_t rows = 64*(size_t)backend_ctx->q2_k_mv_rows; + const size_t nsg = backend_ctx->q2_k_mv_nsg; + size_t global[] = { CEIL_DIV((size_t)m, rows)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - cl_int err; - cl_buffer_region region; - cl_image_format img_fmt; - cl_image_desc img_desc; + if (ggml_cl_mul_mat_q2_K_dp4a(backend, src0, src1, dst)) { + return; + } - const int M = ne01; - const int N = ne1; - const int K = ne00; + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - if (ne1 == 1) { - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - img_fmt = { CL_RGBA, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - kernel = backend_ctx->kernel_gemv_noshuffle_q5_k_f32_32b_trans; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne01)); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_q2_k_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - size_t local_work_size[3] = { 64, 8, 1 }; - size_t global_work_size[3] = { (size_t)ne01, 8, 1 }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +static void ggml_cl_mul_mat_q3_k_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_q3_K * extra0 = (ggml_tensor_extra_cl_q3_K *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } else { - static const char * q5_k_bin_dp4a_env = getenv("GGML_OPENCL_Q5_K_BIN_DP4A"); - bool q5_k_bin_dp4a_on = q5_k_bin_dp4a_env - ? (atoi(q5_k_bin_dp4a_env) != 0) - : true; - // dot prod has to be available - q5_k_bin_dp4a_on = backend_ctx->has_integer_dot && q5_k_bin_dp4a_on; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_q3_k_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->hm)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t rows = 64*(size_t)backend_ctx->q3_k_mv_rows; + const size_t nsg = backend_ctx->q3_k_mv_nsg; + size_t global[] = { CEIL_DIV((size_t)m, rows)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - if (q5_k_bin_dp4a_on && backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin) { - const int dp4a_N_pad = CEIL_DIV(N, 32) * 32; - const size_t n_blocks = (size_t)dp4a_N_pad * (K / 32); + if (ggml_cl_mul_mat_q3_K_dp4a(backend, src0, src1, dst)) { + return; + } - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)dp4a_N_pad * K * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_mem b_sub = nullptr; - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - cl_int tb = (cl_int)((size_t)N * (K / 32)); - cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub)); - CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)CEIL_DIV(tb, 64) * 64 }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_mem d_sub = nullptr; - cl_mem d_img = nullptr; - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - CL_CHECK((d_sub = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_q3_k_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->hm)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a_ila_a8_bin; +static void ggml_cl_mul_mat_iq3_s_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq3_s * extra0 = (ggml_tensor_extra_cl_iq3_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->qh)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_uint), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_int), &N)); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq3_s_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq3_s_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 12, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 13, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq3_s_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - size_t local_work_size_dp4a[3] = { 64, 1, 1 }; - size_t global_work_size_dp4a[3] = { 64, (size_t)(M / 64), (size_t)(dp4a_N_pad / 32) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size_dp4a, local_work_size_dp4a, dst); + if (ggml_cl_mul_mat_iq3_s_dp4a(backend, src0, src1, dst)) { + return; + } - CL_CHECK(clReleaseMemObject(b_sub)); - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub)); - return; - } + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - const int gemm_tile_n = 64; - int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n; + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - cl_mem b_sub_buf = nullptr; - cl_mem b_padded = nullptr; - cl_mem b_buf = nullptr; - if (N_pad == N) { - region.origin = offset1; - region.size = (size_t)K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - b_buf = b_sub_buf; - } else { - CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, (size_t)K * N_pad * sizeof(float), NULL, &err), err)); - const float zero = 0.0f; - CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL)); - CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL)); - b_buf = b_padded; - } + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)K * N_pad; - img_desc.buffer = b_buf; - cl_mem b_img; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - region.origin = offsetd; - region.size = (size_t)M * N * sizeof(float); - cl_mem d_sub_buf; - CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); - img_fmt = { CL_R, CL_FLOAT }; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = (size_t)M * N; - img_desc.buffer = d_sub_buf; - cl_mem d_img; - CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq3_s_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_f32_32b_trans_ila_a8_bin; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &d_img)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_uint), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_uint), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &N)); +static void ggml_cl_mul_mat_iq3_xxs_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq3_xxs * extra0 = (ggml_tensor_extra_cl_iq3_xxs *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - size_t local_work_size[3] = { 64, 2, 2 }; - size_t m_tiles = (size_t)CEIL_DIV(M, 64); - size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq3_xxs_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq3_xxs_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq3_xxs_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - CL_CHECK(clReleaseMemObject(b_img)); - if (b_sub_buf) { - CL_CHECK(clReleaseMemObject(b_sub_buf)); - } - if (b_padded) { - CL_CHECK(clReleaseMemObject(b_padded)); - } - CL_CHECK(clReleaseMemObject(d_img)); - CL_CHECK(clReleaseMemObject(d_sub_buf)); + if (ggml_cl_mul_mat_iq3_xxs_dp4a(backend, src0, src1, dst)) { + return; } -} -#endif // GGML_OPENCL_USE_ADRENO_KERNELS -static void ggml_cl_mul_mat_q5_K_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); + + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq3_xxs_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} +static void ggml_cl_mul_mat_iq1_m_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq1_m * extra0 = (ggml_tensor_extra_cl_iq1_m *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - ggml_tensor_extra_cl_q5_K * extra0_q5_k = (ggml_tensor_extra_cl_q5_K *)src0->extra; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq1_m_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq1_s_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq1_m_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - const int ne00 = src0->ne[0]; - const int ne01 = src0->ne[1]; - const int ne1 = dst->ne[1]; - - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); + if (ggml_cl_mul_mat_iq1_m_dp4a(backend, src0, src1, dst)) { + return; + } cl_context context = backend_ctx->context; - cl_kernel kernel; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_int err; - cl_image_format img_fmt; - cl_image_desc img_desc; - cl_buffer_region region; + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - int M = ne01; - int N = ne1; - int K = ne00; + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_uchar mask_d6 = 0x3F; - cl_uchar mask_d4 = 0x0F; - cl_uchar mask_hi2 = 0xC0; + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - // Multi-column (N=3) verify GEMV for q5_K: route the spec/MTP verify batch - // (ne1==3) onto the efficient GEMV path instead of the transposed-GEMM dead- - // zone (gemm_noshuffle_q5_k, the #2 chunk of MTP decode on a Q4_0-mix model - // after q4_0 mc3). Reuses the ne1==1 GEMV image setup (q + qh + activations). - // Opt-in via GGML_OPENCL_Q5K_MC3=1. Per-layer only (ne01 < 32768). - static const bool q5k_mc3 = (getenv("GGML_OPENCL_Q5K_MC3") != nullptr); - const bool use_q5k_mc3 = q5k_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq1_m_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - const bool use_bin = use_q5_k_bin_kernels(backend_ctx, src0); +static void ggml_cl_mul_mat_iq1_s_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq1_s * extra0 = (ggml_tensor_extra_cl_iq1_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - if (use_bin) { - if (use_q5k_mc3) { - static bool warned = false; - if (!warned) { - GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q5K_MC3 is bypassed by Q5_K binary kernels\n"); - warned = true; - } - } - ggml_cl_mul_mat_q5_K_f32_adreno_ila(backend, src0, src1, dst); + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq1_s_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq1_s_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq1_s_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); return; } - if (ne1 == 1 || use_q5k_mc3) { - cl_mem q_img = nullptr; - cl_mem qh_img = nullptr; - cl_mem b_sub_buf = nullptr; - cl_mem b_img = nullptr; + if (ggml_cl_mul_mat_iq1_s_dp4a(backend, src0, src1, dst)) { + return; + } - // image for q (CL_R, CL_UNSIGNED_INT32): width = M*K/2/4 - img_fmt = {CL_R, CL_UNSIGNED_INT32}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 2 / 4; - img_desc.buffer = extra0_q5_k->q; - CL_CHECK((q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // image for qh (CL_R, CL_HALF_FLOAT): width = M*K/16 - img_fmt = {CL_R, CL_HALF_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = M * K / 16; - img_desc.buffer = extra0_q5_k->qh; - CL_CHECK((qh_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // image for activations (CL_RGBA, CL_FLOAT): width = K*N/4 - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - kernel = use_q5k_mc3 ? backend_ctx->kernel_gemv_noshuffle_q5_k_f32_mc3 - : backend_ctx->kernel_gemv_noshuffle_q5_k_f32; + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq1_s_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &qh_img)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_hi2)); - if (use_q5k_mc3) { - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_int), &ne1)); // n_cols - } +static void ggml_cl_mul_mat_iq2_s_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_s * extra0 = (ggml_tensor_extra_cl_iq2_s *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - size_t local_work_size[3] = {64, 4, 1}; - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne01/2, 64)*64, 4, 1}; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq2_s_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq2_s_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 12, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 13, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq2_s_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + if (ggml_cl_mul_mat_iq2_s_dp4a(backend, src0, src1, dst)) { + return; + } - CL_CHECK(clReleaseMemObject(q_img)); - CL_CHECK(clReleaseMemObject(qh_img)); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_img)); - } else { - cl_mem b_sub_buf = nullptr; - cl_mem b_sub_buf_trans = nullptr; - cl_mem b_img = nullptr; - cl_mem b_img_trans = nullptr; + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // subbuffer for activations - region.origin = offset1; - region.size = K * N * sizeof(float); - CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - // image for activations - img_fmt = {CL_RGBA, CL_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * N / 4; - img_desc.buffer = b_sub_buf; - CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err)); + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // pad N to multiple of 8 - int extra_elements = N % 8; - int padding = 0; - if (extra_elements > 0) { - padding = 8 - extra_elements; - } + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - // subbuffer for transposed activations - region.origin = 0; - region.size = K * (N + padding) * sizeof(float) / 2; - backend_ctx->prealloc_act_trans.allocate(context, region.size); - CL_CHECK((b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err)); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq2_s_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} - // image for transposed activations - img_fmt = {CL_RGBA, CL_HALF_FLOAT}; - memset(&img_desc, 0, sizeof(img_desc)); - img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc.image_width = K * (N + padding) / 4; - img_desc.buffer = b_sub_buf_trans; - CL_CHECK((b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, NULL, &err), err)); +static void ggml_cl_mul_mat_iq2_xs_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_xs * extra0 = (ggml_tensor_extra_cl_iq2_xs *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - // transpose activations - int height_B = N / 4; - if (height_B == 0) height_B = 1; - int width_B = K / 4; - int padded_height_B = (N + padding) / 4; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq2_xs_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq2_xs_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq2_xs_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } - kernel = backend_ctx->kernel_transpose_32_16; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_B)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_B)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_B)); + if (ggml_cl_mul_mat_iq2_xs_dp4a(backend, src0, src1, dst)) { + return; + } - size_t local_work_size_t[2] = {1, 16}; - size_t global_work_size_t[2] = {(size_t)width_B, (size_t)padded_height_B}; - backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size_t, local_work_size_t, dst); + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // dp4a (int8) dense q5_K prefill GEMM - static const char * q5k_dense_dp4a_env = getenv("GGML_OPENCL_Q5K_DENSE_DP4A"); - bool q5k_dense_dp4a_on = q5k_dense_dp4a_env - ? (atoi(q5k_dense_dp4a_env) != 0) - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); - // dot prod has to be available - q5k_dense_dp4a_on = backend_ctx->has_integer_dot && q5k_dense_dp4a_on; + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - if (q5k_dense_dp4a_on && ne1 > 8 && (ne00 % 32 == 0) && (ne01 % 64 == 0)) { - const int Mm = ne01, Nn = ne1, Kk = ne00; - const size_t n_blocks = (size_t)Nn * (Kk / 32); - backend_ctx->prealloc_moe_qa.allocate(context, (size_t)Nn * Kk * sizeof(cl_char)); - backend_ctx->prealloc_moe_da.allocate(context, n_blocks * sizeof(cl_half)); - backend_ctx->prealloc_moe_sa.allocate(context, n_blocks * sizeof(cl_half)); + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_int tb = (cl_int)n_blocks; - cl_kernel qk = backend_ctx->kernel_quant_a_q8_1; - CL_CHECK(clSetKernelArg(qk, 0, sizeof(cl_mem), &b_sub_buf)); - CL_CHECK(clSetKernelArg(qk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(qk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(qk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(qk, 4, sizeof(cl_int), &tb)); - size_t q_local[1] = { 64 }; - size_t q_global[1] = { (size_t)(((n_blocks + 63) / 64) * 64) }; - backend_ctx->enqueue_ndrange_kernel(qk, 1, q_global, q_local, dst); + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); + + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq2_xs_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} + +static void ggml_cl_mul_mat_iq2_xxs_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl_iq2_xxs * extra0 = (ggml_tensor_extra_cl_iq2_xxs *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + const int m = src0->ne[1]; + const int n = src1->ne[1]; + const int k = src0->ne[0]; + + if (n == 1 || !ggml_is_contiguous(src1) || offset1 % backend_ctx->alignment != 0) { + cl_kernel gemv = backend_ctx->kernel_gemv_noshuffle_iq2_xxs_f32; + const int stride_d = dst->ne[0]; + const int stride_b = src1->nb[1]/sizeof(float); + CL_CHECK(clSetKernelArg(gemv, 0, sizeof(cl_mem), &backend_ctx->iq2_xxs_grid_image)); + CL_CHECK(clSetKernelArg(gemv, 1, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(gemv, 2, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(gemv, 3, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(gemv, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(gemv, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(gemv, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(gemv, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(gemv, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(gemv, 9, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(gemv, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(gemv, 11, sizeof(int), &stride_d)); + const size_t nsg = backend_ctx->iq2_xxs_mv_nsg; + size_t global[] = { (size_t)CEIL_DIV(m, 128)*64, (size_t)n*nsg, 1 }; + size_t local[] = { 64, nsg, 1 }; + backend_ctx->enqueue_ndrange_kernel(gemv, 3, global, local, dst); + return; + } + + if (ggml_cl_mul_mat_iq2_xxs_dp4a(backend, src0, src1, dst)) { + return; + } + + cl_context context = backend_ctx->context; + cl_int err; + cl_buffer_region region = { (size_t)offset1, (size_t)k*n*sizeof(float) }; + cl_mem b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - cl_kernel dk = backend_ctx->kernel_gemm_noshuffle_q5_k_q8_1_dp4a; - int ai = 0; - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->q)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->qh)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &backend_ctx->prealloc_moe_sa.buffer)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Mm)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Nn)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_int), &Kk)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(dk, ai++, sizeof(cl_uchar), &mask_hi2)); - size_t d_local[3] = { 64, 1, 1 }; - size_t d_global[3] = { 64, (size_t)(Mm / 64), (size_t)CEIL_DIV(Nn, 32) }; - backend_ctx->enqueue_ndrange_kernel(dk, 3, d_global, d_local, dst); + cl_image_format img_fmt = { CL_RGBA, CL_FLOAT }; + cl_image_desc img_desc = {}; + img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; + img_desc.image_width = (size_t)k*n/4; + img_desc.buffer = b_sub_buf; + cl_mem b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); - return; - } + const int padded_n = CEIL_DIV(n, 8)*8; + region.origin = 0; + region.size = (size_t)k*padded_n*sizeof(cl_half); + backend_ctx->prealloc_act_trans.allocate(context, region.size); + cl_mem b_sub_buf_trans = clCreateSubBuffer(backend_ctx->prealloc_act_trans.buffer, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); - // gemm - kernel = backend_ctx->kernel_gemm_noshuffle_q5_k_f32; - int padded_N = N + padding; + img_fmt = { CL_RGBA, CL_HALF_FLOAT }; + img_desc.image_width = (size_t)k*padded_n/4; + img_desc.buffer = b_sub_buf_trans; + cl_mem b_img_trans = clCreateImage(context, 0, &img_fmt, &img_desc, nullptr, &err); + CL_CHECK(err); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_k->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_k->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_k->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_k->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_k->dm)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &b_img_trans)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_int), &padded_N)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_uchar), &mask_d6)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_uchar), &mask_d4)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_uchar), &mask_hi2)); + const int height_b = std::max(n/4, 1); + const int width_b = k/4; + const int padded_height_b = padded_n/4; + cl_kernel kernel = backend_ctx->kernel_transpose_32_16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &b_img)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_b)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &width_b)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &padded_height_b)); + size_t t_global[] = { (size_t)width_b, (size_t)padded_height_b }; + size_t t_local[] = { 1, 16 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, t_global, t_local, dst); + + kernel = backend_ctx->kernel_gemm_noshuffle_iq2_xxs_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &b_img_trans)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &m)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &padded_n)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n)); + size_t global[] = { (size_t)CEIL_DIV(n, 8), (size_t)CEIL_DIV(m, 512)*128, 1 }; + size_t local[] = { 1, 128, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global, local, dst); + + CL_CHECK(clReleaseMemObject(b_img_trans)); + CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); + CL_CHECK(clReleaseMemObject(b_img)); + CL_CHECK(clReleaseMemObject(b_sub_buf)); +} +#endif - size_t global_work_size[3] = {(size_t)CEIL_DIV(ne1, 8), (size_t)CEIL_DIV(ne01, 4), 1}; - size_t local_work_size[3] = {1, 128, 1}; +static void ggml_cl_fwht(ggml_backend_t backend, const ggml_tensor * src, ggml_tensor * dst) { + auto * backend_ctx = (ggml_backend_opencl_context *) backend->context; + + auto * extra_src = (ggml_tensor_extra_cl *) src->extra; + auto * extra_dst = (ggml_tensor_extra_cl *) dst->extra; + + const cl_ulong offset_src = extra_src->offset + src->view_offs; + const cl_ulong offset_dst = extra_dst->offset + dst->view_offs; + + const cl_ulong ne1 = src->ne[1]; + const cl_ulong ne2 = src->ne[2]; + const cl_ulong nb1 = src->nb[1]; + const cl_ulong nb2 = src->nb[2]; + const cl_ulong nb3 = src->nb[3]; + + const int n = src->ne[0]; + const float scale = 1.0f/sqrtf((float)n); + const int type_index = src->type == GGML_TYPE_F16 ? 1 : 0; + + cl_kernel kernel = backend_ctx->kernel_fwht[type_index]; + const size_t nth = std::min((size_t)n/2, backend_ctx->fwht_workgroup_size[type_index]); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_src->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_src)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_dst->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_dst)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &n)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 11, n*sizeof(float), nullptr)); + + size_t global[] = { nth, (size_t)ggml_nrows(src) }; + size_t local[] = { nth, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global, local, dst); +} - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); - CL_CHECK(clReleaseMemObject(b_sub_buf)); - CL_CHECK(clReleaseMemObject(b_sub_buf_trans)); - CL_CHECK(clReleaseMemObject(b_img)); - CL_CHECK(clReleaseMemObject(b_img_trans)); + // bf16 is stored as f16 on device + const enum ggml_type src0t = (src0->type == GGML_TYPE_BF16) ? GGML_TYPE_F16 : src0->type; + const enum ggml_type src1t = src1->type; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + if (ggml_cl_mul_mat_can_use_fwht(backend_ctx, dst)) { + ggml_cl_fwht(backend, src1, dst); + return; } -#else - GGML_UNUSED(backend); - GGML_UNUSED(src0); - GGML_UNUSED(src1); - GGML_UNUSED(dst); + + // quant kv without FA + // used for non-contiguous src0 (the usual head-major permuted K view when n_head_kv>1) + // AND for the contiguous case that occurs when n_head_kv==1 (e.g. Gemma-4 E2B) + // Q4_0 bin kernels use a special weight layout, which the restore below does not support. + bool q4_0_bin_layout = false; +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + q4_0_bin_layout = src0t == GGML_TYPE_Q4_0 && src0->view_src == nullptr && + ggml_is_contiguous(src0) && + src0->ne[2] == 1 && src0->ne[3] == 1 && + use_adreno_kernels(backend_ctx, src0) && + !use_adreno_moe_kernels(backend_ctx, src0) && + use_q4_0_bin_kernels(backend_ctx, src0); #endif -} + if ((src0t == GGML_TYPE_Q4_0 || src0t == GGML_TYPE_Q8_0) && !q4_0_bin_layout && + (!ggml_is_contiguous(src0) || src1->ne[2] > src0->ne[2])) { + cl_mem f16_buf = ggml_cl_mul_mat_dequant_quant_to_f16(backend_ctx, src0, nullptr); -// Dequant a possibly-strided q4_0/q8_0 tensor to tight-packed f16. Returns a -// temp cl_mem the caller must release. SoA inputs are reconstructed into a -// temp AoS buffer reported via *extra_reconstruct (also caller-released). -// this is for quantized K cache without FA. -static cl_mem ggml_cl_mul_mat_dequant_quant_to_f16( - ggml_backend_opencl_context * backend_ctx, - const ggml_tensor * tensor, - cl_mem * extra_reconstruct /* out, may be NULL */ -) { - GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0 || tensor->type == GGML_TYPE_Q8_0); + ggml_tensor fake_src0 = *src0; + ggml_tensor_extra_cl fake_extra = {}; + fake_extra.data_device = f16_buf; + fake_extra.offset = 0; + fake_src0.type = GGML_TYPE_F16; + fake_src0.extra = &fake_extra; + fake_src0.view_src = nullptr; + fake_src0.view_offs = 0; + fake_src0.nb[0] = sizeof(ggml_fp16_t); + fake_src0.nb[1] = fake_src0.nb[0] * src0->ne[0]; + fake_src0.nb[2] = fake_src0.nb[1] * src0->ne[1]; + fake_src0.nb[3] = fake_src0.nb[2] * src0->ne[2]; - if (extra_reconstruct) { - *extra_reconstruct = NULL; + ggml_cl_mul_mat(backend, &fake_src0, src1, dst); + return; } - cl_mem src_buf; - cl_ulong src_offset; - cl_ulong src_nb1; - cl_ulong src_nb2; - cl_ulong src_nb3; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; - uintptr_t pool_key_buf = 0; - cl_ulong pool_key_off = (cl_ulong) tensor->view_offs; + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; - const bool is_soa = tensor->type == GGML_TYPE_Q4_0 - ? ggml_cl_is_q4_0_soa(tensor) - : ggml_cl_is_q8_0_soa(tensor); +#ifdef GGML_OPENCL_SOA_Q + // view->extra stays pre-SoA; cast to the SoA struct would SIGSEGV. + // Follow view_src to reach the real SoA extra. + const ggml_tensor * soa0_src = src0->view_src != nullptr ? src0->view_src : src0; + ggml_tensor_extra_cl_q1_0 * extra0_q1_0 = (ggml_tensor_extra_cl_q1_0 *)src0->extra; + ggml_tensor_extra_cl_q2_0 * extra0_q2_0 = (ggml_tensor_extra_cl_q2_0 *)soa0_src->extra; + ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)soa0_src->extra; + ggml_tensor_extra_cl_q4_1 * extra0_q4_1 = (ggml_tensor_extra_cl_q4_1 *)soa0_src->extra; + ggml_tensor_extra_cl_q5_0 * extra0_q5_0 = (ggml_tensor_extra_cl_q5_0 *)soa0_src->extra; + ggml_tensor_extra_cl_q5_1 * extra0_q5_1 = (ggml_tensor_extra_cl_q5_1 *)soa0_src->extra; + ggml_tensor_extra_cl_mxfp4 * extra0_mxfp4 = (ggml_tensor_extra_cl_mxfp4 *)soa0_src->extra; + ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)soa0_src->extra; + ggml_tensor_extra_cl_iq4_nl * extra0_iq4_nl = (ggml_tensor_extra_cl_iq4_nl *)soa0_src->extra; + ggml_tensor_extra_cl_q2_K * extra0_q2_K = (ggml_tensor_extra_cl_q2_K *)soa0_src->extra; + ggml_tensor_extra_cl_q3_K * extra0_q3_K = (ggml_tensor_extra_cl_q3_K *)soa0_src->extra; + ggml_tensor_extra_cl_iq2_s * extra0_iq2_s = (ggml_tensor_extra_cl_iq2_s *)soa0_src->extra; + ggml_tensor_extra_cl_iq2_xs * extra0_iq2_xs = (ggml_tensor_extra_cl_iq2_xs *)soa0_src->extra; + ggml_tensor_extra_cl_iq2_xxs * extra0_iq2_xxs = (ggml_tensor_extra_cl_iq2_xxs *)soa0_src->extra; + ggml_tensor_extra_cl_iq1_m * extra0_iq1_m = (ggml_tensor_extra_cl_iq1_m *)soa0_src->extra; + ggml_tensor_extra_cl_iq1_s * extra0_iq1_s = (ggml_tensor_extra_cl_iq1_s *)soa0_src->extra; + ggml_tensor_extra_cl_iq3_s * extra0_iq3_s = (ggml_tensor_extra_cl_iq3_s *)soa0_src->extra; + ggml_tensor_extra_cl_iq3_xxs * extra0_iq3_xxs = (ggml_tensor_extra_cl_iq3_xxs *)soa0_src->extra; + ggml_tensor_extra_cl_q4_K * extra0_q4_K = (ggml_tensor_extra_cl_q4_K *)soa0_src->extra; + ggml_tensor_extra_cl_q5_K * extra0_q5_K = (ggml_tensor_extra_cl_q5_K *)soa0_src->extra; + ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)soa0_src->extra; +#endif - cl_mem aos = nullptr; - if (is_soa) { - // Reconstruct full parent AoS; view's own nb[] then index it correctly. - const ggml_tensor * parent = tensor->view_src ? tensor->view_src : tensor; - const ggml_tensor * soa_src = parent; - const size_t block_bytes = (size_t) ggml_type_size(tensor->type); - const size_t blck_size = (size_t) ggml_blck_size(tensor->type); - const size_t parent_row_blocks = (size_t) parent->ne[0] / blck_size; - const size_t parent_row_bytes = parent_row_blocks * block_bytes; - const size_t parent_nbytes = (size_t) ggml_nelements(parent) / blck_size * block_bytes; + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + GGML_TENSOR_LOCALS(int, ne1, src1, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); + GGML_TENSOR_LOCALS(int, ne, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); - cl_int err; - aos = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, parent_nbytes, NULL, &err); - CL_CHECK(err); + int r2 = ne12/ne02; + int r3 = ne13/ne03; + + GGML_ASSERT(ne00 == ne10); + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + // adreno GEMM/GEMV kernels do not support broadcast, assuming ne2 and ne3 are 1 for src1 + // so we handle broadcast here + if ((ne12 > 1 || ne13 > 1) && ne02 == 1 && ne03 == 1 && + src0t != GGML_TYPE_F16 && src0t != GGML_TYPE_F32) { + for (int i13 = 0; i13 < ne13; ++i13) { + for (int i12 = 0; i12 < ne12; ++i12) { + ggml_tensor s1 = *src1; + s1.ne[2] = 1; s1.ne[3] = 1; + s1.view_offs = src1->view_offs + (size_t)i12*nb12 + (size_t)i13*nb13; + ggml_tensor d = *dst; + d.ne[2] = 1; d.ne[3] = 1; + d.view_offs = dst->view_offs + (size_t)i12*nb2 + (size_t)i13*nb3; + d.src[1] = &s1; + ggml_cl_mul_mat(backend, src0, &s1, &d); + } + } + return; + } +#endif + + int nth0 = 32; + int nth1 = 1; + int nrows = 1; + // The number of values produced by each subgroup + int ndst = 4; + + cl_kernel kernel; + +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if(src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32){ + // Two tiling assumptions these kernels make but nothing enforced: + // + // ne00 % TILESIZE_K(16): the K loop has no tail, so a K that does not + // divide folds 1-15 rows of whatever follows the operands into every + // output. + // + // ne01 % TILESIZE_M(64): mm_store_c_N guards the n direction with its + // `mask` argument but nothing guards m -- the store walks all 64 rows + // of the tile at a stride of M. When M does not divide, the last tile + // does not run off the end of the buffer, it writes 64 - (M % 64) + // values ON TOP OF the next column, so the result is silently wrong. + // Reachable on the KQV side for any head size >= 64 that is not a + // multiple of it (80, 96, 112). + // + // Attention shapes in the graph satisfy both -- head sizes are multiples + // of 64 and n_kv is padded -- which is why this has stayed latent. + // Declining leaves the odd shapes on the generic GEMM, which handles them. + if (ne01 >= 64 && ne1 >= 32 && ne00 >= 16 && + (ne00 % 16) == 0 && (ne01 % 64) == 0 && (ne12 % ne02) == 0 && + // the KQ/KQV image kernels do not handle dim 3 (multi-stream batches) + ne03 == 1 && ne13 == 1 && + // dst is wrapped with image1d_buffer, the size limit applies, also src0 + (ne0 * ne1 * dst->ne[2] * dst->nb[0] / 4 <= backend_ctx->image_max_buffer_size)) { + // For KQ. + // + // Layout admission, mirroring the KQV arm below. The KQ kernel takes + // no stride arguments for A or B: it derives them as K*D_A*2 and + // K*D_B*4, i.e. it assumes both operands pack exactly D heads of K + // elements per row. Every real KV-cache view and permuted-Q view + // does, but a view spanning part of a wider allocation does not, and + // the kernel then walks the wrong rows with nothing to range-check + // it. Gate on the packed layout itself rather than on the stride + // ORDERING, which a wider parent satisfies just as well. + const bool kq_packed_a = (nb01 == (cl_ulong)ne00 * ne02 * ggml_type_size(src0t)) && + (nb02 == (cl_ulong)ne00 * ggml_type_size(src0t)); + const bool kq_packed_b = (nb11 == (cl_ulong)ne10 * ne12 * ggml_type_size(src1t)) && + (nb12 == (cl_ulong)ne10 * ggml_type_size(src1t)); + // + // ggml_is_permuted(src0) stands in for "K is head-major", but it is + // only a proxy and it COLLAPSES at n_head_kv == 1: with a single + // head there is no head stride to be out of order, so nb01 == nb02 + // and the view reports itself unpermuted. Such a KQ was declined + // here and fell through to the generic GEMM (gemma-4 E2B, and any + // other multi-query model). The packed check above is the contract + // the kernel actually needs -- it pins both strides exactly -- so + // require permutedness only where there is more than one head for + // it to mean anything. + // + // Default on; GGML_OPENCL_KQ_NHEAD_KV1=0 restores the old proxy so + // the two routings can be compared in one binary. + static const char * kq_nhkv1_env = getenv("GGML_OPENCL_KQ_NHEAD_KV1"); + static const bool kq_nhkv1_on = + (kq_nhkv1_env == nullptr || kq_nhkv1_env[0] != '0'); + if ((ggml_is_permuted(src0) || (ne02 == 1 && kq_nhkv1_on)) && ggml_is_permuted(src1) && + kq_packed_a && kq_packed_b && + ((nb01 * ne01 / 4)/4 <= backend_ctx->image_max_buffer_size) && + nb00 <= nb02 && + nb02 <= nb01 && + nb01 <= nb03 && + nb10 <= nb12 && + nb12 <= nb11 && + nb11 <= nb13) { + ggml_cl_mul_mat_kq_kqv_adreno(backend, src0, src1, dst, /*is_kq =*/ true); + return; + } + // For KQV. Reaching this arm is what makes the op a KQV; the callee + // is told so explicitly rather than re-deriving it from the strides + // the arm above has already ruled on. + if (!ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && + ((nb02 * ne02 / 4)/4 <= backend_ctx->image_max_buffer_size)) { + ggml_cl_mul_mat_kq_kqv_adreno(backend, src0, src1, dst, /*is_kq =*/ false); + return; + } + } - // large q4_0/q8_0 WEIGHTS are stored transposed and small weights - // (and the AoS KV-cache, handled in the else branch above) are not. - // choose a proper restore kernel based on this. - bool restored = false; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - const int p_ne00 = (int) parent->ne[0]; - const int p_ne01 = (int) parent->ne[1]; - if (tensor->type == GGML_TYPE_Q8_0 && enable_adreno_trans_weight(backend_ctx, parent)) { - auto * extra = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; - pool_key_buf = (uintptr_t) extra->q; - cl_kernel kernel = backend_ctx->kernel_restore_block_q8_0_trans; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_int), &p_ne00)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_int), &p_ne01)); - size_t gws[] = { (size_t)(((p_ne01 + 63) / 64) * 64), 1, 1 }; - size_t lws[] = { 64, 1, 1 }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws, lws, 0, NULL, NULL)); - restored = true; - } else if (tensor->type == GGML_TYPE_Q4_0 && - use_adreno_kernels(backend_ctx, parent) && - !use_adreno_moe_kernels(backend_ctx, parent)) { - auto * extra = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; - pool_key_buf = (uintptr_t) extra->q; - const size_t size_q = (size_t) ggml_nelements(parent) / blck_size * (blck_size / 2); - const size_t size_d = (size_t) ggml_nelements(parent) / blck_size * sizeof(ggml_fp16_t); - cl_int err2 = CL_SUCCESS; - cl_mem buf_tq = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, size_q, NULL, &err2); CL_CHECK(err2); - cl_mem buf_td = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, size_d, NULL, &err2); CL_CHECK(err2); - transpose_2d_as_16b(backend_ctx, extra->q, buf_tq, size_q, p_ne01, p_ne00 / 4); - transpose_2d_as_16b(backend_ctx, extra->d, buf_td, size_d, p_ne01, p_ne00 / 32); - cl_uchar mask_0F = 0x0F, mask_F0 = 0xF0; - cl_kernel kernel = backend_ctx->kernel_restore_block_q4_0_noshuffle; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &buf_tq)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &buf_td)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_uchar), &mask_0F)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_uchar), &mask_F0)); - const size_t n_blk = parent_nbytes / block_bytes; - size_t gws[] = { n_blk, 1, 1 }; - size_t lws[] = { 1, 1, 1 }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws, lws, 0, NULL, NULL)); + static const char * mm_kq_gqa_img_env = getenv("GGML_OPENCL_MM_KQ_GQA_IMG"); + static const bool mm_kq_gqa_img_on = (mm_kq_gqa_img_env == nullptr || mm_kq_gqa_img_env[0] != '0'); + static const char * mm_kq_gqa_r4_img_env = getenv("GGML_OPENCL_MM_KQ_GQA_R4_IMG"); + static const bool mm_kq_gqa_r4_img_on = (mm_kq_gqa_r4_img_env == nullptr || mm_kq_gqa_r4_img_env[0] != '0'); + const bool img_r4_gate = + mm_kq_gqa_r4_img_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img != nullptr && + ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 128 && + (ne12 % ne02) == 0 && (ne12 / ne02) == 4 && (ne13 / ne03) == 1; + if (mm_kq_gqa_img_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img != nullptr && + ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 128 && + (ne12 % ne02) == 0 && (ne12 / ne02) == 8 && (ne13 / ne03) == 1) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t k_bytes_span = + (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + + (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + + (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + + (size_t)ne00 * nb00_bytes; - CL_CHECK(clReleaseMemObject(buf_tq)); - CL_CHECK(clReleaseMemObject(buf_td)); - restored = true; - } -#endif // GGML_OPENCL_USE_ADRENO_KERNELS + const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; + const size_t k_pixels = k_bytes >> 4; + if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { + cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img; + cl_mem K_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kq_img_pool, + extra0->data_device, offset0, k_bytes, CL_FLOAT); + if (K_img != nullptr) { + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); - if (!restored) { - cl_kernel kernel; - if (tensor->type == GGML_TYPE_Q8_0) { - auto * extra = (ggml_tensor_extra_cl_q8_0 *) soa_src->extra; - kernel = backend_ctx->kernel_restore_block_q8_0; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); - pool_key_buf = (uintptr_t) extra->q; - } else { - auto * extra = (ggml_tensor_extra_cl_q4_0 *) soa_src->extra; - kernel = backend_ctx->kernel_restore_block_q4_0; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &aos)); - pool_key_buf = (uintptr_t) extra->q; + const int nth0_d = 64; + const int64_t n_wg_x = ne01 / 16; + size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; + size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } } - - const size_t n_blocks = parent_nbytes / block_bytes; - size_t gws_rec[] = { n_blocks, 1, 1 }; - size_t lws_rec[] = { 1, 1, 1 }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, kernel, 3, NULL, gws_rec, lws_rec, 0, NULL, NULL)); } - (void) parent_row_blocks; - (void) parent_row_bytes; - src_buf = aos; - src_offset = tensor->view_offs; - src_nb1 = tensor->nb[1]; - src_nb2 = tensor->nb[2]; - src_nb3 = tensor->nb[3]; + // r2=4 specialization + if (img_r4_gate) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t k_bytes_span = + (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + + (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + + (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + + (size_t)ne00 * nb00_bytes; + const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; + const size_t k_pixels = k_bytes >> 4; + if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { + cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img; + cl_mem K_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kq_img_pool, + extra0->data_device, offset0, k_bytes, CL_FLOAT); + if (K_img != nullptr) { + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); - if (extra_reconstruct) { - *extra_reconstruct = aos; + const int nth0_d = 64; + const int64_t n_wg_x = ne01 / 16; + size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; + size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + } } - } else { - auto * extra = (ggml_tensor_extra_cl *) tensor->extra; - GGML_ASSERT(extra && extra->data_device); - src_buf = extra->data_device; - src_offset = extra->offset + tensor->view_offs; - src_nb1 = tensor->nb[1]; - src_nb2 = tensor->nb[2]; - src_nb3 = tensor->nb[3]; - pool_key_buf = (uintptr_t) extra->data_device; - pool_key_off = (cl_ulong) src_offset; - } - - const cl_int nblk0 = (cl_int) (tensor->ne[0] / ggml_blck_size(tensor->type)); - const cl_int ne1_ = (cl_int) tensor->ne[1]; - const cl_int ne2_ = (cl_int) tensor->ne[2]; - const cl_int ne3_ = (cl_int) tensor->ne[3]; - const size_t out_bytes = (size_t) ggml_nelements(tensor) * sizeof(ggml_fp16_t); + // DK=256, r2=2 specialization + static const char * mm_kq_r2_dk256_env = getenv("GGML_OPENCL_MM_KQ_GQA_R2_DK256_IMG"); + static const bool mm_kq_r2_dk256_on = (mm_kq_r2_dk256_env != nullptr && mm_kq_r2_dk256_env[0] != '0'); + if (mm_kq_r2_dk256_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img != nullptr && + ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 256 && + (ne12 % ne02) == 0 && (ne12 / ne02) == 2 && (ne13 / ne03) == 1) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t k_bytes_span = + (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + + (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + + (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + + (size_t)ne00 * nb00_bytes; + const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; + const size_t k_pixels = k_bytes >> 4; + if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { + cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img; + cl_mem K_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kq_img_pool, + extra0->data_device, offset0, k_bytes, CL_FLOAT); + if (K_img != nullptr) { + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); - // reuse a pooled f16 buffer for this KV-cache view across decode steps instead of - // allocating new one per attention op - cl_mem out = nullptr; - { - auto & pool = backend_ctx->dequant_f16_pool; - ggml_backend_opencl_context::ImagePoolKey key{pool_key_buf, (uint64_t) pool_key_off}; - auto it = pool.find(key); - if (it != pool.end() && it->second.k_bytes >= out_bytes && it->second.image) { - out = it->second.image; - } else { - if (it != pool.end()) { - if (it->second.image) { CL_CHECK(clReleaseMemObject(it->second.image)); } - pool.erase(it); + const int nth0_d = 64; + const int64_t n_wg_x = ne01 / 16; + size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; + size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } } - cl_int err = CL_SUCCESS; - out = clCreateBuffer(backend_ctx->context, CL_MEM_READ_WRITE, out_bytes, NULL, &err); - CL_CHECK(err); - ggml_backend_opencl_context::ImagePoolEntry entry; - entry.image = out; - entry.k_bytes = out_bytes; - pool[key] = entry; } - } - - cl_kernel dq_kernel = tensor->type == GGML_TYPE_Q8_0 - ? backend_ctx->kernel_dequant_q8_0_f16_view_aos - : backend_ctx->kernel_dequant_q4_0_f16_view_aos; - - CL_CHECK(clSetKernelArg(dq_kernel, 0, sizeof(cl_mem), &src_buf)); - CL_CHECK(clSetKernelArg(dq_kernel, 1, sizeof(cl_ulong), &src_offset)); - CL_CHECK(clSetKernelArg(dq_kernel, 2, sizeof(cl_ulong), &src_nb1)); - CL_CHECK(clSetKernelArg(dq_kernel, 3, sizeof(cl_ulong), &src_nb2)); - CL_CHECK(clSetKernelArg(dq_kernel, 4, sizeof(cl_ulong), &src_nb3)); - CL_CHECK(clSetKernelArg(dq_kernel, 5, sizeof(cl_int), &nblk0)); - CL_CHECK(clSetKernelArg(dq_kernel, 6, sizeof(cl_int), &ne1_)); - CL_CHECK(clSetKernelArg(dq_kernel, 7, sizeof(cl_int), &ne2_)); - CL_CHECK(clSetKernelArg(dq_kernel, 8, sizeof(cl_int), &ne3_)); - CL_CHECK(clSetKernelArg(dq_kernel, 9, sizeof(cl_mem), &out)); - size_t gws[3] = { (size_t) nblk0, (size_t) ne1_, (size_t) (ne2_ * ne3_) }; - size_t lws[3] = { 1, 1, 1 }; - CL_CHECK(clEnqueueNDRangeKernel(backend_ctx->queue, dq_kernel, 3, NULL, gws, lws, 0, NULL, NULL)); + // GQA-coalesced KQV for decode using image1d_buffer_t + static const char * mm_kqv_gqa_img_env = getenv("GGML_OPENCL_MM_KQV_GQA_IMG"); + static const bool mm_kqv_gqa_img_on = (mm_kqv_gqa_img_env != nullptr && mm_kqv_gqa_img_env[0] != '0'); + if (mm_kqv_gqa_img_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img != nullptr && + ne11 == 1 && ne01 == 128 && + (ne12 % ne02) == 0 && (ne12 / ne02) == 8 && (ne13 / ne03) == 1) { + const size_t nb00_bytes = sizeof(uint16_t); + const size_t v_bytes_span = + (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + + (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + + (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + + (size_t)ne00 * nb00_bytes; + const size_t v_bytes = (v_bytes_span + 7) & ~(size_t)7; + const size_t v_pixels = v_bytes >> 3; + if (v_pixels > 0 && v_pixels <= backend_ctx->image_max_buffer_size) { + cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img; + cl_mem V_img = ggml_cl_img_pool_get_or_create( + backend_ctx, backend_ctx->kqv_img_pool, + extra0->data_device, offset0, v_bytes, CL_HALF_FLOAT); + if (V_img != nullptr) { + cl_uint k_arg = 0; + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &V_img)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); - // release the reconstructed aos if - // 1. it was actually reconstructed - // 2. the caller didn't request it to be returned - // src_buf may refer to aos, so we should release after this enqueue - if (aos && !extra_reconstruct) { - CL_CHECK(clReleaseMemObject(aos)); + const int nth0_d = 64; + const int64_t n_wg_x = ne01 / 8; + size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; + size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + } + } } - return out; -} -// look up or create a pooled image1d_buffer over a KV-cache view. -static cl_mem ggml_cl_img_pool_get_or_create( - ggml_backend_opencl_context * backend_ctx, - std::map & pool, - cl_mem data_device, - cl_ulong offset0, - size_t required_bytes, - cl_channel_type channel_data_type -) { - ggml_backend_opencl_context::ImagePoolKey key{(uintptr_t)data_device, (uint64_t)offset0}; - auto it = pool.find(key); - if (it != pool.end() - && it->second.k_bytes >= required_bytes - && it->second.channel_data_type == channel_data_type - && it->second.image != nullptr) { - return it->second.image; - } + if (ne01 && ne1 && use_adreno_kernels(backend_ctx, src0)) { + // NOTE: Kernels using image1d_buffer_t (e.g., src0_q) would normally require + // a limit check, but q4_0 / q4_1 tensors are very unlikely to exceed that + // limit, so the check is omitted. - // need to create or recreate and release any stale entry first. - if (it != pool.end()) { - if (it->second.image) { CL_CHECK(clReleaseMemObject(it->second.image)); } - if (it->second.sub_buffer) {CL_CHECK(clReleaseMemObject(it->second.sub_buffer)); } - pool.erase(it); - } + // q1_0 x fp32 + if (src0t == GGML_TYPE_Q1_0 && src1t == GGML_TYPE_F32 && + enable_adreno_trans_weight(backend_ctx, src0)) { + ggml_cl_mul_mat_q1_0_f32_adreno(backend, src0, src1, dst); + return; + } - cl_int status = CL_SUCCESS; - cl_buffer_region region = {}; - region.origin = (size_t)offset0; - region.size = required_bytes; - cl_mem sub = clCreateSubBuffer(data_device, 0, - CL_BUFFER_CREATE_TYPE_REGION, ®ion, &status); - if (status != CL_SUCCESS) { - return nullptr; - } + // q2_0 x fp32 + if (src0t == GGML_TYPE_Q2_0 && src1t == GGML_TYPE_F32 && extra0_q2_0->noshuffle) { + ggml_cl_mul_mat_q2_0_f32_adreno(backend, src0, src1, dst); + return; + } - const size_t pixel_size = (channel_data_type == CL_HALF_FLOAT) ? 8 : 16; - cl_image_format fmt = {CL_RGBA, channel_data_type}; - cl_image_desc desc = {}; - desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - desc.image_width = required_bytes / pixel_size; - desc.buffer = sub; - cl_mem img = clCreateImage(backend_ctx->context, CL_MEM_READ_ONLY, - &fmt, &desc, NULL, &status); - if (status != CL_SUCCESS) { - CL_CHECK(clReleaseMemObject(sub)); - return nullptr; - } + // q4_0 x fp32 + if(src0t == GGML_TYPE_Q4_0 && src1t == GGML_TYPE_F32) { + ggml_cl_mul_mat_q4_0_f32_adreno(backend, src0, src1, dst); + return; + } - ggml_backend_opencl_context::ImagePoolEntry entry; - entry.sub_buffer = sub; - entry.image = img; - entry.k_bytes = required_bytes; - entry.channel_data_type = channel_data_type; - pool[key] = entry; - return img; -} + // q4_1 x fp32 + if (src0t == GGML_TYPE_Q4_1 && src1t == GGML_TYPE_F32) { + ggml_cl_mul_mat_q4_1_f32_adreno(backend, src0, src1, dst); + return; + } -static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { - GGML_ASSERT(src0); - GGML_ASSERT(src0->extra); - GGML_ASSERT(src1); - GGML_ASSERT(src1->extra); - GGML_ASSERT(dst); - GGML_ASSERT(dst->extra); + // q5_0 x fp32 + if (src0t == GGML_TYPE_Q5_0 && src1t == GGML_TYPE_F32) { + ggml_cl_mul_mat_q5_0_f32_adreno(backend, src0, src1, dst); + return; + } - // bf16 is stored as f16 on device - const enum ggml_type src0t = (src0->type == GGML_TYPE_BF16) ? GGML_TYPE_F16 : src0->type; - const enum ggml_type src1t = src1->type; + // q5_1 x fp32 + if (src0t == GGML_TYPE_Q5_1 && src1t == GGML_TYPE_F32) { + ggml_cl_mul_mat_q5_1_f32_adreno(backend, src0, src1, dst); + return; + } - ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + // iq4_nl x fp32 + if (src0t == GGML_TYPE_IQ4_NL && src1t == GGML_TYPE_F32) { + ggml_cl_mul_mat_iq4_nl_f32_adreno(backend, src0, src1, dst); + return; + } - // quant kv without FA - // used for non-contiguous src0 (the usual head-major permuted K view when n_head_kv>1) - // AND for the contiguous case that occurs when n_head_kv==1 (e.g. Gemma-4 E2B) - // Q4_0 bin kernels use a special weight layout, which the restore below does not support. - bool q4_0_bin_layout = false; -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - q4_0_bin_layout = src0t == GGML_TYPE_Q4_0 && src0->view_src == nullptr && - ggml_is_contiguous(src0) && - src0->ne[2] == 1 && src0->ne[3] == 1 && - use_adreno_kernels(backend_ctx, src0) && - !use_adreno_moe_kernels(backend_ctx, src0) && - use_q4_0_bin_kernels(backend_ctx, src0); -#endif - if ((src0t == GGML_TYPE_Q4_0 || src0t == GGML_TYPE_Q8_0) && !q4_0_bin_layout && - (!ggml_is_contiguous(src0) || src1->ne[2] > src0->ne[2])) { - cl_mem f16_buf = ggml_cl_mul_mat_dequant_quant_to_f16(backend_ctx, src0, nullptr); + // q8_0 x fp32 + if (src0t == GGML_TYPE_Q8_0 && src1t == GGML_TYPE_F32 && + enable_adreno_trans_weight(backend_ctx, src0)) { + ggml_cl_mul_mat_q8_0_f32_adreno(backend, src0, src1, dst); + return; + } - ggml_tensor fake_src0 = *src0; - ggml_tensor_extra_cl fake_extra = {}; - fake_extra.data_device = f16_buf; - fake_extra.offset = 0; - fake_src0.type = GGML_TYPE_F16; - fake_src0.extra = &fake_extra; - fake_src0.view_src = nullptr; - fake_src0.view_offs = 0; - fake_src0.nb[0] = sizeof(ggml_fp16_t); - fake_src0.nb[1] = fake_src0.nb[0] * src0->ne[0]; - fake_src0.nb[2] = fake_src0.nb[1] * src0->ne[1]; - fake_src0.nb[3] = fake_src0.nb[2] * src0->ne[2]; + // q2_k x fp32 + if (src0t == GGML_TYPE_Q2_K && src1t == GGML_TYPE_F32 && extra0_q2_K->noshuffle) { + ggml_cl_mul_mat_q2_k_f32_adreno(backend, src0, src1, dst); + return; + } - ggml_cl_mul_mat(backend, &fake_src0, src1, dst); - return; - } + // q3_k x fp32 + if (src0t == GGML_TYPE_Q3_K && src1t == GGML_TYPE_F32 && extra0_q3_K->noshuffle) { + ggml_cl_mul_mat_q3_k_f32_adreno(backend, src0, src1, dst); + return; + } - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; - ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; - ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + // iq3_s x fp32 + if (src0t == GGML_TYPE_IQ3_S && src1t == GGML_TYPE_F32 && extra0_iq3_s->noshuffle) { + ggml_cl_mul_mat_iq3_s_f32_adreno(backend, src0, src1, dst); + return; + } - cl_ulong offset0 = extra0->offset + src0->view_offs; - cl_ulong offset1 = extra1->offset + src1->view_offs; - cl_ulong offsetd = extrad->offset + dst->view_offs; + // iq3_xxs x fp32 + if (src0t == GGML_TYPE_IQ3_XXS && src1t == GGML_TYPE_F32 && extra0_iq3_xxs->noshuffle) { + ggml_cl_mul_mat_iq3_xxs_f32_adreno(backend, src0, src1, dst); + return; + } -#ifdef GGML_OPENCL_SOA_Q - // view->extra stays pre-SoA; cast to the SoA struct would SIGSEGV. - // Follow view_src to reach the real SoA extra. - const ggml_tensor * soa0_src = src0->view_src != nullptr ? src0->view_src : src0; - ggml_tensor_extra_cl_q1_0 * extra0_q1_0 = (ggml_tensor_extra_cl_q1_0 *)src0->extra; - ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)soa0_src->extra; - ggml_tensor_extra_cl_q4_1 * extra0_q4_1 = (ggml_tensor_extra_cl_q4_1 *)soa0_src->extra; - ggml_tensor_extra_cl_q5_0 * extra0_q5_0 = (ggml_tensor_extra_cl_q5_0 *)soa0_src->extra; - ggml_tensor_extra_cl_q5_1 * extra0_q5_1 = (ggml_tensor_extra_cl_q5_1 *)soa0_src->extra; - ggml_tensor_extra_cl_mxfp4 * extra0_mxfp4 = (ggml_tensor_extra_cl_mxfp4 *)soa0_src->extra; - ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)soa0_src->extra; - ggml_tensor_extra_cl_iq4_nl * extra0_iq4_nl = (ggml_tensor_extra_cl_iq4_nl *)soa0_src->extra; - ggml_tensor_extra_cl_q4_K * extra0_q4_K = (ggml_tensor_extra_cl_q4_K *)soa0_src->extra; - ggml_tensor_extra_cl_q5_K * extra0_q5_K = (ggml_tensor_extra_cl_q5_K *)soa0_src->extra; - ggml_tensor_extra_cl_q6_K * extra0_q6_K = (ggml_tensor_extra_cl_q6_K *)soa0_src->extra; -#endif + // iq1_m x fp32 + if (src0t == GGML_TYPE_IQ1_M && src1t == GGML_TYPE_F32 && extra0_iq1_m->noshuffle) { + ggml_cl_mul_mat_iq1_m_f32_adreno(backend, src0, src1, dst); + return; + } - GGML_TENSOR_LOCALS(int, ne0, src0, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); - GGML_TENSOR_LOCALS(int, ne1, src1, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb1, src1, nb); - GGML_TENSOR_LOCALS(int, ne, dst, ne); - GGML_TENSOR_LOCALS(cl_ulong, nb, dst, nb); + // iq1_s x fp32 + if (src0t == GGML_TYPE_IQ1_S && src1t == GGML_TYPE_F32 && extra0_iq1_s->noshuffle) { + ggml_cl_mul_mat_iq1_s_f32_adreno(backend, src0, src1, dst); + return; + } - int r2 = ne12/ne02; - int r3 = ne13/ne03; + // iq2_s x fp32 + if (src0t == GGML_TYPE_IQ2_S && src1t == GGML_TYPE_F32 && extra0_iq2_s->noshuffle) { + ggml_cl_mul_mat_iq2_s_f32_adreno(backend, src0, src1, dst); + return; + } - GGML_ASSERT(ne00 == ne10); + // iq2_xs x fp32 + if (src0t == GGML_TYPE_IQ2_XS && src1t == GGML_TYPE_F32 && extra0_iq2_xs->noshuffle) { + ggml_cl_mul_mat_iq2_xs_f32_adreno(backend, src0, src1, dst); + return; + } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - // adreno GEMM/GEMV kernels do not support broadcast, assuming ne2 and ne3 are 1 for src1 - // so we handle broadcast here - if ((ne12 > 1 || ne13 > 1) && ne02 == 1 && ne03 == 1 && - src0t != GGML_TYPE_F16 && src0t != GGML_TYPE_F32) { - for (int i13 = 0; i13 < ne13; ++i13) { - for (int i12 = 0; i12 < ne12; ++i12) { - ggml_tensor s1 = *src1; - s1.ne[2] = 1; s1.ne[3] = 1; - s1.view_offs = src1->view_offs + (size_t)i12*nb12 + (size_t)i13*nb13; - ggml_tensor d = *dst; - d.ne[2] = 1; d.ne[3] = 1; - d.view_offs = dst->view_offs + (size_t)i12*nb2 + (size_t)i13*nb3; - ggml_cl_mul_mat(backend, src0, &s1, &d); - } + // iq2_xxs x fp32 + if (src0t == GGML_TYPE_IQ2_XXS && src1t == GGML_TYPE_F32 && extra0_iq2_xxs->noshuffle) { + ggml_cl_mul_mat_iq2_xxs_f32_adreno(backend, src0, src1, dst); + return; } - return; - } -#endif - int nth0 = 32; - int nth1 = 1; - int nrows = 1; - // The number of values produced by each subgroup - int ndst = 4; + // q4_k x fp32 + if (src0t == GGML_TYPE_Q4_K && src1t == GGML_TYPE_F32 && !use_flat_gemv_for_large_m_q4_K(backend_ctx, src0)) { + ggml_cl_mul_mat_q4_k_f32_adreno(backend, src0, src1, dst); + return; + } - cl_kernel kernel; + // q6_K x fp32 + if (src0t == GGML_TYPE_Q6_K && src1t == GGML_TYPE_F32 && !use_flat_gemv_for_large_m_q6_K(backend_ctx, src0)) { + ggml_cl_mul_mat_q6_K_f32_adreno(backend, src0, src1, dst); + return; + } -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if(src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32){ - // Two tiling assumptions these kernels make but nothing enforced: - // - // ne00 % TILESIZE_K(16): the K loop has no tail, so a K that does not - // divide folds 1-15 rows of whatever follows the operands into every - // output. - // - // ne01 % TILESIZE_M(64): mm_store_c_N guards the n direction with its - // `mask` argument but nothing guards m -- the store walks all 64 rows - // of the tile at a stride of M. When M does not divide, the last tile - // does not run off the end of the buffer, it writes 64 - (M % 64) - // values ON TOP OF the next column, so the result is silently wrong. - // Reachable on the KQV side for any head size >= 64 that is not a - // multiple of it (80, 96, 112). - // - // Attention shapes in the graph satisfy both -- head sizes are multiples - // of 64 and n_kv is padded -- which is why this has stayed latent. - // Declining leaves the odd shapes on the generic GEMM, which handles them. - if (ne01 >= 64 && ne1 >= 32 && ne00 >= 16 && - (ne00 % 16) == 0 && (ne01 % 64) == 0 && (ne12 % ne02) == 0 && - // the KQ/KQV image kernels do not handle dim 3 (multi-stream batches) - ne03 == 1 && ne13 == 1 && - // dst is wrapped with image1d_buffer, the size limit applies, also src0 - (ne0 * ne1 * dst->ne[2] * dst->nb[0] / 4 <= backend_ctx->image_max_buffer_size)) { - // For KQ. - // - // Layout admission, mirroring the KQV arm below. The KQ kernel takes - // no stride arguments for A or B: it derives them as K*D_A*2 and - // K*D_B*4, i.e. it assumes both operands pack exactly D heads of K - // elements per row. Every real KV-cache view and permuted-Q view - // does, but a view spanning part of a wider allocation does not, and - // the kernel then walks the wrong rows with nothing to range-check - // it. Gate on the packed layout itself rather than on the stride - // ORDERING, which a wider parent satisfies just as well. - const bool kq_packed_a = (nb01 == (cl_ulong)ne00 * ne02 * ggml_type_size(src0t)) && - (nb02 == (cl_ulong)ne00 * ggml_type_size(src0t)); - const bool kq_packed_b = (nb11 == (cl_ulong)ne10 * ne12 * ggml_type_size(src1t)) && - (nb12 == (cl_ulong)ne10 * ggml_type_size(src1t)); - // - // ggml_is_permuted(src0) stands in for "K is head-major", but it is - // only a proxy and it COLLAPSES at n_head_kv == 1: with a single - // head there is no head stride to be out of order, so nb01 == nb02 - // and the view reports itself unpermuted. Such a KQ was declined - // here and fell through to the generic GEMM (gemma-4 E2B, and any - // other multi-query model). The packed check above is the contract - // the kernel actually needs -- it pins both strides exactly -- so - // require permutedness only where there is more than one head for - // it to mean anything. - // - // Default on; GGML_OPENCL_KQ_NHEAD_KV1=0 restores the old proxy so - // the two routings can be compared in one binary. - static const char * kq_nhkv1_env = getenv("GGML_OPENCL_KQ_NHEAD_KV1"); - static const bool kq_nhkv1_on = - (kq_nhkv1_env == nullptr || kq_nhkv1_env[0] != '0'); - if ((ggml_is_permuted(src0) || (ne02 == 1 && kq_nhkv1_on)) && ggml_is_permuted(src1) && - kq_packed_a && kq_packed_b && - ((nb01 * ne01 / 4)/4 <= backend_ctx->image_max_buffer_size) && - nb00 <= nb02 && - nb02 <= nb01 && - nb01 <= nb03 && - nb10 <= nb12 && - nb12 <= nb11 && - nb11 <= nb13) { - ggml_cl_mul_mat_kq_kqv_adreno(backend, src0, src1, dst, /*is_kq =*/ true); - return; - } - // For KQV. Reaching this arm is what makes the op a KQV; the callee - // is told so explicitly rather than re-deriving it from the strides - // the arm above has already ruled on. - if (!ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && - ((nb02 * ne02 / 4)/4 <= backend_ctx->image_max_buffer_size)) { - ggml_cl_mul_mat_kq_kqv_adreno(backend, src0, src1, dst, /*is_kq =*/ false); + // q5_K x fp32 + if (src0t == GGML_TYPE_Q5_K && src1t == GGML_TYPE_F32 && + enable_adreno_trans_weight_q5_K(backend_ctx, src0)) { + ggml_cl_mul_mat_q5_K_f32_adreno(backend, src0, src1, dst); + return; + } + } // if (ne01 && ne1) +#endif // GGML_OPENCL_USE_ADRENO_KERNELS + + // GEMM using local memory + // Current BK = 16, so ne00 % 16 == 0 + // + // Certain A7X compiler (E031.41) executes kernel_mul_mm_f32_f32_l4_lm poorly; + // matrices with ne11 <= 8 appears OK. + // Fallback to the MV style kernels for A7x and ne11 > 8. + // Override with GGML_OPENCL_A7X_F32_LM_BYPASS=0. + static const char * a7x_f32lm_env = getenv("GGML_OPENCL_A7X_F32_LM_BYPASS"); + static const bool a7x_f32lm_bypass = (a7x_f32lm_env == nullptr || a7x_f32lm_env[0] != '0'); + if (src1t == GGML_TYPE_F32 && + ne00 % 16 == 0 && + ne11 > 1 && + !(a7x_f32lm_bypass && src0t == GGML_TYPE_F32 && ne11 > 8 && + backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X)) { + switch(src0t) { + case GGML_TYPE_F32: { + // Small-N f32 GEMV for the spec/MTP verify batch: the tiled GEMM + // below always computes a full 64x64 tile, so at ne11=3 with a + // skinny f32 weight (GDN ssm_alpha/ssm_beta, M=32) it launches one + // under-occupied WG at ~2.3% tile utilization. Route to a per-output + // (m,n) GEMV (64-thread WG, K-split + __local reduce) instead. + // Opt-in GGML_OPENCL_F32_MC=1; 2D contiguous, small N + skinny M only. + static const bool f32_mc = (getenv("GGML_OPENCL_F32_MC") != nullptr); + if (f32_mc && ne11 >= 2 && ne11 <= 8 && ne01 <= 512 && (ne00 % 4 == 0) && + ne02 == 1 && ne12 == 1 && ne13 == 1 && + ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { + cl_kernel kmc = backend_ctx->kernel_gemv_f32_f32_mc; + int stride_a = ne00, stride_b = ne00, stride_d = ne01; + CL_CHECK(clSetKernelArg(kmc, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kmc, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kmc, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kmc, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kmc, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kmc, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kmc, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kmc, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kmc, 8, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kmc, 9, sizeof(int), &stride_a)); + CL_CHECK(clSetKernelArg(kmc, 10, sizeof(int), &stride_b)); + CL_CHECK(clSetKernelArg(kmc, 11, sizeof(int), &stride_d)); + size_t gws[3] = {64, (size_t)ne01 * (size_t)ne11, 1}; + size_t lws[3] = {64, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kmc, 3, gws, lws, dst); + return; + } + kernel = backend_ctx->kernel_mul_mm_f32_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + cl_mem mem_src0 = extra0->data_device; + cl_mem mem_src1 = extra1->data_device; + + cl_ulong nb00_cont = nb00; + cl_ulong nb01_cont = nb01; + cl_ulong nb02_cont = nb02; + cl_ulong nb03_cont = nb03; + + cl_ulong nb10_cont = nb10; + cl_ulong nb11_cont = nb11; + cl_ulong nb12_cont = nb12; + cl_ulong nb13_cont = nb13; + + cl_ulong offset0_cont = offset0; + cl_ulong offset1_cont = offset1; + + if (!ggml_is_contiguous(src0)) { + backend_ctx->prealloc_src0.allocate(backend_ctx->context, ggml_nbytes(src0)); + ggml_cl_copy_to_contiguous(backend, src0, backend_ctx->prealloc_src0.buffer, + nb00_cont, nb01_cont, nb02_cont, nb03_cont); + mem_src0 = backend_ctx->prealloc_src0.buffer; + offset0_cont = 0; + } + + if (!ggml_is_contiguous(src1)) { + backend_ctx->prealloc_src1.allocate(backend_ctx->context, ggml_nbytes(src1)); + ggml_cl_copy_to_contiguous(backend, src1, backend_ctx->prealloc_src1.buffer, + nb10_cont, nb11_cont, nb12_cont, nb13_cont); + mem_src1 = backend_ctx->prealloc_src1.buffer; + offset1_cont = 0; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &mem_src0)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0_cont)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &mem_src1)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1_cont)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - } + case GGML_TYPE_F16: { +#ifdef GGML_OPENCL_USE_ADRENO_KERNELS + if (ggml_cl_can_use_adreno_xmem_gemm_f16_f32(backend_ctx, src0, src1, dst)) { + ggml_cl_mul_mat_f16_f32_adreno_xmem(backend, src0, src1, dst); + return; + } +#endif + static const char * mm_narrow_n_env = getenv("GGML_OPENCL_MM_NARROW_N"); + const bool use_narrow_n = (mm_narrow_n_env == nullptr || mm_narrow_n_env[0] != '0') && ne11 >= 2 && ne11 <= 8; + kernel = use_narrow_n ? backend_ctx->kernel_mul_mm_f16_f32_l4_lm_n8 : backend_ctx->kernel_mul_mm_f16_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) - static const char * mm_kq_gqa_img_env = getenv("GGML_OPENCL_MM_KQ_GQA_IMG"); - static const bool mm_kq_gqa_img_on = (mm_kq_gqa_img_env == nullptr || mm_kq_gqa_img_env[0] != '0'); - static const char * mm_kq_gqa_r4_img_env = getenv("GGML_OPENCL_MM_KQ_GQA_R4_IMG"); - static const bool mm_kq_gqa_r4_img_on = (mm_kq_gqa_r4_img_env == nullptr || mm_kq_gqa_r4_img_env[0] != '0'); - const bool img_r4_gate = - mm_kq_gqa_r4_img_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img != nullptr && - ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 128 && - (ne12 % ne02) == 0 && (ne12 / ne02) == 4 && (ne13 / ne03) == 1; - if (mm_kq_gqa_img_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img != nullptr && - ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 128 && - (ne12 % ne02) == 0 && (ne12 / ne02) == 8 && (ne13 / ne03) == 1) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t k_bytes_span = - (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + - (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + - (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + - (size_t)ne00 * nb00_bytes; + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; - const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; - const size_t k_pixels = k_bytes >> 4; - if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { - cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4_img; - cl_mem K_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kq_img_pool, - extra0->data_device, offset0, k_bytes, CL_FLOAT); - if (K_img != nullptr) { - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); + cl_mem mem_src0 = extra0->data_device; + cl_mem mem_src1 = extra1->data_device; - const int nth0_d = 64; - const int64_t n_wg_x = ne01 / 16; - size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; - size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; - } - } - } + cl_ulong nb00_cont = nb00; + cl_ulong nb01_cont = nb01; + cl_ulong nb02_cont = nb02; + cl_ulong nb03_cont = nb03; - // r2=4 specialization - if (img_r4_gate) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t k_bytes_span = - (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + - (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + - (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + - (size_t)ne00 * nb00_bytes; - const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; - const size_t k_pixels = k_bytes >> 4; - if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { - cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r4_img; - cl_mem K_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kq_img_pool, - extra0->data_device, offset0, k_bytes, CL_FLOAT); - if (K_img != nullptr) { - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); + cl_ulong nb10_cont = nb10; + cl_ulong nb11_cont = nb11; + cl_ulong nb12_cont = nb12; + cl_ulong nb13_cont = nb13; - const int nth0_d = 64; - const int64_t n_wg_x = ne01 / 16; - size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; - size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + cl_ulong offset0_cont = offset0; + cl_ulong offset1_cont = offset1; + + if (!ggml_is_contiguous(src0)) { + backend_ctx->prealloc_src0.allocate(backend_ctx->context, ggml_nbytes(src0)); + ggml_cl_copy_to_contiguous(backend, src0, backend_ctx->prealloc_src0.buffer, + nb00_cont, nb01_cont, nb02_cont, nb03_cont); + mem_src0 = backend_ctx->prealloc_src0.buffer; + offset0_cont = 0; + } + + if (!ggml_is_contiguous(src1)) { + backend_ctx->prealloc_src1.allocate(backend_ctx->context, ggml_nbytes(src1)); + ggml_cl_copy_to_contiguous(backend, src1, backend_ctx->prealloc_src1.buffer, + nb10_cont, nb11_cont, nb12_cont, nb13_cont); + mem_src1 = backend_ctx->prealloc_src1.buffer; + offset1_cont = 0; } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &mem_src0)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0_cont)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &mem_src1)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1_cont)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // BN=8/TN=1 keeps 128 threads for small batches, including attention KQ/KQV. + const int bn = use_narrow_n ? 8 : 64; + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, bn)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; } - } + case GGML_TYPE_Q1_0: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - // DK=256, r2=2 specialization - static const char * mm_kq_r2_dk256_env = getenv("GGML_OPENCL_MM_KQ_GQA_R2_DK256_IMG"); - static const bool mm_kq_r2_dk256_on = (mm_kq_r2_dk256_env != nullptr && mm_kq_r2_dk256_env[0] != '0'); - if (mm_kq_r2_dk256_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img != nullptr && - ne11 == 1 && ne01 >= 64 && (ne01 % 16) == 0 && ne00 == 256 && - (ne12 % ne02) == 0 && (ne12 / ne02) == 2 && (ne13 / ne03) == 1) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t k_bytes_span = - (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + - (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + - (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + - (size_t)ne00 * nb00_bytes; - const size_t k_bytes = (k_bytes_span + 15) & ~(size_t)15; - const size_t k_pixels = k_bytes >> 4; - if (k_pixels > 0 && k_pixels <= backend_ctx->image_max_buffer_size) { - cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa_r2_dk256_img; - cl_mem K_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kq_img_pool, - extra0->data_device, offset0, k_bytes, CL_FLOAT); - if (K_img != nullptr) { - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &K_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); + kernel = backend_ctx->kernel_mul_mm_q1_0_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - const int nth0_d = 64; - const int64_t n_wg_x = ne01 / 16; - size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; - size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; - } + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; } - } + case GGML_TYPE_Q2_0: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - // GQA-coalesced KQV for decode using image1d_buffer_t - static const char * mm_kqv_gqa_img_env = getenv("GGML_OPENCL_MM_KQV_GQA_IMG"); - static const bool mm_kqv_gqa_img_on = (mm_kqv_gqa_img_env != nullptr && mm_kqv_gqa_img_env[0] != '0'); - if (mm_kqv_gqa_img_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img != nullptr && - ne11 == 1 && ne01 == 128 && - (ne12 % ne02) == 0 && (ne12 / ne02) == 8 && (ne13 / ne03) == 1) { - const size_t nb00_bytes = sizeof(uint16_t); - const size_t v_bytes_span = - (size_t)(ne01 > 0 ? ne01 - 1 : 0) * (size_t)nb01 + - (size_t)(ne02 > 0 ? ne02 - 1 : 0) * (size_t)nb02 + - (size_t)(ne03 > 0 ? ne03 - 1 : 0) * (size_t)nb03 + - (size_t)ne00 * nb00_bytes; - const size_t v_bytes = (v_bytes_span + 7) & ~(size_t)7; - const size_t v_pixels = v_bytes >> 3; - if (v_pixels > 0 && v_pixels <= backend_ctx->image_max_buffer_size) { - cl_kernel kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa_img; - cl_mem V_img = ggml_cl_img_pool_get_or_create( - backend_ctx, backend_ctx->kqv_img_pool, - extra0->data_device, offset0, v_bytes, CL_HALF_FLOAT); - if (V_img != nullptr) { - cl_uint k_arg = 0; - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &V_img)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, k_arg++, sizeof(int), &r3)); + kernel = backend_ctx->kernel_mul_mm_q2_0_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; - const int nth0_d = 64; - const int64_t n_wg_x = ne01 / 8; - size_t global_work_size[] = {(size_t)n_wg_x * nth0_d, (size_t)1, (size_t)ne02 * ne13}; - size_t local_work_size[] = {(size_t)nth0_d, (size_t)1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; - } + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q2_0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q2_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; } - } - } + case GGML_TYPE_Q4_0: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - if (ne01 && ne1 && use_adreno_kernels(backend_ctx, src0)) { - // NOTE: Kernels using image1d_buffer_t (e.g., src0_q) would normally require - // a limit check, but q4_0 / q4_1 tensors are very unlikely to exceed that - // limit, so the check is omitted. + kernel = backend_ctx->kernel_mul_mm_q4_0_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) - // q1_0 x fp32 - if (src0t == GGML_TYPE_Q1_0 && src1t == GGML_TYPE_F32 && - enable_adreno_trans_weight(backend_ctx, src0)) { - ggml_cl_mul_mat_q1_0_f32_adreno(backend, src0, src1, dst); + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; - } + } + case GGML_TYPE_Q4_1: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - // q4_0 x fp32 - if(src0t == GGML_TYPE_Q4_0 && src1t == GGML_TYPE_F32) { - ggml_cl_mul_mat_q4_0_f32_adreno(backend, src0, src1, dst); - return; - } + kernel = backend_ctx->kernel_mul_mm_q4_1_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) - // q4_1 x fp32 - if (src0t == GGML_TYPE_Q4_1 && src1t == GGML_TYPE_F32) { - ggml_cl_mul_mat_q4_1_f32_adreno(backend, src0, src1, dst); - return; - } + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; - // q5_0 x fp32 - if (src0t == GGML_TYPE_Q5_0 && src1t == GGML_TYPE_F32) { - ggml_cl_mul_mat_q5_0_f32_adreno(backend, src0, src1, dst); - return; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); - // q5_1 x fp32 - if (src0t == GGML_TYPE_Q5_1 && src1t == GGML_TYPE_F32) { - ggml_cl_mul_mat_q5_1_f32_adreno(backend, src0, src1, dst); - return; - } + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; - // iq4_nl x fp32 - if (src0t == GGML_TYPE_IQ4_NL && src1t == GGML_TYPE_F32) { - ggml_cl_mul_mat_iq4_nl_f32_adreno(backend, src0, src1, dst); - return; - } + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_Q5_0: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - // q8_0 x fp32 - if (src0t == GGML_TYPE_Q8_0 && src1t == GGML_TYPE_F32 && - enable_adreno_trans_weight(backend_ctx, src0)) { - ggml_cl_mul_mat_q8_0_f32_adreno(backend, src0, src1, dst); + kernel = backend_ctx->kernel_mul_mm_q5_0_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; - } + } + case GGML_TYPE_Q5_1: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_q5_1_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) - // q4_k x fp32 - if (src0t == GGML_TYPE_Q4_K && src1t == GGML_TYPE_F32 && !use_flat_gemv_for_large_m_q4_K(backend_ctx, src0)) { - ggml_cl_mul_mat_q4_k_f32_adreno(backend, src0, src1, dst); - return; - } + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; - // q6_K x fp32 - if (src0t == GGML_TYPE_Q6_K && src1t == GGML_TYPE_F32 && !use_flat_gemv_for_large_m_q6_K(backend_ctx, src0)) { - ggml_cl_mul_mat_q6_K_f32_adreno(backend, src0, src1, dst); - return; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); - // q5_K x fp32 - if (src0t == GGML_TYPE_Q5_K && src1t == GGML_TYPE_F32 && - enable_adreno_trans_weight_q5_K(backend_ctx, src0)) { - ggml_cl_mul_mat_q5_K_f32_adreno(backend, src0, src1, dst); - return; - } - } // if (ne01 && ne1) -#endif // GGML_OPENCL_USE_ADRENO_KERNELS + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; - // GEMM using local memory - // Current BK = 16, so ne00 % 16 == 0 - // - // Certain A7X compiler (E031.41) executes kernel_mul_mm_f32_f32_l4_lm poorly; - // matrices with ne11 <= 8 appears OK. - // Fallback to the MV style kernels for A7x and ne11 > 8. - // Override with GGML_OPENCL_A7X_F32_LM_BYPASS=0. - static const char * a7x_f32lm_env = getenv("GGML_OPENCL_A7X_F32_LM_BYPASS"); - static const bool a7x_f32lm_bypass = (a7x_f32lm_env == nullptr || a7x_f32lm_env[0] != '0'); - if (src1t == GGML_TYPE_F32 && - ne00 % 16 == 0 && - ne11 > 1 && - !(a7x_f32lm_bypass && src0t == GGML_TYPE_F32 && ne11 > 8 && - backend_ctx->adreno_gen == ADRENO_GPU_GEN::A7X)) { - switch(src0t) { - case GGML_TYPE_F32: { - // Small-N f32 GEMV for the spec/MTP verify batch: the tiled GEMM - // below always computes a full 64x64 tile, so at ne11=3 with a - // skinny f32 weight (GDN ssm_alpha/ssm_beta, M=32) it launches one - // under-occupied WG at ~2.3% tile utilization. Route to a per-output - // (m,n) GEMV (64-thread WG, K-split + __local reduce) instead. - // Opt-in GGML_OPENCL_F32_MC=1; 2D contiguous, small N + skinny M only. - static const bool f32_mc = (getenv("GGML_OPENCL_F32_MC") != nullptr); - if (f32_mc && ne11 >= 2 && ne11 <= 8 && ne01 <= 512 && (ne00 % 4 == 0) && - ne02 == 1 && ne12 == 1 && ne13 == 1 && - ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - cl_kernel kmc = backend_ctx->kernel_gemv_f32_f32_mc; - int stride_a = ne00, stride_b = ne00, stride_d = ne01; - CL_CHECK(clSetKernelArg(kmc, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kmc, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kmc, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kmc, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kmc, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kmc, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kmc, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kmc, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kmc, 8, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kmc, 9, sizeof(int), &stride_a)); - CL_CHECK(clSetKernelArg(kmc, 10, sizeof(int), &stride_b)); - CL_CHECK(clSetKernelArg(kmc, 11, sizeof(int), &stride_d)); - size_t gws[3] = {64, (size_t)ne01 * (size_t)ne11, 1}; - size_t lws[3] = {64, 1, 1}; - backend_ctx->enqueue_ndrange_kernel(kmc, 3, gws, lws, dst); - return; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_Q8_0: { + if (ne11 < 32) { + break; } - kernel = backend_ctx->kernel_mul_mm_f32_f32_l4_lm; + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_q8_0_f32_l4_lm; nth0 = 128; // calculated as (BM*BN)/(TM*TN) int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - cl_mem mem_src0 = extra0->data_device; - cl_mem mem_src1 = extra1->data_device; - - cl_ulong nb00_cont = nb00; - cl_ulong nb01_cont = nb01; - cl_ulong nb02_cont = nb02; - cl_ulong nb03_cont = nb03; - - cl_ulong nb10_cont = nb10; - cl_ulong nb11_cont = nb11; - cl_ulong nb12_cont = nb12; - cl_ulong nb13_cont = nb13; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - cl_ulong offset0_cont = offset0; - cl_ulong offset1_cont = offset1; + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; - if (!ggml_is_contiguous(src0)) { - backend_ctx->prealloc_src0.allocate(backend_ctx->context, ggml_nbytes(src0)); - ggml_cl_copy_to_contiguous(backend, src0, backend_ctx->prealloc_src0.buffer, - nb00_cont, nb01_cont, nb02_cont, nb03_cont); - mem_src0 = backend_ctx->prealloc_src0.buffer; - offset0_cont = 0; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_IQ4_NL: { + if (ne11 < 32) { + break; } - - if (!ggml_is_contiguous(src1)) { - backend_ctx->prealloc_src1.allocate(backend_ctx->context, ggml_nbytes(src1)); - ggml_cl_copy_to_contiguous(backend, src1, backend_ctx->prealloc_src1.buffer, - nb10_cont, nb11_cont, nb12_cont, nb13_cont); - mem_src1 = backend_ctx->prealloc_src1.buffer; - offset1_cont = 0; + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &mem_src0)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0_cont)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &mem_src1)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1_cont)); + kernel = backend_ctx->kernel_mul_mm_iq4_nl_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); @@ -24274,87 +30882,327 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_Q2_K: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_q2_k_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q2_K->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q2_K->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q2_K->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_Q3_K: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_q3_k_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q3_K->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q3_K->hm)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q3_K->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q3_K->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_IQ3_S: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_iq3_s_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq3_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq3_s->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq3_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_iq3_s->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_iq3_s->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_IQ3_XXS: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_iq3_xxs_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq3_xxs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq3_xxs->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq3_xxs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; size_t local_work_size[] = {(size_t)nth0, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_F16: { -#ifdef GGML_OPENCL_USE_ADRENO_KERNELS - if (ggml_cl_can_use_adreno_xmem_gemm_f16_f32(backend_ctx, src0, src1, dst)) { - ggml_cl_mul_mat_f16_f32_adreno_xmem(backend, src0, src1, dst); - return; + case GGML_TYPE_IQ1_M: { + if (ne11 < 32) { + break; } -#endif - kernel = backend_ctx->kernel_mul_mm_f16_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } + + kernel = backend_ctx->kernel_mul_mm_iq1_m_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - cl_mem mem_src0 = extra0->data_device; - cl_mem mem_src1 = extra1->data_device; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq1_m->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq1_m->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq1_m->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; - cl_ulong nb00_cont = nb00; - cl_ulong nb01_cont = nb01; - cl_ulong nb02_cont = nb02; - cl_ulong nb03_cont = nb03; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_IQ1_S: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; + } - cl_ulong nb10_cont = nb10; - cl_ulong nb11_cont = nb11; - cl_ulong nb12_cont = nb12; - cl_ulong nb13_cont = nb13; + kernel = backend_ctx->kernel_mul_mm_iq1_s_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; - cl_ulong offset0_cont = offset0; - cl_ulong offset1_cont = offset1; + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; - if (!ggml_is_contiguous(src0)) { - backend_ctx->prealloc_src0.allocate(backend_ctx->context, ggml_nbytes(src0)); - ggml_cl_copy_to_contiguous(backend, src0, backend_ctx->prealloc_src0.buffer, - nb00_cont, nb01_cont, nb02_cont, nb03_cont); - mem_src0 = backend_ctx->prealloc_src0.buffer; - offset0_cont = 0; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq1_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq1_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq1_s->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; - if (!ggml_is_contiguous(src1)) { - backend_ctx->prealloc_src1.allocate(backend_ctx->context, ggml_nbytes(src1)); - ggml_cl_copy_to_contiguous(backend, src1, backend_ctx->prealloc_src1.buffer, - nb10_cont, nb11_cont, nb12_cont, nb13_cont); - mem_src1 = backend_ctx->prealloc_src1.buffer; - offset1_cont = 0; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_IQ2_S: { + if (ne11 < 32) { + break; + } + if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { + break; } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &mem_src0)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0_cont)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &mem_src1)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1_cont)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + kernel = backend_ctx->kernel_mul_mm_iq2_s_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_s->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_iq2_s->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_iq2_s->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; size_t local_work_size[] = {(size_t)nth0, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q1_0: { + case GGML_TYPE_IQ2_XS: { if (ne11 < 32) { break; } @@ -24362,41 +31210,43 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co break; } - kernel = backend_ctx->kernel_mul_mm_q1_0_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + kernel = backend_ctx->kernel_mul_mm_iq2_xs_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_xs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_xs->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_xs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; size_t local_work_size[] = {(size_t)nth0, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q4_0: { + case GGML_TYPE_IQ2_XXS: { if (ne11 < 32) { break; } @@ -24404,41 +31254,43 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co break; } - kernel = backend_ctx->kernel_mul_mm_q4_0_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + kernel = backend_ctx->kernel_mul_mm_iq2_xxs_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; + offset0 = src0->view_offs; int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_xxs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_xxs->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_xxs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); + + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)CEIL_DIV(ne11, 64), (size_t)ne12*ne13}; size_t local_work_size[] = {(size_t)nth0, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q4_1: { + case GGML_TYPE_Q4_K: { if (ne11 < 32) { break; } @@ -24446,33 +31298,35 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co break; } - kernel = backend_ctx->kernel_mul_mm_q4_1_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + kernel = backend_ctx->kernel_mul_mm_q4_k_f32_l4_lm; + // (BM*BN)/(TM*TN): Intel uses an 8x8 microtile (WG=64), others 4x8 (WG=128) + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_K->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_K->s)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_K->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_K->dm)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; @@ -24481,7 +31335,7 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q5_0: { + case GGML_TYPE_Q5_K: { if (ne11 < 32) { break; } @@ -24489,33 +31343,35 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co break; } - kernel = backend_ctx->kernel_mul_mm_q5_0_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + kernel = backend_ctx->kernel_mul_mm_q5_k_f32_l4_lm; + nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; // Intel 8x8 microtile int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; int batch_stride_d = ne0*ne1; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_K->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_K->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_K->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_K->dm)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r3)); // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; @@ -24524,7 +31380,7 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q5_1: { + case GGML_TYPE_Q6_K: { if (ne11 < 32) { break; } @@ -24532,17 +31388,17 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co break; } - kernel = backend_ctx->kernel_mul_mm_q5_1_f32_l4_lm; + kernel = backend_ctx->kernel_mul_mm_q6_k_f32_l4_lm; nth0 = 128; // calculated as (BM*BN)/(TM*TN) int batch_stride_a = ne00*ne01; int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); @@ -24568,23 +31424,52 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); return; } - case GGML_TYPE_Q8_0: { - if (ne11 < 32) { - break; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { - break; - } + default: + break; + } + } - kernel = backend_ctx->kernel_mul_mm_q8_0_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) + if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && + src0->ne[1] > 32 && // M > 32 + src1->ne[1] > 32 && // N > 32 + src0->ne[0] > 32 && // K > 32 + src0->ne[2] == 1 && src0->ne[3] == 1 && + src1->ne[2] == 1 && src1->ne[3] == 1 && + ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && + backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { + ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); + return; + } - int batch_stride_a = ne00*ne01; - int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; + if (!ggml_is_transposed(src0) && + !ggml_is_transposed(src1) && + src1t == GGML_TYPE_F32 && + ne00%32 == 0 && + ne11 > 2) { +#ifdef GGML_OPENCL_SOA_Q + // Set up kernel. + switch(src0t) { + case GGML_TYPE_Q4_0: + // This should have been satisfied. + GGML_ASSERT(ne11 == ne1); + GGML_ASSERT(ne01 == ne0); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; + + kernel = backend_ctx->kernel_mul_mat_q4_0_f32_1d_16x_flat; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + + kernel = backend_ctx->kernel_mul_mat_q4_0_f32_1d_8x_flat; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); @@ -24592,303 +31477,571 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + break; + default: + break; + } - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, 1, 1}; + // Launch kernel. + if (src0t == GGML_TYPE_Q4_0) { + size_t global_work_size[] = {(size_t)(ne01 + 7)/8*nth0, (size_t)ne11*nth1, (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, (size_t)nth1, 1}; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + if (backend_ctx->gpu_family == INTEL) { + // Set global size for Intel. It uses 16x output values. + global_work_size[0] = (size_t)(ne01 + 15)/16*nth0; + global_work_size[1] = (size_t)ne11*nth1; + global_work_size[2] = (size_t)ne12*ne13; } - case GGML_TYPE_IQ4_NL: { - if (ne11 < 32) { - break; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { - break; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } +#else // GGML_OPENCL_SOA_Q + // TODO: add block_q4_0 variant. +#endif // GGML_OPENCL_SOA_Q + } + + // use custom matrix x vector kernel + bool use_f16_mrow = false; + switch (src0t) { + case GGML_TYPE_F32: + //GGML_ASSERT(ne02 == ne12); + GGML_ASSERT(src1t == GGML_TYPE_F32); + kernel = backend_ctx->kernel_mul_mat_f32_f32; + nrows = 4; + + if (backend_ctx->gpu_family == INTEL) { + nth0 = 32; + nth1 = 1; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); + break; + case GGML_TYPE_F16: + //GGML_ASSERT(ne02 == ne12); + if (backend_ctx->gpu_family == INTEL) { + nth0 = 32; + nth1 = 1; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + if (src1t == GGML_TYPE_F32) { + // heuristic for packing more work for Adreno + const bool adreno_use_lane_split = + backend_ctx->gpu_family == ADRENO && + ne11 == 1 && + ne01 >= 8 && + ne00 % 4 == 0 && + r3 == 1 && r2 >= 1 && r2 <= 8 && + (ne12 % r2) == 0; + + if (ne11 * ne12 < 4) { + // Decode (single token): the legacy _1row runs one 64-lane + // subgroup per WG (one output row), under-utilizing BW. Route the + // wide f16 weight matmuls (attn proj + lm_head) to the multi-row + // variant: MROW rows per WG -> more loads in flight + activation + // staged once in __local. ne00<=8192 bounds the LDS. The mrow WG + // is 64 x MROW = 1024 work-items (> Intel's 512 max) and reduces + // within a 64-wide subgroup, so skip on Intel. + if (backend_ctx->f16_mrow && backend_ctx->gpu_family != INTEL && + backend_ctx->kernel_mul_mat_f16_f32_mrow != nullptr && + ne00 >= 128 && ne01 >= 8 && ne00 % 4 == 0 && ne00 <= 8192) { + // The register-blocked / half8 variants cast the src0 row pointer to + // half4 / half8 (8- and 16-byte loads) with no scalar fallback inside + // the kernel. ne00 % 4 == 0 constrains the element count per row, NOT + // the byte stride between rows: a permuted or strided src0 (or a view + // at an odd offset) can leave nb01/nb02/nb03 unaligned. Only take them + // when every row this dispatch touches is aligned; the base mrow kernel + // re-checks per row and falls back to its scalar loop. + const cl_ulong row_addr_bits = offset0 | nb01 | nb02 | nb03; + const bool aligned8 = (row_addr_bits & 7) == 0; + const bool aligned16 = (row_addr_bits & 15) == 0; + + // Register-blocked variants: each subgroup does RPT rows (more + // weight loads in flight per lane). 8/16 use half8 (128-bit) + // loads, gated on ne00 % 8 == 0. + const int rpt = backend_ctx->f16_mrow_rpt; + if (rpt == 16 && ne00 % 8 == 0 && aligned16 && backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2; + } else if (rpt == 8 && ne00 % 8 == 0 && aligned16 && backend_ctx->kernel_mul_mat_f16_f32_mrow_h8 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_h8; + } else if (rpt == 4 && aligned8 && backend_ctx->kernel_mul_mat_f16_f32_mrow_r4 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_r4; + } else if (rpt == 2 && aligned8 && backend_ctx->kernel_mul_mat_f16_f32_mrow_r2 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_r2; + } else { + kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow; + } + use_f16_mrow = true; + } else { + kernel = backend_ctx->kernel_mul_mat_f16_f32_1row; + } + } else if (adreno_use_lane_split && ne00 >= 64 && ne00 <= 128) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr_lq; + nrows = 1; + } else if (adreno_use_lane_split && r2 >= 2 && ne00 > 128 && ne00 <= 256) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr_ls; + nrows = 1; + } else if (ne00 >= 128 && ne01 >= 8 && ne00%4 == 0) { + // multi-output decode variants when Q is a single row + static const char * mm_force_l4_env = getenv("GGML_OPENCL_MM_F16_FORCE_L4"); + static const bool mm_force_l4_on = (mm_force_l4_env != nullptr && mm_force_l4_env[0] != '0'); + const bool can_multi_out = !mm_force_l4_on && ne11 == 1 && ne01 >= 64 && ne01 % 8 == 0; + // paired-K-row variant that doubles per-wave-cycle + static const char * mm_kq_pair_env = getenv("GGML_OPENCL_MM_KQ_PAIR"); + static const bool mm_kq_pair_on = (mm_kq_pair_env != nullptr && mm_kq_pair_env[0] != '0'); + // GQA-coalesced variant that reads each K-row once and + // emits gqa_ratio outputs + static const char * mm_kq_gqa_env = getenv("GGML_OPENCL_MM_KQ_GQA"); + static const bool mm_kq_gqa_on = (mm_kq_gqa_env != nullptr && mm_kq_gqa_env[0] != '0'); + // GQA-coalesced KQV variant (DK=128/r2=8/r3=1) that reads + // each V slab once per K-head and emits all r2 Q-heads + static const char * mm_kqv_gqa_env = getenv("GGML_OPENCL_MM_KQV_GQA"); + static const bool mm_kqv_gqa_on = (mm_kqv_gqa_env != nullptr && mm_kqv_gqa_env[0] != '0'); + if (can_multi_out && (ne01 % 16) == 0 && ne00 == 128 && r2 == 8 && r3 == 1 && mm_kq_gqa_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4; + nrows = 1; + } else if (can_multi_out && ne00 <= 256 && mm_kq_pair_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair; + nrows = 1; + } else if (can_multi_out && ne00 <= 256 && + backend_ctx->kernel_mul_mat_f16_f32_l4_x8 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8; + nrows = 1; + } else if (can_multi_out && ne01 == 128 && r2 == 8 && r3 == 1 && mm_kqv_gqa_on && + backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa; + nrows = 1; + } else if (can_multi_out && + backend_ctx->kernel_mul_mat_f16_f32_l4_y8 != nullptr) { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8; + nrows = 1; + } else if (ne11 == 1) { + // Decode shapes that don't satisfy the x8/y8 row + // constraints (ne01 < 64 or ne01 % 8 != 0) fall back to + // upstream's 4-output _dr kernel. + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr; + nrows = 1; // not used by this kernel + } else { + kernel = backend_ctx->kernel_mul_mat_f16_f32_l4; + nrows = ne11; + } + } else { + kernel = backend_ctx->kernel_mul_mat_f16_f32; + nrows = 4; } - - kernel = backend_ctx->kernel_mul_mm_iq4_nl_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) - - int batch_stride_a = ne00*ne01; - int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); - - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, 1, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + } else { + kernel = backend_ctx->kernel_mul_mat_f16_f16; + nrows = 4; } - case GGML_TYPE_Q4_K: { - if (ne11 < 32) { - break; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { - break; - } - - kernel = backend_ctx->kernel_mul_mm_q4_k_f32_l4_lm; - // (BM*BN)/(TM*TN): Intel uses an 8x8 microtile (WG=64), others 4x8 (WG=128) - nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; - int batch_stride_a = ne00*ne01; - int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_K->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_K->s)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_K->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_K->dm)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); - - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, 1, 1}; - - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); + if (use_f16_mrow) { + const int MROW = 16; // must match MROW in mul_mv_f16_f32_mrow.cl + // rows-per-subgroup multiplier for the selected variant: + // 1/2/4 -> half4 register blocking; 8 -> half8(1 row); 16 -> half8(2 rows) + const int rpt = backend_ctx->f16_mrow_rpt; + int rmul; + if (rpt == 16) rmul = (ne00 % 8 == 0) ? 2 : 1; + else if (rpt == 8) rmul = 1; + else rmul = rpt; // 1,2,4 + const int rows_per_wg = MROW * rmul; + // __local activation buffer: ne00 floats, rounded up for float4 access + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float) * ((ne00 + 3) / 4 * 4), nullptr)); + size_t mrow_global[] = { (size_t)((ne01 + rows_per_wg - 1) / rows_per_wg) * 64, (size_t)ne11 * MROW, (size_t)ne12 * ne13 }; + size_t mrow_local[] = { 64, (size_t)MROW, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, mrow_global, mrow_local, dst); return; } - case GGML_TYPE_Q5_K: { - if (ne11 < 32) { - break; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { - break; - } - - kernel = backend_ctx->kernel_mul_mm_q5_k_f32_l4_lm; - nth0 = (backend_ctx->gpu_family == INTEL) ? 64 : 128; // Intel 8x8 microtile + break; + case GGML_TYPE_Q1_0: { +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_q1_0_f32_flat; - int batch_stride_a = ne00*ne01; - int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; + // nth0 - subgroup size + // nth1 - number of subgroups per workgroup + // ndst - number of output values per workgroup = output per subgroup * number of subgroups + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_K->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_K->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_q5_K->dm)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_q1_0_f32; - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, 1, 1}; + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_Q2_0: { + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); } - case GGML_TYPE_Q6_K: { - if (ne11 < 32) { - break; - } - if (!ggml_is_contiguous(src0) || !ggml_is_contiguous(src1)) { - break; - } - kernel = backend_ctx->kernel_mul_mm_q6_k_f32_l4_lm; - nth0 = 128; // calculated as (BM*BN)/(TM*TN) +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_q2_0_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q2_0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q2_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_q2_0_f32; - int batch_stride_a = ne00*ne01; - int batch_stride_b = ne10*ne11; - int batch_stride_d = ne0*ne1; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_Q4_0: + // This should have been satisfied. + GGML_ASSERT(ne11 == ne1); + GGML_ASSERT(ne01 == ne0); - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q6_K->ql)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q6_K->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q6_K->s)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q6_K->d)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); // stride_a - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); // stride_b - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne01)); // stride_d - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_a)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &batch_stride_b)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &batch_stride_d)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#ifdef GGML_OPENCL_SOA_Q + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; - // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. - size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, 1, 1}; + kernel = backend_ctx->kernel_mul_mat_q4_0_f32_8x_flat; + ndst = 8; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; + kernel = backend_ctx->kernel_mul_mat_q4_0_f32_8x_flat; + ndst =8; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); } - default: - break; - } - } - - if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && - src0->ne[1] > 32 && // M > 32 - src1->ne[1] > 32 && // N > 32 - src0->ne[0] > 32 && // K > 32 - src0->ne[2] == 1 && src0->ne[3] == 1 && - src1->ne[2] == 1 && src1->ne[3] == 1 && - ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && - backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { - ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); - return; - } - - if (!ggml_is_transposed(src0) && - !ggml_is_transposed(src1) && - src1t == GGML_TYPE_F32 && - ne00%32 == 0 && - ne11 > 2) { -#ifdef GGML_OPENCL_SOA_Q - // Set up kernel. - switch(src0t) { - case GGML_TYPE_Q4_0: - // This should have been satisfied. - GGML_ASSERT(ne11 == ne1); - GGML_ASSERT(ne01 == ne0); - if (backend_ctx->gpu_family == INTEL) { - nth0 = 16; - nth1 = 1; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); +#else // GGML_OPENCL_SOA_Q + if (backend_ctx->gpu_family == INTEL) { + // Use 1D local size. Each workgroup is a SIMD group. Each SIMD + // group produces N_DST (4 for Q4_0 kernel) values in the result. + // The number of workgroups on dim 0 (the leading dimension) is + // the nearest multiple of 4 that covers ne0 (equals ne01). + nth0 = 16; + nth1 = 1; - kernel = backend_ctx->kernel_mul_mat_q4_0_f32_1d_16x_flat; - } else if (backend_ctx->gpu_family == ADRENO) { - nth0 = 64; - nth1 = 1; + kernel = backend_ctx->kernel_mul_mat_q4_0_f32; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; - kernel = backend_ctx->kernel_mul_mat_q4_0_f32_1d_8x_flat; - } else { - GGML_ASSERT(false && "TODO: Unknown GPU"); - } + kernel = backend_ctx->kernel_mul_mat_q4_0_f32_v; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); - break; - default: - break; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + case GGML_TYPE_Q4_1: { +#ifdef GGML_OPENCL_SOA_Q + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } - // Launch kernel. - if (src0t == GGML_TYPE_Q4_0) { - size_t global_work_size[] = {(size_t)(ne01 + 7)/8*nth0, (size_t)ne11*nth1, (size_t)ne12*ne13}; - size_t local_work_size[] = {(size_t)nth0, (size_t)nth1, 1}; + kernel = backend_ctx->kernel_mul_mv_q4_1_f32_flat; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r3)); +#else if (backend_ctx->gpu_family == INTEL) { - // Set global size for Intel. It uses 16x output values. - global_work_size[0] = (size_t)(ne01 + 15)/16*nth0; - global_work_size[1] = (size_t)ne11*nth1; - global_work_size[2] = (size_t)ne12*ne13; + nth0 = 16; + nth1 = 1; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - return; - } -#else // GGML_OPENCL_SOA_Q - // TODO: add block_q4_0 variant. + kernel = backend_ctx->kernel_mul_mv_q4_1_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); #endif // GGML_OPENCL_SOA_Q - } + break; + } + case GGML_TYPE_Q5_0: { +#ifdef GGML_OPENCL_SOA_Q + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } - // use custom matrix x vector kernel - bool use_f16_mrow = false; - switch (src0t) { - case GGML_TYPE_F32: - //GGML_ASSERT(ne02 == ne12); - GGML_ASSERT(src1t == GGML_TYPE_F32); - kernel = backend_ctx->kernel_mul_mat_f32_f32; - nrows = 4; + kernel = backend_ctx->kernel_mul_mv_q5_0_f32_flat; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r3)); +#else if (backend_ctx->gpu_family == INTEL) { - nth0 = 32; + nth0 = 16; nth1 = 1; + ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; + ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } + kernel = backend_ctx->kernel_mul_mv_q5_0_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); @@ -24898,146 +32051,63 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q break; - case GGML_TYPE_F16: - //GGML_ASSERT(ne02 == ne12); + } + case GGML_TYPE_Q5_1: { +#ifdef GGML_OPENCL_SOA_Q if (backend_ctx->gpu_family == INTEL) { - nth0 = 32; + nth0 = 16; nth1 = 1; + ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; + ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } - if (src1t == GGML_TYPE_F32) { - // heuristic for packing more work for Adreno - const bool adreno_use_lane_split = - backend_ctx->gpu_family == ADRENO && - ne11 == 1 && - ne01 >= 8 && - ne00 % 4 == 0 && - r3 == 1 && r2 >= 1 && r2 <= 8 && - (ne12 % r2) == 0; - - if (ne11 * ne12 < 4) { - // Decode (single token): the legacy _1row runs one 64-lane - // subgroup per WG (one output row), under-utilizing BW. Route the - // wide f16 weight matmuls (attn proj + lm_head) to the multi-row - // variant: MROW rows per WG -> more loads in flight + activation - // staged once in __local. ne00<=8192 bounds the LDS. The mrow WG - // is 64 x MROW = 1024 work-items (> Intel's 512 max) and reduces - // within a 64-wide subgroup, so skip on Intel. - if (backend_ctx->f16_mrow && backend_ctx->gpu_family != INTEL && - backend_ctx->kernel_mul_mat_f16_f32_mrow != nullptr && - ne00 >= 128 && ne01 >= 8 && ne00 % 4 == 0 && ne00 <= 8192) { - // The register-blocked / half8 variants cast the src0 row pointer to - // half4 / half8 (8- and 16-byte loads) with no scalar fallback inside - // the kernel. ne00 % 4 == 0 constrains the element count per row, NOT - // the byte stride between rows: a permuted or strided src0 (or a view - // at an odd offset) can leave nb01/nb02/nb03 unaligned. Only take them - // when every row this dispatch touches is aligned; the base mrow kernel - // re-checks per row and falls back to its scalar loop. - const cl_ulong row_addr_bits = offset0 | nb01 | nb02 | nb03; - const bool aligned8 = (row_addr_bits & 7) == 0; - const bool aligned16 = (row_addr_bits & 15) == 0; + kernel = backend_ctx->kernel_mul_mv_q5_1_f32_flat; - // Register-blocked variants: each subgroup does RPT rows (more - // weight loads in flight per lane). 8/16 use half8 (128-bit) - // loads, gated on ne00 % 8 == 0. - const int rpt = backend_ctx->f16_mrow_rpt; - if (rpt == 16 && ne00 % 8 == 0 && aligned16 && backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_h8r2; - } else if (rpt == 8 && ne00 % 8 == 0 && aligned16 && backend_ctx->kernel_mul_mat_f16_f32_mrow_h8 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_h8; - } else if (rpt == 4 && aligned8 && backend_ctx->kernel_mul_mat_f16_f32_mrow_r4 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_r4; - } else if (rpt == 2 && aligned8 && backend_ctx->kernel_mul_mat_f16_f32_mrow_r2 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow_r2; - } else { - kernel = backend_ctx->kernel_mul_mat_f16_f32_mrow; - } - use_f16_mrow = true; - } else { - kernel = backend_ctx->kernel_mul_mat_f16_f32_1row; - } - } else if (adreno_use_lane_split && ne00 >= 64 && ne00 <= 128) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr_lq; - nrows = 1; - } else if (adreno_use_lane_split && r2 >= 2 && ne00 > 128 && ne00 <= 256) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr_ls; - nrows = 1; - } else if (ne00 >= 128 && ne01 >= 8 && ne00%4 == 0) { - // multi-output decode variants when Q is a single row - static const char * mm_force_l4_env = getenv("GGML_OPENCL_MM_F16_FORCE_L4"); - static const bool mm_force_l4_on = (mm_force_l4_env != nullptr && mm_force_l4_env[0] != '0'); - const bool can_multi_out = !mm_force_l4_on && ne11 == 1 && ne01 >= 64 && ne01 % 8 == 0; - // paired-K-row variant that doubles per-wave-cycle - static const char * mm_kq_pair_env = getenv("GGML_OPENCL_MM_KQ_PAIR"); - static const bool mm_kq_pair_on = (mm_kq_pair_env != nullptr && mm_kq_pair_env[0] != '0'); - // GQA-coalesced variant that reads each K-row once and - // emits gqa_ratio outputs - static const char * mm_kq_gqa_env = getenv("GGML_OPENCL_MM_KQ_GQA"); - static const bool mm_kq_gqa_on = (mm_kq_gqa_env != nullptr && mm_kq_gqa_env[0] != '0'); - // GQA-coalesced KQV variant (DK=128/r2=8/r3=1) that reads - // each V slab once per K-head and emits all r2 Q-heads - static const char * mm_kqv_gqa_env = getenv("GGML_OPENCL_MM_KQV_GQA"); - static const bool mm_kqv_gqa_on = (mm_kqv_gqa_env != nullptr && mm_kqv_gqa_env[0] != '0'); - if (can_multi_out && (ne01 % 16) == 0 && ne00 == 128 && r2 == 8 && r3 == 1 && mm_kq_gqa_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_gqa4; - nrows = 1; - } else if (can_multi_out && ne00 <= 256 && mm_kq_pair_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8_pair; - nrows = 1; - } else if (can_multi_out && ne00 <= 256 && - backend_ctx->kernel_mul_mat_f16_f32_l4_x8 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_x8; - nrows = 1; - } else if (can_multi_out && ne01 == 128 && r2 == 8 && r3 == 1 && mm_kqv_gqa_on && - backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8_gqa; - nrows = 1; - } else if (can_multi_out && - backend_ctx->kernel_mul_mat_f16_f32_l4_y8 != nullptr) { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_y8; - nrows = 1; - } else if (ne11 == 1) { - // Decode shapes that don't satisfy the x8/y8 row - // constraints (ne01 < 64 or ne01 % 8 != 0) fall back to - // upstream's 4-output _dr kernel. - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4_dr; - nrows = 1; // not used by this kernel - } else { - kernel = backend_ctx->kernel_mul_mat_f16_f32_l4; - nrows = ne11; - } - } else { - kernel = backend_ctx->kernel_mul_mat_f16_f32; - nrows = 4; - } + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &r3)); +#else + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 1; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 1; + ndst = 4; } else { - kernel = backend_ctx->kernel_mul_mat_f16_f16; - nrows = 4; + GGML_ASSERT(false && "TODO: Unknown GPU"); } + kernel = backend_ctx->kernel_mul_mv_q5_1_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); @@ -25047,42 +32117,18 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); - if (use_f16_mrow) { - const int MROW = 16; // must match MROW in mul_mv_f16_f32_mrow.cl - // rows-per-subgroup multiplier for the selected variant: - // 1/2/4 -> half4 register blocking; 8 -> half8(1 row); 16 -> half8(2 rows) - const int rpt = backend_ctx->f16_mrow_rpt; - int rmul; - if (rpt == 16) rmul = (ne00 % 8 == 0) ? 2 : 1; - else if (rpt == 8) rmul = 1; - else rmul = rpt; // 1,2,4 - const int rows_per_wg = MROW * rmul; - // __local activation buffer: ne00 floats, rounded up for float4 access - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float) * ((ne00 + 3) / 4 * 4), nullptr)); - size_t mrow_global[] = { (size_t)((ne01 + rows_per_wg - 1) / rows_per_wg) * 64, (size_t)ne11 * MROW, (size_t)ne12 * ne13 }; - size_t mrow_local[] = { 64, (size_t)MROW, 1 }; - backend_ctx->enqueue_ndrange_kernel(kernel, 3, mrow_global, mrow_local, dst); - return; - } + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q break; - case GGML_TYPE_Q1_0: { + } + case GGML_TYPE_Q8_0: { #ifdef GGML_OPENCL_SOA_Q - kernel = backend_ctx->kernel_mul_mv_q1_0_f32_flat; + kernel = backend_ctx->kernel_mul_mv_q8_0_f32_flat; // nth0 - subgroup size // nth1 - number of subgroups per workgroup @@ -25099,8 +32145,8 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q1_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q1_0->d)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); @@ -25119,8 +32165,11 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); #else - kernel = backend_ctx->kernel_mul_mv_q1_0_f32; + kernel = backend_ctx->kernel_mul_mv_q8_0_f32; + // nth0 - subgroup size + // nth1 - number of subgroups per workgroup + // ndst - number of output values per workgroup = output per subgroup * number of subgroups if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 2; @@ -25155,30 +32204,24 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co #endif // GGML_OPENCL_SOA_Q break; } - case GGML_TYPE_Q4_0: - // This should have been satisfied. - GGML_ASSERT(ne11 == ne1); - GGML_ASSERT(ne01 == ne0); - + case GGML_TYPE_IQ4_NL: { #ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq4_nl_f32_flat; + if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; - - kernel = backend_ctx->kernel_mul_mat_q4_0_f32_8x_flat; ndst = 8; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; - - kernel = backend_ctx->kernel_mul_mat_q4_0_f32_8x_flat; - ndst =8; + ndst = 8; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_0->d)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); @@ -25192,22 +32235,16 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); -#else // GGML_OPENCL_SOA_Q +#else + kernel = backend_ctx->kernel_mul_mv_iq4_nl_f32; + if (backend_ctx->gpu_family == INTEL) { - // Use 1D local size. Each workgroup is a SIMD group. Each SIMD - // group produces N_DST (4 for Q4_0 kernel) values in the result. - // The number of workgroups on dim 0 (the leading dimension) is - // the nearest multiple of 4 that covers ne0 (equals ne01). nth0 = 16; nth1 = 1; - - kernel = backend_ctx->kernel_mul_mat_q4_0_f32; ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; - - kernel = backend_ctx->kernel_mul_mat_q4_0_f32_v; ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); @@ -25230,8 +32267,8 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); #endif // GGML_OPENCL_SOA_Q break; - case GGML_TYPE_Q4_1: { -#ifdef GGML_OPENCL_SOA_Q + } + case GGML_TYPE_Q2_K: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; @@ -25244,38 +32281,33 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } - kernel = backend_ctx->kernel_mul_mv_q4_1_f32_flat; +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_q2_K_f32_flat; + offset0 = src0->view_offs; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_1->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_1->d)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_1->m)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q2_K->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q2_K->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q2_K->dm)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); #else - if (backend_ctx->gpu_family == INTEL) { - nth0 = 16; - nth1 = 1; - ndst = 4; - } else if (backend_ctx->gpu_family == ADRENO) { - nth0 = 64; - nth1 = 1; - ndst = 4; - } else { - GGML_ASSERT(false && "TODO: Unknown GPU"); - } - - kernel = backend_ctx->kernel_mul_mv_q4_1_f32; + kernel = backend_ctx->kernel_mul_mv_q2_K_f32; CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -25285,49 +32317,85 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); #endif // GGML_OPENCL_SOA_Q break; } - case GGML_TYPE_Q5_0: { -#ifdef GGML_OPENCL_SOA_Q + case GGML_TYPE_Q3_K: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; - ndst = 4; + ndst = 2; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; - ndst = 4; + ndst = 2; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } - kernel = backend_ctx->kernel_mul_mv_q5_0_f32_flat; +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_q3_K_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q3_K->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q3_K->hm)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q3_K->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q3_K->d)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_q3_K_f32; - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_0->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_0->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_0->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r3)); -#else + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_IQ3_XXS: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; @@ -25340,7 +32408,33 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } - kernel = backend_ctx->kernel_mul_mv_q5_0_f32; +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq3_xxs_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq3_xxs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq3_xxs->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq3_xxs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq3_xxs_f32; CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -25350,18 +32444,21 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); #endif // GGML_OPENCL_SOA_Q break; } - case GGML_TYPE_Q5_1: { -#ifdef GGML_OPENCL_SOA_Q + case GGML_TYPE_IQ3_S: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; @@ -25374,26 +32471,59 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } - kernel = backend_ctx->kernel_mul_mv_q5_1_f32_flat; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q5_1->qs)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q5_1->qh)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q5_1->d)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q5_1->m)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &r3)); +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq3_s_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq3_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq3_s->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq3_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_iq3_s->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_iq3_s->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r3)); #else + kernel = backend_ctx->kernel_mul_mv_iq3_s_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_IQ1_M: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; @@ -25406,7 +32536,33 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } - kernel = backend_ctx->kernel_mul_mv_q5_1_f32; +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq1_m_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq1_m->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq1_m->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq1_m->sc)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq1_m_f32; CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -25416,37 +32572,63 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); -#endif // GGML_OPENCL_SOA_Q - break; - } - case GGML_TYPE_Q8_0: { -#ifdef GGML_OPENCL_SOA_Q - kernel = backend_ctx->kernel_mul_mv_q8_0_f32_flat; - - // nth0 - subgroup size - // nth1 - number of subgroups per workgroup - // ndst - number of output values per workgroup = output per subgroup * number of subgroups + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_IQ1_S: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; - nth1 = 2; - ndst = nth1*4; + nth1 = 1; + ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; - nth1 = 2; - ndst = nth1*4; + nth1 = 1; + ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq1_s_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq1_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq1_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq1_s->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq1_s_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); @@ -25464,24 +32646,52 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); -#else - kernel = backend_ctx->kernel_mul_mv_q8_0_f32; - - // nth0 - subgroup size - // nth1 - number of subgroups per workgroup - // ndst - number of output values per workgroup = output per subgroup * number of subgroups +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_IQ2_S: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; - nth1 = 2; - ndst = nth1*4; + nth1 = 1; + ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; - nth1 = 2; - ndst = nth1*4; + nth1 = 1; + ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq2_s_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_s->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_s->sg)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_s->qh)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_iq2_s->sc)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra0_iq2_s->d)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq2_s_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); @@ -25504,40 +32714,70 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co #endif // GGML_OPENCL_SOA_Q break; } - case GGML_TYPE_IQ4_NL: { -#ifdef GGML_OPENCL_SOA_Q - kernel = backend_ctx->kernel_mul_mv_iq4_nl_f32_flat; - + case GGML_TYPE_IQ2_XS: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; - ndst = 8; + ndst = 4; } else if (backend_ctx->gpu_family == ADRENO) { nth0 = 64; nth1 = 1; - ndst = 8; + ndst = 4; } else { GGML_ASSERT(false && "TODO: Unknown GPU"); } - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq4_nl->q)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq4_nl->d)); +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq2_xs_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_xs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_xs->sc)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_xs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq2_xs_f32; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); -#else - kernel = backend_ctx->kernel_mul_mv_iq4_nl_f32; - + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_IQ2_XXS: { if (backend_ctx->gpu_family == INTEL) { nth0 = 16; nth1 = 1; @@ -25550,6 +32790,34 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co GGML_ASSERT(false && "TODO: Unknown GPU"); } +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_iq2_xxs_f32_flat; + offset0 = src0->view_offs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_iq2_xxs->qs)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_iq2_xxs->sas)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_iq2_xxs->d)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_iq2_xxs_f32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); @@ -25558,18 +32826,20 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); #endif // GGML_OPENCL_SOA_Q break; } - case GGML_TYPE_Q2_K: - case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: { #ifdef GGML_OPENCL_SOA_Q kernel = backend_ctx->kernel_mul_mv_q4_K_f32_flat; @@ -25876,8 +33146,9 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co src0t == GGML_TYPE_Q5_1 || src0t == GGML_TYPE_Q8_0 || src0t == GGML_TYPE_Q1_0 || + src0t == GGML_TYPE_Q2_0 || src0t == GGML_TYPE_IQ4_NL || - src0t == GGML_TYPE_Q2_K) { + src0t == GGML_TYPE_Q2_K || src0t == GGML_TYPE_Q3_K || src0t == GGML_TYPE_IQ2_S || src0t == GGML_TYPE_IQ2_XS || src0t == GGML_TYPE_IQ2_XXS || src0t == GGML_TYPE_IQ1_S || src0t == GGML_TYPE_IQ1_M || src0t == GGML_TYPE_IQ3_S || src0t == GGML_TYPE_IQ3_XXS) { // Each SIMD group produces N_DST values in the result. Assuming each // workgroup has N_SIMDGROUP SIMD groups, then each workgroup will // produce N_DST*N_SIMDGROUP values in the result. Hence, the grid size @@ -25893,8 +33164,6 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co size_t local_work_size[] = {(size_t)nth0, (size_t)nth1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); - } else if (src0t == GGML_TYPE_Q3_K) { - GGML_ASSERT(false && "not implemented"); } else if (src0t == GGML_TYPE_Q5_K) { size_t global_work_size[] = {(size_t)(ne01+ndst*nth1-1)/(ndst*nth1)*nth0, (size_t)ne11*nth1, (size_t)ne12*ne13}; size_t local_work_size[] = {(size_t)nth0, (size_t)nth1, 1}; @@ -26192,6 +33461,25 @@ static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, GGML_ASSERT(ne00 == ne10); + // the matmul kernels only write the rows an expert owns, so zero the skipped rows here + { + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + cl_kernel kernel_zero = backend_ctx->kernel_moe_zero_dst; + CL_CHECK(clSetKernelArg(kernel_zero, 0, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel_zero, 1, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel_zero, 2, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel_zero, 3, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_zero, 4, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_zero, 5, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel_zero, 6, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel_zero, 7, sizeof(int), &ne0)); + + size_t zero_local[3] = {1, 1, 64}; + size_t zero_global[3] = {(size_t) ne20, (size_t) ne21, 64}; + backend_ctx->enqueue_ndrange_kernel(kernel_zero, 3, zero_global, zero_local, dst); + } + int sgs = 32; // subgroup size int nsg = 1; // number of subgroups int nrows = 1; // number of row in src1 @@ -28259,11 +35547,19 @@ static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, static const char * mxfp4_moe_dp4a_env = getenv("GGML_OPENCL_MXFP4_MOE_DP4A"); bool use_moe_dp4a = mxfp4_moe_dp4a_env ? (atoi(mxfp4_moe_dp4a_env) != 0) - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E); + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E); // dot prod has to be available use_moe_dp4a = backend_ctx->has_integer_dot && use_moe_dp4a; // bin kernel takes precedence, dp4a bin kernel has higher priority than normal bin kernel - if (backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin == nullptr) { + // ldck dp4a bin kernel (X1) has the same priority as normal bin kernel (X2/A8x), they are not expected to coexist. + const bool use_moe_dp4a_ldck = backend_ctx->has_integer_dot && + (!mxfp4_moe_dp4a_env || atoi(mxfp4_moe_dp4a_env) != 0) && + backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin == nullptr && + backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin == nullptr && + backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_ldck_bin != nullptr; + if (use_moe_dp4a_ldck) { + use_moe_dp4a = true; + } else if (backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin == nullptr) { use_moe_dp4a = use_moe_dp4a && backend_ctx->kernel_gemm_moe_mxfp4_f32_ns_bin == nullptr; } @@ -28352,6 +35648,12 @@ static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, backend_ctx->prealloc_moe_qa.allocate(backend_ctx->context, tok_slots * ne00 * sizeof(cl_char)); backend_ctx->prealloc_moe_da.allocate(backend_ctx->context, n_blocks * sizeof(cl_half)); backend_ctx->prealloc_moe_sa.allocate(backend_ctx->context, n_blocks * sizeof(cl_half)); + if (use_moe_dp4a_ldck) { + backend_ctx->prealloc_moe_qa_trans.allocate(backend_ctx->context, tok_slots * ne00 * sizeof(cl_char)); + backend_ctx->prealloc_moe_da_trans.allocate(backend_ctx->context, n_blocks * sizeof(cl_float)); + // matches max_constant_size of src1_a_cm in the ldck kernel + backend_ctx->prealloc_moe_qda_on_chip.allocate(backend_ctx->context, 2304); + } // fused reorder + q8_1 quant straight from the original // activations (no intermediate f32 reorder buffer). mxfp4 has no @@ -28376,13 +35678,33 @@ static void ggml_cl_mul_mat_id(ggml_backend_t backend, const ggml_tensor * src0, cl_kernel dk = backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a; if (backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin) { dk = backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_bin; + } else if (use_moe_dp4a_ldck) { + dk = backend_ctx->kernel_gemm_moe_mxfp4_q8_1_dp4a_ldck_bin; + + // per-tile transpose of qa/da for the ldck kernel + cl_kernel tk = backend_ctx->kernel_transpose_activation_q8; + CL_CHECK(clSetKernelArg(tk, 0, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(tk, 1, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa_trans.buffer)); + CL_CHECK(clSetKernelArg(tk, 2, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + CL_CHECK(clSetKernelArg(tk, 3, sizeof(cl_mem), &backend_ctx->prealloc_moe_da_trans.buffer)); + CL_CHECK(clSetKernelArg(tk, 4, sizeof(cl_mem), &(backend_ctx->prealloc_total_tiles.buffer))); + CL_CHECK(clSetKernelArg(tk, 5, sizeof(cl_uint), &ne00)); + size_t tk_local[3] = { 32, 8, 1 }; + size_t tk_global[3] = { 32, (size_t)(ne00 / 4), (size_t)max_post_router_tile }; + backend_ctx->enqueue_ndrange_kernel(tk, 3, tk_global, tk_local, dst); } int aidx = 0; CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &extra0_mxfp4->q_img)); CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &extra0_mxfp4->e)); - CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); - CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + if (use_moe_dp4a_ldck) { + CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa_trans.buffer)); + CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da_trans.buffer)); + CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qda_on_chip.buffer)); + } else { + CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_qa.buffer)); + CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &backend_ctx->prealloc_moe_da.buffer)); + } CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &buf_src2)); CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &buf_src2_emap)); CL_CHECK(clSetKernelArg(dk, aidx++, sizeof(cl_mem), &buf_dst_image)); @@ -28652,6 +35974,9 @@ static void ggml_cl_cpy(ggml_backend_t backend, const ggml_tensor * src0, const switch (src0t) { case GGML_TYPE_F32: switch (src1t) { + case GGML_TYPE_I32: + kernel = backend_ctx->kernel_cpy_f32_i32; + break; case GGML_TYPE_F16: kernel = backend_ctx->kernel_cpy_f32_f16; break; @@ -28678,6 +36003,9 @@ static void ggml_cl_cpy(ggml_backend_t backend, const ggml_tensor * src0, const break; case GGML_TYPE_I32: switch (src1t) { + case GGML_TYPE_F32: + kernel = backend_ctx->kernel_cpy_i32_f32; + break; case GGML_TYPE_I32: kernel = backend_ctx->kernel_cpy_i32_i32; break; @@ -29394,6 +36722,400 @@ static void ggml_cl_im2col(ggml_backend_t backend, const ggml_tensor * src0, con backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } +static void ggml_cl_im2col_3d(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F16 || dst->type == GGML_TYPE_F32); + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + const int32_t s0 = ((const int32_t*)(dst->op_params))[0]; + const int32_t s1 = ((const int32_t*)(dst->op_params))[1]; + const int32_t s2 = ((const int32_t*)(dst->op_params))[2]; + const int32_t p0 = ((const int32_t*)(dst->op_params))[3]; + const int32_t p1 = ((const int32_t*)(dst->op_params))[4]; + const int32_t p2 = ((const int32_t*)(dst->op_params))[5]; + const int32_t d0 = ((const int32_t*)(dst->op_params))[6]; + const int32_t d1 = ((const int32_t*)(dst->op_params))[7]; + const int32_t d2 = ((const int32_t*)(dst->op_params))[8]; + const cl_long IC = ((const int32_t*)(dst->op_params))[9]; + + const cl_long N = src1->ne[3] / IC; + const cl_long ID = src1->ne[2]; + const cl_long IH = src1->ne[1]; + const cl_long IW = src1->ne[0]; + + const cl_long KD = src0->ne[2]; + const cl_long KH = src0->ne[1]; + const cl_long KW = src0->ne[0]; + + const cl_long OD = dst->ne[3] / N; + const cl_long OH = dst->ne[2]; + const cl_long OW = dst->ne[1]; + + const size_t es = ggml_element_size(src1); + const cl_long stride_x = src1->nb[0] / es; + const cl_long stride_y = src1->nb[1] / es; + const cl_long stride_z = src1->nb[2] / es; + const cl_long stride_q = src1->nb[3] / es; + + const cl_long IC_KD_KH_KW = IC * KD * KH * KW; + + cl_kernel kernel; + + if (dst->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_im2col_3d_f16; + } else { + kernel = backend_ctx->kernel_im2col_3d_f32; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_long), &IC)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_long), &ID)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_long), &IH)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_long), &IW)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_long), &KD)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_long), &KH)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_long), &KW)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_long), &OD)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_long), &OH)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_long), &OW)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_long), &N)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_long), &stride_x)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_long), &stride_y)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_long), &stride_z)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_long), &stride_q)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &s0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &s1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &s2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &p0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &p1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &p2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &d0)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(int), &d1)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(int), &d2)); + + const size_t local_col = 64; + const size_t num_blocks = (IC_KD_KH_KW + local_col - 1) / local_col; + size_t global_work_size[] = { num_blocks * local_col, (size_t)OW, (size_t)(N * OD * OH) }; + size_t local_work_size[] = { local_col, 1, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_cl_argmax(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + GGML_UNUSED(src1); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_I32); + GGML_ASSERT(ggml_is_contiguous(src0)); + GGML_ASSERT(ggml_is_contiguous(dst)); + + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; + + const cl_ulong offset0 = extra0->offset + src0->view_offs; + const cl_ulong offsetd = extrad->offset + dst->view_offs; + const int ne00 = src0->ne[0]; + const int nrows = ggml_nrows(src0); + constexpr int nth = 64; + + cl_kernel kernel = backend_ctx->kernel_argmax_f32_i32; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &nrows)); + + size_t global_work_size[] = { (size_t) nth, (size_t) CEIL_DIV(nrows, 2), 1 }; + size_t local_work_size[] = { (size_t) nth, 1, 1 }; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_cl_lightning_indexer(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; + cl_kernel kernel = backend_ctx->kernel_lightning_indexer; + const ggml_tensor * src2 = dst->src[2]; + const ggml_tensor * src3 = dst->src[3]; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *) src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *) src2->extra; + ggml_tensor_extra_cl * extra3 = (ggml_tensor_extra_cl *) src3->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; + + const cl_ulong offset0 = extra0->offset + src0->view_offs; + const cl_ulong offset1 = extra1->offset + src1->view_offs; + const cl_ulong offset2 = extra2->offset + src2->view_offs; + const cl_ulong offset3 = extra3->offset + src3->view_offs; + const cl_ulong offsetd = extrad->offset + dst->view_offs; + + const int head_size = src0->ne[0]; + const int n_heads = src0->ne[1]; + const int n_tokens = src0->ne[2]; + const int n_keys = src1->ne[2]; + const int n_masks = src3->ne[3]; + // Keep the local-memory reduction for small grids or few heads. + const int use_shuffle = head_size == 128 && backend_ctx->has_khr_subgroup_shuffle && n_heads >= 32 && ggml_nelements(dst) >= 1024; + // BF16 tensors are stored as F16 on the device. + const int type_k = src1->type == GGML_TYPE_F32 ? 0 : 1; + + const cl_ulong nbq1 = src0->nb[1]; + const cl_ulong nbq2 = src0->nb[2]; + const cl_ulong nbq3 = src0->nb[3]; + const cl_ulong nbk2 = src1->nb[2]; + const cl_ulong nbk3 = src1->nb[3]; + const cl_ulong nbw1 = src2->nb[1]; + const cl_ulong nbw3 = src2->nb[3]; + const cl_ulong nbm1 = src3->nb[1]; + const cl_ulong nbm3 = src3->nb[3]; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra3->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset3)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &head_size)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &n_heads)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &n_tokens)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &n_keys)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &n_masks)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &type_k)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nbq1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nbq2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nbq3)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nbk2)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nbk3)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nbw1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nbw3)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &nbm1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &nbm3)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &use_shuffle)); + + const int keys_per_group = use_shuffle ? 16 : 4; + size_t global_work_size[] = {(size_t) ((src1->ne[2] + keys_per_group - 1)/keys_per_group)*64, (size_t) src0->ne[2], (size_t) src0->ne[3]}; + size_t local_work_size[] = {64, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_cl_top_k(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_UNUSED(src1); + + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *) src0->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *) dst->extra; + + const cl_ulong offset0 = extra0->offset + src0->view_offs; + const cl_ulong offsetd = extrad->offset + dst->view_offs; + + GGML_TENSOR_LOCALS(int, ne0, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nb0, src0, nb); + + const int k = dst->ne[0]; + cl_kernel kernel = backend_ctx->kernel_top_k_f32; + const int max_wg = backend_ctx->get_kernel_workgroup_size(kernel); + + int nth = 1; + const int target = MIN(512, MAX(32, ne00/4)); + while (2*nth <= MIN(target, max_wg)) { + nth *= 2; + } + + const size_t n_rows = ggml_nrows(src0); + const bool tiled = ne00 > 32768 && k > 0 && k <= 256 && n_rows <= 4; + const int tile_width = tiled ? 4096 : ne00; + const int n_tiles = tiled ? 1 + (ne00 - 1)/tile_width : 1; + const int n_candidates = (n_tiles - 1)*k + MIN(k, ne00 - (n_tiles - 1)*tile_width); + cl_mem candidates = nullptr; + if (tiled) { + GGML_ASSERT(n_rows <= SIZE_MAX/sizeof(cl_uint2)/(size_t) n_candidates); + backend_ctx->prealloc_top_k.allocate(backend_ctx->context, n_rows*(size_t) n_candidates*sizeof(cl_uint2)); + candidates = backend_ctx->prealloc_top_k.buffer; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 12, MAX(259, 2*nth)*sizeof(cl_uint), nullptr)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_mem), &candidates)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &tile_width)); + + size_t global_work_size[] = {(size_t) nth*n_tiles, n_rows, 1}; + size_t local_work_size[] = {(size_t) nth, 1, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + + if (tiled) { + // The global top-k is contained in the top-k of each tile. + kernel = backend_ctx->kernel_top_k_merge_f32; + const int max_wg_merge = backend_ctx->get_kernel_workgroup_size(kernel); + + int nth_merge = 1; + const int target_merge = MIN(512, MAX(32, n_candidates/4)); + while (2*nth_merge <= MIN(target_merge, max_wg_merge)) { + nth_merge *= 2; + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &candidates)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(int), &n_candidates)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(int), &k)); + CL_CHECK(clSetKernelArg(kernel, 5, MAX(259, 2*nth_merge)*sizeof(cl_uint), nullptr)); + + global_work_size[0] = nth_merge; + local_work_size[0] = nth_merge; + + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + } +} + +static void ggml_cl_top_k_mask(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + ggml_backend_opencl_context * backend_ctx = (ggml_backend_opencl_context *) backend->context; + const ggml_tensor * score = dst->src[2]; + const ggml_tensor * blocks = dst->src[3]; + const ggml_tensor * extra = dst->src[4]; + const int type = dst->type == GGML_TYPE_F16 ? 0 : 1; + cl_kernel kernel = backend_ctx->kernel_top_k_mask[type]; + + const ggml_tensor_extra_cl * extram = (const ggml_tensor_extra_cl *) src0->extra; + const ggml_tensor_extra_cl * extrak = (const ggml_tensor_extra_cl *) src1->extra; + const ggml_tensor_extra_cl * extras = score ? (const ggml_tensor_extra_cl *) score->extra : nullptr; + const ggml_tensor_extra_cl * extrab = blocks ? (const ggml_tensor_extra_cl *) blocks->extra : nullptr; + const ggml_tensor_extra_cl * extrae = extra ? (const ggml_tensor_extra_cl *) extra->extra : nullptr; + const ggml_tensor_extra_cl * extrad = (const ggml_tensor_extra_cl *) dst->extra; + + const cl_mem buffer_s = extras ? extras->data_device : nullptr; + const cl_mem buffer_b = extrab ? extrab->data_device : nullptr; + const cl_mem buffer_e = extrae ? extrae->data_device : nullptr; + + const cl_ulong offsetm = extram->offset + src0->view_offs; + const cl_ulong offsetk = extrak->offset + src1->view_offs; + const cl_ulong offsets = extras ? extras->offset + score->view_offs : 0; + const cl_ulong offsetb = extrab ? extrab->offset + blocks->view_offs : 0; + const cl_ulong offsete = extrae ? extrae->offset + extra->view_offs : 0; + const cl_ulong offsetd = extrad->offset + dst->view_offs; + + // single launch: fill == true, two launches: fill = false + // X2 benefits from a parallel fill for long single rows; mobile Adreno favors one launch. + const cl_int fill = !(backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E && + ggml_nrows(dst) == 1 && dst->ne[0] >= 65536 && ggml_is_contiguous(dst)); + + if (!fill) { + GGML_ASSERT(ggml_is_contiguous(dst)); + + cl_kernel kernel_fill = backend_ctx->kernel_top_k_mask_fill[type]; + + const cl_ulong n = ggml_nelements(dst); + const size_t nv = 16/ggml_type_size(dst->type); + const size_t nth = MIN((size_t) 256, backend_ctx->get_kernel_workgroup_size(kernel_fill)); + + CL_CHECK(clSetKernelArg(kernel_fill, 0, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel_fill, 1, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel_fill, 2, sizeof(cl_ulong), &n)); + + size_t global[] = {((n + nv - 1)/nv + nth - 1)/nth*nth}; + size_t local[] = {nth}; + backend_ctx->enqueue_ndrange_kernel(kernel_fill, 1, global, local, dst); + } + + GGML_TENSOR_LOCALS(cl_ulong, nem, src0, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbm, src0, nb); + GGML_TENSOR_LOCALS(cl_ulong, nek, src1, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbk, src1, nb); + GGML_TENSOR_LOCALS(cl_ulong, nes, score, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbs, score, nb); + GGML_TENSOR_LOCALS(cl_ulong, neb, blocks, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbb, blocks, nb); + GGML_TENSOR_LOCALS(cl_ulong, nee, extra, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbe, extra, nb); + GGML_TENSOR_LOCALS(cl_ulong, ned, dst, ne); + GGML_TENSOR_LOCALS(cl_ulong, nbd, dst, nb); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extram->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offsetm)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extrak->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offsetk)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &buffer_s)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsets)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &buffer_b)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetb)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_mem), &buffer_e)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &offsete)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nem0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nem1)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nem2)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nem3)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nbm1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nbm2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nbm3)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nek0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nbk0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nbk1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nbk2)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &nbk3)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &nes0)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(cl_ulong), &nbs0)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nbs1)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nbs2)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nbs3)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &neb0)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &neb1)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nbb0)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &nbb1)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &nee0)); + CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &nbe0)); + CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &nbe1)); + CL_CHECK(clSetKernelArg(kernel, 36, sizeof(cl_ulong), &nbe2)); + CL_CHECK(clSetKernelArg(kernel, 37, sizeof(cl_ulong), &nbe3)); + CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_ulong), &ned1)); + CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_ulong), &ned2)); + CL_CHECK(clSetKernelArg(kernel, 40, sizeof(cl_ulong), &nbd1)); + CL_CHECK(clSetKernelArg(kernel, 41, sizeof(cl_ulong), &nbd2)); + CL_CHECK(clSetKernelArg(kernel, 42, sizeof(cl_ulong), &nbd3)); + CL_CHECK(clSetKernelArg(kernel, 43, sizeof(cl_int), &fill)); + + const size_t nth = MIN((size_t) 512, backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global[] = {nth, (size_t) ggml_nrows(dst)}; + size_t local[] = {nth, 1}; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global, local, dst); +} + static void ggml_cl_argsort(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -30198,6 +37920,12 @@ bool ggml_cl_compute_forward(ggml_backend_t backend, struct ggml_tensor * tensor } func = ggml_cl_conv_2d; break; + case GGML_OP_CONV_2D_DW: + if (!any_on_device) { + return false; + } + func = ggml_cl_conv2_dw; + break; case GGML_OP_SSM_CONV: if (!any_on_device) { return false; @@ -30295,6 +38023,27 @@ bool ggml_cl_compute_forward(ggml_backend_t backend, struct ggml_tensor * tensor } func = ggml_cl_im2col; break; + case GGML_OP_IM2COL_3D: + if (!any_on_device) { + return false; + } + func = ggml_cl_im2col_3d; + break; + case GGML_OP_ARGMAX: + if (!any_on_device) { + return false; + } + func = ggml_cl_argmax; + break; + case GGML_OP_LIGHTNING_INDEXER: + func = ggml_cl_lightning_indexer; + break; + case GGML_OP_TOP_K: + func = ggml_cl_top_k; + break; + case GGML_OP_TOP_K_MASK: + func = ggml_cl_top_k_mask; + break; case GGML_OP_ARGSORT: if (!any_on_device) { return false; diff --git a/ggml/src/ggml-opencl/kernels/add_id.cl b/ggml/src/ggml-opencl/kernels/add_id.cl index e9c6d55e6a2f..e9aa5a150f35 100644 --- a/ggml/src/ggml-opencl/kernels/add_id.cl +++ b/ggml/src/ggml-opencl/kernels/add_id.cl @@ -34,6 +34,14 @@ kernel void kernel_add_id( global float * dst_row = (global float *)((global char *)dst + i1*nb1 + i2*nb2); global float * src0_row = (global float *)((global char *)src0 + i1*nb01 + i2*nb02); + + if (i11 == -1) { // skipped slot, add nothing + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + dst_row[i0] = src0_row[i0]; + } + return; + } + global float * src1_row = (global float *)((global char *)src1 + i11*nb11); for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { diff --git a/ggml/src/ggml-opencl/kernels/argmax.cl b/ggml/src/ggml-opencl/kernels/argmax.cl new file mode 100644 index 000000000000..24ed0e68bcd1 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/argmax.cl @@ -0,0 +1,55 @@ +#define ARGMAX_LANES_PER_ROW 32 +#define ARGMAX_ROWS_PER_GROUP 2 +#define ARGMAX_BLOCK_SIZE (ARGMAX_LANES_PER_ROW * ARGMAX_ROWS_PER_GROUP) + +kernel void kernel_argmax_f32_i32( + global const char * src0, + ulong offset0, + global char * dst, + ulong offsetd, + int ne00, + int nrows) { + const int local_id = get_local_id(0); + const int col = local_id % ARGMAX_LANES_PER_ROW; + const int row = get_group_id(1) * ARGMAX_ROWS_PER_GROUP + local_id / ARGMAX_LANES_PER_ROW; + + float max_value = -INFINITY; + int max_index = 0; + + if (row < nrows) { + global const float * src_row = (global const float *) (src0 + offset0) + row * ne00; + for (int i = col; i < ne00; i += ARGMAX_LANES_PER_ROW) { + const float value = src_row[i]; + if (value > max_value || (value == max_value && i > max_index)) { + max_value = value; + max_index = i; + } + } + } + + local float max_values[ARGMAX_BLOCK_SIZE]; + local int max_indices[ARGMAX_BLOCK_SIZE]; + + max_values[local_id] = max_value; + max_indices[local_id] = max_index; + + barrier(CLK_LOCAL_MEM_FENCE); + + const int row_offset = local_id / ARGMAX_LANES_PER_ROW * ARGMAX_LANES_PER_ROW; + for (int stride = ARGMAX_LANES_PER_ROW / 2; stride > 0; stride /= 2) { + if (col < stride) { + const float value = max_values[row_offset + col + stride]; + const int index = max_indices[row_offset + col + stride]; + if (value > max_values[row_offset + col] || (value == max_values[row_offset + col] && index > max_indices[row_offset + col])) { + max_values[row_offset + col] = value; + max_indices[row_offset + col] = index; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (col == 0 && row < nrows) { + global int * dst_row = (global int *) (dst + offsetd) + row; + dst_row[0] = max_indices[row_offset]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/conv2_dw.cl b/ggml/src/ggml-opencl/kernels/conv2_dw.cl new file mode 100644 index 000000000000..2a35b9c9672c --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/conv2_dw.cl @@ -0,0 +1,139 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +kernel void kernel_conv2d_dw_f32_f32( + global const float * weights, + long weights_offset, + global const float * input, + long input_offset, + global float * output, + long output_offset, + long C, + long N, + long KW, + long KH, + long W, + long H, + long OW, + long OH, + int s0, + int s1, + int p0, + int p1, + int d0, + int d1, + long nb01, + long nb03, + long nb11, + long nb12, + long nb13, + long nb1, + long nb2, + long nb3 +) { + weights = (global const float *) ((global const char *) weights + weights_offset); + input = (global const float *) ((global const char *) input + input_offset); + output = (global float *) ((global char *) output + output_offset); + + const long gid = get_global_id(0); + const long OHW = OH * OW; + const long COHW = C * OHW; + const long total = N * COHW; + if (gid >= total) { + return; + } + + const long n = gid / COHW; + const long c_rem = gid - n * COHW; + const long c = c_rem / OHW; + const long oh = (c_rem - c * OHW) / OW; + const long ow = c_rem - c * OHW - oh * OW; + + float sum = 0.0f; + for (long kh = 0; kh < KH; ++kh) { + const long ih = oh * s1 + kh * d1 - p1; + if (ih < 0 || ih >= H) { + continue; + } + for (long kw = 0; kw < KW; ++kw) { + const long iw = ow * s0 + kw * d0 - p0; + if (iw < 0 || iw >= W) { + continue; + } + const long weight_idx = kw + kh * nb01 + c * nb03; + const long input_idx = iw + ih * nb11 + c * nb12 + n * nb13; + sum += weights[weight_idx] * input[input_idx]; + } + } + + const long output_idx = ow + oh * nb1 + c * nb2 + n * nb3; + output[output_idx] = sum; +} + +kernel void kernel_conv2d_dwf16_f32( + global const half * weights, + long weights_offset, + global const float * input, + long input_offset, + global float * output, + long output_offset, + long C, + long N, + long KW, + long KH, + long W, + long H, + long OW, + long OH, + int s0, + int s1, + int p0, + int p1, + int d0, + int d1, + long nb01, + long nb03, + long nb11, + long nb12, + long nb13, + long nb1, + long nb2, + long nb3 +) { + weights = (global const half *) ((global const char *) weights + weights_offset); + input = (global const float *) ((global const char *) input + input_offset); + output = (global float *) ((global char *) output + output_offset); + + const long gid = get_global_id(0); + const long OHW = OH * OW; + const long COHW = C * OHW; + const long total = N * COHW; + if (gid >= total) { + return; + } + + const long n = gid / COHW; + const long c_rem = gid - n * COHW; + const long c = c_rem / OHW; + const long oh = (c_rem - c * OHW) / OW; + const long ow = c_rem - c * OHW - oh * OW; + + float sum = 0.0f; + for (long kh = 0; kh < KH; ++kh) { + const long ih = oh * s1 + kh * d1 - p1; + if (ih < 0 || ih >= H) { + continue; + } + for (long kw = 0; kw < KW; ++kw) { + const long iw = ow * s0 + kw * d0 - p0; + if (iw < 0 || iw >= W) { + continue; + } + const long weight_idx = kw + kh * nb01 + c * nb03; + const long input_idx = iw + ih * nb11 + c * nb12 + n * nb13; + sum += (float) weights[weight_idx] * input[input_idx]; + } + } + + const long output_idx = ow + oh * nb1 + c * nb2 + n * nb3; + output[output_idx] = sum; +} diff --git a/ggml/src/ggml-opencl/kernels/cpy.cl b/ggml/src/ggml-opencl/kernels/cpy.cl index 11d7a57c17de..18400d37f1d5 100644 --- a/ggml/src/ggml-opencl/kernels/cpy.cl +++ b/ggml/src/ggml-opencl/kernels/cpy.cl @@ -313,3 +313,88 @@ kernel void kernel_cpy_f32_f32_flat( } } } + +kernel void kernel_cpy_i32_f32( + global int * src0, + ulong offset0, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = (global int *) ((global char *) src0 + offset0); + dst = (global float *) ((global char *) dst + offsetd); + + const ulong i01 = get_group_id(0); + const ulong i02 = get_group_id(1); + const ulong i03 = get_group_id(2); + + for (ulong i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { + const ulong n = ((i03 * ne02 + i02) * ne01 + i01) * ne00 + i00; + const ulong i0 = n % ne0; + const ulong i1 = n / ne0 % ne1; + const ulong i2 = n / ne0 / ne1 % ne2; + const ulong i3 = n / ne0 / ne1 / ne2; + + global const int * src = (global const int *) ((global char *) src0 + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); + global float * out = (global float *) ((global char *) dst + i0*nb0 + i1*nb1 + i2*nb2 + i3*nb3); + out[0] = convert_float(src[0]); + } +} + + +kernel void kernel_cpy_f32_i32( + global float * src0, + ulong offset0, + global int * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = (global float *) ((global char *) src0 + offset0); + dst = (global int *) ((global char *) dst + offsetd); + + const ulong i01 = get_group_id(0); + const ulong i02 = get_group_id(1); + const ulong i03 = get_group_id(2); + + for (ulong i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { + const ulong n = ((i03 * ne02 + i02) * ne01 + i01) * ne00 + i00; + const ulong i0 = n % ne0; + const ulong i1 = n / ne0 % ne1; + const ulong i2 = n / ne0 / ne1 % ne2; + const ulong i3 = n / ne0 / ne1 / ne2; + + global const float * src = (global const float *) ((global char *) src0 + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); + global int * out = (global int *) ((global char *) dst + i0*nb0 + i1*nb1 + i2*nb2 + i3*nb3); + out[0] = convert_int_rtz(src[0]); + } +} diff --git a/ggml/src/ggml-opencl/kernels/cvt.cl b/ggml/src/ggml-opencl/kernels/cvt.cl index acc8f980763f..143f7c24d1df 100644 --- a/ggml/src/ggml-opencl/kernels/cvt.cl +++ b/ggml/src/ggml-opencl/kernels/cvt.cl @@ -2661,3 +2661,625 @@ kernel void kernel_moe_expand_scale_q5_K( dst_min[((long)e*ne01 + row)*nblk32 + sub] = (half)(dm * (float)mn); } } + +struct block_q2_K { + uint8_t scales[QK_K/16]; // low nibble scale, high nibble min, one per 16 weights + uint8_t qs[QK_K/4]; // quants, 2 bits each + half d; // super-block scale for the quantized scales + half dmin; // super-block scale for the quantized mins +}; + +kernel void kernel_convert_block_q2_K( + global struct block_q2_K * src0, + global uchar * dst_qs, + global uchar * dst_sc, + global half * dst_dm, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q2_K * b = src0 + i; + for (int j = 0; j < 64; ++j) { + dst_qs[64*i + j] = b->qs[j]; + } + for (int j = 0; j < 16; ++j) { + dst_sc[16*i + j] = b->scales[j]; + } + dst_dm[2*i + 0] = b->d; + dst_dm[2*i + 1] = b->dmin; +} + +kernel void kernel_restore_block_q2_K( + global uchar * src_qs, + global uchar * src_sc, + global half * src_dm, + global struct block_q2_K * dst, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q2_K * b = dst + i; + for (int j = 0; j < 64; ++j) { + b->qs[j] = src_qs[64*i + j]; + } + for (int j = 0; j < 16; ++j) { + b->scales[j] = src_sc[16*i + j]; + } + b->d = src_dm[2*i + 0]; + b->dmin = src_dm[2*i + 1]; +} + +kernel void kernel_convert_block_q2_k_noshuffle( + global struct block_q2_K * src0, + global uchar * dst_qs, // QK_K/4 per block + global uchar * dst_sc, // QK_K/16 per block + global half * dst_dm, // 2 per block (d, dmin) + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q2_K * b = (global struct block_q2_K *) src0 + i; + + dst_dm[2*i + 0] = b->d; + dst_dm[2*i + 1] = b->dmin; + + for (int j = 0; j < QK_K/16; ++j) { dst_sc[(QK_K/16) * i + j] = b->scales[j]; } + + for (int g = 0; g < QK_K/4; ++g) { + uint pk = 0; + for (int t = 0; t < 4; ++t) { + const int e = 4*g + t; + const int sb = e >> 5; + const int ee = e & 31; + pk |= (uint)(((b->qs[32*(sb >> 2) + ee] >> (2*(sb & 3))) & 3) << (2*t)); + } + dst_qs[(QK_K/4) * i + g] = (uchar)pk; + } +} + +kernel void kernel_restore_block_q2_k_noshuffle( + global uchar * src_qs, + global uchar * src_sc, + global half * src_dm, + global struct block_q2_K * dst, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q2_K * b = (global struct block_q2_K *) dst + i; + + b->d = src_dm[2*i + 0]; + b->dmin = src_dm[2*i + 1]; + + for (int j = 0; j < QK_K/16; ++j) { b->scales[j] = src_sc[(QK_K/16) * i + j]; } + + for (int n2 = 0; n2 < 2; ++n2) { + for (int ee = 0; ee < 32; ++ee) { + uint v = 0; + for (int j = 0; j < 4; ++j) { + const int sb = 4*n2 + j; + const int e = 32*sb + ee; + v |= ((uint)(src_qs[(QK_K/4) * i + (e >> 2)] >> (2*(e & 3))) & 3u) << (2*j); + } + b->qs[32*n2 + ee] = (uchar)v; + } + } +} + +struct block_q3_K { + uchar hmask[QK_K/8]; + uchar qs[QK_K/4]; + uchar scales[12]; + half d; +}; + +kernel void kernel_convert_block_q3_K( + global struct block_q3_K * src0, + global uchar * dst_qs, + global uchar * dst_hm, + global uchar * dst_sc, + global half * dst_d, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q3_K * b = src0 + i; + for (int j = 0; j < 64; ++j) { + dst_qs[64*i + j] = b->qs[j]; + } + for (int j = 0; j < 32; ++j) { + dst_hm[32*i + j] = b->hmask[j]; + } + for (int j = 0; j < 12; ++j) { + dst_sc[12*i + j] = b->scales[j]; + } + dst_d[i] = b->d; +} + +kernel void kernel_restore_block_q3_K( + global uchar * src_qs, + global uchar * src_hm, + global uchar * src_sc, + global half * src_d, + global struct block_q3_K * dst, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q3_K * b = dst + i; + for (int j = 0; j < 64; ++j) { + b->qs[j] = src_qs[64*i + j]; + } + for (int j = 0; j < 32; ++j) { + b->hmask[j] = src_hm[32*i + j]; + } + for (int j = 0; j < 12; ++j) { + b->scales[j] = src_sc[12*i + j]; + } + b->d = src_d[i]; +} + +kernel void kernel_convert_block_q3_k_noshuffle( + global struct block_q3_K * src0, + global uchar * dst_qs, // QK_K/4 per block + global uchar * dst_hm, // QK_K/8 per block + global uint * dst_sc, // 3 per block + global half * dst_d, // 1 + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q3_K * b = (global struct block_q3_K *) src0 + i; + + dst_d[i] = b->d; + + for (int w = 0; w < 3; ++w) { + global const uchar * p = b->scales + 4*w; + dst_sc[3*i + w] = (uint)p[0] | ((uint)p[1] << 8) | ((uint)p[2] << 16) | ((uint)p[3] << 24); + } + + for (int g = 0; g < QK_K/4; ++g) { + uint pk = 0; + for (int t = 0; t < 4; ++t) { + const int e = 4*g + t; + const int sb = e >> 5; + const int ee = e & 31; + pk |= (uint)(((b->qs[32*(sb >> 2) + ee] >> (2*(sb & 3))) & 3) << (2*t)); + } + dst_qs[(QK_K/4) * i + g] = (uchar)pk; + } + + // two groups per hmask byte, so this loop owns the byte and cannot race + for (int t = 0; t < QK_K/8; ++t) { + uint v = 0; + for (int s = 0; s < 2; ++s) { + const int g = 2*t + s; + for (int u = 0; u < 4; ++u) { + const int e = 4*g + u; + const int sb = e >> 5; + const int ee = e & 31; + v |= (uint)(((b->hmask[ee] >> sb) & 1) << (4*s + u)); + } + } + dst_hm[(QK_K/8) * i + t] = (uchar)v; + } +} + +kernel void kernel_restore_block_q3_k_noshuffle( + global uchar * src_qs, + global uchar * src_hm, + global uint * src_sc, + global half * src_d, + global struct block_q3_K * dst, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_q3_K * b = (global struct block_q3_K *) dst + i; + + b->d = src_d[i]; + + for (int w = 0; w < 3; ++w) { + const uint x = src_sc[3*i + w]; + global uchar * p = b->scales + 4*w; + p[0] = (uchar)( x & 0xFF); + p[1] = (uchar)((x >> 8) & 0xFF); + p[2] = (uchar)((x >> 16) & 0xFF); + p[3] = (uchar)((x >> 24) & 0xFF); + } + + for (int n2 = 0; n2 < 2; ++n2) { + for (int ee = 0; ee < 32; ++ee) { + uint v = 0; + for (int j = 0; j < 4; ++j) { + const int sb = 4*n2 + j; + const int e = 32*sb + ee; + v |= ((uint)(src_qs[(QK_K/4) * i + (e >> 2)] >> (2*(e & 3))) & 3u) << (2*j); + } + b->qs[32*n2 + ee] = (uchar)v; + } + } + + for (int ee = 0; ee < 32; ++ee) { + uint v = 0; + for (int sb = 0; sb < 8; ++sb) { + const int e = 32*sb + ee; + const int g = e >> 2; + v |= ((uint)(src_hm[(QK_K/8) * i + (g >> 1)] >> (4*(g & 1) + (e & 3))) & 1u) << sb; + } + b->hmask[ee] = (uchar)v; + } +} + +struct block_iq2_s { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar scales[QK_K/32]; +}; + +kernel void kernel_convert_block_iq2_s( + global struct block_iq2_s * src0, + global uchar * dst_qs, // QK_K/8 per block + global uchar * dst_sg, // QK_K/8 + global uchar * dst_qh, // QK_K/32 + global uchar * dst_sc, // QK_K/32 + global half * dst_d, // 1 + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_iq2_s * b = src0 + i; + + dst_d[i] = b->d; + for (int j = 0; j < QK_K/8; ++j) { dst_qs[(QK_K/8) * i + j] = b->qs[j]; } + for (int j = 0; j < QK_K/8; ++j) { dst_sg[(QK_K/8) * i + j] = b->qs[QK_K/8 + j]; } + for (int j = 0; j < QK_K/32; ++j) { dst_qh[(QK_K/32) * i + j] = b->qh[j]; } + for (int j = 0; j < QK_K/32; ++j) { dst_sc[(QK_K/32) * i + j] = b->scales[j]; } +} + +kernel void kernel_restore_block_iq2_s( + global uchar * src_qs, + global uchar * src_sg, + global uchar * src_qh, + global uchar * src_sc, + global half * src_d, + global struct block_iq2_s * dst, + ulong n_blk +) { + const ulong i = get_global_id(0); + if (i >= n_blk) { + return; + } + global struct block_iq2_s * b = dst + i; + + b->d = src_d[i]; + for (int j = 0; j < QK_K/8; ++j) { b->qs[j] = src_qs[(QK_K/8) * i + j]; } + for (int j = 0; j < QK_K/8; ++j) { b->qs[QK_K/8 + j] = src_sg[(QK_K/8) * i + j]; } + for (int j = 0; j < QK_K/32; ++j) { b->qh[j] = src_qh[(QK_K/32) * i + j]; } + for (int j = 0; j < QK_K/32; ++j) { b->scales[j] = src_sc[(QK_K/32) * i + j]; } +} + +struct block_iq2_xs { + half d; + ushort qs[QK_K/8]; + uchar scales[QK_K/32]; +}; + +kernel void kernel_convert_block_iq2_xs( + global struct block_iq2_xs * src0, + global ushort * dst_qs, + global uchar * dst_sc, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 32; ++j) { dst_qs[32*i + j] = src0[i].qs[j]; } + for (int j = 0; j < 8; ++j) { dst_sc[8*i + j] = src0[i].scales[j]; } +} + +kernel void kernel_restore_block_iq2_xs( + global ushort * src_qs, + global uchar * src_sc, + global half * src_d, + global struct block_iq2_xs * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 32; ++j) { dst[i].qs[j] = src_qs[32*i + j]; } + for (int j = 0; j < 8; ++j) { dst[i].scales[j] = src_sc[8*i + j]; } +} + +struct block_iq2_xxs { + half d; + ushort qs[QK_K/8]; +}; + +kernel void kernel_convert_block_iq2_xxs( + global struct block_iq2_xxs * src0, + global uchar * dst_qs, + global uint * dst_sas, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 8; ++j) { + global ushort * q = src0[i].qs + 4*j; + uint indices = (uint)q[0] | ((uint)q[1] << 16); + vstore4(as_uchar4(indices), 8*i + j, dst_qs); + dst_sas[8*i + j] = (uint)q[2] | ((uint)q[3] << 16); + } +} + +kernel void kernel_restore_block_iq2_xxs( + global uchar * src_qs, + global uint * src_sas, + global half * src_d, + global struct block_iq2_xxs * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 8; ++j) { + global ushort * q = dst[i].qs + 4*j; + uint indices = as_uint(vload4(8*i + j, src_qs)); + uint sas = src_sas[8*i + j]; + q[0] = (ushort)indices; + q[1] = (ushort)(indices >> 16); + q[2] = (ushort)sas; + q[3] = (ushort)(sas >> 16); + } +} + +struct block_q2_0 { + half d; + uchar qs[16]; +}; + +kernel void kernel_convert_block_q2_0( + global struct block_q2_0 * src0, + global uchar * dst_qs, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 16; ++j) { + dst_qs[16*i + j] = src0[i].qs[j]; + } +} + +kernel void kernel_restore_block_q2_0( + global uchar * src_qs, + global half * src_d, + global struct block_q2_0 * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 16; ++j) { + dst[i].qs[j] = src_qs[16*i + j]; + } +} + +struct block_iq1_s { + half d; + uchar qs[QK_K/8]; + ushort qh[QK_K/32]; +}; + +kernel void kernel_convert_block_iq1_s( + global struct block_iq1_s * src0, + global uchar * dst_qs, + global ushort * dst_qh, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 32; ++j) { + dst_qs[32*i + j] = src0[i].qs[j]; + } + for (int j = 0; j < 8; ++j) { + dst_qh[8*i + j] = src0[i].qh[j]; + } +} + +kernel void kernel_restore_block_iq1_s( + global uchar * src_qs, + global ushort * src_qh, + global half * src_d, + global struct block_iq1_s * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 32; ++j) { + dst[i].qs[j] = src_qs[32*i + j]; + } + for (int j = 0; j < 8; ++j) { + dst[i].qh[j] = src_qh[8*i + j]; + } +} + +struct block_iq1_m { + uchar qs[QK_K/8]; + uchar qh[QK_K/16]; + uchar scales[QK_K/32]; +}; + +kernel void kernel_convert_block_iq1_m( + global struct block_iq1_m * src0, + global uchar * dst_qs, + global uchar * dst_qh, + global ushort * dst_sc, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + for (int j = 0; j < 32; ++j) { + dst_qs[32*i + j] = src0[i].qs[j]; + } + for (int j = 0; j < 16; ++j) { + dst_qh[16*i + j] = src0[i].qh[j]; + } + for (int j = 0; j < 4; ++j) { + dst_sc[4*i + j] = (ushort)src0[i].scales[2*j] | ((ushort)src0[i].scales[2*j + 1] << 8); + } +} + +kernel void kernel_restore_block_iq1_m( + global uchar * src_qs, + global uchar * src_qh, + global ushort * src_sc, + global struct block_iq1_m * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + for (int j = 0; j < 32; ++j) { + dst[i].qs[j] = src_qs[32*i + j]; + } + for (int j = 0; j < 16; ++j) { + dst[i].qh[j] = src_qh[16*i + j]; + } + for (int j = 0; j < 4; ++j) { + ushort sc = src_sc[4*i + j]; + dst[i].scales[2*j] = (uchar)sc; + dst[i].scales[2*j + 1] = (uchar)(sc >> 8); + } +} + +struct block_iq3_s { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar signs[QK_K/8]; + uchar scales[QK_K/64]; +}; + +kernel void kernel_convert_block_iq3_s( + global struct block_iq3_s * src0, + global uchar * dst_qs, + global uchar * dst_sg, + global uchar * dst_qh, + global uchar * dst_sc, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 64; ++j) { + dst_qs[64*i + j] = src0[i].qs[j]; + } + for (int j = 0; j < 32; ++j) { + dst_sg[32*i + j] = src0[i].signs[j]; + } + for (int j = 0; j < 8; ++j) { + dst_qh[8*i + j] = src0[i].qh[j]; + } + for (int j = 0; j < 4; ++j) { + dst_sc[4*i + j] = src0[i].scales[j]; + } +} + +kernel void kernel_restore_block_iq3_s( + global uchar * src_qs, + global uchar * src_sg, + global uchar * src_qh, + global uchar * src_sc, + global half * src_d, + global struct block_iq3_s * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 64; ++j) { + dst[i].qs[j] = src_qs[64*i + j]; + } + for (int j = 0; j < 32; ++j) { + dst[i].signs[j] = src_sg[32*i + j]; + } + for (int j = 0; j < 8; ++j) { + dst[i].qh[j] = src_qh[8*i + j]; + } + for (int j = 0; j < 4; ++j) { + dst[i].scales[j] = src_sc[4*i + j]; + } +} + +struct block_iq3_xxs { + half d; + uchar qs[3*QK_K/8]; +}; + +kernel void kernel_convert_block_iq3_xxs( + global struct block_iq3_xxs * src0, + global uchar * dst_qs, + global uint * dst_sas, + global half * dst_d, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst_d[i] = src0[i].d; + for (int j = 0; j < 64; ++j) { + dst_qs[64*i + j] = src0[i].qs[j]; + } + for (int j = 0; j < 8; ++j) { + global ushort * q = (global ushort *)(src0[i].qs + 64 + 4*j); + dst_sas[8*i + j] = (uint)q[0] | ((uint)q[1] << 16); + } +} + +kernel void kernel_restore_block_iq3_xxs( + global uchar * src_qs, + global uint * src_sas, + global half * src_d, + global struct block_iq3_xxs * dst, + ulong n_blocks +) { + const ulong i = get_global_id(0); + if (i >= n_blocks) { return; } + dst[i].d = src_d[i]; + for (int j = 0; j < 64; ++j) { + dst[i].qs[j] = src_qs[64*i + j]; + } + for (int j = 0; j < 8; ++j) { + global ushort * q = (global ushort *)(dst[i].qs + 64 + 4*j); + uint sas = src_sas[8*i + j]; + q[0] = (ushort)sas; + q[1] = (ushort)(sas >> 16); + } +} diff --git a/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl b/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl index f9797d346005..cb6fd89308f4 100644 --- a/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl +++ b/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl @@ -175,6 +175,12 @@ __kernel void flash_attn_f16( ACC_TYPE s1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; ACC_TYPE s2 = (dot_acc2.s0 + dot_acc2.s1 + dot_acc2.s2 + dot_acc2.s3) * scale; ACC_TYPE s3 = (dot_acc3.s0 + dot_acc3.s1 + dot_acc3.s2 + dot_acc3.s3) * scale; + if (logit_softcap > 0.0f) { + s0 = logit_softcap * tanh(s0 / logit_softcap); + s1 = logit_softcap * tanh(s1 / logit_softcap); + s2 = logit_softcap * tanh(s2 / logit_softcap); + s3 = logit_softcap * tanh(s3 / logit_softcap); + } if (is_causal) { const int causal_limit = n_kv - n_q + my_query_row; @@ -196,13 +202,6 @@ __kernel void flash_attn_f16( if (k_row3 < n_kv) s3 += slope * (ACC_TYPE)mask_ptr[k_row3]; } - if (logit_softcap > 0.0f) { - s0 = logit_softcap * tanh(s0 / logit_softcap); - s1 = logit_softcap * tanh(s1 / logit_softcap); - s2 = logit_softcap * tanh(s2 / logit_softcap); - s3 = logit_softcap * tanh(s3 / logit_softcap); - } - const ACC_TYPE m_new = max(m_i, max(max(s0, s1), max(s2, s3))); const ACC_TYPE scale_prev = native_exp(m_i - m_new); const ACC_TYPE p0 = native_exp(s0 - m_new); @@ -331,13 +330,13 @@ __kernel void flash_attn_f16_q1( dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } m_i = max(m_i, score); } @@ -367,13 +366,13 @@ __kernel void flash_attn_f16_q1( dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE p = exp(score - m_final); l_i += p; FA_UNROLL diff --git a/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl b/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl index 5911524e156c..15b9cf30a740 100644 --- a/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl +++ b/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl @@ -176,6 +176,12 @@ __kernel void flash_attn_f32( ACC_TYPE s1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; ACC_TYPE s2 = (dot_acc2.s0 + dot_acc2.s1 + dot_acc2.s2 + dot_acc2.s3) * scale; ACC_TYPE s3 = (dot_acc3.s0 + dot_acc3.s1 + dot_acc3.s2 + dot_acc3.s3) * scale; + if (logit_softcap > 0.0f) { + s0 = logit_softcap * tanh(s0 / logit_softcap); + s1 = logit_softcap * tanh(s1 / logit_softcap); + s2 = logit_softcap * tanh(s2 / logit_softcap); + s3 = logit_softcap * tanh(s3 / logit_softcap); + } if (is_causal) { const int causal_limit = n_kv - n_q + my_query_row; @@ -197,13 +203,6 @@ __kernel void flash_attn_f32( if (k_row3 < n_kv) s3 += slope * (ACC_TYPE)mask_ptr[k_row3]; } - if (logit_softcap > 0.0f) { - s0 = logit_softcap * tanh(s0 / logit_softcap); - s1 = logit_softcap * tanh(s1 / logit_softcap); - s2 = logit_softcap * tanh(s2 / logit_softcap); - s3 = logit_softcap * tanh(s3 / logit_softcap); - } - const ACC_TYPE m_new = max(m_i, max(max(s0, s1), max(s2, s3))); const ACC_TYPE scale_prev = native_exp(m_i - m_new); const ACC_TYPE p0 = native_exp(s0 - m_new); @@ -332,13 +331,13 @@ __kernel void flash_attn_f32_q1( dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } m_i = max(m_i, score); } @@ -368,13 +367,13 @@ __kernel void flash_attn_f32_q1( dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE p = exp(score - m_final); l_i += p; FA_UNROLL diff --git a/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl b/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl index 27553c729af8..d1cc1480105d 100644 --- a/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl +++ b/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl @@ -336,6 +336,10 @@ __kernel void FA_TILE_NAME( ACC_TYPE score0 = partial0 * scale; ACC_TYPE score1 = partial1 * scale; + if (logit_softcap > 0.0f) { + score0 = logit_softcap * tanh(score0 / logit_softcap); + score1 = logit_softcap * tanh(score1 / logit_softcap); + } if (!query_valid) { score0 = FA_M_INIT; score1 = FA_M_INIT; } if (is_causal) { @@ -359,11 +363,6 @@ __kernel void FA_TILE_NAME( } } - if (logit_softcap > 0.0f) { - score0 = logit_softcap * tanh(score0 / logit_softcap); - score1 = logit_softcap * tanh(score1 / logit_softcap); - } - const ACC_TYPE m_new = max(m_i, max(score0, score1)); // Whole tile masked (m_new == FA_M_INIT): force the exp() args // far negative so the tile contributes 0, not exp(0)=1. @@ -408,6 +407,9 @@ __kernel void FA_TILE_NAME( score += local_partial[j][q_lane * N_SPLIT + s]; } score *= scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (is_causal && k_row > (n_kv - n_q + my_query_row)) score = FA_M_INIT; if (k_row >= n_kv) score = FA_M_INIT; @@ -424,10 +426,6 @@ __kernel void FA_TILE_NAME( } } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } - m_new = max(m_new, score); local_p[q_lane][j] = score; } @@ -502,6 +500,12 @@ __kernel void FA_TILE_NAME( ACC_TYPE s1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; ACC_TYPE s2 = (dot_acc2.s0 + dot_acc2.s1 + dot_acc2.s2 + dot_acc2.s3) * scale; ACC_TYPE s3 = (dot_acc3.s0 + dot_acc3.s1 + dot_acc3.s2 + dot_acc3.s3) * scale; + if (logit_softcap > 0.0f) { + s0 = logit_softcap * tanh(s0 / logit_softcap); + s1 = logit_softcap * tanh(s1 / logit_softcap); + s2 = logit_softcap * tanh(s2 / logit_softcap); + s3 = logit_softcap * tanh(s3 / logit_softcap); + } if (is_causal) { const int causal_limit = n_kv - n_q + my_query_row; @@ -531,13 +535,6 @@ __kernel void FA_TILE_NAME( } } - if (logit_softcap > 0.0f) { - s0 = logit_softcap * tanh(s0 / logit_softcap); - s1 = logit_softcap * tanh(s1 / logit_softcap); - s2 = logit_softcap * tanh(s2 / logit_softcap); - s3 = logit_softcap * tanh(s3 / logit_softcap); - } - const ACC_TYPE m_new = max(m_i, max(max(s0, s1), max(s2, s3))); // Whole tile masked (m_new == FA_M_INIT): force the exp() args // far negative so the tile contributes 0, not exp(0)=1. @@ -748,13 +745,13 @@ __kernel void flash_attn_f32_f16_q1( dot_acc = mad(q_shared[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } m_i = max(m_i, score); } @@ -776,13 +773,13 @@ __kernel void flash_attn_f32_f16_q1( dot_acc = mad(q_shared[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE p = exp(score - m_final); l_i += p; FA_UNROLL @@ -1122,13 +1119,13 @@ __kernel void flash_attn_f32_f16_q1_local_tile( if (tid == 0) { float s = red[0] * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base; s += slope * (float) mask_ptr[kv_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score_shared = s; } barrier(CLK_LOCAL_MEM_FENCE); @@ -1323,13 +1320,13 @@ __kernel void flash_attn_f32_f16_q1_local_mq_split( contrib += q_shared[h * DK + d] * (float) k_tile[j * DK + d]; } float s = sub_group_reduce_add(contrib) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (float) mask_ptr[kv_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } @@ -1510,13 +1507,13 @@ __kernel void flash_attn_f32_f16_q1_vec_mq( for (int h = 0; h < MQ_GQA; ++h) { const ACC_TYPE dot_partial = dot4[h].s0 + dot4[h].s1 + dot4[h].s2 + dot4[h].s3; ACC_TYPE s = sub_group_reduce_add(dot_partial) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } @@ -2448,13 +2445,13 @@ __kernel void flash_attn_f32_f16_q1_vec_mq_split_k_img( for (int h = 0; h < MQ_GQA; ++h) { const ACC_TYPE dot_partial = dot4[h].s0 + dot4[h].s1 + dot4[h].s2 + dot4[h].s3; ACC_TYPE s = sub_group_reduce_add(dot_partial) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } @@ -2633,13 +2630,13 @@ __kernel void flash_attn_f32_f16_q1_split( dot_acc = mad(q_shared[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) (mask_base); score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } m_i = max(m_i, score); } @@ -2662,13 +2659,13 @@ __kernel void flash_attn_f32_f16_q1_split( dot_acc = mad(q_shared[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); } ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) (mask_base); score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE p = exp(score - m_c); l_i += p; #pragma unroll diff --git a/ggml/src/ggml-opencl/kernels/flash_attn_f32_q4_0.cl b/ggml/src/ggml-opencl/kernels/flash_attn_f32_q4_0.cl index 48adba4f725b..3e75dc942bfb 100644 --- a/ggml/src/ggml-opencl/kernels/flash_attn_f32_q4_0.cl +++ b/ggml/src/ggml-opencl/kernels/flash_attn_f32_q4_0.cl @@ -287,14 +287,14 @@ __kernel void flash_attn_f32_q4_0_q1( #endif } score *= scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } // Online softmax step. const ACC_TYPE m_new = max(m_i, score); @@ -554,14 +554,14 @@ __kernel void flash_attn_f32_q4_0_q1_vec( ACC_TYPE dot_partial = dot4.s0 + dot4.s1 + dot4.s2 + dot4.s3; ACC_TYPE score = sub_group_reduce_add(dot_partial) * scale; #endif + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base; score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE m_new = max(m_i, score); const ACC_TYPE scale_prev = native_exp(m_i - m_new); @@ -745,13 +745,13 @@ __kernel void flash_attn_f32_q4_0_q1_split( #endif } score *= scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) (mask_base); score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } // Online softmax step. const ACC_TYPE m_new = max(m_i, score); @@ -1037,13 +1037,13 @@ __kernel void flash_attn_f32_q4_0_q1_vec_mq_split( #pragma unroll for (int h = 0; h < MQ_GQA; ++h) { ACC_TYPE s = sub_group_reduce_add(lane_contrib[h]) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } #else @@ -1067,13 +1067,13 @@ __kernel void flash_attn_f32_q4_0_q1_vec_mq_split( for (int h = 0; h < MQ_GQA; ++h) { const ACC_TYPE dot_partial = dot4[h].s0 + dot4[h].s1 + dot4[h].s2 + dot4[h].s3; ACC_TYPE s = sub_group_reduce_add(dot_partial) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } #endif @@ -1385,13 +1385,13 @@ __kernel void flash_attn_f32_q4_0_q1_vec_mq_split_c8( s += sub_group_shuffle_xor(s, step); } s *= scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_safe]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = valid ? s : FA_M_INIT; } @@ -1852,9 +1852,15 @@ __kernel void flash_attn_f32_q4_0( s2 = sub_group_shuffle(s2, tri_base + 0) + sub_group_shuffle(s2, tri_base + 1) + sub_group_shuffle(s2, tri_base + 2); s3 = sub_group_shuffle(s3, tri_base + 0) + sub_group_shuffle(s3, tri_base + 1) + sub_group_shuffle(s3, tri_base + 2); #endif - if (!query_valid) { s0 = FA_M_INIT; s1 = FA_M_INIT; s2 = FA_M_INIT; s3 = FA_M_INIT; } #endif s0 *= scale; s1 *= scale; s2 *= scale; s3 *= scale; + if (logit_softcap > 0.0f) { + s0 = logit_softcap * tanh(s0 / logit_softcap); + s1 = logit_softcap * tanh(s1 / logit_softcap); + s2 = logit_softcap * tanh(s2 / logit_softcap); + s3 = logit_softcap * tanh(s3 / logit_softcap); + } + if (!query_valid) { s0 = FA_M_INIT; s1 = FA_M_INIT; s2 = FA_M_INIT; s3 = FA_M_INIT; } if (is_causal) { const int causal_limit = n_kv - n_q + my_query_row; @@ -1876,12 +1882,6 @@ __kernel void flash_attn_f32_q4_0( if (k_row2 < n_kv) s2 += slope * (ACC_TYPE) mask_ptr[k_row2]; if (k_row3 < n_kv) s3 += slope * (ACC_TYPE) mask_ptr[k_row3]; } - if (logit_softcap > 0.0f) { - s0 = logit_softcap * tanh(s0 / logit_softcap); - s1 = logit_softcap * tanh(s1 / logit_softcap); - s2 = logit_softcap * tanh(s2 / logit_softcap); - s3 = logit_softcap * tanh(s3 / logit_softcap); - } const ACC_TYPE m_new = max(m_i, max(max(s0, s1), max(s2, s3))); // Whole tile masked (m_new == FA_M_INIT): force the exp() args diff --git a/ggml/src/ggml-opencl/kernels/flash_attn_f32_q8_0.cl b/ggml/src/ggml-opencl/kernels/flash_attn_f32_q8_0.cl index f50912d21101..75d0d9b0a4df 100644 --- a/ggml/src/ggml-opencl/kernels/flash_attn_f32_q8_0.cl +++ b/ggml/src/ggml-opencl/kernels/flash_attn_f32_q8_0.cl @@ -232,14 +232,14 @@ __kernel void flash_attn_f32_q8_0_q1( #endif } score *= scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); score += slope * (ACC_TYPE)mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } // Online softmax step. const ACC_TYPE m_new = max(m_i, score); @@ -437,14 +437,14 @@ __kernel void flash_attn_f32_q8_0_q1_vec( } ACC_TYPE dot_partial = dot4.s0 + dot4.s1 + dot4.s2 + dot4.s3; ACC_TYPE score = sub_group_reduce_add(dot_partial) * scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base; score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } const ACC_TYPE m_new = max(m_i, score); const ACC_TYPE scale_prev = native_exp(m_i - m_new); @@ -627,13 +627,13 @@ __kernel void flash_attn_f32_q8_0_q1_split( #endif } score *= scale; + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } if (mask_base != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) (mask_base); score += slope * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - score = logit_softcap * tanh(score / logit_softcap); - } // Online softmax step. const ACC_TYPE m_new = max(m_i, score); @@ -882,13 +882,13 @@ __kernel void flash_attn_f32_q8_0_q1_vec_mq_split( for (int h = 0; h < MQ_GQA; ++h) { const ACC_TYPE dot_partial = dot4[h].s0 + dot4[h].s1 + dot4[h].s2 + dot4[h].s3; ACC_TYPE s = sub_group_reduce_add(dot_partial) * scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_idx]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = s; } @@ -1151,13 +1151,13 @@ __kernel void flash_attn_f32_q8_0_q1_vec_mq_split_c8( s += sub_group_shuffle_xor(s, step); } s *= scale; + if (logit_softcap > 0.0f) { + s = logit_softcap * tanh(s / logit_softcap); + } if (mask_base[h] != NULL) { const global MASK_DATA_TYPE * mask_ptr = (const global MASK_DATA_TYPE *) mask_base[h]; s += slope[h] * (ACC_TYPE) mask_ptr[k_safe]; } - if (logit_softcap > 0.0f) { - s = logit_softcap * tanh(s / logit_softcap); - } score[h] = valid ? s : FA_M_INIT; } @@ -1652,9 +1652,15 @@ __kernel void flash_attn_f32_q8_0( s2 = sub_group_shuffle(s2, tri_base + 0) + sub_group_shuffle(s2, tri_base + 1) + sub_group_shuffle(s2, tri_base + 2); s3 = sub_group_shuffle(s3, tri_base + 0) + sub_group_shuffle(s3, tri_base + 1) + sub_group_shuffle(s3, tri_base + 2); #endif - if (!query_valid) { s0 = FA_M_INIT; s1 = FA_M_INIT; s2 = FA_M_INIT; s3 = FA_M_INIT; } #endif s0 *= scale; s1 *= scale; s2 *= scale; s3 *= scale; + if (logit_softcap > 0.0f) { + s0 = logit_softcap * tanh(s0 / logit_softcap); + s1 = logit_softcap * tanh(s1 / logit_softcap); + s2 = logit_softcap * tanh(s2 / logit_softcap); + s3 = logit_softcap * tanh(s3 / logit_softcap); + } + if (!query_valid) { s0 = FA_M_INIT; s1 = FA_M_INIT; s2 = FA_M_INIT; s3 = FA_M_INIT; } if (is_causal) { const int causal_limit = n_kv - n_q + my_query_row; @@ -1676,12 +1682,6 @@ __kernel void flash_attn_f32_q8_0( if (k_row2 < n_kv) s2 += slope * (ACC_TYPE) mask_ptr[k_row2]; if (k_row3 < n_kv) s3 += slope * (ACC_TYPE) mask_ptr[k_row3]; } - if (logit_softcap > 0.0f) { - s0 = logit_softcap * tanh(s0 / logit_softcap); - s1 = logit_softcap * tanh(s1 / logit_softcap); - s2 = logit_softcap * tanh(s2 / logit_softcap); - s3 = logit_softcap * tanh(s3 / logit_softcap); - } const ACC_TYPE m_new = max(m_i, max(max(s0, s1), max(s2, s3))); // Whole tile masked (m_new == FA_M_INIT): force the exp() args diff --git a/ggml/src/ggml-opencl/kernels/fwht.cl b/ggml/src/ggml-opencl/kernels/fwht.cl new file mode 100644 index 000000000000..b1fafc34f807 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/fwht.cl @@ -0,0 +1,44 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +kernel void kernel_fwht( + global const char * src, + ulong offset_src, + global char * dst, + ulong offset_dst, + int n, + ulong ne1, + ulong ne2, + ulong nb1, + ulong nb2, + ulong nb3, + float scale, + local float * work) { + const ulong row = get_group_id(1); + const ulong i1 = row % ne1; + const ulong i2 = row / ne1 % ne2; + const ulong i3 = row / ne1 / ne2; + global const SRC_TYPE * x = (global const SRC_TYPE *)(src + offset_src + i1*nb1 + i2*nb2 + i3*nb3); + global float * y = (global float *)(dst + offset_dst) + row*n; + const int tid = get_local_id(0); + const int nth = get_local_size(0); + + for (int i = tid; i < n; i += nth) { + work[i] = (float)x[i] * scale; + } + barrier(CLK_LOCAL_MEM_FENCE); + + for (int h = 1; h < n; h *= 2) { + for (int i = tid; i < n/2; i += nth) { + const int j = 2*i - (i & (h - 1)); + const float a = work[j]; + const float b = work[j + h]; + work[j] = a + b; + work[j + h] = a - b; + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + for (int i = tid; i < n; i += nth) { + y[i] = work[i]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_0_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_0_q8_1_dp4a.cl new file mode 100644 index 000000000000..a35957409987 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_0_q8_1_dp4a.cl @@ -0,0 +1,205 @@ +// Cooperative-K DP4A GEMM for 2 to 4 columns with Q4_0 weights and Q8_1 activations. +// Named vector components avoid dynamic private-array indexing, which can cause register spills. + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#ifndef COOPK_NSG +#define COOPK_NSG 4 +#endif +#define COOPK_SG 64 + +#ifndef COOPK_ROWS +#define COOPK_ROWS 4 +#endif +#ifndef COOPK_COLS +#define COOPK_COLS 4 +#endif + +#if COOPK_COLS == 4 +typedef float4 coopk_accv; +typedef int4 coopk_dotv; +#define COOPK_CONVF convert_float4 +#else +typedef float2 coopk_accv; +typedef int2 coopk_dotv; +#define COOPK_CONVF convert_float2 +#endif + +// Pack four Q4_0 weights as signed bytes after subtracting 8. +#define EXP40(l) \ + ( (((uint)((int)(( (l) & 0x000Fu) - 8) & 0xFF))) \ + | (((uint)((int)((((l) & 0x00F0u) >> 4) - 8) & 0xFF)) << 8) \ + | (((uint)((int)((((l) & 0x0F00u) >> 8) - 8) & 0xFF)) << 16) \ + | (((uint)((int)((((l) & 0xF000u) >> 12) - 8) & 0xFF)) << 24) ) + +#if COOPK_ROWS == 4 +#define COOPK_DOT(ci, t) \ + d0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, d0.s##ci); \ + d1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, d1.s##ci); \ + d2.s##ci = dot_acc_sat_4x8packed_ss_int(w2, A##ci.s##t, d2.s##ci); \ + d3.s##ci = dot_acc_sat_4x8packed_ss_int(w3, A##ci.s##t, d3.s##ci); +#else +#define COOPK_DOT(ci, t) \ + d0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, d0.s##ci); \ + d1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, d1.s##ci); +#endif + +#if COOPK_COLS == 4 +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) COOPK_DOT(2,t) COOPK_DOT(3,t) +#define COOPK_FOR_COLS(F) F(0) F(1) F(2) F(3) +#else +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) +#define COOPK_FOR_COLS(F) F(0) F(1) +#endif + +#if COOPK_ROWS == 4 +#define COOPK_KSTEP(t) \ + { \ + ushort4 bl = vload4(0, src0_q + row0 + (ku0 + t) * m); \ + const uint w0 = EXP40(bl.s0); \ + const uint w1 = EXP40(bl.s1); \ + const uint w2 = EXP40(bl.s2); \ + const uint w3 = EXP40(bl.s3); \ + COOPK_DOTS_AT(t) \ + } +#else +#define COOPK_KSTEP(t) \ + { \ + ushort2 bl = vload2(0, src0_q + row0 + (ku0 + t) * m); \ + const uint w0 = EXP40(bl.s0); \ + const uint w1 = EXP40(bl.s1); \ + COOPK_DOTS_AT(t) \ + } +#endif + +// Weights use the untiled Adreno noshuffle SoA layout, with the output row contiguous in each plane. +// Q8_1 activation planes are K-major (K contiguous); no activation transpose is used. +kernel void kernel_gemm_coopk_q4_0_q8_1_dp4a( + global const ushort * src0_q, // four consecutive K nibbles per ushort, [k/4][m] + global const half * src0_d, // block scales, [k/32][m] + global const uint * src1_qa, // four signed activation bytes per uint, [n][k/4] + global const half * src1_da, // activation scales, [n][k/32] + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + + const int gx = get_global_id(0); + const int sg = get_local_id(1); + const int lane = get_local_id(0); + + const int row0 = gx * COOPK_ROWS; + const int num_32blk = k / 32; + const int k_u = k >> 2; + const int k_b = k >> 5; + + // The host pads activations to COOPK_COLS; stores mask columns beyond n_no_padding. + const int c0 = 0, c1 = 1; +#if COOPK_COLS == 4 + const int c2 = 2, c3 = 3; +#endif + + coopk_accv acc0 = (coopk_accv)(0.0f), acc1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv acc2 = (coopk_accv)(0.0f), acc3 = (coopk_accv)(0.0f); +#endif + + for (int blk = sg; blk < num_32blk; blk += COOPK_NSG) { +#if COOPK_ROWS == 4 + half4 scale = vload4(0, src0_d + row0 + blk * m); +#else + half2 scale = vload2(0, src0_d + row0 + blk * m); +#endif + + coopk_accv da; + da.s0 = (float)src1_da[c0*k_b + blk]; + da.s1 = (float)src1_da[c1*k_b + blk]; +#if COOPK_COLS == 4 + da.s2 = (float)src1_da[c2*k_b + blk]; + da.s3 = (float)src1_da[c3*k_b + blk]; +#endif + + // Q4_0 uses one weight scale per 32 K values. + coopk_dotv d0 = (coopk_dotv)(0), d1 = (coopk_dotv)(0); +#if COOPK_ROWS == 4 + coopk_dotv d2 = (coopk_dotv)(0), d3 = (coopk_dotv)(0); +#endif + for (int half_idx = 0; half_idx < 2; ++half_idx) { + const int ku0 = (blk << 3) + half_idx * 4; + + uint4 A0 = vload4(0, src1_qa + (uint)c0 * k_u + ku0); + uint4 A1 = vload4(0, src1_qa + (uint)c1 * k_u + ku0); +#if COOPK_COLS == 4 + uint4 A2 = vload4(0, src1_qa + (uint)c2 * k_u + ku0); + uint4 A3 = vload4(0, src1_qa + (uint)c3 * k_u + ku0); +#endif + COOPK_KSTEP(0) + COOPK_KSTEP(1) + COOPK_KSTEP(2) + COOPK_KSTEP(3) + } + + acc0 += (float)scale.s0 * da * COOPK_CONVF(d0); + acc1 += (float)scale.s1 * da * COOPK_CONVF(d1); +#if COOPK_ROWS == 4 + acc2 += (float)scale.s2 * da * COOPK_CONVF(d2); + acc3 += (float)scale.s3 * da * COOPK_CONVF(d3); +#endif + } + + // Reuse one local buffer for all rows; the first barrier protects the previous row's reads. + local coopk_accv reduceLM[COOPK_SG * (COOPK_NSG - 1)]; + coopk_accv out0 = (coopk_accv)(0.0f), out1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv out2 = (coopk_accv)(0.0f), out3 = (coopk_accv)(0.0f); +#endif + +#define COOPK_REDUCE(accv, outv) \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg > 0) { reduceLM[(sg - 1) * COOPK_SG + lane] = (accv); } \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg == 0) { \ + coopk_accv sum = (accv); \ + for (int s = 0; s < COOPK_NSG - 1; s++) { \ + sum += reduceLM[s * COOPK_SG + lane]; \ + } \ + (outv) = sum; \ + } + + COOPK_REDUCE(acc0, out0) + COOPK_REDUCE(acc1, out1) +#if COOPK_ROWS == 4 + COOPK_REDUCE(acc2, out2) + COOPK_REDUCE(acc3, out3) +#endif + +#undef COOPK_REDUCE + +#if COOPK_ROWS == 4 +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore4((float4)(out0.s##ci, out1.s##ci, out2.s##ci, out3.s##ci), 0, dst + idx); \ + idx += m; \ + } +#else +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore2((float2)(out0.s##ci, out1.s##ci), 0, dst + idx); \ + idx += m; \ + } +#endif + + if (sg == 0) { + int idx = row0; + COOPK_FOR_COLS(COOPK_STORE_COL) + } + +#undef COOPK_STORE_COL +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_k_q8_1_dp4a.cl new file mode 100644 index 000000000000..31dce626f142 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_coopk_q4_k_q8_1_dp4a.cl @@ -0,0 +1,264 @@ +// Cooperative-K DP4A GEMM for 2 to 4 columns with Q4_K weights and Q8_1 activations. +// Named vector components avoid dynamic private-array indexing, which can cause register spills. + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 +#define K_SCALE_SIZE 12 + +#ifndef COOPK_NSG +#define COOPK_NSG 4 +#endif +#define COOPK_SG 64 + +#ifndef COOPK_ROWS +#define COOPK_ROWS 4 +#endif +#ifndef COOPK_COLS +#define COOPK_COLS 4 +#endif + +#if COOPK_COLS == 4 +typedef float4 coopk_accv; +typedef int4 coopk_dotv; +#define COOPK_CONVF convert_float4 +#else +typedef float2 coopk_accv; +typedef int2 coopk_dotv; +#define COOPK_CONVF convert_float2 +#endif + +// Expand four Q4_K nibbles into bytes for DP4A. +#define EXP4(u) ( ((uint)((u) & 0x000Fu)) | \ + (((uint)((u) & 0x00F0u)) << 4) | \ + (((uint)((u) & 0x0F00u)) << 8) | \ + (((uint)((u) & 0xF000u)) << 12) ) + +#if COOPK_ROWS == 4 +#define COOPK_DOT(ci, t) \ + s0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, s0.s##ci); \ + s1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, s1.s##ci); \ + s2.s##ci = dot_acc_sat_4x8packed_ss_int(w2, A##ci.s##t, s2.s##ci); \ + s3.s##ci = dot_acc_sat_4x8packed_ss_int(w3, A##ci.s##t, s3.s##ci); +#else +#define COOPK_DOT(ci, t) \ + s0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, s0.s##ci); \ + s1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, s1.s##ci); +#endif + +#if COOPK_COLS == 4 +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) COOPK_DOT(2,t) COOPK_DOT(3,t) +#define COOPK_FOR_COLS(F) F(0) F(1) F(2) F(3) +#else +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) +#define COOPK_FOR_COLS(F) F(0) F(1) +#endif + +// The bin layout packs eight K values in each uint, with four nibbles in each 16-bit half. +// Since ku0 is a multiple of four, t / 2 selects the uint and t & 1 selects its half. +#ifdef COOPK_Q_BIN +#define COOPK_QBITS4(t) convert_ushort4(((t) & 1) ? (vload4(0, src0_q + row0 + ((ku0 >> 1) + ((t) >> 1)) * m) >> 16) \ + : (vload4(0, src0_q + row0 + ((ku0 >> 1) + ((t) >> 1)) * m) & 0xFFFFu)) +#define COOPK_QBITS2(t) convert_ushort2(((t) & 1) ? (vload2(0, src0_q + row0 + ((ku0 >> 1) + ((t) >> 1)) * m) >> 16) \ + : (vload2(0, src0_q + row0 + ((ku0 >> 1) + ((t) >> 1)) * m) & 0xFFFFu)) +#else +#define COOPK_QBITS4(t) vload4(0, src0_q + row0 + (ku0 + t) * m) +#define COOPK_QBITS2(t) vload2(0, src0_q + row0 + (ku0 + t) * m) +#endif + +#if COOPK_ROWS == 4 +#define COOPK_KSTEP(t) \ + { \ + ushort4 bits = COOPK_QBITS4(t); \ + const uint w0 = EXP4(bits.s0); \ + const uint w1 = EXP4(bits.s1); \ + const uint w2 = EXP4(bits.s2); \ + const uint w3 = EXP4(bits.s3); \ + COOPK_DOTS_AT(t) \ + } +#else +#define COOPK_KSTEP(t) \ + { \ + ushort2 bits = COOPK_QBITS2(t); \ + const uint w0 = EXP4(bits.s0); \ + const uint w1 = EXP4(bits.s1); \ + COOPK_DOTS_AT(t) \ + } +#endif + +inline void get_scale_min_k4_c(int j, global const uchar * q, int stride, + uchar * d, uchar * m, + uchar mask_d6, uchar mask_d4, uchar mask_hi2) { + if (j < 4) { + *d = q[j*stride] & mask_d6; + *m = q[(j + 4)*stride] & mask_d6; + } else { + *d = (q[(j + 4)*stride] & mask_d4) | ((q[(j - 4)*stride] >> 6) << 4); + *m = (q[(j + 4)*stride] >> 4) | ((q[(j )*stride] >> 6) << 4); + } +} + +// Weights use the untiled Adreno noshuffle SoA layout; COOPK_Q_BIN selects uint-transposed q instead of ushort-transposed q. +// Q8_1 activation planes are K-major (K contiguous); no activation transpose is used. +kernel void kernel_gemm_coopk_q4_k_q8_1_dp4a( +#ifdef COOPK_Q_BIN + global const uint * src0_q, // eight consecutive K nibbles per uint, [k/8][m] +#else + global const ushort * src0_q, // four consecutive K nibbles per ushort, [k/4][m] +#endif + global const uchar * src0_s, // packed 6-bit scales/mins, [k/256][12][m] + global const half * src0_d, // super-block scales, [k/256][m] + global const half * src0_dm, // super-block mins, [k/256][m] + global const uint * src1_qa, // four signed activation bytes per uint, [n][k/4] + global const half * src1_da, // activation scales, [n][k/32] + global const half * src1_sa, // scaled activation sums, [n][k/32] + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding, + uchar mask_d6, + uchar mask_d4, + uchar mask_hi2 +) { + dst = (global float *)((global char *)dst + offsetd); + + const int gx = get_global_id(0); // row group + const int sg = get_local_id(1); // K-split subgroup + const int lane = get_local_id(0); + + const int row0 = gx * COOPK_ROWS; + const int num_32blk = k / 32; + const int k_u = k >> 2; // K in uint (int8x4) units + const int k_b = k >> 5; // 32-blocks along K + + // The host pads activations to COOPK_COLS; stores mask columns beyond n_no_padding. + const int nl = n - 1; + const int c0 = 0; + const int c1 = (1 < n) ? 1 : nl; +#if COOPK_COLS >= 4 + const int c2 = (2 < n) ? 2 : nl; + const int c3 = (3 < n) ? 3 : nl; +#endif + + coopk_accv acc0 = (coopk_accv)(0.0f), acc1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv acc2 = (coopk_accv)(0.0f), acc3 = (coopk_accv)(0.0f); +#endif + + for (int blk = sg; blk < num_32blk; blk += COOPK_NSG) { + const int i = blk << 5; + const int sb_idx = blk >> 3; + const int sub_idx = blk & 7; + + global const uchar * sc = src0_s + sb_idx * K_SCALE_SIZE * m + row0; + uchar sv0, mn0, sv1, mn1; + get_scale_min_k4_c(sub_idx, sc + 0, m, &sv0, &mn0, mask_d6, mask_d4, mask_hi2); + get_scale_min_k4_c(sub_idx, sc + 1, m, &sv1, &mn1, mask_d6, mask_d4, mask_hi2); +#if COOPK_ROWS == 4 + half4 dd = vload4(0, src0_d + row0 + sb_idx * m); + half4 dmm = vload4(0, src0_dm + row0 + sb_idx * m); + uchar sv2, mn2, sv3, mn3; + get_scale_min_k4_c(sub_idx, sc + 2, m, &sv2, &mn2, mask_d6, mask_d4, mask_hi2); + get_scale_min_k4_c(sub_idx, sc + 3, m, &sv3, &mn3, mask_d6, mask_d4, mask_hi2); + const float sc2 = (float)dd.s2 * (float)sv2, mv2 = (float)dmm.s2 * (float)mn2; + const float sc3 = (float)dd.s3 * (float)sv3, mv3 = (float)dmm.s3 * (float)mn3; +#else + half2 dd = vload2(0, src0_d + row0 + sb_idx * m); + half2 dmm = vload2(0, src0_dm + row0 + sb_idx * m); +#endif + const float sc0 = (float)dd.s0 * (float)sv0, mv0 = (float)dmm.s0 * (float)mn0; + const float sc1 = (float)dd.s1 * (float)sv1, mv1 = (float)dmm.s1 * (float)mn1; + + // Q4_K scale and min values change every 32 K values. + coopk_dotv s0 = (coopk_dotv)(0), s1 = (coopk_dotv)(0); +#if COOPK_ROWS == 4 + coopk_dotv s2 = (coopk_dotv)(0), s3 = (coopk_dotv)(0); +#endif + + for (int uq = 0; uq < 2; ++uq) { + const int ku0 = (i >> 2) + uq * 4; + + uint4 A0 = vload4(0, src1_qa + (uint)c0 * k_u + ku0); + uint4 A1 = vload4(0, src1_qa + (uint)c1 * k_u + ku0); +#if COOPK_COLS >= 4 + uint4 A2 = vload4(0, src1_qa + (uint)c2 * k_u + ku0); + uint4 A3 = vload4(0, src1_qa + (uint)c3 * k_u + ku0); +#endif + COOPK_KSTEP(0) + COOPK_KSTEP(1) + COOPK_KSTEP(2) + COOPK_KSTEP(3) + } + + // Q4_K stores q * scale - min for each 32-value block. + // src1_sa already includes the activation scale, so the min term needs no extra factor of da. + coopk_accv da, sa; + da.s0 = (float)src1_da[c0*k_b + blk]; sa.s0 = (float)src1_sa[c0*k_b + blk]; + da.s1 = (float)src1_da[c1*k_b + blk]; sa.s1 = (float)src1_sa[c1*k_b + blk]; +#if COOPK_COLS >= 4 + da.s2 = (float)src1_da[c2*k_b + blk]; sa.s2 = (float)src1_sa[c2*k_b + blk]; + da.s3 = (float)src1_da[c3*k_b + blk]; sa.s3 = (float)src1_sa[c3*k_b + blk]; +#endif + + acc0 += sc0 * da * COOPK_CONVF(s0) - mv0 * sa; + acc1 += sc1 * da * COOPK_CONVF(s1) - mv1 * sa; +#if COOPK_ROWS == 4 + acc2 += sc2 * da * COOPK_CONVF(s2) - mv2 * sa; + acc3 += sc3 * da * COOPK_CONVF(s3) - mv3 * sa; +#endif + } + + // Reuse one local buffer for all rows; the first barrier protects the previous row's reads. + local coopk_accv reduceLM[COOPK_SG * (COOPK_NSG - 1)]; + coopk_accv out0 = (coopk_accv)(0.0f), out1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv out2 = (coopk_accv)(0.0f), out3 = (coopk_accv)(0.0f); +#endif + +#define COOPK_REDUCE(accv, outv) \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg > 0) { reduceLM[(sg - 1) * COOPK_SG + lane] = (accv); } \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg == 0) { \ + coopk_accv sum = (accv); \ + for (int s = 0; s < COOPK_NSG - 1; s++) { \ + sum += reduceLM[s * COOPK_SG + lane]; \ + } \ + (outv) = sum; \ + } + + COOPK_REDUCE(acc0, out0) + COOPK_REDUCE(acc1, out1) +#if COOPK_ROWS == 4 + COOPK_REDUCE(acc2, out2) + COOPK_REDUCE(acc3, out3) +#endif + +#undef COOPK_REDUCE + +#if COOPK_ROWS == 4 +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore4((float4)(out0.s##ci, out1.s##ci, out2.s##ci, out3.s##ci), 0, dst + idx); \ + idx += m; \ + } +#else +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore2((float2)(out0.s##ci, out1.s##ci), 0, dst + idx); \ + idx += m; \ + } +#endif + + if (sg == 0) { + int idx = row0; + COOPK_FOR_COLS(COOPK_STORE_COL) + } + +#undef COOPK_STORE_COL +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_coopk_q6_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_coopk_q6_k_q8_1_dp4a.cl new file mode 100644 index 000000000000..4410a230d773 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_coopk_q6_k_q8_1_dp4a.cl @@ -0,0 +1,216 @@ +// Cooperative-K DP4A GEMM for 2 to 4 columns with Q6_K weights and Q8_1 activations. +// Named vector components avoid dynamic private-array indexing, which can cause register spills. + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#ifndef COOPK_NSG +#define COOPK_NSG 4 +#endif +#define COOPK_SG 64 + +#ifndef COOPK_ROWS +#define COOPK_ROWS 4 +#endif +#ifndef COOPK_COLS +#define COOPK_COLS 4 +#endif + +#if COOPK_COLS == 4 +typedef float4 coopk_accv; +typedef int4 coopk_dotv; +#define COOPK_CONVF convert_float4 +#else +typedef float2 coopk_accv; +typedef int2 coopk_dotv; +#define COOPK_CONVF convert_float2 +#endif + +// Combine low nibbles and high bits, subtract 32, and pack four signed bytes for DP4A. +#define EXP6(l, h, mf, mc) \ + ( (((uint)((int)((( (l) & 0x000Fu) | (((h) & 0x03u) << 4)) - 32) & 0xFF))) \ + | (((uint)((int)(((((l) & 0x00F0u) >> 4) | (((h) & 0x0Cu) << 2)) - 32) & 0xFF)) << 8) \ + | (((uint)((int)(((((l) & 0x0F00u) >> 8) | ((h) & 0x30u)) - 32) & 0xFF)) << 16) \ + | (((uint)((int)(((((l) & (mf)) >> 12) | (((h) & (mc)) >> 2)) - 32) & 0xFF)) << 24) ) + +#if COOPK_ROWS == 4 +#define COOPK_DOT(ci, t) \ + d0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, d0.s##ci); \ + d1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, d1.s##ci); \ + d2.s##ci = dot_acc_sat_4x8packed_ss_int(w2, A##ci.s##t, d2.s##ci); \ + d3.s##ci = dot_acc_sat_4x8packed_ss_int(w3, A##ci.s##t, d3.s##ci); +#else +#define COOPK_DOT(ci, t) \ + d0.s##ci = dot_acc_sat_4x8packed_ss_int(w0, A##ci.s##t, d0.s##ci); \ + d1.s##ci = dot_acc_sat_4x8packed_ss_int(w1, A##ci.s##t, d1.s##ci); +#endif + +#if COOPK_COLS == 4 +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) COOPK_DOT(2,t) COOPK_DOT(3,t) +#define COOPK_FOR_COLS(F) F(0) F(1) F(2) F(3) +#else +#define COOPK_DOTS_AT(t) COOPK_DOT(0,t) COOPK_DOT(1,t) +#define COOPK_FOR_COLS(F) F(0) F(1) +#endif + +#if COOPK_ROWS == 4 +#define COOPK_KSTEP(t) \ + { \ + ushort4 bl = vload4(0, src0_ql + row0 + (ku0 + t) * m); \ + uchar4 bh = vload4(0, src0_qh + row0 + (ku0 + t) * m); \ + const uint w0 = EXP6(bl.s0, bh.s0, mask_f000, mask_c0); \ + const uint w1 = EXP6(bl.s1, bh.s1, mask_f000, mask_c0); \ + const uint w2 = EXP6(bl.s2, bh.s2, mask_f000, mask_c0); \ + const uint w3 = EXP6(bl.s3, bh.s3, mask_f000, mask_c0); \ + COOPK_DOTS_AT(t) \ + } +#else +#define COOPK_KSTEP(t) \ + { \ + ushort2 bl = vload2(0, src0_ql + row0 + (ku0 + t) * m); \ + uchar2 bh = vload2(0, src0_qh + row0 + (ku0 + t) * m); \ + const uint w0 = EXP6(bl.s0, bh.s0, mask_f000, mask_c0); \ + const uint w1 = EXP6(bl.s1, bh.s1, mask_f000, mask_c0); \ + COOPK_DOTS_AT(t) \ + } +#endif + +// Weights use the untiled Adreno noshuffle SoA layout, with the output row contiguous in each plane. +// Q8_1 activation planes are K-major (K contiguous); no activation transpose is used. +kernel void kernel_gemm_coopk_q6_k_q8_1_dp4a( + global const ushort * src0_ql, // four consecutive low nibbles per ushort, [k/4][m] + global const uchar * src0_qh, // four consecutive high 2-bit codes per uchar, [k/4][m] + global const ushort * src0_s, // two signed int8 scales per ushort, [k/32][m] + global const half * src0_d, // super-block scales, [k/256][m] + global const uint * src1_qa, // four signed activation bytes per uint, [n][k/4] + global const half * src1_da, // activation scales, [n][k/32] + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding, + ushort mask_f000, + uchar mask_c0 +) { + dst = (global float *)((global char *)dst + offsetd); + + const int gx = get_global_id(0); + const int sg = get_local_id(1); + const int lane = get_local_id(0); + + const int row0 = gx * COOPK_ROWS; + const int num_32blk = k / 32; + const int k_u = k >> 2; + const int k_b = k >> 5; + + // The host pads activations to COOPK_COLS; stores mask columns beyond n_no_padding. + const int c0 = 0, c1 = 1; +#if COOPK_COLS == 4 + const int c2 = 2, c3 = 3; +#endif + + coopk_accv acc0 = (coopk_accv)(0.0f), acc1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv acc2 = (coopk_accv)(0.0f), acc3 = (coopk_accv)(0.0f); +#endif + + for (int blk = sg; blk < num_32blk; blk += COOPK_NSG) { + const int i = blk << 5; + + // Each ushort packs two signed scale bytes, one for each 16-value half of this 32-value block. + // The half-precision super-block scale is shared by 256 K values. + ushort4 spk = vload4(0, src0_s + row0 + blk * m); + half4 scd = vload4(0, src0_d + row0 + (i >> 8) * m); + + coopk_accv da; + da.s0 = (float)src1_da[c0*k_b + blk]; + da.s1 = (float)src1_da[c1*k_b + blk]; +#if COOPK_COLS == 4 + da.s2 = (float)src1_da[c2*k_b + blk]; + da.s3 = (float)src1_da[c3*k_b + blk]; +#endif + + // Apply each signed weight scale to its 16-value dot product. + for (int half_idx = 0; half_idx < 2; ++half_idx) { + const int ku0 = (i >> 2) + half_idx * 4; + + coopk_dotv d0 = (coopk_dotv)(0), d1 = (coopk_dotv)(0); +#if COOPK_ROWS == 4 + coopk_dotv d2 = (coopk_dotv)(0), d3 = (coopk_dotv)(0); +#endif + uint4 A0 = vload4(0, src1_qa + (uint)c0 * k_u + ku0); + uint4 A1 = vload4(0, src1_qa + (uint)c1 * k_u + ku0); +#if COOPK_COLS == 4 + uint4 A2 = vload4(0, src1_qa + (uint)c2 * k_u + ku0); + uint4 A3 = vload4(0, src1_qa + (uint)c3 * k_u + ku0); +#endif + COOPK_KSTEP(0) + COOPK_KSTEP(1) + COOPK_KSTEP(2) + COOPK_KSTEP(3) + + const float s0f = (float)(half_idx ? as_char2(spk.s0).s1 : as_char2(spk.s0).s0) * (float)scd.s0; + const float s1f = (float)(half_idx ? as_char2(spk.s1).s1 : as_char2(spk.s1).s0) * (float)scd.s1; + acc0 += s0f * da * COOPK_CONVF(d0); + acc1 += s1f * da * COOPK_CONVF(d1); +#if COOPK_ROWS == 4 + const float s2f = (float)(half_idx ? as_char2(spk.s2).s1 : as_char2(spk.s2).s0) * (float)scd.s2; + const float s3f = (float)(half_idx ? as_char2(spk.s3).s1 : as_char2(spk.s3).s0) * (float)scd.s3; + acc2 += s2f * da * COOPK_CONVF(d2); + acc3 += s3f * da * COOPK_CONVF(d3); +#endif + } + } + + // Reuse one local buffer for all rows; the first barrier protects the previous row's reads. + local coopk_accv reduceLM[COOPK_SG * (COOPK_NSG - 1)]; + coopk_accv out0 = (coopk_accv)(0.0f), out1 = (coopk_accv)(0.0f); +#if COOPK_ROWS == 4 + coopk_accv out2 = (coopk_accv)(0.0f), out3 = (coopk_accv)(0.0f); +#endif + +#define COOPK_REDUCE(accv, outv) \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg > 0) { reduceLM[(sg - 1) * COOPK_SG + lane] = (accv); } \ + barrier(CLK_LOCAL_MEM_FENCE); \ + if (sg == 0) { \ + coopk_accv sum = (accv); \ + for (int s = 0; s < COOPK_NSG - 1; s++) { \ + sum += reduceLM[s * COOPK_SG + lane]; \ + } \ + (outv) = sum; \ + } + + COOPK_REDUCE(acc0, out0) + COOPK_REDUCE(acc1, out1) +#if COOPK_ROWS == 4 + COOPK_REDUCE(acc2, out2) + COOPK_REDUCE(acc3, out3) +#endif + +#undef COOPK_REDUCE + +#if COOPK_ROWS == 4 +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore4((float4)(out0.s##ci, out1.s##ci, out2.s##ci, out3.s##ci), 0, dst + idx); \ + idx += m; \ + } +#else +#define COOPK_STORE_COL(ci) \ + if (idx < m*n_no_padding) { \ + vstore2((float2)(out0.s##ci, out1.s##ci), 0, dst + idx); \ + idx += m; \ + } +#endif + + if (sg == 0) { + int idx = row0; + COOPK_FOR_COLS(COOPK_STORE_COL) + } + +#undef COOPK_STORE_COL +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_f32.cl new file mode 100644 index 000000000000..cc9e3d45a60c --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_f32.cl @@ -0,0 +1,93 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq1_m_f32( + global const uchar * src0_qs, + global const uchar * src0_qh, + global const ushort * src0_sc, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uint4 w0 = convert_uint4(vload4(0, src0_sc + row + (4*(i / 256) + 0) * m)); + const uint4 w1 = convert_uint4(vload4(0, src0_sc + row + (4*(i / 256) + 1) * m)); + const uint4 w2 = convert_uint4(vload4(0, src0_sc + row + (4*(i / 256) + 2) * m)); + const uint4 w3 = convert_uint4(vload4(0, src0_sc + row + (4*(i / 256) + 3) * m)); + const ushort4 bits = convert_ushort4((w0 >> (uint4)(12)) | ((w1 >> (uint4)(8)) & (uint4)(0x00f0)) + | ((w2 >> (uint4)(4)) & (uint4)(0x0f00)) | (w3 & (uint4)(0xf000))); + const half4 d = as_half4(bits); + const uint4 sc = convert_uint4(vload4(0, src0_sc + row + (i / 64) * m)); + const half4 scale = d * convert_half4(2*((sc >> (uint4)(3*((i / 16) & 3))) & (uint4)(7)) + 1); + const uint4 qh = convert_uint4(vload4(0, src0_qh + row + (i / 16) * m)); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 gi = convert_uint4(vload4(0, src0_qs + row + (ki / 8) * m)) + | (((qh >> (uint4)(4*((ki / 8) & 1))) & (uint4)(7)) << (uint4)(8)); + const uint4 grid = (uint4)(iq1_s_grid[gi.s0], iq1_s_grid[gi.s1], iq1_s_grid[gi.s2], iq1_s_grid[gi.s3]); + const float4 delta = select((float4)(-0.875f), (float4)(-1.125f), (qh & (uint4)(0x08 << (4*((ki / 8) & 1)))) != 0); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const float4 magnitude = convert_float4((grid >> (uint4)(8*j + (ki & 4))) & (uint4)(15)); + const half4 w = convert_half4(magnitude + delta) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_q8_1_dp4a.cl new file mode 100644 index 000000000000..fb5d58a880f3 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_m_q8_1_dp4a.cl @@ -0,0 +1,144 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq1_m_pack(uint g, uint shift, uint negative_delta) { + // 8*(grid + delta) is an exact signed integer in [-9, 9]. + const int bias = negative_delta ? -9 : -7; + const int4 values = 8*convert_int4(as_uchar4((g >> shift) & 0x0F0F0F0Fu)) + bias; + return as_uint(convert_char4(values)); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq1_m_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uchar * src0_qh, + __global const ushort * src0_sc, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define IQ1_M_GRID(i) iq1_s_grid[(i)] + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + float dsuper = 0.f; + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + if ((sub & 7u) == 0u) { + const uint sb = rrow + 4u*ib*(uint)m; + const uint w0 = src0_sc[sb + 0u*(uint)m]; + const uint w1 = src0_sc[sb + 1u*(uint)m]; + const uint w2 = src0_sc[sb + 2u*(uint)m]; + const uint w3 = src0_sc[sb + 3u*(uint)m]; + const ushort bits = (ushort)((w0 >> 12) | ((w1 >> 8) & 0x00f0u) + | ((w2 >> 4) & 0x0f00u) | (w3 & 0xf000u)); + dsuper = (float)as_half(bits); + } + const uint sc = src0_sc[rrow + (4u*ib + (sub & 7u)/2u)*(uint)m]; + const uint sh = 6u*(sub & 1u); + const float dl0 = dsuper * (float)(2u*((sc >> sh) & 7u) + 1u) * 0.125f; + const float dl1 = dsuper * (float)(2u*((sc >> (sh + 3u)) & 7u) + 1u) * 0.125f; + const uint h0 = src0_qh[rrow + (2u*sub + 0u)*(uint)m]; + const uint h1 = src0_qh[rrow + (2u*sub + 1u)*(uint)m]; + const uint gb = rrow + 4u*sub*(uint)m; + const uint g0 = IQ1_M_GRID((uint)src0_qs[gb + 0u*(uint)m] | (( h0 & 7u) << 8)); + const uint g1 = IQ1_M_GRID((uint)src0_qs[gb + 1u*(uint)m] | (((h0 >> 4) & 7u) << 8)); + const uint g2 = IQ1_M_GRID((uint)src0_qs[gb + 2u*(uint)m] | (( h1 & 7u) << 8)); + const uint g3 = IQ1_M_GRID((uint)src0_qs[gb + 3u*(uint)m] | (((h1 >> 4) & 7u) << 8)); + const uint4 qlo = (uint4)(iq1_m_pack(g0, 0, h0 & 0x08u), iq1_m_pack(g0, 4, h0 & 0x08u), + iq1_m_pack(g1, 0, h0 & 0x80u), iq1_m_pack(g1, 4, h0 & 0x80u)); + const uint4 qhi = (uint4)(iq1_m_pack(g2, 0, h1 & 0x08u), iq1_m_pack(g2, 4, h1 & 0x08u), + iq1_m_pack(g3, 0, h1 & 0x80u), iq1_m_pack(g3, 4, h1 & 0x80u)); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) +#define IQ1_M_COL(b) (dl0 * (float)dot4_q8a_v(qlo, (uint4)(sh_qa4[b][0])) \ + + dl1 * (float)dot4_q8a_v(qhi, (uint4)(sh_qa4[b][1]))) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + rf.s0 = IQ1_M_COL(b+0); rf.s1 = IQ1_M_COL(b+1); + rf.s2 = IQ1_M_COL(b+2); rf.s3 = IQ1_M_COL(b+3); + acc[g] += LD4(sh_d, b) * rf; + } +#undef IQ1_M_COL +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +#undef IQ1_M_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_f32.cl new file mode 100644 index 000000000000..55fdba62094a --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_f32.cl @@ -0,0 +1,86 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq1_s_f32( + global const uchar * src0_qs, + global const ushort * src0_qh, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uint4 qh = convert_uint4(vload4(0, src0_qh + row + (i / 32) * m)); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const half4 scale = d * convert_half4(2*((qh >> (uint4)(12)) & (uint4)(7)) + 1); + const float4 delta = select((float4)(-0.875f), (float4)(-1.125f), (qh & (uint4)(0x8000)) != 0); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 gi = convert_uint4(vload4(0, src0_qs + row + (ki / 8) * m)) + | (((qh >> (uint4)(3*((ki / 8) & 3))) & (uint4)(7)) << (uint4)(8)); + const uint4 grid = (uint4)(iq1_s_grid[gi.s0], iq1_s_grid[gi.s1], iq1_s_grid[gi.s2], iq1_s_grid[gi.s3]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const float4 magnitude = convert_float4((grid >> (uint4)(8*j + (ki & 4))) & (uint4)(15)); + const half4 w = convert_half4(magnitude + delta) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_q8_1_dp4a.cl new file mode 100644 index 000000000000..92acb89b9858 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq1_s_q8_1_dp4a.cl @@ -0,0 +1,138 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq1_s_q8_1_dp4a( + __global const uchar * src0_qs, + __global const ushort * src0_qh, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global const half * src1_sa, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_da[TILESIZE_N]; + __local half sh_sa[TILESIZE_N]; + +#define IQ1_S_GRID(i) iq1_s_grid[(i)] + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + const uint qhv = (uint)src0_qh[rrow + sub * (uint)m]; + const float dl = (float)src0_d[rrow + ib * (uint)m] + * (float)(2u * ((qhv >> 12) & 7u) + 1u); + + // The codebook stores grid + 1; sa includes the Q8_1 activation scale. + const float dlt = ((qhv & 0x8000u) ? -0.125f : 0.125f) - 1.0f; + + const uint gb = rrow + (step >> 3) * (uint)m; + + uint8 qw; + { + const uint g0 = IQ1_S_GRID((uint)src0_qs[gb + 0u * (uint)m] | ((( qhv & 7u) << 8))); + const uint g1 = IQ1_S_GRID((uint)src0_qs[gb + 1u * (uint)m] | ((((qhv >> 3) & 7u) << 8))); + const uint g2 = IQ1_S_GRID((uint)src0_qs[gb + 2u * (uint)m] | ((((qhv >> 6) & 7u) << 8))); + const uint g3 = IQ1_S_GRID((uint)src0_qs[gb + 3u * (uint)m] | ((((qhv >> 9) & 7u) << 8))); + qw.s0 = g0 & 0x0F0F0F0Fu; qw.s1 = (g0 >> 4) & 0x0F0F0F0Fu; + qw.s2 = g1 & 0x0F0F0F0Fu; qw.s3 = (g1 >> 4) & 0x0F0F0F0Fu; + qw.s4 = g2 & 0x0F0F0F0Fu; qw.s5 = (g2 >> 4) & 0x0F0F0F0Fu; + qw.s6 = g3 & 0x0F0F0F0Fu; qw.s7 = (g3 >> 4) & 0x0F0F0F0Fu; + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + const bool ok = c < (uint)n_no_padding; + sh_da[lid] = ok ? src1_da[c * k_b + sub] : (half)0; + sh_sa[lid] = ok ? src1_sa[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define TDOT4(T) dot8_q8a_v(qw, (uint4)(sh_qa4[T][0]), (uint4)(sh_qa4[T][1])) + rf.s0 = (float)TDOT4(b+0); rf.s1 = (float)TDOT4(b+1); + rf.s2 = (float)TDOT4(b+2); rf.s3 = (float)TDOT4(b+3); + acc[g] += dl * (LD4(sh_da, b) * rf) + (dl * dlt) * LD4(sh_sa, b); + } +#undef TDOT4 +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +#undef IQ1_S_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_f32.cl new file mode 100644 index 000000000000..757a5ebd14f8 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_f32.cl @@ -0,0 +1,93 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq2_s_f32( + global const uchar * src0_qs, + global const uchar * src0_sg, + global const uchar * src0_qh, + global const uchar * src0_sc, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uchar4 sc = vload4(0, src0_sc + row + (i / 32) * m); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const float4 scale_f = convert_float4(d) * 0.25f * (0.5f + convert_float4((sc >> (uchar4)(4*((i / 16) & 1))) & (uchar4)(15))); + const half4 scale = convert_half4(scale_f); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 qs = convert_uint4(vload4(0, src0_qs + row + (ki / 8) * m)); + const uint4 qh = convert_uint4(vload4(0, src0_qh + row + (ki / 32) * m)); + const uchar4 sg = vload4(0, src0_sg + row + (ki / 8) * m); + const uint4 gi = qs | (((qh >> (uint4)(2*((ki / 8) & 3))) & (uint4)(3)) << (uint4)(8)); + const uint half_grid = (ki & 7) / 4; + const uint4 grid = (uint4)(iq2_s_grid[2*gi.s0 + half_grid], iq2_s_grid[2*gi.s1 + half_grid], + iq2_s_grid[2*gi.s2 + half_grid], iq2_s_grid[2*gi.s3 + half_grid]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 magnitude = convert_int4((grid >> (uint4)(8*j)) & (uint4)(255)); + const int4 signs = convert_int4((sg >> (uchar4)((ki & 7) + j)) & (uchar4)(1)); + const half4 w = convert_half4(magnitude * ((int4)(1) - 2*signs)) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_q8_1_dp4a.cl new file mode 100644 index 000000000000..a8f1bf9d06e8 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_s_q8_1_dp4a.cl @@ -0,0 +1,149 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq2_s_pack(uint gv, uint sg, uint base) { + int v0 = (int)((gv >> 0) & 0xFF); if (sg & (1u << (base + 0))) { v0 = -v0; } + int v1 = (int)((gv >> 8) & 0xFF); if (sg & (1u << (base + 1))) { v1 = -v1; } + int v2 = (int)((gv >> 16) & 0xFF); if (sg & (1u << (base + 2))) { v2 = -v2; } + int v3 = (int)((gv >> 24) & 0xFF); if (sg & (1u << (base + 3))) { v3 = -v3; } + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq2_s_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uchar * src0_sg, + __global const uchar * src0_qh, + __global const uchar * src0_sc, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define IQ2_S_GRID(i) iq2_s_grid[(i)] + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + const uint qhv = (uint)src0_qh[rrow + sub * (uint)m]; + const uint scv = (uint)src0_sc[rrow + sub * (uint)m]; + const float dv = (float)src0_d[rrow + ib * (uint)m]; + const float dl0 = dv * (0.5f + (float)( scv & 0xFu)) * 0.25f; + const float dl1 = dv * (0.5f + (float)( scv >> 4) ) * 0.25f; + + const uint gb = rrow + (step >> 3) * (uint)m; + + uint4 qlo, qhi; + { + const uint gi0 = (uint)src0_qs[gb + 0u * (uint)m] | ((( qhv & 3u) << 8)); + const uint gi1 = (uint)src0_qs[gb + 1u * (uint)m] | ((((qhv >> 2) & 3u) << 8)); + const uint gi2 = (uint)src0_qs[gb + 2u * (uint)m] | ((((qhv >> 4) & 3u) << 8)); + const uint gi3 = (uint)src0_qs[gb + 3u * (uint)m] | ((((qhv >> 6) & 3u) << 8)); + const uint s0 = (uint)src0_sg[gb + 0u * (uint)m]; + const uint s1 = (uint)src0_sg[gb + 1u * (uint)m]; + const uint s2 = (uint)src0_sg[gb + 2u * (uint)m]; + const uint s3 = (uint)src0_sg[gb + 3u * (uint)m]; + qlo.s0 = iq2_s_pack(IQ2_S_GRID(2u*gi0 + 0u), s0, 0u); + qlo.s1 = iq2_s_pack(IQ2_S_GRID(2u*gi0 + 1u), s0, 4u); + qlo.s2 = iq2_s_pack(IQ2_S_GRID(2u*gi1 + 0u), s1, 0u); + qlo.s3 = iq2_s_pack(IQ2_S_GRID(2u*gi1 + 1u), s1, 4u); + qhi.s0 = iq2_s_pack(IQ2_S_GRID(2u*gi2 + 0u), s2, 0u); + qhi.s1 = iq2_s_pack(IQ2_S_GRID(2u*gi2 + 1u), s2, 4u); + qhi.s2 = iq2_s_pack(IQ2_S_GRID(2u*gi3 + 0u), s3, 0u); + qhi.s3 = iq2_s_pack(IQ2_S_GRID(2u*gi3 + 1u), s3, 4u); + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) +#define IQ2_S_COL(b) (dl0 * (float)dot4_q8a_v(qlo, (uint4)(sh_qa4[b][0])) \ + + dl1 * (float)dot4_q8a_v(qhi, (uint4)(sh_qa4[b][1]))) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + rf.s0 = IQ2_S_COL(b+0); rf.s1 = IQ2_S_COL(b+1); + rf.s2 = IQ2_S_COL(b+2); rf.s3 = IQ2_S_COL(b+3); + acc[g] += LD4(sh_d, b) * rf; + } +#undef IQ2_S_COL +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +#undef IQ2_S_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_f32.cl new file mode 100644 index 000000000000..f4a07506393e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_f32.cl @@ -0,0 +1,91 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq2_xs_f32( + global const ushort * src0_qs, + global const uchar * src0_sc, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uchar4 sc = vload4(0, src0_sc + row + (i / 32) * m); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const float4 scale_f = convert_float4(d) * 0.25f * (0.5f + convert_float4((sc >> (uchar4)(4*((i / 16) & 1))) & (uchar4)(15))); + const half4 scale = convert_half4(scale_f); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 qs = convert_uint4(vload4(0, src0_qs + row + (ki / 8) * m)); + const uint4 code = qs >> (uint4)(9); + const uint4 sg = code | ((popcount(code) & (uint4)(1)) << (uint4)(7)); + const uint4 gi = qs & (uint4)(511); + const uint half_grid = (ki & 7) / 4; + const uint4 grid = (uint4)(iq2_xs_grid[2*gi.s0 + half_grid], iq2_xs_grid[2*gi.s1 + half_grid], + iq2_xs_grid[2*gi.s2 + half_grid], iq2_xs_grid[2*gi.s3 + half_grid]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 magnitude = convert_int4((grid >> (uint4)(8*j)) & (uint4)(255)); + const int4 signs = convert_int4((sg >> (uint4)((ki & 7) + j)) & (uint4)(1)); + const half4 w = convert_half4(magnitude * ((int4)(1) - 2*signs)) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_q8_1_dp4a.cl new file mode 100644 index 000000000000..c322803b9b09 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xs_q8_1_dp4a.cl @@ -0,0 +1,150 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq2_xs_pack(uint gv, uint sg, uint base) { + int v0 = (int)((gv >> 0) & 0xFF); if (sg & (1u << (base + 0))) { v0 = -v0; } + int v1 = (int)((gv >> 8) & 0xFF); if (sg & (1u << (base + 1))) { v1 = -v1; } + int v2 = (int)((gv >> 16) & 0xFF); if (sg & (1u << (base + 2))) { v2 = -v2; } + int v3 = (int)((gv >> 24) & 0xFF); if (sg & (1u << (base + 3))) { v3 = -v3; } + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq2_xs_q8_1_dp4a( + __global const ushort * src0_qs, + __global const uchar * src0_sc, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define IQ2_XS_GRID(i) iq2_xs_grid[(i)] + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + const uint scv = (uint)src0_sc[rrow + sub * (uint)m]; + const float dv = (float)src0_d[rrow + ib * (uint)m]; + const float dl0 = dv * (0.5f + (float)( scv & 0xFu)) * 0.25f; + const float dl1 = dv * (0.5f + (float)( scv >> 4) ) * 0.25f; + + const uint gb = rrow + (step >> 3) * (uint)m; + + uint4 qlo, qhi; + { + const uint q0 = (uint)src0_qs[gb + 0u * (uint)m]; + const uint q1 = (uint)src0_qs[gb + 1u * (uint)m]; + const uint q2 = (uint)src0_qs[gb + 2u * (uint)m]; + const uint q3 = (uint)src0_qs[gb + 3u * (uint)m]; + const uint gi0 = (q0 & 511u) << 1; + const uint gi1 = (q1 & 511u) << 1; + const uint gi2 = (q2 & 511u) << 1; + const uint gi3 = (q3 & 511u) << 1; + const uint s0 = iq2_xs_signs(q0 >> 9); + const uint s1 = iq2_xs_signs(q1 >> 9); + const uint s2 = iq2_xs_signs(q2 >> 9); + const uint s3 = iq2_xs_signs(q3 >> 9); + qlo.s0 = iq2_xs_pack(IQ2_XS_GRID(gi0 + 0u), s0, 0u); + qlo.s1 = iq2_xs_pack(IQ2_XS_GRID(gi0 + 1u), s0, 4u); + qlo.s2 = iq2_xs_pack(IQ2_XS_GRID(gi1 + 0u), s1, 0u); + qlo.s3 = iq2_xs_pack(IQ2_XS_GRID(gi1 + 1u), s1, 4u); + qhi.s0 = iq2_xs_pack(IQ2_XS_GRID(gi2 + 0u), s2, 0u); + qhi.s1 = iq2_xs_pack(IQ2_XS_GRID(gi2 + 1u), s2, 4u); + qhi.s2 = iq2_xs_pack(IQ2_XS_GRID(gi3 + 0u), s3, 0u); + qhi.s3 = iq2_xs_pack(IQ2_XS_GRID(gi3 + 1u), s3, 4u); + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) +#define IQ2_XS_COL(b) (dl0 * (float)dot4_q8a_v(qlo, (uint4)(sh_qa4[b][0])) \ + + dl1 * (float)dot4_q8a_v(qhi, (uint4)(sh_qa4[b][1]))) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + rf.s0 = IQ2_XS_COL(b+0); rf.s1 = IQ2_XS_COL(b+1); + rf.s2 = IQ2_XS_COL(b+2); rf.s3 = IQ2_XS_COL(b+3); + acc[g] += LD4(sh_d, b) * rf; + } +#undef IQ2_XS_COL +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +#undef IQ2_XS_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_f32.cl new file mode 100644 index 000000000000..5d6cc0dea965 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_f32.cl @@ -0,0 +1,90 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq2_xxs_f32( + global const uchar * src0_qs, + global const uint * src0_sas, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uint4 sas = vload4(0, src0_sas + row + (i / 32) * m); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const float4 scale_f = convert_float4(d) * 0.25f * (0.5f + convert_float4(sas >> (uint4)(28))); + const half4 scale = convert_half4(scale_f); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 gi = convert_uint4(vload4(0, src0_qs + row + (ki / 8) * m)); + const uint4 code = (sas >> (uint4)(7*((ki / 8) & 3))) & (uint4)(127); + const uint4 sg = code | ((popcount(code) & (uint4)(1)) << (uint4)(7)); + const uint half_grid = (ki & 7) / 4; + const uint4 grid = (uint4)(iq2_xxs_grid[2*gi.s0 + half_grid], iq2_xxs_grid[2*gi.s1 + half_grid], + iq2_xxs_grid[2*gi.s2 + half_grid], iq2_xxs_grid[2*gi.s3 + half_grid]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 magnitude = convert_int4((grid >> (uint4)(8*j)) & (uint4)(255)); + const int4 signs = convert_int4((sg >> (uint4)((ki & 7) + j)) & (uint4)(1)); + const half4 w = convert_half4(magnitude * ((int4)(1) - 2*signs)) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_q8_1_dp4a.cl new file mode 100644 index 000000000000..60cd268f3d39 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq2_xxs_q8_1_dp4a.cl @@ -0,0 +1,145 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq2_xxs_pack(uint gv, uint sg, uint base) { + int v0 = (int)((gv >> 0) & 0xFF); if (sg & (1u << (base + 0))) { v0 = -v0; } + int v1 = (int)((gv >> 8) & 0xFF); if (sg & (1u << (base + 1))) { v1 = -v1; } + int v2 = (int)((gv >> 16) & 0xFF); if (sg & (1u << (base + 2))) { v2 = -v2; } + int v3 = (int)((gv >> 24) & 0xFF); if (sg & (1u << (base + 3))) { v3 = -v3; } + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq2_xxs_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uint * src0_sas, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define IQ2_XXS_GRID(i) iq2_xxs_grid[(i)] + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + const uint aux = src0_sas[rrow + sub * (uint)m]; + const float dv = (float)src0_d[rrow + ib * (uint)m]; + const float dl = dv * (0.5f + (float)(aux >> 28)) * 0.25f; + + const uint gb = rrow + (step >> 3) * (uint)m; + + uint4 qlo, qhi; + { + const uint gi0 = (uint)src0_qs[gb + 0u * (uint)m] << 1; + const uint gi1 = (uint)src0_qs[gb + 1u * (uint)m] << 1; + const uint gi2 = (uint)src0_qs[gb + 2u * (uint)m] << 1; + const uint gi3 = (uint)src0_qs[gb + 3u * (uint)m] << 1; + const uint s0 = iq2_xxs_signs((aux >> 0) & 127u); + const uint s1 = iq2_xxs_signs((aux >> 7) & 127u); + const uint s2 = iq2_xxs_signs((aux >> 14) & 127u); + const uint s3 = iq2_xxs_signs((aux >> 21) & 127u); + qlo.s0 = iq2_xxs_pack(IQ2_XXS_GRID(gi0 + 0u), s0, 0u); + qlo.s1 = iq2_xxs_pack(IQ2_XXS_GRID(gi0 + 1u), s0, 4u); + qlo.s2 = iq2_xxs_pack(IQ2_XXS_GRID(gi1 + 0u), s1, 0u); + qlo.s3 = iq2_xxs_pack(IQ2_XXS_GRID(gi1 + 1u), s1, 4u); + qhi.s0 = iq2_xxs_pack(IQ2_XXS_GRID(gi2 + 0u), s2, 0u); + qhi.s1 = iq2_xxs_pack(IQ2_XXS_GRID(gi2 + 1u), s2, 4u); + qhi.s2 = iq2_xxs_pack(IQ2_XXS_GRID(gi3 + 0u), s3, 0u); + qhi.s3 = iq2_xxs_pack(IQ2_XXS_GRID(gi3 + 1u), s3, 4u); + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) +#define IQ2_XXS_COL(b) (dl * (float)(dot4_q8a_v(qlo, (uint4)(sh_qa4[b][0])) \ + + dot4_q8a_v(qhi, (uint4)(sh_qa4[b][1])))) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + rf.s0 = IQ2_XXS_COL(b+0); rf.s1 = IQ2_XXS_COL(b+1); + rf.s2 = IQ2_XXS_COL(b+2); rf.s3 = IQ2_XXS_COL(b+3); + acc[g] += LD4(sh_d, b) * rf; + } +#undef IQ2_XXS_COL +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +#undef IQ2_XXS_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_f32.cl new file mode 100644 index 000000000000..1a15ff86cdb2 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_f32.cl @@ -0,0 +1,92 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq3_s_f32( + global const uchar * src0_qs, + global const uchar * src0_sg, + global const uchar * src0_qh, + global const uchar * src0_sc, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uchar4 sc = vload4(0, src0_sc + row + (i / 64) * m); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const float4 scale_f = convert_float4(d) * (1.0f + 2.0f*convert_float4((sc >> (uchar4)(4*((i / 32) & 1))) & (uchar4)(15))); + const half4 scale = convert_half4(scale_f); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 qs = convert_uint4(vload4(0, src0_qs + row + (ki / 4) * m)); + const uint4 qh = convert_uint4(vload4(0, src0_qh + row + (ki / 32) * m)); + const uchar4 sg = vload4(0, src0_sg + row + (ki / 8) * m); + const uint4 gi = qs | (((qh >> (uint4)(((ki / 4) & 7))) & (uint4)(1)) << (uint4)(8)); + const uint4 grid = (uint4)(iq3_s_grid[gi.s0], iq3_s_grid[gi.s1], + iq3_s_grid[gi.s2], iq3_s_grid[gi.s3]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 magnitude = convert_int4((grid >> (uint4)(8*j)) & (uint4)(255)); + const int4 signs = convert_int4((sg >> (uchar4)((ki & 7) + j)) & (uchar4)(1)); + const half4 w = convert_half4(magnitude * ((int4)(1) - 2*signs)) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_q8_1_dp4a.cl new file mode 100644 index 000000000000..43cb38f72067 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_s_q8_1_dp4a.cl @@ -0,0 +1,154 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq3_s_pack(uint gv, uint sg, uint base) { + int v0 = (int)((gv >> 0) & 0xFF); if (sg & (1u << (base + 0))) { v0 = -v0; } + int v1 = (int)((gv >> 8) & 0xFF); if (sg & (1u << (base + 1))) { v1 = -v1; } + int v2 = (int)((gv >> 16) & 0xFF); if (sg & (1u << (base + 2))) { v2 = -v2; } + int v3 = (int)((gv >> 24) & 0xFF); if (sg & (1u << (base + 3))) { v3 = -v3; } + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +#define IQ3_S_GEMM_GRID(i) iq3_s_grid[(i)] + +inline uint iq3_s_load(__global const uchar * qs, uint qsb, uint qhb, uint m, + uint u, uint sgv, uint base) { + const uint gidx = (uint)qs[qsb + u * m] | (((qhb >> u) & 1u) << 8); + return iq3_s_pack(IQ3_S_GEMM_GRID(gidx), sgv, base); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq3_s_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uchar * src0_sg, + __global const uchar * src0_qh, + __global const uchar * src0_sc, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + + const uint ib = sub >> 3; + const uint sb = sub & 7u; + + const uint scb = (uint)src0_sc[rrow + (ib*(QK_K/64) + (sb >> 1)) * (uint)m]; + const uint nib = (sb & 1u) ? (scb >> 4) : (scb & 0xFu); + const float d_w = (float)src0_d[rrow + ib * (uint)m] * (float)(1 + 2*nib); + + const uint qhb = (uint)src0_qh[rrow + (ib*(QK_K/32) + sb) * (uint)m]; + const uint qsb = rrow + (ib*(QK_K/4) + 8*sb) * (uint)m; + const uint sgb = rrow + (ib*(QK_K/8) + 4*sb) * (uint)m; + + const uint sg0 = (uint)src0_sg[sgb + 0 * (uint)m]; + const uint sg1 = (uint)src0_sg[sgb + 1 * (uint)m]; + const uint sg2 = (uint)src0_sg[sgb + 2 * (uint)m]; + const uint sg3 = (uint)src0_sg[sgb + 3 * (uint)m]; + + uint8 qw; + qw.s0 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 0u, sg0, 0u); + qw.s1 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 1u, sg0, 4u); + qw.s2 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 2u, sg1, 0u); + qw.s3 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 3u, sg1, 4u); + qw.s4 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 4u, sg2, 0u); + qw.s5 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 5u, sg2, 4u); + qw.s6 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 6u, sg3, 0u); + qw.s7 = iq3_s_load(src0_qs, qsb, qhb, (uint)m, 7u, sg3, 4u); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define TDOT4(T) dot8_q8a_v(qw, (uint4)(sh_qa4[T][0]), (uint4)(sh_qa4[T][1])) + rf.s0 = (float)TDOT4(b+0); rf.s1 = (float)TDOT4(b+1); + rf.s2 = (float)TDOT4(b+2); rf.s3 = (float)TDOT4(b+3); + acc[g] += d_w * LD4(sh_d, b) * rf; + } +#undef TDOT4 +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_f32.cl new file mode 100644 index 000000000000..af58e850cc2e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_f32.cl @@ -0,0 +1,89 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_iq3_xxs_f32( + global const uchar * src0_qs, + global const uint * src0_sas, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const uint4 sas = vload4(0, src0_sas + row + (i / 32) * m); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const float4 scale_f = convert_float4(d) * 0.5f * (0.5f + convert_float4(sas >> (uint4)(28))); + const half4 scale = convert_half4(scale_f); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uint4 gi = convert_uint4(vload4(0, src0_qs + row + (ki / 4) * m)); + const uint4 code = (sas >> (uint4)(7*((ki / 8) & 3))) & (uint4)(127); + const uint4 sg = code | ((popcount(code) & (uint4)(1)) << (uint4)(7)); + const uint4 grid = (uint4)(iq3_xxs_grid[gi.s0], iq3_xxs_grid[gi.s1], + iq3_xxs_grid[gi.s2], iq3_xxs_grid[gi.s3]); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 magnitude = convert_int4((grid >> (uint4)(8*j)) & (uint4)(255)); + const int4 signs = convert_int4((sg >> (uint4)((ki & 7) + j)) & (uint4)(1)); + const half4 w = convert_half4(magnitude * ((int4)(1) - 2*signs)) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_q8_1_dp4a.cl new file mode 100644 index 000000000000..2ade6e2cf4c2 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_iq3_xxs_q8_1_dp4a.cl @@ -0,0 +1,137 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint iq3_xxs_pack(uint gv, uint sg, uint base) { + int v0 = (int)((gv >> 0) & 0xFF); if (sg & (1u << (base + 0))) { v0 = -v0; } + int v1 = (int)((gv >> 8) & 0xFF); if (sg & (1u << (base + 1))) { v1 = -v1; } + int v2 = (int)((gv >> 16) & 0xFF); if (sg & (1u << (base + 2))) { v2 = -v2; } + int v3 = (int)((gv >> 24) & 0xFF); if (sg & (1u << (base + 3))) { v3 = -v3; } + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_iq3_xxs_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uint * src0_sas, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + + const uint ib = sub >> 3; + const uint aux = src0_sas[rrow + sub*(uint)m]; + const float d_w = (float)src0_d[rrow + ib*(uint)m] * (0.5f + (float)(aux >> 28)) * 0.5f; + const uint sg0 = iq3_xxs_signs( aux & 127u); + const uint sg1 = iq3_xxs_signs((aux >> 7) & 127u); + const uint sg2 = iq3_xxs_signs((aux >> 14) & 127u); + const uint sg3 = iq3_xxs_signs((aux >> 21) & 127u); + const uint qsb = rrow + sub*8u*(uint)m; + + uint8 qw; + qw.s0 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 0u*(uint)m]], sg0, 0u); + qw.s1 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 1u*(uint)m]], sg0, 4u); + qw.s2 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 2u*(uint)m]], sg1, 0u); + qw.s3 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 3u*(uint)m]], sg1, 4u); + qw.s4 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 4u*(uint)m]], sg2, 0u); + qw.s5 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 5u*(uint)m]], sg2, 4u); + qw.s6 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 6u*(uint)m]], sg3, 0u); + qw.s7 = iq3_xxs_pack(iq3_xxs_grid[src0_qs[qsb + 7u*(uint)m]], sg3, 4u); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define TDOT4(T) dot8_q8a_v(qw, (uint4)(sh_qa4[T][0]), (uint4)(sh_qa4[T][1])) + rf.s0 = (float)TDOT4(b+0); rf.s1 = (float)TDOT4(b+1); + rf.s2 = (float)TDOT4(b+2); rf.s3 = (float)TDOT4(b+3); + acc[g] += d_w * LD4(sh_d, b) * rf; + } +#undef TDOT4 +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_f32.cl new file mode 100644 index 000000000000..b7885841f91b --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_f32.cl @@ -0,0 +1,80 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_q2_0_f32( + global const uchar * src0_qs, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + float8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const float4 scale = convert_float4(vload4(0, src0_d + row + (i / 64) * m)); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uchar4 q = vload4(0, src0_qs + row + (ki / 4) * m); + #pragma unroll + for (int j = 0; j < 4; ++j) { + float8 b; + b.s0123 = convert_float4(read_imageh(src1, gy * 2 + (ki + j) * n_4)); + b.s4567 = convert_float4(read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4)); + const int4 v = convert_int4((q >> (uchar4)(2*j)) & (uchar4)(3)) - (int4)(1); + const float4 w = convert_float4(v) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_q8_1_dp4a.cl new file mode 100644 index 000000000000..d99e166f1917 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_0_q8_1_dp4a.cl @@ -0,0 +1,127 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint q2_0_pack(uchar q) { + return (((uint)(q & 3) - 1u) & 255u) + | (((((uint)q >> 2) & 3u) - 1u) & 255u) << 8 + | (((((uint)q >> 4) & 3u) - 1u) & 255u) << 16 + | (((((uint)q >> 6) & 3u) - 1u) & 255u) << 24; +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q2_0_q8_1_dp4a( + __global const uchar * src0_qs, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + + const uint ib = sub >> 1; + const float d_w = (float)src0_d[rrow + ib*(uint)m]; + const uint qsb = rrow + sub*8u*(uint)m; + + uint8 qw; + qw.s0 = q2_0_pack(src0_qs[qsb + 0u*(uint)m]); + qw.s1 = q2_0_pack(src0_qs[qsb + 1u*(uint)m]); + qw.s2 = q2_0_pack(src0_qs[qsb + 2u*(uint)m]); + qw.s3 = q2_0_pack(src0_qs[qsb + 3u*(uint)m]); + qw.s4 = q2_0_pack(src0_qs[qsb + 4u*(uint)m]); + qw.s5 = q2_0_pack(src0_qs[qsb + 5u*(uint)m]); + qw.s6 = q2_0_pack(src0_qs[qsb + 6u*(uint)m]); + qw.s7 = q2_0_pack(src0_qs[qsb + 7u*(uint)m]); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define TDOT4(T) dot8_q8a_v(qw, (uint4)(sh_qa4[T][0]), (uint4)(sh_qa4[T][1])) + rf.s0 = (float)TDOT4(b+0); rf.s1 = (float)TDOT4(b+1); + rf.s2 = (float)TDOT4(b+2); rf.s3 = (float)TDOT4(b+3); + acc[g] += d_w * LD4(sh_d, b) * rf; + } +#undef TDOT4 +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_f32.cl new file mode 100644 index 000000000000..2749e1c14556 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_f32.cl @@ -0,0 +1,83 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_q2_k_f32( + global const uchar * src0_qs, + global const uchar * src0_sc, + global const half * src0_dm, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const half8 dm = vload8(0, src0_dm + 2 * (row + (i / 256) * m)); + const uchar4 sc = vload4(0, src0_sc + row + (i / 16) * m); + const half4 scale = convert_half4(convert_float4(dm.s0246) * convert_float4(sc & (uchar4)(15))); + const half4 mval = convert_half4(convert_float4(dm.s1357) * convert_float4(sc >> (uchar4)(4))); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uchar4 bits = vload4(0, src0_qs + row + (ki / 4) * m); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const half4 w = convert_half4((bits >> (uchar4)(2 * j)) & (uchar4)(3)) * scale - mval; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_q8_1_dp4a.cl new file mode 100644 index 000000000000..7db7e6d71f74 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q2_k_q8_1_dp4a.cl @@ -0,0 +1,146 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline uint q2_k_pack(uint pk) { + return ( (pk ) & 3u) + | (((pk >> 2) & 3u) << 8) + | (((pk >> 4) & 3u) << 16) + | (((pk >> 6) & 3u) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +#define KQ_STAGE(p) vload4(0, (p)) + +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q2_k_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uchar * src0_sc, + __global const half * src0_dm, // half pairs: d, dmin + __global const uint * src1_qa, // q8_1 activations int8 (as uint, 4/elem) [N, K] + __global const half * src1_da, // q8_1 per-block scale [N, K/32] + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local float sh_s [TILESIZE_N][2]; // per-16 activation sums, in qa units + __local half sh_d [TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; + + const half2 dm = vload2(rrow + ib * (uint)m, src0_dm); + const float dv = (float)dm.s0; + const float dmv = (float)dm.s1; + + const uint scb = rrow + (sub << 1) * (uint)m; + const uint sc0 = (uint)src0_sc[scb + 0u * (uint)m]; + const uint sc1 = (uint)src0_sc[scb + 1u * (uint)m]; + const float dl0 = dv * (float)( sc0 & 0xFu); + const float ml0 = dmv * (float)( sc0 >> 4); + const float dl1 = dv * (float)( sc1 & 0xFu); + const float ml1 = dmv * (float)( sc1 >> 4); + + const uint qsb = rrow + (step >> 2) * (uint)m; + uint4 qlo, qhi; + qlo.s0 = q2_k_pack((uint)src0_qs[qsb + 0u * (uint)m]); + qlo.s1 = q2_k_pack((uint)src0_qs[qsb + 1u * (uint)m]); + qlo.s2 = q2_k_pack((uint)src0_qs[qsb + 2u * (uint)m]); + qlo.s3 = q2_k_pack((uint)src0_qs[qsb + 3u * (uint)m]); + qhi.s0 = q2_k_pack((uint)src0_qs[qsb + 4u * (uint)m]); + qhi.s1 = q2_k_pack((uint)src0_qs[qsb + 5u * (uint)m]); + qhi.s2 = q2_k_pack((uint)src0_qs[qsb + 6u * (uint)m]); + qhi.s3 = q2_k_pack((uint)src0_qs[qsb + 7u * (uint)m]); + + for (uint idx = lid; idx < TILESIZE_N * 2u; idx += 64u) { + const uint t = idx >> 1; + const uint h = idx & 1u; + const uint c = col_base + t; + const bool ok = c < (uint)n_no_padding; + const uint4 w = ok ? KQ_STAGE(src1_qa + c * k_u + (step >> 2) + (h << 2)) + : (uint4)(0u); + sh_qa4[t][h] = w; + int s = 0; + s = dot_acc_sat_4x8packed_ss_int(w.x, 0x01010101u, s); + s = dot_acc_sat_4x8packed_ss_int(w.y, 0x01010101u, s); + s = dot_acc_sat_4x8packed_ss_int(w.z, 0x01010101u, s); + s = dot_acc_sat_4x8packed_ss_int(w.w, 0x01010101u, s); + sh_s[t][h] = (float)s; + if (h == 0u) { + sh_d[t] = ok ? src1_da[c * k_b + sub] : (half)0; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) +#define Q2_K_COL(b) (dl0 * (float)dot4_q8a_v(qlo, (uint4)(sh_qa4[b][0])) - ml0 * sh_s[b][0] + \ + dl1 * (float)dot4_q8a_v(qhi, (uint4)(sh_qa4[b][1])) - ml1 * sh_s[b][1]) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + rf.s0 = Q2_K_COL(b+0); rf.s1 = Q2_K_COL(b+1); + rf.s2 = Q2_K_COL(b+2); rf.s3 = Q2_K_COL(b+3); + acc[g] += LD4(sh_d, b) * rf; + } +#undef Q2_K_COL +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_f32.cl new file mode 100644 index 000000000000..2851146787ec --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_f32.cl @@ -0,0 +1,92 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +__attribute__((qcom_reqd_sub_group_size("full"))) +#endif +kernel void kernel_gemm_noshuffle_q3_k_f32( + global const uchar * src0_qs, + global const uchar * src0_hm, + global const uint * src0_sc, + global const half * src0_d, + read_only image1d_buffer_t src1, + global float * dst, + ulong offsetd, + int m, + int n, + int k, + int n_no_padding +) { + dst = (global float *)((global char *)dst + offsetd); + const int gy = get_global_id(0); + const int row = get_global_id(1) * 4; + const int n_4 = n / 4; + if (row >= m) { + return; + } + + half8 c0 = 0, c1 = 0, c2 = 0, c3 = 0; + for (int i = 0; i < k; i += 16) { + const int is = (i / 16) & 15; + const int word = is >> 2; + const int shift = 8 * (is & 3); + const int sc_base = row + 3 * (i / 256) * m; + const uint4 low = vload4(0, src0_sc + sc_base + (word & 1) * m) >> (uint4)(4 * (word >> 1)); + const uint4 high = vload4(0, src0_sc + sc_base + 2 * m) >> (uint4)(2 * word); + const int4 sc = convert_int4(((low >> (uint4)(shift)) & (uint4)(15)) | (((high >> (uint4)(shift)) & (uint4)(3)) << (uint4)(4))) - (int4)(32); + const half4 d = vload4(0, src0_d + row + (i / 256) * m); + const half4 scale = convert_half4(convert_float4(d) * convert_float4(sc)); + + for (int l = 0; l < 16; l += 4) { + const int ki = i + l; + const uchar4 bits = vload4(0, src0_qs + row + (ki / 4) * m); + const uchar4 hbits = vload4(0, src0_hm + row + (ki / 8) * m); + #pragma unroll + for (int j = 0; j < 4; ++j) { + half8 b; + b.s0123 = read_imageh(src1, gy * 2 + (ki + j) * n_4); + b.s4567 = read_imageh(src1, gy * 2 + 1 + (ki + j) * n_4); + const int4 low = convert_int4((bits >> (uchar4)(2 * j)) & (uchar4)(3)); + const int4 high = convert_int4((hbits >> (uchar4)((ki & 7) + j)) & (uchar4)(1)); + const half4 w = convert_half4(low - (int4)(4) + (int4)(4) * high) * scale; + c0 += b * w.s0; + c1 += b * w.s1; + c2 += b * w.s2; + c3 += b * w.s3; + } + } + } + + int idx = gy * 8 * m + row; + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s0, c1.s0, c2.s0, c3.s0), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s1, c1.s1, c2.s1, c3.s1), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s2, c1.s2, c2.s2, c3.s2), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s3, c1.s3, c2.s3, c3.s3), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s4, c1.s4, c2.s4, c3.s4), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s5, c1.s5, c2.s5, c3.s5), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s6, c1.s6, c2.s6, c3.s6), 0, dst + idx); + idx += m; + } + if (idx + 3 < m * n_no_padding) { + vstore4((float4)(c0.s7, c1.s7, c2.s7, c3.s7), 0, dst + idx); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_q8_1_dp4a.cl new file mode 100644 index 000000000000..04fcca0b3376 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q3_k_q8_1_dp4a.cl @@ -0,0 +1,160 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#define QK_K 256 + +#ifndef TILESIZE_N +#define TILESIZE_N 32 +#endif + +inline int q3_k_scale(uint sc0, uint sc1, uint sc2, uint is) { + const uint w = is >> 2; + const uint sh = 8u * (is & 3u); + const uint tb = (sc2 >> sh) & 0xFFu; + uint v; + if (w == 0u) { v = ( (sc0 >> sh) & 0xFu) | (((tb >> 0) & 3u) << 4); } + else if (w == 1u) { v = ( (sc1 >> sh) & 0xFu) | (((tb >> 2) & 3u) << 4); } + else if (w == 2u) { v = (((sc0 >> sh) >> 4) & 0xFu) | (((tb >> 4) & 3u) << 4); } + else { v = (((sc1 >> sh) >> 4) & 0xFu) | (((tb >> 6) & 3u) << 4); } + return (int)v - 32; +} + +inline uint q3_k_pack(uint pk, uint hb) { + int v0 = (int)((pk ) & 3u) - 4 + 4*(int)((hb ) & 1u); + int v1 = (int)((pk >> 2) & 3u) - 4 + 4*(int)((hb >> 1) & 1u); + int v2 = (int)((pk >> 4) & 3u) - 4 + 4*(int)((hb >> 2) & 1u); + int v3 = (int)((pk >> 6) & 3u) - 4 + 4*(int)((hb >> 3) & 1u); + return ((uint)v0 & 0xFFu) | (((uint)v1 & 0xFFu) << 8) + | (((uint)v2 & 0xFFu) << 16) | (((uint)v3 & 0xFFu) << 24); +} + +// Pass staged operands by value; local dp4a operands miscompile on X2. +#define KQ_STAGE(p) vload4(0, (p)) + +inline int dot4_q8a_v(uint4 qw, uint4 a) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q3_k_q8_1_dp4a( + __global const uchar * src0_qs, + __global const uchar * src0_hm, + __global const uint * src0_sc, + __global const half * src0_d, + __global const uint * src1_qa, // q8_1 activations int8 (as uint, 4/elem) [N, K] + __global const half * src1_da, // q8_1 per-block scale [N, K/32] + __global float * dst, + ulong offsetd, + int m, // output features (rows) + int n_no_padding, // tokens (cols) + int k // K (== ne00) +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) acc[g] = (float4)(0.0f); + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint ib = sub >> 3; // super-block along K + const uint sb = sub & 7u; + + const uint scb = rrow + (3u * ib) * (uint)m; + const uint sc0 = src0_sc[scb + 0u * (uint)m]; + const uint sc1 = src0_sc[scb + 1u * (uint)m]; + const uint sc2 = src0_sc[scb + 2u * (uint)m]; + + const float d_w = (float)src0_d[rrow + ib * (uint)m]; + const float dl0 = d_w * (float)q3_k_scale(sc0, sc1, sc2, 2u*sb + 0u); + const float dl1 = d_w * (float)q3_k_scale(sc0, sc1, sc2, 2u*sb + 1u); + + const uint qsb = rrow + (step >> 2) * (uint)m; + const uint hmb = rrow + (step >> 3) * (uint)m; + + uint4 qlo, qhi; + { + const uint h0 = (uint)src0_hm[hmb + 0u * (uint)m]; + const uint h1 = (uint)src0_hm[hmb + 1u * (uint)m]; + const uint h2 = (uint)src0_hm[hmb + 2u * (uint)m]; + const uint h3 = (uint)src0_hm[hmb + 3u * (uint)m]; + qlo.s0 = q3_k_pack((uint)src0_qs[qsb + 0u * (uint)m], h0 & 0xFu); + qlo.s1 = q3_k_pack((uint)src0_qs[qsb + 1u * (uint)m], (h0 >> 4) & 0xFu); + qlo.s2 = q3_k_pack((uint)src0_qs[qsb + 2u * (uint)m], h1 & 0xFu); + qlo.s3 = q3_k_pack((uint)src0_qs[qsb + 3u * (uint)m], (h1 >> 4) & 0xFu); + qhi.s0 = q3_k_pack((uint)src0_qs[qsb + 4u * (uint)m], h2 & 0xFu); + qhi.s1 = q3_k_pack((uint)src0_qs[qsb + 5u * (uint)m], (h2 >> 4) & 0xFu); + qhi.s2 = q3_k_pack((uint)src0_qs[qsb + 6u * (uint)m], h3 & 0xFu); + qhi.s3 = q3_k_pack((uint)src0_qs[qsb + 7u * (uint)m], (h3 >> 4) & 0xFu); + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? KQ_STAGE(src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define Q3_K_COL(T) (dl0 * (float)dot4_q8a_v(qlo, (uint4)(sh_qa4[T][0])) \ + + dl1 * (float)dot4_q8a_v(qhi, (uint4)(sh_qa4[T][1]))) + rf.s0 = Q3_K_COL(b+0); rf.s1 = Q3_K_COL(b+1); + rf.s2 = Q3_K_COL(b+2); rf.s3 = Q3_K_COL(b+3); +#undef Q3_K_COL + acc[g] += LD4(sh_d, b) * rf; + } +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) dst[(c0 + 0) * (uint)m + row] = a.s0; + if (c0 + 1 < (uint)n_no_padding) dst[(c0 + 1) * (uint)m + row] = a.s1; + if (c0 + 2 < (uint)n_no_padding) dst[(c0 + 2) * (uint)m + row] = a.s2; + if (c0 + 3 < (uint)n_no_padding) dst[(c0 + 3) * (uint)m + row] = a.s3; + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_0_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_0_q8_1_dp4a.cl index 446a8eb18483..6418d0f8ff44 100644 --- a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_0_q8_1_dp4a.cl +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_0_q8_1_dp4a.cl @@ -125,3 +125,129 @@ kernel void kernel_gemm_noshuffle_q4_0_q8_1_dp4a( } #undef NGROUPS } + +// Stage each 32-K activation block as two uint4 values. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q4_0_q8_1_dp4a_act_vload4( + __global const ushort * src0_q, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global const half * src1_sa, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + __local half sh_s[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + acc[g] = (float4)(0.0f); + } + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + + const float d_w = (float)src0_d[rrow + sub * (uint)m]; + + const uint qsbase = rrow + (step >> 2) * (uint)m; + uint8 qw; + qw.s0 = EXP4(src0_q[qsbase + 0 * m]); + qw.s1 = EXP4(src0_q[qsbase + 1 * m]); + qw.s2 = EXP4(src0_q[qsbase + 2 * m]); + qw.s3 = EXP4(src0_q[qsbase + 3 * m]); + qw.s4 = EXP4(src0_q[qsbase + 4 * m]); + qw.s5 = EXP4(src0_q[qsbase + 5 * m]); + qw.s6 = EXP4(src0_q[qsbase + 6 * m]); + qw.s7 = EXP4(src0_q[qsbase + 7 * m]); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + sh_s[lid] = (c < (uint)n_no_padding) ? src1_sa[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define DOTV(T) dot8_q8a_v(qw, sh_qa4[T][0], sh_qa4[T][1]) + rf.s0 = (float)DOTV(b+0); + rf.s1 = (float)DOTV(b+1); + rf.s2 = (float)DOTV(b+2); + rf.s3 = (float)DOTV(b+3); +#undef DOTV + + acc[g] += d_w * (LD4(sh_d, b) * rf - 8.0f * LD4(sh_s, b)); + } +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) { + dst[(c0 + 0) * (uint)m + row] = a.s0; + } + if (c0 + 1 < (uint)n_no_padding) { + dst[(c0 + 1) * (uint)m + row] = a.s1; + } + if (c0 + 2 < (uint)n_no_padding) { + dst[(c0 + 2) * (uint)m + row] = a.s2; + } + if (c0 + 3 < (uint)n_no_padding) { + dst[(c0 + 3) * (uint)m + row] = a.s3; + } + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_K_f32_tiled_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_K_f32_tiled_dp4a.cl new file mode 100644 index 000000000000..af642b4df611 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_K_f32_tiled_dp4a.cl @@ -0,0 +1,131 @@ +// DP4A GEMM for the canonical 64-row Q4_K layout. +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#ifdef cl_khr_integer_dot_product +#pragma OPENCL EXTENSION cl_khr_integer_dot_product : enable +#endif + +#ifdef cl_qcom_reqd_sub_group_size +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#endif + +#define QK_K 256 +#define TILE_ROWS 64 +#define NTILES 4 +#define BN_DP 8 +#define WG_THREADS (NTILES * TILE_ROWS) + +inline void q4k_scale_min(int j, __global const uchar * q, uchar * d, uchar * m) { + if (j < 4) { + *d = q[j] & 0x3F; + *m = q[j+4] & 0x3F; + } else { + *d = (q[j+4] & 0x0F) | ((q[j-4] & 0xC0) >> 2); + *m = ((q[j+4] >> 4) & 0x0F) | ((q[j] & 0xC0) >> 2); + } +} + +// dp4a GEMM over the tiled q4_K layout (ne1 > 1) with a q8_1 activation; per 32-element sub-block: +// acc += d*sd*qad*dp4a(q, qa) - dm*sm*qas +#if defined(ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_gemm_noshuffle_q4_K_f32_tiled_dp4a( + __global uint4 * src0_q, + __global half * src0_d, + __global half * src0_dm, + __global uchar * src0_s, + __global uint * qa, // q8_1 int8 activation, 4/uint [ne11][ne00/4] + __global half * qad, // q8_1 per-32-block scale [ne11][ne00/32] + __global half * qas, // q8_1 per-32-block sum (qad*Sum)[ne11][ne00/32] + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne11 +) { + int rit = get_local_id(0); + int sg = get_local_id(1); + int lid = sg * TILE_ROWS + rit; + int row = get_group_id(0) * WG_THREADS + lid; + int rt = row / TILE_ROWS; + int col0 = get_global_id(2) * BN_DP; + int nb = ne00 / QK_K; + int qcs = ne00 / 4; + int dcs = ne00 / 32; + + const bool row_ok = row < ne01; + __local uint sh_qa[BN_DP * 64]; + __local half sh_qad[BN_DP * 8]; + __local half sh_qas[BN_DP * 8]; + + float acc[BN_DP]; + #pragma unroll + for (int j = 0; j < BN_DP; ++j) acc[j] = 0.0f; + + for (int sb = 0; sb < nb; ++sb) { + for (int p = lid; p < BN_DP * 64; p += WG_THREADS) { + int j = p >> 6, u = p & 63, c = col0 + j; + sh_qa[p] = (c < ne11) ? qa[c * qcs + sb * 64 + u] : 0u; + } + for (int p = lid; p < BN_DP * 8; p += WG_THREADS) { + int j = p >> 3, b = p & 7, c = col0 + j; + sh_qad[p] = (c < ne11) ? qad[c * dcs + sb * 8 + b] : (half)0; + sh_qas[p] = (c < ne11) ? qas[c * dcs + sb * 8 + b] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + + if (row_ok) { + int tile_blk = rt * nb + sb; + float dval = (float)src0_d [tile_blk * TILE_ROWS + rit]; + float dmval = (float)src0_dm[tile_blk * TILE_ROWS + rit]; + __global uchar * sc = src0_s + (tile_blk * TILE_ROWS + rit) * 12; + + uint q[32]; + #pragma unroll + for (int g = 0; g < 8; ++g) { + uint4 v = src0_q[(tile_blk * 8 + g) * TILE_ROWS + rit]; + q[g*4+0] = v.x; q[g*4+1] = v.y; q[g*4+2] = v.z; q[g*4+3] = v.w; + } + + for (int is = 0; is < 8; ++is) { + uchar sd, sm; + q4k_scale_min(is, sc, &sd, &sm); + float scl = dval * (float)sd, mnv = dmval * (float)sm; + + uint cw[8]; + #pragma unroll + for (int t = 0; t < 8; ++t) { + uint pk = 0; + #pragma unroll + for (int u = 0; u < 4; ++u) { + int e = is * 32 + t * 4 + u; + uint code = (q[e >> 3] >> ((e & 7) * 4)) & 0xF; + pk |= (code & 0xFF) << (u * 8); + } + cw[t] = pk; + } + #pragma unroll + for (int j = 0; j < BN_DP; ++j) { + __local uint * a = sh_qa + j * 64 + is * 8; + int raw = 0; + #pragma unroll + for (int t = 0; t < 8; ++t) raw = dot_acc_sat_4x8packed_ss_int(cw[t], a[t], raw); + acc[j] += scl * (float)sh_qad[j*8 + is] * (float)raw + - mnv * (float)sh_qas[j*8 + is]; + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (row_ok) { + dst = (global float*)((global char*)dst + offsetd); + #pragma unroll + for (int j = 0; j < BN_DP; ++j) { + int c = col0 + j; + if (c < ne11) dst[(ulong)c * ne01 + row] = acc[j]; + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_k_q8_1_dp4a.cl index a3b39b6aa984..69cabb946ce5 100644 --- a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_k_q8_1_dp4a.cl +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q4_k_q8_1_dp4a.cl @@ -279,3 +279,141 @@ kernel void kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg( } #undef NGROUPS } + +// Stage each 32-K activation block as two uint4 values. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q4_k_q8_1_dp4a_act_vload4( + __global const ushort * src0_q, + __global const uchar * src0_s, + __global const half * src0_d, + __global const half * src0_dm, + __global const uint * src1_qa, + __global const half * src1_da, + __global const half * src1_sa, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k, + uchar mask_d6, + uchar mask_d4, + uchar mask_hi2 +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + __local half sh_s[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + acc[g] = (float4)(0.0f); + } + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint sb_idx = step / QK_K; + const uint sub_idx = sub & 7; + + const float dd = (float)src0_d [rrow + sb_idx * m]; + const float dmm = (float)src0_dm[rrow + sb_idx * m]; + global const uchar * sc = src0_s + sb_idx * K_SCALE_SIZE * (uint)m + rrow; + uchar sv, mn; + get_scale_min_k4(sub_idx, sc, (uint)m, &sv, &mn, mask_d6, mask_d4, mask_hi2); + const float scale = dd * (float)sv; + const float minv = dmm * (float)mn; + + const uint wbase = rrow + (step >> 2) * (uint)m; + uint8 qw; + qw.s0 = EXP4(src0_q[wbase + 0 * m]); + qw.s1 = EXP4(src0_q[wbase + 1 * m]); + qw.s2 = EXP4(src0_q[wbase + 2 * m]); + qw.s3 = EXP4(src0_q[wbase + 3 * m]); + qw.s4 = EXP4(src0_q[wbase + 4 * m]); + qw.s5 = EXP4(src0_q[wbase + 5 * m]); + qw.s6 = EXP4(src0_q[wbase + 6 * m]); + qw.s7 = EXP4(src0_q[wbase + 7 * m]); + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + sh_s[lid] = (c < (uint)n_no_padding) ? src1_sa[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define DOTV(T) dot8_q8a_v(qw, sh_qa4[T][0], sh_qa4[T][1]) + rf.s0 = (float)DOTV(b+0); + rf.s1 = (float)DOTV(b+1); + rf.s2 = (float)DOTV(b+2); + rf.s3 = (float)DOTV(b+3); +#undef DOTV + acc[g] += scale * LD4(sh_d, b) * rf - minv * LD4(sh_s, b); + } +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) { + dst[(c0 + 0) * (uint)m + row] = a.s0; + } + if (c0 + 1 < (uint)n_no_padding) { + dst[(c0 + 1) * (uint)m + row] = a.s1; + } + if (c0 + 2 < (uint)n_no_padding) { + dst[(c0 + 2) * (uint)m + row] = a.s2; + } + if (c0 + 3 < (uint)n_no_padding) { + dst[(c0 + 3) * (uint)m + row] = a.s3; + } + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q5_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q5_k_q8_1_dp4a.cl index aaeed68f615c..eef474b47f7b 100644 --- a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q5_k_q8_1_dp4a.cl +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q5_k_q8_1_dp4a.cl @@ -162,3 +162,141 @@ kernel void kernel_gemm_noshuffle_q5_k_q8_1_dp4a( } #undef NGROUPS } + +// Stage each 32-K activation block as two uint4 values. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q5_k_q8_1_dp4a_act_vload4( + __global const ushort * src0_q, + __global const uchar * src0_qh, + __global const uchar * src0_s, + __global const half * src0_d, + __global const half * src0_dm, + __global const uint * src1_qa, + __global const half * src1_da, + __global const half * src1_sa, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k, + uchar mask_d6, + uchar mask_d4, + uchar mask_hi2 +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint num_superblocks = (uint)k / QK_K; + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + __local half sh_s[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + acc[g] = (float4)(0.0f); + } + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint sb_idx = step / QK_K; + const uint sub_idx = sub & 7; + + const float dd = (float)src0_d [rrow + sb_idx * m]; + const float dmm = (float)src0_dm[rrow + sb_idx * m]; + global const uchar * sc = src0_s + rrow * num_superblocks * K_SCALE_SIZE + sb_idx * K_SCALE_SIZE; + uchar sv, mn; + get_scale_min_k4(sub_idx, sc, &sv, &mn, mask_d6, mask_d4, mask_hi2); + const float scale = dd * (float)sv; + const float minv = dmm * (float)mn; + + const uint wbase = rrow + (step >> 2) * (uint)m; + const uint qhbase = rrow + (step >> 3) * (uint)m; + uint8 qw; +#define QWU(u) ( EXP4((uint)src0_q[wbase + (uint)(u) * m]) \ + | EXP1( (uint)((src0_qh[qhbase + (uint)((u) >> 1) * m] >> (((u) & 1) * 4)) & 0x0Fu) ) ) + qw.s0 = QWU(0); qw.s1 = QWU(1); qw.s2 = QWU(2); qw.s3 = QWU(3); + qw.s4 = QWU(4); qw.s5 = QWU(5); qw.s6 = QWU(6); qw.s7 = QWU(7); +#undef QWU + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + sh_s[lid] = (c < (uint)n_no_padding) ? src1_sa[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define DOTV(T) dot8_q8a_v(qw, sh_qa4[T][0], sh_qa4[T][1]) + rf.s0 = (float)DOTV(b+0); + rf.s1 = (float)DOTV(b+1); + rf.s2 = (float)DOTV(b+2); + rf.s3 = (float)DOTV(b+3); +#undef DOTV + acc[g] += scale * LD4(sh_d, b) * rf - minv * LD4(sh_s, b); + } +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) { + dst[(c0 + 0) * (uint)m + row] = a.s0; + } + if (c0 + 1 < (uint)n_no_padding) { + dst[(c0 + 1) * (uint)m + row] = a.s1; + } + if (c0 + 2 < (uint)n_no_padding) { + dst[(c0 + 2) * (uint)m + row] = a.s2; + } + if (c0 + 3 < (uint)n_no_padding) { + dst[(c0 + 3) * (uint)m + row] = a.s3; + } + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q6_k_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q6_k_q8_1_dp4a.cl index 382d79fddafc..f17403a722e4 100644 --- a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q6_k_q8_1_dp4a.cl +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q6_k_q8_1_dp4a.cl @@ -142,3 +142,117 @@ kernel void kernel_gemm_noshuffle_q6_k_q8_1_dp4a( } #undef NGROUPS } + +// Stage each 32-K activation block as two uint4 values. +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q6_k_q8_1_dp4a_act_vload4( + __global const ushort * src0_ql, + __global const uchar * src0_qh, + __global const ushort * src0_s, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + acc[g] = (float4)(0.0f); + } + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + const uint sb_idx = step / QK_K; + + const float dd = (float)src0_d[rrow + sb_idx * m]; + const char2 sc = as_char2(src0_s[rrow + sub * m]); + const float scale0 = dd * (float)sc.s0; + const float scale1 = dd * (float)sc.s1; + + const uint wbase = rrow + (step >> 2) * (uint)m; + uint qw[8]; + #pragma unroll + for (int u = 0; u < 8; ++u) { + const uint o = wbase + (uint)u * (uint)m; + qw[u] = SIGN6(EXP4((uint)src0_ql[o]) | EXP2((uint)src0_qh[o])); + } + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; + #define DOT_TOK(j) { \ + const uint4 a0 = sh_qa4[b + (j)][0]; \ + const uint4 a1 = sh_qa4[b + (j)][1]; \ + const int raw1 = dot4_q8a(qw[0], qw[1], qw[2], qw[3], a0.x, a0.y, a0.z, a0.w); \ + const int raw2 = dot4_q8a(qw[4], qw[5], qw[6], qw[7], a1.x, a1.y, a1.z, a1.w); \ + rf.s##j = scale0 * (float)raw1 + scale1 * (float)raw2; \ + } + DOT_TOK(0); DOT_TOK(1); DOT_TOK(2); DOT_TOK(3); + #undef DOT_TOK + const float4 ad = (float4)((float)sh_d[b+0], (float)sh_d[b+1], (float)sh_d[b+2], (float)sh_d[b+3]); + acc[g] += ad * rf; + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) { + dst[(c0 + 0) * (uint)m + row] = a.s0; + } + if (c0 + 1 < (uint)n_no_padding) { + dst[(c0 + 1) * (uint)m + row] = a.s1; + } + if (c0 + 2 < (uint)n_no_padding) { + dst[(c0 + 2) * (uint)m + row] = a.s2; + } + if (c0 + 3 < (uint)n_no_padding) { + dst[(c0 + 3) * (uint)m + row] = a.s3; + } + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q8_0_q8_1_dp4a.cl b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q8_0_q8_1_dp4a.cl index a481636c2324..32ff7b4f20c5 100644 --- a/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q8_0_q8_1_dp4a.cl +++ b/ggml/src/ggml-opencl/kernels/gemm_noshuffle_q8_0_q8_1_dp4a.cl @@ -210,3 +210,125 @@ kernel void kernel_gemm_noshuffle_q8_0_q8_1_dp4a_wimg( } #undef NGROUPS } + +// Stage each 32-K activation block as two uint4 values. +inline int dot8_q8a_v(uint8 qw, uint4 a0, uint4 a1) { + int r = 0; + r = dot_acc_sat_4x8packed_ss_int(qw.s0, a0.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s1, a0.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s2, a0.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s3, a0.w, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s4, a1.x, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s5, a1.y, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s6, a1.z, r); + r = dot_acc_sat_4x8packed_ss_int(qw.s7, a1.w, r); + return r; +} + +__attribute__((qcom_wave_pair_mode(1))) +kernel void kernel_gemm_noshuffle_q8_0_q8_1_dp4a_act_vload4( + __global const uint * src0_q, + __global const half * src0_d, + __global const uint * src1_qa, + __global const half * src1_da, + __global float * dst, + ulong offsetd, + int m, + int n_no_padding, + int k +) { + dst = (global float *)((global char *)dst + offsetd); + + const uint lid = get_local_id(0); + const uint block_id_m = get_global_id(1); + const uint block_id_n = get_global_id(2); + + const uint row = block_id_m * 64 + lid; + const uint col_base = block_id_n * TILESIZE_N; + const bool row_valid = row < (uint)m; + const uint rrow = row_valid ? row : 0; + + const uint k_u = (uint)k >> 2; + const uint k_b = (uint)k >> 5; + + __local uint4 sh_qa4[TILESIZE_N][2]; + __local half sh_d[TILESIZE_N]; + +#define NGROUPS (TILESIZE_N / 4) + float4 acc[NGROUPS]; + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + acc[g] = (float4)(0.0f); + } + + for (uint step = 0; step < (uint)k; step += 32) { + const uint sub = step >> 5; + + const float d_w = (float)src0_d[rrow + sub * (uint)m]; + + const uint wbase = rrow + (step >> 2) * (uint)m; + uint8 qw; + qw.s0 = src0_q[wbase + 0 * m]; + qw.s1 = src0_q[wbase + 1 * m]; + qw.s2 = src0_q[wbase + 2 * m]; + qw.s3 = src0_q[wbase + 3 * m]; + qw.s4 = src0_q[wbase + 4 * m]; + qw.s5 = src0_q[wbase + 5 * m]; + qw.s6 = src0_q[wbase + 6 * m]; + qw.s7 = src0_q[wbase + 7 * m]; + + for (uint idx = lid; idx < TILESIZE_N * 2; idx += 64) { + const uint t = idx >> 1; + const uint v = idx & 1; + const uint c = col_base + t; + sh_qa4[t][v] = (c < (uint)n_no_padding) + ? vload4(0, src1_qa + c * k_u + (step >> 2) + (v << 2)) + : (uint4)(0u); + } + if (lid < TILESIZE_N) { + const uint c = col_base + lid; + sh_d[lid] = (c < (uint)n_no_padding) ? src1_da[c * k_b + sub] : (half)0; + } + barrier(CLK_LOCAL_MEM_FENCE); + +#define LD4(arr, b) ((float4)((float)arr[(b)+0], (float)arr[(b)+1], (float)arr[(b)+2], (float)arr[(b)+3])) + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const int b = g * 4; + float4 rf; +#define DOTV(T) dot8_q8a_v(qw, sh_qa4[T][0], sh_qa4[T][1]) + rf.s0 = (float)DOTV(b+0); + rf.s1 = (float)DOTV(b+1); + rf.s2 = (float)DOTV(b+2); + rf.s3 = (float)DOTV(b+3); +#undef DOTV + acc[g] += d_w * LD4(sh_d, b) * rf; + } +#undef LD4 + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (!row_valid) { + return; + } + + #pragma unroll + for (int g = 0; g < NGROUPS; ++g) { + const uint b = (uint)(g * 4); + const float4 a = acc[g]; + const uint c0 = col_base + b; + if (c0 + 0 < (uint)n_no_padding) { + dst[(c0 + 0) * (uint)m + row] = a.s0; + } + if (c0 + 1 < (uint)n_no_padding) { + dst[(c0 + 1) * (uint)m + row] = a.s1; + } + if (c0 + 2 < (uint)n_no_padding) { + dst[(c0 + 2) * (uint)m + row] = a.s2; + } + if (c0 + 3 < (uint)n_no_padding) { + dst[(c0 + 3) * (uint)m + row] = a.s3; + } + } +#undef NGROUPS +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_mxfp4_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_mxfp4_f32_ns.cl index ee8b94f446c5..3f21c3523ee1 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_mxfp4_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_mxfp4_f32_ns.cl @@ -89,6 +89,9 @@ __kernel void kernel_gemv_moe_mxfp4_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; // each thread calculate partial sum of one output @@ -188,6 +191,9 @@ __kernel void kernel_gemv_moe_mxfp4_f32_ns_wimg( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_0_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_0_f32_ns.cl index 2d28db63ec57..f90970b21b27 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_0_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_0_f32_ns.cl @@ -44,6 +44,9 @@ __kernel void kernel_gemv_moe_q4_0_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; // each thread calculate partial sum of one output diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_1_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_1_f32_ns.cl index b98bdc0f12e0..44bc15ff9497 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_1_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_1_f32_ns.cl @@ -45,6 +45,9 @@ __kernel void kernel_gemv_moe_q4_1_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; // each thread calculate partial sum of one output diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_k_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_k_f32_ns.cl index d3a3c7db8798..290a315933aa 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q4_k_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q4_k_f32_ns.cl @@ -61,6 +61,9 @@ __kernel void kernel_gemv_moe_q4_k_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int num_superblocks = ne00 / QK_K; int num_subblocks = ne00 / 32; @@ -180,6 +183,9 @@ __kernel void kernel_gemv_moe_q4_k_f32_ns_wimg( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int num_superblocks = ne00 / QK_K; int num_subblocks = ne00 / 32; diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_0_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_0_f32_ns.cl index b43613638a85..83b186b44c24 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_0_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_0_f32_ns.cl @@ -45,6 +45,9 @@ __kernel void kernel_gemv_moe_q5_0_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; // each thread calculate partial sum of one output diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_1_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_1_f32_ns.cl index 7a666006e68b..2eba34e68557 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_1_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_1_f32_ns.cl @@ -46,6 +46,9 @@ __kernel void kernel_gemv_moe_q5_1_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } uint expert_offset = expert_id * ne00 * ne01 / 32; __private float sum = 0.0f; // each thread calculate partial sum of one output diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_k_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_k_f32_ns.cl index 7d868d7abd92..a959f72c397e 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q5_k_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q5_k_f32_ns.cl @@ -62,6 +62,9 @@ __kernel void kernel_gemv_moe_q5_k_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int num_superblocks = ne00 / QK_K; int num_subblocks = ne00 / 32; diff --git a/ggml/src/ggml-opencl/kernels/gemv_moe_q6_k_f32_ns.cl b/ggml/src/ggml-opencl/kernels/gemv_moe_q6_k_f32_ns.cl index c166bad5ba52..dcd34fbc2ab3 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_moe_q6_k_f32_ns.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_moe_q6_k_f32_ns.cl @@ -45,6 +45,9 @@ __kernel void kernel_gemv_moe_q6_k_f32_ns( uint i11 = i20 % ne11; uint expert_id = src2[i20]; + if ((int)expert_id == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int num_superblocks = ne00 / QK_K; int num_subblocks = ne00 / 32; // 8 sub-blocks of 32 per super-block diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_m_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_m_f32.cl new file mode 100644 index 000000000000..e1f4484fee23 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_m_f32.cl @@ -0,0 +1,134 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 +#define IQ1_M_DELTA 0.125f + +#ifndef IQ1_M_MV_NSG +#define IQ1_M_MV_NSG 4 +#endif + +inline float4 iq1_m_vals(uint g) { + return (float4)((float)( g & 0xFu), (float)((g >> 8) & 0xFu), + (float)((g >> 16) & 0xFu), (float)((g >> 24) & 0xFu)); +} + +inline float iq1_m_super(uint w0, uint w1, uint w2, uint w3) { + const ushort u16 = (ushort)(((w0 >> 12)) | ((w1 >> 8) & 0x00f0u) + | ((w2 >> 4) & 0x0f00u) | (w3 & 0xf000u)); + return (float)as_half(u16); +} + +kernel void kernel_gemv_noshuffle_iq1_m_f32( + __read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const uchar * src0_qh, + global const ushort * src0_sc, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ1_M_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f, sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + global const ushort * qhu = (global const ushort *)src0_qh; + global const uint * scu = (global const uint *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += IQ1_M_MV_NSG) { + const uint sb = j + (ib * 4u) * mh; + const uint w0 = scu[sb + 0u * mh]; + const uint w1 = scu[sb + 1u * mh]; + const uint w2 = scu[sb + 2u * mh]; + const uint w3 = scu[sb + 3u * mh]; + const float d0 = iq1_m_super( w0 & 0xFFFFu, w1 & 0xFFFFu, + w2 & 0xFFFFu, w3 & 0xFFFFu); + const float d1 = iq1_m_super((w0 >> 16) & 0xFFFFu, (w1 >> 16) & 0xFFFFu, + (w2 >> 16) & 0xFFFFu, (w3 >> 16) & 0xFFFFu); + + float acc0 = 0.f, acc1 = 0.f; + + for (uint sub_l = 0; sub_l < 8u; ++sub_l) { + const uint sub = ib * 8u + sub_l; + const uint scw = scu[j + (ib * 4u + (sub_l >> 1)) * mh]; + const uint grp = sub * 8u; + const uint shb = 3u * (2u * (sub_l & 1u)); + + for (uint l = 0; l < 4u; ++l) { + const uint sh = shb + 3u * (l >> 1); + const float s0 = (float)(2u * (((scw ) >> sh) & 7u) + 1u); + const float s1 = (float)(2u * (((scw >> 16) >> sh) & 7u) + 1u); + + const uint qhv = (uint)qhu[j + (sub * 2u + (l >> 1)) * mh]; + const uint h0 = qhv & 0xFFu; + const uint h1 = (qhv >> 8) & 0xFFu; + const uint qsv = (uint)qsu[j + (sub * 4u + l) * mh]; + + const uint msk = 0x08u << (4u * (l & 1u)); + const float t0 = (h0 & msk) ? (-1.f - IQ1_M_DELTA) : (-1.f + IQ1_M_DELTA); + const float t1 = (h1 & msk) ? (-1.f - IQ1_M_DELTA) : (-1.f + IQ1_M_DELTA); + + const uint g0 = IQ1_M_GRID(( qsv & 0xFFu) + | ((((h0 >> (4u*(l & 1u))) & 7u) << 8))); + const uint g1 = IQ1_M_GRID(((qsv >> 8) & 0xFFu) + | ((((h1 >> (4u*(l & 1u))) & 7u) << 8))); + + const float4 y0 = vload4(grp + 2u*l + 0u, y); + const float4 y1 = vload4(grp + 2u*l + 1u, y); + + const float4 ys = y0 + y1; + const float as = ys.s0 + ys.s1 + ys.s2 + ys.s3; + + const float a0 = dot(y0, iq1_m_vals(g0)) + dot(y1, iq1_m_vals(g0 >> 4)); + const float a1 = dot(y0, iq1_m_vals(g1)) + dot(y1, iq1_m_vals(g1 >> 4)); + acc0 += s0 * (a0 + t0 * as); + acc1 += s1 * (a1 + t1 * as); + } + } + sumf += d0 * acc0; + sumf1 += d1 * acc1; + } + } + +#if IQ1_M_MV_NSG > 1 + __local float2 part[IQ1_M_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ1_M_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ1_M_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_s_f32.cl new file mode 100644 index 000000000000..6a6eb6e9c3f3 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq1_s_f32.cl @@ -0,0 +1,117 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ1_S_MV_NSG +#define IQ1_S_MV_NSG 4 +#endif + +inline float4 iq1_s_vals(uint g) { + return (float4)((float)( g & 0xFu), (float)((g >> 8) & 0xFu), + (float)((g >> 16) & 0xFu), (float)((g >> 24) & 0xFu)); +} + +kernel void kernel_gemv_noshuffle_iq1_s_f32( + __read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const ushort * src0_qh, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ1_S_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f, sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + + for (uint ib = sgi; ib < nsb; ib += IQ1_S_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint sub = ib * 8u + sb; + const ushort2 qhv = vload2(j + sub * mh, src0_qh); + const uint h0 = (uint)qhv.s0, h1 = (uint)qhv.s1; + + const float s0 = (float)(2u * ((h0 >> 12) & 7u) + 1u); + const float s1 = (float)(2u * ((h1 >> 12) & 7u) + 1u); + const float t0 = ((h0 & 0x8000u) ? -0.125f : 0.125f) - 1.0f; + const float t1 = ((h1 & 0x8000u) ? -0.125f : 0.125f) - 1.0f; + + const uint gb = j + (sub * 4u) * mh; + const uint grp = sub * 8u; + + float a0 = 0.f, a1 = 0.f; + float4 as = (float4)(0.f); + for (uint l = 0; l < 4u; ++l) { + const uint qsv = (uint)qsu[gb + l * mh]; + const uint g0 = IQ1_S_GRID(( qsv & 0xFFu) | ((((h0 >> (3u*l)) & 7u) << 8))); + const uint g1 = IQ1_S_GRID(((qsv >> 8) & 0xFFu) | ((((h1 >> (3u*l)) & 7u) << 8))); + + const float4 y0 = vload4(grp + 2u*l + 0u, y); + const float4 y1 = vload4(grp + 2u*l + 1u, y); + as += y0 + y1; + a0 += dot(y0, iq1_s_vals(g0)) + dot(y1, iq1_s_vals(g0 >> 4)); + a1 += dot(y0, iq1_s_vals(g1)) + dot(y1, iq1_s_vals(g1 >> 4)); + } + + const float asum = as.s0 + as.s1 + as.s2 + as.s3; + acc0 += s0 * (a0 + t0 * asum); + acc1 += s1 * (a1 + t1 * asum); + } + sumf += (float)dh.s0 * acc0; + sumf1 += (float)dh.s1 * acc1; + } + } + +#if IQ1_S_MV_NSG > 1 + __local float2 part[IQ1_S_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ1_S_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ1_S_GRID +} + +kernel void kernel_iq1_s_grid_export(global uint * out) { + const uint i = get_global_id(0); + if (i < 2048u) { + out[i] = iq1_s_grid[i]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_s_f32.cl new file mode 100644 index 000000000000..25de1cb91f5e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_s_f32.cl @@ -0,0 +1,122 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ2_S_MV_NSG +#define IQ2_S_MV_NSG 8 +#endif + +inline float4 iq2_s_vals(uint gv, uint sg, uint base) { + + const uint s = sg >> base; + const uint4 sgn = (uint4)(s << 31, s << 30, s << 29, s << 28) & 0x80000000u; + return as_float4(as_uint4(convert_float4(as_uchar4(gv))) ^ sgn); +} + +kernel void kernel_iq2_s_grid_export(global uint * out) { + out[get_global_id(0)] = iq2_s_grid[get_global_id(0)]; +} + +kernel void kernel_gemv_noshuffle_iq2_s_f32( + read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const uchar * src0_sg, + global const uchar * src0_qh, + global const uchar * src0_sc, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ2_S_GRID(i) read_imageui(grid_img, (int)(i)).x + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f, sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + global const ushort * sgu = (global const ushort *)src0_sg; + global const ushort * qhu = (global const ushort *)src0_qh; + global const ushort * scu = (global const ushort *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += IQ2_S_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint sub = ib * 8u + sb; + const uint qhv = (uint)qhu[j + sub * mh]; + const uint scv = (uint)scu[j + sub * mh]; + const uint gb = j + (sub * 4u) * mh; + + for (uint h = 0; h < 2u; ++h) { + const uint n0 = (h == 0u) ? ( scv & 0xFu) : (( scv >> 4) & 0xFu); + const uint n1 = (h == 0u) ? ((scv >> 8) & 0xFu) : (((scv >> 8) >> 4) & 0xFu); + + float a0 = 0.f, a1 = 0.f; + for (uint t = 0; t < 2u; ++t) { + const uint l = 2u*h + t; + const uint qsv = (uint)qsu[gb + l * mh]; + const uint sgv = (uint)sgu[gb + l * mh]; + const uint gi0 = ( qsv & 0xFFu) | ((((qhv ) >> (2u*l)) & 3u) << 8); + const uint gi1 = ((qsv >> 8) & 0xFFu) | ((((qhv >> 8) >> (2u*l)) & 3u) << 8); + const uint s0 = sgv & 0xFFu; + const uint s1 = (sgv >> 8) & 0xFFu; + + const uint grp = (ib * 64u + sb * 8u) + l * 2u; + const float4 y0 = vload4(grp + 0u, y); + const float4 y1 = vload4(grp + 1u, y); + a0 += dot(y0, iq2_s_vals(IQ2_S_GRID(2u*gi0 + 0u), s0, 0u)); + a0 += dot(y1, iq2_s_vals(IQ2_S_GRID(2u*gi0 + 1u), s0, 4u)); + a1 += dot(y0, iq2_s_vals(IQ2_S_GRID(2u*gi1 + 0u), s1, 0u)); + a1 += dot(y1, iq2_s_vals(IQ2_S_GRID(2u*gi1 + 1u), s1, 4u)); + } + acc0 += (0.5f + (float)n0) * a0; + acc1 += (0.5f + (float)n1) * a1; + } + } + sumf += (float)dh.s0 * 0.25f * acc0; + sumf1 += (float)dh.s1 * 0.25f * acc1; + } + } + +#if IQ2_S_MV_NSG > 1 + __local float2 part[IQ2_S_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ2_S_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ2_S_GRID +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xs_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xs_f32.cl new file mode 100644 index 000000000000..52d626ec8d34 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xs_f32.cl @@ -0,0 +1,128 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ2_XS_MV_NSG +#define IQ2_XS_MV_NSG 4 +#endif + +inline float4 iq2_xs_vals(uint gv, uint sgv, uint base) { + const uint s = sgv >> base; + const uint4 sgn = (uint4)(s << 31, s << 30, s << 29, s << 28) & 0x80000000u; + return as_float4(as_uint4(convert_float4(as_uchar4(gv))) ^ sgn); +} + +kernel void kernel_gemv_noshuffle_iq2_xs_f32( + __read_only image1d_buffer_t grid_img, + global const ushort * src0_qs, + global const uchar * src0_sc, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ2_XS_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f; + float sumf1 = 0.f; + + if (j < mh) { + global const uint * qsu = (global const uint *)src0_qs; + global const ushort * scu = (global const ushort *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += IQ2_XS_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + const float d0 = (float)dh.s0; + const float d1 = (float)dh.s1; + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint sub = ib * 8u + sb; + const uint scv = (uint)scu[j + sub * mh]; + + const float lo0 = 0.5f + (float)( scv & 0xFu); + const float hi0 = 0.5f + (float)((scv >> 4) & 0xFu); + const float lo1 = 0.5f + (float)((scv >> 8) & 0xFu); + const float hi1 = 0.5f + (float)((scv >> 12) & 0xFu); + + const uint grp = sub * 4u; + const uint qsb = j + grp * mh; + + float alo0 = 0.f, ahi0 = 0.f, alo1 = 0.f, ahi1 = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint qsv = qsu[qsb + u * mh]; + const uint q0 = qsv & 0xFFFFu; + const uint q1 = qsv >> 16; + + const uint g0 = (q0 & 511u) << 1; + const uint g1 = (q1 & 511u) << 1; + const uint sg0 = iq2_xs_signs(q0 >> 9); + const uint sg1 = iq2_xs_signs(q1 >> 9); + + const float4 yl = vload4(sub * 8u + u * 2u + 0u, y); + const float4 yh = vload4(sub * 8u + u * 2u + 1u, y); + + const float a0 = dot(yl, iq2_xs_vals(IQ2_XS_GRID(g0 ), sg0, 0u)) + + dot(yh, iq2_xs_vals(IQ2_XS_GRID(g0 + 1), sg0, 4u)); + const float a1 = dot(yl, iq2_xs_vals(IQ2_XS_GRID(g1 ), sg1, 0u)) + + dot(yh, iq2_xs_vals(IQ2_XS_GRID(g1 + 1), sg1, 4u)); + + if (u < 2u) { alo0 += a0; alo1 += a1; } + else { ahi0 += a0; ahi1 += a1; } + } + acc0 += lo0 * alo0 + hi0 * ahi0; + acc1 += lo1 * alo1 + hi1 * ahi1; + } + sumf += d0 * 0.25f * acc0; + sumf1 += d1 * 0.25f * acc1; + } + } + +#if IQ2_XS_MV_NSG > 1 + __local float2 part[IQ2_XS_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ2_XS_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ2_XS_GRID +} + +kernel void kernel_iq2_xs_grid_export(global uint * out) { + const uint i = get_global_id(0); + if (i < 1024u) { + out[i] = iq2_xs_grid[i]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xxs_f32.cl new file mode 100644 index 000000000000..405a8144f3a5 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq2_xxs_f32.cl @@ -0,0 +1,117 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ2_XXS_MV_NSG +#define IQ2_XXS_MV_NSG 4 +#endif + +inline float4 iq2_xxs_vals(uint gv, uint sgv, uint base) { + const uint s = sgv >> base; + const uint4 sgn = (uint4)(s << 31, s << 30, s << 29, s << 28) & 0x80000000u; + return as_float4(as_uint4(convert_float4(as_uchar4(gv))) ^ sgn); +} + +kernel void kernel_gemv_noshuffle_iq2_xxs_f32( + __read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const uint * src0_sas, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ2_XXS_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f; + float sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + + for (uint ib = sgi; ib < nsb; ib += IQ2_XXS_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + const float d0 = (float)dh.s0; + const float d1 = (float)dh.s1; + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint sub = ib * 8u + sb; + const uint2 aux = vload2(j + sub * mh, src0_sas); + + const uint grp = sub * 4u; + const uint qsb = j + grp * mh; + + float a0 = 0.f, a1 = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint qsv = (uint)qsu[qsb + u * mh]; + const uint sg0 = iq2_xxs_signs((aux.s0 >> (7u * u)) & 127u); + const uint sg1 = iq2_xxs_signs((aux.s1 >> (7u * u)) & 127u); + + const uint g0 = ( qsv & 0xFFu) << 1; + const uint g1 = ((qsv >> 8) & 0xFFu) << 1; + + const float4 yl = vload4(sub * 8u + u * 2u + 0u, y); + const float4 yh = vload4(sub * 8u + u * 2u + 1u, y); + + a0 += dot(yl, iq2_xxs_vals(IQ2_XXS_GRID(g0 ), sg0, 0u)) + + dot(yh, iq2_xxs_vals(IQ2_XXS_GRID(g0 + 1), sg0, 4u)); + a1 += dot(yl, iq2_xxs_vals(IQ2_XXS_GRID(g1 ), sg1, 0u)) + + dot(yh, iq2_xxs_vals(IQ2_XXS_GRID(g1 + 1), sg1, 4u)); + } + acc0 += (0.5f + (float)(aux.s0 >> 28)) * a0; + acc1 += (0.5f + (float)(aux.s1 >> 28)) * a1; + } + sumf += d0 * 0.25f * acc0; + sumf1 += d1 * 0.25f * acc1; + } + } + +#if IQ2_XXS_MV_NSG > 1 + __local float2 part[IQ2_XXS_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ2_XXS_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ2_XXS_GRID +} + +kernel void kernel_iq2_xxs_grid_export(global uint * out) { + const uint i = get_global_id(0); + if (i < 512u) { + out[i] = iq2_xxs_grid[i]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_s_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_s_f32.cl new file mode 100644 index 000000000000..e94b84a86c05 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_s_f32.cl @@ -0,0 +1,128 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ3_S_MV_NSG +#define IQ3_S_MV_NSG 4 +#endif + +inline float4 iq3_s_vals(uint gv, uint sg, uint base) { + + const uint s = sg >> base; + const uint4 sgn = (uint4)(s << 31, s << 30, s << 29, s << 28) & 0x80000000u; + return as_float4(as_uint4(convert_float4(as_uchar4(gv))) ^ sgn); +} + +kernel void kernel_gemv_noshuffle_iq3_s_f32( + __read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const uchar * src0_sg, + global const uchar * src0_qh, + global const uchar * src0_sc, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ3_S_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f; + float sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + global const ushort * qhu = (global const ushort *)src0_qh; + global const ushort * sgu = (global const ushort *)src0_sg; + global const ushort * scu = (global const ushort *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += IQ3_S_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + const float d0 = (float)dh.s0; + const float d1 = (float)dh.s1; + + const uint scbase = j + ib * 4u * mh; + ushort sc4[4]; + sc4[0] = scu[scbase + 0u * mh]; + sc4[1] = scu[scbase + 1u * mh]; + sc4[2] = scu[scbase + 2u * mh]; + sc4[3] = scu[scbase + 3u * mh]; + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint scv = (uint)sc4[sb >> 1]; + const uint nib0 = (sb & 1u) ? ((scv >> 4) & 0xFu) : ( scv & 0xFu); + const uint nib1 = (sb & 1u) ? ((scv >> 12) & 0xFu) : ((scv >> 8) & 0xFu); + + const uint qhv = (uint)qhu[j + (ib * 8u + sb) * mh]; + const uint qh0 = qhv & 0xFFu; + const uint qh1 = qhv >> 8; + + const uint grp = ib * 64u + sb * 8u; + const uint qsb = j + grp * mh; + const uint sgb = j + (ib * 32u + sb * 4u) * mh; + + float a0 = 0.f, a1 = 0.f; + for (uint u = 0; u < 8u; ++u) { + const uint qsv = (uint)qsu[qsb + u * mh]; + const uint sgv = (uint)sgu[sgb + (u >> 1) * mh]; + const uint g0 = ( qsv & 0xFFu) | (((qh0 >> u) & 1u) << 8); + const uint g1 = ((qsv >> 8) & 0xFFu) | (((qh1 >> u) & 1u) << 8); + const uint base = (u & 1u) * 4u; + const float4 yv = vload4(grp + u, y); + const uint gw0 = IQ3_S_GRID(g0); + const uint gw1 = IQ3_S_GRID(g1); + a0 += dot(yv, iq3_s_vals(gw0, sgv & 0xFFu, base)); + a1 += dot(yv, iq3_s_vals(gw1, (sgv >> 8) & 0xFFu, base)); + } + acc0 += (float)(1u + 2u * nib0) * a0; + acc1 += (float)(1u + 2u * nib1) * a1; + } + sumf += d0 * acc0; + sumf1 += d1 * acc1; + } + } + +#if IQ3_S_MV_NSG > 1 + __local float2 part[IQ3_S_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ3_S_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +} + +kernel void kernel_iq3_s_grid_export(global uint * out) { + out[get_global_id(0)] = iq3_s_grid[get_global_id(0)]; +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_xxs_f32.cl new file mode 100644 index 000000000000..c6a5dbeac347 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq3_xxs_f32.cl @@ -0,0 +1,120 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef IQ3_XXS_MV_NSG +#define IQ3_XXS_MV_NSG 4 +#endif + +inline float4 iq3_xxs_vals(uint gv, uint sgv, uint base) { + const uint s = sgv >> base; + const uint4 sgn = (uint4)(s << 31, s << 30, s << 29, s << 28) & 0x80000000u; + return as_float4(as_uint4(convert_float4(as_uchar4(gv))) ^ sgn); +} + +kernel void kernel_gemv_noshuffle_iq3_xxs_f32( + __read_only image1d_buffer_t grid_img, + global const uchar * src0_qs, + global const uint * src0_sas, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#define IQ3_XXS_GRID(i) (read_imageui(grid_img, (int)(i)).x) + + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f; + float sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + + for (uint ib = sgi; ib < nsb; ib += IQ3_XXS_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + const float d0 = (float)dh.s0; + const float d1 = (float)dh.s1; + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint sub = ib * 8u + sb; + const uint2 aux = vload2(j + sub * mh, src0_sas); + + const uint grp = sub * 8u; + const uint qsb = j + grp * mh; + + float a0 = 0.f, a1 = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint qsv0 = (uint)qsu[qsb + (2u*u)*mh]; + const uint qsv1 = (uint)qsu[qsb + (2u*u + 1u)*mh]; + const uint sg0 = iq3_xxs_signs((aux.s0 >> (7u * u)) & 127u); + const uint sg1 = iq3_xxs_signs((aux.s1 >> (7u * u)) & 127u); + + const uint g00 = qsv0 & 0xFFu; + const uint g01 = qsv1 & 0xFFu; + const uint g10 = (qsv0 >> 8) & 0xFFu; + const uint g11 = (qsv1 >> 8) & 0xFFu; + + const float4 yl = vload4(sub * 8u + u * 2u + 0u, y); + const float4 yh = vload4(sub * 8u + u * 2u + 1u, y); + + a0 += dot(yl, iq3_xxs_vals(IQ3_XXS_GRID(g00), sg0, 0u)) + + dot(yh, iq3_xxs_vals(IQ3_XXS_GRID(g01), sg0, 4u)); + a1 += dot(yl, iq3_xxs_vals(IQ3_XXS_GRID(g10), sg1, 0u)) + + dot(yh, iq3_xxs_vals(IQ3_XXS_GRID(g11), sg1, 4u)); + } + acc0 += (0.5f + (float)(aux.s0 >> 28)) * a0; + acc1 += (0.5f + (float)(aux.s1 >> 28)) * a1; + } + sumf += d0 * 0.5f * acc0; + sumf1 += d1 * 0.5f * acc1; + } + } + +#if IQ3_XXS_MV_NSG > 1 + __local float2 part[IQ3_XXS_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < IQ3_XXS_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#undef IQ3_XXS_GRID +} + +kernel void kernel_iq3_xxs_grid_export(global uint * out) { + const uint i = get_global_id(0); + if (i < 256u) { + out[i] = iq3_xxs_grid[i]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq4_nl_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq4_nl_f32.cl index 1f832cb253b7..e17ca09ba815 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq4_nl_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_iq4_nl_f32.cl @@ -230,6 +230,8 @@ kernel void kernel_gemv_noshuffle_iq4_nl_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; private uint4 regA; @@ -240,7 +242,7 @@ kernel void kernel_gemv_noshuffle_iq4_nl_f32( // loop along K in block granularity, skip 4 blocks every iter for (uint k = groupId; k < (K / QK4_NL); k += NSUBGROUPS) { - regS = src0_d[gid + k * LINE_STRIDE_A]; // each fiber loads scale of two rows + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // each fiber loads scale of two rows // first 4 fibers in each wave load 8 B values to its private scope if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); @@ -248,20 +250,20 @@ kernel void kernel_gemv_noshuffle_iq4_nl_f32( } // load half weights for two blocks in consecutive rows - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), regS, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), regS, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), regS, regB); #else diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q1_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q1_0_f32.cl index 9efede29411b..572f11637b99 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q1_0_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q1_0_f32.cl @@ -8,7 +8,9 @@ #endif #define QK1_0 128 +#ifndef N_SIMDGROUP #define N_SIMDGROUP 4 +#endif #define dequantizeBlockAccum_q1(total, bits, scale, regB, lb) \ total += (2.0f*(float)((bits >> 0) & 1u) - 1.0f) * scale * sub_group_broadcast(regB.s0, lb+0); \ @@ -73,6 +75,8 @@ __kernel void kernel_gemv_noshuffle_q1_0_f32( uint M = ne01; uint LINE_STRIDE_A = M; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = 4 * M; uint4 regA; @@ -83,7 +87,7 @@ __kernel void kernel_gemv_noshuffle_q1_0_f32( #pragma unroll 1 for (uint kb = groupId; kb < (K / QK1_0); kb += N_SIMDGROUP) { - regS = src0_d[gid + kb * LINE_STRIDE_A]; // each fiber loads its row's scale + regS = src0_d[gid_s + kb * LINE_STRIDE_A]; // each fiber loads its row's scale // first 16 fibers load 8 B values each -> 128 activations for this block if (slid < 16) { @@ -92,10 +96,10 @@ __kernel void kernel_gemv_noshuffle_q1_0_f32( } // load this row's 4 uint32 (128 sign bits) - regA.s0 = read_imageui(src0_q, (gid + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + kb * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; float scale = (float)regS; dequantizeBlockAccum_q1(totalSum, regA.s0, scale, regB, 0); @@ -104,15 +108,19 @@ __kernel void kernel_gemv_noshuffle_q1_0_f32( dequantizeBlockAccum_q1(totalSum, regA.s3, scale, regB, 12); } - // reduction in local memory, assumes #wave = N_SIMDGROUP = 4 - local float reduceLM[SIMDGROUP_WIDTH * 3]; - if (groupId == 1) reduceLM[SIMDGROUP_WIDTH * 0 + slid] = totalSum; - if (groupId == 2) reduceLM[SIMDGROUP_WIDTH * 1 + slid] = totalSum; - if (groupId == 3) reduceLM[SIMDGROUP_WIDTH * 2 + slid] = totalSum; +#if N_SIMDGROUP > 1 + // Sum the K slices from the other subgroups. + local float reduceLM[SIMDGROUP_WIDTH * (N_SIMDGROUP - 1)]; + if (groupId > 0) { + reduceLM[SIMDGROUP_WIDTH * (groupId - 1) + slid] = totalSum; + } barrier(CLK_LOCAL_MEM_FENCE); - if (groupId == 0) totalSum += reduceLM[SIMDGROUP_WIDTH * 0 + slid]; - if (groupId == 0) totalSum += reduceLM[SIMDGROUP_WIDTH * 1 + slid]; - if (groupId == 0) totalSum += reduceLM[SIMDGROUP_WIDTH * 2 + slid]; + if (groupId == 0) { + for (uint w = 0; w < N_SIMDGROUP - 1; ++w) { + totalSum += reduceLM[SIMDGROUP_WIDTH * w + slid]; + } + } +#endif if (groupId == 0) { dst = (global float*)((global char*)dst + offsetd); @@ -120,6 +128,8 @@ __kernel void kernel_gemv_noshuffle_q1_0_f32( // so when ne01 is not a multiple of the wave size the tail work-items run past // row ne01 and would overrun dst into the adjacent tensor. No-op / byte-identical // when ne01 is wave-aligned (no padding). - if (gid < M) dst[gid] = totalSum; + if (gid < M) { + dst[gid] = totalSum; + } } } diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_0_f32.cl new file mode 100644 index 000000000000..27ff7edd34fc --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_0_f32.cl @@ -0,0 +1,64 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifndef Q2_0_MV_NSG +#define Q2_0_MV_NSG 8 +#endif + +kernel void kernel_gemv_noshuffle_q2_0_f32( + global const uchar * src0_qs, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, + int ne01, + int ne10, + int ne0 +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint mh = m >> 1; + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + const uint j = get_group_id(0)*64u + lid; + const uint row = j << 1; + global const float * y = src1 + (ulong)col * (uint)ne10; + + float2 sum = 0.0f; + if (j < mh) { + global const ushort * qs = (global const ushort *)src0_qs; + for (uint ib = sgi; ib < (uint)ne00/64; ib += Q2_0_MV_NSG) { + const float2 d = convert_float2(vload2(j + ib*mh, src0_d)); + float2 acc = 0.0f; + for (uint u = 0; u < 16; ++u) { + const uint group = ib*16 + u; + const uint q = qs[j + group*mh]; + const float4 yv = vload4(group, y); + const int4 v0 = convert_int4(((uint4)(q) >> (uint4)(0, 2, 4, 6)) & (uint4)(3)) - (int4)(1); + const int4 v1 = convert_int4(((uint4)(q) >> (uint4)(8, 10, 12, 14)) & (uint4)(3)) - (int4)(1); + acc.s0 += dot(yv, convert_float4(v0)); + acc.s1 += dot(yv, convert_float4(v1)); + } + sum += d*acc; + } + } + +#if Q2_0_MV_NSG > 1 + local float2 part[Q2_0_MV_NSG][64]; + part[sgi][lid] = sum; + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q2_0_MV_NSG; ++s) { + sum += part[s][lid]; + } +#endif + if (j < mh) { + vstore2(sum, 0, dst + (ulong)col*(uint)ne0 + row); + } +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_k_f32.cl new file mode 100644 index 000000000000..efcc310775e3 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q2_k_f32.cl @@ -0,0 +1,231 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef Q2_K_MV_NSG +#define Q2_K_MV_NSG 8 +#endif + +#ifndef Q2_K_MV_R +#define Q2_K_MV_R 4 +#endif + +inline float4 q2_k_vals(uint pk) { + return (float4)((float)( pk & 3u), (float)((pk >> 2) & 3u), + (float)((pk >> 4) & 3u), (float)((pk >> 6) & 3u)); +} + +kernel void kernel_gemv_noshuffle_q2_k_f32( + global const uchar * src0_qs, + global const uchar * src0_sc, + global const half * src0_dm, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, // K + int ne01, // M + int ne10, // activation row stride, == K + int ne0 // dst row stride +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + + const uint mr = m / Q2_K_MV_R; // row groups + const uint j = get_group_id(0) * 64u + lid; // row group this lane owns + const uint row = j * Q2_K_MV_R; + +#if Q2_K_MV_R == 4 + float sumf0 = 0.f; + float sumf1 = 0.f; + float sumf2 = 0.f; + float sumf3 = 0.f; + + if (j < mr) { + global const uint * qsu = (global const uint *)src0_qs; + global const uint * scu = (global const uint *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += Q2_K_MV_NSG) { + const half4 dma = vload4(2u*(j + ib*mr) + 0u, src0_dm); // d0, dmin0, d1, dmin1 + const half4 dmb = vload4(2u*(j + ib*mr) + 1u, src0_dm); // d2, dmin2, d3, dmin3 + + float ad0 = 0.f, am0 = 0.f, ad1 = 0.f, am1 = 0.f; + float ad2 = 0.f, am2 = 0.f, ad3 = 0.f, am3 = 0.f; + + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = j + grp * mr; + + for (uint h = 0; h < 2u; ++h) { + const uint scv = scu[j + (2u * (ib * 8u + sb) + h) * mr]; + + float a0 = 0.f, a1 = 0.f, a2 = 0.f, a3 = 0.f; + float4 as = (float4)(0.f); + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const uint qsv = qsu[qsb + gg * mr]; // four rows, one load + const float4 yv = vload4(grp + gg, y); + as += yv; + a0 += dot(yv, q2_k_vals( qsv & 0xFFu)); + a1 += dot(yv, q2_k_vals((qsv >> 8) & 0xFFu)); + a2 += dot(yv, q2_k_vals((qsv >> 16) & 0xFFu)); + a3 += dot(yv, q2_k_vals((qsv >> 24) & 0xFFu)); + } + const float asum = as.s0 + as.s1 + as.s2 + as.s3; + + const uint s0 = scv & 0xFFu; + const uint s1 = (scv >> 8) & 0xFFu; + const uint s2 = (scv >> 16) & 0xFFu; + const uint s3 = (scv >> 24) & 0xFFu; + ad0 += (float)(s0 & 0xFu) * a0; am0 += (float)(s0 >> 4) * asum; + ad1 += (float)(s1 & 0xFu) * a1; am1 += (float)(s1 >> 4) * asum; + ad2 += (float)(s2 & 0xFu) * a2; am2 += (float)(s2 >> 4) * asum; + ad3 += (float)(s3 & 0xFu) * a3; am3 += (float)(s3 >> 4) * asum; + } + } + sumf0 += (float)dma.s0 * ad0 - (float)dma.s1 * am0; + sumf1 += (float)dma.s2 * ad1 - (float)dma.s3 * am1; + sumf2 += (float)dmb.s0 * ad2 - (float)dmb.s1 * am2; + sumf3 += (float)dmb.s2 * ad3 - (float)dmb.s3 * am3; + } + } + +#if Q2_K_MV_NSG > 1 + __local float4 part[Q2_K_MV_NSG][64]; + part[sgi][lid] = (float4)(sumf0, sumf1, sumf2, sumf3); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q2_K_MV_NSG; ++s) { + const float4 p = part[s][lid]; + sumf0 += p.s0; + sumf1 += p.s1; + sumf2 += p.s2; + sumf3 += p.s3; + } +#endif + + if (j < mr) { + global float * o = dst + (ulong)col * (uint)ne0 + row; + o[0] = sumf0; o[1] = sumf1; o[2] = sumf2; o[3] = sumf3; + } + +#elif Q2_K_MV_R == 2 + float sumf0 = 0.f; + float sumf1 = 0.f; + + if (j < mr) { + global const ushort * qsu = (global const ushort *)src0_qs; + global const ushort * scu = (global const ushort *)src0_sc; + + for (uint ib = sgi; ib < nsb; ib += Q2_K_MV_NSG) { + const half4 dm = vload4(j + ib * mr, src0_dm); // d0, dmin0, d1, dmin1 + + float ad0 = 0.f, am0 = 0.f, ad1 = 0.f, am1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = j + grp * mr; + + for (uint h = 0; h < 2u; ++h) { + const uint scv = (uint)scu[j + (2u * (ib * 8u + sb) + h) * mr]; + const uint s0 = scv & 0xFFu; + const uint s1 = scv >> 8; + + float a0 = 0.f, a1 = 0.f; + float4 as = (float4)(0.f); + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const uint qsv = (uint)qsu[qsb + gg * mr]; + const float4 yv = vload4(grp + gg, y); + as += yv; + a0 += dot(yv, q2_k_vals( qsv & 0xFFu)); + a1 += dot(yv, q2_k_vals((qsv >> 8) & 0xFFu)); + } + const float asum = as.s0 + as.s1 + as.s2 + as.s3; + ad0 += (float)(s0 & 0xFu) * a0; am0 += (float)(s0 >> 4) * asum; + ad1 += (float)(s1 & 0xFu) * a1; am1 += (float)(s1 >> 4) * asum; + } + } + sumf0 += (float)dm.s0 * ad0 - (float)dm.s1 * am0; + sumf1 += (float)dm.s2 * ad1 - (float)dm.s3 * am1; + } + } + +#if Q2_K_MV_NSG > 1 + __local float2 part[Q2_K_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf0, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q2_K_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf0 += p.s0; + sumf1 += p.s1; + } +#endif + + if (j < mr) { + vstore2((float2)(sumf0, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } + +#else + float sumf0 = 0.f; + + if (j < mr) { + for (uint ib = sgi; ib < nsb; ib += Q2_K_MV_NSG) { + const half2 dm = vload2(row + ib * m, src0_dm); + + float ad = 0.f, am = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = row + grp * m; + + for (uint h = 0; h < 2u; ++h) { + const uint sc = (uint)src0_sc[row + (2u * (ib * 8u + sb) + h) * m]; + + float a = 0.f; + float4 as = (float4)(0.f); + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const float4 yv = vload4(grp + gg, y); + as += yv; + const uint pkv = (uint)src0_qs[qsb + gg * m]; + a += dot(yv, q2_k_vals(pkv)); + } + const float asum = as.s0 + as.s1 + as.s2 + as.s3; + ad += (float)(sc & 0xFu) * a; am += (float)(sc >> 4) * asum; + } + } + sumf0 += (float)dm.s0 * ad - (float)dm.s1 * am; + } + } + +#if Q2_K_MV_NSG > 1 + __local float part[Q2_K_MV_NSG][64]; + part[sgi][lid] = sumf0; + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q2_K_MV_NSG; ++s) { + sumf0 += part[s][lid]; + } +#endif + + if (j < mr) { + dst[(ulong)col * (uint)ne0 + row] = sumf0; + } +#endif +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q3_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q3_k_f32.cl new file mode 100644 index 000000000000..f44354154c08 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q3_k_f32.cl @@ -0,0 +1,249 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define QK_K 256 + +#ifndef Q3_K_MV_NSG +#define Q3_K_MV_NSG 8 +#endif + +#ifndef Q3_K_MV_R +#define Q3_K_MV_R 2 +#endif + +inline int q3_k_scale(uint sc0, uint sc1, uint sc2, uint is) { + const uint w = is >> 2; + const uint sh = 8u * (is & 3u); + const uint tb = (sc2 >> sh) & 0xFFu; + uint v; + if (w == 0u) { v = ( (sc0 >> sh) & 0xFu) | (((tb >> 0) & 3u) << 4); } + else if (w == 1u) { v = ( (sc1 >> sh) & 0xFu) | (((tb >> 2) & 3u) << 4); } + else if (w == 2u) { v = (((sc0 >> sh) >> 4) & 0xFu) | (((tb >> 4) & 3u) << 4); } + else { v = (((sc1 >> sh) >> 4) & 0xFu) | (((tb >> 6) & 3u) << 4); } + return (int)v - 32; +} + +inline float4 q3_k_vals(uint pk, uint hb) { + float4 v; + v.s0 = (float)((int)((pk ) & 3u) - 4 + 4*(int)((hb ) & 1u)); + v.s1 = (float)((int)((pk >> 2) & 3u) - 4 + 4*(int)((hb >> 1) & 1u)); + v.s2 = (float)((int)((pk >> 4) & 3u) - 4 + 4*(int)((hb >> 2) & 1u)); + v.s3 = (float)((int)((pk >> 6) & 3u) - 4 + 4*(int)((hb >> 3) & 1u)); + return v; +} + +kernel void kernel_gemv_noshuffle_q3_k_f32( + global const uchar * src0_qs, + global const uchar * src0_hm, + global const uint * src0_sc, + global const half * src0_d, + global const float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + int ne00, // K + int ne01, // M + int ne10, // activation row stride + int ne0 // dst row stride +) { + src1 = (global const float *)((global const char *)src1 + offset1); + dst = (global float *)((global char *)dst + offsetd); + + const uint m = (uint)ne01; + const uint K = (uint)ne00; + const uint nsb = K / QK_K; + + const uint lid = get_local_id(0); + const uint sgi = get_local_id(1); + const uint col = get_group_id(1); + + global const float * y = src1 + (ulong)col * (uint)ne10; + +#if Q3_K_MV_R == 4 + const uint mq = m >> 2; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 2; + + float sumf = 0.f, sumf1 = 0.f, sumf2 = 0.f, sumf3 = 0.f; + + if (j < mq) { + global const uint * qsw = (global const uint *)src0_qs; + global const uint * hmw = (global const uint *)src0_hm; + + for (uint ib = sgi; ib < nsb; ib += Q3_K_MV_NSG) { + const half4 dh = vload4(j + ib * mq, src0_d); + const uint4 s0 = vload4(j + (3u * ib + 0u) * mq, src0_sc); + const uint4 s1 = vload4(j + (3u * ib + 1u) * mq, src0_sc); + const uint4 s2 = vload4(j + (3u * ib + 2u) * mq, src0_sc); + + float acc0 = 0.f, acc1 = 0.f, acc2 = 0.f, acc3 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = j + grp * mq; + const uint hmb = j + (grp >> 1) * mq; + + for (uint h = 0; h < 2u; ++h) { // two 16-weight halves + const int l0 = q3_k_scale(s0.s0, s1.s0, s2.s0, 2u*sb + h); + const int l1 = q3_k_scale(s0.s1, s1.s1, s2.s1, 2u*sb + h); + const int l2 = q3_k_scale(s0.s2, s1.s2, s2.s2, 2u*sb + h); + const int l3 = q3_k_scale(s0.s3, s1.s3, s2.s3, 2u*sb + h); + + float a0 = 0.f, a1 = 0.f, a2 = 0.f, a3 = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const uint qsv = qsw[qsb + gg * mq]; // four rows, one load + const uint hmv = hmw[hmb + (gg >> 1) * mq]; + const uint hsh = 4u * (gg & 1u); + const float4 yv = vload4(grp + gg, y); // shared by all four + a0 += dot(yv, q3_k_vals((qsv ) & 0xFFu, ((hmv ) >> hsh) & 0xFu)); + a1 += dot(yv, q3_k_vals((qsv >> 8) & 0xFFu, ((hmv >> 8) >> hsh) & 0xFu)); + a2 += dot(yv, q3_k_vals((qsv >> 16) & 0xFFu, ((hmv >> 16) >> hsh) & 0xFu)); + a3 += dot(yv, q3_k_vals((qsv >> 24) & 0xFFu, ((hmv >> 24) >> hsh) & 0xFu)); + } + acc0 += (float)l0 * a0; + acc1 += (float)l1 * a1; + acc2 += (float)l2 * a2; + acc3 += (float)l3 * a3; + } + } + sumf += (float)dh.s0 * acc0; + sumf1 += (float)dh.s1 * acc1; + sumf2 += (float)dh.s2 * acc2; + sumf3 += (float)dh.s3 * acc3; + } + } +#elif Q3_K_MV_R == 2 + const uint mh = m >> 1; + const uint j = get_group_id(0) * 64u + lid; + const uint row = j << 1; + + float sumf = 0.f; + float sumf1 = 0.f; + + if (j < mh) { + global const ushort * qsu = (global const ushort *)src0_qs; + global const ushort * hmu = (global const ushort *)src0_hm; + + for (uint ib = sgi; ib < nsb; ib += Q3_K_MV_NSG) { + const half2 dh = vload2(j + ib * mh, src0_d); + const uint2 s0 = vload2(j + (3u * ib + 0u) * mh, src0_sc); + const uint2 s1 = vload2(j + (3u * ib + 1u) * mh, src0_sc); + const uint2 s2 = vload2(j + (3u * ib + 2u) * mh, src0_sc); + + float acc0 = 0.f, acc1 = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = j + grp * mh; + const uint hmb = j + (grp >> 1) * mh; + + for (uint h = 0; h < 2u; ++h) { // two 16-weight halves + const int l0 = q3_k_scale(s0.s0, s1.s0, s2.s0, 2u*sb + h); + const int l1 = q3_k_scale(s0.s1, s1.s1, s2.s1, 2u*sb + h); + + float a0 = 0.f, a1 = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const uint qsv = (uint)qsu[qsb + gg * mh]; + const uint hmv = (uint)hmu[hmb + (gg >> 1) * mh]; + const uint hsh = 4u * (gg & 1u); + const float4 yv = vload4(grp + gg, y); + a0 += dot(yv, q3_k_vals( qsv & 0xFFu, ( hmv >> hsh) & 0xFu)); + a1 += dot(yv, q3_k_vals((qsv >> 8) & 0xFFu, ((hmv >> 8) >> hsh) & 0xFu)); + } + acc0 += (float)l0 * a0; + acc1 += (float)l1 * a1; + } + } + sumf += (float)dh.s0 * acc0; + sumf1 += (float)dh.s1 * acc1; + } + } +#else + const uint row = get_group_id(0) * 64u + lid; + + float sumf = 0.f; + + if (row < m) { + for (uint ib = sgi; ib < nsb; ib += Q3_K_MV_NSG) { + const float d = (float)src0_d[row + ib * m]; + const uint s0 = src0_sc[row + (3u * ib + 0u) * m]; + const uint s1 = src0_sc[row + (3u * ib + 1u) * m]; + const uint s2 = src0_sc[row + (3u * ib + 2u) * m]; + + float acc = 0.f; + for (uint sb = 0; sb < 8u; ++sb) { + const uint grp = ib * 64u + sb * 8u; + const uint qsb = row + grp * m; + const uint hmb = row + (grp >> 1) * m; + + for (uint h = 0; h < 2u; ++h) { + const int l = q3_k_scale(s0, s1, s2, 2u*sb + h); + float a = 0.f; + for (uint u = 0; u < 4u; ++u) { + const uint gg = 4u*h + u; + const uint qsv = (uint)src0_qs[qsb + gg * m]; + const uint hmv = (uint)src0_hm[hmb + (gg >> 1) * m]; + const float4 yv = vload4(grp + gg, y); + a += dot(yv, q3_k_vals(qsv, (hmv >> (4u * (gg & 1u))) & 0xFu)); + } + acc += (float)l * a; + } + } + sumf += d * acc; + } + } +#endif + +#if Q3_K_MV_NSG > 1 +#if Q3_K_MV_R == 4 + __local float4 part[Q3_K_MV_NSG][64]; + part[sgi][lid] = (float4)(sumf, sumf1, sumf2, sumf3); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q3_K_MV_NSG; ++s) { + const float4 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + sumf2 += p.s2; + sumf3 += p.s3; + } +#elif Q3_K_MV_R == 2 + __local float2 part[Q3_K_MV_NSG][64]; + part[sgi][lid] = (float2)(sumf, sumf1); + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q3_K_MV_NSG; ++s) { + const float2 p = part[s][lid]; + sumf += p.s0; + sumf1 += p.s1; + } +#else + __local float part[Q3_K_MV_NSG][64]; + part[sgi][lid] = sumf; + barrier(CLK_LOCAL_MEM_FENCE); + if (sgi != 0) { + return; + } + for (uint s = 1; s < Q3_K_MV_NSG; ++s) { + sumf += part[s][lid]; + } +#endif +#endif + +#if Q3_K_MV_R == 4 + if (j < mq) { + vstore4((float4)(sumf, sumf1, sumf2, sumf3), 0, dst + (ulong)col * (uint)ne0 + row); + } +#elif Q3_K_MV_R == 2 + if (j < mh) { + vstore2((float2)(sumf, sumf1), 0, dst + (ulong)col * (uint)ne0 + row); + } +#else + if (row < m) { + dst[(ulong)col * (uint)ne0 + row] = sumf; + } +#endif +} diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32.cl index 0dcc929a6bea..6066ae3a9b40 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32.cl @@ -224,6 +224,8 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = N_SIMDGROUP * M; __private uint4 regA; @@ -234,7 +236,7 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( // loop along K in block granularity, skip 4 blocks every iter for (uint k = groupId; k < (K / QK4_0); k += N_SIMDGROUP) { - regS = src0_d[gid + k * LINE_STRIDE_A]; // each fiber loads scale of two rows + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // each fiber loads scale of two rows // first 4 fibers in each wave load 8 B values to its private scope if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); @@ -242,20 +244,20 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( } // load half weights for two blocks in consecutive rows - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), regS, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), regS, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), regS, regB); #else @@ -329,6 +331,8 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32_mc3( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); // BLOCK_STRIDE_A is the LAYOUT stride between consecutive K-blocks = 4 uints // per q4_0 block * M (set by the trans4_ns convert). The "4" is uints/block, NOT // the subgroup count — keep it fixed so the K-split count (nsg) can vary. @@ -347,17 +351,17 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32_mc3( __private float2 ts3 = (float2)(0.0f); for (uint k = groupId; k < (K / QK4_0); k += nsg) { - regS = src0_d[gid + k * LINE_STRIDE_A]; + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // weights loaded ONCE, reused across the columns - regA_hi.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA_hi.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA_hi.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA_hi.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA_lo.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA_lo.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA_lo.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA_lo.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA_hi.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA_hi.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA_hi.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA_hi.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA_lo.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA_lo.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA_lo.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA_lo.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; MC_COL_Q40(ts0, 0); MC_COL_Q40(ts1, 1); @@ -381,10 +385,12 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32_mc3( } dst = (global float*)((global char*)dst + offsetd); // dst is column-major [M rows x n_cols cols]: (row, col) at col*M + row - vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); - vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); - if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); - if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + if (gid < LINE_STRIDE_A) { + vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); + vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); + if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); + if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + } } } #undef MC_COL_Q40 diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32_spec.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32_spec.cl index 0dca20f71f92..63990c414044 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32_spec.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_0_f32_spec.cl @@ -210,6 +210,8 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( { uint groupId = get_local_id(1); uint gid = get_global_id(0); + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, (uint)LINE_STRIDE_A - 1u); ushort slid = get_sub_group_local_id(); __private uint4 regA; @@ -220,7 +222,7 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( // loop along K in block granularity, skip 4 blocks every iter for (uint k = groupId; k < (K / QK4_0); k += N_SIMDGROUP) { - regS = src0_d[gid + k * LINE_STRIDE_A]; // each fiber loads scale of two rows + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // each fiber loads scale of two rows // first 4 fibers in each wave load 8 B values to its private scope if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); @@ -228,20 +230,20 @@ __kernel void kernel_gemv_noshuffle_q4_0_f32( } // load half weights for two blocks in consecutive rows - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), regS, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), regS, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), regS, regB); #else diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_1_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_1_f32.cl index 2ccf4214c0bb..b0b4793d7f18 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_1_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_1_f32.cl @@ -209,6 +209,8 @@ kernel void kernel_gemv_noshuffle_q4_1_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; private uint4 regA; @@ -220,8 +222,8 @@ kernel void kernel_gemv_noshuffle_q4_1_f32( // loop along K in block granularity, skip 4 blocks every iter for (uint k = groupId; k < (K / QK4_0); k += NSUBGROUPS) { - regS = src0_d[gid + k * LINE_STRIDE_A]; // each fiber loads scale of two rows - regM = src0_m[gid + k * LINE_STRIDE_A]; // each fiber loads min of two rows + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // each fiber loads scale of two rows + regM = src0_m[gid_s + k * LINE_STRIDE_A]; // each fiber loads min of two rows // first 4 fibers in each wave load 8 B values to its private scope if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); @@ -229,20 +231,20 @@ kernel void kernel_gemv_noshuffle_q4_1_f32( } // load half weights for two blocks in consecutive rows - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAT dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), regS, regM, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), regS, regM, regB); #endif // VECTOR_SUB_GROUP_BROADCAT - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAT dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), regS, regM, regB); #else @@ -326,6 +328,8 @@ kernel void kernel_gemv_noshuffle_q4_1_f32_mc3( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; uint COL_STRIDE = K / 4; // float4 pixels per activation column @@ -339,18 +343,18 @@ kernel void kernel_gemv_noshuffle_q4_1_f32_mc3( private float2 ts3 = (float2)(0.0f); for (uint k = groupId; k < (K / QK4_0); k += NSUBGROUPS) { - regS = src0_d[gid + k * LINE_STRIDE_A]; - regM = src0_m[gid + k * LINE_STRIDE_A]; + regS = src0_d[gid_s + k * LINE_STRIDE_A]; + regM = src0_m[gid_s + k * LINE_STRIDE_A]; // weights loaded ONCE, reused across the columns - regA_hi.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA_hi.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA_hi.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA_hi.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA_lo.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA_lo.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA_lo.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA_lo.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA_hi.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA_hi.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA_hi.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA_hi.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA_lo.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA_lo.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA_lo.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA_lo.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; MC_COL_Q41(ts0, 0); MC_COL_Q41(ts1, 1); @@ -373,10 +377,12 @@ kernel void kernel_gemv_noshuffle_q4_1_f32_mc3( acc += reduceLM[SUBGROUP_SIZE * 2 + slid]; dst = (global float*)((global char*)dst + offsetd); // dst is column-major [M rows x n_cols cols]: (row, col) at col*M + row - vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); - vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); - if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); - if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + if (gid < LINE_STRIDE_A) { + vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); + vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); + if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); + if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + } } } #undef MC_COL_Q41 diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32.cl index 916e00118639..3dc30db5889f 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32.cl @@ -415,6 +415,8 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_glu( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = 4 * M; private uint4 regA; @@ -434,9 +436,9 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_glu( for (uint k = groupId; k < (K / 32); k += nsg) { \ uint sb = k / 8; \ uint j = k % 8; \ - half2 d = DD[gid + sb * LINE_STRIDE_A]; \ - half2 dm = MM[gid + sb * LINE_STRIDE_A]; \ - global const uchar * sc0 = SS + sb * 12 * M + 2 * gid; \ + half2 d = DD[gid_s + sb * LINE_STRIDE_A]; \ + half2 dm = MM[gid_s + sb * LINE_STRIDE_A]; \ + global const uchar * sc0 = SS + sb * 12 * M + 2 * gid_s; \ global const uchar * sc1 = sc0 + 1; \ uchar sv0, mn0, sv1, mn1; \ get_scale_min_k4(j, sc0, M, &sv0, &mn0, mask_d6, mask_d4, mask_hi2); \ @@ -447,15 +449,15 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_glu( regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); \ regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); \ } \ - regA.s0 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; \ - regA.s1 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; \ - regA.s2 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; \ - regA.s3 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; \ + regA.s0 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; \ + regA.s1 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; \ + regA.s2 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; \ + regA.s3 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; \ DEQ_HI(SUM, as_ushort8(regA), regS, regM, regB); \ - regA.s0 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; \ - regA.s1 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; \ - regA.s2 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; \ - regA.s3 = read_imageui(Q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; \ + regA.s0 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; \ + regA.s1 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; \ + regA.s2 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; \ + regA.s3 = read_imageui(Q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; \ DEQ_LO(SUM, as_ushort8(regA), regS, regM, regB); \ } @@ -489,8 +491,10 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_glu( upSum += p.zw; } dst = (global float*)((global char*)dst + offsetd); - dst[gid * 2 + 0] = glu_apply(glu_op, gateSum.s0, upSum.s0); - dst[gid * 2 + 1] = glu_apply(glu_op, gateSum.s1, upSum.s1); + if (gid < LINE_STRIDE_A) { + dst[gid * 2 + 0] = glu_apply(glu_op, gateSum.s0, upSum.s0); + dst[gid * 2 + 1] = glu_apply(glu_op, gateSum.s1, upSum.s1); + } } } @@ -533,6 +537,9 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_splitk( uint LINE_STRIDE_A = M / 2; uint BLOCK_STRIDE_A = 4 * M; // physical, independent of the K-split + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); + private uint4 regA; private half2 regS, regM; private float8 regB; @@ -542,9 +549,9 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_splitk( for (uint k = kslice * nsg + groupId; k < (K / 32); k += ksplit * nsg) { uint sb = k / 8; uint j = k % 8; - half2 d = src0_d[gid + sb * LINE_STRIDE_A]; - half2 dm = src0_m[gid + sb * LINE_STRIDE_A]; - global const uchar * sc0 = src0_s + sb * 12 * M + 2 * gid; + half2 d = src0_d[gid_s + sb * LINE_STRIDE_A]; + half2 dm = src0_m[gid_s + sb * LINE_STRIDE_A]; + global const uchar * sc0 = src0_s + sb * 12 * M + 2 * gid_s; global const uchar * sc1 = sc0 + 1; uchar sv0, mn0, sv1, mn1; get_scale_min_k4(j, sc0, M, &sv0, &mn0, mask_d6, mask_d4, mask_hi2); @@ -555,19 +562,19 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_splitk( regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); } - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), regS, regM, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), regS, regM, regB); #endif - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), regS, regM, regB); #else @@ -584,7 +591,9 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_splitk( for (uint i = 0; i < nsg - 1; ++i) { totalSum += reduceLM[SUBGROUP_SIZE * i + slid]; } - vstore2(totalSum, 0, &(partial[kslice * M + gid * 2])); + // Keep tail stores inside this K-slice. + if (gid * 2 + 0 < M) partial[kslice * M + gid * 2 + 0] = totalSum.s0; + if (gid * 2 + 1 < M) partial[kslice * M + gid * 2 + 1] = totalSum.s1; } } @@ -689,6 +698,8 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_mc3( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; uint COL_STRIDE = K / 4; // float4 pixels per activation column @@ -713,10 +724,10 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_mc3( uint sb = k / 8; uint j = k % 8; - half2 d = src0_d[gid + sb * LINE_STRIDE_A]; - half2 dm = src0_m[gid + sb * LINE_STRIDE_A]; + half2 d = src0_d[gid_s + sb * LINE_STRIDE_A]; + half2 dm = src0_m[gid_s + sb * LINE_STRIDE_A]; - global const uchar * sc0 = src0_s + sb * 12 * M + 2 * gid; + global const uchar * sc0 = src0_s + sb * 12 * M + 2 * gid_s; global const uchar * sc1 = sc0 + 1; uchar sv0, mn0, sv1, mn1; @@ -727,14 +738,14 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_mc3( regM = convert_half2(convert_float2(dm) * convert_float2((uchar2)(mn0, mn1))); // weights loaded ONCE, reused across the 3 columns - regA_hi.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA_hi.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA_hi.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA_hi.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA_lo.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA_lo.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA_lo.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA_lo.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA_hi.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA_hi.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA_hi.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA_hi.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA_lo.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA_lo.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA_lo.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA_lo.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef Q4K_MC3_DEQUANT_ONCE // Dequant the 32 weights/row (16 hi + 16 lo) ONCE into half2[] (byte- @@ -827,8 +838,10 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_mc3( acc += reduceLM[SUBGROUP_SIZE * 2 + slid]; dst = (global float*)((global char*)dst + offsetd); // dst is column-major [M rows x 3 cols]: (row, col) at col*M + row - vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); - vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); - vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); + if (gid < LINE_STRIDE_A) { + vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); + vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); + vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); + } } } diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32_o4.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32_o4.cl index 02916bb91ffa..2c1c659a31e8 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32_o4.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q4_k_f32_o4.cl @@ -231,8 +231,9 @@ kernel void kernel_gemv_noshuffle_q4_k_f32_o4( // Two consecutive pair-indices (each the same access pattern the 2-output // kernel uses); together they cover 4 consecutive output rows. - uint gid_a = gid * 2; - uint gid_b = gid * 2 + 1; + // Keep tail lanes active for subgroup ops, but read valid weight pairs. + uint gid_a = min(gid * 2, (uint)(ne01 / 2) - 1u); + uint gid_b = min(gid * 2 + 1, (uint)(ne01 / 2) - 1u); uint K = ne00; uint M = ne01; diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_0_f32.cl index 7dbf5a3bbbfb..d8537e158ee3 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_0_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_0_f32.cl @@ -209,6 +209,8 @@ __kernel void kernel_gemv_noshuffle_q5_0_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; private uint4 regA; @@ -218,13 +220,13 @@ __kernel void kernel_gemv_noshuffle_q5_0_f32( private float2 totalSum = (float2)(0.0f); for (uint k = groupId; k < (K / QK5_0); k += NSUBGROUPS) { - regS = src0_d[gid + k * LINE_STRIDE_A]; + regS = src0_d[gid_s + k * LINE_STRIDE_A]; ushort4 qh_raw; - qh_raw.s0 = src0_qh[gid + (4*k + 0) * LINE_STRIDE_A]; - qh_raw.s1 = src0_qh[gid + (4*k + 1) * LINE_STRIDE_A]; - qh_raw.s2 = src0_qh[gid + (4*k + 2) * LINE_STRIDE_A]; - qh_raw.s3 = src0_qh[gid + (4*k + 3) * LINE_STRIDE_A]; + qh_raw.s0 = src0_qh[gid_s + (4*k + 0) * LINE_STRIDE_A]; + qh_raw.s1 = src0_qh[gid_s + (4*k + 1) * LINE_STRIDE_A]; + qh_raw.s2 = src0_qh[gid_s + (4*k + 2) * LINE_STRIDE_A]; + qh_raw.s3 = src0_qh[gid_s + (4*k + 3) * LINE_STRIDE_A]; uchar8 raw = as_uchar8(qh_raw); uchar8 qh_bytes = (uchar8)(raw.s0, raw.s2, raw.s4, raw.s6, @@ -236,10 +238,10 @@ __kernel void kernel_gemv_noshuffle_q5_0_f32( regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); } - regA.s0 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_q5_0_sgbroadcast_8_hi(totalSum, as_ushort8(regA), qh_bytes, regS, regB); @@ -247,10 +249,10 @@ __kernel void kernel_gemv_noshuffle_q5_0_f32( dequantizeBlockAccum_ns_q5_0_sgbroadcast_1_hi(totalSum, as_ushort8(regA), qh_bytes, regS, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_q5_0_sgbroadcast_8_lo(totalSum, as_ushort8(regA), qh_bytes, regS, regB); #else diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_1_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_1_f32.cl index ba0e2a711565..82b4c741e804 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_1_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_1_f32.cl @@ -210,6 +210,8 @@ __kernel void kernel_gemv_noshuffle_q5_1_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; __private uint4 regA; @@ -220,14 +222,14 @@ __kernel void kernel_gemv_noshuffle_q5_1_f32( __private float2 totalSum = (float2)(0.0f); for (uint k = groupId; k < (K / QK5_1); k += NSUBGROUPS) { - regS = src0_d[gid + k * LINE_STRIDE_A]; - regM = src0_m[gid + k * LINE_STRIDE_A]; + regS = src0_d[gid_s + k * LINE_STRIDE_A]; + regM = src0_m[gid_s + k * LINE_STRIDE_A]; ushort4 qh_raw; - qh_raw.s0 = src0_qh[gid + (4*k + 0) * LINE_STRIDE_A]; - qh_raw.s1 = src0_qh[gid + (4*k + 1) * LINE_STRIDE_A]; - qh_raw.s2 = src0_qh[gid + (4*k + 2) * LINE_STRIDE_A]; - qh_raw.s3 = src0_qh[gid + (4*k + 3) * LINE_STRIDE_A]; + qh_raw.s0 = src0_qh[gid_s + (4*k + 0) * LINE_STRIDE_A]; + qh_raw.s1 = src0_qh[gid_s + (4*k + 1) * LINE_STRIDE_A]; + qh_raw.s2 = src0_qh[gid_s + (4*k + 2) * LINE_STRIDE_A]; + qh_raw.s3 = src0_qh[gid_s + (4*k + 3) * LINE_STRIDE_A]; uchar8 raw = as_uchar8(qh_raw); uchar8 qh_bytes = (uchar8)(raw.s0, raw.s2, raw.s4, raw.s6, @@ -239,10 +241,10 @@ __kernel void kernel_gemv_noshuffle_q5_1_f32( regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); } - regA.s0 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_q5_1_sgbroadcast_8_hi(totalSum, as_ushort8(regA), qh_bytes, regS, regM, regB); @@ -250,10 +252,10 @@ __kernel void kernel_gemv_noshuffle_q5_1_f32( dequantizeBlockAccum_ns_q5_1_sgbroadcast_1_hi(totalSum, as_ushort8(regA), qh_bytes, regS, regM, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_qs, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_qs, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_q5_1_sgbroadcast_8_lo(totalSum, as_ushort8(regA), qh_bytes, regS, regM, regB); #else diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_k_f32.cl index ae864b19ba9a..6570167c9a68 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_k_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q5_k_f32.cl @@ -232,6 +232,8 @@ kernel void kernel_gemv_noshuffle_q5_k_f32( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; uint LINE_STRIDE_A_QH = M / 2; @@ -250,11 +252,11 @@ kernel void kernel_gemv_noshuffle_q5_k_f32( uint sb = k / 8; uint j = k % 8; - half2 d = src0_d[gid + sb * LINE_STRIDE_A]; - half2 dm = src0_m[gid + sb * LINE_STRIDE_A]; + half2 d = src0_d[gid_s + sb * LINE_STRIDE_A]; + half2 dm = src0_m[gid_s + sb * LINE_STRIDE_A]; - global const uchar * sc0 = src0_s + 2 * gid * scales_per_row + sb * 12; - global const uchar * sc1 = src0_s + (2 * gid + 1) * scales_per_row + sb * 12; + global const uchar * sc0 = src0_s + 2 * gid_s * scales_per_row + sb * 12; + global const uchar * sc1 = src0_s + (2 * gid_s + 1) * scales_per_row + sb * 12; uchar sv0, mn0, sv1, mn1; get_scale_min_k4(j, sc0, &sv0, &mn0, mask_d6, mask_d4, mask_hi2); @@ -268,25 +270,25 @@ kernel void kernel_gemv_noshuffle_q5_k_f32( regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); } - regH.s0 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 0)).x); - regH.s1 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 1)).x); - regH.s2 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 2)).x); - regH.s3 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 3)).x); + regH.s0 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 0)).x); + regH.s1 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 1)).x); + regH.s2 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 2)).x); + regH.s3 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 3)).x); - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_hi(totalSum, as_ushort8(regA), as_uchar8(regH), regS, regM, regB); #else dequantizeBlockAccum_ns_sgbroadcast_1_hi(totalSum, as_ushort8(regA), as_uchar8(regH), regS, regM, regB); #endif // VECTOR_SUB_GROUP_BROADCAST - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; #ifdef VECTOR_SUB_GROUP_BROADCAST dequantizeBlockAccum_ns_sgbroadcast_8_lo(totalSum, as_ushort8(regA), as_uchar8(regH), regS, regM, regB); #else @@ -373,6 +375,8 @@ kernel void kernel_gemv_noshuffle_q5_k_f32_mc3( uint M = ne01; uint LINE_STRIDE_A = M / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = NSUBGROUPS * M; uint LINE_STRIDE_A_QH = M / 2; uint BLOCK_STRIDE_A_QH = NSUBGROUPS * M / 2; @@ -393,11 +397,11 @@ kernel void kernel_gemv_noshuffle_q5_k_f32_mc3( uint sb = k / 8; uint j = k % 8; - half2 d = src0_d[gid + sb * LINE_STRIDE_A]; - half2 dm = src0_m[gid + sb * LINE_STRIDE_A]; + half2 d = src0_d[gid_s + sb * LINE_STRIDE_A]; + half2 dm = src0_m[gid_s + sb * LINE_STRIDE_A]; - global const uchar * sc0 = src0_s + 2 * gid * scales_per_row + sb * 12; - global const uchar * sc1 = src0_s + (2 * gid + 1) * scales_per_row + sb * 12; + global const uchar * sc0 = src0_s + 2 * gid_s * scales_per_row + sb * 12; + global const uchar * sc1 = src0_s + (2 * gid_s + 1) * scales_per_row + sb * 12; uchar sv0, mn0, sv1, mn1; get_scale_min_k4(j, sc0, &sv0, &mn0, mask_d6, mask_d4, mask_hi2); @@ -407,19 +411,19 @@ kernel void kernel_gemv_noshuffle_q5_k_f32_mc3( regM = convert_half2(convert_float2(dm) * convert_float2((uchar2)(mn0, mn1))); // high-bit plane + weights loaded ONCE, reused across the columns - regH.s0 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 0)).x); - regH.s1 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 1)).x); - regH.s2 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 2)).x); - regH.s3 = as_ushort(read_imageh(src0_qh, (gid + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 3)).x); - - regA_hi.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA_hi.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA_hi.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA_hi.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA_lo.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA_lo.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA_lo.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA_lo.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regH.s0 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 0)).x); + regH.s1 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 1)).x); + regH.s2 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 2)).x); + regH.s3 = as_ushort(read_imageh(src0_qh, (gid_s + k * BLOCK_STRIDE_A_QH + LINE_STRIDE_A_QH * 3)).x); + + regA_hi.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA_hi.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA_hi.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA_hi.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA_lo.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA_lo.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA_lo.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA_lo.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; MC_COL_Q5K(ts0, 0); MC_COL_Q5K(ts1, 1); @@ -442,10 +446,12 @@ kernel void kernel_gemv_noshuffle_q5_k_f32_mc3( acc += reduceLM[SUBGROUP_SIZE * 2 + slid]; dst = (global float*)((global char*)dst + offsetd); // dst is column-major [M rows x n_cols cols]: (row, col) at col*M + row - vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); - vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); - if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); - if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + if (gid < LINE_STRIDE_A) { + vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0 * M + gid * 2])); + vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1 * M + gid * 2])); + if (n_cols > 2) vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2 * M + gid * 2])); + if (n_cols > 3) vstore2((float2)(acc.s6, acc.s7), 0, &(dst[3 * M + gid * 2])); + } } } #undef MC_COL_Q5K diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32.cl index 32624ac868fe..a6908a6a7089 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32.cl @@ -219,26 +219,28 @@ kernel void kernel_gemv_noshuffle_q6_K_f32( float2 total_sum = 0.0f; int line_stride_a = ne01 / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + int gid_s = min(gid, line_stride_a - 1); int block_stride_a = NSUBGROUPS * ne01; for (int k = grp; k < nb; k += NSUBGROUPS) { - reg_d = src0_d[gid + k/8 * line_stride_a]; - reg_s = as_char4(src0_s[gid + k * line_stride_a]); + reg_d = src0_d[gid_s + k/8 * line_stride_a]; + reg_s = as_char4(src0_s[gid_s + k * line_stride_a]); if (slid < 4) { reg_b.s0123 = read_imagef(src1, 0 + slid*2 + k*8); reg_b.s4567 = read_imagef(src1, 1 + slid*2 + k*8); } - reg_a_l.s0 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*0).x; - reg_a_l.s1 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*1).x; - reg_a_l.s2 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*2).x; - reg_a_l.s3 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*3).x; + reg_a_l.s0 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*0).x; + reg_a_l.s1 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*1).x; + reg_a_l.s2 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*2).x; + reg_a_l.s3 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*3).x; - reg_a_h.s0 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*0).x); - reg_a_h.s1 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*1).x); - reg_a_h.s2 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*2).x); - reg_a_h.s3 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*3).x); + reg_a_h.s0 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*0).x); + reg_a_h.s1 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*1).x); + reg_a_h.s2 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*2).x); + reg_a_h.s3 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*3).x); #ifdef VECTOR_SUB_GROUP_BROADCAT dequantize_block_acc_bcast_8_hi(total_sum, as_ushort8(reg_a_l), as_uchar8(reg_a_h), reg_d, reg_s, reg_b); @@ -246,15 +248,15 @@ kernel void kernel_gemv_noshuffle_q6_K_f32( dequantize_block_acc_bcast_1_hi(total_sum, as_ushort8(reg_a_l), as_uchar8(reg_a_h), reg_d, reg_s, reg_b); #endif // VECTOR_SUB_GROUP_BROADCAT - reg_a_l.s0 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*4).x; - reg_a_l.s1 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*5).x; - reg_a_l.s2 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*6).x; - reg_a_l.s3 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*7).x; + reg_a_l.s0 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*4).x; + reg_a_l.s1 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*5).x; + reg_a_l.s2 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*6).x; + reg_a_l.s3 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*7).x; - reg_a_h.s0 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*4).x); - reg_a_h.s1 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*5).x); - reg_a_h.s2 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*6).x); - reg_a_h.s3 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*7).x); + reg_a_h.s0 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*4).x); + reg_a_h.s1 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*5).x); + reg_a_h.s2 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*6).x); + reg_a_h.s3 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*7).x); #ifdef VECTOR_SUB_GROUP_BROADCAT dequantize_block_acc_bcast_8_lo(total_sum, as_ushort8(reg_a_l), as_uchar8(reg_a_h), reg_d, reg_s, reg_b); @@ -323,6 +325,8 @@ kernel void kernel_gemv_noshuffle_q6_K_f32_mc3( int nb = ne00 / 32; int line_stride_a = ne01 / 2; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + int gid_s = min(gid, line_stride_a - 1); int block_stride_a = NSUBGROUPS * ne01; int COL_STRIDE = ne00 / 4; // float4 pixels per activation column @@ -335,27 +339,27 @@ kernel void kernel_gemv_noshuffle_q6_K_f32_mc3( float2 ts0 = 0.0f, ts1 = 0.0f, ts2 = 0.0f; for (int k = grp; k < nb; k += NSUBGROUPS) { - reg_d = src0_d[gid + k/8 * line_stride_a]; - reg_s = as_char4(src0_s[gid + k * line_stride_a]); + reg_d = src0_d[gid_s + k/8 * line_stride_a]; + reg_s = as_char4(src0_s[gid_s + k * line_stride_a]); // weights loaded ONCE (hi: blocks 0-3, lo: blocks 4-7), reused x3 cols - ql_hi.s0 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*0).x; - ql_hi.s1 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*1).x; - ql_hi.s2 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*2).x; - ql_hi.s3 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*3).x; - qh_hi.s0 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*0).x); - qh_hi.s1 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*1).x); - qh_hi.s2 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*2).x); - qh_hi.s3 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*3).x); - - ql_lo.s0 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*4).x; - ql_lo.s1 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*5).x; - ql_lo.s2 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*6).x; - ql_lo.s3 = read_imageui(src0_ql, gid + k*block_stride_a + line_stride_a*7).x; - qh_lo.s0 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*4).x); - qh_lo.s1 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*5).x); - qh_lo.s2 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*6).x); - qh_lo.s3 = as_ushort(read_imageh(src0_qh, gid + k*block_stride_a + line_stride_a*7).x); + ql_hi.s0 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*0).x; + ql_hi.s1 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*1).x; + ql_hi.s2 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*2).x; + ql_hi.s3 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*3).x; + qh_hi.s0 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*0).x); + qh_hi.s1 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*1).x); + qh_hi.s2 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*2).x); + qh_hi.s3 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*3).x); + + ql_lo.s0 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*4).x; + ql_lo.s1 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*5).x; + ql_lo.s2 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*6).x; + ql_lo.s3 = read_imageui(src0_ql, gid_s + k*block_stride_a + line_stride_a*7).x; + qh_lo.s0 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*4).x); + qh_lo.s1 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*5).x); + qh_lo.s2 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*6).x); + qh_lo.s3 = as_ushort(read_imageh(src0_qh, gid_s + k*block_stride_a + line_stride_a*7).x); // Per-column: load only this column's activation (single reg_b live) -> // 1/3 the activation register pressure, cutting the private-mem spill. @@ -402,8 +406,10 @@ kernel void kernel_gemv_noshuffle_q6_K_f32_mc3( acc += reduce_lm[SUBGROUP_SIZE*2 + slid]; dst = (global float*)((global char*)dst + offsetd); // dst column-major [ne01 rows x 3 cols]: (row, col) at col*ne01 + row - vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0*ne01 + gid*2])); - vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1*ne01 + gid*2])); - vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2*ne01 + gid*2])); + if (gid < line_stride_a) { + vstore2((float2)(acc.s0, acc.s1), 0, &(dst[0*ne01 + gid*2])); + vstore2((float2)(acc.s2, acc.s3), 0, &(dst[1*ne01 + gid*2])); + vstore2((float2)(acc.s4, acc.s5), 0, &(dst[2*ne01 + gid*2])); + } } } diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32_o4.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32_o4.cl index 84447e61bb6f..22efb6c3caa6 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32_o4.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q6_k_f32_o4.cl @@ -249,8 +249,9 @@ kernel void Q6K_O4_NAME( // ne01/4 apart) is slower because two distant cache-line streams have worse // locality than the adjacent pair whose reads interleave into the same lines // each iteration. - int gid_a = gid * 2; - int gid_b = gid * 2 + 1; + // Keep tail lanes active for subgroup ops, but read valid weight pairs. + int gid_a = min(gid * 2, ne01 / 2 - 1); + int gid_b = min(gid * 2 + 1, ne01 / 2 - 1); int nb = ne00 / 32; diff --git a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q8_0_f32.cl b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q8_0_f32.cl index 6f6d7425c656..6109c967aac1 100644 --- a/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q8_0_f32.cl +++ b/ggml/src/ggml-opencl/kernels/gemv_noshuffle_q8_0_f32.cl @@ -155,6 +155,8 @@ __kernel void kernel_gemv_noshuffle_q8_0_f32_splitk( uint M = ne01; uint LINE_STRIDE_A = M; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = 8 * M; // physical, independent of the K-split __private uint8 regA; @@ -164,19 +166,19 @@ __kernel void kernel_gemv_noshuffle_q8_0_f32_splitk( #pragma unroll 1 for (uint k = kslice * nsg + groupId; k < (K / QK8_0); k += ksplit * nsg) { - regS = src0_d[gid + k * LINE_STRIDE_A]; + regS = src0_d[gid_s + k * LINE_STRIDE_A]; if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); regB.s4567 = read_imagef(src1, (1 + slid * 2 + k * 8)); } - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA.s4 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s5 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s6 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s7 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s4 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s5 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s6 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s7 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; dequantizeBlockAccum_ns_sgbroadcast_1(totalSum, regA, convert_float(regS), regB); } @@ -227,6 +229,8 @@ __kernel void kernel_gemv_noshuffle_q8_0_f32( uint M = ne01; uint LINE_STRIDE_A = M; + // Keep tail lanes active for subgroup ops, but read a valid weight row. + uint gid_s = min(gid, LINE_STRIDE_A - 1); uint BLOCK_STRIDE_A = 8 * M; // 32 / 4 = 8 __private uint8 regA; @@ -238,7 +242,7 @@ __kernel void kernel_gemv_noshuffle_q8_0_f32( // loop along K in block granularity, skip 4 blocks every iter #pragma unroll 1 /* tell compiler not to unroll */ for (uint k = groupId; k < (K / QK8_0); k += N_SIMDGROUP) { - regS = src0_d[gid + k * LINE_STRIDE_A]; // each fiber loads scale of one rows + regS = src0_d[gid_s + k * LINE_STRIDE_A]; // each fiber loads the scale of one row // first 4 fibers in each wave load 8 B values to its private scope if (slid < 4) { regB.s0123 = read_imagef(src1, (slid * 2 + k * 8)); @@ -246,14 +250,14 @@ __kernel void kernel_gemv_noshuffle_q8_0_f32( } // load weights for one block in consecutive rows - regA.s0 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; - regA.s1 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; - regA.s2 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; - regA.s3 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; - regA.s4 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; - regA.s5 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; - regA.s6 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; - regA.s7 = read_imageui(src0_q, (gid + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; + regA.s0 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 0)).x; + regA.s1 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 1)).x; + regA.s2 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 2)).x; + regA.s3 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 3)).x; + regA.s4 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 4)).x; + regA.s5 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 5)).x; + regA.s6 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 6)).x; + regA.s7 = read_imageui(src0_q, (gid_s + k * BLOCK_STRIDE_A + LINE_STRIDE_A * 7)).x; dequantizeBlockAccum_ns_sgbroadcast_1(totalSum, regA, convert_float(regS), regB); } diff --git a/ggml/src/ggml-opencl/kernels/get_rows.cl b/ggml/src/ggml-opencl/kernels/get_rows.cl index 9ae4fff09fc2..f060e46aecc1 100644 --- a/ggml/src/ggml-opencl/kernels/get_rows.cl +++ b/ggml/src/ggml-opencl/kernels/get_rows.cl @@ -106,6 +106,53 @@ kernel void kernel_get_rows_f32( } } +kernel void kernel_get_rows_i32( + global void * src0, + ulong offset0, + global int * src1, + ulong offset1, + global int * dst, + ulong offsetd, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = (global void*)((global char*)src0 + offset0); + src1 = (global int*)((global char*)src1 + offset1); + dst = (global int*)((global char*)dst + offsetd); + + int nchunks = get_num_groups(0) / ne10; + int g = get_group_id(0); + int i10 = g / nchunks; + int chunk = g - i10 * nchunks; + int i11 = get_group_id(1); + int i12 = get_group_id(2); + + int r = ((global int *) ((global char *) src1 + i12*nb12 + i11*nb11 + i10*nb10))[0]; + + int i02 = i11; + int i03 = i12; + + global int * dst_row = (global int *) ((global char *) dst + i12*nb3 + i11*nb2 + i10*nb1); + global int * src_row = (global int *) ((global char *) src0 + r*nb01 + i02*nb02 + i03*nb03); + + int span = (ne00 + nchunks - 1) / nchunks; + int start = chunk * span; + int end = min(start + span, ne00); + + for (int ind = start + get_local_id(0); ind < end; ind += get_local_size(0)) { + dst_row[ind] = src_row[ind]; + } +} + kernel void kernel_get_rows_f16( global void * src0, ulong offset0, diff --git a/ggml/src/ggml-opencl/kernels/im2col_3d_f16.cl b/ggml/src/ggml-opencl/kernels/im2col_3d_f16.cl new file mode 100644 index 000000000000..a165e4460460 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/im2col_3d_f16.cl @@ -0,0 +1,90 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +kernel void kernel_im2col_3d_f16( + global float * src1, + ulong offset1, + global half * dst, + ulong offsetd, + long IC, + long ID, + long IH, + long IW, + long KD, + long KH, + long KW, + long OD, + long OH, + long OW, + long N, + long stride_x, + long stride_y, + long stride_z, + long stride_q, + int s0, + int s1, + int s2, + int p0, + int p1, + int p2, + int d0, + int d1, + int d2 +) { + const int ic = (int)IC; + const int kd = (int)KD; + const int kh = (int)KH; + const int kw = (int)KW; + const int od = (int)OD; + const int oh = (int)OH; + const int ow = (int)OW; + const int n = (int)N; + + const int KD_KH_KW = kd * kh * kw; + const int KH_KW = kh * kw; + const int IC_KD_KH_KW = ic * KD_KH_KW; + + const int i = (int)get_global_id(0); + if (i >= IC_KD_KH_KW) { + return; + } + + const int iow = (int)get_global_id(1); + if (iow >= ow) { + return; + } + + const int OD_OH = od * oh; + const int iz = (int)get_global_id(2); + if (iz >= n * OD_OH) { + return; + } + + src1 = (global float*)((global char*)src1 + offset1); + dst = (global half*)((global char*)dst + offsetd); + + const int iic = i / KD_KH_KW; + const int ikd = (i - iic * KD_KH_KW) / KH_KW; + const int ikh = (i - iic * KD_KH_KW - ikd * KH_KW) / kw; + const int ikw = i % kw; + + const int in = iz / OD_OH; + const int iod = (iz - in * OD_OH) / oh; + const int ioh = iz % oh; + + const int iiw = iow * s0 + ikw * d0 - p0; + const int iih = ioh * s1 + ikh * d1 - p1; + const int iid = iod * s2 + ikd * d2 - p2; + + const long offset_dst = + (long)(iz * ow + iow) * (long)IC_KD_KH_KW + + (long)(iic * KD_KH_KW + ikd * KH_KW + ikh * kw + ikw); + + if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW || iid < 0 || iid >= ID) { + dst[offset_dst] = 0.0f; + } else { + const long offset_src = + (long)(in * ic + iic) * stride_q + (long)iid * stride_z + + (long)iih * stride_y + (long)iiw * stride_x; + dst[offset_dst] = convert_half_rte(src1[offset_src]); + } +} diff --git a/ggml/src/ggml-opencl/kernels/im2col_3d_f32.cl b/ggml/src/ggml-opencl/kernels/im2col_3d_f32.cl new file mode 100644 index 000000000000..ea94d5a5d083 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/im2col_3d_f32.cl @@ -0,0 +1,90 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +kernel void kernel_im2col_3d_f32( + global float * src1, + ulong offset1, + global float * dst, + ulong offsetd, + long IC, + long ID, + long IH, + long IW, + long KD, + long KH, + long KW, + long OD, + long OH, + long OW, + long N, + long stride_x, + long stride_y, + long stride_z, + long stride_q, + int s0, + int s1, + int s2, + int p0, + int p1, + int p2, + int d0, + int d1, + int d2 +) { + const int ic = (int)IC; + const int kd = (int)KD; + const int kh = (int)KH; + const int kw = (int)KW; + const int od = (int)OD; + const int oh = (int)OH; + const int ow = (int)OW; + const int n = (int)N; + + const int KD_KH_KW = kd * kh * kw; + const int KH_KW = kh * kw; + const int IC_KD_KH_KW = ic * KD_KH_KW; + + const int i = (int)get_global_id(0); + if (i >= IC_KD_KH_KW) { + return; + } + + const int iow = (int)get_global_id(1); + if (iow >= ow) { + return; + } + + const int OD_OH = od * oh; + const int iz = (int)get_global_id(2); + if (iz >= n * OD_OH) { + return; + } + + src1 = (global float*)((global char*)src1 + offset1); + dst = (global float*)((global char*)dst + offsetd); + + const int iic = i / KD_KH_KW; + const int ikd = (i - iic * KD_KH_KW) / KH_KW; + const int ikh = (i - iic * KD_KH_KW - ikd * KH_KW) / kw; + const int ikw = i % kw; + + const int in = iz / OD_OH; + const int iod = (iz - in * OD_OH) / oh; + const int ioh = iz % oh; + + const int iiw = iow * s0 + ikw * d0 - p0; + const int iih = ioh * s1 + ikh * d1 - p1; + const int iid = iod * s2 + ikd * d2 - p2; + + const long offset_dst = + (long)(iz * ow + iow) * (long)IC_KD_KH_KW + + (long)(iic * KD_KH_KW + ikd * KH_KW + ikh * kw + ikw); + + if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW || iid < 0 || iid >= ID) { + dst[offset_dst] = 0.0f; + } else { + const long offset_src = + (long)(in * ic + iic) * stride_q + (long)iid * stride_z + + (long)iih * stride_y + (long)iiw * stride_x; + dst[offset_dst] = src1[offset_src]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/iq1_s_grid.cl b/ggml/src/ggml-opencl/kernels/iq1_s_grid.cl new file mode 100644 index 000000000000..df28039e059a --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq1_s_grid.cl @@ -0,0 +1,259 @@ +// IQ1 codebook: each byte packs grid[j] + 1 and grid[j + 4] + 1. +constant uint iq1_s_grid[2048] = { + 0x00000000, 0x00000002, 0x00000101, 0x00000200, 0x00000202, 0x00010001, 0x00010101, 0x00020000, + 0x00020002, 0x00020200, 0x00020202, 0x01000101, 0x01010001, 0x01010100, 0x01010102, 0x01020101, + 0x02000000, 0x02000002, 0x02000200, 0x02000202, 0x02010101, 0x02020000, 0x02020002, 0x02020200, + 0x02020202, 0x00000110, 0x00000111, 0x00010011, 0x00010110, 0x00010112, 0x00010211, 0x00010212, + 0x00020111, 0x01000011, 0x01000112, 0x01000211, 0x01010012, 0x01010111, 0x01010212, 0x01020011, + 0x01020110, 0x01020112, 0x01020210, 0x02000111, 0x02010011, 0x02010110, 0x02010112, 0x02020111, + 0x00000020, 0x00000022, 0x00000220, 0x00000222, 0x00010121, 0x00020020, 0x00020022, 0x00020220, + 0x00020222, 0x01000121, 0x01010021, 0x01010221, 0x01020120, 0x01020221, 0x02000020, 0x02000022, + 0x02000220, 0x02000222, 0x02010021, 0x02010121, 0x02010221, 0x02020020, 0x02020022, 0x02020220, + 0x02020222, 0x00011001, 0x00011100, 0x00011102, 0x00021101, 0x01001001, 0x01001201, 0x01011101, + 0x01011202, 0x01021100, 0x01021101, 0x02011001, 0x02011201, 0x02021101, 0x00001011, 0x00001110, + 0x00001111, 0x00001112, 0x00011111, 0x00011210, 0x00011212, 0x00021211, 0x01001010, 0x01001111, + 0x01001212, 0x01011010, 0x01011011, 0x01011110, 0x01011111, 0x01011112, 0x01011211, 0x01021010, + 0x01021012, 0x01021111, 0x01021210, 0x01021212, 0x02001011, 0x02011011, 0x02011111, 0x02011210, + 0x02011212, 0x02021011, 0x02021110, 0x02021111, 0x02021112, 0x02021211, 0x00011120, 0x00011221, + 0x01001021, 0x01001120, 0x01011020, 0x01011022, 0x01011121, 0x01011220, 0x01021020, 0x01021021, + 0x01021122, 0x01021221, 0x02001121, 0x02011021, 0x02011120, 0x02011221, 0x00002000, 0x00002002, + 0x00002200, 0x00002202, 0x00012101, 0x00022000, 0x00022002, 0x00022200, 0x00022202, 0x01002101, + 0x01012001, 0x01012102, 0x01022101, 0x02002000, 0x02002002, 0x02002200, 0x02002202, 0x02012101, + 0x02022000, 0x02022002, 0x02022200, 0x02022202, 0x00002111, 0x00012011, 0x00012110, 0x00012211, + 0x00022110, 0x00022111, 0x01002011, 0x01012010, 0x01012011, 0x01012111, 0x01022011, 0x01022110, + 0x01022211, 0x02012011, 0x02012110, 0x02012112, 0x02012211, 0x02022111, 0x00002020, 0x00002022, + 0x00002220, 0x00002222, 0x00012121, 0x00022020, 0x00022022, 0x00022220, 0x00022222, 0x01002121, + 0x01012021, 0x01012221, 0x01022021, 0x01022121, 0x02002020, 0x02002022, 0x02002121, 0x02002220, + 0x02002222, 0x02012121, 0x02022020, 0x02022022, 0x02022220, 0x02022222, 0x00110000, 0x00110001, + 0x00110100, 0x00110201, 0x00120100, 0x00120101, 0x01100001, 0x01100100, 0x01110000, 0x01110101, + 0x01110200, 0x01120001, 0x01120100, 0x01120101, 0x01120201, 0x02110001, 0x02110100, 0x02110102, + 0x02120001, 0x02120101, 0x00100011, 0x00100110, 0x00100112, 0x00100211, 0x00110010, 0x00110012, + 0x00110111, 0x00110210, 0x00120011, 0x00120110, 0x00120211, 0x01100111, 0x01100212, 0x01110010, + 0x01110011, 0x01110012, 0x01110110, 0x01110111, 0x01110112, 0x01110211, 0x01120010, 0x01120111, + 0x02100110, 0x02110012, 0x02110111, 0x02120011, 0x02120110, 0x00110021, 0x00110120, 0x00110122, + 0x00120121, 0x01100020, 0x01100122, 0x01100221, 0x01110022, 0x01110121, 0x01110220, 0x01110222, + 0x01120120, 0x01120122, 0x02100121, 0x02110021, 0x02110120, 0x02110122, 0x02120121, 0x00101001, + 0x00101102, 0x00101201, 0x00111100, 0x00111101, 0x00111200, 0x00111201, 0x00121001, 0x00121102, + 0x01101001, 0x01101101, 0x01101102, 0x01101200, 0x01101202, 0x01111001, 0x01111100, 0x01111101, + 0x01111102, 0x01111201, 0x01121002, 0x01121101, 0x01121200, 0x02101100, 0x02101201, 0x02111000, + 0x02111100, 0x02111101, 0x02111200, 0x02111201, 0x02111202, 0x02121001, 0x02121100, 0x02121101, + 0x02121201, 0x00101012, 0x00101111, 0x00101212, 0x00111011, 0x00111110, 0x00111111, 0x00111112, + 0x00111211, 0x00121010, 0x00121012, 0x00121111, 0x00121210, 0x00121212, 0x01101011, 0x01101110, + 0x01101111, 0x01101112, 0x01111011, 0x01111012, 0x01111110, 0x01111111, 0x01111112, 0x01111211, + 0x01111212, 0x01121011, 0x01121110, 0x01121111, 0x01121112, 0x01121211, 0x02101010, 0x02101012, + 0x02101110, 0x02101111, 0x02101210, 0x02101212, 0x02111010, 0x02111011, 0x02111110, 0x02111111, + 0x02111112, 0x02111211, 0x02111212, 0x02121010, 0x02121012, 0x02121111, 0x00101021, 0x00101120, + 0x00101121, 0x00101122, 0x00111121, 0x00111122, 0x00111220, 0x00111222, 0x00121021, 0x00121122, + 0x01101020, 0x01101022, 0x01101120, 0x01101121, 0x01101220, 0x01101222, 0x01111021, 0x01111121, + 0x01111122, 0x01111220, 0x01111221, 0x01121021, 0x01121120, 0x01121121, 0x01121220, 0x01121221, + 0x01121222, 0x02101122, 0x02101222, 0x02111022, 0x02111121, 0x02121120, 0x02121221, 0x00112001, + 0x00112102, 0x00122101, 0x01102001, 0x01102100, 0x01102102, 0x01102201, 0x01112000, 0x01112101, + 0x01112200, 0x01112202, 0x01122000, 0x01122001, 0x01122100, 0x01122102, 0x01122201, 0x02102101, + 0x02112001, 0x02112100, 0x02122101, 0x00112010, 0x00112012, 0x00112111, 0x00112212, 0x00122011, + 0x00122111, 0x01102012, 0x01102110, 0x01102111, 0x01102210, 0x01112011, 0x01112110, 0x01112111, + 0x01112112, 0x01112211, 0x01112212, 0x01122010, 0x01122111, 0x01122212, 0x02102211, 0x02112011, + 0x02112012, 0x02112111, 0x02112210, 0x02122011, 0x02122112, 0x02122211, 0x00102221, 0x00112122, + 0x00122120, 0x00122122, 0x01102120, 0x01102122, 0x01102221, 0x01112020, 0x01112022, 0x01112121, + 0x01112220, 0x01122021, 0x01122122, 0x01122221, 0x02102121, 0x02112021, 0x02112122, 0x02112222, + 0x00200000, 0x00200002, 0x00200200, 0x00200202, 0x00210101, 0x00220000, 0x00220002, 0x00220101, + 0x00220200, 0x00220202, 0x01200101, 0x01210001, 0x01210201, 0x01220001, 0x01220101, 0x02200000, + 0x02200002, 0x02200200, 0x02200202, 0x02210101, 0x02220000, 0x02220002, 0x02220101, 0x02220200, + 0x02220202, 0x00200111, 0x00210011, 0x00210110, 0x00210211, 0x00220111, 0x01200012, 0x01200110, + 0x01200211, 0x01210111, 0x01210210, 0x01210212, 0x01220011, 0x01220110, 0x01220111, 0x01220112, + 0x02200111, 0x02210010, 0x02210112, 0x02210211, 0x02220111, 0x00200021, 0x00200220, 0x00200222, + 0x00210021, 0x00210121, 0x00220020, 0x00220022, 0x00220220, 0x00220222, 0x01200121, 0x01210021, + 0x01210122, 0x01210221, 0x01220121, 0x02200021, 0x02200220, 0x02200222, 0x02210021, 0x02210121, + 0x02220020, 0x02220022, 0x02220220, 0x02220222, 0x00201101, 0x00211100, 0x00211102, 0x00211201, + 0x00221101, 0x01201100, 0x01201101, 0x01201102, 0x01201201, 0x01211002, 0x01211101, 0x01211200, + 0x01211202, 0x01221102, 0x02201101, 0x02211001, 0x02211100, 0x02211201, 0x02221001, 0x02221101, + 0x00201211, 0x00211111, 0x00221011, 0x00221211, 0x01201010, 0x01201111, 0x01201210, 0x01211011, + 0x01211110, 0x01211111, 0x01211211, 0x01221012, 0x01221111, 0x01221210, 0x02201211, 0x02211010, + 0x02211110, 0x02211111, 0x02211210, 0x02211212, 0x02221011, 0x02221110, 0x02221112, 0x02221211, + 0x00201121, 0x00211020, 0x00211022, 0x00211221, 0x00221121, 0x01201021, 0x01201221, 0x01211121, + 0x01221020, 0x01221021, 0x01221221, 0x02201120, 0x02201122, 0x02211020, 0x02211222, 0x00202000, + 0x00202002, 0x00202200, 0x00202202, 0x00212101, 0x00222000, 0x00222002, 0x00222200, 0x00222202, + 0x01202101, 0x01212001, 0x01212100, 0x01222101, 0x02202000, 0x02202002, 0x02202200, 0x02202202, + 0x02222000, 0x02222002, 0x02222200, 0x02222202, 0x00202211, 0x00212011, 0x00212110, 0x00212211, + 0x00222111, 0x01202112, 0x01202211, 0x01212012, 0x01212111, 0x01222011, 0x01222110, 0x01222112, + 0x01222211, 0x02202111, 0x02212010, 0x02212112, 0x02212211, 0x02222110, 0x02222111, 0x00202020, + 0x00202022, 0x00202220, 0x00202222, 0x00222020, 0x00222022, 0x00222220, 0x00222222, 0x01202121, + 0x01212021, 0x01212122, 0x01212221, 0x01222121, 0x02202020, 0x02202022, 0x02202220, 0x02202222, + 0x02212121, 0x02222020, 0x02222022, 0x02222220, 0x02222222, 0x10000101, 0x10010001, 0x10010102, + 0x10020101, 0x11000201, 0x11010002, 0x11010101, 0x11010200, 0x11010202, 0x11020001, 0x11020100, + 0x11020102, 0x12010100, 0x12010201, 0x12020001, 0x12020102, 0x10000010, 0x10000011, 0x10000110, + 0x10000112, 0x10000211, 0x10010012, 0x10010111, 0x10010112, 0x10010210, 0x10010212, 0x10020011, + 0x10020112, 0x10020211, 0x11000111, 0x11000210, 0x11000212, 0x11010011, 0x11010110, 0x11010111, + 0x11010112, 0x11010211, 0x11010212, 0x11020111, 0x11020210, 0x11020212, 0x12000011, 0x12000110, + 0x12000112, 0x12010010, 0x12010012, 0x12010111, 0x12020010, 0x12020011, 0x12020012, 0x10000121, + 0x10010021, 0x10010120, 0x10010122, 0x10020121, 0x11000021, 0x11010022, 0x11010121, 0x11010222, + 0x11020120, 0x11020221, 0x12000221, 0x12010120, 0x12020121, 0x10001001, 0x10011101, 0x10011201, + 0x10021201, 0x11001101, 0x11001200, 0x11001202, 0x11011001, 0x11011100, 0x11011101, 0x11011102, + 0x11021001, 0x11021002, 0x11021101, 0x11021200, 0x11021202, 0x12001001, 0x12001102, 0x12001201, + 0x12011000, 0x12011002, 0x12011101, 0x12021000, 0x12021001, 0x12021201, 0x10001011, 0x10001012, + 0x10001111, 0x10001212, 0x10011011, 0x10011110, 0x10011111, 0x10011112, 0x10011211, 0x10021010, + 0x10021111, 0x10021212, 0x11001011, 0x11001110, 0x11001111, 0x11001112, 0x11001211, 0x11011010, + 0x11011011, 0x11011110, 0x11011111, 0x11011112, 0x11011210, 0x11011211, 0x11021011, 0x11021110, + 0x11021111, 0x11021112, 0x11021211, 0x12001012, 0x12001110, 0x12001111, 0x12001210, 0x12011011, + 0x12011110, 0x12011111, 0x12011112, 0x12011211, 0x12011212, 0x12021111, 0x12021210, 0x12021212, + 0x10001021, 0x10001121, 0x10001221, 0x10011120, 0x10011121, 0x10011220, 0x10011222, 0x10021021, + 0x10021120, 0x10021221, 0x11001020, 0x11001022, 0x11001121, 0x11001220, 0x11011020, 0x11011021, + 0x11011022, 0x11011121, 0x11011122, 0x11011221, 0x11021022, 0x11021121, 0x11021220, 0x12001021, + 0x12001121, 0x12001222, 0x12011120, 0x12011121, 0x12021021, 0x12021120, 0x12021122, 0x10002101, + 0x10012001, 0x10012101, 0x10012202, 0x10022101, 0x11002002, 0x11002201, 0x11012000, 0x11012101, + 0x11012200, 0x11022001, 0x11022100, 0x11022102, 0x11022201, 0x12002101, 0x12012001, 0x12012100, + 0x12012102, 0x12012201, 0x12022101, 0x10002011, 0x10002111, 0x10002112, 0x10002212, 0x10012010, + 0x10012110, 0x10012111, 0x10012210, 0x10022011, 0x10022110, 0x10022112, 0x11002010, 0x11002111, + 0x11002212, 0x11012011, 0x11012012, 0x11012110, 0x11012111, 0x11012112, 0x11012211, 0x11022010, + 0x11022012, 0x11022111, 0x11022112, 0x11022212, 0x12002112, 0x12002211, 0x12012012, 0x12012111, + 0x12012112, 0x12012210, 0x12022011, 0x12022110, 0x12022112, 0x12022211, 0x10012122, 0x11002120, + 0x11002122, 0x11002221, 0x11012121, 0x11012220, 0x11012222, 0x11022120, 0x11022221, 0x12012120, + 0x12022121, 0x10100001, 0x10100100, 0x10100101, 0x10100102, 0x10100201, 0x10110002, 0x10110101, + 0x10110202, 0x10120001, 0x10120100, 0x10120201, 0x11100000, 0x11100101, 0x11100200, 0x11110001, + 0x11110100, 0x11110101, 0x11110102, 0x11110201, 0x11120101, 0x11120200, 0x12100102, 0x12100201, + 0x12110101, 0x12110200, 0x12120000, 0x12120001, 0x12120102, 0x12120201, 0x10100111, 0x10100210, + 0x10100211, 0x10100212, 0x10110011, 0x10110110, 0x10110111, 0x10110112, 0x10110210, 0x10110211, + 0x10120010, 0x10120111, 0x10120112, 0x10120210, 0x10120212, 0x11100011, 0x11100110, 0x11100111, + 0x11100112, 0x11100211, 0x11110010, 0x11110011, 0x11110012, 0x11110110, 0x11110111, 0x11110112, + 0x11110210, 0x11110211, 0x11110212, 0x11120011, 0x11120110, 0x11120111, 0x11120112, 0x11120211, + 0x12100012, 0x12100111, 0x12110011, 0x12110110, 0x12110111, 0x12110112, 0x12110211, 0x12120010, + 0x12120111, 0x12120212, 0x10100021, 0x10100122, 0x10110022, 0x10110121, 0x10110222, 0x10120021, + 0x10120120, 0x11100022, 0x11100121, 0x11100222, 0x11110021, 0x11110120, 0x11110121, 0x11110122, + 0x11110221, 0x11120022, 0x11120121, 0x12100121, 0x12110020, 0x12110022, 0x12110121, 0x12110221, + 0x12110222, 0x12120120, 0x10101100, 0x10101101, 0x10111001, 0x10111100, 0x10111101, 0x10111102, + 0x10111200, 0x10111201, 0x10121001, 0x10121101, 0x10121200, 0x10121202, 0x11101001, 0x11101100, + 0x11101101, 0x11101102, 0x11101201, 0x11101202, 0x11111000, 0x11111001, 0x11111100, 0x11111101, + 0x11111102, 0x11111200, 0x11111201, 0x11111202, 0x11121001, 0x11121002, 0x11121100, 0x11121101, + 0x11121102, 0x11121201, 0x12101000, 0x12101200, 0x12101202, 0x12111001, 0x12111100, 0x12111101, + 0x12111102, 0x12111201, 0x12121001, 0x12121100, 0x12121101, 0x12121202, 0x10101011, 0x10101012, + 0x10101110, 0x10101111, 0x10101112, 0x10101211, 0x10111010, 0x10111011, 0x10111012, 0x10111110, + 0x10111111, 0x10111112, 0x10111211, 0x10111212, 0x10121011, 0x10121110, 0x10121111, 0x10121112, + 0x10121211, 0x11101010, 0x11101011, 0x11101012, 0x11101110, 0x11101111, 0x11101112, 0x11101210, + 0x11101211, 0x11111010, 0x11111011, 0x11111012, 0x11111110, 0x11111111, 0x11111112, 0x11111210, + 0x11111211, 0x11111212, 0x11121010, 0x11121011, 0x11121110, 0x11121111, 0x11121112, 0x11121210, + 0x11121211, 0x11121212, 0x12101011, 0x12101110, 0x12101111, 0x12101211, 0x12101212, 0x12111010, + 0x12111011, 0x12111110, 0x12111111, 0x12111112, 0x12111210, 0x12111211, 0x12121011, 0x12121110, + 0x12121111, 0x12121112, 0x12121211, 0x10101020, 0x10101021, 0x10101022, 0x10101120, 0x10101122, + 0x10101220, 0x10101221, 0x10111021, 0x10111120, 0x10111121, 0x10111220, 0x10111221, 0x10121020, + 0x10121021, 0x10121022, 0x10121120, 0x10121121, 0x10121122, 0x10121220, 0x10121221, 0x11101021, + 0x11101121, 0x11101122, 0x11101220, 0x11101221, 0x11101222, 0x11111020, 0x11111021, 0x11111022, + 0x11111120, 0x11111121, 0x11111122, 0x11111220, 0x11111221, 0x11111222, 0x11121021, 0x11121120, + 0x11121121, 0x11121221, 0x12101022, 0x12101121, 0x12101122, 0x12101220, 0x12101221, 0x12101222, + 0x12111021, 0x12111121, 0x12111222, 0x12121022, 0x12121121, 0x12121122, 0x12121220, 0x12121221, + 0x10102100, 0x10102101, 0x10102102, 0x10102201, 0x10112000, 0x10112101, 0x10112200, 0x10122001, + 0x10122202, 0x11102101, 0x11102200, 0x11102202, 0x11112001, 0x11112100, 0x11112101, 0x11112102, + 0x11112200, 0x11112201, 0x11122000, 0x11122002, 0x11122100, 0x11122101, 0x12102002, 0x12102201, + 0x12112000, 0x12112002, 0x12112101, 0x12112200, 0x12122001, 0x12122201, 0x10102011, 0x10102012, + 0x10102111, 0x10102212, 0x10112011, 0x10112110, 0x10112111, 0x10112112, 0x10112211, 0x10122111, + 0x11102011, 0x11102110, 0x11102111, 0x11102112, 0x11102211, 0x11112010, 0x11112011, 0x11112012, + 0x11112110, 0x11112111, 0x11112112, 0x11112210, 0x11112211, 0x11112212, 0x11122011, 0x11122110, + 0x11122111, 0x11122112, 0x11122211, 0x12102011, 0x12102111, 0x12102211, 0x12112011, 0x12112110, + 0x12112111, 0x12112112, 0x12112210, 0x12112211, 0x12122111, 0x10102120, 0x10102220, 0x10112121, + 0x10112222, 0x10122020, 0x10122121, 0x10122122, 0x10122221, 0x11102121, 0x11102220, 0x11102221, + 0x11112021, 0x11112121, 0x11112122, 0x11112220, 0x11112221, 0x11122022, 0x11122121, 0x11122220, + 0x11122222, 0x12102021, 0x12102222, 0x12112022, 0x12112121, 0x12112122, 0x12112220, 0x12112222, + 0x12122021, 0x10200101, 0x10210100, 0x10210102, 0x10210201, 0x10220101, 0x11200100, 0x11210000, + 0x11210101, 0x11210102, 0x11210200, 0x11210202, 0x11220001, 0x11220100, 0x11220102, 0x11220201, + 0x12200001, 0x12210102, 0x12220101, 0x10200011, 0x10200110, 0x10200112, 0x10200211, 0x10210012, + 0x10210111, 0x10220011, 0x10220012, 0x10220112, 0x10220211, 0x11200111, 0x11200211, 0x11210011, + 0x11210111, 0x11210112, 0x11210211, 0x11220111, 0x11220112, 0x11220212, 0x12200110, 0x12200212, + 0x12210012, 0x12210111, 0x12220011, 0x12220112, 0x12220211, 0x10210021, 0x10210122, 0x10210221, + 0x11200020, 0x11200021, 0x11200122, 0x11210121, 0x11210122, 0x11210220, 0x11220020, 0x12200121, + 0x12210021, 0x12210122, 0x12220121, 0x10211001, 0x10211002, 0x10211101, 0x10211102, 0x10211202, + 0x10221001, 0x10221102, 0x10221201, 0x11201000, 0x11201002, 0x11201101, 0x11201200, 0x11201202, + 0x11211001, 0x11211100, 0x11211101, 0x11211102, 0x11211201, 0x11211202, 0x11221000, 0x11221002, + 0x11221101, 0x12201100, 0x12201101, 0x12201201, 0x12211000, 0x12211002, 0x12211100, 0x12211101, + 0x12211102, 0x12211200, 0x12211202, 0x12221001, 0x12221100, 0x12221201, 0x10201111, 0x10201210, + 0x10201212, 0x10211011, 0x10211111, 0x10211112, 0x10211211, 0x11201110, 0x11201111, 0x11201112, + 0x11201211, 0x11211010, 0x11211011, 0x11211110, 0x11211111, 0x11211112, 0x11211211, 0x11221011, + 0x11221110, 0x11221111, 0x11221112, 0x11221211, 0x12201112, 0x12201211, 0x12201212, 0x12211011, + 0x12211111, 0x12211112, 0x12211211, 0x12211212, 0x12221012, 0x12221111, 0x12221112, 0x12221210, + 0x10201022, 0x10201221, 0x10211121, 0x10221020, 0x10221122, 0x10221220, 0x10221221, 0x11201020, + 0x11201121, 0x11201220, 0x11201222, 0x11211021, 0x11211120, 0x11211121, 0x11211122, 0x11211220, + 0x11211222, 0x11221020, 0x11221121, 0x11221220, 0x12201020, 0x12201022, 0x12201121, 0x12201222, + 0x12211120, 0x12211122, 0x12211220, 0x12211221, 0x12221020, 0x12221120, 0x12221122, 0x12221222, + 0x10212102, 0x10212201, 0x10222101, 0x11202001, 0x11212002, 0x11212101, 0x11212202, 0x11222001, + 0x11222201, 0x12202101, 0x12212001, 0x12212200, 0x12222102, 0x10202011, 0x10202110, 0x10212010, + 0x10212111, 0x10222011, 0x10222110, 0x10222112, 0x10222211, 0x11202010, 0x11202011, 0x11202111, + 0x11202112, 0x11202210, 0x11212011, 0x11212110, 0x11212111, 0x11212112, 0x11212211, 0x11222010, + 0x11222111, 0x11222212, 0x12202012, 0x12202110, 0x12202212, 0x12212111, 0x12222011, 0x12222110, + 0x12222111, 0x12222211, 0x10212021, 0x10212122, 0x10212220, 0x11202021, 0x11202120, 0x11202221, + 0x11212020, 0x11212121, 0x11212220, 0x11212222, 0x11222120, 0x11222121, 0x11222221, 0x12202122, + 0x12212120, 0x12212220, 0x12212222, 0x12222122, 0x20000000, 0x20000002, 0x20000200, 0x20000202, + 0x20020000, 0x20020002, 0x20020200, 0x20020202, 0x21000101, 0x21010000, 0x21010001, 0x21010100, + 0x21010102, 0x21010201, 0x21020101, 0x22000000, 0x22000002, 0x22000200, 0x22000202, 0x22010101, + 0x22020000, 0x22020002, 0x22020200, 0x22020202, 0x20000111, 0x20010011, 0x20010110, 0x20010112, + 0x20010211, 0x20020111, 0x21000011, 0x21000110, 0x21000211, 0x21010010, 0x21010012, 0x21010111, + 0x21010112, 0x21010210, 0x21010211, 0x21020110, 0x21020112, 0x21020211, 0x22000111, 0x22000211, + 0x22010110, 0x22010112, 0x22010211, 0x22020111, 0x20000020, 0x20000022, 0x20000220, 0x20000222, + 0x20010121, 0x20020020, 0x20020022, 0x20020220, 0x20020222, 0x21010021, 0x21010120, 0x21010221, + 0x21020121, 0x22000020, 0x22000022, 0x22000220, 0x22000222, 0x22010121, 0x22020020, 0x22020022, + 0x22020220, 0x22020222, 0x20011100, 0x20011201, 0x21001001, 0x21001100, 0x21011001, 0x21011101, + 0x21011202, 0x21021001, 0x21021100, 0x21021201, 0x22011100, 0x22011201, 0x20001011, 0x20001211, + 0x20011012, 0x20011111, 0x20011212, 0x20021112, 0x20021211, 0x21001010, 0x21001011, 0x21001111, + 0x21001210, 0x21011011, 0x21011110, 0x21011111, 0x21011112, 0x21011211, 0x21011212, 0x21021111, + 0x21021112, 0x21021210, 0x21021212, 0x22001011, 0x22001110, 0x22001112, 0x22001211, 0x22011010, + 0x22011012, 0x22011111, 0x22011210, 0x22021112, 0x20011021, 0x20011122, 0x20011221, 0x20021121, + 0x21001021, 0x21001120, 0x21001221, 0x21001222, 0x21011020, 0x21011121, 0x21011221, 0x21011222, + 0x21021021, 0x21021122, 0x21021222, 0x22001121, 0x22011021, 0x22011222, 0x22021120, 0x20002000, + 0x20002002, 0x20002200, 0x20002202, 0x20012101, 0x20022000, 0x20022002, 0x20022200, 0x20022202, + 0x21002001, 0x21002101, 0x21012001, 0x21012100, 0x21012201, 0x21022101, 0x21022201, 0x22002000, + 0x22002002, 0x22002200, 0x22002202, 0x22012101, 0x22022000, 0x22022002, 0x22022200, 0x22022202, + 0x20002111, 0x20002112, 0x20012011, 0x20012110, 0x20012112, 0x20022111, 0x21002011, 0x21002110, + 0x21002112, 0x21002211, 0x21012010, 0x21012012, 0x21012111, 0x21012212, 0x21022011, 0x21022110, + 0x22002111, 0x22012112, 0x22012211, 0x22022111, 0x20002020, 0x20002022, 0x20002220, 0x20002222, + 0x20012121, 0x20022020, 0x20022022, 0x20022220, 0x20022222, 0x21002121, 0x21012021, 0x21012120, + 0x21012122, 0x22002020, 0x22002022, 0x22002220, 0x22002222, 0x22012121, 0x22022020, 0x22022022, + 0x22022220, 0x22022222, 0x20100101, 0x20110001, 0x20110102, 0x20110200, 0x20110201, 0x20120101, + 0x21100001, 0x21100102, 0x21100201, 0x21110101, 0x21110200, 0x21110202, 0x21120201, 0x21120202, + 0x22100101, 0x22110001, 0x22110100, 0x22110102, 0x22110201, 0x22120101, 0x20100011, 0x20100110, + 0x20100112, 0x20100211, 0x20110010, 0x20110111, 0x20110210, 0x20110212, 0x20120011, 0x20120110, + 0x20120112, 0x20120211, 0x21100010, 0x21100111, 0x21110010, 0x21110011, 0x21110110, 0x21110111, + 0x21110112, 0x21110211, 0x21120012, 0x21120111, 0x22100110, 0x22100112, 0x22110012, 0x22110111, + 0x22110210, 0x22120011, 0x22120110, 0x22120112, 0x22120211, 0x20100121, 0x20110021, 0x20110120, + 0x20110221, 0x20120121, 0x21100120, 0x21100122, 0x21100221, 0x21110020, 0x21110022, 0x21110121, + 0x21110220, 0x21120122, 0x21120221, 0x22100121, 0x22110120, 0x22110122, 0x22120221, 0x20101001, + 0x20101100, 0x20101102, 0x20111000, 0x20111101, 0x20111200, 0x20121102, 0x21101000, 0x21101202, + 0x21111001, 0x21111100, 0x21111101, 0x21111102, 0x21111200, 0x21111201, 0x21121000, 0x21121001, + 0x21121002, 0x21121101, 0x22101100, 0x22101102, 0x22111002, 0x22111100, 0x22111101, 0x22111200, + 0x22121001, 0x22121201, 0x20101010, 0x20101111, 0x20101210, 0x20101212, 0x20111010, 0x20111011, + 0x20111110, 0x20111111, 0x20111112, 0x20111211, 0x20121011, 0x20121111, 0x20121211, 0x20121212, + 0x21101011, 0x21101110, 0x21101111, 0x21101112, 0x21101211, 0x21111010, 0x21111011, 0x21111012, + 0x21111110, 0x21111111, 0x21111112, 0x21111210, 0x21111211, 0x21111212, 0x21121011, 0x21121110, + 0x21121111, 0x21121112, 0x21121211, 0x22101011, 0x22101111, 0x22101210, 0x22111011, 0x22111012, + 0x22111110, 0x22111111, 0x22111112, 0x22111211, 0x22111212, 0x22121010, 0x22121012, 0x22121111, + 0x22121210, 0x22121212, 0x20101021, 0x20101120, 0x20111020, 0x20111121, 0x20111221, 0x20121020, + 0x20121122, 0x20121221, 0x21101121, 0x21101220, 0x21101221, 0x21111021, 0x21111022, 0x21111121, + 0x21111122, 0x21111221, 0x21121121, 0x21121220, 0x22101022, 0x22101120, 0x22101221, 0x22101222, + 0x22111022, 0x22111120, 0x22111121, 0x22121120, 0x22121122, 0x22121221, 0x20102101, 0x20112102, + 0x20112201, 0x20122101, 0x21102001, 0x21102102, 0x21112000, 0x21112002, 0x21112101, 0x21112102, + 0x21112202, 0x21122100, 0x21122101, 0x22102101, 0x22112001, 0x22112102, 0x22112201, 0x22122101, + 0x20102110, 0x20102112, 0x20102211, 0x20112010, 0x20112012, 0x20112111, 0x20112210, 0x20112212, + 0x20122010, 0x20122011, 0x20122110, 0x20122112, 0x21102010, 0x21102012, 0x21102111, 0x21102210, + 0x21102212, 0x21112011, 0x21112110, 0x21112111, 0x21112112, 0x21112211, 0x21122012, 0x21122111, + 0x21122112, 0x21122212, 0x22102011, 0x22102110, 0x22112010, 0x22112012, 0x22112111, 0x22112212, + 0x22122011, 0x22122112, 0x20102121, 0x20112121, 0x20122121, 0x21102120, 0x21102122, 0x21102221, + 0x21112020, 0x21112121, 0x21112220, 0x21122021, 0x22102121, 0x22112021, 0x22112120, 0x22112121, + 0x22112122, 0x20200000, 0x20200002, 0x20200200, 0x20200202, 0x20210101, 0x20220000, 0x20220002, + 0x20220200, 0x20220202, 0x21200101, 0x21210001, 0x21210100, 0x21210102, 0x21210201, 0x22200000, + 0x22200002, 0x22200200, 0x22200202, 0x22210101, 0x22220000, 0x22220002, 0x22220200, 0x22220202, + 0x20200111, 0x20200211, 0x20210011, 0x20210110, 0x20210112, 0x20210211, 0x20210212, 0x21200112, + 0x21200211, 0x21210011, 0x21210111, 0x21210210, 0x21210212, 0x21220011, 0x21220110, 0x22200111, + 0x22210010, 0x22210012, 0x22210112, 0x22210211, 0x20200022, 0x20200220, 0x20200222, 0x20210020, + 0x20210221, 0x20220022, 0x20220220, 0x20220222, 0x21200121, 0x21210021, 0x21210122, 0x21210221, + 0x21220121, 0x22200020, 0x22200022, 0x22200220, 0x22200222, 0x22210121, 0x22220020, 0x22220022, + 0x22220220, 0x22220222, 0x20211201, 0x20221101, 0x21201001, 0x21201100, 0x21211000, 0x21211100, + 0x21211101, 0x21211200, 0x21211202, 0x21221001, 0x21221101, 0x21221102, 0x21221200, 0x21221201, + 0x22201101, 0x20201112, 0x20201211, 0x20211010, 0x20211012, 0x20211111, 0x20211210, 0x20221112, + 0x20221211, 0x21201012, 0x21201111, 0x21211011, 0x21211110, 0x21211111, 0x21211112, 0x21211211, + 0x21221111, 0x21221212, 0x22201011, 0x22201110, 0x22201111, 0x22201112, 0x22201211, 0x22211012, + 0x22211111, 0x22211210, 0x20201121, 0x20211021, 0x20211122, 0x20211222, 0x20221021, 0x20221121, + 0x21201120, 0x21201122, 0x21201222, 0x21211022, 0x21211121, 0x21211122, 0x21211220, 0x21221020, + 0x21221022, 0x22201122, 0x22211020, 0x22211121, 0x22211122, 0x22211221, 0x22221021, 0x22221120, + 0x22221122, 0x20202000, 0x20202002, 0x20202200, 0x20202202, 0x20222000, 0x20222002, 0x20222200, + 0x20222202, 0x21212001, 0x21212100, 0x21212102, 0x21212201, 0x22202000, 0x22202002, 0x22202200, + 0x22202202, 0x22212101, 0x22222000, 0x22222002, 0x22222200, 0x22222202, 0x20202111, 0x20212110, + 0x20212211, 0x20222011, 0x20222111, 0x21202011, 0x21212010, 0x21212111, 0x21212212, 0x21222011, + 0x21222112, 0x21222211, 0x22212010, 0x22212112, 0x20202020, 0x20202022, 0x20202220, 0x20202222, + 0x20222020, 0x20222022, 0x20222220, 0x20222222, 0x21212021, 0x21212120, 0x21212122, 0x22202020, + 0x22202022, 0x22202220, 0x22202222, 0x22212121, 0x22222020, 0x22222022, 0x22222220, 0x22222222 +}; diff --git a/ggml/src/ggml-opencl/kernels/iq2_s_grid.cl b/ggml/src/ggml-opencl/kernels/iq2_s_grid.cl new file mode 100644 index 000000000000..e0666574669f --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq2_s_grid.cl @@ -0,0 +1,259 @@ +// IQ2_S codebook, stored as pairs of four packed magnitudes. +constant uint iq2_s_grid[2048] = { + 0x08080808, 0x08080808, 0x0808082b, 0x08080808, 0x08081919, 0x08080808, 0x08082b08, 0x08080808, + 0x08082b2b, 0x08080808, 0x08190819, 0x08080808, 0x08191908, 0x08080808, 0x0819192b, 0x08080808, + 0x08192b19, 0x08080808, 0x082b0808, 0x08080808, 0x082b082b, 0x08080808, 0x082b1919, 0x08080808, + 0x082b2b08, 0x08080808, 0x19080819, 0x08080808, 0x19081908, 0x08080808, 0x1908192b, 0x08080808, + 0x19082b19, 0x08080808, 0x19190808, 0x08080808, 0x1919082b, 0x08080808, 0x19191919, 0x08080808, + 0x19192b08, 0x08080808, 0x192b0819, 0x08080808, 0x192b1908, 0x08080808, 0x192b192b, 0x08080808, + 0x192b2b19, 0x08080808, 0x2b080808, 0x08080808, 0x2b08082b, 0x08080808, 0x2b081919, 0x08080808, + 0x2b082b08, 0x08080808, 0x2b190819, 0x08080808, 0x2b191908, 0x08080808, 0x2b2b0808, 0x08080808, + 0x2b2b1919, 0x08080808, 0x2b2b2b2b, 0x08080808, 0x08080819, 0x08080819, 0x08081908, 0x08080819, + 0x0808192b, 0x08080819, 0x08082b19, 0x08080819, 0x08190808, 0x08080819, 0x0819082b, 0x08080819, + 0x08191919, 0x08080819, 0x08192b08, 0x08080819, 0x082b0819, 0x08080819, 0x082b1908, 0x08080819, + 0x19080808, 0x08080819, 0x1908082b, 0x08080819, 0x19081919, 0x08080819, 0x19082b08, 0x08080819, + 0x19190819, 0x08080819, 0x19191908, 0x08080819, 0x1919192b, 0x08080819, 0x19192b19, 0x08080819, + 0x192b0808, 0x08080819, 0x192b1919, 0x08080819, 0x192b2b08, 0x08080819, 0x2b080819, 0x08080819, + 0x2b081908, 0x08080819, 0x2b190808, 0x08080819, 0x2b19082b, 0x08080819, 0x2b191919, 0x08080819, + 0x2b2b0819, 0x08080819, 0x2b2b1908, 0x08080819, 0x08080808, 0x0808082b, 0x0808082b, 0x0808082b, + 0x08081919, 0x0808082b, 0x08082b08, 0x0808082b, 0x08190819, 0x0808082b, 0x08191908, 0x0808082b, + 0x082b0808, 0x0808082b, 0x082b2b2b, 0x0808082b, 0x19080819, 0x0808082b, 0x19081908, 0x0808082b, + 0x1908192b, 0x0808082b, 0x19082b19, 0x0808082b, 0x19190808, 0x0808082b, 0x19191919, 0x0808082b, + 0x2b080808, 0x0808082b, 0x2b081919, 0x0808082b, 0x2b082b2b, 0x0808082b, 0x2b191908, 0x0808082b, + 0x2b2b082b, 0x0808082b, 0x08080819, 0x08081908, 0x08081908, 0x08081908, 0x0808192b, 0x08081908, + 0x08082b19, 0x08081908, 0x08190808, 0x08081908, 0x0819082b, 0x08081908, 0x08191919, 0x08081908, + 0x08192b08, 0x08081908, 0x082b0819, 0x08081908, 0x082b1908, 0x08081908, 0x082b192b, 0x08081908, + 0x082b2b19, 0x08081908, 0x19080808, 0x08081908, 0x1908082b, 0x08081908, 0x19081919, 0x08081908, + 0x19082b08, 0x08081908, 0x19082b2b, 0x08081908, 0x19190819, 0x08081908, 0x19191908, 0x08081908, + 0x1919192b, 0x08081908, 0x19192b19, 0x08081908, 0x192b0808, 0x08081908, 0x192b082b, 0x08081908, + 0x192b1919, 0x08081908, 0x2b080819, 0x08081908, 0x2b081908, 0x08081908, 0x2b08192b, 0x08081908, + 0x2b082b19, 0x08081908, 0x2b190808, 0x08081908, 0x2b191919, 0x08081908, 0x2b192b08, 0x08081908, + 0x2b2b0819, 0x08081908, 0x2b2b1908, 0x08081908, 0x08080808, 0x08081919, 0x0808082b, 0x08081919, + 0x08081919, 0x08081919, 0x08082b08, 0x08081919, 0x08082b2b, 0x08081919, 0x08190819, 0x08081919, + 0x08191908, 0x08081919, 0x0819192b, 0x08081919, 0x08192b19, 0x08081919, 0x082b0808, 0x08081919, + 0x082b1919, 0x08081919, 0x082b2b08, 0x08081919, 0x19080819, 0x08081919, 0x19081908, 0x08081919, + 0x1908192b, 0x08081919, 0x19082b19, 0x08081919, 0x19190808, 0x08081919, 0x1919082b, 0x08081919, + 0x19191919, 0x08081919, 0x19192b08, 0x08081919, 0x192b0819, 0x08081919, 0x192b1908, 0x08081919, + 0x2b080808, 0x08081919, 0x2b08082b, 0x08081919, 0x2b081919, 0x08081919, 0x2b082b08, 0x08081919, + 0x2b190819, 0x08081919, 0x2b191908, 0x08081919, 0x2b2b0808, 0x08081919, 0x08080819, 0x0808192b, + 0x08081908, 0x0808192b, 0x0808192b, 0x0808192b, 0x08082b19, 0x0808192b, 0x08190808, 0x0808192b, + 0x08191919, 0x0808192b, 0x19080808, 0x0808192b, 0x19081919, 0x0808192b, 0x19082b08, 0x0808192b, + 0x19190819, 0x0808192b, 0x19191908, 0x0808192b, 0x192b0808, 0x0808192b, 0x2b080819, 0x0808192b, + 0x2b081908, 0x0808192b, 0x2b190808, 0x0808192b, 0x08080808, 0x08082b08, 0x0808082b, 0x08082b08, + 0x08081919, 0x08082b08, 0x08082b08, 0x08082b08, 0x08190819, 0x08082b08, 0x08191908, 0x08082b08, + 0x0819192b, 0x08082b08, 0x08192b19, 0x08082b08, 0x082b0808, 0x08082b08, 0x082b1919, 0x08082b08, + 0x082b2b2b, 0x08082b08, 0x19080819, 0x08082b08, 0x19081908, 0x08082b08, 0x1908192b, 0x08082b08, + 0x19082b19, 0x08082b08, 0x19190808, 0x08082b08, 0x1919082b, 0x08082b08, 0x19191919, 0x08082b08, + 0x19192b08, 0x08082b08, 0x192b0819, 0x08082b08, 0x192b1908, 0x08082b08, 0x2b080808, 0x08082b08, + 0x2b081919, 0x08082b08, 0x2b191908, 0x08082b08, 0x2b2b2b2b, 0x08082b08, 0x08080819, 0x08082b19, + 0x08081908, 0x08082b19, 0x08190808, 0x08082b19, 0x0819082b, 0x08082b19, 0x08191919, 0x08082b19, + 0x08192b08, 0x08082b19, 0x082b0819, 0x08082b19, 0x19080808, 0x08082b19, 0x19081919, 0x08082b19, + 0x19082b08, 0x08082b19, 0x19190819, 0x08082b19, 0x19191908, 0x08082b19, 0x192b0808, 0x08082b19, + 0x2b080819, 0x08082b19, 0x2b190808, 0x08082b19, 0x08080808, 0x08082b2b, 0x08190819, 0x08082b2b, + 0x08191908, 0x08082b2b, 0x082b082b, 0x08082b2b, 0x082b2b08, 0x08082b2b, 0x082b2b2b, 0x08082b2b, + 0x19190808, 0x08082b2b, 0x2b192b19, 0x08082b2b, 0x08080819, 0x08190808, 0x08081908, 0x08190808, + 0x0808192b, 0x08190808, 0x08082b19, 0x08190808, 0x08190808, 0x08190808, 0x0819082b, 0x08190808, + 0x08191919, 0x08190808, 0x08192b08, 0x08190808, 0x082b0819, 0x08190808, 0x082b1908, 0x08190808, + 0x082b192b, 0x08190808, 0x19080808, 0x08190808, 0x1908082b, 0x08190808, 0x19081919, 0x08190808, + 0x19082b08, 0x08190808, 0x19190819, 0x08190808, 0x19191908, 0x08190808, 0x1919192b, 0x08190808, + 0x19192b19, 0x08190808, 0x192b0808, 0x08190808, 0x192b082b, 0x08190808, 0x192b1919, 0x08190808, + 0x192b2b08, 0x08190808, 0x2b080819, 0x08190808, 0x2b081908, 0x08190808, 0x2b08192b, 0x08190808, + 0x2b190808, 0x08190808, 0x2b191919, 0x08190808, 0x2b192b08, 0x08190808, 0x2b2b0819, 0x08190808, + 0x2b2b1908, 0x08190808, 0x08080808, 0x08190819, 0x0808082b, 0x08190819, 0x08081919, 0x08190819, + 0x08082b08, 0x08190819, 0x08082b2b, 0x08190819, 0x08190819, 0x08190819, 0x08191908, 0x08190819, + 0x0819192b, 0x08190819, 0x08192b19, 0x08190819, 0x082b0808, 0x08190819, 0x082b082b, 0x08190819, + 0x082b1919, 0x08190819, 0x082b2b08, 0x08190819, 0x19080819, 0x08190819, 0x19081908, 0x08190819, + 0x1908192b, 0x08190819, 0x19082b19, 0x08190819, 0x19190808, 0x08190819, 0x1919082b, 0x08190819, + 0x19191919, 0x08190819, 0x19192b08, 0x08190819, 0x192b0819, 0x08190819, 0x192b1908, 0x08190819, + 0x2b080808, 0x08190819, 0x2b08082b, 0x08190819, 0x2b081919, 0x08190819, 0x2b082b08, 0x08190819, + 0x2b190819, 0x08190819, 0x2b191908, 0x08190819, 0x08080819, 0x0819082b, 0x08081908, 0x0819082b, + 0x08082b19, 0x0819082b, 0x08190808, 0x0819082b, 0x08191919, 0x0819082b, 0x082b0819, 0x0819082b, + 0x082b1908, 0x0819082b, 0x19080808, 0x0819082b, 0x19081919, 0x0819082b, 0x19190819, 0x0819082b, + 0x19191908, 0x0819082b, 0x2b080819, 0x0819082b, 0x2b081908, 0x0819082b, 0x2b190808, 0x0819082b, + 0x08080808, 0x08191908, 0x0808082b, 0x08191908, 0x08081919, 0x08191908, 0x08082b08, 0x08191908, + 0x08190819, 0x08191908, 0x08191908, 0x08191908, 0x0819192b, 0x08191908, 0x08192b19, 0x08191908, + 0x082b0808, 0x08191908, 0x082b1919, 0x08191908, 0x082b2b08, 0x08191908, 0x19080819, 0x08191908, + 0x19081908, 0x08191908, 0x1908192b, 0x08191908, 0x19082b19, 0x08191908, 0x19190808, 0x08191908, + 0x1919082b, 0x08191908, 0x19191919, 0x08191908, 0x19192b08, 0x08191908, 0x192b0819, 0x08191908, + 0x192b1908, 0x08191908, 0x2b080808, 0x08191908, 0x2b08082b, 0x08191908, 0x2b081919, 0x08191908, + 0x2b082b08, 0x08191908, 0x2b190819, 0x08191908, 0x2b191908, 0x08191908, 0x2b2b0808, 0x08191908, + 0x08080819, 0x08191919, 0x08081908, 0x08191919, 0x0808192b, 0x08191919, 0x08082b19, 0x08191919, + 0x08190808, 0x08191919, 0x0819082b, 0x08191919, 0x08191919, 0x08191919, 0x08192b08, 0x08191919, + 0x082b0819, 0x08191919, 0x082b1908, 0x08191919, 0x19080808, 0x08191919, 0x1908082b, 0x08191919, + 0x19081919, 0x08191919, 0x19082b08, 0x08191919, 0x19190819, 0x08191919, 0x19191908, 0x08191919, + 0x192b0808, 0x08191919, 0x2b080819, 0x08191919, 0x2b081908, 0x08191919, 0x2b190808, 0x08191919, + 0x08080808, 0x0819192b, 0x08081919, 0x0819192b, 0x08082b08, 0x0819192b, 0x08190819, 0x0819192b, + 0x08191908, 0x0819192b, 0x082b0808, 0x0819192b, 0x19080819, 0x0819192b, 0x19081908, 0x0819192b, + 0x19190808, 0x0819192b, 0x2b080808, 0x0819192b, 0x2b2b2b2b, 0x0819192b, 0x08080819, 0x08192b08, + 0x08081908, 0x08192b08, 0x0808192b, 0x08192b08, 0x08082b19, 0x08192b08, 0x08190808, 0x08192b08, + 0x08191919, 0x08192b08, 0x08192b08, 0x08192b08, 0x082b0819, 0x08192b08, 0x19080808, 0x08192b08, + 0x1908082b, 0x08192b08, 0x19081919, 0x08192b08, 0x19082b08, 0x08192b08, 0x19190819, 0x08192b08, + 0x19191908, 0x08192b08, 0x192b0808, 0x08192b08, 0x2b080819, 0x08192b08, 0x2b081908, 0x08192b08, + 0x08080808, 0x08192b19, 0x0808082b, 0x08192b19, 0x08081919, 0x08192b19, 0x08082b08, 0x08192b19, + 0x08190819, 0x08192b19, 0x08191908, 0x08192b19, 0x082b0808, 0x08192b19, 0x19080819, 0x08192b19, + 0x19081908, 0x08192b19, 0x19190808, 0x08192b19, 0x192b2b19, 0x08192b19, 0x2b2b082b, 0x08192b19, + 0x08081908, 0x08192b2b, 0x08190808, 0x08192b2b, 0x19080808, 0x08192b2b, 0x1919192b, 0x08192b2b, + 0x08080808, 0x082b0808, 0x0808082b, 0x082b0808, 0x08081919, 0x082b0808, 0x08082b08, 0x082b0808, + 0x08190819, 0x082b0808, 0x08191908, 0x082b0808, 0x0819192b, 0x082b0808, 0x08192b19, 0x082b0808, + 0x082b0808, 0x082b0808, 0x082b1919, 0x082b0808, 0x082b2b2b, 0x082b0808, 0x19080819, 0x082b0808, + 0x19081908, 0x082b0808, 0x19190808, 0x082b0808, 0x1919082b, 0x082b0808, 0x19191919, 0x082b0808, + 0x192b1908, 0x082b0808, 0x2b080808, 0x082b0808, 0x2b082b2b, 0x082b0808, 0x2b191908, 0x082b0808, + 0x2b2b2b2b, 0x082b0808, 0x08080819, 0x082b0819, 0x08081908, 0x082b0819, 0x08190808, 0x082b0819, + 0x0819082b, 0x082b0819, 0x08191919, 0x082b0819, 0x082b0819, 0x082b0819, 0x19080808, 0x082b0819, + 0x1908082b, 0x082b0819, 0x19081919, 0x082b0819, 0x19190819, 0x082b0819, 0x19191908, 0x082b0819, + 0x192b0808, 0x082b0819, 0x2b080819, 0x082b0819, 0x2b081908, 0x082b0819, 0x2b190808, 0x082b0819, + 0x08080808, 0x082b082b, 0x08082b2b, 0x082b082b, 0x082b082b, 0x082b082b, 0x082b2b08, 0x082b082b, + 0x082b2b2b, 0x082b082b, 0x19081908, 0x082b082b, 0x19190808, 0x082b082b, 0x2b082b08, 0x082b082b, + 0x2b082b2b, 0x082b082b, 0x2b2b2b08, 0x082b082b, 0x08080819, 0x082b1908, 0x08081908, 0x082b1908, + 0x0808192b, 0x082b1908, 0x08082b19, 0x082b1908, 0x08190808, 0x082b1908, 0x08191919, 0x082b1908, + 0x08192b08, 0x082b1908, 0x082b0819, 0x082b1908, 0x082b1908, 0x082b1908, 0x19080808, 0x082b1908, + 0x1908082b, 0x082b1908, 0x19081919, 0x082b1908, 0x19082b08, 0x082b1908, 0x19190819, 0x082b1908, + 0x19191908, 0x082b1908, 0x192b0808, 0x082b1908, 0x2b080819, 0x082b1908, 0x2b081908, 0x082b1908, + 0x2b190808, 0x082b1908, 0x08080808, 0x082b1919, 0x08081919, 0x082b1919, 0x08082b08, 0x082b1919, + 0x08190819, 0x082b1919, 0x08191908, 0x082b1919, 0x082b0808, 0x082b1919, 0x19080819, 0x082b1919, + 0x19081908, 0x082b1919, 0x19190808, 0x082b1919, 0x192b192b, 0x082b1919, 0x2b080808, 0x082b1919, + 0x08080819, 0x082b192b, 0x08081908, 0x082b192b, 0x08190808, 0x082b192b, 0x19080808, 0x082b192b, + 0x19192b19, 0x082b192b, 0x08080808, 0x082b2b08, 0x08081919, 0x082b2b08, 0x08190819, 0x082b2b08, + 0x08191908, 0x082b2b08, 0x19080819, 0x082b2b08, 0x19081908, 0x082b2b08, 0x19190808, 0x082b2b08, + 0x2b082b2b, 0x082b2b08, 0x2b2b2b2b, 0x082b2b08, 0x08080819, 0x082b2b19, 0x08081908, 0x082b2b19, + 0x08190808, 0x082b2b19, 0x2b191919, 0x082b2b19, 0x08082b2b, 0x082b2b2b, 0x082b082b, 0x082b2b2b, + 0x192b1908, 0x082b2b2b, 0x2b082b08, 0x082b2b2b, 0x2b082b2b, 0x082b2b2b, 0x08080819, 0x19080808, + 0x08081908, 0x19080808, 0x0808192b, 0x19080808, 0x08082b19, 0x19080808, 0x08190808, 0x19080808, + 0x0819082b, 0x19080808, 0x08191919, 0x19080808, 0x08192b08, 0x19080808, 0x08192b2b, 0x19080808, + 0x082b0819, 0x19080808, 0x082b1908, 0x19080808, 0x082b192b, 0x19080808, 0x19080808, 0x19080808, + 0x1908082b, 0x19080808, 0x19081919, 0x19080808, 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0x082b0808, 0x2b081919, + 0x19080819, 0x2b081919, 0x19081908, 0x2b081919, 0x19190808, 0x2b081919, 0x2b080808, 0x2b081919, + 0x2b082b2b, 0x2b081919, 0x08080819, 0x2b08192b, 0x08081908, 0x2b08192b, 0x08190808, 0x2b08192b, + 0x082b2b19, 0x2b08192b, 0x19080808, 0x2b08192b, 0x08080808, 0x2b082b08, 0x08081919, 0x2b082b08, + 0x08190819, 0x2b082b08, 0x08191908, 0x2b082b08, 0x19080819, 0x2b082b08, 0x19081908, 0x2b082b08, + 0x19190808, 0x2b082b08, 0x2b2b082b, 0x2b082b08, 0x08080819, 0x2b082b19, 0x08081908, 0x2b082b19, + 0x19080808, 0x2b082b19, 0x192b1919, 0x2b082b19, 0x082b082b, 0x2b082b2b, 0x19192b08, 0x2b082b2b, + 0x19192b2b, 0x2b082b2b, 0x2b08082b, 0x2b082b2b, 0x2b2b082b, 0x2b082b2b, 0x08080819, 0x2b190808, + 0x08081908, 0x2b190808, 0x08082b19, 0x2b190808, 0x08190808, 0x2b190808, 0x0819082b, 0x2b190808, + 0x08191919, 0x2b190808, 0x08192b08, 0x2b190808, 0x082b1908, 0x2b190808, 0x19080808, 0x2b190808, + 0x1908082b, 0x2b190808, 0x19081919, 0x2b190808, 0x19082b08, 0x2b190808, 0x19190819, 0x2b190808, + 0x19191908, 0x2b190808, 0x192b0808, 0x2b190808, 0x2b080819, 0x2b190808, 0x2b081908, 0x2b190808, + 0x2b190808, 0x2b190808, 0x08080808, 0x2b190819, 0x08081919, 0x2b190819, 0x08190819, 0x2b190819, + 0x08191908, 0x2b190819, 0x19080819, 0x2b190819, 0x19081908, 0x2b190819, 0x19190808, 0x2b190819, + 0x19192b2b, 0x2b190819, 0x08080819, 0x2b19082b, 0x08081908, 0x2b19082b, 0x08190808, 0x2b19082b, + 0x19080808, 0x2b19082b, 0x2b2b192b, 0x2b19082b, 0x08080808, 0x2b191908, 0x0808082b, 0x2b191908, + 0x08081919, 0x2b191908, 0x08082b08, 0x2b191908, 0x08190819, 0x2b191908, 0x08191908, 0x2b191908, + 0x082b0808, 0x2b191908, 0x19080819, 0x2b191908, 0x19081908, 0x2b191908, 0x19190808, 0x2b191908, + 0x2b080808, 0x2b191908, 0x2b19192b, 0x2b191908, 0x08080819, 0x2b191919, 0x08081908, 0x2b191919, + 0x08190808, 0x2b191919, 0x19080808, 0x2b191919, 0x2b192b08, 0x2b191919, 0x2b2b0819, 0x2b191919, + 0x08080808, 0x2b19192b, 0x1908192b, 0x2b19192b, 0x192b1908, 0x2b19192b, 0x08080819, 0x2b192b08, + 0x08081908, 0x2b192b08, 0x08190808, 0x2b192b08, 0x082b192b, 0x2b192b08, 0x19080808, 0x2b192b08, + 0x2b2b2b19, 0x2b192b08, 0x08080808, 0x2b192b19, 0x19082b19, 0x2b192b19, 0x1919082b, 0x2b192b19, + 0x2b190808, 0x2b192b2b, 0x08080808, 0x2b2b0808, 0x08081919, 0x2b2b0808, 0x08082b2b, 0x2b2b0808, + 0x08191908, 0x2b2b0808, 0x082b082b, 0x2b2b0808, 0x082b2b2b, 0x2b2b0808, 0x19080819, 0x2b2b0808, + 0x19081908, 0x2b2b0808, 0x19190808, 0x2b2b0808, 0x2b2b082b, 0x2b2b0808, 0x2b2b2b2b, 0x2b2b0808, + 0x19080808, 0x2b2b0819, 0x192b1919, 0x2b2b0819, 0x0808082b, 0x2b2b082b, 0x08082b2b, 0x2b2b082b, + 0x082b082b, 0x2b2b082b, 0x082b2b08, 0x2b2b082b, 0x082b2b2b, 0x2b2b082b, 0x2b08082b, 0x2b2b082b, + 0x2b082b08, 0x2b2b082b, 0x2b082b2b, 0x2b2b082b, 0x2b2b2b08, 0x2b2b082b, 0x08080819, 0x2b2b1908, + 0x08081908, 0x2b2b1908, 0x08190808, 0x2b2b1908, 0x19080808, 0x2b2b1908, 0x2b082b19, 0x2b2b1908, + 0x2b2b1908, 0x2b2b1908, 0x08080808, 0x2b2b1919, 0x08192b19, 0x2b2b1919, 0x19190819, 0x2b2b192b, + 0x08082b2b, 0x2b2b2b08, 0x082b2b08, 0x2b2b2b08, 0x2b2b082b, 0x2b2b2b08, 0x19191908, 0x2b2b2b19, + 0x2b08192b, 0x2b2b2b19, 0x08082b08, 0x2b2b2b2b, 0x08082b2b, 0x2b2b2b2b, 0x082b0808, 0x2b2b2b2b, + 0x082b082b, 0x2b2b2b2b, 0x082b2b08, 0x2b2b2b2b, 0x2b082b08, 0x2b2b2b2b, 0x2b2b2b2b, 0x2b2b2b2b +}; diff --git a/ggml/src/ggml-opencl/kernels/iq2_xs_grid.cl b/ggml/src/ggml-opencl/kernels/iq2_xs_grid.cl new file mode 100644 index 000000000000..0893713a962d --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq2_xs_grid.cl @@ -0,0 +1,135 @@ +// IQ2_XS codebook, stored as pairs of four packed magnitudes. +constant uint iq2_xs_grid[1024] = { + 0x08080808, 0x08080808, 0x0808082b, 0x08080808, 0x08081919, 0x08080808, 0x08082b08, 0x08080808, + 0x08082b2b, 0x08080808, 0x08190819, 0x08080808, 0x08191908, 0x08080808, 0x0819192b, 0x08080808, + 0x08192b19, 0x08080808, 0x082b0808, 0x08080808, 0x082b082b, 0x08080808, 0x082b1919, 0x08080808, + 0x082b2b08, 0x08080808, 0x19080819, 0x08080808, 0x19081908, 0x08080808, 0x1908192b, 0x08080808, + 0x19082b19, 0x08080808, 0x19190808, 0x08080808, 0x1919082b, 0x08080808, 0x19191919, 0x08080808, + 0x19192b08, 0x08080808, 0x192b0819, 0x08080808, 0x192b1908, 0x08080808, 0x2b080808, 0x08080808, + 0x2b08082b, 0x08080808, 0x2b081919, 0x08080808, 0x2b082b08, 0x08080808, 0x2b190819, 0x08080808, + 0x2b191908, 0x08080808, 0x2b192b19, 0x08080808, 0x2b2b0808, 0x08080808, 0x08080819, 0x08080819, + 0x08081908, 0x08080819, 0x0808192b, 0x08080819, 0x08082b19, 0x08080819, 0x08190808, 0x08080819, + 0x0819082b, 0x08080819, 0x08191919, 0x08080819, 0x08192b08, 0x08080819, 0x08192b2b, 0x08080819, + 0x082b0819, 0x08080819, 0x082b1908, 0x08080819, 0x19080808, 0x08080819, 0x1908082b, 0x08080819, + 0x19081919, 0x08080819, 0x19082b08, 0x08080819, 0x19190819, 0x08080819, 0x19191908, 0x08080819, + 0x192b0808, 0x08080819, 0x192b2b08, 0x08080819, 0x2b080819, 0x08080819, 0x2b081908, 0x08080819, + 0x2b190808, 0x08080819, 0x08080808, 0x0808082b, 0x0808082b, 0x0808082b, 0x08081919, 0x0808082b, + 0x08082b08, 0x0808082b, 0x08190819, 0x0808082b, 0x08191908, 0x0808082b, 0x082b0808, 0x0808082b, + 0x19080819, 0x0808082b, 0x19081908, 0x0808082b, 0x19190808, 0x0808082b, 0x19191919, 0x0808082b, + 0x2b080808, 0x0808082b, 0x2b082b2b, 0x0808082b, 0x08080819, 0x08081908, 0x08081908, 0x08081908, + 0x0808192b, 0x08081908, 0x08082b19, 0x08081908, 0x08190808, 0x08081908, 0x0819082b, 0x08081908, + 0x08191919, 0x08081908, 0x08192b08, 0x08081908, 0x082b0819, 0x08081908, 0x082b1908, 0x08081908, + 0x19080808, 0x08081908, 0x1908082b, 0x08081908, 0x19081919, 0x08081908, 0x19082b08, 0x08081908, + 0x19190819, 0x08081908, 0x19191908, 0x08081908, 0x1919192b, 0x08081908, 0x192b0808, 0x08081908, + 0x2b080819, 0x08081908, 0x2b081908, 0x08081908, 0x2b190808, 0x08081908, 0x08080808, 0x08081919, + 0x0808082b, 0x08081919, 0x08081919, 0x08081919, 0x08082b08, 0x08081919, 0x08190819, 0x08081919, + 0x08191908, 0x08081919, 0x082b0808, 0x08081919, 0x19080819, 0x08081919, 0x19081908, 0x08081919, + 0x19190808, 0x08081919, 0x192b0819, 0x08081919, 0x2b080808, 0x08081919, 0x08080819, 0x0808192b, + 0x08081908, 0x0808192b, 0x08190808, 0x0808192b, 0x082b192b, 0x0808192b, 0x19080808, 0x0808192b, + 0x1908082b, 0x0808192b, 0x2b081908, 0x0808192b, 0x08080808, 0x08082b08, 0x0808082b, 0x08082b08, + 0x08081919, 0x08082b08, 0x08082b08, 0x08082b08, 0x08082b2b, 0x08082b08, 0x08190819, 0x08082b08, + 0x08191908, 0x08082b08, 0x082b0808, 0x08082b08, 0x082b1919, 0x08082b08, 0x19080819, 0x08082b08, + 0x19081908, 0x08082b08, 0x19190808, 0x08082b08, 0x19192b08, 0x08082b08, 0x2b080808, 0x08082b08, + 0x2b2b0808, 0x08082b08, 0x2b2b2b2b, 0x08082b08, 0x08080819, 0x08082b19, 0x08081908, 0x08082b19, + 0x08190808, 0x08082b19, 0x19080808, 0x08082b19, 0x2b080819, 0x08082b19, 0x2b082b19, 0x08082b19, + 0x08080808, 0x08082b2b, 0x082b0808, 0x08082b2b, 0x082b2b08, 0x08082b2b, 0x2b19192b, 0x08082b2b, + 0x2b2b0808, 0x08082b2b, 0x08080819, 0x08190808, 0x08081908, 0x08190808, 0x0808192b, 0x08190808, + 0x08082b19, 0x08190808, 0x08190808, 0x08190808, 0x0819082b, 0x08190808, 0x08191919, 0x08190808, + 0x08192b08, 0x08190808, 0x082b0819, 0x08190808, 0x082b1908, 0x08190808, 0x19080808, 0x08190808, + 0x1908082b, 0x08190808, 0x19081919, 0x08190808, 0x19082b08, 0x08190808, 0x19190819, 0x08190808, + 0x19191908, 0x08190808, 0x192b0808, 0x08190808, 0x192b2b2b, 0x08190808, 0x2b080819, 0x08190808, + 0x2b081908, 0x08190808, 0x2b190808, 0x08190808, 0x08080808, 0x08190819, 0x0808082b, 0x08190819, + 0x08081919, 0x08190819, 0x08082b08, 0x08190819, 0x08190819, 0x08190819, 0x08191908, 0x08190819, + 0x082b0808, 0x08190819, 0x19080819, 0x08190819, 0x19081908, 0x08190819, 0x19190808, 0x08190819, + 0x2b080808, 0x08190819, 0x2b191908, 0x08190819, 0x2b19192b, 0x08190819, 0x08080819, 0x0819082b, + 0x08081908, 0x0819082b, 0x0808192b, 0x0819082b, 0x08190808, 0x0819082b, 0x19080808, 0x0819082b, + 0x192b0808, 0x0819082b, 0x08080808, 0x08191908, 0x0808082b, 0x08191908, 0x08081919, 0x08191908, + 0x08082b08, 0x08191908, 0x08190819, 0x08191908, 0x08191908, 0x08191908, 0x082b0808, 0x08191908, + 0x19080819, 0x08191908, 0x19081908, 0x08191908, 0x19082b19, 0x08191908, 0x19190808, 0x08191908, + 0x192b1908, 0x08191908, 0x2b080808, 0x08191908, 0x08080819, 0x08191919, 0x08081908, 0x08191919, + 0x08190808, 0x08191919, 0x19080808, 0x08191919, 0x08080808, 0x0819192b, 0x08191908, 0x0819192b, + 0x19082b19, 0x0819192b, 0x08080819, 0x08192b08, 0x08081908, 0x08192b08, 0x08190808, 0x08192b08, + 0x0819082b, 0x08192b08, 0x19080808, 0x08192b08, 0x19191908, 0x08192b08, 0x2b08192b, 0x08192b08, + 0x08080808, 0x08192b19, 0x08081919, 0x08192b19, 0x192b192b, 0x08192b19, 0x19190819, 0x08192b2b, + 0x2b2b2b19, 0x08192b2b, 0x08080808, 0x082b0808, 0x0808082b, 0x082b0808, 0x08081919, 0x082b0808, + 0x08082b08, 0x082b0808, 0x08082b2b, 0x082b0808, 0x08190819, 0x082b0808, 0x08191908, 0x082b0808, + 0x082b0808, 0x082b0808, 0x19080819, 0x082b0808, 0x19081908, 0x082b0808, 0x19190808, 0x082b0808, + 0x2b080808, 0x082b0808, 0x2b2b0808, 0x082b0808, 0x08080819, 0x082b0819, 0x08081908, 0x082b0819, + 0x08190808, 0x082b0819, 0x19080808, 0x082b0819, 0x19082b08, 0x082b0819, 0x192b1919, 0x082b0819, + 0x08080808, 0x082b082b, 0x082b082b, 0x082b082b, 0x2b080808, 0x082b082b, 0x2b2b2b08, 0x082b082b, + 0x08080819, 0x082b1908, 0x08081908, 0x082b1908, 0x08190808, 0x082b1908, 0x082b2b19, 0x082b1908, + 0x19080808, 0x082b1908, 0x08080808, 0x082b1919, 0x19080819, 0x082b1919, 0x1919082b, 0x082b1919, + 0x2b192b19, 0x082b1919, 0x08080819, 0x082b192b, 0x08192b2b, 0x082b192b, 0x2b2b192b, 0x082b192b, + 0x08080808, 0x082b2b08, 0x08082b08, 0x082b2b08, 0x08082b2b, 0x082b2b08, 0x082b0808, 0x082b2b08, + 0x19191919, 0x082b2b08, 0x2b082b08, 0x082b2b08, 0x2b2b082b, 0x082b2b08, 0x192b2b08, 0x082b2b19, + 0x2b190808, 0x082b2b19, 0x08082b08, 0x082b2b2b, 0x082b0808, 0x082b2b2b, 0x2b08082b, 0x082b2b2b, + 0x2b082b08, 0x082b2b2b, 0x2b082b2b, 0x082b2b2b, 0x08080819, 0x19080808, 0x08081908, 0x19080808, + 0x0808192b, 0x19080808, 0x08082b19, 0x19080808, 0x08190808, 0x19080808, 0x0819082b, 0x19080808, + 0x08191919, 0x19080808, 0x08192b08, 0x19080808, 0x082b0819, 0x19080808, 0x082b1908, 0x19080808, + 0x19080808, 0x19080808, 0x1908082b, 0x19080808, 0x19081919, 0x19080808, 0x19082b08, 0x19080808, + 0x19082b2b, 0x19080808, 0x19190819, 0x19080808, 0x19191908, 0x19080808, 0x192b0808, 0x19080808, + 0x192b1919, 0x19080808, 0x2b080819, 0x19080808, 0x2b081908, 0x19080808, 0x2b190808, 0x19080808, + 0x08080808, 0x19080819, 0x0808082b, 0x19080819, 0x08081919, 0x19080819, 0x08082b08, 0x19080819, + 0x08190819, 0x19080819, 0x08191908, 0x19080819, 0x082b0808, 0x19080819, 0x19080819, 0x19080819, + 0x19081908, 0x19080819, 0x19190808, 0x19080819, 0x2b080808, 0x19080819, 0x2b081919, 0x19080819, + 0x2b2b082b, 0x19080819, 0x08080819, 0x1908082b, 0x08081908, 0x1908082b, 0x08190808, 0x1908082b, + 0x0819082b, 0x1908082b, 0x082b2b19, 0x1908082b, 0x19080808, 0x1908082b, 0x08080808, 0x19081908, + 0x0808082b, 0x19081908, 0x08081919, 0x19081908, 0x08082b08, 0x19081908, 0x08190819, 0x19081908, + 0x08191908, 0x19081908, 0x08192b19, 0x19081908, 0x082b0808, 0x19081908, 0x19080819, 0x19081908, + 0x19081908, 0x19081908, 0x19190808, 0x19081908, 0x2b080808, 0x19081908, 0x2b191908, 0x19081908, + 0x08080819, 0x19081919, 0x08081908, 0x19081919, 0x08190808, 0x19081919, 0x082b1908, 0x19081919, + 0x19080808, 0x19081919, 0x2b192b2b, 0x19081919, 0x08080808, 0x1908192b, 0x08082b2b, 0x1908192b, + 0x19081908, 0x1908192b, 0x19190808, 0x1908192b, 0x08080819, 0x19082b08, 0x08081908, 0x19082b08, + 0x08190808, 0x19082b08, 0x19080808, 0x19082b08, 0x19081919, 0x19082b08, 0x19191908, 0x19082b08, + 0x192b082b, 0x19082b08, 0x08080808, 0x19082b19, 0x08190819, 0x19082b19, 0x19081908, 0x19082b19, + 0x19190808, 0x19082b19, 0x192b2b19, 0x19082b19, 0x08081908, 0x19082b2b, 0x08080808, 0x19190808, + 0x0808082b, 0x19190808, 0x08081919, 0x19190808, 0x08082b08, 0x19190808, 0x08190819, 0x19190808, + 0x08191908, 0x19190808, 0x082b0808, 0x19190808, 0x082b2b08, 0x19190808, 0x19080819, 0x19190808, + 0x19081908, 0x19190808, 0x19190808, 0x19190808, 0x2b080808, 0x19190808, 0x08080819, 0x19190819, + 0x08081908, 0x19190819, 0x08190808, 0x19190819, 0x08191919, 0x19190819, 0x19080808, 0x19190819, + 0x1908082b, 0x19190819, 0x08080808, 0x1919082b, 0x19081908, 0x1919082b, 0x2b2b2b2b, 0x1919082b, + 0x08080819, 0x19191908, 0x08081908, 0x19191908, 0x08190808, 0x19191908, 0x082b0819, 0x19191908, + 0x19080808, 0x19191908, 0x192b0808, 0x19191908, 0x2b080819, 0x19191908, 0x2b2b0819, 0x19191908, + 0x08080808, 0x19191919, 0x08082b08, 0x19191919, 0x2b080808, 0x19191919, 0x2b082b08, 0x19191919, + 0x082b0819, 0x1919192b, 0x192b2b08, 0x1919192b, 0x2b2b0819, 0x1919192b, 0x08080808, 0x19192b08, + 0x08191908, 0x19192b08, 0x19080819, 0x19192b08, 0x19190808, 0x19192b08, 0x2b192b19, 0x19192b08, + 0x08192b2b, 0x19192b19, 0x19080808, 0x19192b19, 0x1908082b, 0x19192b19, 0x2b081919, 0x19192b2b, + 0x08080819, 0x192b0808, 0x08081908, 0x192b0808, 0x08190808, 0x192b0808, 0x19080808, 0x192b0808, + 0x19191908, 0x192b0808, 0x192b082b, 0x192b0808, 0x2b08192b, 0x192b0808, 0x2b2b2b19, 0x192b0808, + 0x08080808, 0x192b0819, 0x082b1908, 0x192b082b, 0x19082b2b, 0x192b082b, 0x2b19082b, 0x192b082b, + 0x08080808, 0x192b1908, 0x0819192b, 0x192b1908, 0x08190808, 0x192b1919, 0x19080808, 0x192b1919, + 0x19081919, 0x192b1919, 0x2b2b1908, 0x192b1919, 0x08080819, 0x192b2b08, 0x192b2b2b, 0x192b2b08, + 0x082b1919, 0x192b2b19, 0x0808192b, 0x192b2b2b, 0x19191908, 0x192b2b2b, 0x192b082b, 0x192b2b2b, + 0x08080808, 0x2b080808, 0x0808082b, 0x2b080808, 0x08081919, 0x2b080808, 0x08082b08, 0x2b080808, + 0x08190819, 0x2b080808, 0x08191908, 0x2b080808, 0x082b0808, 0x2b080808, 0x082b2b2b, 0x2b080808, + 0x19080819, 0x2b080808, 0x19081908, 0x2b080808, 0x19190808, 0x2b080808, 0x2b080808, 0x2b080808, + 0x2b08082b, 0x2b080808, 0x2b2b2b08, 0x2b080808, 0x2b2b2b2b, 0x2b080808, 0x08080819, 0x2b080819, + 0x08081908, 0x2b080819, 0x0808192b, 0x2b080819, 0x08190808, 0x2b080819, 0x19080808, 0x2b080819, + 0x19190819, 0x2b080819, 0x19192b19, 0x2b080819, 0x08080808, 0x2b08082b, 0x082b0808, 0x2b08082b, + 0x2b080808, 0x2b08082b, 0x2b08082b, 0x2b08082b, 0x2b2b0808, 0x2b08082b, 0x2b2b2b08, 0x2b08082b, + 0x08080819, 0x2b081908, 0x08081908, 0x2b081908, 0x08190808, 0x2b081908, 0x0819082b, 0x2b081908, + 0x08191919, 0x2b081908, 0x19080808, 0x2b081908, 0x192b0808, 0x2b081908, 0x2b082b19, 0x2b081908, + 0x08080808, 0x2b081919, 0x19081908, 0x2b081919, 0x2b2b1919, 0x2b081919, 0x08192b08, 0x2b08192b, + 0x192b2b2b, 0x2b08192b, 0x08080808, 0x2b082b08, 0x08082b08, 0x2b082b08, 0x082b1919, 0x2b082b08, + 0x19192b2b, 0x2b082b08, 0x2b080808, 0x2b082b08, 0x2b08082b, 0x2b082b08, 0x2b2b2b08, 0x2b082b08, + 0x0808192b, 0x2b082b19, 0x082b082b, 0x2b082b2b, 0x2b080808, 0x2b082b2b, 0x2b082b08, 0x2b082b2b, + 0x2b19192b, 0x2b082b2b, 0x2b2b2b08, 0x2b082b2b, 0x08080819, 0x2b190808, 0x08081908, 0x2b190808, + 0x08190808, 0x2b190808, 0x19080808, 0x2b190808, 0x1919192b, 0x2b190808, 0x2b081908, 0x2b190808, + 0x08080808, 0x2b190819, 0x082b082b, 0x2b190819, 0x192b1908, 0x2b190819, 0x1919192b, 0x2b19082b, + 0x2b082b19, 0x2b19082b, 0x08080808, 0x2b191908, 0x08081919, 0x2b191908, 0x19081908, 0x2b191908, + 0x19190808, 0x2b191908, 0x19192b08, 0x2b191908, 0x082b2b19, 0x2b191919, 0x2b190808, 0x2b191919, + 0x2b19082b, 0x2b191919, 0x19080819, 0x2b19192b, 0x19190819, 0x2b192b08, 0x2b2b192b, 0x2b192b08, + 0x19082b19, 0x2b192b19, 0x08191919, 0x2b192b2b, 0x192b0808, 0x2b192b2b, 0x08080808, 0x2b2b0808, + 0x0808082b, 0x2b2b0808, 0x08082b08, 0x2b2b0808, 0x08082b2b, 0x2b2b0808, 0x082b0808, 0x2b2b0808, + 0x082b2b2b, 0x2b2b0808, 0x2b2b0808, 0x2b2b0808, 0x19190819, 0x2b2b0819, 0x19192b19, 0x2b2b0819, + 0x2b2b192b, 0x2b2b0819, 0x08080808, 0x2b2b082b, 0x0808082b, 0x2b2b082b, 0x08082b08, 0x2b2b082b, + 0x082b2b2b, 0x2b2b082b, 0x2b080808, 0x2b2b082b, 0x2b2b0808, 0x2b2b082b, 0x19080808, 0x2b2b1908, + 0x2b191919, 0x2b2b1908, 0x192b1919, 0x2b2b192b, 0x2b192b08, 0x2b2b192b, 0x08082b2b, 0x2b2b2b08, + 0x082b0808, 0x2b2b2b08, 0x082b082b, 0x2b2b2b08, 0x082b2b08, 0x2b2b2b08, 0x2b2b0808, 0x2b2b2b08, + 0x2b2b2b08, 0x2b2b2b08, 0x08081908, 0x2b2b2b19, 0x2b081908, 0x2b2b2b19, 0x2b08192b, 0x2b2b2b19, + 0x082b2b08, 0x2b2b2b2b, 0x082b2b2b, 0x2b2b2b2b, 0x2b190819, 0x2b2b2b2b, 0x2b2b2b2b, 0x2b2b2b2b +}; + +inline uint iq2_xs_signs(uint code) { + return code | ((popcount(code) & 1u) << 7); +} diff --git a/ggml/src/ggml-opencl/kernels/iq2_xxs_grid.cl b/ggml/src/ggml-opencl/kernels/iq2_xxs_grid.cl new file mode 100644 index 000000000000..794e097ef4b5 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq2_xxs_grid.cl @@ -0,0 +1,71 @@ +// IQ2_XXS codebook, stored as pairs of four packed magnitudes. +constant uint iq2_xxs_grid[512] = { + 0x08080808, 0x08080808, 0x0808082b, 0x08080808, 0x08081919, 0x08080808, 0x08082b08, 0x08080808, + 0x08082b2b, 0x08080808, 0x08190819, 0x08080808, 0x08191908, 0x08080808, 0x082b0808, 0x08080808, + 0x082b082b, 0x08080808, 0x082b2b08, 0x08080808, 0x082b2b2b, 0x08080808, 0x19080819, 0x08080808, + 0x19081908, 0x08080808, 0x19190808, 0x08080808, 0x19192b08, 0x08080808, 0x192b0819, 0x08080808, + 0x192b1908, 0x08080808, 0x2b080808, 0x08080808, 0x2b08082b, 0x08080808, 0x2b082b2b, 0x08080808, + 0x2b2b082b, 0x08080808, 0x08080819, 0x08080819, 0x08081908, 0x08080819, 0x08190808, 0x08080819, + 0x08191919, 0x08080819, 0x19080808, 0x08080819, 0x2b081908, 0x08080819, 0x2b192b08, 0x08080819, + 0x08080808, 0x0808082b, 0x0808082b, 0x0808082b, 0x082b082b, 0x0808082b, 0x2b08082b, 0x0808082b, + 0x08080819, 0x08081908, 0x08081908, 0x08081908, 0x08190808, 0x08081908, 0x082b0819, 0x08081908, + 0x082b1908, 0x08081908, 0x19080808, 0x08081908, 0x1908082b, 0x08081908, 0x19082b08, 0x08081908, + 0x192b0808, 0x08081908, 0x2b080819, 0x08081908, 0x2b081908, 0x08081908, 0x2b190808, 0x08081908, + 0x2b2b1908, 0x08081908, 0x08080808, 0x08081919, 0x0808082b, 0x08081919, 0x08082b08, 0x08081919, + 0x082b0808, 0x08081919, 0x1908192b, 0x08081919, 0x192b2b19, 0x08081919, 0x2b080808, 0x08081919, + 0x2b190819, 0x08081919, 0x08082b19, 0x0808192b, 0x08190808, 0x0808192b, 0x19080808, 0x0808192b, + 0x2b081908, 0x0808192b, 0x2b2b1908, 0x0808192b, 0x08080808, 0x08082b08, 0x08081919, 0x08082b08, + 0x08082b08, 0x08082b08, 0x08191908, 0x08082b08, 0x082b2b08, 0x08082b08, 0x19080819, 0x08082b08, + 0x19081908, 0x08082b08, 0x19190808, 0x08082b08, 0x1919082b, 0x08082b08, 0x2b082b08, 0x08082b08, + 0x08081908, 0x08082b19, 0x19080808, 0x08082b19, 0x0808082b, 0x08082b2b, 0x08191908, 0x08082b2b, + 0x08080819, 0x08190808, 0x08081908, 0x08190808, 0x08190808, 0x08190808, 0x082b0819, 0x08190808, + 0x19080808, 0x08190808, 0x192b0808, 0x08190808, 0x2b081908, 0x08190808, 0x2b190808, 0x08190808, + 0x2b191919, 0x08190808, 0x08080808, 0x08190819, 0x08082b08, 0x08190819, 0x082b0808, 0x08190819, + 0x19190808, 0x08190819, 0x19192b2b, 0x08190819, 0x2b080808, 0x08190819, 0x082b1908, 0x0819082b, + 0x19081919, 0x0819082b, 0x08080808, 0x08191908, 0x08082b08, 0x08191908, 0x082b0808, 0x08191908, + 0x082b1919, 0x08191908, 0x19082b19, 0x08191908, 0x2b080808, 0x08191908, 0x08192b08, 0x08191919, + 0x192b082b, 0x08191919, 0x08080808, 0x0819192b, 0x0819192b, 0x0819192b, 0x08080819, 0x08192b08, + 0x08081908, 0x08192b08, 0x08190808, 0x08192b08, 0x19080808, 0x08192b08, 0x2b080819, 0x08192b08, + 0x08080808, 0x08192b19, 0x08081919, 0x08192b19, 0x2b2b0808, 0x08192b19, 0x19190819, 0x08192b2b, + 0x08080808, 0x082b0808, 0x0808082b, 0x082b0808, 0x08082b2b, 0x082b0808, 0x19081908, 0x082b0808, + 0x192b0819, 0x082b0808, 0x2b080808, 0x082b0808, 0x2b08082b, 0x082b0808, 0x082b2b19, 0x082b0819, + 0x19082b08, 0x082b0819, 0x08080808, 0x082b082b, 0x0808082b, 0x082b082b, 0x08080819, 0x082b1908, + 0x08081908, 0x082b1908, 0x08190808, 0x082b1908, 0x19080808, 0x082b1908, 0x1919192b, 0x082b1908, + 0x08080808, 0x082b1919, 0x19080819, 0x082b1919, 0x192b1908, 0x082b1919, 0x2b190808, 0x082b192b, + 0x08082b08, 0x082b2b08, 0x082b0808, 0x082b2b08, 0x2b191908, 0x082b2b08, 0x19081908, 0x082b2b2b, + 0x08080819, 0x19080808, 0x08081908, 0x19080808, 0x08190808, 0x19080808, 0x08192b08, 0x19080808, + 0x082b0819, 0x19080808, 0x082b1908, 0x19080808, 0x19080808, 0x19080808, 0x19082b08, 0x19080808, + 0x1919192b, 0x19080808, 0x192b0808, 0x19080808, 0x2b080819, 0x19080808, 0x2b081908, 0x19080808, + 0x2b190808, 0x19080808, 0x08080808, 0x19080819, 0x082b0808, 0x19080819, 0x192b0819, 0x19080819, + 0x2b080808, 0x19080819, 0x2b081919, 0x19080819, 0x08080819, 0x1908082b, 0x08190808, 0x1908082b, + 0x19082b08, 0x1908082b, 0x1919192b, 0x1908082b, 0x192b2b08, 0x1908082b, 0x08080808, 0x19081908, + 0x08082b08, 0x19081908, 0x082b0808, 0x19081908, 0x2b080808, 0x19081908, 0x2b192b19, 0x19081908, + 0x0819082b, 0x19081919, 0x082b1908, 0x19081919, 0x08080808, 0x1908192b, 0x08080819, 0x19082b08, + 0x08081908, 0x19082b08, 0x08190808, 0x19082b08, 0x19080808, 0x19082b08, 0x19081919, 0x19082b08, + 0x08080808, 0x19082b19, 0x19192b08, 0x19082b19, 0x192b0819, 0x19082b19, 0x2b08082b, 0x19082b19, + 0x19081919, 0x19082b2b, 0x2b190808, 0x19082b2b, 0x08080808, 0x19190808, 0x08082b08, 0x19190808, + 0x08190819, 0x19190808, 0x08192b19, 0x19190808, 0x082b0808, 0x19190808, 0x2b080808, 0x19190808, + 0x2b082b08, 0x19190808, 0x08081908, 0x19190819, 0x1908082b, 0x19190819, 0x2b2b1908, 0x19190819, + 0x2b190819, 0x1919082b, 0x2b190808, 0x19191908, 0x2b19082b, 0x19191908, 0x08082b2b, 0x19191919, + 0x08080819, 0x1919192b, 0x19191908, 0x1919192b, 0x08080808, 0x19192b08, 0x08190819, 0x19192b08, + 0x08192b19, 0x19192b08, 0x192b1908, 0x19192b08, 0x19080808, 0x19192b19, 0x08082b08, 0x19192b2b, + 0x08081908, 0x192b0808, 0x08190808, 0x192b0808, 0x19080808, 0x192b0808, 0x192b2b08, 0x192b0808, + 0x08080808, 0x192b0819, 0x19191919, 0x192b0819, 0x08192b08, 0x192b082b, 0x192b0808, 0x192b082b, + 0x08080808, 0x192b1908, 0x08081919, 0x192b1908, 0x08190808, 0x192b1919, 0x0819082b, 0x192b1919, + 0x2b081908, 0x192b1919, 0x1908082b, 0x192b2b08, 0x08080808, 0x2b080808, 0x0808082b, 0x2b080808, + 0x08082b2b, 0x2b080808, 0x19080819, 0x2b080808, 0x2b08082b, 0x2b080808, 0x08081908, 0x2b080819, + 0x08192b08, 0x2b080819, 0x19080808, 0x2b080819, 0x08190819, 0x2b08082b, 0x08080819, 0x2b081908, + 0x08081908, 0x2b081908, 0x08190808, 0x2b081908, 0x08191919, 0x2b081908, 0x19080808, 0x2b081908, + 0x192b0808, 0x2b081908, 0x08080808, 0x2b081919, 0x1908192b, 0x2b081919, 0x2b191908, 0x2b081919, + 0x08082b19, 0x2b08192b, 0x19080808, 0x2b08192b, 0x192b0808, 0x2b08192b, 0x0808082b, 0x2b082b08, + 0x08081908, 0x2b082b19, 0x08190819, 0x2b082b2b, 0x08081908, 0x2b190808, 0x08190808, 0x2b190808, + 0x082b1908, 0x2b190808, 0x19080808, 0x2b190808, 0x2b2b0819, 0x2b190808, 0x0819192b, 0x2b190819, + 0x2b080808, 0x2b190819, 0x19081919, 0x2b19082b, 0x08080808, 0x2b191908, 0x082b082b, 0x2b191908, + 0x19081908, 0x2b191908, 0x19190819, 0x2b191919, 0x2b080819, 0x2b192b08, 0x082b0808, 0x2b192b19, + 0x0808082b, 0x2b2b0808, 0x19190808, 0x2b2b0808, 0x2b081919, 0x2b2b0808, 0x08082b19, 0x2b2b0819, + 0x08080808, 0x2b2b082b, 0x08192b08, 0x2b2b1908, 0x19190808, 0x2b2b2b08, 0x08081908, 0x2b2b2b19 +}; + +inline uint iq2_xxs_signs(uint code) { + return code | ((popcount(code) & 1u) << 7); +} diff --git a/ggml/src/ggml-opencl/kernels/iq3_s_grid.cl b/ggml/src/ggml-opencl/kernels/iq3_s_grid.cl new file mode 100644 index 000000000000..7ffd2c4fe5f6 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq3_s_grid.cl @@ -0,0 +1,66 @@ +constant uint iq3_s_grid[512] = { + 0x01010101, 0x01010103, 0x01010105, 0x0101010b, 0x0101010f, 0x01010301, 0x01010303, 0x01010305, + 0x01010309, 0x0101030d, 0x01010501, 0x01010503, 0x0101050b, 0x01010707, 0x01010901, 0x01010905, + 0x0101090b, 0x0101090f, 0x01010b03, 0x01010b07, 0x01010d01, 0x01010d05, 0x01010f03, 0x01010f09, + 0x01010f0f, 0x01030101, 0x01030103, 0x01030105, 0x01030109, 0x01030301, 0x01030303, 0x0103030b, + 0x01030501, 0x01030507, 0x0103050f, 0x01030703, 0x0103070b, 0x01030909, 0x01030d03, 0x01030d0b, + 0x01030f05, 0x01050101, 0x01050103, 0x0105010b, 0x0105010f, 0x01050301, 0x01050307, 0x0105030d, + 0x01050503, 0x0105050b, 0x01050701, 0x01050709, 0x01050905, 0x0105090b, 0x0105090f, 0x01050b03, + 0x01050b07, 0x01050f01, 0x01050f07, 0x01070107, 0x01070303, 0x0107030b, 0x01070501, 0x01070505, + 0x01070703, 0x01070707, 0x0107070d, 0x01070909, 0x01070b01, 0x01070b05, 0x01070d0f, 0x01070f03, + 0x01070f0b, 0x01090101, 0x01090307, 0x0109030f, 0x01090503, 0x01090509, 0x01090705, 0x01090901, + 0x01090907, 0x01090b03, 0x01090f01, 0x010b0105, 0x010b0109, 0x010b0501, 0x010b0505, 0x010b050d, + 0x010b0707, 0x010b0903, 0x010b090b, 0x010b090f, 0x010b0d0d, 0x010b0f07, 0x010d010d, 0x010d0303, + 0x010d0307, 0x010d0703, 0x010d0b05, 0x010d0f03, 0x010f0101, 0x010f0105, 0x010f0109, 0x010f0501, + 0x010f0505, 0x010f050d, 0x010f0707, 0x010f0b01, 0x010f0b09, 0x03010101, 0x03010103, 0x03010105, + 0x03010109, 0x03010301, 0x03010303, 0x03010307, 0x0301030b, 0x0301030f, 0x03010501, 0x03010505, + 0x03010703, 0x03010709, 0x0301070d, 0x03010b09, 0x03010b0d, 0x03010d03, 0x03010f05, 0x03030101, + 0x03030103, 0x03030107, 0x0303010d, 0x03030301, 0x03030309, 0x03030503, 0x03030701, 0x03030707, + 0x03030903, 0x03030b01, 0x03030b05, 0x03030f01, 0x03030f0d, 0x03050101, 0x03050305, 0x0305030b, + 0x0305030f, 0x03050501, 0x03050509, 0x03050705, 0x03050901, 0x03050907, 0x03050b0b, 0x03050d01, + 0x03050f05, 0x03070103, 0x03070109, 0x0307010f, 0x03070301, 0x03070307, 0x03070503, 0x0307050f, + 0x03070701, 0x03070709, 0x03070903, 0x03070d05, 0x03070f01, 0x03090107, 0x0309010b, 0x03090305, + 0x03090309, 0x03090703, 0x03090707, 0x03090905, 0x0309090d, 0x03090b01, 0x03090b09, 0x030b0103, + 0x030b0301, 0x030b0307, 0x030b0503, 0x030b0701, 0x030b0705, 0x030b0b03, 0x030d0501, 0x030d0509, + 0x030d050f, 0x030d0909, 0x030d090d, 0x030f0103, 0x030f0107, 0x030f0301, 0x030f0305, 0x030f0503, + 0x030f070b, 0x030f0903, 0x030f0d05, 0x030f0f01, 0x05010101, 0x05010103, 0x05010107, 0x0501010b, + 0x0501010f, 0x05010301, 0x05010305, 0x05010309, 0x0501030d, 0x05010503, 0x05010507, 0x0501050f, + 0x05010701, 0x05010705, 0x05010903, 0x05010907, 0x0501090b, 0x05010b01, 0x05010b05, 0x05010d0f, + 0x05010f01, 0x05010f07, 0x05010f0b, 0x05030101, 0x05030105, 0x05030301, 0x05030307, 0x0503030f, + 0x05030505, 0x0503050b, 0x05030703, 0x05030709, 0x05030905, 0x05030b03, 0x05050103, 0x05050109, + 0x0505010f, 0x05050503, 0x05050507, 0x05050701, 0x0505070f, 0x05050903, 0x05050b07, 0x05050b0f, + 0x05050f03, 0x05050f09, 0x05070101, 0x05070105, 0x0507010b, 0x05070303, 0x05070505, 0x05070509, + 0x05070703, 0x05070707, 0x05070905, 0x05070b01, 0x05070d0d, 0x05090103, 0x0509010f, 0x05090501, + 0x05090507, 0x05090705, 0x0509070b, 0x05090903, 0x05090f05, 0x05090f0b, 0x050b0109, 0x050b0303, + 0x050b0505, 0x050b070f, 0x050b0901, 0x050b0b07, 0x050b0f01, 0x050d0101, 0x050d0105, 0x050d010f, + 0x050d0503, 0x050d0b0b, 0x050d0d03, 0x050f010b, 0x050f0303, 0x050f050d, 0x050f0701, 0x050f0907, + 0x050f0b01, 0x07010105, 0x07010303, 0x07010307, 0x0701030b, 0x0701030f, 0x07010505, 0x07010703, + 0x07010707, 0x0701070b, 0x07010905, 0x07010909, 0x0701090f, 0x07010b03, 0x07010d07, 0x07010f03, + 0x07030103, 0x07030107, 0x0703010b, 0x07030309, 0x07030503, 0x07030507, 0x07030901, 0x07030d01, + 0x07030f05, 0x07030f0d, 0x07050101, 0x07050305, 0x07050501, 0x07050705, 0x07050709, 0x07050b01, + 0x07070103, 0x07070301, 0x07070309, 0x07070503, 0x07070507, 0x0707050f, 0x07070701, 0x07070903, + 0x07070907, 0x0707090f, 0x07070b0b, 0x07070f07, 0x07090107, 0x07090303, 0x0709030d, 0x07090505, + 0x07090703, 0x07090b05, 0x07090d01, 0x07090d09, 0x070b0103, 0x070b0301, 0x070b0305, 0x070b050b, + 0x070b0705, 0x070b0909, 0x070b0b0d, 0x070b0f07, 0x070d030d, 0x070d0903, 0x070f0103, 0x070f0107, + 0x070f0501, 0x070f0505, 0x070f070b, 0x09010101, 0x09010109, 0x09010305, 0x09010501, 0x09010509, + 0x0901050f, 0x09010705, 0x09010903, 0x09010b01, 0x09010f01, 0x09030105, 0x0903010f, 0x09030303, + 0x09030307, 0x09030505, 0x09030701, 0x0903070b, 0x09030907, 0x09030b03, 0x09030b0b, 0x09050103, + 0x09050107, 0x09050301, 0x0905030b, 0x09050503, 0x09050707, 0x09050901, 0x09050b0f, 0x09050d05, + 0x09050f01, 0x09070109, 0x09070303, 0x09070307, 0x09070501, 0x09070505, 0x09070703, 0x0907070b, + 0x09090101, 0x09090105, 0x09090509, 0x0909070f, 0x09090901, 0x09090f03, 0x090b010b, 0x090b010f, + 0x090b0503, 0x090b0d05, 0x090d0307, 0x090d0709, 0x090d0d01, 0x090f0301, 0x090f030b, 0x090f0701, + 0x090f0907, 0x090f0b03, 0x0b010105, 0x0b010301, 0x0b010309, 0x0b010505, 0x0b010901, 0x0b010909, + 0x0b01090f, 0x0b010b05, 0x0b010d0d, 0x0b010f09, 0x0b030103, 0x0b030107, 0x0b03010b, 0x0b030305, + 0x0b030503, 0x0b030705, 0x0b030f05, 0x0b050101, 0x0b050303, 0x0b050507, 0x0b050701, 0x0b05070d, + 0x0b050b07, 0x0b070105, 0x0b07010f, 0x0b070301, 0x0b07050f, 0x0b070909, 0x0b070b03, 0x0b070d0b, + 0x0b070f07, 0x0b090103, 0x0b090109, 0x0b090501, 0x0b090705, 0x0b09090d, 0x0b0b0305, 0x0b0b050d, + 0x0b0b0b03, 0x0b0b0b07, 0x0b0d0905, 0x0b0f0105, 0x0b0f0109, 0x0b0f0505, 0x0d010303, 0x0d010307, + 0x0d01030b, 0x0d010703, 0x0d010707, 0x0d010d01, 0x0d030101, 0x0d030501, 0x0d03050f, 0x0d030d09, + 0x0d050305, 0x0d050709, 0x0d050905, 0x0d050b0b, 0x0d050d05, 0x0d050f01, 0x0d070101, 0x0d070309, + 0x0d070503, 0x0d070901, 0x0d09050b, 0x0d090907, 0x0d090d05, 0x0d0b0101, 0x0d0b0107, 0x0d0b0709, + 0x0d0b0d01, 0x0d0d010b, 0x0d0d0901, 0x0d0f0303, 0x0d0f0307, 0x0f010101, 0x0f010109, 0x0f01010f, + 0x0f010501, 0x0f010505, 0x0f01070d, 0x0f010901, 0x0f010b09, 0x0f010d05, 0x0f030105, 0x0f030303, + 0x0f030509, 0x0f030907, 0x0f03090b, 0x0f050103, 0x0f050109, 0x0f050301, 0x0f05030d, 0x0f050503, + 0x0f050701, 0x0f050b03, 0x0f070105, 0x0f070705, 0x0f07070b, 0x0f070b07, 0x0f090103, 0x0f09010b, + 0x0f090307, 0x0f090501, 0x0f090b01, 0x0f0b0505, 0x0f0b0905, 0x0f0d0105, 0x0f0d0703, 0x0f0f0101 +}; diff --git a/ggml/src/ggml-opencl/kernels/iq3_xxs_grid.cl b/ggml/src/ggml-opencl/kernels/iq3_xxs_grid.cl new file mode 100644 index 000000000000..4c79ddf1adcc --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/iq3_xxs_grid.cl @@ -0,0 +1,38 @@ +constant uint iq3_xxs_grid[256] = { + 0x04040404, 0x04040414, 0x04040424, 0x04040c0c, 0x04040c1c, 0x04040c3e, 0x04041404, 0x04041414, + 0x04041c0c, 0x04042414, 0x04043e1c, 0x04043e2c, 0x040c040c, 0x040c041c, 0x040c0c04, 0x040c0c14, + 0x040c140c, 0x040c142c, 0x040c1c04, 0x040c1c14, 0x040c240c, 0x040c2c24, 0x040c3e04, 0x04140404, + 0x04140414, 0x04140424, 0x04140c0c, 0x04141404, 0x04141414, 0x04141c0c, 0x04141c1c, 0x04141c3e, + 0x04142c0c, 0x04142c3e, 0x04143e2c, 0x041c040c, 0x041c043e, 0x041c0c04, 0x041c0c14, 0x041c142c, + 0x041c3e04, 0x04240c1c, 0x04241c3e, 0x04242424, 0x04242c3e, 0x04243e1c, 0x04243e2c, 0x042c040c, + 0x042c043e, 0x042c1c14, 0x042c2c14, 0x04341c2c, 0x04343424, 0x043e0c04, 0x043e0c24, 0x043e0c34, + 0x043e241c, 0x043e340c, 0x0c04040c, 0x0c04041c, 0x0c040c04, 0x0c040c14, 0x0c04140c, 0x0c04141c, + 0x0c041c04, 0x0c041c14, 0x0c041c24, 0x0c04243e, 0x0c042c04, 0x0c0c0404, 0x0c0c0414, 0x0c0c0c0c, + 0x0c0c1404, 0x0c0c1414, 0x0c14040c, 0x0c14041c, 0x0c140c04, 0x0c140c14, 0x0c14140c, 0x0c141c04, + 0x0c143e14, 0x0c1c0404, 0x0c1c0414, 0x0c1c1404, 0x0c1c1c0c, 0x0c1c2434, 0x0c1c3434, 0x0c24040c, + 0x0c24042c, 0x0c242c04, 0x0c2c1404, 0x0c2c1424, 0x0c2c2434, 0x0c2c3e0c, 0x0c34042c, 0x0c3e1414, + 0x0c3e2404, 0x14040404, 0x14040414, 0x14040c0c, 0x14040c1c, 0x14041404, 0x14041414, 0x14041434, + 0x14041c0c, 0x14042414, 0x140c040c, 0x140c041c, 0x140c042c, 0x140c0c04, 0x140c0c14, 0x140c140c, + 0x140c1c04, 0x140c341c, 0x140c343e, 0x140c3e04, 0x14140404, 0x14140414, 0x14140c0c, 0x14140c3e, + 0x14141404, 0x14141414, 0x14141c3e, 0x14142404, 0x14142c2c, 0x141c040c, 0x141c0c04, 0x141c0c24, + 0x141c3e04, 0x141c3e24, 0x14241c2c, 0x14242c1c, 0x142c041c, 0x142c143e, 0x142c240c, 0x142c3e24, + 0x143e040c, 0x143e041c, 0x143e0c34, 0x143e242c, 0x1c04040c, 0x1c040c04, 0x1c040c14, 0x1c04140c, + 0x1c04141c, 0x1c042c04, 0x1c04342c, 0x1c043e14, 0x1c0c0404, 0x1c0c0414, 0x1c0c1404, 0x1c0c1c0c, + 0x1c0c2424, 0x1c0c2434, 0x1c14040c, 0x1c14041c, 0x1c140c04, 0x1c14142c, 0x1c142c14, 0x1c143e14, + 0x1c1c0c0c, 0x1c1c1c1c, 0x1c241c04, 0x1c24243e, 0x1c243e14, 0x1c2c0404, 0x1c2c0434, 0x1c2c1414, + 0x1c2c2c2c, 0x1c340c24, 0x1c341c34, 0x1c34341c, 0x1c3e1c1c, 0x1c3e3404, 0x24040424, 0x24040c3e, + 0x24041c2c, 0x24041c3e, 0x24042c1c, 0x24042c3e, 0x240c3e24, 0x24141404, 0x24141c3e, 0x24142404, + 0x24143404, 0x24143434, 0x241c043e, 0x241c242c, 0x24240424, 0x24242c0c, 0x24243424, 0x242c142c, + 0x242c241c, 0x242c3e04, 0x243e042c, 0x243e0c04, 0x243e0c14, 0x243e1c04, 0x2c040c14, 0x2c04240c, + 0x2c043e04, 0x2c0c0404, 0x2c0c0434, 0x2c0c1434, 0x2c0c2c2c, 0x2c140c24, 0x2c141c14, 0x2c143e14, + 0x2c1c0414, 0x2c1c2c1c, 0x2c240c04, 0x2c24141c, 0x2c24143e, 0x2c243e14, 0x2c2c0414, 0x2c2c1c0c, + 0x2c342c04, 0x2c3e1424, 0x2c3e2414, 0x34041424, 0x34042424, 0x34042434, 0x34043424, 0x340c140c, + 0x340c340c, 0x34140c3e, 0x34143424, 0x341c1c04, 0x341c1c34, 0x34242424, 0x342c042c, 0x342c2c14, + 0x34341c1c, 0x343e041c, 0x343e140c, 0x3e04041c, 0x3e04042c, 0x3e04043e, 0x3e040c04, 0x3e041c14, + 0x3e042c14, 0x3e0c1434, 0x3e0c2404, 0x3e140c14, 0x3e14242c, 0x3e142c14, 0x3e1c0404, 0x3e1c0c2c, + 0x3e1c1c1c, 0x3e1c3404, 0x3e24140c, 0x3e24240c, 0x3e2c0404, 0x3e2c0414, 0x3e2c1424, 0x3e341c04 +}; + +inline uint iq3_xxs_signs(uint code) { + return code | ((popcount(code) & 1u) << 7); +} diff --git a/ggml/src/ggml-opencl/kernels/lightning_indexer.cl b/ggml/src/ggml-opencl/kernels/lightning_indexer.cl new file mode 100644 index 000000000000..efd2f11652fd --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/lightning_indexer.cl @@ -0,0 +1,111 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#ifdef cl_khr_subgroup_shuffle +#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable +#endif + +kernel void kernel_lightning_indexer( + global const char * q, + ulong offset_q, + global const char * k, + ulong offset_k, + global const char * w, + ulong offset_w, + global const char * mask, + ulong offset_m, + global float * dst, + ulong offset_d, + int head_size, + int n_heads, + int n_tokens, + int n_keys, + int n_masks, + int type_k, + ulong nbq1, + ulong nbq2, + ulong nbq3, + ulong nbk2, + ulong nbk3, + ulong nbw1, + ulong nbw3, + ulong nbm1, + ulong nbm3, + int use_shuffle +) { + const int tid = get_local_id(0); + const int lane = tid & (use_shuffle ? 3 : 15); + const int key = use_shuffle ? get_group_id(0)*16 + tid/4 : get_group_id(0)*4 + tid/16; + const int token = get_group_id(1); + const int stream = get_group_id(2); + + q += offset_q + token*nbq2 + stream*nbq3; + k += offset_k + (ulong) key*nbk2 + stream*nbk3; + w += offset_w + token*nbw1 + stream*nbw3; + mask += offset_m + token*nbm1 + (stream % n_masks)*nbm3; + dst = (global float *) ((global char *) dst + offset_d); + +#ifdef cl_khr_subgroup_shuffle + if (use_shuffle) { + // Each group of four lanes keeps one key for all query heads. + float4 cached[8]; + #pragma unroll + for (int j = 0; j < 8; ++j) { + const int i = 4*(lane + j*4); + cached[j] = key < n_keys ? (type_k == 0 ? vload4(0, (global const float *) k + i) : convert_float4(vload4(0, (global const half *) k + i))) : (float4) (0.0f); + } + + float score = 0.0f; + for (int h = 0; h < n_heads; ++h) { + global const float * q_head = (global const float *) (q + h*nbq1); + float4 sum = (float4) (0.0f); + #pragma unroll + for (int j = 0; j < 8; ++j) { + sum = mad(vload4(0, q_head + 4*(lane + j*4)), cached[j], sum); + } + float value = sum.s0 + sum.s1 + sum.s2 + sum.s3; + value += sub_group_shuffle_xor(value, 2); + value += sub_group_shuffle_xor(value, 1); + if (lane == 0) { + score = mad(fmax(value, 0.0f), ((global const float *) w)[h], score); + } + } + if (lane == 0 && key < n_keys) { + dst[((ulong) stream*n_tokens + token)*n_keys + key] = score + (float) ((global const half *) mask)[key]; + } + return; + } +#endif + + local float sums[64]; + float score = 0.0f; + for (int h = 0; h < n_heads; ++h) { + global const float * q_head = (global const float *) (q + h*nbq1); + float sum = 0.0f; + if (key < n_keys) { + for (int i = lane; i < head_size; i += 16) { + float kv; + if (type_k == 0) { + kv = ((global const float *) k)[i]; + } else { + kv = (float) ((global const half *) k)[i]; + } + sum = mad(q_head[i], kv, sum); + } + } + sums[tid] = sum; + barrier(CLK_LOCAL_MEM_FENCE); + for (int stride = 8; stride > 0; stride /= 2) { + if (lane < stride) { + sums[tid] += sums[tid + stride]; + } + barrier(CLK_LOCAL_MEM_FENCE); + } + if (lane == 0) { + score = mad(fmax(sums[tid], 0.0f), ((global const float *) w)[h], score); + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + if (lane == 0 && key < n_keys) { + dst[((ulong) stream*n_tokens + token)*n_keys + key] = score + (float) ((global const half *) mask)[key]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/moe_add_id_glu.cl b/ggml/src/ggml-opencl/kernels/moe_add_id_glu.cl index 6a8e4fb17f18..df9919ec107d 100644 --- a/ggml/src/ggml-opencl/kernels/moe_add_id_glu.cl +++ b/ggml/src/ggml-opencl/kernels/moe_add_id_glu.cl @@ -57,13 +57,17 @@ kernel void kernel_add_id_add_id_swiglu_oai( global const float * g_row = (global const float *)(src_g + i1*nb01_g + i2*nb02_g); global const float * u_row = (global const float *)(src_u + i1*nb01_u + i2*nb02_u); - global const float * gb_row = (global const float *)(src_gb + i11*nb11_g); - global const float * ub_row = (global const float *)(src_ub + i11*nb11_u); global float * d_row = (global float *)(dst + i1*nbd1 + i2*nbd2); for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { - float x0 = g_row[i0] + gb_row[i0]; - float x1 = u_row[i0] + ub_row[i0]; + float x0 = g_row[i0]; + float x1 = u_row[i0]; + if (i11 != -1) { + global const float * gb_row = (global const float *)(src_gb + i11*nb11_g); + global const float * ub_row = (global const float *)(src_ub + i11*nb11_u); + x0 += gb_row[i0]; + x1 += ub_row[i0]; + } x0 = min(x0, limit); x1 = max(min(x1, limit), -limit); diff --git a/ggml/src/ggml-opencl/kernels/moe_combine.cl b/ggml/src/ggml-opencl/kernels/moe_combine.cl index acd08dbe66b3..cae7a7f2a980 100644 --- a/ggml/src/ggml-opencl/kernels/moe_combine.cl +++ b/ggml/src/ggml-opencl/kernels/moe_combine.cl @@ -42,8 +42,11 @@ __kernel void kernel_moe_combine_bias_f32( float4 acc = (float4)(0.0f); for (int e = 0; e < k; ++e) { const int i11 = *((__global const int *)(I + (ulong)e*sizeof(int))); - __global const float * Brow = (__global const float *)(B + (ulong)i11*nb_b1) + r4*4u; - const float4 v = vload4(0, E + (uint)e*e1) + vload4(0, Brow); + float4 v = vload4(0, E + (uint)e*e1); + if (i11 != -1) { + __global const float * Brow = (__global const float *)(B + (ulong)i11*nb_b1) + r4*4u; + v += vload4(0, Brow); + } acc = mad(v, (float4)(W[(uint)e*w1]), acc); } diff --git a/ggml/src/ggml-opencl/kernels/moe_sort_by_expert.cl b/ggml/src/ggml-opencl/kernels/moe_sort_by_expert.cl index d0f9e8c8772c..e8ac31af22d1 100644 --- a/ggml/src/ggml-opencl/kernels/moe_sort_by_expert.cl +++ b/ggml/src/ggml-opencl/kernels/moe_sort_by_expert.cl @@ -18,6 +18,9 @@ __kernel void kernel_moe_histogram( } int expert_id = input[n * n_experts + k]; + if (expert_id == -1) { // skipped slot, owned by no expert + return; + } atomic_inc(&hist[expert_id]); } @@ -63,6 +66,9 @@ __kernel void kernel_moe_scatter( } int val = input[n * n_experts + k]; + if (val == -1) { // skipped slot, owned by no expert + return; + } int local_slot = atomic_inc(&slot_counter[val]); diff --git a/ggml/src/ggml-opencl/kernels/mul_mat_id_utils.cl b/ggml/src/ggml-opencl/kernels/mul_mat_id_utils.cl new file mode 100644 index 000000000000..79ec211632a1 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mat_id_utils.cl @@ -0,0 +1,22 @@ +kernel void kernel_moe_zero_dst( + global const char * ids, + ulong offset_ids, + ulong nb_ids1, + global char * dst, + ulong offset_dst, + ulong nb1, + ulong nb2, + int ne0 +) { + const size_t i1 = get_group_id(0); + const size_t i2 = get_group_id(1); + const int expert = *((global const int *)(ids + offset_ids + i1*sizeof(int) + i2*nb_ids1)); + if (expert != -1) { + return; + } + + global float * row = (global float *)(dst + offset_dst + i1*nb1 + i2*nb2); + for (size_t i0 = get_local_id(2); i0 < (size_t)ne0; i0 += get_local_size(2)) { + row[i0] = 0.0f; + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl index 6982f8f514dd..eba1778afd2f 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl @@ -4,12 +4,20 @@ #define LOAD_VEC_B 4 #define BM 64 +#ifndef BN #define BN 64 +#endif #define BK 16 #define TM 4 +#ifndef TN #define TN 8 +#endif -kernel void kernel_mul_mm_f16_f32_l4_lm( +#ifndef KERNEL_NAME_LM +#define KERNEL_NAME_LM kernel_mul_mm_f16_f32_l4_lm +#endif + +kernel void KERNEL_NAME_LM( global half4 * src0, ulong offset0, global float4 * src1, @@ -93,7 +101,8 @@ kernel void kernel_mul_mm_f16_f32_l4_lm( } } - for (int l = 0; l < BN; l += loadstride_b) { + // BN=8 uses only the threads that load a column inside the tile. + for (int l = 0; loadc_b + l < BN; l += loadstride_b) { if (ic*BN + loadc_b + l < ne11) { const int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq1_m_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq1_m_f32_l4_lm.cl new file mode 100644 index 000000000000..192a6c69e47c --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq1_m_f32_l4_lm.cl @@ -0,0 +1,191 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq1_m { + uchar qs[QK_K/8]; + uchar qh[QK_K/16]; + uchar scales[QK_K/32]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq1_m_f32_l4_lm( + global uchar * src0_qs, + global uchar * src0_qh, + global ushort * src0_sc, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq1_m super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq1_m); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + global ushort * sc = src0_sc + 4*ib; + ushort u16 = (ushort)((sc[0] >> 12) | ((sc[1] >> 8) & 0x00f0) + | ((sc[2] >> 4) & 0x0f00) | (sc[3] & 0xf000)); + float dl = (float)as_half(u16) * (float)(2*((sc[ib32/2] >> (6*(ib32%2) + 3*(lg/2))) & 7) + 1); + uchar qhb = src0_qh[16*ib + 2*ib32 + lg/2]; + float dlt = (qhb & (0x08 << (4*(lg%2)))) ? -1.125f : -0.875f; + uint gi = (uint)src0_qs[32*ib + 4*ib32 + lg] | ((((uint)qhb >> (4*(lg%2))) & 7) << 8); + uint g = iq1_s_grid[gi]; + int sh = (j0 >> 2) * 4; + + float4 v1; + v1.s0 = dl * ((float)((g >> ( 0 + sh)) & 0xF) + dlt); + v1.s1 = dl * ((float)((g >> ( 8 + sh)) & 0xF) + dlt); + v1.s2 = dl * ((float)((g >> (16 + sh)) & 0xF) + dlt); + v1.s3 = dl * ((float)((g >> (24 + sh)) & 0xF) + dlt); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq1_s_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq1_s_f32_l4_lm.cl new file mode 100644 index 000000000000..fca4eeacea85 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq1_s_f32_l4_lm.cl @@ -0,0 +1,188 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq1_s { + half d; + uchar qs[QK_K/8]; + ushort qh[QK_K/32]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq1_s_f32_l4_lm( + global uchar * src0_qs, + global ushort * src0_qh, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq1_s super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq1_s); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + ushort qhb = src0_qh[8*ib + ib32]; + float dl = (float)src0_d[ib] * (float)(2*((qhb >> 12) & 7) + 1); + float dlt = (qhb & 0x8000) ? -1.125f : -0.875f; + uint gi = (uint)src0_qs[32*ib + 4*ib32 + lg] | ((((uint)qhb >> (3*lg)) & 7) << 8); + uint g = iq1_s_grid[gi]; + int sh = (j0 >> 2) * 4; + + float4 v1; + v1.s0 = dl * ((float)((g >> ( 0 + sh)) & 0xF) + dlt); + v1.s1 = dl * ((float)((g >> ( 8 + sh)) & 0xF) + dlt); + v1.s2 = dl * ((float)((g >> (16 + sh)) & 0xF) + dlt); + v1.s3 = dl * ((float)((g >> (24 + sh)) & 0xF) + dlt); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq2_s_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_s_f32_l4_lm.cl new file mode 100644 index 000000000000..f33f500a4c3f --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_s_f32_l4_lm.cl @@ -0,0 +1,191 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq2_s { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar scales[QK_K/32]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq2_s_f32_l4_lm( + global uchar * src0_qs, + global uchar * src0_sg, + global uchar * src0_qh, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq2_s super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq2_s); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + uchar scb = src0_sc[8*ib + ib32]; + float db = (float)src0_d[ib] * (0.5f + (float)((lg < 2) ? (scb & 0xf) : (scb >> 4))) * 0.25f; + + uint gi = (uint)src0_qs[32*ib + 4*ib32 + lg] | (((uint)src0_qh[8*ib + ib32] << (8-2*lg)) & 0x300); + uchar sg = src0_sg[32*ib + 4*ib32 + lg]; + uint g = iq2_s_grid[2*gi + (j0 >> 2)]; + + float4 v1; + v1.s0 = db * (float)((g >> 0) & 0xFF) * ((sg & (1 << (j0+0))) ? -1.f : 1.f); + v1.s1 = db * (float)((g >> 8) & 0xFF) * ((sg & (1 << (j0+1))) ? -1.f : 1.f); + v1.s2 = db * (float)((g >> 16) & 0xFF) * ((sg & (1 << (j0+2))) ? -1.f : 1.f); + v1.s3 = db * (float)((g >> 24) & 0xFF) * ((sg & (1 << (j0+3))) ? -1.f : 1.f); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xs_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xs_f32_l4_lm.cl new file mode 100644 index 000000000000..cdff38bc4e8e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xs_f32_l4_lm.cl @@ -0,0 +1,189 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq2_xs { + half d; + ushort qs[QK_K/8]; + uchar scales[QK_K/32]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq2_xs_f32_l4_lm( + global ushort * src0_qs, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq2_xs super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq2_xs); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + uchar scb = src0_sc[8*ib + ib32]; + float db = (float)src0_d[ib] * (0.5f + (float)((lg < 2) ? (scb & 0xf) : (scb >> 4))) * 0.25f; + + uint q = src0_qs[32*ib + 4*ib32 + lg]; + uint gi = q & 511u; + uint sg = iq2_xs_signs(q >> 9); + uint g = iq2_xs_grid[2*gi + (j0 >> 2)]; + + float4 v1; + v1.s0 = db * (float)((g >> 0) & 0xFF) * ((sg & (1 << (j0+0))) ? -1.f : 1.f); + v1.s1 = db * (float)((g >> 8) & 0xFF) * ((sg & (1 << (j0+1))) ? -1.f : 1.f); + v1.s2 = db * (float)((g >> 16) & 0xFF) * ((sg & (1 << (j0+2))) ? -1.f : 1.f); + v1.s3 = db * (float)((g >> 24) & 0xFF) * ((sg & (1 << (j0+3))) ? -1.f : 1.f); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xxs_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xxs_f32_l4_lm.cl new file mode 100644 index 000000000000..7a44038b8eea --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq2_xxs_f32_l4_lm.cl @@ -0,0 +1,187 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq2_xxs { + half d; + ushort qs[QK_K/8]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq2_xxs_f32_l4_lm( + global uchar * src0_qs, + global uint * src0_sas, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq2_xxs super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq2_xxs); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + uint aux = src0_sas[8*ib + ib32]; + float db = (float)src0_d[ib] * (0.5f + (float)(aux >> 28)) * 0.25f; + + uint gi = src0_qs[32*ib + 4*ib32 + lg]; + uint sg = iq2_xxs_signs((aux >> (7*lg)) & 127u); + uint g = iq2_xxs_grid[2*gi + (j0 >> 2)]; + + float4 v1; + v1.s0 = db * (float)((g >> 0) & 0xFF) * ((sg & (1 << (j0+0))) ? -1.f : 1.f); + v1.s1 = db * (float)((g >> 8) & 0xFF) * ((sg & (1 << (j0+1))) ? -1.f : 1.f); + v1.s2 = db * (float)((g >> 16) & 0xFF) * ((sg & (1 << (j0+2))) ? -1.f : 1.f); + v1.s3 = db * (float)((g >> 24) & 0xFF) * ((sg & (1 << (j0+3))) ? -1.f : 1.f); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq3_s_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq3_s_f32_l4_lm.cl new file mode 100644 index 000000000000..e75c296ac012 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq3_s_f32_l4_lm.cl @@ -0,0 +1,193 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq3_s { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar signs[QK_K/8]; + uchar scales[QK_K/64]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq3_s_f32_l4_lm( + global uchar * src0_qs, + global uchar * src0_sg, + global uchar * src0_qh, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq3_s super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq3_s); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + uchar scb = src0_sc[4*ib + ib32/2]; + float db = (float)src0_d[ib] * (float)(1 + 2*((scb >> (4*(ib32 & 1))) & 15)); + int which = j0 >> 2; + uint gi = (uint)src0_qs[64*ib + 8*ib32 + 2*lg + which] + | (((uint)src0_qh[8*ib + ib32] << (8 - 2*lg - which)) & 256); + uchar sg = src0_sg[32*ib + 4*ib32 + lg]; + uint g = iq3_s_grid[gi]; + + float4 v1; + v1.s0 = db * (float)((g >> 0) & 0xFF) * ((sg & (1 << (j0+0))) ? -1.f : 1.f); + v1.s1 = db * (float)((g >> 8) & 0xFF) * ((sg & (1 << (j0+1))) ? -1.f : 1.f); + v1.s2 = db * (float)((g >> 16) & 0xFF) * ((sg & (1 << (j0+2))) ? -1.f : 1.f); + v1.s3 = db * (float)((g >> 24) & 0xFF) * ((sg & (1 << (j0+3))) ? -1.f : 1.f); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_iq3_xxs_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_iq3_xxs_f32_l4_lm.cl new file mode 100644 index 000000000000..3c50d62303c6 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_iq3_xxs_f32_l4_lm.cl @@ -0,0 +1,187 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_iq3_xxs { + half d; + uchar qs[3*QK_K/8]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_iq3_xxs_f32_l4_lm( + global uchar * src0_qs, + global uint * src0_sas, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one iq3_xxs super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_iq3_xxs); + int e = idx % QK_K; + + int ib32 = e >> 5; + int rem = e & 31; + int lg = rem >> 3; + int j0 = rem & 7; + + uint aux = src0_sas[8*ib + ib32]; + float db = (float)src0_d[ib] * (0.5f + (float)(aux >> 28)) * 0.5f; + + uint gi = src0_qs[64*ib + 8*ib32 + 2*lg + (j0 >> 2)]; + uint sg = iq3_xxs_signs((aux >> (7*lg)) & 127u); + uint g = iq3_xxs_grid[gi]; + + float4 v1; + v1.s0 = db * (float)((g >> 0) & 0xFF) * ((sg & (1 << (j0+0))) ? -1.f : 1.f); + v1.s1 = db * (float)((g >> 8) & 0xFF) * ((sg & (1 << (j0+1))) ? -1.f : 1.f); + v1.s2 = db * (float)((g >> 16) & 0xFF) * ((sg & (1 << (j0+2))) ? -1.f : 1.f); + v1.s3 = db * (float)((g >> 24) & 0xFF) * ((sg & (1 << (j0+3))) ? -1.f : 1.f); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_q2_0_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_q2_0_f32_l4_lm.cl new file mode 100644 index 000000000000..673b70655464 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_q2_0_f32_l4_lm.cl @@ -0,0 +1,171 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK2_0 64 + +struct block_q2_0 { + half d; + uchar qs[16]; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 32 +#ifdef INTEL_GPU +#define TM 8 +#define TN 8 +#else +#define TM 4 +#define TN 8 +#endif + +kernel void kernel_mul_mm_q2_0_f32_l4_lm( + global uchar * src0_qs, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK2_0; + ib += offset0/sizeof(struct block_q2_0); + int e = idx % QK2_0; + + const uint q = src0_qs[16*ib + e/4]; + const int4 v = convert_int4(((uint4)(q) >> (uint4)(0, 2, 4, 6)) & (uint4)(3)) - (int4)(1); + const float4 v1 = (float)src0_d[ib] * convert_float4(v); + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_q2_k_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_q2_k_f32_l4_lm.cl new file mode 100644 index 000000000000..e192bdefb689 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_q2_k_f32_l4_lm.cl @@ -0,0 +1,203 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_q2_K { + uchar scales[QK_K/16]; + uchar qs[QK_K/4]; + half d; + half dmin; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#ifndef BK +#define BK 32 +#endif +#ifdef INTEL_GPU +#define TM 8 +#else +#define TM 4 +#endif +#define TN 8 + +#ifndef LM_HALF +#define LM_HALF 0 +#endif +#if LM_HALF +typedef half lm_st; +#define LM_LD4(p, i) convert_float4(vload4((i), (p))) +#else +typedef float lm_st; +#define LM_LD4(p, i) vload4((i), (p)) +#endif + +kernel void kernel_mul_mm_q2_k_f32_l4_lm( + global uchar * src0_qs, + global uchar * src0_sc, + global half * src0_dm, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local lm_st buf_a[BM * BK]; + local lm_st buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one q2_K super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float4 sums4[(TM/4) * TN]; + float4 cache_a4[TM/4]; + + for (int i = 0; i < (TM/4) * TN; i++) { + sums4[i] = (float4)(0.0f); + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_q2_K); + int e = idx % QK_K; + + // dequantize_row_q2_K walks 2 halves of 128, each as 4 shifts of + // 2 groups of 16. Recover that position from the element index. + int n = e >> 7; + int rem = e & 127; + int j = rem >> 5; + int s = (rem >> 4) & 1; + int l16 = rem & 15; + int isc = 8*n + 2*j + s; + int shift = 2*j; + + uchar sc = src0_sc[16*ib + isc]; + float d = (float)src0_dm[2*ib] * (float)(sc & 0xF); + float m = -(float)src0_dm[2*ib + 1] * (float)(sc >> 4); + + uchar4 q = vload4(0, src0_qs + 64*ib + 32*n + 16*s + l16); + float4 v1 = convert_float4((uchar4)((q.s0 >> shift) & 3, + (q.s1 >> shift) & 3, + (q.s2 >> shift) & 3, + (q.s3 >> shift) & 3)) * d + m; + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int a = 0; a < TM/4; a++) { + cache_a4[a] = LM_LD4(buf_a + (i) * BM + th_r * TM, a); + } + + for (int cc = 0; cc < TN; cc++) { + const float cache_b = buf_b[(i) * BN + th_c * TN + cc]; + for (int a = 0; a < TM/4; a++) { + const int sums_idx = cc*(TM/4) + a; + sums4[sums_idx] = mad(cache_a4[a], (float4)cache_b, sums4[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int a = 0; a < TM/4; a++) { + const float4 v = sums4[cc * (TM/4) + a]; + const float vs[4] = { v.s0, v.s1, v.s2, v.s3 }; + for (int k = 0; k < 4; k++) { + if (dr + 4*a + k < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + 4*a + k] = vs[k]; + } + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_q3_k_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_q3_k_f32_l4_lm.cl new file mode 100644 index 000000000000..da3997417e12 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_q3_k_f32_l4_lm.cl @@ -0,0 +1,219 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#define INTEL_GPU 1 +#endif + +#define QK_K 256 + +struct block_q3_K { + uchar hmask[QK_K/8]; + uchar qs[QK_K/4]; + uchar scales[12]; + half d; +}; + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#ifndef BK +#define BK 32 +#endif +#ifdef INTEL_GPU +#define TM 8 +#else +#define TM 4 +#endif +#define TN 8 + +#ifndef LM_HALF +#define LM_HALF 0 +#endif +#if LM_HALF +typedef half lm_st; +#define LM_LD4(p, i) convert_float4(vload4((i), (p))) +#else +typedef float lm_st; +#define LM_LD4(p, i) vload4((i), (p)) +#endif + +kernel void kernel_mul_mm_q3_k_f32_l4_lm( + global uchar * src0_qs, + global uchar * src0_hm, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float *)((global char*)dst + offsetd); + + local lm_st buf_a[BM * BK]; + local lm_st buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + // pos_a counts elements, not blocks - one q3_K super block holds QK_K of them + int pos_a = batch_idx_a * batch_stride_a + ir * BM * stride_a; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float4 sums4[(TM/4) * TN]; + float4 cache_a4[TM/4]; + + for (int i = 0; i < (TM/4) * TN; i++) { + sums4[i] = (float4)(0.0f); + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + if (ir*BM + loadc_a + l < ne01) { + int idx = pos_a + (loadc_a + l) * stride_a + loadr_a * LOAD_VEC_A; + int ib = idx / QK_K; + ib += offset0/sizeof(struct block_q3_K); + int e = idx % QK_K; + + // Only qs advances in the second half of a super-block. + int n = e >> 7; + int rem = e & 127; + int j = rem >> 5; + int s = (rem >> 4) & 1; + int l16 = rem & 15; + int is = 8*n + 2*j + s; + int shift = 2*j; + uchar m = (uchar)(1u << (4*n + j)); + + global ushort * a = (global ushort *)(src0_sc + 12*ib); + uint a0 = (uint)a[0] | ((uint)a[1] << 16); + uint a1 = (uint)a[2] | ((uint)a[3] << 16); + uint tmp = (uint)a[4] | ((uint)a[5] << 16); + + uint g = is >> 2; + uint w = (g & 1u) ? a1 : a0; + w = ((w >> ((g >> 1)*4)) & 0x0f0f0f0fu) | (((tmp >> (2*g)) & 0x03030303u) << 4); + + uint sc6 = (w >> (8*(is & 3))) & 0xFFu; + float dl = (float)src0_d[ib] * ((float)sc6 - 32.0f); + + uchar4 q = vload4(0, src0_qs + 64*ib + 32*n + 16*s + l16); + uchar4 hb = vload4(0, src0_hm + 32*ib + 16*s + l16); + + float4 qv = convert_float4((uchar4)((q.s0 >> shift) & 3, + (q.s1 >> shift) & 3, + (q.s2 >> shift) & 3, + (q.s3 >> shift) & 3)); + float4 hv = (float4)((hb.s0 & m) ? 0.f : 4.f, + (hb.s1 & m) ? 0.f : 4.f, + (hb.s2 & m) ? 0.f : 4.f, + (hb.s3 & m) ? 0.f : 4.f); + float4 v1 = (qv - hv) * dl; + + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = v1.s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = v1.s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = v1.s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = v1.s3; + } else { + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = 0.0f; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = 0.0f; + } + } + + for (int l = 0; l < BN; l += loadstride_b) { + if (ic*BN + loadc_b + l < ne11) { + int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } else { + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = 0.0f; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = 0.0f; + } + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int a = 0; a < TM/4; a++) { + cache_a4[a] = LM_LD4(buf_a + (i) * BM + th_r * TM, a); + } + + for (int cc = 0; cc < TN; cc++) { + const float cache_b = buf_b[(i) * BN + th_c * TN + cc]; + for (int a = 0; a < TM/4; a++) { + const int sums_idx = cc*(TM/4) + a; + sums4[sums_idx] = mad(cache_a4[a], (float4)cache_b, sums4[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const ulong offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int a = 0; a < TM/4; a++) { + const float4 v = sums4[cc * (TM/4) + a]; + const float vs[4] = { v.s0, v.s1, v.s2, v.s3 }; + for (int k = 0; k < 4; k++) { + if (dr + 4*a + k < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + 4*a + k] = vs[k]; + } + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl index d50bd1fc4285..4c0755e14f2b 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl @@ -172,6 +172,9 @@ kernel void kernel_mul_mv_id_mxfp4_f32( const int idx = get_group_id(2)%ne20; int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + if (i02 == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int i11 = idx % ne11; int i12 = iid1; diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl index f65e86ed6a24..962ddd76da26 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl @@ -101,6 +101,9 @@ kernel void kernel_mul_mv_id_mxfp4_f32_flat( const int idx = get_group_id(2) % ne20; uint i02 = ((global uint *) (src2 + offset2 + iid1 * nb21))[idx]; + if ((int)i02 == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int i11 = idx % ne11; diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_id_q4_0_f32_8x_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_id_q4_0_f32_8x_flat.cl index 7ccf41efbe91..13314689fa5f 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_id_q4_0_f32_8x_flat.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_id_q4_0_f32_8x_flat.cl @@ -267,6 +267,9 @@ kernel void kernel_mul_mv_id_q4_0_f32_8x_flat( const int idx = get_group_id(2)%ne20; const int i02 = ((global int *)(src2 + iid1*nb21))[idx]; + if (i02 == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } const int i11 = idx%ne11; const int i12 = iid1; diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl index f37e83ee8aa4..2c40a43f1ea3 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl @@ -73,6 +73,9 @@ kernel void kernel_mul_mv_id_q8_0_f32( int idx = get_group_id(2)%ne20; int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + if (i02 == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int i11_ = idx % ne11; int i12_ = iid1; diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl index fd3a0710f5cc..3b1b39b62430 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl @@ -72,6 +72,9 @@ kernel void kernel_mul_mv_id_q8_0_f32_flat( int idx = (int)get_group_id(2)%ne20; int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + if (i02 == -1) { // skipped slot, the dst row is zeroed by kernel_moe_zero_dst + return; + } int i11_ = idx % ne11; int i12_ = iid1; diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32.cl new file mode 100644 index 000000000000..9e1554dc74c3 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32.cl @@ -0,0 +1,149 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ1_M_DELTA 0.125f + +// no d field: the super block scale is 4 nibbles spread over scales[] +typedef struct { + uchar qs[QK_K/8]; + uchar qh[QK_K/16]; + uchar scales[QK_K/32]; +} block_iq1_m; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq1_m_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq1_m * x = (global block_iq1_m *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq1_m * xb = (global block_iq1_m *)(xrow + row*nb01); + + global ushort * sc = (global ushort *)xb->scales; + ushort u16 = (ushort)(((uint)sc[0] >> 12) | (((uint)sc[1] >> 8) & 0x00f0) + | (((uint)sc[2] >> 4) & 0x0f00) | ((uint)sc[3] & 0xf000)); + float dsuper = (float)as_half(u16); + + float acc = 0.f; + for (int il = 0; il < 4; ++il) { + int ib16 = 2*it + il/2; + float dl = dsuper * (float)(2*(((uint)sc[ib16/4] >> (3*(ib16%4))) & 7) + 1); + + uchar qhb = xb->qh[2*it + il/2]; + float dlt = (qhb & (0x08 << (4*(il%2)))) ? (-1.f - IQ1_M_DELTA) : (-1.f + IQ1_M_DELTA); + + uint gi = (uint)xb->qs[4*it+il] | ((((uint)qhb >> (4*(il%2))) & 7) << 8); + uint g = iq1_s_grid[gi]; + + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*il+j+0] * ((float)((g >> (8*j+0)) & 0xF) + dlt); + a += yl[8*il+j+4] * ((float)((g >> (8*j+4)) & 0xF) + dlt); + } + acc += dl * a; + } + + sumf[row] += acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32_flat.cl new file mode 100644 index 000000000000..3b5e18934a94 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_m_f32_flat.cl @@ -0,0 +1,148 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ1_M_DELTA 0.125f + +// no d field: the super block scale is 4 nibbles spread over scales[] +typedef struct { + uchar qs[QK_K/8]; + uchar qh[QK_K/16]; + uchar scales[QK_K/32]; +} block_iq1_m; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq1_m_f32_flat( + global uchar * src0_qs, + global uchar * src0_qh, + global ushort * src0_sc, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq1_m); + ulong row_stride = nb01/sizeof(block_iq1_m); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + global ushort * sc = src0_sc + 4*b; + ushort u16 = (ushort)(((uint)sc[0] >> 12) | (((uint)sc[1] >> 8) & 0x00f0) + | (((uint)sc[2] >> 4) & 0x0f00) | ((uint)sc[3] & 0xf000)); + float dsuper = (float)as_half(u16); + + float acc = 0.f; + for (int il = 0; il < 4; ++il) { + int ib16 = 2*it + il/2; + float dl = dsuper * (float)(2*(((uint)sc[ib16/4] >> (3*(ib16%4))) & 7) + 1); + + uchar qhb = src0_qh[16*b + 2*it + il/2]; + float dlt = (qhb & (0x08 << (4*(il%2)))) ? (-1.f - IQ1_M_DELTA) : (-1.f + IQ1_M_DELTA); + + uint gi = (uint)src0_qs[32*b + 4*it+il] | ((((uint)qhb >> (4*(il%2))) & 7) << 8); + uint g = iq1_s_grid[gi]; + + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*il+j+0] * ((float)((g >> (8*j+0)) & 0xF) + dlt); + a += yl[8*il+j+4] * ((float)((g >> (8*j+4)) & 0xF) + dlt); + } + acc += dl * a; + } + + sumf[row] += acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32.cl new file mode 100644 index 000000000000..46a6730724fb --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32.cl @@ -0,0 +1,140 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ1_S_DELTA 0.125f + +typedef struct { + half d; + uchar qs[QK_K/8]; + ushort qh[QK_K/32]; +} block_iq1_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq1_s_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq1_s * x = (global block_iq1_s *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq1_s * xb = (global block_iq1_s *)(xrow + row*nb01); + + ushort qhb = xb->qh[it]; + float dl = (float)xb->d * (float)(2*((qhb >> 12) & 7) + 1); + float dlt = (qhb & 0x8000) ? (-1.f - IQ1_S_DELTA) : (-1.f + IQ1_S_DELTA); + + global uchar * qsb = xb->qs + 4*it; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (uint)qsb[l] | ((((uint)qhb >> (3*l)) & 7) << 8); + uint g = iq1_s_grid[gi]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * ((float)((g >> (8*j+0)) & 0xF) + dlt); + acc += yl[8*l+j+4] * ((float)((g >> (8*j+4)) & 0xF) + dlt); + } + } + + sumf[row] += dl * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32_flat.cl new file mode 100644 index 000000000000..9aba05b9e580 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq1_s_f32_flat.cl @@ -0,0 +1,139 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ1_S_DELTA 0.125f + +typedef struct { + half d; + uchar qs[QK_K/8]; + ushort qh[QK_K/32]; +} block_iq1_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq1_s_f32_flat( + global uchar * src0_qs, + global ushort * src0_qh, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq1_s); + ulong row_stride = nb01/sizeof(block_iq1_s); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + ushort qhb = src0_qh[8*b + it]; + float dl = (float)src0_d[b] * (float)(2*((qhb >> 12) & 7) + 1); + float dlt = (qhb & 0x8000) ? (-1.f - IQ1_S_DELTA) : (-1.f + IQ1_S_DELTA); + + global uchar * qsb = src0_qs + 32*b + 4*it; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (uint)qsb[l] | ((((uint)qhb >> (3*l)) & 7) << 8); + uint g = iq1_s_grid[gi]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * ((float)((g >> (8*j+0)) & 0xF) + dlt); + acc += yl[8*l+j+4] * ((float)((g >> (8*j+4)) & 0xF) + dlt); + } + } + + sumf[row] += dl * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32.cl new file mode 100644 index 000000000000..43650972bde3 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32.cl @@ -0,0 +1,147 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +// qs holds 32 grid low bytes then 32 sign bytes +typedef struct { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar scales[QK_K/32]; +} block_iq2_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_s_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq2_s * x = (global block_iq2_s *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq2_s * xb = (global block_iq2_s *)(xrow + row*nb01); + + uchar scb = xb->scales[it]; + float dlo = (float)xb->d * (0.5f + (float)(scb & 0xf)) * 0.25f; + float dhi = (float)xb->d * (0.5f + (float)(scb >> 4)) * 0.25f; + + uchar qhb = xb->qh[it]; + global uchar * qsb = xb->qs + 4*it; + global uchar * sgb = xb->qs + 32 + 4*it; + + float alo = 0.f, ahi = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (uint)qsb[l] | (((uint)qhb << (8-2*l)) & 0x300); + uchar sg = sgb[l]; + uint lo = iq2_s_grid[2*gi+0]; + uint hi = iq2_s_grid[2*gi+1]; + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + a += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + if (l < 2) alo += a; else ahi += a; + } + + sumf[row] += dlo * alo + dhi * ahi; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32_flat.cl new file mode 100644 index 000000000000..94d3ffd6f523 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_s_f32_flat.cl @@ -0,0 +1,148 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +// qs holds 32 grid low bytes then 32 sign bytes +typedef struct { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar scales[QK_K/32]; +} block_iq2_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_s_f32_flat( + global uchar * src0_qs, + global uchar * src0_sg, + global uchar * src0_qh, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq2_s); + ulong row_stride = nb01/sizeof(block_iq2_s); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + uchar scb = src0_sc[8*b + it]; + float dlo = (float)src0_d[b] * (0.5f + (float)(scb & 0xf)) * 0.25f; + float dhi = (float)src0_d[b] * (0.5f + (float)(scb >> 4)) * 0.25f; + + uchar qhb = src0_qh[8*b + it]; + global uchar * qsb = src0_qs + 32*b + 4*it; + global uchar * sgb = src0_sg + 32*b + 4*it; + + float alo = 0.f, ahi = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (uint)qsb[l] | (((uint)qhb << (8-2*l)) & 0x300); + uchar sg = sgb[l]; + uint lo = iq2_s_grid[2*gi+0]; + uint hi = iq2_s_grid[2*gi+1]; + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + a += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + if (l < 2) alo += a; else ahi += a; + } + + sumf[row] += dlo * alo + dhi * ahi; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32.cl new file mode 100644 index 000000000000..264e8e8e2f94 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32.cl @@ -0,0 +1,143 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +typedef struct { + half d; + ushort qs[QK_K/8]; + uchar scales[QK_K/32]; +} block_iq2_xs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_xs_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq2_xs * x = (global block_iq2_xs *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq2_xs * xb = (global block_iq2_xs *)(xrow + row*nb01); + + uchar scb = xb->scales[it]; + float dlo = (float)xb->d * (0.5f + (float)(scb & 0xf)) * 0.25f; + float dhi = (float)xb->d * (0.5f + (float)(scb >> 4)) * 0.25f; + + global ushort * q16 = xb->qs + 4*it; + + float alo = 0.f, ahi = 0.f; + for (int l = 0; l < 4; ++l) { + ushort q = q16[l]; + uchar sg = iq2_xs_signs(q >> 9); + uint lo = iq2_xs_grid[2*(q & 511)+0]; + uint hi = iq2_xs_grid[2*(q & 511)+1]; + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + a += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + if (l < 2) alo += a; else ahi += a; + } + + sumf[row] += dlo * alo + dhi * ahi; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32_flat.cl new file mode 100644 index 000000000000..a699a0e9f40a --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xs_f32_flat.cl @@ -0,0 +1,142 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +typedef struct { + half d; + ushort qs[QK_K/8]; + uchar scales[QK_K/32]; +} block_iq2_xs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_xs_f32_flat( + global ushort * src0_qs, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq2_xs); + ulong row_stride = nb01/sizeof(block_iq2_xs); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + uchar scb = src0_sc[8*b + it]; + float dlo = (float)src0_d[b] * (0.5f + (float)(scb & 0xf)) * 0.25f; + float dhi = (float)src0_d[b] * (0.5f + (float)(scb >> 4)) * 0.25f; + + global ushort * q16 = src0_qs + 32*b + 4*it; + + float alo = 0.f, ahi = 0.f; + for (int l = 0; l < 4; ++l) { + ushort q = q16[l]; + uchar sg = iq2_xs_signs(q >> 9); + uint lo = iq2_xs_grid[2*(q & 511)+0]; + uint hi = iq2_xs_grid[2*(q & 511)+1]; + float a = 0.f; + for (int j = 0; j < 4; ++j) { + a += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + a += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + if (l < 2) alo += a; else ahi += a; + } + + sumf[row] += dlo * alo + dhi * ahi; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32.cl new file mode 100644 index 000000000000..7d4595086bf1 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32.cl @@ -0,0 +1,140 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +typedef struct { + half d; + ushort qs[QK_K/8]; +} block_iq2_xxs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_xxs_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq2_xxs * x = (global block_iq2_xxs *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq2_xxs * xb = (global block_iq2_xxs *)(xrow + row*nb01); + + global ushort * q16 = xb->qs + 4*it; + uint a0 = (uint)q16[0] | ((uint)q16[1] << 16); + uint a1 = (uint)q16[2] | ((uint)q16[3] << 16); + + float db = (float)xb->d * (0.5f + (float)(a1 >> 28)) * 0.25f; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (a0 >> (8*l)) & 0xFF; + uchar sg = iq2_xxs_signs((a1 >> (7*l)) & 127); + uint lo = iq2_xxs_grid[2*gi+0]; + uint hi = iq2_xxs_grid[2*gi+1]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + acc += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32_flat.cl new file mode 100644 index 000000000000..4d9b984160d2 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq2_xxs_f32_flat.cl @@ -0,0 +1,137 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +typedef struct { + half d; + ushort qs[QK_K/8]; +} block_iq2_xxs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq2_xxs_f32_flat( + global uchar * src0_qs, + global uint * src0_sas, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq2_xxs); + ulong row_stride = nb01/sizeof(block_iq2_xxs); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + uint a0 = as_uint(vload4(8*b + it, src0_qs)); + uint a1 = src0_sas[8*b + it]; + + float db = (float)src0_d[b] * (0.5f + (float)(a1 >> 28)) * 0.25f; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint gi = (a0 >> (8*l)) & 0xFF; + uchar sg = iq2_xxs_signs((a1 >> (7*l)) & 127); + uint lo = iq2_xxs_grid[2*gi+0]; + uint hi = iq2_xxs_grid[2*gi+1]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * (float)((lo >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + acc += yl[8*l+j+4] * (float)((hi >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32.cl new file mode 100644 index 000000000000..0d9b67b4d1b6 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32.cl @@ -0,0 +1,146 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ3_S_N_SCALE (QK_K/64) + +typedef struct { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar signs[QK_K/8]; + uchar scales[IQ3_S_N_SCALE]; +} block_iq3_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq3_s_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq3_s * x = (global block_iq3_s *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq3_s * xb = (global block_iq3_s *)(xrow + row*nb01); + + uchar nib = (it & 1) ? (xb->scales[it >> 1] >> 4) : (xb->scales[it >> 1] & 0xf); + float db = (float)xb->d * (float)(1 + 2*nib); + + uchar qhb = xb->qh[it]; + global uchar * qsb = xb->qs + 8*it; + global uchar * sgb = xb->signs + 4*it; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint i1 = (uint)qsb[2*l+0] | (((uint)qhb << (8-2*l)) & 256); + uint i2 = (uint)qsb[2*l+1] | (((uint)qhb << (7-2*l)) & 256); + uint g1 = iq3_s_grid[i1]; + uint g2 = iq3_s_grid[i2]; + uchar sg = sgb[l]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * (float)((g1 >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + acc += yl[8*l+j+4] * (float)((g2 >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32_flat.cl new file mode 100644 index 000000000000..0208a53c3bca --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_s_f32_flat.cl @@ -0,0 +1,147 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 +#define IQ3_S_N_SCALE (QK_K/64) + +typedef struct { + half d; + uchar qs[QK_K/4]; + uchar qh[QK_K/32]; + uchar signs[QK_K/8]; + uchar scales[IQ3_S_N_SCALE]; +} block_iq3_s; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq3_s_f32_flat( + global uchar * src0_qs, + global uchar * src0_sg, + global uchar * src0_qh, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq3_s); + ulong row_stride = nb01/sizeof(block_iq3_s); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + uchar nib = (it & 1) ? (src0_sc[4*b + (it >> 1)] >> 4) : (src0_sc[4*b + (it >> 1)] & 0xf); + float db = (float)src0_d[b] * (float)(1 + 2*nib); + + uchar qhb = src0_qh[8*b + it]; + global uchar * qsb = src0_qs + 64*b + 8*it; + global uchar * sgb = src0_sg + 32*b + 4*it; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uint i1 = (uint)qsb[2*l+0] | (((uint)qhb << (8-2*l)) & 256); + uint i2 = (uint)qsb[2*l+1] | (((uint)qhb << (7-2*l)) & 256); + uint g1 = iq3_s_grid[i1]; + uint g2 = iq3_s_grid[i2]; + uchar sg = sgb[l]; + for (int j = 0; j < 4; ++j) { + acc += yl[8*l+j+0] * (float)((g1 >> (8*j)) & 0xFF) * ((sg & (1 << j)) ? -1.f : 1.f); + acc += yl[8*l+j+4] * (float)((g2 >> (8*j)) & 0xFF) * ((sg & (1 << (j+4))) ? -1.f : 1.f); + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32.cl new file mode 100644 index 000000000000..8355621d1ed8 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32.cl @@ -0,0 +1,145 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +// d, then 64 grid index bytes, then 8 uint32 of packed scale+signs +typedef struct { + half d; + uchar qs[3*QK_K/8]; +} block_iq3_xxs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq3_xxs_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_iq3_xxs * x = (global block_iq3_xxs *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_iq3_xxs * xb = (global block_iq3_xxs *)(xrow + row*nb01); + + global uchar * qs = xb->qs + 8*it; + + // Blocks are 98 bytes, so packed signs are only 2-byte aligned. + global ushort * sw = (global ushort *)(xb->qs + 64 + 4*it); + uint aux32 = (uint)sw[0] | ((uint)sw[1] << 16); + + float db = (float)xb->d * (0.5f + (float)(aux32 >> 28)) * 0.5f; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uchar signs = iq3_xxs_signs((aux32 >> (7*l)) & 127u); + uint g1 = iq3_xxs_grid[qs[2*l+0]]; + uint g2 = iq3_xxs_grid[qs[2*l+1]]; + + for (int j = 0; j < 4; ++j) { + float s1 = (signs & (1 << j)) ? -1.f : 1.f; + float s2 = (signs & (1 << (j+4))) ? -1.f : 1.f; + acc += yl[8*l+j+0] * (float)((g1 >> (8*j)) & 0xFF) * s1; + acc += yl[8*l+j+4] * (float)((g2 >> (8*j)) & 0xFF) * s2; + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32_flat.cl new file mode 100644 index 000000000000..974daf85915e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_iq3_xxs_f32_flat.cl @@ -0,0 +1,142 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_K 256 + +// d, then 64 grid index bytes, then 8 uint32 of packed scale+signs +typedef struct { + half d; + uchar qs[3*QK_K/8]; +} block_iq3_xxs; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 16 +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, one 32 element sub block each +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_iq3_xxs_f32_flat( + global uchar * src0_qs, + global uint * src0_sas, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // sub block inside the super block + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_iq3_xxs); + ulong row_stride = nb01/sizeof(block_iq3_xxs); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 32 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 32; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + global uchar * qs = src0_qs + 64*b + 8*it; + + uint aux32 = src0_sas[8*b + it]; + + float db = (float)src0_d[b] * (0.5f + (float)(aux32 >> 28)) * 0.5f; + + float acc = 0.f; + for (int l = 0; l < 4; ++l) { + uchar signs = iq3_xxs_signs((aux32 >> (7*l)) & 127u); + uint g1 = iq3_xxs_grid[qs[2*l+0]]; + uint g2 = iq3_xxs_grid[qs[2*l+1]]; + + for (int j = 0; j < 4; ++j) { + float s1 = (signs & (1 << j)) ? -1.f : 1.f; + float s2 = (signs & (1 << (j+4))) ? -1.f : 1.f; + acc += yl[8*l+j+0] * (float)((g1 >> (8*j)) & 0xFF) * s1; + acc += yl[8*l+j+4] * (float)((g2 >> (8*j)) & 0xFF) * s2; + } + } + + sumf[row] += db * acc; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl index 3d5a923eee0d..2e31831ca4c3 100644 --- a/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl +++ b/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl @@ -132,7 +132,7 @@ kernel void kernel_mul_mv_mxfp4_f32_flat( global float4 * y4 = (global float4 *)yb; #pragma unroll - for (short row = 0; row < N_R0_MXFP4; row++) { + for (short row = 0; row < N_R0_MXFP4 && first_row + row < ne0; row++) { uchar xb_e = x_e[row * nb + ib]; #ifdef SRC0Q_IMG ushort4 xb_q = as_ushort4(read_imageui(src0_q, (offset_q + row * nb + ib) * 2 + it).xy); diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32.cl new file mode 100644 index 000000000000..1be4f54305ff --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32.cl @@ -0,0 +1,134 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK2_0 64 + +// 00=-1, 01=0, 10=+1, 11=+2 +typedef struct { + half d; + uchar qs[QK2_0/4]; +} block_q2_0; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 4 threads cover one block +#define BLOCK_STRIDE (N_SIMDWIDTH/4) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q2_0_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/4; // block index + int it = get_sub_group_local_id()%4; // part of the block + + int nb = ne00/QK2_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_q2_0 * x = (global block_q2_0 *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[16]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK2_0 + 16 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 16; ++i) { + yl[i] = y4[i]; + } + + global char * xrow = (global char *)(x + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + global block_q2_0 * xb = (global block_q2_0 *)(xrow + row*nb01); + + global uchar * q = xb->qs + 4*it; + + float acc = 0.f; + for (int i = 0; i < 4; ++i) { + uchar b = q[i]; + acc += yl[4*i+0] * (float)(((b >> 0) & 3) - 1); + acc += yl[4*i+1] * (float)(((b >> 2) & 3) - 1); + acc += yl[4*i+2] * (float)(((b >> 4) & 3) - 1); + acc += yl[4*i+3] * (float)(((b >> 6) & 3) - 1); + } + + sumf[row] += (float)xb->d * acc; + } + + y4 += BLOCK_STRIDE * QK2_0; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32_flat.cl new file mode 100644 index 000000000000..7fd8899d234e --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q2_0_f32_flat.cl @@ -0,0 +1,132 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK2_0 64 + +// 00=-1, 01=0, 10=+1, 11=+2 +typedef struct { + half d; + uchar qs[QK2_0/4]; +} block_q2_0; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 4 threads cover one block +#define BLOCK_STRIDE (N_SIMDWIDTH/4) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q2_0_f32_flat( + global uchar * src0_qs, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/4; // block index + int it = get_sub_group_local_id()%4; // part of the block + + int nb = ne00/QK2_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_q2_0); + ulong row_stride = nb01/sizeof(block_q2_0); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[16]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK2_0 + 16 * it; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + for (int i = 0; i < 16; ++i) { + yl[i] = y4[i]; + } + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + const ulong b = offset_src0 + ib + row*row_stride; + + global uchar * q = src0_qs + 16*b + 4*it; + + float acc = 0.f; + for (int i = 0; i < 4; ++i) { + uchar b = q[i]; + acc += yl[4*i+0] * (float)(((b >> 0) & 3) - 1); + acc += yl[4*i+1] * (float)(((b >> 2) & 3) - 1); + acc += yl[4*i+2] * (float)(((b >> 4) & 3) - 1); + acc += yl[4*i+3] * (float)(((b >> 6) & 3) - 1); + } + + sumf[row] += (float)src0_d[b] * acc; + } + + y4 += BLOCK_STRIDE * QK2_0; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32.cl new file mode 100644 index 000000000000..7f5328136d56 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32.cl @@ -0,0 +1,161 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +//------------------------------------------------------------------------------ +// block_q2_K +//------------------------------------------------------------------------------ +#define QK_K 256 + +// 16 blocks of 16 elements each +// weight is represented as x = a * q + b +typedef struct { + uchar scales[QK_K/16]; // scales and mins, quantized with 4 bits + uchar qs[QK_K/4]; // 2-bit quants + half d; // super-block scale for quantized scales + half dmin; // super-block scale for quantized mins +} block_q2_K; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// number of (super) blocks each subgroup processes +// 8 threads cover one super block, so a wave covers N_SIMDWIDTH/8 of them +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q2_K_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // block index (inside super block) + int iq = it/4; // 0 or 1 - first or second half of the super block + int ir = it%4; // 0...3 - block index in the half super block + int is = (8*ir)/16; // 0 or 1 - scale pair + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_q2_K * x = (global block_q2_K *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 128 * iq + 8 * ir; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + float4 sumy = {0.f, 0.f, 0.f, 0.f}; + for (int i = 0; i < 8; ++i) { + yl[i+ 0] = y4[i+ 0]; sumy.s0 += yl[i+ 0]; + yl[i+ 8] = y4[i+32]; sumy.s1 += yl[i+ 8]; + yl[i+16] = y4[i+64]; sumy.s2 += yl[i+16]; + yl[i+24] = y4[i+96]; sumy.s3 += yl[i+24]; + } + + global uchar * sc = (global uchar *)x[ib].scales + 8*iq + is; + global ushort * qs = (global ushort *)x[ib].qs + 16 * iq + 4 * ir; + global half * dh = &x[ib].d; + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + float4 acc1 = {0.f, 0.f, 0.f, 0.f}; + float4 acc2 = {0.f, 0.f, 0.f, 0.f}; + for (int i = 0; i < 8; i += 2) { + acc1.s0 += yl[i+ 0] * (qs[i/2] & 0x0003); + acc2.s0 += yl[i+ 1] * (qs[i/2] & 0x0300); + acc1.s1 += yl[i+ 8] * (qs[i/2] & 0x000c); + acc2.s1 += yl[i+ 9] * (qs[i/2] & 0x0c00); + acc1.s2 += yl[i+16] * (qs[i/2] & 0x0030); + acc2.s2 += yl[i+17] * (qs[i/2] & 0x3000); + acc1.s3 += yl[i+24] * (qs[i/2] & 0x00c0); + acc2.s3 += yl[i+25] * (qs[i/2] & 0xc000); + } + + float dall = dh[0]; + float dmin = dh[1] * 1.f/16.f; + sumf[row] += dall * ((acc1.s0 + 1.f/256.f * acc2.s0) * (sc[0] & 0xF) * 1.f/ 1.f + + (acc1.s1 + 1.f/256.f * acc2.s1) * (sc[2] & 0xF) * 1.f/ 4.f + + (acc1.s2 + 1.f/256.f * acc2.s2) * (sc[4] & 0xF) * 1.f/16.f + + (acc1.s3 + 1.f/256.f * acc2.s3) * (sc[6] & 0xF) * 1.f/64.f) - + dmin * (sumy.s0 * (sc[0] & 0xF0) + sumy.s1 * (sc[2] & 0xF0) + + sumy.s2 * (sc[4] & 0xF0) + sumy.s3 * (sc[6] & 0xF0)); + + qs += nb01/2; + sc += nb01; + dh += nb01/2; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32_flat.cl new file mode 100644 index 000000000000..c993abebedf5 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q2_k_f32_flat.cl @@ -0,0 +1,162 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +//------------------------------------------------------------------------------ +// struct block_q2_K +//------------------------------------------------------------------------------ +#define QK_K 256 + +// 16 blocks of 16 elements each +// weight is represented as x = a * q + b +struct block_q2_K { + uchar scales[QK_K/16]; // scales and mins, quantized with 4 bits + uchar qs[QK_K/4]; // 2-bit quants + half d; // super-block scale for quantized scales + half dmin; // super-block scale for quantized mins +}; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 4 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 4 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// number of (super) blocks each subgroup processes +// 8 threads cover one super block, so a wave covers N_SIMDWIDTH/8 of them +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q2_K_f32_flat( + global uchar * src0_qs, + global uchar * src0_sc, + global half * src0_dm, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int ix = get_sub_group_local_id()/8; // super block index + int it = get_sub_group_local_id()%8; // block index (inside super block) + int iq = it/4; // 0 or 1 - first or second half of the super block + int ir = it%4; // 0...3 - block index in the half super block + int is = (8*ir)/16; // 0 or 1 - scale pair + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(struct block_q2_K); + ulong row_stride = nb01/sizeof(struct block_q2_K); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * y = (global float *) (src1 + offset_src1); + + float yl[32]; + float sumf[N_DST] = {0.f}; + float all_sum; + + global float * y4 = y + ix * QK_K + 128 * iq + 8 * ir; + + for (int ib = ix; ib < nb; ib += BLOCK_STRIDE) { + float4 sumy = {0.f, 0.f, 0.f, 0.f}; + for (int i = 0; i < 8; ++i) { + yl[i+ 0] = y4[i+ 0]; sumy.s0 += yl[i+ 0]; + yl[i+ 8] = y4[i+32]; sumy.s1 += yl[i+ 8]; + yl[i+16] = y4[i+64]; sumy.s2 += yl[i+16]; + yl[i+24] = y4[i+96]; sumy.s3 += yl[i+24]; + } + + global uchar * sc = (src0_sc + 16*(offset_src0 + ib)) + 8*iq + is; + global ushort * qs = (global ushort *)(src0_qs + 64*(offset_src0 + ib)) + 16 * iq + 4 * ir; + global half * dh = src0_dm + 2*(offset_src0 + ib); + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; row++) { + float4 acc1 = {0.f, 0.f, 0.f, 0.f}; + float4 acc2 = {0.f, 0.f, 0.f, 0.f}; + for (int i = 0; i < 8; i += 2) { + acc1.s0 += yl[i+ 0] * (qs[i/2] & 0x0003); + acc2.s0 += yl[i+ 1] * (qs[i/2] & 0x0300); + acc1.s1 += yl[i+ 8] * (qs[i/2] & 0x000c); + acc2.s1 += yl[i+ 9] * (qs[i/2] & 0x0c00); + acc1.s2 += yl[i+16] * (qs[i/2] & 0x0030); + acc2.s2 += yl[i+17] * (qs[i/2] & 0x3000); + acc1.s3 += yl[i+24] * (qs[i/2] & 0x00c0); + acc2.s3 += yl[i+25] * (qs[i/2] & 0xc000); + } + + float dall = dh[0]; + float dmin = dh[1] * 1.f/16.f; + sumf[row] += dall * ((acc1.s0 + 1.f/256.f * acc2.s0) * (sc[0] & 0xF) * 1.f/ 1.f + + (acc1.s1 + 1.f/256.f * acc2.s1) * (sc[2] & 0xF) * 1.f/ 4.f + + (acc1.s2 + 1.f/256.f * acc2.s2) * (sc[4] & 0xF) * 1.f/16.f + + (acc1.s3 + 1.f/256.f * acc2.s3) * (sc[6] & 0xF) * 1.f/64.f) - + dmin * (sumy.s0 * (sc[0] & 0xF0) + sumy.s1 * (sc[2] & 0xF0) + + sumy.s2 * (sc[4] & 0xF0) + sumy.s3 * (sc[6] & 0xF0)); + + qs += row_stride*32; + sc += row_stride*16; + dh += row_stride*2; + } + + y4 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add(sumf[row]); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32.cl new file mode 100644 index 000000000000..77c70f4ac4ae --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32.cl @@ -0,0 +1,197 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +//------------------------------------------------------------------------------ +// block_q3_K +//------------------------------------------------------------------------------ +#define QK_K 256 + +// 16 blocks of 16 elements each +// weight is represented as x = a * q +typedef struct { + uchar hmask[QK_K/8]; // quants - high bit + uchar qs[QK_K/4]; // quants - low 2 bits + uchar scales[12]; // scales, quantized with 6 bits + half d; // super-block scale +} block_q3_K; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 2 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 2 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, so a wave covers N_SIMDWIDTH/8 of them +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q3_K_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_q3_K * x = (global block_q3_K *) (src0 + offset_src0); + global float * yy = (global float *) (src1 + offset_src1); + + float yl[32]; + + // Eight lanes cover one super-block. + int ix = get_sub_group_local_id() % BLOCK_STRIDE; + int tid = get_sub_group_local_id() / BLOCK_STRIDE; + + int ip = tid/4; // 0 or 1 + int il = 2*((tid%4)/2); // 0 or 2 + int ir = tid%2; + int l0 = 8*ir; + + // Shift the masks instead of indexing private arrays to avoid spills. + ushort4 hm = (ushort4)(0x0001, 0x0100, 0x0002, 0x0200) << (ushort4)(2*(2*ip + il/2)); + int4 qm = (int4) (0x0003, 0x0300, 0x000c, 0x0c00) << (int4) (4*(il/2)); + + int shift = 2*il; + + float v1 = il == 0 ? 4.f : 64.f; + float v2 = 4.f * v1; + + int s_shift1 = 4*ip; + int s_shift2 = s_shift1 + il; + + int q_offset = 32*ip + l0; + int y_offset = 128*ip + 32*il + l0; + + global float * y1 = yy + ix*QK_K + y_offset; + + float sumf1[N_DST] = {0.f}; + float sumf2[N_DST] = {0.f}; + float all_sum; + + for (int i = ix; i < nb; i += BLOCK_STRIDE) { + for (int l = 0; l < 8; ++l) { + yl[l+ 0] = y1[l+ 0]; + yl[l+ 8] = y1[l+16]; + yl[l+16] = y1[l+32]; + yl[l+24] = y1[l+48]; + } + + global ushort * q = (global ushort *)(x[i].qs + q_offset); + global ushort * h = (global ushort *)(x[i].hmask + l0); + global ushort * a = (global ushort *)(x[i].scales); + global half * dh = &x[i].d; + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; ++row) { + float d_all = dh[0]; + + uint s32 = (uint)a[4] | ((uint)a[5] << 16); + uint aux32 = ((s32 >> s_shift2) << 4) & 0x30303030u; + s32 = (uint)a[il+0] | ((uint)a[il+1] << 16); + s32 = ((s32 >> s_shift1) & 0x0f0f0f0fu) | aux32; + char4 sc = as_char4(s32); + + float s1 = 0, s2 = 0, s3 = 0, s4 = 0, s5 = 0, s6 = 0; + for (int l = 0; l < 8; l += 2) { + int qs = q[l/2]; + s1 += yl[l+0] * (qs & qm.s0); + s2 += yl[l+1] * (qs & qm.s1); + s3 += ((h[l/2] & hm.s0) ? 0.f : yl[l+0]) + ((h[l/2] & hm.s1) ? 0.f : yl[l+1]); + s4 += yl[l+16] * (qs & qm.s2); + s5 += yl[l+17] * (qs & qm.s3); + s6 += ((h[l/2] & hm.s2) ? 0.f : yl[l+16]) + ((h[l/2] & hm.s3) ? 0.f : yl[l+17]); + } + float d1 = d_all * (s1 + 1.f/256.f * s2 - s3*v1); + float d2 = d_all * (s4 + 1.f/256.f * s5 - s6*v2); + sumf1[row] += d1 * (sc.s0 - 32); + sumf2[row] += d2 * (sc.s2 - 32); + + s1 = s2 = s3 = s4 = s5 = s6 = 0; + for (int l = 0; l < 8; l += 2) { + int qs = q[l/2+8]; + s1 += yl[l+8] * (qs & qm.s0); + s2 += yl[l+9] * (qs & qm.s1); + s3 += ((h[l/2+8] & hm.s0) ? 0.f : yl[l+8]) + ((h[l/2+8] & hm.s1) ? 0.f : yl[l+9]); + s4 += yl[l+24] * (qs & qm.s2); + s5 += yl[l+25] * (qs & qm.s3); + s6 += ((h[l/2+8] & hm.s2) ? 0.f : yl[l+24]) + ((h[l/2+8] & hm.s3) ? 0.f : yl[l+25]); + } + d1 = d_all * (s1 + 1.f/256.f * s2 - s3*v1); + d2 = d_all * (s4 + 1.f/256.f * s5 - s6*v2); + sumf1[row] += d1 * (sc.s1 - 32); + sumf2[row] += d2 * (sc.s3 - 32); + + q += nb01/2; + h += nb01/2; + a += nb01/2; + dh += nb01/2; + } + + y1 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add((sumf1[row] + 0.25f * sumf2[row]) / (1 << shift)); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32_flat.cl b/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32_flat.cl new file mode 100644 index 000000000000..c2c2219d8a68 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mv_q3_k_f32_flat.cl @@ -0,0 +1,199 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +//------------------------------------------------------------------------------ +// block_q3_K +//------------------------------------------------------------------------------ +#define QK_K 256 + +// 16 blocks of 16 elements each +// weight is represented as x = a * q +typedef struct { + uchar hmask[QK_K/8]; // quants - high bit + uchar qs[QK_K/4]; // quants - low 2 bits + uchar scales[12]; // scales, quantized with 6 bits + half d; // super-block scale +} block_q3_K; + +#undef N_DST +#undef N_SIMDGROUP +#undef N_SIMDWIDTH + +#ifdef INTEL_GPU +#define N_DST 2 // number of rows each SIMD group works on +#define N_SIMDGROUP 1 // number of SIMD groups in a thread group +#define N_SIMDWIDTH 16 // SIMD group size +#elif defined (ADRENO_GPU) +#define N_DST 2 +#define N_SIMDGROUP 1 +#define N_SIMDWIDTH 64 +#endif + +#undef BLOCK_STRIDE +// 8 threads cover one super block, so a wave covers N_SIMDWIDTH/8 of them +#define BLOCK_STRIDE (N_SIMDWIDTH/8) + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q3_K_f32_flat( + global uchar * src0_qs, + global uchar * src0_hm, + global uchar * src0_sc, + global half * src0_d, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int nb = ne00/QK_K; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + int first_row = (r0 * N_SIMDGROUP + get_sub_group_id()) * N_DST; + + int i12 = im%ne12; + int i13 = im/ne12; + + ulong offset_src0 = (offset0 + first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03)/sizeof(block_q3_K); + ulong row_stride = nb01/sizeof(block_q3_K); + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global float * yy = (global float *) (src1 + offset_src1); + + float yl[32]; + + // Eight lanes cover one super-block. + int ix = get_sub_group_local_id() % BLOCK_STRIDE; + int tid = get_sub_group_local_id() / BLOCK_STRIDE; + + int ip = tid/4; // 0 or 1 + int il = 2*((tid%4)/2); // 0 or 2 + int ir = tid%2; + int l0 = 8*ir; + + // Shift the masks instead of indexing private arrays to avoid spills. + ushort4 hm = (ushort4)(0x0001, 0x0100, 0x0002, 0x0200) << (ushort4)(2*(2*ip + il/2)); + int4 qm = (int4) (0x0003, 0x0300, 0x000c, 0x0c00) << (int4) (4*(il/2)); + + int shift = 2*il; + + float v1 = il == 0 ? 4.f : 64.f; + float v2 = 4.f * v1; + + int s_shift1 = 4*ip; + int s_shift2 = s_shift1 + il; + + int q_offset = 32*ip + l0; + int y_offset = 128*ip + 32*il + l0; + + global float * y1 = yy + ix*QK_K + y_offset; + + float sumf1[N_DST] = {0.f}; + float sumf2[N_DST] = {0.f}; + float all_sum; + + for (int i = ix; i < nb; i += BLOCK_STRIDE) { + for (int l = 0; l < 8; ++l) { + yl[l+ 0] = y1[l+ 0]; + yl[l+ 8] = y1[l+16]; + yl[l+16] = y1[l+32]; + yl[l+24] = y1[l+48]; + } + + global ushort * q = (global ushort *)(src0_qs + 64*(offset_src0 + i) + q_offset); + global ushort * h = (global ushort *)(src0_hm + 32*(offset_src0 + i) + l0); + global ushort * a = (global ushort *)(src0_sc + 12*(offset_src0 + i)); + global half * dh = src0_d + offset_src0 + i; + + // only ne01 output rows exist; reading past them can pull in an inf scale + for (int row = 0; row < N_DST && first_row + row < ne01; ++row) { + float d_all = dh[0]; + + uint s32 = (uint)a[4] | ((uint)a[5] << 16); + uint aux32 = ((s32 >> s_shift2) << 4) & 0x30303030u; + s32 = (uint)a[il+0] | ((uint)a[il+1] << 16); + s32 = ((s32 >> s_shift1) & 0x0f0f0f0fu) | aux32; + char4 sc = as_char4(s32); + + float s1 = 0, s2 = 0, s3 = 0, s4 = 0, s5 = 0, s6 = 0; + for (int l = 0; l < 8; l += 2) { + int qs = q[l/2]; + s1 += yl[l+0] * (qs & qm.s0); + s2 += yl[l+1] * (qs & qm.s1); + s3 += ((h[l/2] & hm.s0) ? 0.f : yl[l+0]) + ((h[l/2] & hm.s1) ? 0.f : yl[l+1]); + s4 += yl[l+16] * (qs & qm.s2); + s5 += yl[l+17] * (qs & qm.s3); + s6 += ((h[l/2] & hm.s2) ? 0.f : yl[l+16]) + ((h[l/2] & hm.s3) ? 0.f : yl[l+17]); + } + float d1 = d_all * (s1 + 1.f/256.f * s2 - s3*v1); + float d2 = d_all * (s4 + 1.f/256.f * s5 - s6*v2); + sumf1[row] += d1 * (sc.s0 - 32); + sumf2[row] += d2 * (sc.s2 - 32); + + s1 = s2 = s3 = s4 = s5 = s6 = 0; + for (int l = 0; l < 8; l += 2) { + int qs = q[l/2+8]; + s1 += yl[l+8] * (qs & qm.s0); + s2 += yl[l+9] * (qs & qm.s1); + s3 += ((h[l/2+8] & hm.s0) ? 0.f : yl[l+8]) + ((h[l/2+8] & hm.s1) ? 0.f : yl[l+9]); + s4 += yl[l+24] * (qs & qm.s2); + s5 += yl[l+25] * (qs & qm.s3); + s6 += ((h[l/2+8] & hm.s2) ? 0.f : yl[l+24]) + ((h[l/2+8] & hm.s3) ? 0.f : yl[l+25]); + } + d1 = d_all * (s1 + 1.f/256.f * s2 - s3*v1); + d2 = d_all * (s4 + 1.f/256.f * s5 - s6*v2); + sumf1[row] += d1 * (sc.s1 - 32); + sumf2[row] += d2 * (sc.s3 - 32); + + q += row_stride*32; + h += row_stride*16; + a += row_stride*6; + dh += row_stride*1; + } + + y1 += BLOCK_STRIDE * QK_K; + } + + global float * dst_f32 = (global float *) dst + im*ne0*ne1 + r1*ne0; + + for (int row = 0; row < N_DST; ++row) { + all_sum = sub_group_reduce_add((sumf1[row] + 0.25f * sumf2[row]) / (1 << shift)); + if (first_row + row < ne01) { + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = all_sum; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/quant_a_q8_1.cl b/ggml/src/ggml-opencl/kernels/quant_a_q8_1.cl index 3ce06305a36a..5b6dea773e7f 100644 --- a/ggml/src/ggml-opencl/kernels/quant_a_q8_1.cl +++ b/ggml/src/ggml-opencl/kernels/quant_a_q8_1.cl @@ -1,9 +1,7 @@ #pragma OPENCL EXTENSION cl_khr_fp16 : enable -// Quantize a contiguous [N, K] f32 activation buffer (token-major, K contiguous -// per token) into q8_1 blocks of 32: int8 quants + per-block scale d + per-block -// sum s (= d * Sum(qs)). Consumed by kernel_gemm_noshuffle_q4_k_q8_1_dp4a for the -// dp4a (int8) dense q4_K prefill GEMM. One work-item per 32-element block. +// Quantize a contiguous K-major [N, K] f32 activation buffer (K contiguous) into 32-value Q8_1 SoA blocks. +// Store int8 quants, per-block scale d, and scaled sum s = d * sum(qs); one work-item handles each block. __kernel void kernel_quant_a_q8_1( __global const float * src, // [N * K] __global char * qa, // [N * K] diff --git a/ggml/src/ggml-opencl/kernels/rope.cl b/ggml/src/ggml-opencl/kernels/rope.cl index 27fdbbbc4ff1..5b99d42de3ed 100644 --- a/ggml/src/ggml-opencl/kernels/rope.cl +++ b/ggml/src/ggml-opencl/kernels/rope.cl @@ -520,7 +520,7 @@ kernel void kernel_rope_multi_f16( src0 = (global void*)((global char*)src0 + offset0); src1 = (global int*)((global char*)src1 + offset1); src2 = (global float*)((global char*)src2 + offset2); - dst = (global float*)((global char*)dst + offsetd); + dst = (global half*)((global char*)dst + offsetd); int i3 = get_group_id(2); int i2 = get_group_id(1); @@ -714,7 +714,7 @@ kernel void kernel_rope_vision_f16( src0 = (global void*)((global char*)src0 + offset0); src1 = (global int*)((global char*)src1 + offset1); src2 = (global float*)((global char*)src2 + offset2); - dst = (global float*)((global char*)dst + offsetd); + dst = (global half*)((global char*)dst + offsetd); int i3 = get_group_id(2); int i2 = get_group_id(1); diff --git a/ggml/src/ggml-opencl/kernels/top_k.cl b/ggml/src/ggml-opencl/kernels/top_k.cl new file mode 100644 index 000000000000..6b5126e0d9a2 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/top_k.cl @@ -0,0 +1,207 @@ +#ifdef cl_khr_subgroups +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +uint top_k_key(float value) { + uint bits = as_uint(value); + if ((bits & 0x7fffffffu) == 0) { + bits = 0; + } + return bits & 0x80000000u ? ~bits : bits ^ 0x80000000u; +} + +uint4 top_k_keys(global const char * src, int i, int n, ulong nb0) { + if (nb0 == sizeof(float) && i + 3 < n) { + const float4 v = vload4(0, (global const float *) src + i); + return (uint4) (top_k_key(v.s0), top_k_key(v.s1), top_k_key(v.s2), top_k_key(v.s3)); + } + return (uint4) ( + i < n ? top_k_key(*(global const float *) (src + (ulong) i *nb0)) : 0, + i + 1 < n ? top_k_key(*(global const float *) (src + (ulong) (i + 1)*nb0)) : 0, + i + 2 < n ? top_k_key(*(global const float *) (src + (ulong) (i + 2)*nb0)) : 0, + i + 3 < n ? top_k_key(*(global const float *) (src + (ulong) (i + 3)*nb0)) : 0); +} + +void top_k_store(global int * dst, global uint2 * candidates, global const char * src, + ulong nb0, int indexed, int base, int i, uint pos) { + const int index = indexed ? *(global const int *) (src + (ulong) i*nb0 + sizeof(float)) : base + i; + if (candidates) { + candidates[pos] = (uint2) (as_uint(*(global const float *) (src + (ulong) i*nb0)), index); + } else { + dst[pos] = index; + } +} + +void top_k_select( + global const char * src, + global int * dst, + global uint2 * candidates, + ulong nb00, + int ne00, + int k, + int base, + int indexed, + local uint * hist +) { + const int tid = get_local_id(0); + const int nth = get_local_size(0); + if (k == ne00) { + for (int i = tid; i < ne00; i += nth) { + top_k_store(dst, candidates, src, nb00, indexed, base, i, i); + } + return; + } + + uint prefix = 0; + uint mask = 0; + uint rank = k; + for (int shift = 24; shift >= 0; shift -= 8) { + for (int i = tid; i < 256; i += nth) { + hist[i] = 0; + } + barrier(CLK_LOCAL_MEM_FENCE); + for (int i = 4*tid; i < ne00; i += 4*nth) { + const uint4 v = top_k_keys(src, i, ne00, nb00); + const uint keys[4] = {v.s0, v.s1, v.s2, v.s3}; + #pragma unroll + for (int j = 0; j < 4; ++j) { + const uint key = keys[j]; + if (i + j < ne00 && (key & mask) == prefix) { + atomic_inc(hist + ((key >> shift) & 255)); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + if (tid == 0) { + uint above = 0; + for (int b = 255; b >= 0; --b) { + uint count = hist[b]; + if (above + count >= rank) { + hist[256] = b; + hist[257] = rank - above; + hist[258] = count; + break; + } + above += count; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + prefix |= hist[256] << shift; + rank = hist[257]; + const bool done = hist[258] == rank; + barrier(CLK_LOCAL_MEM_FENCE); + if (done) { + // The whole bucket is selected, so its low bits do not matter. + break; + } + mask |= 255u << shift; + } + + uint greater = 0; + uint equal = 0; + for (int i = 4*tid; i < ne00; i += 4*nth) { + const uint4 v = top_k_keys(src, i, ne00, nb00); + const uint keys[4] = {v.s0, v.s1, v.s2, v.s3}; + #pragma unroll + for (int j = 0; j < 4; ++j) { + greater += i + j < ne00 && keys[j] > prefix; + equal += i + j < ne00 && keys[j] == prefix; + } + } + uint pos_greater; + uint pos_equal; +#ifdef cl_khr_subgroups + const uint sg = get_sub_group_id(); + const uint nsg = get_num_sub_groups(); + const uint total_greater = sub_group_reduce_add(greater); + const uint total_equal = sub_group_reduce_add(equal); + pos_greater = sub_group_scan_exclusive_add(greater); + pos_equal = sub_group_scan_exclusive_add(equal); + if (get_sub_group_local_id() == 0) { + hist[sg] = total_greater; + hist[nsg + sg] = total_equal; + } + barrier(CLK_LOCAL_MEM_FENCE); + for (uint i = 0; i < nsg; ++i) { + pos_equal += hist[i]; + if (i < sg) { + pos_greater += hist[i]; + pos_equal += hist[nsg + i]; + } + } +#else + hist[tid] = greater; + hist[nth + tid] = equal; + barrier(CLK_LOCAL_MEM_FENCE); + pos_greater = 0; + pos_equal = 0; + for (int i = 0; i < nth; ++i) { + pos_equal += hist[i]; + if (i < tid) { + pos_greater += hist[i]; + pos_equal += hist[nth + i]; + } + } +#endif + for (int i = 4*tid; i < ne00; i += 4*nth) { + const uint4 v = top_k_keys(src, i, ne00, nb00); + const uint keys[4] = {v.s0, v.s1, v.s2, v.s3}; + #pragma unroll + for (int j = 0; j < 4; ++j) { + if (i + j < ne00) { + if (keys[j] > prefix) { + top_k_store(dst, candidates, src, nb00, indexed, base, i + j, pos_greater++); + } else if (keys[j] == prefix && pos_equal < k) { + top_k_store(dst, candidates, src, nb00, indexed, base, i + j, pos_equal++); + } + } + } + } +} + +kernel void kernel_top_k_f32( + global const char * src, + ulong offset0, + global int * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int k_max, + local uint * hist, + global uint2 * candidates, + int tile_width +) { + const ulong row = get_group_id(1); + const int part = get_group_id(0); + const int parts = get_num_groups(0); + const int base = part*tile_width; + const int n = min(ne00 - base, tile_width); + const int k = min(k_max, n); + const int out_width = (parts - 1)*k_max + min(k_max, ne00 - (parts - 1)*tile_width); + src += offset0 + (row % ne01)*nb01 + (row / ne01 % ne02)*nb02 + (row / ne01 / ne02)*nb03 + (ulong) base*nb00; + if (candidates) { + candidates += row*out_width + part*k_max; + } else { + dst = (global int *) ((global char *) dst + offsetd) + row*out_width + part*k_max; + } + top_k_select(src, dst, candidates, nb00, n, k, base, 0, hist); +} + +kernel void kernel_top_k_merge_f32( + global const uint2 * candidates, + global int * dst, + ulong offsetd, + int n_candidates, + int k, + local uint * hist +) { + const ulong row = get_group_id(1); + candidates += row*n_candidates; + dst = (global int *) ((global char *) dst + offsetd) + row*k; + top_k_select((global const char *) candidates, dst, 0, sizeof(uint2), n_candidates, k, 0, 1, hist); +} diff --git a/ggml/src/ggml-opencl/kernels/top_k_mask.cl b/ggml/src/ggml-opencl/kernels/top_k_mask.cl new file mode 100644 index 000000000000..00fc0fb132b2 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/top_k_mask.cl @@ -0,0 +1,129 @@ +// Integer storage preserves the mask bits without FP16 conversion. +#if MASK_F16 +#define MASK_T ushort +#define MASK_V ushort8 +#define MASK_NV 8 +#define MASK_NINF 0xfc00 +#define MASK_STORE vstore8 +#else +#define MASK_T uint +#define MASK_V uint4 +#define MASK_NV 4 +#define MASK_NINF 0xff800000u +#define MASK_STORE vstore4 +#endif + +kernel void kernel_top_k_mask_fill( + global char * dst, + ulong offsetd, + ulong n +) { + global MASK_T * out = (global MASK_T *) (dst + offsetd); + const ulong c = get_global_id(0)*MASK_NV; + if (c + MASK_NV <= n) { + MASK_STORE((MASK_V) (MASK_NINF), 0, out + c); + } else { + for (ulong j = c; j < n; ++j) { + out[j] = MASK_NINF; + } + } +} + +kernel void kernel_top_k_mask( + global const char * mask, + ulong offsetm, + global const char * top_k, + ulong offsetk, + global const char * score, + ulong offsets, + global const char * blocks, + ulong offsetb, + global const char * extra, + ulong offsete, + global char * dst, + ulong offsetd, + ulong nem0, + ulong nem1, + ulong nem2, + ulong nem3, + ulong nbm1, + ulong nbm2, + ulong nbm3, + ulong nek0, + ulong nbk0, + ulong nbk1, + ulong nbk2, + ulong nbk3, + ulong nes0, + ulong nbs0, + ulong nbs1, + ulong nbs2, + ulong nbs3, + ulong neb0, + ulong neb1, + ulong nbb0, + ulong nbb1, + ulong nee0, + ulong nbe0, + ulong nbe1, + ulong nbe2, + ulong nbe3, + ulong ned1, + ulong ned2, + ulong nbd1, + ulong nbd2, + ulong nbd3, + int fill +) { + const ulong row = get_group_id(1); + const ulong i1 = row % ned1; + const ulong i2 = (row / ned1) % ned2; + const ulong i3 = row / (ned1*ned2); + const ulong tid = get_local_id(0); + const ulong nth = get_local_size(0); + const ulong n_pick = blocks ? neb1 : score ? nes0 : nem0; + + global const MASK_T * mask_row = (global const MASK_T *) (mask + offsetm + + (i1 % nem1)*nbm1 + (i2 % nem2)*nbm2 + (i3 % nem3)*nbm3); + global MASK_T * dst_row = (global MASK_T *) (dst + offsetd + i1*nbd1 + i2*nbd2 + i3*nbd3); + global const char * top_k_row = top_k + offsetk + i1*nbk1 + i2*nbk2 + i3*nbk3; + + if (fill) { + for (ulong c = tid; c < nem0/MASK_NV; c += nth) { + MASK_STORE((MASK_V) (MASK_NINF), c, dst_row); + } + for (ulong c = nem0/MASK_NV*MASK_NV + tid; c < nem0; c += nth) { + dst_row[c] = MASK_NINF; + } + barrier(CLK_GLOBAL_MEM_FENCE); + } + + // Repeated cells copy the same mask value, as in the CUDA and Metal kernels. + for (ulong j = tid; j < nek0 + nee0; j += nth) { + if (j >= nek0) { + const int c = *(global const int *) (extra + offsete + (j - nek0)*nbe0 + i1*nbe1 + i2*nbe2 + i3*nbe3); + if (c >= 0 && (ulong) c < nem0) { + dst_row[c] = mask_row[c]; + } + continue; + } + + const int p = *(global const int *) (top_k_row + j*nbk0); + if (p < 0 || (ulong) p >= n_pick) { + continue; + } + if (score && !(*(global const float *) (score + offsets + p*nbs0 + i1*nbs1 + i2*nbs2 + i3*nbs3) > -INFINITY)) { + continue; + } + if (blocks) { + for (ulong k = 0; k < neb0; ++k) { + const int c = *(global const int *) (blocks + offsetb + k*nbb0 + p*nbb1); + if (c >= 0 && (ulong) c < nem0) { + dst_row[c] = mask_row[c]; + } + } + } else if ((ulong) p < nem0) { + dst_row[p] = mask_row[p]; + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/transpose_activation_q8.cl b/ggml/src/ggml-opencl/kernels/transpose_activation_q8.cl new file mode 100644 index 000000000000..34d54b57e24a --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/transpose_activation_q8.cl @@ -0,0 +1,35 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_subgroups : enable + +#define tile_size 32 + +kernel void kernel_transpose_activation_q8( + __global uint * src1_qa, + __global uint * src1_qa_trans, + __global half * src1_sa, + __global float * src1_sa_trans, + __global const int * total_tiles, + uint K +) { + uint row_in_tile = get_global_id(0); + uint blk_k = get_group_id(1); + uint col_in_tile = get_local_id(1); + uint tile_n = get_global_id(2); + + if (blk_k >= (K / tile_size) || tile_n >= (uint)total_tiles[0]) { + return; + } + + uint src_idx = (tile_n * tile_size + row_in_tile) * K / 4 + blk_k * 8 + col_in_tile; + uint dst_idx = tile_n * tile_size * K / 4 + (blk_k * 8 + col_in_tile) * tile_size + row_in_tile; + + src1_qa_trans[dst_idx] = src1_qa[src_idx]; + + if (col_in_tile == 0) { + src_idx = (tile_n * tile_size + row_in_tile) * K / 32 + blk_k; + dst_idx = tile_n * tile_size * K / 32 + blk_k * tile_size + row_in_tile; + + src1_sa_trans[dst_idx] = (float)(src1_sa[src_idx]); + } + +} diff --git a/ggml/src/ggml-openvino/ggml-openvino.cpp b/ggml/src/ggml-openvino/ggml-openvino.cpp index 22b2f45e24a6..88634557cd58 100644 --- a/ggml/src/ggml-openvino/ggml-openvino.cpp +++ b/ggml/src/ggml-openvino/ggml-openvino.cpp @@ -638,6 +638,9 @@ static const ggml_backend_buffer_i ggml_backend_openvino_buffer_interface = { /* .cpy_tensor = */ ggml_backend_openvino_buffer_cpy_tensor, /* .clear = */ ggml_backend_openvino_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; // Buffer type interface functions @@ -1446,6 +1449,10 @@ static ggml_openvino_op_support is_op_supported_case(const ggml_tensor * op) { if (op->type == GGML_TYPE_BF16) { return {false, "SCALE with BF16 type is not supported"}; } + // The result is copied back densely, so an in-place SCALE on a strided view would be written wrongly. + if (op->view_src != nullptr && !ggml_is_contiguous(op)) { + return {false, "SCALE in place on a non-contiguous view is not supported"}; + } break; } case GGML_OP_ADD_ID: { @@ -1513,6 +1520,11 @@ static ggml_openvino_op_support is_op_supported_case(const ggml_tensor * op) { return {false, "FLASH_ATTN_EXT gemma3n pattern on GPU is not supported"}; } + // K/V row lists (ggml_flash_attn_ext_rows) are not supported + if (op->src[5] != nullptr) { + return {false, "FLASH_ATTN_EXT with K/V row lists is not supported"}; + } + if (op->src[4] != nullptr) { return {false, "FLASH_ATTN_EXT with sinks is not supported"}; } diff --git a/ggml/src/ggml-openvino/openvino/op/add_id.cpp b/ggml/src/ggml-openvino/openvino/op/add_id.cpp index 79bdbe87731e..04b1d3ff256b 100644 --- a/ggml/src/ggml-openvino/openvino/op/add_id.cpp +++ b/ggml/src/ggml-openvino/openvino/op/add_id.cpp @@ -9,8 +9,12 @@ #include #include #include +#include +#include +#include #include #include +#include namespace ov { namespace frontend { @@ -52,8 +56,16 @@ OutputVector translate_add_id(const NodeContext & context) { ids = std::make_shared(ids, ov::element::i32); } + // an id of -1 marks a skipped slot: gather row 0 for it and zero the bias with a mask + auto zero = ov::op::v0::Constant::create(ids.get_element_type(), ov::Shape{}, {0}); + ov::Output keep = std::make_shared(ids, zero); + keep = std::make_shared(keep, bias.get_element_type()); + keep = std::make_shared(keep, ov::op::v0::Constant::create(ov::element::i64, ov::Shape{1}, {-1})); + ids = std::make_shared(ids, zero); + auto gather_axis = ov::op::v0::Constant::create(ov::element::i32, ov::Shape{}, {0}); ov::Output selected_bias = std::make_shared(bias, ids, gather_axis); + selected_bias = std::make_shared(selected_bias, keep); selected_bias = std::make_shared( selected_bias, std::make_shared(input, ov::element::i64), false); diff --git a/ggml/src/ggml-openvino/openvino/op/glu_swiglu.cpp b/ggml/src/ggml-openvino/openvino/op/glu_swiglu.cpp index 7eea81d96e59..2c206a597db6 100644 --- a/ggml/src/ggml-openvino/openvino/op/glu_swiglu.cpp +++ b/ggml/src/ggml-openvino/openvino/op/glu_swiglu.cpp @@ -75,6 +75,15 @@ OutputVector translate_glu_swiglu_oai(const NodeContext & context) { const float alpha = reinterpret_cast(params)[2]; const float limit = reinterpret_cast(params)[3]; + // Compute in f32: alpha_const/one are f32, and Swish/Add need matching input types. + auto output_type = context.get_output_type(); + if (src0.get_element_type() != ov::element::f32) { + src0 = std::make_shared(src0, ov::element::f32); + } + if (src1.get_element_type() != ov::element::f32) { + src1 = std::make_shared(src1, ov::element::f32); + } + auto gate = std::make_shared(src0, -std::numeric_limits::infinity(), limit); auto alpha_const = ov::op::v0::Constant::create(ov::element::f32, {}, {alpha}); auto out_glu = std::make_shared(gate, alpha_const); @@ -82,7 +91,10 @@ OutputVector translate_glu_swiglu_oai(const NodeContext & context) { auto up = std::make_shared(src1, -limit, limit); auto one = ov::op::v0::Constant::create(ov::element::f32, {}, {1.0f}); auto up_plus_one = std::make_shared(up, one); - auto res = std::make_shared(out_glu, up_plus_one); + ov::Output res = std::make_shared(out_glu, up_plus_one); + if (res.get_element_type() != output_type) { + res = std::make_shared(res, output_type); + } return rename_outputs_with_suffix({res}, context.get_name()); } diff --git a/ggml/src/ggml-openvino/openvino/op/scale.cpp b/ggml/src/ggml-openvino/openvino/op/scale.cpp index 2947ee03c97c..4be2e700c20e 100644 --- a/ggml/src/ggml-openvino/openvino/op/scale.cpp +++ b/ggml/src/ggml-openvino/openvino/op/scale.cpp @@ -70,7 +70,7 @@ OutputVector translate_scale(const NodeContext & context) { return rename_outputs_with_suffix({cleared_cache_rs}, context.get_name()); } - auto scaled = std::make_shared(context.get_input(0), scale_node); + auto scaled = std::make_shared(process_view_input_new(context, 0), scale_node); std::shared_ptr res; if (bias != 0.0f) { diff --git a/ggml/src/ggml-quants.c b/ggml/src/ggml-quants.c index 0dc8e59a01e2..e913aaf7da44 100644 --- a/ggml/src/ggml-quants.c +++ b/ggml/src/ggml-quants.c @@ -25,15 +25,12 @@ #define UNUSED GGML_UNUSED -static inline int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) return 0; - if (x >= val[n-1]) return n-1; - int ml = 0, mu = n-1; - while (mu-ml > 1) { - int mav = (ml+mu)/2; - if (x < val[mav]) mu = mav; else ml = mav; - } - return x - val[mu-1] < val[mu] - x ? mu-1 : mu; +// index of the nearest kvalues_iq4nl value, with mid[k] = (values[k] + values[k+1])/2 +// for this table it matches a binary search with the tie rule x - values[k] < values[k+1] - x for every float x +static inline int best_index_iq4nl(const float * GGML_RESTRICT mid, float x) { + int l = 15; + for (int k = 0; k < 15; ++k) l -= x < mid[k]; + return l; } // reference implementation for deterministic creation of model files @@ -416,6 +413,12 @@ void quantize_row_nvfp4_ref(const float * GGML_RESTRICT x, block_nvfp4 * GGML_RE } } +void quantize_row_f8_e4m3_ref(const float * GGML_RESTRICT x, ggml_fp8_e4m3_t * GGML_RESTRICT y, int64_t k) { + for (int64_t i = 0; i < k; ++i) { + y[i].bits = ggml_fp32_to_f8_e4m3(x[i]); + } +} + void dequantize_row_q1_0(const block_q1_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { static const int qk = QK1_0; @@ -1140,6 +1143,12 @@ bool rocmfp4_validate_row_data_fast(const void * data, size_t nbytes) { return true; } +void dequantize_row_f8_e4m3(const ggml_fp8_e4m3_t * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + for (int64_t i = 0; i < k; ++i) { + y[i] = ggml_f8_e4m3_to_fp32(x[i].bits); + } +} + // // 2-6 bit quantization in super-blocks // @@ -2841,6 +2850,12 @@ size_t quantize_nvfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, return nrow * ggml_row_size(GGML_TYPE_NVFP4, n_per_row); } +size_t quantize_f8_e4m3(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrow, int64_t n_per_row, const float * quant_weights) { + GGML_UNUSED(quant_weights); + quantize_row_f8_e4m3_ref(src, dst, (int64_t)nrow*n_per_row); + return nrow * ggml_row_size(GGML_TYPE_F8_E4M3, n_per_row); +} + // ====================== Ternary (de)-quantization (BitNet b1.58 and TriLMs) void quantize_row_tq1_0_ref(const float * GGML_RESTRICT x, block_tq1_0 * GGML_RESTRICT y, int64_t k) { @@ -5478,6 +5493,11 @@ static void quantize_row_iq4_nl_impl(const int super_block_size, const int block memset(q4, 0, super_block_size/2); dh[0] = GGML_FP32_TO_FP16(0.f); + float mid[15]; + float fval[16]; + for (int k = 0; k < 15; ++k) mid[k] = 0.5f*(values[k] + values[k+1]); + for (int k = 0; k < 16; ++k) fval[k] = values[k]; + float max_scale = 0, amax_scale = 0; for (int ib = 0; ib < super_block_size/block_size; ++ib) { const float * xb = x + ib*block_size; @@ -5500,32 +5520,28 @@ static void quantize_row_iq4_nl_impl(const int super_block_size, const int block continue; } float d = ntry > 0 ? -max/values[0] : max/values[0]; - float id = 1/d; - float sumqx = 0, sumq2 = 0; + // lane 0 is the initial guess, lanes 1..nt-1 are itry = -ntry..ntry; each lane sums over j in order + const int nt = ntry >= 0 ? 2*ntry + 2 : 1; + float idt[16], sqx[16], sq2[16]; + idt[0] = 1/d; + for (int t = 1; t < nt; ++t) idt[t] = (t - 1 - ntry + values[0])/max; + for (int t = 0; t < nt; ++t) sqx[t] = sq2[t] = 0; for (int j = 0; j < block_size; ++j) { - float al = id*xb[j]; - int l = best_index_int8(16, values, al); - Lb[j] = l; - float q = values[l]; - float w = weight[j]; - sumqx += w*q*xb[j]; - sumq2 += w*q*q; + Lb[j] = best_index_iq4nl(mid, idt[0]*xb[j]); } - d = sumq2 > 0 ? sumqx/sumq2 : 0.f; - float best = d*sumqx; - for (int itry = -ntry; itry <= ntry; ++itry) { - id = (itry + values[0])/max; - sumqx = sumq2 = 0; - for (int j = 0; j < block_size; ++j) { - float al = id*xb[j]; - int l = best_index_int8(16, values, al); - float q = values[l]; - float w = weight[j]; - sumqx += w*q*xb[j]; - sumq2 += w*q*q; + for (int j = 0; j < block_size; ++j) { + float w = weight[j]; + for (int t = 0; t < nt; ++t) { + float q = fval[best_index_iq4nl(mid, idt[t]*xb[j])]; + sqx[t] += w*q*xb[j]; + sq2[t] += w*q*q; } - if (sumq2 > 0 && sumqx*sumqx > best*sumq2) { - d = sumqx/sumq2; best = d * sumqx; + } + d = sq2[0] > 0 ? sqx[0]/sq2[0] : 0.f; + float best = d*sqx[0]; + for (int t = 1; t < nt; ++t) { + if (sq2[t] > 0 && sqx[t]*sqx[t] > best*sq2[t]) { + d = sqx[t]/sq2[t]; best = d * sqx[t]; } } scales[ib] = d; @@ -5549,7 +5565,7 @@ static void quantize_row_iq4_nl_impl(const int super_block_size, const int block uint8_t * Lb = L + ib*block_size; const float * xb = x + ib*block_size; for (int j = 0; j < block_size; ++j) { - Lb[j] = best_index_int8(16, values, idl*xb[j]); + Lb[j] = best_index_iq4nl(mid, idl*xb[j]); } l += 32; uint8_t l_l = l & 0xf; @@ -5563,7 +5579,7 @@ static void quantize_row_iq4_nl_impl(const int super_block_size, const int block if (ntry > 0) { float id = scales[0] ? 1/scales[0] : 0; for (int j = 0; j < super_block_size; ++j) { - L[j] = best_index_int8(16, values, id*x[j]); + L[j] = best_index_iq4nl(mid, id*x[j]); } } } @@ -6078,10 +6094,20 @@ bool ggml_validate_row_data(enum ggml_type type, const void * data, size_t nbyte } break; case GGML_TYPE_NVFP4: { - // UE4M3 scales are uint8_t — all byte values are valid + // TODO: validate each unsigned E4M3 scale; NaN encodings and scales with the sign bit set are invalid. GGML_UNUSED(data); GGML_UNUSED(nb); } break; + case GGML_TYPE_F8_E4M3: + { + const ggml_fp8_e4m3_t * q = (const ggml_fp8_e4m3_t *) data; + for (size_t i = 0; i < nb; ++i) { + if ((q[i].bits & 0x7F) == 0x7F) { + fprintf(stderr, "%s: found NaN at index %zu in row of %zu F8_E4M3 values\n", __func__, i, nb); + return false; + } + } + } break; case GGML_TYPE_Q2_K: { VALIDATE_ROW_DATA_DM_F16_IMPL(block_q2_K, data, nb, d, dmin); diff --git a/ggml/src/ggml-quants.h b/ggml/src/ggml-quants.h index 07f021a3fdae..b4428cf6dfbc 100644 --- a/ggml/src/ggml-quants.h +++ b/ggml/src/ggml-quants.h @@ -25,6 +25,7 @@ GGML_API void quantize_row_q8_1_ref(const float * GGML_RESTRICT x, block_q8_1 * GGML_API void quantize_row_mxfp4_ref(const float * GGML_RESTRICT x, block_mxfp4 * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_nvfp4_ref(const float * GGML_RESTRICT x, block_nvfp4 * GGML_RESTRICT y, int64_t k); +GGML_API void quantize_row_f8_e4m3_ref(const float * GGML_RESTRICT x, ggml_fp8_e4m3_t * GGML_RESTRICT y, int64_t k); GGML_API void rocmfp4_quantize_row_q4_0_ref (const float * GGML_RESTRICT x, block_rocmfp4 * GGML_RESTRICT y, int64_t k); GGML_API void rocmfp4_quantize_row_q4_0_fast_ref(const float * GGML_RESTRICT x, block_rocmfp4_fast * GGML_RESTRICT y, int64_t k); @@ -57,6 +58,7 @@ GGML_API void dequantize_row_q8_0(const block_q8_0 * GGML_RESTRICT x, float * GG GGML_API void dequantize_row_mxfp4(const block_mxfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void dequantize_row_nvfp4(const block_nvfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_f8_e4m3(const ggml_fp8_e4m3_t * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void rocmfp4_dequantize_row_q4_0 (const block_rocmfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void rocmfp4_dequantize_row_q4_0_fast(const block_rocmfp4_fast * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); @@ -110,6 +112,7 @@ GGML_API size_t quantize_q8_0(const float * GGML_RESTRICT src, void * GGML_RESTR GGML_API size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t quantize_nvfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +GGML_API size_t quantize_f8_e4m3(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t rocmfp4_quantize_q4_0 (const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t rocmfp4_quantize_q4_0_fast(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); diff --git a/ggml/src/ggml-rpc/ggml-rpc.cpp b/ggml/src/ggml-rpc/ggml-rpc.cpp index 49f11073e993..5cf9339bd4bb 100644 --- a/ggml/src/ggml-rpc/ggml-rpc.cpp +++ b/ggml/src/ggml-rpc/ggml-rpc.cpp @@ -348,7 +348,10 @@ static bool recv_msg(socket_ptr sock, std::vector & input) { } try { input.resize(size); - } catch (const std::bad_alloc & e) { + } catch (const std::length_error &) { + LOG_ERROR("Failed to allocate input buffer of size %" PRIu64 "\n", size); + return false; + } catch (const std::bad_alloc &) { LOG_ERROR("Failed to allocate input buffer of size %" PRIu64 "\n", size); return false; } @@ -971,6 +974,9 @@ static ggml_backend_buffer_i ggml_backend_rpc_buffer_interface = { /* .cpy_tensor = */ ggml_backend_rpc_buffer_cpy_tensor, /* .clear = */ ggml_backend_rpc_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; static const char * ggml_backend_rpc_buffer_type_name(ggml_backend_buffer_type_t buft) { diff --git a/ggml/src/ggml-rpc/transport.cpp b/ggml/src/ggml-rpc/transport.cpp index 22b38e00f508..d5670f34d904 100644 --- a/ggml/src/ggml-rpc/transport.cpp +++ b/ggml/src/ggml-rpc/transport.cpp @@ -517,6 +517,11 @@ bool socket_t::impl::rdma_recv(void * data, size_t size) { int slot = (int)wc.wr_id; size_t got = wc.byte_len; + if (got > rem) { + LOG_ERROR("RDMA recv overrun: got=%zu rem=%zu\n", got, rem); + c->post_rx(slot); + return false; + } memcpy(dst, c->rx_slot(slot), got); if (!c->post_rx(slot)) return false; diff --git a/ggml/src/ggml-sycl/CMakeLists.txt b/ggml/src/ggml-sycl/CMakeLists.txt index dfdb4746d061..35d36e583734 100644 --- a/ggml/src/ggml-sycl/CMakeLists.txt +++ b/ggml/src/ggml-sycl/CMakeLists.txt @@ -44,7 +44,7 @@ if (WIN32) if(DEFINED ENV{LEVEL_ZERO_V1_SDK_PATH}) set(LEVEL_ZERO_V1_SDK_PATH $ENV{LEVEL_ZERO_V1_SDK_PATH}) if(EXISTS "${LEVEL_ZERO_V1_SDK_PATH}") - target_include_directories(ggml-sycl PRIVATE "${LEVEL_ZERO_V1_SDK_PATH}/include") + target_include_directories(ggml-sycl SYSTEM PRIVATE "${LEVEL_ZERO_V1_SDK_PATH}/include") set(LEVEL_ZERO_V1_SDK_LIB_PATH "${LEVEL_ZERO_V1_SDK_PATH}/lib") else() message(WARNING "LEVEL_ZERO_V1_SDK_PATH set but folder not found: ${LEVEL_ZERO_V1_SDK_PATH}") @@ -107,24 +107,36 @@ target_compile_options(ggml-sycl PRIVATE "-Wno-narrowing") message(STATUS "GGML_SYCL_SUPPORT_LEVEL_ZERO_API ${GGML_SYCL_SUPPORT_LEVEL_ZERO_API}") if (GGML_SYCL_SUPPORT_LEVEL_ZERO_API) - # Link against Level Zero loader for direct device memory allocation. - # Avoids sycl::malloc_device triggering DMA-buf/TTM system RAM staging - # in the xe kernel driver during multi-GPU inference. - find_path(LEVEL_ZERO_DEV_INCLUDE_DIR level_zero/ze_api.h HINTS ${ONEAPI_ROOT}/include ${LEVEL_ZERO_V1_SDK_PATH}/include) - find_library(ZE_LOADER_LIB ze_loader HINTS ${ONEAPI_ROOT}/lib ${LEVEL_ZERO_V1_SDK_LIB_PATH} ENV LD_LIBRARY_PATH) - if(ZE_LOADER_LIB AND LEVEL_ZERO_DEV_INCLUDE_DIR) - target_link_libraries(ggml-sycl PRIVATE ${ZE_LOADER_LIB}) - target_compile_definitions(ggml-sycl PRIVATE GGML_SYCL_SUPPORT_LEVEL_ZERO_API) - message(STATUS "Level Zero loader found: ${ZE_LOADER_LIB}") - message(STATUS "Level Zero development headers found: ${LEVEL_ZERO_DEV_INCLUDE_DIR}") + find_package(PkgConfig) + if (PkgConfig_FOUND) + pkg_check_modules(LEVEL_ZERO level-zero) + if (LEVEL_ZERO_FOUND) + target_include_directories(ggml-sycl PRIVATE ${LEVEL_ZERO_INCLUDE_DIRS}) + target_link_libraries(ggml-sycl PRIVATE ${LEVEL_ZERO_LINK_LIBRARIES}) + target_compile_definitions(ggml-sycl PRIVATE GGML_SYCL_SUPPORT_LEVEL_ZERO_API) + message(STATUS "Level Zero loader found: ${LEVEL_ZERO_LINK_LIBRARIES}") + message(STATUS "Level Zero development headers found: ${LEVEL_ZERO_INCLUDE_DIRS}") + endif() else() - message(WARNING "Level Zero loader or development headers not found, " - "Level Zero API support disabled. " - "Please install the Level Zero SDK/development package " - "to support Level Zero API features. " - "Level Zero API is not mandatory for SYCL backend, " - "but it is required by the special features for better " - "function & performance on Intel GPUs.") + # Link against Level Zero loader for direct device memory allocation. + # Avoids sycl::malloc_device triggering DMA-buf/TTM system RAM staging + # in the xe kernel driver during multi-GPU inference. + find_path(LEVEL_ZERO_DEV_INCLUDE_DIR level_zero/ze_api.h HINTS ${ONEAPI_ROOT}/include ${LEVEL_ZERO_V1_SDK_PATH}/include) + find_library(ZE_LOADER_LIB ze_loader HINTS ${ONEAPI_ROOT}/lib ${LEVEL_ZERO_V1_SDK_LIB_PATH} ENV LD_LIBRARY_PATH) + if(ZE_LOADER_LIB AND LEVEL_ZERO_DEV_INCLUDE_DIR) + target_link_libraries(ggml-sycl PRIVATE ${ZE_LOADER_LIB}) + target_compile_definitions(ggml-sycl PRIVATE GGML_SYCL_SUPPORT_LEVEL_ZERO_API) + message(STATUS "Level Zero loader found: ${ZE_LOADER_LIB}") + message(STATUS "Level Zero development headers found: ${LEVEL_ZERO_DEV_INCLUDE_DIR}") + else() + message(WARNING "Level Zero loader or development headers not found, " + "Level Zero API support disabled. " + "Please install the Level Zero SDK/development package " + "to support Level Zero API features. " + "Level Zero API is not mandatory for SYCL backend, " + "but it is required by the special features for better " + "function & performance on Intel GPUs.") + endif() endif() endif() @@ -200,6 +212,10 @@ if (GGML_SYCL_F16) add_compile_definitions(GGML_SYCL_F16) endif() +if (GGML_SYCL_SUPPORT_XMX) + add_compile_definitions(GGML_SYCL_SUPPORT_XMX) +endif() + if (GGML_SYCL_TARGET STREQUAL "INTEL") add_compile_definitions(GGML_SYCL_WARP_SIZE=16) if (NOT GGML_SYCL_DEVICE_ARCH) diff --git a/ggml/src/ggml-sycl/add-id.cpp b/ggml/src/ggml-sycl/add-id.cpp index e0adc4fe4230..a7901859a7c2 100644 --- a/ggml/src/ggml-sycl/add-id.cpp +++ b/ggml/src/ggml-sycl/add-id.cpp @@ -26,6 +26,15 @@ static void add_id_kernel( float* dst_row = (float*)((char*)dst + i1 * nb1 + i2 * nb2); const float* src0_row = (const float*)((const char*)src0 + i1 * nb01 + i2 * nb02); + + if (i11 == -1) { // skipped slot, add nothing + for (int64_t i0 = item_ct1.get_local_id(2); i0 < ne0; + i0 += item_ct1.get_local_range(2)) { + dst_row[i0] = src0_row[i0]; + } + return; + } + const float* src1_row = (const float*)((const char*)src1 + i11 * nb11); for (int64_t i0 = item_ct1.get_local_id(2); i0 < ne0; diff --git a/ggml/src/ggml-sycl/common.cpp b/ggml/src/ggml-sycl/common.cpp index 894006949d23..f01d0ff955e5 100644 --- a/ggml/src/ggml-sycl/common.cpp +++ b/ggml/src/ggml-sycl/common.cpp @@ -115,7 +115,8 @@ void * ggml_sycl_malloc_device(size_t size, sycl::queue &q, ggml_sycl_mem_type t #else ze_device_mem_alloc_desc_t alloc_desc = {ZE_STRUCTURE_TYPE_DEVICE_MEM_ALLOC_DESC, nullptr, 0, 0}; #endif - ze_result_t r = zeMemAllocDevice(ze_ctx, &alloc_desc, size, 64, ze_dev, &ptr); + // request SYCL_BUFFER_ALIGNMENT so tensor offsets aligned to it stay aligned in absolute terms + ze_result_t r = zeMemAllocDevice(ze_ctx, &alloc_desc, size, SYCL_BUFFER_ALIGNMENT, ze_dev, &ptr); if (r == ZE_RESULT_SUCCESS && ptr) { ggml_sycl_memtrace_add(type, ptr, size); return ptr; diff --git a/ggml/src/ggml-sycl/common.hpp b/ggml/src/ggml-sycl/common.hpp index 4755093721ba..668e9befb9c5 100644 --- a/ggml/src/ggml-sycl/common.hpp +++ b/ggml/src/ggml-sycl/common.hpp @@ -16,7 +16,10 @@ #include #include #include +#include #include +#include +#include #include "base.hpp" #include "dpct/helper.hpp" @@ -37,6 +40,10 @@ namespace syclexp = sycl::ext::oneapi::experimental; #endif #endif +#if defined(__INTEL_LLVM_COMPILER) + #define GGML_SYCL_DMMV_HAS_ESIMD +#endif + #if GGML_SYCL_DNNL #include "dnnl.hpp" #include "dnnl_sycl.hpp" @@ -64,6 +71,9 @@ extern int g_ggml_sycl_enable_optimize; extern int g_ggml_sycl_enable_fusion; extern int g_ggml_sycl_enable_esimd; extern int g_ggml_sycl_mmvq_wide; +extern int g_ggml_sycl_enable_xmx_esimd; +extern int g_ggml_sycl_xmx_max_cols; +extern int g_ggml_sycl_xmx_glu_max_cols; extern int g_ggml_sycl_prioritize_dmmv; // Which quantized weight formats may take the XMX dequant-GEMM paths. A bitmask rather than one @@ -125,8 +135,10 @@ extern int g_ggml_sycl_dev2dev_memcpy; extern int g_ggml_sycl_fa_onednn; extern int g_ggml_sycl_fa_onednn_max_kv; extern int g_ggml_sycl_enable_mkl_fa; +extern int g_ggml_sycl_fa_dpas; extern int g_ggml_sycl_memtrace; extern int g_ggml_sycl_memtrace_step; +extern int g_ggml_sycl_graph_eviction_timeout; #define CHECK_TRY_ERROR(expr) \ @@ -151,12 +163,6 @@ extern int g_ggml_sycl_memtrace_step; #define GGML_SYCL_MAX_NODES 8192 // TODO: adapt to hardwares -// define for XMX in Intel GPU -// TODO: currently, it's not used for XMX really. -#if !defined(GGML_SYCL_FORCE_MMQ) - #define SYCL_USE_XMX -#endif - // max batch size to use MMQ kernels when tensor cores are available #define MMQ_MAX_BATCH_SIZE 32 @@ -223,6 +229,41 @@ typedef sycl::float2 dfloat2; #define MMVQ_MAX_BATCH_SIZE 8 +#if defined(__INTEL_LLVM_COMPILER) && __has_include() +# define GGML_SYCL_MMVQ_HAS_XMX +#endif // __INTEL_LLVM_COMPILER + +// default of the most columns the XMX mul_mat_vec_q handles (GGML_SYCL_XMX_MAX_COLS), wider batches use other kernels +#define GGML_SYCL_XMX_MAX_COLS_DEFAULT 80 + +// most columns the fused gate and up XMX kernel is built for, GGML_SYCL_XMX_GLU_MAX_COLS can only lower this limit +#define GGML_SYCL_XMX_GLU_MAX_COLS 16 + +static inline bool ggml_sycl_xmx_supports_type(ggml_type type) { + switch (type) { + case GGML_TYPE_Q2_K: + case GGML_TYPE_Q3_K: + case GGML_TYPE_Q4_K: + case GGML_TYPE_Q5_K: + case GGML_TYPE_Q6_K: + case GGML_TYPE_Q8_0: + return true; + default: + return false; + } +} + +// the DPAS shapes and 2D block loads used by the XMX kernel are those of Xe2 +static inline bool ggml_sycl_xmx_supports_arch(gpu_arch arch) { + return arch == gpu_arch::intel_gpu_bmg_g21 || arch == gpu_arch::intel_gpu_bmg_g31 || + arch == gpu_arch::intel_gpu_lnl_m; +} + +// fewest columns for which the XMX kernel is faster than the other kernels +static inline int ggml_sycl_xmx_min_cols(ggml_type type) { + return type == GGML_TYPE_Q2_K || type == GGML_TYPE_Q3_K || type == GGML_TYPE_Q4_K ? 1 : 2; +} + static int g_all_sycl_device_count = -1; static bool g_ggml_backend_sycl_buffer_type_initialized = false; @@ -273,6 +314,7 @@ struct optimize_feature { }; struct sycl_device_info { + bool active; //the device is activated/used in application. int cc; // compute capability int nsm; // number of streaming multiprocessors (CUDA) maps to the maximum // number of compute units on a SYCL device. @@ -289,10 +331,15 @@ struct sycl_device_info { sycl_hw_info hw_info; optimize_feature opt_feature; bool usm_system_support; // support for USM system allocations +#ifdef GGML_SYCL_GRAPH + bool graph_support; // command graphs can be recorded and replayed + bool graph_update_support; // a finalized command graph can be updated +#endif }; struct ggml_sycl_device_info { + int active_device_count; //the number of active devices in the application int device_count; sycl_device_info devices[GGML_SYCL_MAX_DEVICES] = {}; @@ -304,7 +351,11 @@ struct ggml_sycl_device_info { bool ext_oneapi_level_zero = true; // sycl::backend::ext_oneapi_level_zero used by all enumerated GPU devices }; -const ggml_sycl_device_info & ggml_sycl_info(); +ggml_sycl_device_info & ggml_sycl_info(); + +static inline bool ggml_sycl_xmx_enabled(int device) { + return g_ggml_sycl_enable_xmx_esimd && ggml_sycl_xmx_supports_arch(ggml_sycl_info().devices[device].hw_info.arch); +} static constexpr size_t SYCL_BUFFER_ALIGNMENT = 128; @@ -395,6 +446,32 @@ struct ggml_sycl_gg_tile { }; namespace sycl_ex = sycl::ext::oneapi::experimental; + +#ifdef GGML_SYCL_GRAPH +struct ggml_sycl_graph { + // src data/ne/nb are kept next to the node copy: the scheduler can hand back the same src + // pointer with different contents or shape, see https://github.com/ggml-org/llama.cpp/pull/21736 + struct node_properties { + ggml_tensor node; + void * node_src_data_ptrs[GGML_MAX_SRC]; + int64_t node_src_ne[GGML_MAX_SRC][GGML_MAX_DIMS]; + size_t node_src_nb[GGML_MAX_SRC][GGML_MAX_DIMS]; + }; + + std::unique_ptr> exec_graph = nullptr; + std::vector node_props; + bool warmup_complete = false; + uint64_t uid = 0; + int64_t last_used_time = 0; + + // result of check_graph_compatibility() and the uid it was made for + bool compatible = false; + uint64_t compatible_uid = 0; +}; + +static_assert(std::is_trivial::value, "node_properties must be trivial"); +#endif + struct ggml_backend_sycl_context { int device; std::string name; @@ -489,7 +566,36 @@ struct ggml_backend_sycl_context { } #ifdef GGML_SYCL_GRAPH - std::unique_ptr> exec_graph = nullptr; + // Map from first node pointer to graph - allows multiple graphs per context when the + // computation is split across CPU/GPU (e.g. with --n-cpu-moe) + std::unordered_map> sycl_graphs; + + int64_t last_graph_eviction_sweep = 0; + std::optional graph_compatible; + + ggml_sycl_graph * sycl_graph(const void * first_node_ptr) { + const int64_t time_now = ggml_time_us(); + const int64_t eviction_timeout_us = g_ggml_sycl_graph_eviction_timeout * 1'000'000LL; + + // sweep every half the eviction timeout, evicting graphs unused for >= the eviction timeout + if (time_now - last_graph_eviction_sweep >= eviction_timeout_us / 2) { + last_graph_eviction_sweep = time_now; + for (auto it = sycl_graphs.begin(); it != sycl_graphs.end(); ) { + if (time_now - it->second->last_used_time >= eviction_timeout_us) { + it = sycl_graphs.erase(it); + } else { + ++it; + } + } + } + + auto it = sycl_graphs.find(first_node_ptr); + if (it == sycl_graphs.end()) { + it = sycl_graphs.emplace(first_node_ptr, std::make_unique()).first; + } + it->second->last_used_time = time_now; + return it->second.get(); + } #endif ggml_sycl_pool & host_pool(int device) { diff --git a/ggml/src/ggml-sycl/concat.cpp b/ggml/src/ggml-sycl/concat.cpp index bd5f3b2ceb30..77a17412ff58 100644 --- a/ggml/src/ggml-sycl/concat.cpp +++ b/ggml/src/ggml-sycl/concat.cpp @@ -196,7 +196,8 @@ void concat_impl_sycl(ggml_backend_sycl_context & ctx, ggml_tensor *dst) { } } -static void concat_impl_q4_0_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { +template +static void concat_impl_q_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; @@ -204,25 +205,25 @@ static void concat_impl_q4_0_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * const int32_t dim = ((int32_t *) dst->op_params)[0]; - GGML_ASSERT(src0->type == GGML_TYPE_Q4_0); - GGML_ASSERT(src1->type == GGML_TYPE_Q4_0); - GGML_ASSERT(dst->type == GGML_TYPE_Q4_0); - GGML_ASSERT(src0->ne[0] % QK4_0 == 0); - GGML_ASSERT(src1->ne[0] % QK4_0 == 0); - GGML_ASSERT(dst->ne[0] % QK4_0 == 0); + GGML_ASSERT(src0->type == qtype); + GGML_ASSERT(src1->type == qtype); + GGML_ASSERT(dst->type == qtype); + GGML_ASSERT(src0->ne[0] % qk == 0); + GGML_ASSERT(src1->ne[0] % qk == 0); + GGML_ASSERT(dst->ne[0] % qk == 0); - const int ne00_blk = src0->ne[0] / QK4_0; - const int ne0_blk = dst->ne[0] / QK4_0; + const int ne00_blk = src0->ne[0] / qk; + const int ne0_blk = dst->ne[0] / qk; if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - const block_q4_0 * src0_d = (const block_q4_0 *) src0->data; - const block_q4_0 * src1_d = (const block_q4_0 *) src1->data; - block_q4_0 * dst_d = (block_q4_0 *) dst->data; - const size_t type_size = sizeof(block_q4_0); + const block_t * src0_d = (const block_t *) src0->data; + const block_t * src1_d = (const block_t *) src1->data; + block_t * dst_d = (block_t *) dst->data; + const size_t type_size = sizeof(block_t); if (dim != 3) { for (int i3 = 0; i3 < dst->ne[3]; i3++) { - concat_T_sycl( + concat_T_sycl( src0_d + i3 * (src0->nb[3] / type_size), src1_d + i3 * (src1->nb[3] / type_size), dst_d + i3 * (dst->nb[3] / type_size), @@ -237,223 +238,12 @@ static void concat_impl_q4_0_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy((char *) dst_d + size0, src1_d, size1))); } } else { - concat_T_sycl_non_cont( + concat_T_sycl_non_cont( stream, (const char *) src0->data, (const char *) src1->data, (char *) dst->data, ne00_blk, src0->ne[1], src0->ne[2], src0->ne[3], src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], - src1->ne[0] / QK4_0, src1->ne[1], src1->ne[2], src1->ne[3], - src1->nb[0], src1->nb[1], src1->nb[2], src1->nb[3], - ne0_blk, dst->ne[1], dst->ne[2], dst->ne[3], - dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], dim); - } -} - -static void concat_impl_q4_1_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { - scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - queue_ptr stream = ctx.stream(); - - const int32_t dim = ((int32_t *) dst->op_params)[0]; - - GGML_ASSERT(src0->type == GGML_TYPE_Q4_1); - GGML_ASSERT(src1->type == GGML_TYPE_Q4_1); - GGML_ASSERT(dst->type == GGML_TYPE_Q4_1); - GGML_ASSERT(src0->ne[0] % QK4_1 == 0); - GGML_ASSERT(src1->ne[0] % QK4_1 == 0); - GGML_ASSERT(dst->ne[0] % QK4_1 == 0); - - const int ne00_blk = src0->ne[0] / QK4_1; - const int ne0_blk = dst->ne[0] / QK4_1; - - if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - const block_q4_1 * src0_d = (const block_q4_1 *) src0->data; - const block_q4_1 * src1_d = (const block_q4_1 *) src1->data; - block_q4_1 * dst_d = (block_q4_1 *) dst->data; - const size_t type_size = sizeof(block_q4_1); - - if (dim != 3) { - for (int i3 = 0; i3 < dst->ne[3]; i3++) { - concat_T_sycl( - src0_d + i3 * (src0->nb[3] / type_size), - src1_d + i3 * (src1->nb[3] / type_size), - dst_d + i3 * (dst->nb[3] / type_size), - ne00_blk, src0->ne[1], src0->ne[2], ne0_blk, - dst->ne[1], dst->ne[2], dim, stream); - } - } else { - const size_t size0 = ggml_nbytes(src0); - const size_t size1 = ggml_nbytes(src1); - - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy(dst_d, src0_d, size0))); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy((char *) dst_d + size0, src1_d, size1))); - } - } else { - concat_T_sycl_non_cont( - stream, (const char *) src0->data, (const char *) src1->data, - (char *) dst->data, - ne00_blk, src0->ne[1], src0->ne[2], src0->ne[3], - src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], - src1->ne[0] / QK4_1, src1->ne[1], src1->ne[2], src1->ne[3], - src1->nb[0], src1->nb[1], src1->nb[2], src1->nb[3], - ne0_blk, dst->ne[1], dst->ne[2], dst->ne[3], - dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], dim); - } -} - -static void concat_impl_q5_0_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { - scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - queue_ptr stream = ctx.stream(); - - const int32_t dim = ((int32_t *) dst->op_params)[0]; - - GGML_ASSERT(src0->type == GGML_TYPE_Q5_0); - GGML_ASSERT(src1->type == GGML_TYPE_Q5_0); - GGML_ASSERT(dst->type == GGML_TYPE_Q5_0); - GGML_ASSERT(src0->ne[0] % QK5_0 == 0); - GGML_ASSERT(src1->ne[0] % QK5_0 == 0); - GGML_ASSERT(dst->ne[0] % QK5_0 == 0); - - const int ne00_blk = src0->ne[0] / QK5_0; - const int ne0_blk = dst->ne[0] / QK5_0; - - if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - const block_q5_0 * src0_d = (const block_q5_0 *) src0->data; - const block_q5_0 * src1_d = (const block_q5_0 *) src1->data; - block_q5_0 * dst_d = (block_q5_0 *) dst->data; - const size_t type_size = sizeof(block_q5_0); - - if (dim != 3) { - for (int i3 = 0; i3 < dst->ne[3]; i3++) { - concat_T_sycl( - src0_d + i3 * (src0->nb[3] / type_size), - src1_d + i3 * (src1->nb[3] / type_size), - dst_d + i3 * (dst->nb[3] / type_size), - ne00_blk, src0->ne[1], src0->ne[2], ne0_blk, - dst->ne[1], dst->ne[2], dim, stream); - } - } else { - const size_t size0 = ggml_nbytes(src0); - const size_t size1 = ggml_nbytes(src1); - - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy(dst_d, src0_d, size0))); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy((char *) dst_d + size0, src1_d, size1))); - } - } else { - concat_T_sycl_non_cont( - stream, (const char *) src0->data, (const char *) src1->data, - (char *) dst->data, - ne00_blk, src0->ne[1], src0->ne[2], src0->ne[3], - src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], - src1->ne[0] / QK5_0, src1->ne[1], src1->ne[2], src1->ne[3], - src1->nb[0], src1->nb[1], src1->nb[2], src1->nb[3], - ne0_blk, dst->ne[1], dst->ne[2], dst->ne[3], - dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], dim); - } -} - -static void concat_impl_q5_1_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { - scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - queue_ptr stream = ctx.stream(); - - const int32_t dim = ((int32_t *) dst->op_params)[0]; - - GGML_ASSERT(src0->type == GGML_TYPE_Q5_1); - GGML_ASSERT(src1->type == GGML_TYPE_Q5_1); - GGML_ASSERT(dst->type == GGML_TYPE_Q5_1); - GGML_ASSERT(src0->ne[0] % QK5_1 == 0); - GGML_ASSERT(src1->ne[0] % QK5_1 == 0); - GGML_ASSERT(dst->ne[0] % QK5_1 == 0); - - const int ne00_blk = src0->ne[0] / QK5_1; - const int ne0_blk = dst->ne[0] / QK5_1; - - if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - const block_q5_1 * src0_d = (const block_q5_1 *) src0->data; - const block_q5_1 * src1_d = (const block_q5_1 *) src1->data; - block_q5_1 * dst_d = (block_q5_1 *) dst->data; - const size_t type_size = sizeof(block_q5_1); - - if (dim != 3) { - for (int i3 = 0; i3 < dst->ne[3]; i3++) { - concat_T_sycl( - src0_d + i3 * (src0->nb[3] / type_size), - src1_d + i3 * (src1->nb[3] / type_size), - dst_d + i3 * (dst->nb[3] / type_size), - ne00_blk, src0->ne[1], src0->ne[2], ne0_blk, - dst->ne[1], dst->ne[2], dim, stream); - } - } else { - const size_t size0 = ggml_nbytes(src0); - const size_t size1 = ggml_nbytes(src1); - - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy(dst_d, src0_d, size0))); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy((char *) dst_d + size0, src1_d, size1))); - } - } else { - concat_T_sycl_non_cont( - stream, (const char *) src0->data, (const char *) src1->data, - (char *) dst->data, - ne00_blk, src0->ne[1], src0->ne[2], src0->ne[3], - src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], - src1->ne[0] / QK5_1, src1->ne[1], src1->ne[2], src1->ne[3], - src1->nb[0], src1->nb[1], src1->nb[2], src1->nb[3], - ne0_blk, dst->ne[1], dst->ne[2], dst->ne[3], - dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], dim); - } -} - -static void concat_impl_q8_0_sycl(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { - scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - queue_ptr stream = ctx.stream(); - - const int32_t dim = ((int32_t *) dst->op_params)[0]; - - GGML_ASSERT(src0->type == GGML_TYPE_Q8_0); - GGML_ASSERT(src1->type == GGML_TYPE_Q8_0); - GGML_ASSERT(dst->type == GGML_TYPE_Q8_0); - GGML_ASSERT(src0->ne[0] % QK8_0 == 0); - GGML_ASSERT(src1->ne[0] % QK8_0 == 0); - GGML_ASSERT(dst->ne[0] % QK8_0 == 0); - - const int ne00_blk = src0->ne[0] / QK8_0; - const int ne0_blk = dst->ne[0] / QK8_0; - - if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { - const block_q8_0 * src0_d = (const block_q8_0 *) src0->data; - const block_q8_0 * src1_d = (const block_q8_0 *) src1->data; - block_q8_0 * dst_d = (block_q8_0 *) dst->data; - const size_t type_size = sizeof(block_q8_0); - - if (dim != 3) { - for (int i3 = 0; i3 < dst->ne[3]; i3++) { - concat_T_sycl( - src0_d + i3 * (src0->nb[3] / type_size), - src1_d + i3 * (src1->nb[3] / type_size), - dst_d + i3 * (dst->nb[3] / type_size), - ne00_blk, src0->ne[1], src0->ne[2], ne0_blk, - dst->ne[1], dst->ne[2], dim, stream); - } - } else { - const size_t size0 = ggml_nbytes(src0); - const size_t size1 = ggml_nbytes(src1); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy(dst_d, src0_d, size0))); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy((char *) dst_d + size0, src1_d, size1))); - } - } else { - concat_T_sycl_non_cont( - stream, (const char *) src0->data, (const char *) src1->data, - (char *) dst->data, - ne00_blk, src0->ne[1], src0->ne[2], src0->ne[3], - src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], - src1->ne[0] / QK8_0, src1->ne[1], src1->ne[2], src1->ne[3], + src1->ne[0] / qk, src1->ne[1], src1->ne[2], src1->ne[3], src1->nb[0], src1->nb[1], src1->nb[2], src1->nb[3], ne0_blk, dst->ne[1], dst->ne[2], dst->ne[3], dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], dim); @@ -487,23 +277,22 @@ void ggml_sycl_op_concat(ggml_backend_sycl_context & ctx, ggml_tensor *dst) { concat_impl_sycl(ctx, dst); break; case GGML_TYPE_Q4_0: - concat_impl_q4_0_sycl(ctx, dst); + concat_impl_q_sycl(ctx, dst); break; case GGML_TYPE_Q4_1: - concat_impl_q4_1_sycl(ctx, dst); + concat_impl_q_sycl(ctx, dst); break; case GGML_TYPE_Q5_0: - concat_impl_q5_0_sycl(ctx, dst); + concat_impl_q_sycl(ctx, dst); break; case GGML_TYPE_Q5_1: - concat_impl_q5_1_sycl(ctx, dst); + concat_impl_q_sycl(ctx, dst); break; case GGML_TYPE_Q8_0: - concat_impl_q8_0_sycl(ctx, dst); + concat_impl_q_sycl(ctx, dst); break; default: fprintf(stderr, "%s: unsupported types: dst: %s\n", __func__, ggml_type_name(dst->type)); GGML_ASSERT(false); - break; } } diff --git a/ggml/src/ggml-sycl/conv2d.cpp b/ggml/src/ggml-sycl/conv2d.cpp index 3b3b49d05d3c..d13ba97234ef 100644 --- a/ggml/src/ggml-sycl/conv2d.cpp +++ b/ggml/src/ggml-sycl/conv2d.cpp @@ -53,7 +53,16 @@ static inline int64_t whcn_output_index(int64_t n, int64_t c, int64_t y, int64_t return n * (P.OC * P.OW * P.OH) + c * P.OW * P.OH + y * P.OW + x; } -template +// cwhn layout helpers: buffers are [N][H][W][C] input and [KH][KW][IC][OC] kernel +static inline int64_t cwhn_input_index(int64_t n, int64_t c, int64_t y, int64_t x, const conv2d_params & P) { + return ((n * P.IH + y) * P.IW + x) * P.IC + c; +} + +static inline int64_t cwhn_kernel_index(int64_t c_out, int64_t c_in, int64_t ky, int64_t kx, const conv2d_params & P) { + return ((ky * P.KW + kx) * P.IC + c_in) * P.OC + c_out; +} + +template static void conv2d_kernel(const float * input, const T * kernel, float * output, const conv2d_params P, const sycl::nd_item<3> & item_ct1) { const int64_t global_idx = item_ct1.get_local_id(2) + @@ -77,8 +86,8 @@ static void conv2d_kernel(const float * input, const T * kernel, float * output, const int64_t in_y = calculate_input_coord(out_y, ky, P.ST_Y, P.DL_Y, P.PD_Y); for (int64_t kx = bounds.x_min; kx < bounds.x_max; ++kx) { const int64_t in_x = calculate_input_coord(out_x, kx, P.ST_X, P.DL_X, P.PD_X); - const float input_val = input[whcn_input_index(n, c_in, in_y, in_x, P)]; - const T kernel_val = kernel[whcn_kernel_index(c_out, c_in, ky, kx, P)]; + const float input_val = input[CWHN ? cwhn_input_index(n, c_in, in_y, in_x, P) : whcn_input_index(n, c_in, in_y, in_x, P)]; + const T kernel_val = kernel[CWHN ? cwhn_kernel_index(c_out, c_in, ky, kx, P) : whcn_kernel_index(c_out, c_in, ky, kx, P)]; acc += input_val * ggml_sycl_cast(kernel_val); } } @@ -87,7 +96,7 @@ static void conv2d_kernel(const float * input, const T * kernel, float * output, output[whcn_output_index(n, c_out, out_y, out_x, P)] = acc; } -template +template static void conv2d_sycl(const float * X_D, const T * K_D, float * Y_D, const conv2d_params P, const queue_ptr & stream) { const int num_blocks = (P.TOTAL + SYCL_CONV2D_BLOCK_SIZE - 1) / SYCL_CONV2D_BLOCK_SIZE; @@ -95,7 +104,7 @@ static void conv2d_sycl(const float * X_D, const T * K_D, float * Y_D, const sycl::range<3> block_nums(1, 1, num_blocks); stream->parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { - conv2d_kernel(X_D, K_D, Y_D, P, item_ct1); + conv2d_kernel(X_D, K_D, Y_D, P, item_ct1); }); } @@ -108,7 +117,14 @@ void ggml_sycl_op_conv2d(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { const float * X_D = (const float *) input->data; float * Y_D = (float *) dst->data; - GGML_ASSERT(ggml_is_contiguous(kernel)); + // WHCN: contiguous [KW,KH,IC,OC] kernel and [W,H,C,N] input + // CWHN: channel-fastest buffer [N][H][W][C] input and [KH][KW][IC][OC] kernel (OC fastest) + const bool whcn = ggml_is_contiguous(kernel) && ggml_is_contiguous(input); + const bool cwhn = input->nb[2] == ggml_type_size(input->type) && + kernel->nb[3] == ggml_type_size(kernel->type); + GGML_ASSERT(whcn || cwhn); + const bool cwhn_layout = !whcn && cwhn; // prefer whcn when both match (degenerate size-1 dims) + GGML_ASSERT(kernel->type == GGML_TYPE_F16 || kernel->type == GGML_TYPE_F32); GGML_ASSERT(input->type == GGML_TYPE_F32); GGML_ASSERT(dst->type == GGML_TYPE_F32); @@ -126,9 +142,6 @@ void ggml_sycl_op_conv2d(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { const int DL_X = p[4]; const int DL_Y = p[5]; - // no cwhn layout support - GGML_ASSERT(p[6] == 0); - const int IW = input->ne[0]; const int IH = input->ne[1]; const int OW = dst->ne[0]; @@ -142,9 +155,17 @@ void ggml_sycl_op_conv2d(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { const int64_t total = (int64_t) B * OC * OH * OW; const conv2d_params params = { IW, IH, OW, OH, KW, KH, ST_X, ST_Y, PD_X, PD_Y, DL_X, DL_Y, IC, OC, B, total }; - if (kernel->type == GGML_TYPE_F16) { - conv2d_sycl(X_D, (const sycl::half *) K_D, Y_D, params, stream); + if (cwhn_layout) { + if (kernel->type == GGML_TYPE_F16) { + conv2d_sycl(X_D, (const sycl::half *) K_D, Y_D, params, stream); + } else { + conv2d_sycl(X_D, K_D, Y_D, params, stream); + } } else { - conv2d_sycl(X_D, K_D, Y_D, params, stream); + if (kernel->type == GGML_TYPE_F16) { + conv2d_sycl(X_D, (const sycl::half *) K_D, Y_D, params, stream); + } else { + conv2d_sycl(X_D, K_D, Y_D, params, stream); + } } } diff --git a/ggml/src/ggml-sycl/convert.cpp b/ggml/src/ggml-sycl/convert.cpp index 08eca7a36a12..1e7edf3b8a82 100644 --- a/ggml/src/ggml-sycl/convert.cpp +++ b/ggml/src/ggml-sycl/convert.cpp @@ -85,7 +85,7 @@ static void dequantize_row_q2_K_sycl_reorder(const void *vx, dst_t *y, const int stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q2_K_reorder(vx, y, item_ct1, nb); + dequantize_block_q2_K_reorder(vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), item_ct1, nb); }); } @@ -129,7 +129,7 @@ static void dequantize_row_q3_K_sycl_reorder(const void *vx, dst_t *y, const int stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q3_K_reorder(vx, y, item_ct1, nb); + dequantize_block_q3_K_reorder(vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), item_ct1, nb); }); } @@ -158,16 +158,13 @@ static void dequantize_row_q4_0_sycl_reorder(const void *vx, dst_t *y, const int dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - int constexpr WARP_K = WARP_SIZE * QK4_0; - const int n_warp = (k + WARP_K - 1) / WARP_K; - GGML_ASSERT(k % 2 == 0); - stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, n_warp) * - sycl::range<3>(1, 1, WARP_SIZE), - sycl::range<3>(1, 1, WARP_SIZE)), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]]{ - dequantize_block_q4_0_reorder(vx, y, k, item_ct1); + // flat range<1>, four qs bytes (8 outputs) per item: two vectorized stores. + // k % QK4_0 == 0 gives whole 32-element blocks, so the k/8 launch covers every row exactly. + GGML_ASSERT(k % QK4_0 == 0); + stream->parallel_for(sycl::range<1>((size_t) (k / 8)), + [=](sycl::id<1> idx) { + dequantize_block_q4_0_reorder_wide(vx, y, k, idx); }); - } template @@ -177,16 +174,13 @@ static void dequantize_row_q8_0_sycl_reorder(const void *vx, dst_t *y, const int dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - int constexpr WARP_K = WARP_SIZE * QK8_0; - const int n_warp = (k + WARP_K - 1) / WARP_K; + // flat range<1>, two pairs (4 elements) per item: no nd_range/group math, one vectorized store. + // k % QK8_0 == 0 implies k % 4 == 0, so the wide launch covers the row exactly (no tail). GGML_ASSERT(k % QK8_0 == 0); - stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, n_warp) * - sycl::range<3>(1, 1, WARP_SIZE), - sycl::range<3>(1, 1, WARP_SIZE)), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]]{ - dequantize_block_q8_0_reorder(vx, y, k, item_ct1); + stream->parallel_for(sycl::range<1>((size_t) (k / 4)), + [=](sycl::id<1> idx) { + dequantize_block_q8_0_reorder_wide(vx, y, k, idx); }); - } template @@ -212,20 +206,10 @@ template static void dequantize_row_q4_K_sycl(const void *vx, dst_t *y, const int64_t k, dpct::queue_ptr stream) { const int64_t nb = k / QK_K; - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor scale_local_acc(sycl::range<1>(12), cgh); - cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * - sycl::range<3>(1, 1, 32), - sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q4_K(vx, y, get_pointer(scale_local_acc), item_ct1); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); + stream->parallel_for(sycl::nd_range<1>(sycl::range<1>((size_t) nb * SYCL_DEQK_WI_PER_BLOCK), + sycl::range<1>((size_t) SYCL_DEQK_WI_PER_BLOCK)), + [=](sycl::nd_item<1> it) { dequantize_block_q4_K_wide(vx, y, nb, it); }); } template @@ -241,7 +225,7 @@ static void dequantize_row_q4_K_sycl_reorder(const void * vx, dst_t * y, const i cgh.parallel_for(sycl::nd_range<1>(sycl::range<1>(global_size), sycl::range<1>(local_size)), [=](sycl::nd_item<1> item_ct1) { - dequantize_block_q4_K_reorder(vx, y, get_pointer(scale_local_acc), item_ct1, nb); + dequantize_block_q4_K_reorder(vx, y + item_ct1.get_group(0) * QK_K, item_ct1.get_group(0), get_pointer(scale_local_acc), item_ct1, nb); }); }); } @@ -250,32 +234,10 @@ template static void dequantize_row_q5_K_sycl(const void *vx, dst_t *y, const int64_t k, dpct::queue_ptr stream) { const int64_t nb = k / QK_K; -#if QK_K == 256 - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * - sycl::range<3>(1, 1, 64), - sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q5_K(vx, y, item_ct1); - }); - } -#else - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * - sycl::range<3>(1, 1, 32), - sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q5_K(vx, y, item_ct1); - }); - } - -#endif + dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); + stream->parallel_for(sycl::nd_range<1>(sycl::range<1>((size_t) nb * SYCL_DEQK_WI_PER_BLOCK), + sycl::range<1>((size_t) SYCL_DEQK_WI_PER_BLOCK)), + [=](sycl::nd_item<1> it) { dequantize_block_q5_K_wide(vx, y, nb, it); }); } template @@ -288,9 +250,9 @@ static void dequantize_row_q5_K_sycl_reorder(const void * vx, dst_t * y, const i sycl::local_accessor scale_local_acc(sycl::range<1>(K_SCALE_SIZE), cgh); cgh.parallel_for( - sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), + sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q5_K_reorder(vx, y, get_pointer(scale_local_acc), item_ct1, nb); + dequantize_block_q5_K_reorder(vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), get_pointer(scale_local_acc), item_ct1, nb); }); }); } @@ -335,7 +297,7 @@ static void dequantize_row_q6_K_sycl_reorder(const void * vx, dst_t * y, const i stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K_reorder(vx, y, item_ct1, nb); }); + [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K_reorder(vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), item_ct1, nb); }); } template @@ -472,7 +434,8 @@ static void dequantize_row_iq3_xxs_sycl_reorder(const void * vx, dst_t * y, cons sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq3_xxs_reorder( - vx, y, item_ct1, nb, iq3xxs_grid, ksigns_iq2xs, kmask_iq2xs); + vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), item_ct1, nb, + iq3xxs_grid, ksigns_iq2xs, kmask_iq2xs); }); } @@ -504,7 +467,8 @@ static void dequantize_row_iq3_s_sycl_reorder(const void * vx, dst_t * y, const stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), [=](sycl::nd_item<3> item_ct1) { - dequantize_block_iq3_s_reorder(vx, y, item_ct1, nb, kmask_iq2xs, iq3s_grid); + dequantize_block_iq3_s_reorder(vx, y + item_ct1.get_group(2) * QK_K, item_ct1.get_group(2), + item_ct1, nb, kmask_iq2xs, iq3s_grid); }); } @@ -564,13 +528,13 @@ static void dequantize_row_mxfp4_sycl(const void * vx, dst_t * y, const int64_t template static void dequantize_row_mxfp4_sycl_reorder(const void * vx, dst_t * y, const int64_t k, dpct::queue_ptr stream) { + // flat range<1>, four qs bytes (8 outputs) per item: two vectorized stores. + // Each 32-element block holds QK_MXFP4/2 = 16 qs bytes = 4 items, so the + // k/8 launch covers the row exactly (k % QK_MXFP4 == 0 asserted). GGML_ASSERT(k % QK_MXFP4 == 0); - const int n_warp = (k / QK_MXFP4 + WARP_SIZE - 1) / WARP_SIZE; - stream->parallel_for( - sycl::nd_range<3>(sycl::range<3>(1, 1, n_warp) * sycl::range<3>(1, 1, WARP_SIZE), - sycl::range<3>(1, 1, WARP_SIZE)), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_block_mxfp4_reorder(vx, y, k, item_ct1); + stream->parallel_for(sycl::range<1>((size_t) (k / 8)), + [=](sycl::id<1> idx) { + dequantize_block_mxfp4_reorder_wide(vx, y, k, idx); }); } @@ -690,58 +654,68 @@ static void convert_unary_sycl(const void * vx, dst_t * y, const int64_t k, dpct } -to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst) { +static bool is_reordered_src0(const ggml_tensor * dst) { + return dst->src[0]->extra && + ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder; +} + +template +static to_t_sycl_t ggml_get_dequant_sycl(ggml_type type, ggml_tensor * dst) { switch (type) { case GGML_TYPE_Q1_0: - return dequantize_block_sycl; + return dequantize_block_sycl; case GGML_TYPE_Q2_0: - return dequantize_block_sycl; + return dequantize_block_sycl; case GGML_TYPE_Q4_0: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q4_0_sycl_reorder; + } else if constexpr (std::is_same_v) { + return dequantize_row_q4_0_sycl; } else { - return dequantize_block_sycl; + return dequantize_block_sycl; } case GGML_TYPE_Q4_1: - return dequantize_block_sycl; + if constexpr (std::is_same_v) { + return dequantize_row_q4_1_sycl; + } else { + return dequantize_block_sycl; + } case GGML_TYPE_Q5_0: - return dequantize_block_sycl; + return dequantize_block_sycl; case GGML_TYPE_Q5_1: - return dequantize_block_sycl; + return dequantize_block_sycl; case GGML_TYPE_Q8_0: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q8_0_sycl_reorder; } else { - return dequantize_block_sycl; + return dequantize_block_sycl; } case GGML_TYPE_Q2_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q2_K_sycl_reorder; } else { return dequantize_row_q2_K_sycl; } case GGML_TYPE_Q3_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q3_K_sycl_reorder; } else { return dequantize_row_q3_K_sycl; } case GGML_TYPE_Q4_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q4_K_sycl_reorder; } else { return dequantize_row_q4_K_sycl; } case GGML_TYPE_Q5_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q5_K_sycl_reorder; } else { return dequantize_row_q5_K_sycl; } case GGML_TYPE_Q6_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_q6_K_sycl_reorder; } else { return dequantize_row_q6_K_sycl; @@ -757,15 +731,13 @@ to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst) { case GGML_TYPE_IQ2_S: return dequantize_row_iq2_s_sycl; case GGML_TYPE_IQ3_XXS: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_iq3_xxs_sycl_reorder; } else { return dequantize_row_iq3_xxs_sycl; } case GGML_TYPE_IQ3_S: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_iq3_s_sycl_reorder; } else { return dequantize_row_iq3_s_sycl; @@ -775,126 +747,38 @@ to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst) { case GGML_TYPE_IQ4_NL: return dequantize_row_iq4_nl_sycl; case GGML_TYPE_MXFP4: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { + if (is_reordered_src0(dst)) { return dequantize_row_mxfp4_sycl_reorder; } return dequantize_row_mxfp4_sycl; case GGML_TYPE_NVFP4: return dequantize_row_nvfp4_sycl; case GGML_TYPE_F32: - return convert_unary_sycl; + if constexpr (std::is_same_v) { + return convert_unary_sycl; + } + break; + case GGML_TYPE_F16: + if constexpr (std::is_same_v) { + return convert_unary_sycl; + } + break; #ifdef GGML_SYCL_HAS_BF16 case GGML_TYPE_BF16: return convert_unary_sycl; #endif default: - GGML_ABORT("fatal error: unsupport data type=%s\n", ggml_type_name(type)); - return nullptr; + break; } + GGML_ABORT("fatal error: unsupport data type=%s\n", ggml_type_name(type)); +} + +to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst) { + return ggml_get_dequant_sycl(type, dst); } to_fp32_sycl_t ggml_get_to_fp32_sycl(ggml_type type, ggml_tensor *dst) { - switch (type) { - case GGML_TYPE_Q1_0: - return dequantize_block_sycl; - case GGML_TYPE_Q2_0: - return dequantize_block_sycl; - case GGML_TYPE_Q4_0: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q4_0_sycl_reorder; - } else { - return dequantize_row_q4_0_sycl; - } - case GGML_TYPE_Q4_1: - return dequantize_row_q4_1_sycl; - case GGML_TYPE_Q5_0: - return dequantize_block_sycl; - case GGML_TYPE_Q5_1: - return dequantize_block_sycl; - case GGML_TYPE_Q8_0: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q8_0_sycl_reorder; - } else { - return dequantize_block_sycl; - } - case GGML_TYPE_Q2_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q2_K_sycl_reorder; - } else { - return dequantize_row_q2_K_sycl; - } - case GGML_TYPE_Q3_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q3_K_sycl_reorder; - } else { - return dequantize_row_q3_K_sycl; - } - case GGML_TYPE_Q4_K: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q4_K_sycl_reorder; - } else { - return dequantize_row_q4_K_sycl; - } - case GGML_TYPE_Q5_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q5_K_sycl_reorder; - } else { - return dequantize_row_q5_K_sycl; - } - case GGML_TYPE_Q6_K: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_q6_K_sycl_reorder; - } else { - return dequantize_row_q6_K_sycl; - } - case GGML_TYPE_IQ1_S: - return dequantize_row_iq1_s_sycl; - case GGML_TYPE_IQ1_M: - return dequantize_row_iq1_m_sycl; - case GGML_TYPE_IQ2_XXS: - return dequantize_row_iq2_xxs_sycl; - case GGML_TYPE_IQ2_XS: - return dequantize_row_iq2_xs_sycl; - case GGML_TYPE_IQ2_S: - return dequantize_row_iq2_s_sycl; - case GGML_TYPE_IQ3_XXS: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_iq3_xxs_sycl_reorder; - } else { - return dequantize_row_iq3_xxs_sycl; - } - case GGML_TYPE_IQ3_S: - if (dst->src[0]->extra && - ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_iq3_s_sycl_reorder; - } else { - return dequantize_row_iq3_s_sycl; - } - case GGML_TYPE_IQ4_XS: - return dequantize_row_iq4_xs_sycl; - case GGML_TYPE_IQ4_NL: - return dequantize_row_iq4_nl_sycl; - case GGML_TYPE_MXFP4: - if (dst->src[0]->extra && ((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) { - return dequantize_row_mxfp4_sycl_reorder; - } - return dequantize_row_mxfp4_sycl; - case GGML_TYPE_NVFP4: - return dequantize_row_nvfp4_sycl; - case GGML_TYPE_F16: - return convert_unary_sycl; -#ifdef GGML_SYCL_HAS_BF16 - case GGML_TYPE_BF16: - return convert_unary_sycl; -#endif - default: - GGML_ABORT("fatal error: unsupport data type=%s\n", ggml_type_name(type)); - return nullptr; - } + return ggml_get_dequant_sycl(type, dst); } @@ -909,7 +793,6 @@ to_bf16_sycl_t ggml_get_to_bf16_sycl(ggml_type type, ggml_tensor * /*dst*/) { return convert_unary_sycl; default: GGML_ABORT("fatal error: unsupport data type=%s\n", ggml_type_name(type)); - return nullptr; } } #endif diff --git a/ggml/src/ggml-sycl/count-equal.cpp b/ggml/src/ggml-sycl/count-equal.cpp index 4580354cd9d0..20126652baa1 100644 --- a/ggml/src/ggml-sycl/count-equal.cpp +++ b/ggml/src/ggml-sycl/count-equal.cpp @@ -74,6 +74,5 @@ void ggml_sycl_count_equal(ggml_backend_sycl_context &ctx, ggml_tensor *dst) { } break; default: GGML_ASSERT(false); - break; } } diff --git a/ggml/src/ggml-sycl/cpy.cpp b/ggml/src/ggml-sycl/cpy.cpp index ef7413abd880..8e1f1d50a934 100644 --- a/ggml/src/ggml-sycl/cpy.cpp +++ b/ggml/src/ggml-sycl/cpy.cpp @@ -1255,6 +1255,8 @@ void ggml_sycl_cpy(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, co scope_op_debug_print scope_dbg_print(__func__, src1, /*num_src=*/0, debug_get_tensor_str("\tsrc0", src0)); const int64_t ne = ggml_nelements(src0); GGML_ASSERT(ne == ggml_nelements(src1)); + // the cpy kernels index in 32-bit + GGML_ASSERT(ne <= INT32_MAX); GGML_TENSOR_BINARY_OP_LOCALS01; diff --git a/ggml/src/ggml-sycl/cpy.hpp b/ggml/src/ggml-sycl/cpy.hpp index 34bae1b2dd18..9d63960810bb 100644 --- a/ggml/src/ggml-sycl/cpy.hpp +++ b/ggml/src/ggml-sycl/cpy.hpp @@ -70,8 +70,22 @@ inline void cpy_blck_f32_q1_0(const char * cxi, char * cdsti) { } } -inline int round_nearest_int(float x) { - return (int)(x >= 0.0f ? x + 0.5f : x - 0.5f); +// exact roundf (half away from zero); x + 0.5f carries for x = 0.5 - 2^-25, and sycl::round is not exact under fast fp +inline int round_half_away_int(float x) { + const float t = sycl::trunc(x); + return (int) (sycl::fabs(x - t) >= 0.5f ? t + sycl::copysign(1.0f, x) : t); +} + +// correctly rounded a / b to match the CPU: fast fp gives an approximate reciprocal (~12% off by an ulp on B580), +// so pick the approximation or a neighbour by smallest exact FMA residual +inline float div_correctly_rounded(float a, float b) { + const float y = a / b; + const float lo = sycl::nextafter(y, -INFINITY); + const float hi = sycl::nextafter(y, INFINITY); + const float e = sycl::fabs(sycl::fma(-b, y, a)); + const float el = sycl::fabs(sycl::fma(-b, lo, a)); + const float eh = sycl::fabs(sycl::fma(-b, hi, a)); + return el < e && el <= eh ? lo : (eh < e ? hi : y); } inline void cpy_blck_f32_q2_0(const char * cxi, char * cdsti) { @@ -85,7 +99,7 @@ inline void cpy_blck_f32_q2_0(const char * cxi, char * cdsti) { } const float d = amax; - const float id = d > 0.0f ? 1.0f / d : 0.0f; + const float id = d > 0.0f ? div_correctly_rounded(1.0f, d) : 0.0f; dsti->d = d; @@ -94,7 +108,7 @@ inline void cpy_blck_f32_q2_0(const char * cxi, char * cdsti) { } for (int j = 0; j < QK2_0; ++j) { - int q = round_nearest_int(xi[j] * id) + 1; + int q = round_half_away_int(xi[j] * id) + 1; q = dpct::max(0, dpct::min(3, q)); const int byte_index = j / 4; @@ -378,7 +392,7 @@ inline void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { } const float d = vmax / -8; - const float id = d ? 1.0f / d : 0.0f; + const float id = d ? div_correctly_rounded(1.0f, d) : 0.0f; dsti->d = d; @@ -386,8 +400,9 @@ inline void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { const float x0 = xi[0 + j] * id; const float x1 = xi[QK4_0 / 2 + j] * id; - const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 8.5f)); - const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 8.5f)); + // no-op fmin stops x * id + 8.5f being fused into an FMA, so x * id is rounded as on the CPU + const uint8_t xi0 = dpct::min(15, (int8_t) (sycl::fmin(x0, 6.5f) + 8.5f)); + const uint8_t xi1 = dpct::min(15, (int8_t) (sycl::fmin(x1, 6.5f) + 8.5f)); dsti->qs[j] = xi0; dsti->qs[j] |= xi1 << 4; @@ -442,7 +457,7 @@ inline void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { } const float d = vmax / -16; - const float id = d ? 1.0f / d : 0.0f; + const float id = d ? div_correctly_rounded(1.0f, d) : 0.0f; dsti->d = d; @@ -451,8 +466,9 @@ inline void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { const float x0 = xi[0 + j] * id; const float x1 = xi[QK5_0 / 2 + j] * id; - const uint8_t xi0 = dpct::min(31, (int8_t) (x0 + 16.5f)); - const uint8_t xi1 = dpct::min(31, (int8_t) (x1 + 16.5f)); + // fmin: no FMA, see cpy_blck_f32_q4_0 + const uint8_t xi0 = dpct::min(31, (int8_t) (sycl::fmin(x0, 14.5f) + 16.5f)); + const uint8_t xi1 = dpct::min(31, (int8_t) (sycl::fmin(x1, 14.5f) + 16.5f)); dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); qh |= ((xi0 & 0x10u) >> 4) << (j + 0); diff --git a/ggml/src/ggml-sycl/dequantize.hpp b/ggml/src/ggml-sycl/dequantize.hpp index bc86d2c2af0c..eb94771d673f 100644 --- a/ggml/src/ggml-sycl/dequantize.hpp +++ b/ggml/src/ggml-sycl/dequantize.hpp @@ -817,62 +817,73 @@ static void dequantize_block_q4_0(const void * __restrict__ vx, dst_t * __restri } } +// four qs bytes per item, all inside one 32-element block: two vec stores. +// float math, same products as the scalar kernel; nibble order kept (lo at +0, hi at +16). template -static void dequantize_block_q4_0_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t nb32, - const sycl::nd_item<3> &item_ct1) { - - const int64_t i = item_ct1.get_group(2); - auto k=nb32; - // assume 32 threads - const int64_t tid = item_ct1.get_local_id(2); - const int lane_ib = i * WARP_SIZE + tid; - - if (lane_ib >= k / QK4_0) { - return; - } - - dst_t * y_ptr = yy + lane_ib * QK4_0; - - auto qs = (const uint8_t*)vx + lane_ib * QK4_0 / 2; - auto s_ptr = (const sycl::half*)((const uint8_t*)vx + k / 2) + lane_ib; - - const float d = float(*s_ptr); - -#pragma unroll - for (int l = 0; l < QK4_0 / 2; ++l) { - int vq = qs[l]; - y_ptr[l + 0] = d * ((vq & 0xF) - 8); - y_ptr[l + 16] = d * ((vq >> 4) - 8); - } - +static void dequantize_block_q4_0_reorder_wide(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t k, + const sycl::id<1> idx) { + const int64_t i = (int64_t) idx[0]; + const int64_t ib = i / 4; + const int64_t iqs = 4 * (i % 4); + + const uint8_t * qs = (const uint8_t *) vx; + const sycl::half * d_ptr = (const sycl::half *) ((const uint8_t *) vx + k/2); + + const float d = float(d_ptr[ib]); + const uint8_t * q = qs + ib*(QK4_0/2) + iqs; + + sycl::vec lo, hi; + lo[0] = d * ((q[0] & 0xF) - 8); + lo[1] = d * ((q[1] & 0xF) - 8); + lo[2] = d * ((q[2] & 0xF) - 8); + lo[3] = d * ((q[3] & 0xF) - 8); + hi[0] = d * ((q[0] >> 4) - 8); + hi[1] = d * ((q[1] >> 4) - 8); + hi[2] = d * ((q[2] >> 4) - 8); + hi[3] = d * ((q[3] >> 4) - 8); + + dst_t * yb = yy + ib*QK4_0 + iqs; + *reinterpret_cast *>(yb) = lo.convert(); + *reinterpret_cast *>(yb + QK4_0/2) = hi.convert(); } // Dequantize Q8_0 from reorder layout: [all qs (k bytes)][all d values] -// Each thread handles one block of QK8_0 elements. template static void dequantize_block_q8_0_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t k, const sycl::nd_item<3> &item_ct1) { - - const int64_t i = item_ct1.get_group(2); - const int64_t tid = item_ct1.get_local_id(2); - const int lane_ib = i * WARP_SIZE + tid; - - if (lane_ib >= k / QK8_0) { - return; + // two values per thread, like dequantize_block; the reorder layout keeps all qs contiguous + // grid-stride loop because the launcher may shrink the work-group to keep the global range below INT_MAX + // float math, not dequantize_q8_0_reorder: that helper computes in half with GGML_SYCL_F16, which changes f32 output + const int8_t * qs = (const int8_t *) vx; + const sycl::half * d_ptr = (const sycl::half *) ((const uint8_t *) vx + k); + const int64_t stride = 2 * item_ct1.get_local_range(2) * item_ct1.get_group_range(2); + + for (int64_t i = 2 * item_ct1.get_global_id(2); i < k; i += stride) { + const float d = float(d_ptr[i / QK8_0]); + + yy[i + 0] = d * qs[i + 0]; + yy[i + 1] = d * qs[i + 1]; } +} - dst_t * y_ptr = yy + lane_ib * QK8_0; +template +static void dequantize_block_q8_0_reorder_wide(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t k, + const sycl::id<1> idx) { + const int64_t i = 4 * (int64_t) idx[0]; - auto qs = (const int8_t*)vx + lane_ib * QK8_0; - auto s_ptr = (const sycl::half*)((const uint8_t*)vx + k) + lane_ib; + const int8_t * qs = (const int8_t *) vx; + const sycl::half * d_ptr = (const sycl::half *) ((const uint8_t *) vx + k); - const float d = float(*s_ptr); + const float d0 = float(d_ptr[i / QK8_0]); + const float d1 = float(d_ptr[(i + 2) / QK8_0]); -#pragma unroll - for (int l = 0; l < QK8_0; ++l) { - y_ptr[l] = d * qs[l]; - } + sycl::vec p; + p[0] = d0 * (float) qs[i + 0]; + p[1] = d0 * (float) qs[i + 1]; + p[2] = d1 * (float) qs[i + 2]; + p[3] = d1 * (float) qs[i + 3]; + *reinterpret_cast *>(yy + i) = p.convert(); } template @@ -944,10 +955,9 @@ static void dequantize_block_q2_K(const void * __restrict__ vx, dst_t * __restri } template -static void dequantize_block_q2_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +static void dequantize_block_q2_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t i, const sycl::nd_item<3> & item_ct1, int64_t n_blocks) { #if QK_K == 256 - const int64_t i = item_ct1.get_group(2); if (i >= n_blocks) { return; } @@ -962,22 +972,29 @@ static void dequantize_block_q2_K_reorder(const void * __restrict__ vx, dst_t * const ggml_half2 * dm = reinterpret_cast(base + dm_offset); const int64_t tid = item_ct1.get_local_id(2); - const int64_t n = tid / 32; - const int64_t l = tid - 32 * n; - const int64_t is = 8 * n + l / 16; + const int64_t n = tid / 32; // 128-element chunk: 0 or 1 + const int64_t eh0 = 4 * (tid - 32 * n); // base element within the chunk - const uint8_t q = qs[32 * n + l]; - dst_t * y = yy + i * QK_K + 128 * n; + const int shift = 2 * (eh0 / 32); // 2-bit lane: 0/2/4/6 + const uint8_t * q4 = qs + 32 * n + (eh0 & 31); + const uint8_t sc0 = scales[8 * n + eh0 / 16]; const float dall = (*dm)[0]; const float dmin = (*dm)[1]; - y[l+ 0] = dall * (scales[is+0] & 0xF) * ((q >> 0) & 3) - dmin * (scales[is+0] >> 4); - y[l+32] = dall * (scales[is+2] & 0xF) * ((q >> 2) & 3) - dmin * (scales[is+2] >> 4); - y[l+64] = dall * (scales[is+4] & 0xF) * ((q >> 4) & 3) - dmin * (scales[is+4] >> 4); - y[l+96] = dall * (scales[is+6] & 0xF) * ((q >> 6) & 3) - dmin * (scales[is+6] >> 4); + + // remapped decomposition: one aligned vec per thread instead of four + // scalars strided 32 apart; a 4-run shares one scale byte and one 2-bit lane, + // so the per-element math and output are identical to the scalar kernel. + sycl::vec v; +#pragma unroll + for (int j = 0; j < 4; ++j) { + v[j] = dall * (sc0 & 0xF) * ((q4[j] >> shift) & 3) - dmin * (sc0 >> 4); + } + *reinterpret_cast *>(yy + 128 * n + eh0) = v; #else GGML_UNUSED(vx); GGML_UNUSED(yy); + GGML_UNUSED(i); GGML_UNUSED(item_ct1); GGML_UNUSED(n_blocks); GGML_ABORT("Q2_K reorder dequantize not supported for QK_K != 256"); @@ -1040,10 +1057,9 @@ static void dequantize_block_q3_K(const void * __restrict__ vx, dst_t * __restri } template -static void dequantize_block_q3_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +static void dequantize_block_q3_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t i, const sycl::nd_item<3> & item_ct1, int64_t n_blocks) { #if QK_K == 256 - const int64_t i = item_ct1.get_group(2); if (i >= n_blocks) { return; } @@ -1080,16 +1096,20 @@ static void dequantize_block_q3_K_reorder(const void * __restrict__ vx, dst_t * const float dl = d_all * (us - 32); - dst_t * y = yy + i * QK_K + 128 * n + 32 * j; + dst_t * y = yy + 128 * n + 32 * j; const uint8_t * q = qs + 32 * n; const uint8_t * hm = hmask; - for (int l = l0; l < l0 + 4; ++l) { - y[l] = dl * ((int8_t) ((q[l] >> shift) & 3) - ((hm[l] & m) ? 0 : 4)); + sycl::vec v; +#pragma unroll + for (int jj = 0; jj < 4; ++jj) { + v[jj] = dl * ((int8_t) ((q[l0 + jj] >> shift) & 3) - ((hm[l0 + jj] & m) ? 0 : 4)); } + *reinterpret_cast *>(y + l0) = v; #else GGML_UNUSED(vx); GGML_UNUSED(yy); + GGML_UNUSED(i); GGML_UNUSED(item_ct1); GGML_UNUSED(n_blocks); GGML_ABORT("Q3_K reorder dequantize not supported for QK_K != 256"); @@ -1108,6 +1128,53 @@ static inline void get_scale_min_k4(int j, const uint8_t * q, uint8_t & d, uint8 } #endif +// Work-items that cover one 256-weight K-quant block: four 64-element chunks, 8 work-items +// per chunk, 4 qs bytes per work-item. +static constexpr int SYCL_DEQK_WI_PER_BLOCK = 32; + +template +static inline void dequantize_q4_K_wide_one(dst_t * __restrict__ y, const uint8_t * __restrict__ qs, + const uint8_t * __restrict__ scales, const float dall, + const float dmin, const int tid) { + const int il = tid >> 3; // 64-element chunk, 0..3 + const int ir = (tid & 7) * 4; // 4 qs bytes within the chunk + + uint8_t sc, m; + get_scale_min_k4(2 * il + 0, scales, sc, m); + const float d1 = dall * sc; + const float m1 = dmin * m; + get_scale_min_k4(2 * il + 1, scales, sc, m); + const float d2 = dall * sc; + const float m2 = dmin * m; + + const sycl::vec q = vec_aligned_load(qs + 32 * il + ir); + + sycl::vec lo, hi; +#pragma unroll + for (int l = 0; l < 4; ++l) { + lo[l] = d1 * (q[l] & 0xF) - m1; + hi[l] = d2 * (q[l] >> 4) - m2; + } + dst_t * yb = y + 64 * il + ir; + *reinterpret_cast *>(yb + 0) = lo; + *reinterpret_cast *>(yb + 32) = hi; +} + +template +static void dequantize_block_q4_K_wide(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t nb, + const sycl::nd_item<1> & it) { + static_assert(QK_K == 256, "wide K-quant dequant assumes QK_K == 256"); + const int64_t g = it.get_global_id(0); + const int64_t b = g / SYCL_DEQK_WI_PER_BLOCK; + const int tid = (int) (g % SYCL_DEQK_WI_PER_BLOCK); + if (b >= nb) { + return; + } + const block_q4_K * x = (const block_q4_K *) vx + b; + dequantize_q4_K_wide_one(yy + b * QK_K, x->qs, x->scales, (float) x->dm[0], (float) x->dm[1], tid); +} + + template inline void dequantize_q4_K_common(dst_t * __restrict__ y, const uint8_t * __restrict__ qs_ptr, const float dall, const float dmin, uint8_t * __restrict__ scales_local, int il, int ir) { @@ -1124,56 +1191,24 @@ inline void dequantize_q4_K_common(dst_t * __restrict__ y, const uint8_t * __res const float m2 = dmin * m; sycl::vec q_vec = vec_aligned_load(qs_ptr + 32 * il + n * ir); - for (int l = 0; l < n; ++l) { - y[l + 0] = d1 * (q_vec[l] & 0xF) - m1; - y[l + 32] = d2 * (q_vec[l] >> 4) - m2; - } -} - -template -static void dequantize_block_q4_K(const void * __restrict__ vx, dst_t * __restrict__ yy, - uint8_t* scales_local, const sycl::nd_item<3> &item_ct1) { - const block_q4_K * x = (const block_q4_K *) vx; - - const int64_t i = item_ct1.get_group(2); -#if QK_K == 256 - const int64_t tid = item_ct1.get_local_id(2); - const int64_t il = tid / 8; - const int64_t ir = tid % 8; - - dst_t * y = yy + i * QK_K + 64 * il + 4 * ir; - - const sycl::half2 dm = x[i].dm; - const float dall = dm[0]; - const float dmin = dm[1]; - - if (tid < 12) { - scales_local[tid] = x[i].scales[tid]; + sycl::vec lo, hi; + for (int l = 0; l < n; ++l) { + lo[l] = d1 * (q_vec[l] & 0xF) - m1; + hi[l] = d2 * (q_vec[l] >> 4) - m2; } - - item_ct1.barrier(sycl::access::fence_space::local_space); - dequantize_q4_K_common(y, x[i].qs, dall, dmin, scales_local, il, ir); -#else - const int64_t tid = item_ct1.get_local_id(2); - const uint8_t * q = x[i].qs; - dst_t * y = yy + i*QK_K; - const float d = (float)x[i].dm[0]; - const float m = (float)x[i].dm[1]; - y[tid+ 0] = d * (x[i].scales[0] & 0xF) * (q[tid] & 0xF) - m * (x[i].scales[0] >> 4); - y[tid+32] = d * (x[i].scales[1] & 0xF) * (q[tid] >> 4) - m * (x[i].scales[1] >> 4); -#endif + *reinterpret_cast *>(y + 0) = lo; + *reinterpret_cast *>(y + 32) = hi; } template -static void dequantize_block_q4_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, uint8_t * scales_local, - const sycl::nd_item<1> & item_ct1, int64_t nb) { - const int64_t i = item_ct1.get_group(0); // block index +static void dequantize_block_q4_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t i, + uint8_t * scales_local, const sycl::nd_item<1> & item_ct1, int64_t nb) { const int64_t tid = item_ct1.get_local_id(0); // thread index within block const int64_t il = tid / 8; const int64_t ir = tid % 8; - dst_t * y = yy + i * QK_K + 64 * il + 4 * ir; + dst_t * y = yy + 64 * il + 4 * ir; const uint8_t * base = static_cast(vx); const size_t qs_offset = i * (QK_K / 2); @@ -1195,67 +1230,67 @@ static void dequantize_block_q4_K_reorder(const void * __restrict__ vx, dst_t * dequantize_q4_K_common(y, qs_ptr, dall, dmin, scales_local, il, ir); } -template -static void dequantize_block_q5_K(const void * __restrict__ vx, dst_t * __restrict__ yy, - const sycl::nd_item<3> &item_ct1) { - const block_q5_K * x = (const block_q5_K *) vx; - - const int64_t i = item_ct1.get_group(2); - -#if QK_K == 256 - // assume 64 threads - this is very slightly better than the one below - const int64_t tid = item_ct1.get_local_id(2); - const int64_t il = tid/16; // il is in 0...3 - const int64_t ir = tid%16; // ir is in 0...15 - const int64_t is = 2*il; // is is in 0...6 +template +static inline void dequantize_q5_K_wide_one(dst_t * __restrict__ y, const uint8_t * __restrict__ qs, + const uint8_t * __restrict__ qh_ptr, + const uint8_t * __restrict__ scales, const float dall, + const float dmin, const int tid) { + const int il = tid >> 3; // 64-element chunk, 0..3 + const int ir = (tid & 7) * 4; // 4 qs bytes within the chunk; qh holds the 5th bit - dst_t * y = yy + i*QK_K + 64*il + 2*ir; + uint8_t sc, m; + get_scale_min_k4(2 * il + 0, scales, sc, m); + const float d1 = dall * sc; + const float m1 = dmin * m; + get_scale_min_k4(2 * il + 1, scales, sc, m); + const float d2 = dall * sc; + const float m2 = dmin * m; - const float dall = x[i].dm[0]; - const float dmin = x[i].dm[1]; + const sycl::vec q = vec_aligned_load(qs + 32 * il + ir); + const sycl::vec h = vec_aligned_load(qh_ptr + ir); - const uint8_t * ql = x[i].qs + 32*il + 2*ir; - const uint8_t * qh = x[i].qh + 2*ir; + const uint8_t hm1 = 1 << (2 * il); + const uint8_t hm2 = hm1 << 1; - uint8_t sc, m; - get_scale_min_k4(is + 0, x[i].scales, sc, m); - const float d1 = dall * sc; const float m1 = dmin * m; - get_scale_min_k4(is + 1, x[i].scales, sc, m); - const float d2 = dall * sc; const float m2 = dmin * m; + sycl::vec lo, hi; +#pragma unroll + for (int l = 0; l < 4; ++l) { + lo[l] = d1 * ((q[l] & 0xF) + ((h[l] & hm1) ? 16 : 0)) - m1; + hi[l] = d2 * ((q[l] >> 4) + ((h[l] & hm2) ? 16 : 0)) - m2; + } + dst_t * yb = y + 64 * il + ir; + *reinterpret_cast *>(yb + 0) = lo; + *reinterpret_cast *>(yb + 32) = hi; +} - uint8_t hm = 1 << (2*il); - y[ 0] = d1 * ((ql[ 0] & 0xF) + (qh[ 0] & hm ? 16 : 0)) - m1; - y[ 1] = d1 * ((ql[ 1] & 0xF) + (qh[ 1] & hm ? 16 : 0)) - m1; - hm <<= 1; - y[32] = d2 * ((ql[ 0] >> 4) + (qh[ 0] & hm ? 16 : 0)) - m2; - y[33] = d2 * ((ql[ 1] >> 4) + (qh[ 1] & hm ? 16 : 0)) - m2; -#else - const int64_t tid = item_ct1.get_local_id(2); - const uint8_t q = x[i].qs[tid]; - const int64_t im = tid/8; // 0...3 - const int64_t in = tid%8; // 0...7 - const int64_t is = tid/16; // 0 or 1 - const uint8_t h = x[i].qh[in] >> im; - const float d = x[i].d; - dst_t * y = yy + i*QK_K + tid; - y[ 0] = d * x[i].scales[is+0] * ((q & 0xF) - ((h >> 0) & 1 ? 0 : 16)); - y[32] = d * x[i].scales[is+2] * ((q >> 4) - ((h >> 4) & 1 ? 0 : 16)); -#endif +template +static void dequantize_block_q5_K_wide(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t nb, + const sycl::nd_item<1> & it) { + static_assert(QK_K == 256, "wide K-quant dequant assumes QK_K == 256"); + const int64_t g = it.get_global_id(0); + const int64_t b = g / SYCL_DEQK_WI_PER_BLOCK; + const int tid = (int) (g % SYCL_DEQK_WI_PER_BLOCK); + if (b >= nb) { + return; + } + const block_q5_K * x = (const block_q5_K *) vx + b; + dequantize_q5_K_wide_one(yy + b * QK_K, x->qs, x->qh, x->scales, (float) x->dm[0], (float) x->dm[1], tid); } template -static void dequantize_block_q5_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +static void dequantize_block_q5_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t ib, uint8_t * scales_local, const sycl::nd_item<3> & item_ct1, int64_t n_blocks) { - const int64_t ib = item_ct1.get_group(2); #if QK_K == 256 - // assume 64 threads + // remapped decomposition: 32 threads, each emitting two aligned vec + // from four consecutive ql/qh bytes; a 4-element run shares one scale pair, + // so the per-element math and output are identical to the 64-thread kernel. const int64_t tid = item_ct1.get_local_id(2); - const int64_t il = tid / 16; // 0...3 - const int64_t ir = tid % 16; // 0...15 + const int64_t il = tid / 8; // 0...3 + const int64_t ir = tid % 8; // 0...7 const int64_t is = 2 * il; - dst_t * y = yy + ib * QK_K + 64 * il + 2 * ir; + dst_t * y = yy + 64 * il + 4 * ir; const uint8_t * base = static_cast(vx); @@ -1273,8 +1308,8 @@ static void dequantize_block_q5_K_reorder(const void * __restrict__ vx, dst_t * const float dall = dm_values.x(); const float dmin = dm_values.y(); - const uint8_t * ql = qs_ptr + 32 * il + 2 * ir; - const uint8_t * qh = qh_ptr + 2 * ir; + const uint8_t * ql = qs_ptr + 32 * il + 4 * ir; // four consecutive bytes + const uint8_t * qh = qh_ptr + 4 * ir; // four consecutive bytes if (tid < K_SCALE_SIZE) { scales_local[tid] = scales_ptr[tid]; @@ -1288,12 +1323,18 @@ static void dequantize_block_q5_K_reorder(const void * __restrict__ vx, dst_t * get_scale_min_k4(is + 1, scales_local, sc, m); const float d2 = dall * sc; const float m2 = dmin * m; - uint8_t hm = 1 << (2 * il); - y[ 0] = d1 * ((ql[ 0] & 0xF) + (qh[ 0] & hm ? 16 : 0)) - m1; - y[ 1] = d1 * ((ql[ 1] & 0xF) + (qh[ 1] & hm ? 16 : 0)) - m1; - hm <<= 1; - y[32] = d2 * ((ql[ 0] >> 4) + (qh[ 0] & hm ? 16 : 0)) - m2; - y[33] = d2 * ((ql[ 1] >> 4) + (qh[ 1] & hm ? 16 : 0)) - m2; + const uint8_t hm_lo = 1 << (2 * il); + const uint8_t hm_hi = 1 << (2 * il + 1); + + sycl::vec lo, hi; +#pragma unroll + for (int j = 0; j < 4; ++j) { + lo[j] = d1 * ((ql[j] & 0xF) + (qh[j] & hm_lo ? 16 : 0)) - m1; + hi[j] = d2 * ((ql[j] >> 4) + (qh[j] & hm_hi ? 16 : 0)) - m2; + } + + *reinterpret_cast *>(y + 0) = lo; + *reinterpret_cast *>(y + 32) = hi; #else GGML_UNUSED(ib); GGML_UNUSED(tid); GGML_UNUSED(yy); GGML_UNUSED(scales_local); GGML_UNUSED(n_blocks); GGML_ABORT("Q5_K reorder dequantize not supported for QK_K != 256"); @@ -1347,14 +1388,15 @@ static void dequantize_block_q6_K(const void * __restrict__ vx, dst_t * __restri } template -static void dequantize_block_q6_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +static void dequantize_block_q6_K_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t ib, const sycl::nd_item<3> & item_ct1, int64_t n_blocks) { - const int64_t ib = item_ct1.get_group(2); - + // remapped decomposition: each of the 64 threads emits one aligned vec + // instead of four scalars strided 32 apart. The four elements of a run share one + // 16-element scale group, one ql nibble source and one qh bit pair, so the + // per-element math and the output are identical to the scalar kernel. const int64_t tid = item_ct1.get_local_id(2); - const int64_t ip = tid / 32; // ip is 0 or 1 - const int64_t il = tid - 32 * ip; // 0...32 - const int64_t is = 8 * ip + il / 16; + const int64_t ip = tid / 32; // 128-element half: 0 or 1 + const int64_t eh0 = 4 * (tid - 32 * ip); // base element within the half const uint8_t * base_ptr = static_cast(vx); const auto ql_offset = ib * (QK_K / 2); @@ -1366,16 +1408,18 @@ static void dequantize_block_q6_K_reorder(const void * __restrict__ vx, dst_t * const uint8_t * scales_ptr = base_ptr + base_scales_offset; const ggml_half * d = (const ggml_half *) (base_ptr + base_d_offset) + ib; - dst_t * y = yy + ib * QK_K + 128 * ip + il; + const int shift = eh0 >= 64 ? 4 : 0; // low or high ql nibble + const int qb = 2 * (eh0 / 32); // qh bit pair: 0/2/4/6 + const int8_t sc0 = reinterpret_cast(scales_ptr + 8 * ip + eh0 / 16)[0]; + const uint8_t * ql4 = ql_ptr + 64 * ip + (eh0 & 63); + const uint8_t * qh4 = qh_ptr + 32 * ip + (eh0 & 31); - const uint8_t * ql = ql_ptr + 64 * ip + il; - const uint8_t qh = *(qh_ptr + 32 * ip + il); - const int8_t * sc = reinterpret_cast(scales_ptr + is); - - y[0] = *d * sc[0] * ((int8_t) ((ql[0] & 0xF) | (((qh >> 0) & 3) << 4)) - 32); - y[32] = *d * sc[2] * ((int8_t) ((ql[32] & 0xF) | (((qh >> 2) & 3) << 4)) - 32); - y[64] = *d * sc[4] * ((int8_t) ((ql[0] >> 4) | (((qh >> 4) & 3) << 4)) - 32); - y[96] = *d * sc[6] * ((int8_t) ((ql[32] >> 4) | (((qh >> 6) & 3) << 4)) - 32); + sycl::vec v; +#pragma unroll + for (int j = 0; j < 4; ++j) { + v[j] = *d * sc0 * ((int8_t) (((ql4[j] >> shift) & 0xF) | ((((qh4[j] >> qb) & 3)) << 4)) - 32); + } + *reinterpret_cast *>(yy + 128 * ip + eh0) = v; } template @@ -1491,12 +1535,11 @@ static void dequantize_block_iq3_xxs(const void * __restrict__ vx, dst_t * __res } template -static void dequantize_block_iq3_xxs_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +static void dequantize_block_iq3_xxs_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t i, const sycl::nd_item<3> & item_ct1, const int64_t nb, const uint32_t * iq3xxs_grid, const uint8_t * ksigns_iq2xs, const uint8_t * kmask_iq2xs) { - const int64_t i = item_ct1.get_group(2); const int64_t tid = item_ct1.get_local_id(2); #if QK_K == 256 const int64_t il = tid / 8; @@ -1511,15 +1554,19 @@ static void dequantize_block_iq3_xxs_reorder(const void * __restrict__ vx, dst_t const uint32_t aux32 = gas[0] | (gas[1] << 16); const float dl = (float) d[i] * (0.5f + (aux32 >> 28)) * 0.5f; const uint8_t signs = ksigns_iq2xs[(aux32 >> (7 * il)) & 127]; - dst_t * y = yy + i * QK_K + 32 * ib + 8 * il; + dst_t * y = yy + 32 * ib + 8 * il; + sycl::vec lo, hi; #pragma unroll for (int j = 0; j < 4; ++j) { - y[j+0] = dl * grid1[j] * (signs & kmask_iq2xs[j+0] ? -1.f : 1.f); - y[j+4] = dl * grid2[j] * (signs & kmask_iq2xs[j+4] ? -1.f : 1.f); + lo[j] = dl * grid1[j] * (signs & kmask_iq2xs[j+0] ? -1.f : 1.f); + hi[j] = dl * grid2[j] * (signs & kmask_iq2xs[j+4] ? -1.f : 1.f); } + *reinterpret_cast *>(y + 0) = lo; + *reinterpret_cast *>(y + 4) = hi; #else GGML_UNUSED(vx); GGML_UNUSED(yy); + GGML_UNUSED(i); GGML_UNUSED(item_ct1); GGML_UNUSED(nb); GGML_UNUSED(iq3xxs_grid); @@ -1561,10 +1608,9 @@ dequantize_block_iq3_s(const void *__restrict__ vx, dst_t *__restrict__ yy, template __dpct_inline__ static void -dequantize_block_iq3_s_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, +dequantize_block_iq3_s_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, const int64_t i, const sycl::nd_item<3> & item_ct1, const int64_t nb, const uint8_t * kmask_iq2xs, const uint32_t * iq3s_grid) { - const int64_t i = item_ct1.get_group(2); const int64_t tid = item_ct1.get_local_id(2); #if QK_K == 256 const int64_t il = tid / 8; @@ -1584,15 +1630,19 @@ dequantize_block_iq3_s_reorder(const void * __restrict__ vx, dst_t * __restrict_ iq3s_grid + (qs_ib[2*il+1] | ((qh[ib] << (7 - 2*il)) & 256))); const float dl = (float) d * (1 + 2 * ((scales[ib/2] >> (4 * (ib%2))) & 0xf)); const uint8_t signs = signs_base[4 * ib + il]; - dst_t * y = yy + i * QK_K + 32 * ib + 8 * il; + dst_t * y = yy + 32 * ib + 8 * il; + sycl::vec lo, hi; #pragma unroll for (int j = 0; j < 4; ++j) { - y[j+0] = dl * grid1[j] * (signs & kmask_iq2xs[j+0] ? -1.f : 1.f); - y[j+4] = dl * grid2[j] * (signs & kmask_iq2xs[j+4] ? -1.f : 1.f); + lo[j] = dl * grid1[j] * (signs & kmask_iq2xs[j+0] ? -1.f : 1.f); + hi[j] = dl * grid2[j] * (signs & kmask_iq2xs[j+4] ? -1.f : 1.f); } + *reinterpret_cast *>(y + 0) = lo; + *reinterpret_cast *>(y + 4) = hi; #else GGML_UNUSED(vx); GGML_UNUSED(yy); + GGML_UNUSED(i); GGML_UNUSED(item_ct1); GGML_UNUSED(nb); GGML_UNUSED(kmask_iq2xs); @@ -1727,24 +1777,28 @@ static void dequantize_block_mxfp4(const void * __restrict__ vx, dst_t * __restr } } -// Reordered MXFP4 ([qs...][e...], see ggml_sycl_reordered::block_q_t): one work-item per block. -template -static void dequantize_block_mxfp4_reorder(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t k, - const sycl::nd_item<3> & item_ct1) { - const int64_t ib = (int64_t) item_ct1.get_group(2) * WARP_SIZE + item_ct1.get_local_id(2); - if (ib >= k / QK_MXFP4) { - return; - } +// Reordered MXFP4 ([qs...][e...], see ggml_sycl_reordered::block_q_t). +// four qs bytes per item, all inside one 32-element block: two vec stores. +// same LUT lookups and per-block scale; bit-identical output. +template +static void dequantize_block_mxfp4_reorder_wide(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t k, + const sycl::id<1> idx) { + const int64_t i = (int64_t) idx[0]; + const int64_t ib = i / 4; + const int64_t iq = 4 * (i % 4); // first of four qs bytes in the block const uint8_t * qs = (const uint8_t *) vx + ib * (QK_MXFP4 / 2); const float d = ggml_sycl_e8m0_to_fp32(((const uint8_t *) vx)[k / 2 + ib]) * 0.5f; - dst_t * y = yy + ib * QK_MXFP4; + dst_t * y = yy + ib * QK_MXFP4 + iq; + sycl::vec lo, hi; #pragma unroll - for (int j = 0; j < QK_MXFP4 / 2; ++j) { - y[j] = d * kvalues_mxfp4[qs[j] & 0xf]; - y[j + QK_MXFP4 / 2] = d * kvalues_mxfp4[qs[j] >> 4]; + for (int j = 0; j < 4; ++j) { + lo[j] = d * kvalues_mxfp4[qs[iq + j] & 0xf]; + hi[j] = d * kvalues_mxfp4[qs[iq + j] >> 4]; } + *reinterpret_cast *>(y) = lo; + *reinterpret_cast *>(y + QK_MXFP4 / 2) = hi; } diff --git a/ggml/src/ggml-sycl/dmmv.cpp b/ggml/src/ggml-sycl/dmmv.cpp index 90f92682980c..19af72c0eb11 100644 --- a/ggml/src/ggml-sycl/dmmv.cpp +++ b/ggml/src/ggml-sycl/dmmv.cpp @@ -10,7 +10,6 @@ #endif #include #include "esimd.hpp" - #define GGML_SYCL_DMMV_HAS_ESIMD #endif static void convert_f16(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ @@ -113,11 +112,12 @@ static void dequantize_mul_mat_vec(const void * __restrict__ vx, const dfloat * } } -template +template static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const dfloat * __restrict__ y, float * __restrict__ dst, const int ncols, const int nrows, const sycl::nd_item<3> &item_ct1) { // qk = quantized weights per x block // qr = number of quantized weights per data value in x block + // qbytes = bytes of the quants region per block (not qk/qr for bit-packed types) const int row = item_ct1.get_group(2) * item_ct1.get_local_range(1) + item_ct1.get_local_id(1); @@ -128,7 +128,7 @@ static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const d const int tid = item_ct1.get_local_id(2); - const int ncols_left = ncols % (QK4_0*WARP_SIZE); + const int ncols_left = ncols % (qk*WARP_SIZE); const int ncols_align = ncols - ncols_left; const int iter_stride = 8*2*GGML_SYCL_DMMV_X; const int vals_per_iter = iter_stride / WARP_SIZE; // num quantized vals per thread and i iter //64/16=4, 512/16/2= 16 @@ -140,7 +140,7 @@ static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const d #else float tmp = 0.0f; #endif // GGML_SYCL_F16 - const char *d_ptr = (const char*)vx+ncols*nrows/2; + const char *d_ptr = (const char*)vx + (size_t) ncols * nrows / qk * qbytes; int i=0; for (i = 0; i < ncols_align; i += iter_stride) { const int col = i + vals_per_iter*tid; @@ -156,7 +156,7 @@ static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const d // dequantize // for qr = 2 the iqs needs to increase by 1 per j iter because 2 weights per data val dfloat2 v; - dequantize_kernel_reorder((const void *)d_ptr, ib, (const void *)vx, ib * QK4_0 / 2 +iqs+j/qr, v); + dequantize_kernel_reorder((const void *)d_ptr, ib, (const void *)vx, ib * (qk/qr) +iqs+j/qr, v); // matrix multiplication // for qr = 2 the y index needs to increase by 1 per j iter because of y_offset = qk/2 @@ -173,7 +173,7 @@ static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const d } for (; i < ncols; i += iter_stride) { - if (tid>=ncols_left/QK4_0) continue; + if (tid>=ncols_left/qk) continue; const int col = i + vals_per_iter*tid; const int ib = (row*ncols + col)/qk; // x block index const int iqs = (col%qk)/qr; // x quant index @@ -187,7 +187,7 @@ static void dequantize_mul_mat_vec_reorder(const void * __restrict__ vx, const d // dequantize // for qr = 2 the iqs needs to increase by 1 per j iter because 2 weights per data val dfloat2 v; - dequantize_kernel_reorder((const void *)d_ptr, ib, (const void *)vx, ib * QK4_0 / 2 +iqs+j/qr, v); + dequantize_kernel_reorder((const void *)d_ptr, ib, (const void *)vx, ib * (qk/qr) +iqs+j/qr, v); // matrix multiplication // for qr = 2 the y index needs to increase by 1 per j iter because of y_offset = qk/2 @@ -1488,55 +1488,10 @@ static void dequantize_mul_mat_vec_q6_k_reorder(const void * __restrict__ vx, co } } -static void dequantize_mul_mat_vec_q4_0_sycl_reorder(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - // the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_reorder( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - - -static void dequantize_mul_mat_vec_q4_0_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - // the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - -static void dequantize_mul_mat_vec_q1_0_sycl_reorder(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { +template +static void launch_dequantize_mul_mat_vec(const void *vx, const dfloat *y, float *dst, + const int ncols, const int nrows, + dpct::queue_ptr stream) { GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; // the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead @@ -1549,16 +1504,16 @@ static void dequantize_mul_mat_vec_q1_0_sycl_reorder(const void *vx, const dfloa stream->parallel_for( sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_reorder( + dequantize_mul_mat_vec( vx, y, dst, ncols, nrows, item_ct1); }); } } -static void dequantize_mul_mat_vec_q1_0_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { +template +static void launch_dequantize_mul_mat_vec_reorder(const void *vx, const dfloat *y, float *dst, + const int ncols, const int nrows, + dpct::queue_ptr stream) { GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; // the number of rows may exceed maximum grid size in the y or z dimensions, use the x dimension instead @@ -1571,313 +1526,91 @@ static void dequantize_mul_mat_vec_q1_0_sycl(const void *vx, const dfloat *y, stream->parallel_for( sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - -static void dequantize_mul_mat_vec_q4_1_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - -static void dequantize_mul_mat_vec_q5_0_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - -static void dequantize_mul_mat_vec_q5_1_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( + dequantize_mul_mat_vec_reorder( vx, y, dst, ncols, nrows, item_ct1); }); } } -static void dequantize_mul_mat_vec_q8_0_sycl_reorder(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - // Q8_0 reorder layout: [all qs (ncols*nrows bytes)][all d values] - // Cannot reuse dequantize_mul_mat_vec_reorder template because it has - // Q4_0-specific constants hardcoded (d_ptr offset and qs stride). - const int row = item_ct1.get_group(2) * item_ct1.get_local_range(1) + - item_ct1.get_local_id(1); - if (row >= nrows) return; - - const int tid = item_ct1.get_local_id(2); - const int iter_stride = 8*2*GGML_SYCL_DMMV_X; - const int vals_per_iter = iter_stride / WARP_SIZE; - const int ncols_left = ncols % (QK8_0*WARP_SIZE); - const int ncols_align = ncols - ncols_left; - -#ifdef GGML_SYCL_F16 - sycl::half2 tmp = {0.0f, 0.0f}; -#else - float tmp = 0.0f; -#endif - const char *d_ptr = (const char*)vx + ncols*nrows; // d after all qs - - int i = 0; - for (i = 0; i < ncols_align; i += iter_stride) { - const int col = i + vals_per_iter*tid; - const int ib = (row*ncols + col)/QK8_0; - const int iqs = col % QK8_0; - -#pragma unroll - for (int j = 0; j < vals_per_iter; j += 2) { - dfloat2 v; - dequantize_q8_0_reorder((const void *)d_ptr, ib, (const void *)vx, - ib * QK8_0 + iqs + j, v); - -#ifdef GGML_SYCL_F16 - dfloat2 t1{y[col + j + 0], y[col + j + 1]}; - tmp += v * t1; -#else - tmp += v.x() * y[col + j + 0]; - tmp += v.y() * y[col + j + 1]; -#endif - } - } - - // handle remaining columns - for (; i < ncols; i += iter_stride) { - if (tid >= ncols_left/QK8_0) continue; - const int col = i + vals_per_iter*tid; - const int ib = (row*ncols + col)/QK8_0; - const int iqs = col % QK8_0; - -#pragma unroll - for (int j = 0; j < vals_per_iter; j += 2) { - dfloat2 v; - dequantize_q8_0_reorder((const void *)d_ptr, ib, (const void *)vx, - ib * QK8_0 + iqs + j, v); - -#ifdef GGML_SYCL_F16 - dfloat2 t1{y[col + j + 0], y[col + j + 1]}; - tmp += v * t1; -#else - tmp += v.x() * y[col + j + 0]; - tmp += v.y() * y[col + j + 1]; -#endif - } - } - - // reduce - const int mask_start = ncols > GGML_SYCL_DMMV_X ? WARP_SIZE >> 1 : WARP_SIZE >> 2; - for (int mask = mask_start; mask > 0; mask >>= 1) { - tmp += dpct::permute_sub_group_by_xor(item_ct1.get_sub_group(), tmp, mask); - } - - if (tid == 0) { -#ifdef GGML_SYCL_F16 - dst[row] = tmp.x() + tmp.y(); -#else - dst[row] = tmp; -#endif - } - }); - } -} - -static void dequantize_mul_mat_vec_q8_0_sycl(const void *vx, const dfloat *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec( - vx, y, dst, ncols, nrows, item_ct1); - }); - } -} - -static void dequantize_mul_mat_vec_q2_K_sycl(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { +template +static void launch_dequantize_mul_mat_vec_k(const void *vx, const float *y, float *dst, + const int ncols, const int nrows, + dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2; // very slightly faster than 1 even when K_QUANTS_PER_ITERATION = 2 const int block_num_y = (nrows + ny - 1) / ny; const sycl::range<3> block_nums(1, 1, block_num_y); const sycl::range<3> block_dims(1, ny, WARP_SIZE); stream->parallel_for( sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q2_k(vx, y, dst, ncols, nrows, item_ct1); + kernel(vx, y, dst, ncols, nrows, item_ct1); }); } -static void dequantize_mul_mat_vec_q2_K_sycl_reorder(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q2_k_reorder(vx, y, dst, ncols, nrows, item_ct1); - }); -} +#ifdef GGML_SYCL_DMMV_HAS_ESIMD +using ggml_sycl_esimd::GGML_SYCL_DMMV_ESIMD_WG_SIZE; -static void dequantize_mul_mat_vec_q3_K_sycl(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q3_k(vx, y, dst, ncols, nrows, item_ct1); - }); -} +// policies for dequantize_mul_mat_vec_reorder_esimd: row mapping and what to do with the two sums +// plain mat-vec: a work-group owns two consecutive rows of one matrix +struct esimd_dmmv_row_pair_policy { + const void * vx; + float * dst; -static void dequantize_mul_mat_vec_q3_K_sycl_reorder(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q3_k_reorder(vx, y, dst, ncols, nrows, item_ct1); - }); -} + ESIMD_INLINE const void * w_a() const { return vx; } + ESIMD_INLINE const void * w_b() const { return vx; } -static void dequantize_mul_mat_vec_q4_K_sycl(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q4_k(vx, y, dst, ncols, nrows, item_ct1); - }); -} + ESIMD_INLINE int row_a(int g) const { return g * 2; } + ESIMD_INLINE int row_b(int g) const { return g * 2 + 1; } + ESIMD_INLINE bool has_b(int g, int nrows) const { return row_b(g) < nrows; } -static void dequantize_mul_mat_vec_q5_K_sycl(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q5_k(vx, y, dst, ncols, nrows, item_ct1); - }); -} + ESIMD_INLINE void epilogue(int g, int nrows, float sum_a, float sum_b) const { + dst[row_a(g)] = sum_a; + if (has_b(g, nrows)) { + dst[row_b(g)] = sum_b; + } + } +}; -static void dequantize_mul_mat_vec_q6_K_sycl(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q6_k(vx, y, dst, ncols, nrows, item_ct1); - }); -} +// fused gate+up+GLU: a work-group owns one row of both matrices; a is the gate, b the up +struct esimd_dmmv_glu_policy { + const void * vgate; + const void * vup; + float * dst; + ggml_glu_op glu_op; -#ifdef GGML_SYCL_DMMV_HAS_ESIMD -using ggml_sycl_esimd::GGML_SYCL_DMMV_ESIMD_WG_SIZE; + ESIMD_INLINE const void * w_a() const { return vgate; } + ESIMD_INLINE const void * w_b() const { return vup; } -// generic reordered dequantize-matvec: each work-group owns a pair of -// consecutive output rows and updates one 32-wide accumulator per row -template + ESIMD_INLINE int row_a(int g) const { return g; } + ESIMD_INLINE int row_b(int g) const { return g; } + ESIMD_INLINE bool has_b(int, int) const { return true; } // up always contributes + + ESIMD_INLINE void epilogue(int g, int, float gate, float up) const { + using namespace sycl::ext::intel::esimd; + + // SwiGLU: silu(gate)*up = gate*sigmoid(gate)*up. GEGLU's tanh form reduces + // to the same shape via tanh(y) = 2*sigmoid(2y) - 1, so only the sigmoid + // argument differs. sigmoid via exp2 (width-1 simd is a degenerate case for + // the EM pipe, so broadcast to 16 lanes); lane 0 holds the result. + const float GELU_COEF_A = 0.044715f; + const float SQRT_2_OVER_PI = 0.79788456080286535587989211986876f; + const float NEG_LOG2E = -1.44269504088896341f; + + const float arg = (glu_op == GGML_GLU_OP_GEGLU) ? + 2.0f * SQRT_2_OVER_PI * gate * (1.0f + GELU_COEF_A * gate * gate) : + gate; + + simd t = arg * NEG_LOG2E; + simd e = exp2(t); + dst[g] = gate / (1.0f + e[0]) * up; + } +}; + +// generic reordered dequantize-matvec: each work-group owns a pair of rows chosen by the policy +// and updates one 32-wide accumulator per row +template ESIMD_INLINE void dequantize_mul_mat_vec_reorder_esimd( - const void * vx, const float * y, float * dst, + const Policy & policy, const float * y, const int ncols, const int nrows, sycl::local_accessor lmem, const sycl::nd_item<1> & it) { @@ -1886,41 +1619,41 @@ ESIMD_INLINE void dequantize_mul_mat_vec_reorder_esimd( const int num_blocks_per_row = ncols / QK_K; const size_t nb = (size_t) nrows * num_blocks_per_row; - const auto ps = traits::make_ptrs(vx, nb); + const auto pa = traits::make_ptrs(policy.w_a(), nb); + const auto pb = traits::make_ptrs(policy.w_b(), nb); - const int tid = it.get_local_id(0); - const int row_pair = it.get_group(0); - const int row0 = row_pair * 2; // two consecutive output rows - const bool has_row1 = row0 + 1 < nrows; + const int tid = it.get_local_id(0); + const int g = it.get_group(0); + const int row_a = policy.row_a(g); + const int row_b = policy.row_b(g); + const bool has_b = policy.has_b(g, nrows); - // one 32-wide accumulator per output row (small footprint, no spill) - simd acc0 = 0.0f; - simd acc1 = 0.0f; + // one 32-wide accumulator per row (small footprint, no spill) + simd acc_a = 0.0f; + simd acc_b = 0.0f; for (int ib = tid; ib < num_blocks_per_row; ib += GGML_SYCL_DMMV_ESIMD_WG_SIZE) { simd y_vec = block_load(y + (size_t) ib * QK_K); - const size_t bi0 = (size_t) (row0 + 0) * num_blocks_per_row + ib; - const size_t bi1 = (size_t) (row0 + 1) * num_blocks_per_row + ib; + const size_t bi_a = (size_t) row_a * num_blocks_per_row + ib; + const size_t bi_b = (size_t) row_b * num_blocks_per_row + ib; - traits::mac_pair(ps, bi0, ps, bi1, has_row1, y_vec, acc0, acc1); + traits::mac_pair(pa, bi_a, pb, bi_b, has_b, y_vec, acc_a, acc_b); } - lmem[tid * 2 + 0] = reduce(acc0, std::plus<>{}); - lmem[tid * 2 + 1] = reduce(acc1, std::plus<>{}); + lmem[tid * 2 + 0] = reduce(acc_a, std::plus<>{}); + lmem[tid * 2 + 1] = reduce(acc_b, std::plus<>{}); it.barrier(sycl::access::fence_space::local_space); if (tid == 0) { - float sum0 = 0.0f; - float sum1 = 0.0f; + float sum_a = 0.0f; + float sum_b = 0.0f; for (int p = 0; p < GGML_SYCL_DMMV_ESIMD_WG_SIZE; ++p) { - sum0 += lmem[p * 2 + 0]; - sum1 += lmem[p * 2 + 1]; - } - dst[row0 + 0] = sum0; - if (has_row1) { - dst[row0 + 1] = sum1; + sum_a += lmem[p * 2 + 0]; + sum_b += lmem[p * 2 + 1]; } + + policy.epilogue(g, nrows, sum_a, sum_b); } } @@ -1936,7 +1669,7 @@ static void dequantize_mul_mat_vec_q2_K_sycl_reorder_esimd(const void *vx, const sycl::nd_range<1>(sycl::range<1>((size_t)workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { dequantize_mul_mat_vec_reorder_esimd( - vx, y, dst, ncols, nrows, lmem, it); + esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, lmem, it); }); }); } @@ -1953,7 +1686,7 @@ static void dequantize_mul_mat_vec_q3_K_sycl_reorder_esimd(const void *vx, const sycl::nd_range<1>(sycl::range<1>((size_t)workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { dequantize_mul_mat_vec_reorder_esimd( - vx, y, dst, ncols, nrows, lmem, it); + esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, lmem, it); }); }); } @@ -1970,7 +1703,7 @@ static void dequantize_mul_mat_vec_q4_K_sycl_reorder_esimd(const void *vx, const sycl::nd_range<1>(sycl::range<1>((size_t)workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { dequantize_mul_mat_vec_reorder_esimd( - vx, y, dst, ncols, nrows, lmem, it); + esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, lmem, it); }); }); } @@ -1987,7 +1720,7 @@ static void dequantize_mul_mat_vec_q5_K_sycl_reorder_esimd(const void *vx, const sycl::nd_range<1>(sycl::range<1>((size_t)workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { dequantize_mul_mat_vec_reorder_esimd( - vx, y, dst, ncols, nrows, lmem, it); + esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, lmem, it); }); }); } @@ -2004,7 +1737,7 @@ static void dequantize_mul_mat_vec_q6_K_sycl_reorder_esimd(const void *vx, const sycl::nd_range<1>(sycl::range<1>((size_t)workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { dequantize_mul_mat_vec_reorder_esimd( - vx, y, dst, ncols, nrows, lmem, it); + esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, lmem, it); }); }); } @@ -2045,9 +1778,9 @@ ESIMD_INLINE void q8_0_mac_stripe( } } -template +template ESIMD_INLINE void dequantize_mul_mat_vec_q8_0_reorder_esimd( - const void * vx, const float * y, float * dst, + const Policy & policy, const float * y, const int ncols, const int nrows, sycl::local_accessor lmem, const sycl::nd_item<1> & it) { @@ -2057,137 +1790,142 @@ ESIMD_INLINE void dequantize_mul_mat_vec_q8_0_reorder_esimd( const int nblk_row = ncols / QK8_0; const size_t nb = (size_t) nrows * nblk_row; - const int8_t * qs = (const int8_t *) vx; - const sycl::half * d = (const sycl::half *) (qs + nb * QK8_0); + const int8_t * qs_a = (const int8_t *) policy.w_a(); + const int8_t * qs_b = (const int8_t *) policy.w_b(); + const sycl::half * d_a = (const sycl::half *) (qs_a + nb * QK8_0); + const sycl::half * d_b = (const sycl::half *) (qs_b + nb * QK8_0); - const int tid = it.get_local_id(0); - const int row_pair = it.get_group(0); - const int row0 = row_pair * 2; - const bool has_row1 = row0 + 1 < nrows; + const int tid = it.get_local_id(0); + const int g = it.get_group(0); + const bool has_b = policy.has_b(g, nrows); - const size_t base0 = (size_t) row0 * nblk_row; - const size_t base1 = has_row1 ? (size_t) (row0 + 1) * nblk_row : base0; + const size_t base_a = (size_t) policy.row_a(g) * nblk_row; + const size_t base_b = (size_t) policy.row_b(g) * nblk_row; - simd acc0 = 0.0f; - simd acc1 = 0.0f; + simd acc_a = 0.0f; + simd acc_b = 0.0f; // Each thread processes one contiguous stripe. int ib = 0; for (; ib + WG * STRIPE <= nblk_row; ib += WG * STRIPE) { const int b = ib + tid * STRIPE; simd y_vec = block_load(y + (size_t) b * QK8_0); - q8_0_mac_stripe(qs + (base0 + b) * QK8_0, qs + (base1 + b) * QK8_0, - d + base0 + b, d + base1 + b, has_row1, y_vec, acc0, acc1); + q8_0_mac_stripe(qs_a + (base_a + b) * QK8_0, qs_b + (base_b + b) * QK8_0, + d_a + base_a + b, d_b + base_b + b, has_b, y_vec, acc_a, acc_b); } // Distribute remaining blocks across the work-group. for (int b = ib + tid; b < nblk_row; b += WG) { simd y_vec = block_load(y + (size_t) b * QK8_0); - q8_0_mac_stripe<1>(qs + (base0 + b) * QK8_0, qs + (base1 + b) * QK8_0, - d + base0 + b, d + base1 + b, has_row1, y_vec, acc0, acc1); + q8_0_mac_stripe<1>(qs_a + (base_a + b) * QK8_0, qs_b + (base_b + b) * QK8_0, + d_a + base_a + b, d_b + base_b + b, has_b, y_vec, acc_a, acc_b); } - lmem[tid * 2 + 0] = reduce(acc0, std::plus<>{}); - lmem[tid * 2 + 1] = reduce(acc1, std::plus<>{}); + lmem[tid * 2 + 0] = reduce(acc_a, std::plus<>{}); + lmem[tid * 2 + 1] = reduce(acc_b, std::plus<>{}); it.barrier(sycl::access::fence_space::local_space); if (tid == 0) { - float sum0 = 0.0f; - float sum1 = 0.0f; + float sum_a = 0.0f; + float sum_b = 0.0f; for (int p = 0; p < WG; ++p) { - sum0 += lmem[p * 2 + 0]; - sum1 += lmem[p * 2 + 1]; - } - dst[row0 + 0] = sum0; - if (has_row1) { - dst[row0 + 1] = sum1; + sum_a += lmem[p * 2 + 0]; + sum_b += lmem[p * 2 + 1]; } + + policy.epilogue(g, nrows, sum_a, sum_b); } } -template -static void q8_0_esimd_launch(const void * vx, const float * y, float * dst, const int ncols, - const int nrows, dpct::queue_ptr stream) { - const int workgroups = (nrows + 1) / 2; +template +static void q8_0_esimd_launch(const Policy & policy, const float * y, const int ncols, const int nrows, + const int workgroups, dpct::queue_ptr stream) { stream->submit([&](sycl::handler & h) { sycl::local_accessor lmem(sycl::range<1>(WG * 2), h); h.parallel_for( sycl::nd_range<1>(sycl::range<1>((size_t) workgroups * WG), sycl::range<1>(WG)), [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { - dequantize_mul_mat_vec_q8_0_reorder_esimd(vx, y, dst, ncols, nrows, lmem, it); + dequantize_mul_mat_vec_q8_0_reorder_esimd(policy, y, ncols, nrows, lmem, it); }); }); } -static void dequantize_mul_mat_vec_q8_0_sycl_reorder_esimd(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { +// Scale the work-group with the number of blocks per row. +template +static void q8_0_esimd_launch_scaled(const Policy & policy, const float * y, const int ncols, const int nrows, + const int workgroups, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK8_0 == 0); - // Scale the work-group with the number of blocks per row. const int nblk_row = ncols / QK8_0; if (nblk_row >= 64) { - q8_0_esimd_launch<8>(vx, y, dst, ncols, nrows, stream); + q8_0_esimd_launch<8>(policy, y, ncols, nrows, workgroups, stream); } else if (nblk_row >= 32) { - q8_0_esimd_launch<4>(vx, y, dst, ncols, nrows, stream); + q8_0_esimd_launch<4>(policy, y, ncols, nrows, workgroups, stream); } else if (nblk_row >= 16) { - q8_0_esimd_launch<2>(vx, y, dst, ncols, nrows, stream); + q8_0_esimd_launch<2>(policy, y, ncols, nrows, workgroups, stream); } else { - q8_0_esimd_launch<1>(vx, y, dst, ncols, nrows, stream); + q8_0_esimd_launch<1>(policy, y, ncols, nrows, workgroups, stream); } } -#endif // GGML_SYCL_DMMV_HAS_ESIMD - -static void dequantize_mul_mat_vec_q4_K_sycl_reorder(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q4_k_reorder(vx, y, dst, ncols, nrows, item_ct1); - }); +static void dequantize_mul_mat_vec_q8_0_sycl_reorder_esimd(const void *vx, const float *y, + float *dst, const int ncols, + const int nrows, + dpct::queue_ptr stream) { + q8_0_esimd_launch_scaled(esimd_dmmv_row_pair_policy{ vx, dst }, y, ncols, nrows, (nrows + 1) / 2, stream); } -static void dequantize_mul_mat_vec_q5_K_sycl_reorder(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, +// ESIMD fused gate+up+GLU on reordered K-quant SOA weights: one output row (gate +// and up) per work-group, two independent 32-wide accumulators per super-block. +// Reuses the DMMV kernels' dequant+MAC primitive (esimd_reorder_q_traits::mac_pair). +template +static void dequantize_mul_mat_vec_glu_reorder_esimd(const void * vx, const void * vgate, + const float * y, float * dst, + const int ncols, const int nrows, + const ggml_glu_op glu_op, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q5_k_reorder(vx, y, dst, ncols, nrows, item_ct1); - }); + const int workgroups = nrows; // one output row (gate+up) per work-group + stream->submit([&](sycl::handler & h) { + sycl::local_accessor lmem(sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE * 2), h); + h.parallel_for( + sycl::nd_range<1>(sycl::range<1>((size_t) workgroups * GGML_SYCL_DMMV_ESIMD_WG_SIZE), sycl::range<1>(GGML_SYCL_DMMV_ESIMD_WG_SIZE)), + [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { + dequantize_mul_mat_vec_reorder_esimd( + esimd_dmmv_glu_policy{ vgate, vx, dst, glu_op }, y, ncols, nrows, lmem, it); + }); + }); } -static void dequantize_mul_mat_vec_q6_K_sycl_reorder(const void *vx, const float *y, - float *dst, const int ncols, - const int nrows, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int ny = 2 / K_QUANTS_PER_ITERATION; - const int block_num_y = (nrows + ny - 1) / ny; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, ny, WARP_SIZE); - stream->parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_q6_k_reorder(vx, y, dst, ncols, nrows, item_ct1); - }); +bool ggml_sycl_dequantize_mul_mat_vec_glu_reorder_esimd(enum ggml_type src0_type, enum ggml_glu_op glu_op, + const void * vx, const void * vgate, const float * y, + float * dst, int ncols, int nrows, dpct::queue_ptr stream) { + switch (src0_type) { + case GGML_TYPE_Q2_K: + dequantize_mul_mat_vec_glu_reorder_esimd(vx, vgate, y, dst, ncols, nrows, glu_op, stream); + return true; + case GGML_TYPE_Q3_K: + dequantize_mul_mat_vec_glu_reorder_esimd(vx, vgate, y, dst, ncols, nrows, glu_op, stream); + return true; + case GGML_TYPE_Q4_K: + dequantize_mul_mat_vec_glu_reorder_esimd(vx, vgate, y, dst, ncols, nrows, glu_op, stream); + return true; + case GGML_TYPE_Q5_K: + dequantize_mul_mat_vec_glu_reorder_esimd(vx, vgate, y, dst, ncols, nrows, glu_op, stream); + return true; + case GGML_TYPE_Q6_K: + dequantize_mul_mat_vec_glu_reorder_esimd(vx, vgate, y, dst, ncols, nrows, glu_op, stream); + return true; + case GGML_TYPE_Q8_0: + q8_0_esimd_launch_scaled(esimd_dmmv_glu_policy{ vgate, vx, dst, glu_op }, y, ncols, nrows, nrows, stream); + return true; + default: + return false; + } } +#endif // GGML_SYCL_DMMV_HAS_ESIMD + void ggml_sycl_op_dequantize_mul_mat_vec( ggml_backend_sycl_context & ctx, const ggml_tensor *src0, const ggml_tensor *src1, ggml_tensor *dst, @@ -2236,27 +1974,27 @@ void ggml_sycl_op_dequantize_mul_mat_vec( case GGML_TYPE_Q1_0: if ((ggml_tensor_extra_gpu*)dst->src[0]->extra && ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { - dequantize_mul_mat_vec_q1_0_sycl_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } else { - dequantize_mul_mat_vec_q1_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q4_0: if ((ggml_tensor_extra_gpu*)dst->src[0]->extra && ((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) { - dequantize_mul_mat_vec_q4_0_sycl_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } else { - dequantize_mul_mat_vec_q4_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q4_1: - dequantize_mul_mat_vec_q4_1_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); break; case GGML_TYPE_Q5_0: - dequantize_mul_mat_vec_q5_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); break; case GGML_TYPE_Q5_1: - dequantize_mul_mat_vec_q5_1_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); break; case GGML_TYPE_Q8_0: if ((ggml_tensor_extra_gpu *) dst->src[0]->extra && @@ -2267,10 +2005,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( } else #endif { - dequantize_mul_mat_vec_q8_0_sycl_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q8_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q2_K: @@ -2283,10 +2021,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( else #endif { - dequantize_mul_mat_vec_q2_K_sycl_reorder(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q2_k_reorder>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q2_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2, dequantize_mul_mat_vec_q2_k>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q3_K: @@ -2299,10 +2037,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( else #endif { - dequantize_mul_mat_vec_q3_K_sycl_reorder(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q3_k_reorder>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q3_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q3_k>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q4_K: @@ -2315,10 +2053,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( else #endif { - dequantize_mul_mat_vec_q4_K_sycl_reorder(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q4_k_reorder>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q4_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q4_k>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q5_K: @@ -2331,10 +2069,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( else #endif { - dequantize_mul_mat_vec_q5_K_sycl_reorder(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q5_k_reorder>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q5_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q5_k>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_Q6_K: @@ -2347,10 +2085,10 @@ void ggml_sycl_op_dequantize_mul_mat_vec( else #endif { - dequantize_mul_mat_vec_q6_K_sycl_reorder(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q6_k_reorder>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } } else { - dequantize_mul_mat_vec_q6_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); + launch_dequantize_mul_mat_vec_k<2/K_QUANTS_PER_ITERATION, dequantize_mul_mat_vec_q6_k>(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream); } break; case GGML_TYPE_F16: diff --git a/ggml/src/ggml-sycl/dmmv.hpp b/ggml/src/ggml-sycl/dmmv.hpp index bd8373564153..318e3489daa4 100644 --- a/ggml/src/ggml-sycl/dmmv.hpp +++ b/ggml/src/ggml-sycl/dmmv.hpp @@ -24,4 +24,13 @@ void ggml_sycl_op_dequantize_mul_mat_vec( const int64_t src1_ncols, const int64_t src1_padded_row_size, const dpct::queue_ptr &stream); +// Fused dense-FFN mat-vec: writes glu(gate . y, up . y) for same-type reordered +// weights (Q2_K..Q6_K, Q8_0) and a single F32 activation column, using the ESIMD DMMV kernels. +// vx is the up weight, vgate the gate weight. Only defined when GGML_SYCL_DMMV_HAS_ESIMD; +// returns false if the type is unhandled. +bool ggml_sycl_dequantize_mul_mat_vec_glu_reorder_esimd( + enum ggml_type src0_type, enum ggml_glu_op glu_op, + const void * vx, const void * vgate, const float * y, + float * dst, int ncols, int nrows, dpct::queue_ptr stream); + #endif // GGML_SYCL_DMMV_HPP diff --git a/ggml/src/ggml-sycl/dpct/helper.hpp b/ggml/src/ggml-sycl/dpct/helper.hpp index 85af4cab6810..fd3b9655ad1c 100644 --- a/ggml/src/ggml-sycl/dpct/helper.hpp +++ b/ggml/src/ggml-sycl/dpct/helper.hpp @@ -3159,7 +3159,7 @@ namespace dpct _local_mem_size = local_mem_size; - }; + } static inline std::mutex kernel_function_ptr_map_mutex; public: diff --git a/ggml/src/ggml-sycl/element_wise.cpp b/ggml/src/ggml-sycl/element_wise.cpp index 0d263aa76897..c7fe70ac33db 100644 --- a/ggml/src/ggml-sycl/element_wise.cpp +++ b/ggml/src/ggml-sycl/element_wise.cpp @@ -1169,7 +1169,7 @@ static void swiglu_oai_sycl(const T * x, }); } -void ggml_sycl_op_swiglu_oai(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { +static void ggml_sycl_op_swiglu_oai(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; void * src0_d = src0->data; diff --git a/ggml/src/ggml-sycl/esimd.hpp b/ggml/src/ggml-sycl/esimd.hpp index 0485ff0ceed1..85cc93e21ef1 100644 --- a/ggml/src/ggml-sycl/esimd.hpp +++ b/ggml/src/ggml-sycl/esimd.hpp @@ -2,6 +2,8 @@ #define GGML_SYCL_ESIMD_HPP #include +#include +#include #include "common.hpp" @@ -584,6 +586,814 @@ template <> struct esimd_reorder_q_traits { } }; +// +// Multi-column mul_mat_vec for reordered K-quant weights on the XMX engines (int8 DPAS). +// A thread owns 16 weight rows (B operand, one dword is 4 weights of a row), the q8_1 activation +// columns are the A operand. A super-block is 8 groups of 32, run as 2 parts of 4 groups. A quant +// type supplies its loads and unpack as a traits struct. +// +using sycl::ext::intel::esimd::simd; +constexpr int XMX_ROWS = 16; // weight rows per thread (DPAS N) +constexpr int XMX_CHUNK = 64; // widest single launch, more columns run as repeated launches +constexpr int XMX_FUSED_CHUNK = GGML_SYCL_XMX_GLU_MAX_COLS; // widest launch of the fused gate and up kernel + +// threads that split K for one tile, sized so that the shared memory stays small +template constexpr int xmx_n_split() { + return NC <= 8 ? 32 : (NC == 16 ? 16 : 8); +} + +inline bool xmx_supported(const void * vx, const int ncols) { + // 2D block loads need a 64 byte aligned base + return ncols % QK_K == 0 && (uintptr_t) vx % 64 == 0; +} + +// transposed 2D block load of 16 rows, dword (kd, n) lands at [kd * 16 + n] +// 2D block loads need rows of at least 64 bytes, shorter rows (SR) are read row by row +template +ESIMD_INLINE simd xmx_load_t(const void * base, unsigned pitch, unsigned h, int x, int y) { + using namespace sycl::ext::intel::esimd; + if constexpr (SR) { + simd r; + for (int n = 0; n < XMX_ROWS; ++n) { + const unsigned row = y + n < (int) h ? y + n : h; + const char * p = (const char *) base + (size_t) row * (pitch + 1); + r.template select(n) = block_load((const uint32_t *) p + x); + } + return r; + } else { + return load_2d((const uint32_t *) base, pitch, h, pitch, x, y); + } +} + +// per byte (q - zero) as int8 for q in 0..127, no borrow between bytes +ESIMD_INLINE simd xmx_bytes_sub(simd x, uint32_t zero_x4) { + return ((x | 0x80808080u) - zero_x4) ^ 0x80808080u; +} + +// How the scales of a quant type enter the DPAS epilogue of a group of 32 (see xmx_group) +enum class xmx_scale_kind { + split, // two scales per group, one per 16 wide half: the weights are masked to one half for each DPAS + min, // one scale and one min per group: a second DPAS sums the activations for the min term + min16, // a scale and a min per 16 wide half: the scales are folded into the DPAS operands + plain, // one scale per group +}; + +// What every quant type states about itself. nc_wide is the tile width from which it takes the large register file. +template struct xmx_traits_base { + static constexpr bool short_rows = SR; + static constexpr int nc_wide = NC_WIDE; + static constexpr bool has_min = KIND == xmx_scale_kind::min; + static constexpr bool plain = KIND == xmx_scale_kind::plain; + static constexpr bool min16 = KIND == xmx_scale_kind::min16; +}; + +// The part of a context every quant type shares: the last row (the clamp of 2D loads), this thread's first row and +// the number of super-blocks per row. A type adds its array pointers and 2D load pitches. +struct xmx_ctx_base { + unsigned h; + int row0; + int bpr; +}; + +ESIMD_INLINE void xmx_ctx_init(xmx_ctx_base & c, int nrows, int bpr, int row0) { + c.h = nrows - 1; + c.row0 = row0; + c.bpr = bpr; +} + +// pitch of a 2D load over an array with `bytes` bytes per super-block +constexpr unsigned xmx_pitch(int bpr, int bytes) { + return bpr * bytes - 1; +} + +// per group row scales of the 16 rows, one vector per group +template struct xmx_row_scales { + simd v[N]; + + ESIMD_INLINE simd get(int i) { return v[i]; } +}; + +// the 12 packed scale bytes of a super-block (Q3_K, Q4_K, Q5_K) of the 16 rows as three dwords +ESIMD_INLINE void xmx_load_sc12(const uint8_t * sc, + const simd & bi, + simd & w0, + simd & w1, + simd & w2) { + using namespace sycl::ext::intel::esimd; + w0 = gather((const uint32_t *) sc, bi * 12); + w1 = gather((const uint32_t *) sc, bi * 12 + 4); + w2 = gather((const uint32_t *) sc, bi * 12 + 8); +} + +// d and dmin (a half2 per super-block, Q2_K, Q4_K, Q5_K) of the 16 rows +ESIMD_INLINE void xmx_load_dm(const sycl::half * dm, + const simd & bi, + simd & d, + simd & dmin) { + using namespace sycl::ext::intel::esimd; + d = convert(gather(dm, bi * (2 * (uint32_t) sizeof(sycl::half)))); + dmin = convert( + gather(dm, bi * (2 * (uint32_t) sizeof(sycl::half)) + (uint32_t) sizeof(sycl::half))); +} + +// Q6_K reorder layout: [ql: nb*128] [qh: nb*64] [scales int8: nb*16] [d: nb*2] +template struct xmx_traits_q6_k : xmx_traits_base { + struct ctx : xmx_ctx_base { + const uint8_t * ql; + const uint8_t * qh; + const int8_t * scales; + const sycl::half * dh; + unsigned pl, ph, ps; + }; + + static ESIMD_INLINE ctx make(const void * vx, int nrows, int bpr, int row0) { + const size_t nb = (size_t) nrows * bpr; + ctx c; + xmx_ctx_init(c, nrows, bpr, row0); + c.ql = (const uint8_t *) vx; + c.qh = c.ql + nb * (QK_K / 2); + c.scales = (const int8_t *) (c.qh + nb * (QK_K / 4)); + c.dh = (const sycl::half *) (c.scales + nb * (QK_K / 16)); + c.pl = xmx_pitch(bpr, QK_K / 2); + c.ph = xmx_pitch(bpr, QK_K / 4); + c.ps = xmx_pitch(bpr, QK_K / 16); + return c; + } + + // row scales of the 16 scale groups of a super-block + struct scales_t { + simd sc8; + simd dv; + + ESIMD_INLINE simd get(int gr) { + simd s = sc8.template select<16, 4>(64 * (gr / 4) + (gr % 4)); + return sycl::ext::intel::esimd::convert(s) * dv; + } + }; + + // rows: clamped row index of each of the 16 lanes + static ESIMD_INLINE scales_t load_scales(const ctx & c, int sb, const simd & rows) { + using namespace sycl::ext::intel::esimd; + scales_t s; + s.dv = convert(gather(c.dh, (rows * c.bpr + sb) * (uint32_t) sizeof(sycl::half))); + simd raw = xmx_load_t<4, SR>(c.scales, c.ps, c.h, sb * 4, c.row0); + s.sc8 = raw.template bit_cast_view(); + return s; + } + + struct part_t { + simd a, b, h; + }; + + static ESIMD_INLINE part_t load_part(const ctx & c, int sb, int part) { + part_t p; + p.a = xmx_load_t<8, SR>(c.ql, c.pl, c.h, sb * 32 + part * 16, c.row0); + p.b = xmx_load_t<8, SR>(c.ql, c.pl, c.h, sb * 32 + part * 16 + 8, c.row0); + p.h = xmx_load_t<8, SR>(c.qh, c.ph, c.h, sb * 16 + part * 8, c.row0); + return p; + } + + static ESIMD_INLINE simd unpack(const part_t & p, int g, int /*part*/) { + simd qs = (g & 1) ? p.b : p.a; + simd x; + if (g == 0) { + x = (qs & 0x0F0F0F0Fu) | ((p.h << 4) & 0x30303030u); + } else if (g == 1) { + x = (qs & 0x0F0F0F0Fu) | ((p.h << 2) & 0x30303030u); + } else if (g == 2) { + x = ((qs >> 4) & 0x0F0F0F0Fu) | (p.h & 0x30303030u); + } else { + x = ((qs >> 4) & 0x0F0F0F0Fu) | ((p.h >> 2) & 0x30303030u); + } + return xmx_bytes_sub(x, 0x20202020u); + } +}; + +// Q3_K reorder layout: [qs: nb*64] [hmask: nb*32] [scales: nb*12] [d: nb*2] +// chunk s of 32: 2 bits from qs byte 32*(s/4)+l at shift 2*(s%4), high bit is hmask[l] bit s, value is q - 4 +template struct xmx_traits_q3_k : xmx_traits_base { + struct ctx : xmx_ctx_base { + const uint8_t * qs; + const uint8_t * hm; + const uint8_t * sc; + const sycl::half * dh; + unsigned pq, ph; + }; + + static ESIMD_INLINE ctx make(const void * vx, int nrows, int bpr, int row0) { + const size_t nb = (size_t) nrows * bpr; + ctx c; + xmx_ctx_init(c, nrows, bpr, row0); + c.qs = (const uint8_t *) vx; + c.hm = c.qs + nb * (QK_K / 4); + c.sc = c.hm + nb * (QK_K / 8); + c.dh = (const sycl::half *) (c.sc + nb * 12); + c.pq = xmx_pitch(bpr, QK_K / 4); + c.ph = xmx_pitch(bpr, QK_K / 8); + return c; + } + + using scales_t = xmx_row_scales<16>; + + static ESIMD_INLINE scales_t load_scales(const ctx & c, int sb, const simd & rows) { + using namespace sycl::ext::intel::esimd; + scales_t s; + simd bi = rows * c.bpr + sb; + simd w0, w1, w2; + xmx_load_sc12(c.sc, bi, w0, w1, w2); + simd dv = convert(gather(c.dh, bi * (uint32_t) sizeof(sycl::half))); +#pragma unroll + for (int i = 0; i < 16; ++i) { + const simd lo = (i % 8) < 4 ? w0 : w1; + const int bl = i % 4; + simd nib = (lo >> (8 * bl + (i < 8 ? 0 : 4))) & 0xFu; + simd hi = ((w2 >> (8 * bl + 2 * (i / 4))) & 3u) << 4; + simd code = nib | hi; + s.v[i] = convert(code - 32) * dv; + } + return s; + } + + struct part_t { + simd q, h; + }; + + static ESIMD_INLINE part_t load_part(const ctx & c, int sb, int part) { + part_t p; + p.q = xmx_load_t<8, SR>(c.qs, c.pq, c.h, sb * 16 + part * 8, c.row0); + p.h = xmx_load_t<8, SR>(c.hm, c.ph, c.h, sb * 8, c.row0); + return p; + } + + static ESIMD_INLINE simd unpack(const part_t & p, int g, int part) { + const int s = 4 * part + g; + simd x = ((p.q >> (2 * g)) & 0x03030303u) | (((p.h >> s) & 0x01010101u) << 2); + return xmx_bytes_sub(x, 0x04040404u); + } +}; + +// Q4_K and Q5_K (QH) reorder layout: [qs: nb*128] ([qh: nb*32]) [scales: nb*12] [dm: nb*4] +// group j of 32: nibble of qs byte 32*(j/2)+l (low for even j), Q5_K adds 16 * bit j of qh[l] +// value is dall * sc_j * q - dmin * m_j, one scale and one min per group +template struct xmx_traits_q45_k : xmx_traits_base { + struct ctx : xmx_ctx_base { + const uint8_t * qs; + const uint8_t * qh; + const uint8_t * sc; + const sycl::half * dm; + unsigned pq, ph; + }; + + static ESIMD_INLINE ctx make(const void * vx, int nrows, int bpr, int row0) { + const size_t nb = (size_t) nrows * bpr; + ctx c; + xmx_ctx_init(c, nrows, bpr, row0); + c.qs = (const uint8_t *) vx; + c.qh = c.qs + nb * (QK_K / 2); + c.sc = QH ? c.qh + nb * (QK_K / 8) : c.qh; + c.dm = (const sycl::half *) (c.sc + nb * 12); + c.pq = xmx_pitch(bpr, QK_K / 2); + c.ph = xmx_pitch(bpr, QK_K / 8); + return c; + } + + struct scales_t { + xmx_row_scales<8> d; // dall * scale of each group + xmx_row_scales<8> m; // dmin * min of each group + }; + + static ESIMD_INLINE scales_t load_scales(const ctx & c, int sb, const simd & rows) { + using namespace sycl::ext::intel::esimd; + scales_t s; + simd bi = rows * c.bpr + sb; + simd w0, w1, w2; + xmx_load_sc12(c.sc, bi, w0, w1, w2); + simd d, dmin; + xmx_load_dm(c.dm, bi, d, dmin); +#pragma unroll + for (int j = 0; j < 8; ++j) { + const int jj = j % 4; + simd sc, m; + if (j < 4) { + sc = (w0 >> (8 * jj)) & 63u; + m = (w1 >> (8 * jj)) & 63u; + } else { + sc = ((w2 >> (8 * jj)) & 0xFu) | (((w0 >> (8 * jj + 6)) & 3u) << 4); + m = ((w2 >> (8 * jj + 4)) & 0xFu) | (((w1 >> (8 * jj + 6)) & 3u) << 4); + } + s.d.v[j] = convert(simd(sc)) * d; + s.m.v[j] = convert(simd(m)) * dmin; + } + return s; + } + + struct part_t { + simd a, b, h; + }; + + static ESIMD_INLINE part_t load_part(const ctx & c, int sb, int part) { + part_t p; + p.a = xmx_load_t<8, SR>(c.qs, c.pq, c.h, sb * 32 + part * 16, c.row0); + p.b = xmx_load_t<8, SR>(c.qs, c.pq, c.h, sb * 32 + part * 16 + 8, c.row0); + if constexpr (QH) { + p.h = xmx_load_t<8, SR>(c.qh, c.ph, c.h, sb * 8, c.row0); + } + return p; + } + + static ESIMD_INLINE simd unpack(const part_t & p, int g, int part) { + simd qs = (g < 2) ? p.a : p.b; + simd x = (qs >> (4 * (g & 1))) & 0x0F0F0F0Fu; + if constexpr (QH) { + x |= ((p.h >> (4 * part + g)) & 0x01010101u) << 4; + } + return x; + } +}; + +// Q2_K reorder layout: [qs: nb*64] [scales: nb*16] [dm: nb*4] +// chunk s of 32: 2 bits from qs byte 32*(s/4)+l at shift 2*(s%4), each 16 wide half has a 4 bit scale and min +// value is d * (code & 15) * q - dmin * (code >> 4) +template struct xmx_traits_q2_k : xmx_traits_base { + struct ctx : xmx_ctx_base { + const uint8_t * qs; + const uint8_t * sc; + const sycl::half * dm; + unsigned pq, ps; + }; + + static ESIMD_INLINE ctx make(const void * vx, int nrows, int bpr, int row0) { + const size_t nb = (size_t) nrows * bpr; + ctx c; + xmx_ctx_init(c, nrows, bpr, row0); + c.qs = (const uint8_t *) vx; + c.sc = c.qs + nb * (QK_K / 4); + c.dm = (const sycl::half *) (c.sc + nb * (QK_K / 16)); + c.pq = xmx_pitch(bpr, QK_K / 4); + c.ps = xmx_pitch(bpr, QK_K / 16); + return c; + } + + struct scales_t { + simd code; // 4 bit scale (low) and min (high) of each 16 wide half + simd d, dmin; + + ESIMD_INLINE simd byte(int gr) { return code.template select<16, 4>(64 * (gr / 4) + (gr % 4)); } + }; + + static ESIMD_INLINE scales_t load_scales(const ctx & c, int sb, const simd & rows) { + using namespace sycl::ext::intel::esimd; + scales_t s; + simd bi = rows * c.bpr + sb; + simd raw = xmx_load_t<4, SR>(c.sc, c.ps, c.h, sb * 4, c.row0); + s.code = raw.template bit_cast_view(); + xmx_load_dm(c.dm, bi, s.d, s.dmin); + return s; + } + + struct part_t { + simd q; + }; + + static ESIMD_INLINE part_t load_part(const ctx & c, int sb, int part) { + part_t p; + p.q = xmx_load_t<8, SR>(c.qs, c.pq, c.h, sb * 16 + part * 8, c.row0); + return p; + } + + static ESIMD_INLINE simd unpack(const part_t & p, int g, int /*part*/) { + return (p.q >> (2 * g)) & 0x03030303u; + } +}; + +// Q8_0 reorder layout: [qs: nrows*K bytes] [d: one half per 32 weights] +// the int8 weights feed DPAS as they are, a group is one block with one scale +template struct xmx_traits_q8_0 : xmx_traits_base { + struct ctx : xmx_ctx_base { + const uint8_t * qs; + const sycl::half * dh; + unsigned pq; + }; + + static ESIMD_INLINE ctx make(const void * vx, int nrows, int bpr, int row0) { + ctx c; + xmx_ctx_init(c, nrows, bpr, row0); + c.qs = (const uint8_t *) vx; + c.dh = (const sycl::half *) (c.qs + (size_t) nrows * bpr * QK_K); + c.pq = xmx_pitch(bpr, QK_K); + return c; + } + + struct scales_t { + xmx_row_scales<8> d; // scale of each of the 8 blocks of a super-block + }; + + static ESIMD_INLINE scales_t load_scales(const ctx & c, int sb, const simd & rows) { + using namespace sycl::ext::intel::esimd; + scales_t s; + simd blk = (rows * c.bpr + sb) * (QK_K / QK8_0); +#pragma unroll + for (int j = 0; j < 8; ++j) { + s.d.v[j] = convert(gather(c.dh, (blk + j) * (uint32_t) sizeof(sycl::half))); + } + return s; + } + + struct part_t { + simd q[4]; + }; + + static ESIMD_INLINE part_t load_part(const ctx & c, int sb, int part) { + part_t p; +#pragma unroll + for (int g = 0; g < 4; ++g) { + p.q[g] = xmx_load_t<8, SR>(c.qs, c.pq, c.h, sb * 64 + 8 * (4 * part + g), c.row0); + } + return p; + } + + static ESIMD_INLINE simd unpack(const part_t & p, int g, int /*part*/) { return p.q[g]; } +}; + +template using xmx_traits_q4_k = xmx_traits_q45_k; +template using xmx_traits_q5_k = xmx_traits_q45_k; + +// registers per thread, the large file halves the resident threads but avoids spills in wide tiles, the fused +// kernel keeps two sets of weights and scales and always takes it +template constexpr int xmx_grf() { + return FUSED || NC >= T::nc_wide ? 256 : 128; +} + +// One DPAS of a block of RC columns: the int32 products of the weights B and the activations A, as float and scaled +// per weight row. Every quant type sums one or two of these per group of 32. +template +ESIMD_INLINE simd xmx_term(const simd & B, + const simd & A, + const simd & s) { + using namespace sycl::ext::intel::esimd; + namespace xmx = sycl::ext::intel::esimd::xmx; + + simd C = xmx::dpas<8, RC, int>(B, A); + return convert(C) * s.template replicate(); +} + +// one group of 32 of one weight set, accumulated into Cf for all the columns of the tile +template +ESIMD_INLINE void xmx_group(simd & Cf, + const typename T::part_t & pd, + typename T::scales_t & sc, + A2T & A2, + D8T & d8f, + simd & Bl, + simd & Bh, + const simd & Ol, + const int g, + const int part) { + using namespace sycl::ext::intel::esimd; + + constexpr int NT = XMX_ROWS; + constexpr int RC = NC < 8 ? NC : 8; + constexpr int NB = NC / RC; + constexpr bool split = !T::has_min && !T::plain && !T::min16; // two scales per group of 32 + constexpr bool pair = (RC * 32) % 64 == 0; // a block of RC rows fills whole registers + + const int gi = 4 * part + g; + + simd x = T::unpack(pd, g, part); + simd B = x.template bit_cast_view(); + if constexpr (split) { + Bl.template select<256, 1>(0) = B.template select<256, 1>(0); + Bh.template select<256, 1>(256) = B.template select<256, 1>(256); + } + + simd rd; + simd rm; + simd rs0; + simd rs1; + + // Q2_K: scale and min of each 16 wide half are 4 bit codes, the weight is d * scl * q - dmin * mc. scl * q + // is at most 45, so a dword multiply keeps the bytes apart and the scaled weights go to DPAS as int8. The + // min term sums a * mc over K, the codes mc take the place of the weights in a second DPAS. + simd Bs; + simd Bm; + if constexpr (T::min16) { + const simd c0 = sc.byte(2 * gi); + const simd c1 = sc.byte(2 * gi + 1); + simd sl0 = convert(simd(c0 & (uint8_t) 15)); + simd sl1 = convert(simd(c1 & (uint8_t) 15)); + simd mc0 = convert(simd(c0 >> (uint8_t) 4)) * 0x01010101u; + simd mc1 = convert(simd(c1 >> (uint8_t) 4)) * 0x01010101u; + simd ws; + simd wm; + ws.template select<64, 1>(0) = x.template select<64, 1>(0) * sl0.template replicate<4>(); + ws.template select<64, 1>(64) = x.template select<64, 1>(64) * sl1.template replicate<4>(); + wm.template select<64, 1>(0) = mc0.template replicate<4>(); + wm.template select<64, 1>(64) = mc1.template replicate<4>(); + Bs = ws.template bit_cast_view(); + Bm = wm.template bit_cast_view(); + } + if constexpr (T::plain) { + rd = sc.d.get(gi); + } else if constexpr (T::has_min) { + rd = sc.d.get(gi); + rm = sc.m.get(gi); + } else if constexpr (T::min16) { + // scales are applied through Bs and Bm + } else { + rs0 = sc.get(2 * gi); + rs1 = sc.get(2 * gi + 1); + } + +#pragma unroll + for (int b = 0; b < NB; ++b) { + simd A = + A2[b].template select(pair ? (g % 2) * RC * 8 : 0).template bit_cast_view(); + simd d8r = + d8f[b].template select(gi).template replicate_vs_w_hs(0); + auto Cb = Cf.template select(b * RC * NT); + + simd z; + if constexpr (T::plain) { + z = xmx_term(B, A, rd); + } else if constexpr (T::has_min) { + // the second DPAS (all ones against the activations) is the exact integer sum of the activations + z = xmx_term(B, A, rd) - xmx_term(Ol, A, rm); + } else if constexpr (T::min16) { + z = xmx_term(Bs, A, sc.d) - xmx_term(Bm, A, sc.dmin); + } else { + z = xmx_term(Bl, A, rs0) + xmx_term(Bh, A, rs1); + } + Cb += z * d8r; + } +} + +// activation of the GLU applied to the gate, uniform across the launch +template ESIMD_INLINE simd xmx_glu_act(const simd & gate, const int glu_op) { + using namespace sycl::ext::intel::esimd; + if (glu_op == GGML_GLU_OP_SWIGLU) { + return gate / (1.0f + exp(-gate)); + } + // GEGLU, the tanh is written with exp + simd a = 0.79788456f * gate * (1.0f + 0.044715f * gate * gate); + simd t = 1.0f - 2.0f / (exp(2.0f * a) + 1.0f); + return 0.5f * gate * (1.0f + t); +} + +// activations come in through 2D block loads, one for the (d, s) pairs of a super-block (s is unused) and one per two +// groups for the quants, the DPAS A operand needs no repacking. Groups with two scales (16 wide) mask the +// weights instead, zeros in B drop the other half of K. +// KS is the most threads that split K for one tile, the launch may use fewer. +// FUSED computes up * act(gate) from the weights vx (up) and vg (gate), reading the activations once. +template +ESIMD_INLINE void xmx_mul_mat(const void * vx, + const void * vg, + const char * vy, + float * dst, + const int ncols, + const int nrows, + const int ncv, + const int stride_y_bytes, + const int ldd, + const int glu_op, + const int tile, + const int lid, + const int ks) { + using namespace sycl::ext::intel::esimd; + + constexpr int NT = XMX_ROWS; + constexpr int RC = NC < 8 ? NC : 8; + constexpr int NB = NC / RC; + constexpr int N_ACC = FUSED ? 2 : 1; + constexpr bool pair = (RC * 32) % 64 == 0; // a block of RC rows fills whole registers + + if constexpr (KS > 1) { + slm_init(); + } + + const int bpr = ncols / QK_K; + const int row0 = tile * NT; + const auto c = T::make(vx, nrows, bpr, row0); + const auto cg = T::make(FUSED ? vg : vx, nrows, bpr, row0); + + simd rows; +#pragma unroll + for (int n = 0; n < NT; ++n) { + rows[n] = row0 + n < nrows ? row0 + n : nrows - 1; + } + + const uint32_t * yq = (const uint32_t *) vy; + const uint32_t * yd = (const uint32_t *) (vy + ncols); + const unsigned yqw = ncols - 1; + const unsigned ydw = ncols / QK8_1 * sizeof(sycl::half2) - 1; + const unsigned yh = ncv - 1; + const unsigned yp = stride_y_bytes - 1; + + simd Cf = 0.0f; + simd Cfg = 0.0f; // gate, only used when fused + simd Bl = int8_t(0); + simd Bh = int8_t(0); + simd Ol = int8_t(0); + if constexpr (T::has_min) { + Ol = int8_t(1); + } + + for (int sb = lid; sb < bpr; sb += ks) { + auto sc = T::load_scales(c, sb, rows); + typename T::scales_t scg; + if constexpr (FUSED) { + scg = T::load_scales(cg, sb, rows); + } + + // d of the 8 groups of the super-block, [column * 8 + group] + simd d8f[NB]; +#pragma unroll + for (int b = 0; b < NB; ++b) { + simd ds = load_2d(yd, ydw, yh, yp, sb * 8, b * RC); + simd dh = ds.template bit_cast_view(); + d8f[b] = convert(simd(dh.template select<8 * RC, 2>(0))); + } + +#pragma unroll + for (int part = 0; part < 2; ++part) { + const auto pd = T::load_part(c, sb, part); + typename T::part_t pdg; + if constexpr (FUSED) { + pdg = T::load_part(cg, sb, part); + } + + simd A2[NB]; // quants of two groups + +#pragma unroll + for (int g = 0; g < 4; ++g) { + const int gi = 4 * part + g; + if constexpr (pair) { + if (g % 2 == 0) { +#pragma unroll + for (int b = 0; b < NB; ++b) { + A2[b] = + load_2d(yq, yqw, yh, yp, sb * 64 + gi * 8, b * RC); + } + } + } else { +#pragma unroll + for (int b = 0; b < NB; ++b) { + A2[b].template select(0) = + load_2d(yq, yqw, yh, yp, sb * 64 + gi * 8, b * RC); + } + } + + xmx_group(Cf, pd, sc, A2, d8f, Bl, Bh, Ol, g, part); + if constexpr (FUSED) { + xmx_group(Cfg, pdg, scg, A2, d8f, Bl, Bh, Ol, g, part); + } + } + } + } + + if constexpr (KS > 1) { + slm_block_store(lid * NC * NT * sizeof(float), Cf); + if constexpr (FUSED) { + slm_block_store((KS + lid) * NC * NT * sizeof(float), Cfg); + } + barrier(); + if (lid != 0) { + return; + } + Cf = 0.0f; + Cfg = 0.0f; +#pragma unroll 4 + for (int j = 0; j < ks; ++j) { + Cf += slm_block_load(j * NC * NT * sizeof(float)); + if constexpr (FUSED) { + Cfg += slm_block_load((KS + j) * NC * NT * sizeof(float)); + } + } + } + + if constexpr (FUSED) { + Cf *= xmx_glu_act(Cfg, glu_op); + } + + if (row0 + NT <= nrows && ldd % 4 == 0 && (uintptr_t) dst % 16 == 0) { +#pragma unroll + for (int m = 0; m < NC; ++m) { + if (NC <= 8 || m < ncv) { + block_store(dst + (size_t) m * ldd + row0, Cf.template select(m * NT)); + } + } + } else { + // tail tile or unaligned output + simd lane(0, 1); + simd_mask in_rows = (lane + row0) < (uint32_t) nrows; +#pragma unroll + for (int m = 0; m < NC; ++m) { + if (NC <= 8 || m < ncv) { + scatter(dst + (size_t) m * ldd + row0, lane * (uint32_t) sizeof(float), + Cf.template select(m * NT), in_rows); + } + } + } +} + +// KS_MAX bounds the threads that split K for one tile, the launch uses as few as keep every thread to the same +// number of super-blocks as the busiest one +template +static void xmx_mul_mat_launch_ks(const void * vx, + const void * vg, + const char * vy, + float * dst, + const int ncols, + const int nrows, + const int ncv, + const int stride_y_bytes, + const int ldd, + const int glu_op, + dpct::queue_ptr stream) { + GGML_ASSERT(ncols % QK_K == 0); + const size_t n_tiles = (nrows + XMX_ROWS - 1) / XMX_ROWS; + const int bpr = ncols / QK_K; + const int rounds = (bpr + KS_MAX - 1) / KS_MAX; + const int ks = (bpr + rounds - 1) / rounds; + stream->submit([&](sycl::handler & cgh) { + cgh.parallel_for(sycl::nd_range<1>(sycl::range<1>(n_tiles * ks), sycl::range<1>(ks)), + sycl::ext::oneapi::experimental::properties{ + sycl::ext::intel::experimental::grf_size()> }, + [=](sycl::nd_item<1> it) [[intel::sycl_explicit_simd]] { + xmx_mul_mat(vx, vg, vy, dst, ncols, nrows, ncv, stride_y_bytes, ldd, + glu_op, (int) it.get_group(0), (int) it.get_local_id(0), + ks); + }); + }); +} + +template +static void xmx_mul_mat_launch(const void * vx, + const void * vg, + const char * vy, + float * dst, + const int ncols, + const int nrows, + const int ncv, + const int stride_y_bytes, + const int ldd, + const int glu_op, + dpct::queue_ptr stream) { + // the fused kernel keeps two sets of accumulators in shared memory, half the threads for the same size + constexpr int ks_max = xmx_n_split() / (FUSED ? 2 : 1); + xmx_mul_mat_launch_ks(vx, vg, vy, dst, ncols, nrows, ncv, stride_y_bytes, ldd, glu_op, + stream); +} + +// FUSED: vx and vg are the up and gate weights, dst gets up * act(gate) with glu_op a ggml_glu_op +template +static void xmx_mul_mat_ncols(const void * vx, + const void * vg, + const char * vy, + float * dst, + const int ncols, + const int nrows, + const int ncols_dst, + const int stride_y_bytes, + const int ldd, + const int glu_op, + dpct::queue_ptr stream) { + constexpr int chunk_max = FUSED ? XMX_FUSED_CHUNK : XMX_CHUNK; + for (int c0 = 0; c0 < ncols_dst; c0 += chunk_max) { + const int n = std::min(chunk_max, ncols_dst - c0); + const char * y = vy + (size_t) c0 * stride_y_bytes; + float * d = dst + (size_t) c0 * ldd; + const int nc = n > 32 ? 64 : (n > 16 ? 32 : (n > 8 ? 16 : n)); + switch (nc) { +#define XMX_CASE(N) \ + case N: \ + xmx_mul_mat_launch(vx, vg, y, d, ncols, nrows, n, stride_y_bytes, ldd, glu_op, stream); \ + break + XMX_CASE(1); + XMX_CASE(2); + XMX_CASE(3); + XMX_CASE(4); + XMX_CASE(5); + XMX_CASE(6); + XMX_CASE(7); + XMX_CASE(8); +#undef XMX_CASE + // short row variants are for tests, not built for the wide tiles +#define XMX_CASE_WIDE(N) \ + case N: \ + if constexpr (!T::short_rows && (!FUSED || N <= XMX_FUSED_CHUNK)) { \ + xmx_mul_mat_launch(vx, vg, y, d, ncols, nrows, n, stride_y_bytes, ldd, glu_op, stream); \ + } \ + break + XMX_CASE_WIDE(16); + XMX_CASE_WIDE(32); + XMX_CASE_WIDE(64); +#undef XMX_CASE_WIDE + default: + GGML_ABORT("unsupported ncols_dst=%d for XMX MMV", n); + } + } +} + } // namespace ggml_sycl_esimd #endif // GGML_SYCL_ESIMD_HPP diff --git a/ggml/src/ggml-sycl/fattn-common.hpp b/ggml/src/ggml-sycl/fattn-common.hpp index 2e8ac6af3fc8..c37326336db1 100644 --- a/ggml/src/ggml-sycl/fattn-common.hpp +++ b/ggml/src/ggml-sycl/fattn-common.hpp @@ -832,6 +832,29 @@ static void flash_attn_combine_results(const float * __restrict__ VKQ_parts, dst[tid] = VKQ_numerator / VKQ_denominator; } +// Carries the sub-group size (and grf_size_automatic when use_large_grf) as +// kernel properties via get(properties_tag), in place of the +// reqd_sub_group_size attribute and the deprecated parallel_for overload. +template +struct props_kernel { + KernelFunc kernel; + + void operator()(sycl::nd_item<3> item) const { + kernel(item); + } + + auto get(sycl::ext::oneapi::experimental::properties_tag) const { + if constexpr (UseGrf) { + return sycl::ext::oneapi::experimental::properties{ + sycl::ext::intel::experimental::grf_size_automatic, + sycl::ext::oneapi::experimental::sub_group_size }; + } else { + return sycl::ext::oneapi::experimental::properties{ + sycl::ext::oneapi::experimental::sub_group_size }; + } + } +}; + template static void lauch_kernel( dpct::dim3 group_range, @@ -881,7 +904,7 @@ static void lauch_kernel( static_cast>(group_range * local_range), static_cast>(local_range)); - const auto kernel = [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(warp_size)]] { + const auto kernel = [=](sycl::nd_item<3> item_ct1) { GGML_UNUSED(item_ct1); fattn_kernel(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, max_bias, m0, m1, n_head_log2, logit_softcap, ne00, @@ -892,14 +915,7 @@ static void lauch_kernel( q->submit([&](sycl::handler &cgh) { // grf_size_automatic lets the compiler use the large register file when the kernel needs it. grf_size<256> would say the same but is undefined on devices that do not have it. - if constexpr (use_large_grf) { - cgh.parallel_for( - rng, - sycl::ext::oneapi::experimental::properties{ sycl::ext::intel::experimental::grf_size_automatic }, - kernel); - } else { - cgh.parallel_for(rng, kernel); - } + cgh.parallel_for(rng, props_kernel{kernel}); }); } diff --git a/ggml/src/ggml-sycl/fattn-dpas.cpp b/ggml/src/ggml-sycl/fattn-dpas.cpp new file mode 100644 index 000000000000..fb0b3a8161a3 --- /dev/null +++ b/ggml/src/ggml-sycl/fattn-dpas.cpp @@ -0,0 +1,722 @@ +#include +#include +#include "dpct/helper.hpp" +#include "common.hpp" +#include "fattn-common.hpp" +#include "fattn-dpas.hpp" + +// GGML_SYCL_SUPPORT_XMX=OFF builds skip the DPAS below, as do spir64_gen builds for sub-group 8 +// targets (Xe-HPG) or mixed target lists, which cannot compile it +#if !defined(GGML_SYCL_SUPPORT_XMX) || (defined(GGML_SYCL_XMX_AOT_SG) && GGML_SYCL_XMX_AOT_SG != 16) +#define GGML_SYCL_FA_DPAS_BUILD 0 +#else +#define GGML_SYCL_FA_DPAS_BUILD 1 +#endif + +#if GGML_SYCL_FA_DPAS_BUILD +static constexpr int FA_DPAS_WG = 256; // work-group size +static constexpr int FA_DPAS_NSG = 16; // sub-groups of 16 lanes +static constexpr int FA_DPAS_MAX_Q = 31; // larger batches go to the prefill kernels +static constexpr int FA_DPAS_MAX_G = 32; // query heads per KV head +static constexpr float FA_DPAS_MINF = -1.0e30f; // finite start value of the running max + +static bool fattn_dpas_support_arch(gpu_arch arch) { + return arch == gpu_arch::intel_gpu_bmg_g21 || arch == gpu_arch::intel_gpu_bmg_g31 || + arch == gpu_arch::intel_gpu_lnl_m || arch == gpu_arch::intel_gpu_ptl_h || + arch == gpu_arch::intel_gpu_ptl_u || arch == gpu_arch::intel_gpu_wcl; +} + +// head sizes with a compiled kernel (multiples of the 32-dim q4_0 / q8_0 block) +static bool fattn_dpas_head_ok(int64_t d) { + return d == 64 || d == 96 || d == 128 || d == 256 || d == 512; +} +#endif // GGML_SYCL_FA_DPAS_BUILD + +bool ggml_sycl_flash_attn_ext_dpas_supported(int device, const ggml_tensor * dst) { +#if !GGML_SYCL_FA_DPAS_BUILD + GGML_UNUSED(device); + GGML_UNUSED(dst); + return false; +#else + if (!g_ggml_sycl_fa_dpas || !fattn_dpas_support_arch(ggml_sycl_info().devices[device].hw_info.arch)) { + return false; + } + + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + + if (Q->type != GGML_TYPE_F32 || (K->type != GGML_TYPE_Q4_0 && K->type != GGML_TYPE_Q8_0) || V->type != K->type || + (sinks && sinks->type != GGML_TYPE_F32)) { + return false; + } + if (!fattn_dpas_head_ok(K->ne[0]) || V->ne[0] != K->ne[0] || Q->ne[0] != K->ne[0]) { + return false; + } + if (Q->ne[1] < 1 || Q->ne[1] > FA_DPAS_MAX_Q || K->ne[1] < 1) { + return false; + } + if (K->ne[2] < 1 || V->ne[2] != K->ne[2] || Q->ne[2] % K->ne[2] != 0 || Q->ne[2] / K->ne[2] > FA_DPAS_MAX_G) { + return false; + } + if (Q->ne[3] != K->ne[3] || V->ne[3] != K->ne[3]) { + return false; + } + + float max_bias = 0.0f; + float logit_softcap = 0.0f; + memcpy(&max_bias, (const float *) dst->op_params + 1, sizeof(float)); + memcpy(&logit_softcap, (const float *) dst->op_params + 2, sizeof(float)); + if (max_bias != 0.0f || logit_softcap != 0.0f) { + return false; + } + + if (mask && (mask->type != GGML_TYPE_F16 || mask->ne[2] != 1 || mask->nb[0] != sizeof(sycl::half) || + mask->ne[0] < K->ne[1] || mask->ne[1] < Q->ne[1])) { + return false; + } + if (sinks && (sinks->nb[0] != sizeof(float) || sinks->ne[0] < Q->ne[2])) { + return false; + } + if (Q->nb[0] != sizeof(float)) { + return false; + } + // q4_0 / q8_0 rows are read as dwords from the dword at or before the row start: rows must start on 2-byte bounds + // (head sizes with an odd block count, e.g. 96, put every other head 2 bytes into a dword) + // so a row's first/last dword may hold 2 bytes outside it; aligned dwords never cross the 128-byte buffer alignment + for (const ggml_tensor * t : { K, V }) { + if (t->nb[0] != ggml_type_size(t->type) || t->nb[1] % 2 != 0 || t->nb[2] % 2 != 0 || t->nb[3] % 2 != 0 || + (uintptr_t) t->data % 2 != 0) { + return false; + } + } + return true; +#endif +} + +#if GGML_SYCL_FA_DPAS_BUILD + +typedef short fa_dpas_short8 __attribute__((ext_vector_type(8))); +typedef int fa_dpas_int4 __attribute__((ext_vector_type(4))); +typedef int fa_dpas_int8 __attribute__((ext_vector_type(8))); +typedef float fa_dpas_float8 __attribute__((ext_vector_type(8))); + +// Xe2 DPAS (SIMD16, systolic depth 8, repeat count 8) as inline vISA: joint_matrix has no s4 type. +// d = a x b. a: 8 rows x 32 s8, 2 per lane per row. b: 32 x 16 s4, 16 bytes per lane, one column per lane. +static inline void fa_dpas_s8_s4(const fa_dpas_short8 & a, const fa_dpas_int4 & b, fa_dpas_int8 & d) { +#ifdef __SYCL_DEVICE_ONLY__ + __asm__("{\n" + ".decl DB v_type=G type=ud num_elts=64 align=GRF alias=<%1,0>\n" + ".decl DA v_type=G type=ud num_elts=64 align=GRF alias=<%2,0>\n" + "dpas.s4.s8.8.8 (M1, 16) %0.0 %%null.0 DB.0 DA(0,0)\n" + "}\n" + : "=rw"(d) + : "rw"(b), "rw"(a)); +#else + d = 0; + GGML_UNUSED(a); + GGML_UNUSED(b); +#endif +} + +// d = a x b. a: 8 rows x 32 s8, 2 per lane per row. b: 32 x 16 s8, 32 bytes per lane, one column per lane. +static inline void fa_dpas_s8_s8(const fa_dpas_short8 & a, const fa_dpas_int8 & b, fa_dpas_int8 & d) { +#ifdef __SYCL_DEVICE_ONLY__ + __asm__("{\n" + ".decl DB v_type=G type=ud num_elts=128 align=GRF alias=<%1,0>\n" + ".decl DA v_type=G type=ud num_elts=64 align=GRF alias=<%2,0>\n" + "dpas.s8.s8.8.8 (M1, 16) %0.0 %%null.0 DB.0 DA(0,0)\n" + "}\n" + : "=rw"(d) + : "rw"(b), "rw"(a)); +#else + d = 0; + GGML_UNUSED(a); + GGML_UNUSED(b); +#endif +} + +// acc += a x b. a: 8 rows x 16 f16, one per lane per row. b: 16 x 16 f16 as pairs, 8 dwords per lane, one column per lane. +static inline void fa_dpas_f16(const fa_dpas_short8 & a, const fa_dpas_int8 & b, fa_dpas_float8 & acc) { +#ifdef __SYCL_DEVICE_ONLY__ + __asm__("{\n" + ".decl DB v_type=G type=ud num_elts=128 align=GRF alias=<%1,0>\n" + ".decl DA v_type=G type=ud num_elts=64 align=GRF alias=<%2,0>\n" + "dpas.hf.hf.8.8 (M1, 16) %0.0 %0.0 DB.0 DA(0,0)\n" + "}\n" + : "+rw"(acc) + : "rw"(b), "rw"(a)); +#else + GGML_UNUSED(a); + GGML_UNUSED(b); + GGML_UNUSED(acc); +#endif +} + +// Block b of a row = f16 scale + NQ dwords of quants (q4_0: 18 bytes, NQ 4; q8_0: 34 bytes, NQ 8), at byte (2 + 4 NQ) b. +// w = the NQ + 1 dwords from that byte / 4. An odd block starts 2 bytes into w[0]. +template static inline void fa_dpas_split_block(const uint32_t * w, bool odd, uint32_t & sc, uint32_t * q) { + if (!odd) { + sc = w[0] & 0xFFFFu; +#pragma unroll + for (int i = 0; i < NQ; ++i) { + q[i] = (w[i] >> 16) | (w[i + 1] << 16); + } + } else { + sc = w[0] >> 16; +#pragma unroll + for (int i = 0; i < NQ; ++i) { + q[i] = w[i + 1]; + } + } +} + +struct fa_dpas_params { + const char * Q; + const char * K; + const char * V; + const char * mask; + float * dst; + float * parts; // per-split partial results, nsplit > 1 only + sycl::float2 * meta; // per-split (max, sum), nsplit > 1 only + float scale; + const float * sinks; // per query head softmax sink logit, or null + int G; // query heads per KV head + int nq; // query tokens per work-group + int nqc; // token chunks + int ne01; + int ne02; + int ne11; + int ne33; + int nsplit; + int chunk; // keys per split + int64_t nb01, nb02, nb03; + int64_t nb11, nb12, nb13; + int64_t nb21, nb22, nb23; + int64_t nb31, nb33; +}; + +// One work-group = one KV head x nq query tokens x one slice of the keys: S = Q K^T by s8 x s4 / s8 x s8 DPAS on the +// raw K blocks, online softmax, O^T += V^T P^T by f16 DPAS. ST: stage K/V tiles in SLM (1: 16-byte, 2: dword loads). +// LG: 256-register file (no spills at 32 rows, same occupancy). Q8: K/V are q8_0, else q4_0. +template +static void fattn_dpas_kernel(const fa_dpas_params p, const int nkvh, const int ne03, dpct::queue_ptr stream) { + constexpr int RMAX = 16 * NR16; + constexpr int RTMAX = RMAX / 8; // 8-row tiles in Q.K + constexpr int TK = 16 * KG; // keys per tile + static_assert(QK4_0 == QK8_0, "q4_0 and q8_0 blocks hold the same number of dims"); + constexpr int BB = Q8 ? (int) sizeof(block_q8_0) : (int) sizeof(block_q4_0); // bytes per block + constexpr int NQ = (BB - 2) / 4; // quant dwords per block + constexpr int NB = D / QK4_0; // blocks per row + constexpr int DPS = D <= 128 ? 8 : D <= 256 ? 16 : 32; // head dims per sub-group in P.V, inside one 32-dim block + constexpr int NPV = D / DPS; // sub-groups doing P.V, the rest only reach its barrier + constexpr bool ALLPV = NPV == FA_DPAS_NSG; // every sub-group does P.V: no runtime check in the loops + constexpr int XT = DPS / 8; // 8-dim tiles per sub-group in P.V + constexpr int PS = TK + 16; // f16 row stride of P + constexpr int RW = NB * BB / 4; // dwords per row + constexpr bool ODD = (NB * BB) % 4 != 0; // odd block count: rows may start 2 bytes into a dword + constexpr int SW = RW + 1; // odd SLM row stride: no bank conflicts for lane = key + static_assert(D % QK4_0 == 0 && D % DPS == 0 && NPV <= FA_DPAS_NSG && QK4_0 % DPS == 0, "unsupported head size"); + static_assert(ST != 1 || RW % 4 == 0, "16-byte staging needs rows of 16-byte multiples"); + + stream->submit([&](sycl::handler & cgh) { + sycl::local_accessor sQ8(sycl::range<1>(RTMAX * NB * 16), cgh); // Q s8 [tile][block][lane] + sycl::local_accessor sDQ(sycl::range<1>(RTMAX * NB), cgh); // Q scales [tile][block] + sycl::local_accessor sS(sycl::range<1>(RMAX * TK), cgh); // S [row][key] + sycl::local_accessor sP(sycl::range<1>(RMAX * PS / 16), cgh); // P f16 [row][key] + sycl::local_accessor sM(sycl::range<1>(RMAX), cgh); + sycl::local_accessor sL(sycl::range<1>(RMAX), cgh); + sycl::local_accessor sA(sycl::range<1>(RMAX), cgh); + sycl::local_accessor sKV(sycl::range<1>(ST ? TK * SW : 1), cgh); + const sycl::nd_range<3> ndr(sycl::range<3>((size_t) ne03 * p.nqc, nkvh, (size_t) p.nsplit * FA_DPAS_WG), + sycl::range<3>(1, 1, FA_DPAS_WG)); + auto kern = [=](sycl::nd_item<3> it) [[sycl::reqd_sub_group_size(16)]] { + const int tid = it.get_local_id(2); + const int split = it.get_group(2); + const int kvh = it.get_group(1); + const int seq = it.get_group(0) / p.nqc; + const int c0 = (it.get_group(0) % p.nqc) * p.nq; + const int G = p.G; + const int R = p.nq * G; + const int RT = (R + 7) / 8; + auto sg = it.get_sub_group(); + const int w = tid / 16; + const int lane = tid % 16; + short * sQs = (short *) &sQ8[0]; + short * sPs = (short *) &sP[0]; + + // Q -> s8, one scale per row and block. Lane l holds the 2 dims of K column elements 2 l, 2 l + 1: + // q4_0 packs dims l and l + 16 into byte l, q8_0 stores dims in order + for (int e = tid; e < RT * 8 * NB; e += FA_DPAS_WG) { + const int r = e / NB; + const int b = e % NB; + const int c = c0 + r / G; + const bool real = r < R && c < p.ne01; + const float * qr = (const float *) (p.Q + seq * p.nb03 + (int64_t) (real ? c : 0) * p.nb01 + + (int64_t) (kvh * G + (real ? r % G : 0)) * p.nb02) + b * QK4_0; + float x[QK4_0]; + float amax = 0.0f; +#pragma unroll + for (int i = 0; i < QK4_0; ++i) { + x[i] = real ? qr[i] * p.scale : 0.0f; + amax = sycl::fmax(amax, sycl::fabs(x[i])); + } + const float dq = amax / 127.0f; + const float iq = amax > 0.0f ? 127.0f / amax : 0.0f; + const int t = r / 8; + const int m = r % 8; + ((float *) &sDQ[0])[(t * NB + b) * 8 + m] = dq; +#pragma unroll + for (int l = 0; l < 16; ++l) { + const int lo = (int) sycl::rint(x[Q8 ? 2 * l : l] * iq); + const int hi = (int) sycl::rint(x[Q8 ? 2 * l + 1 : l + 16] * iq); + sQs[((t * NB + b) * 16 + l) * 8 + m] = (short) ((lo & 0xFF) | ((hi & 0xFF) << 8)); + } + } + // rows without a query keep P = 0 + for (int e = tid; e < RMAX * PS; e += FA_DPAS_WG) { + sPs[e] = 0; + } + if (tid < RMAX) { + // the sink is one more key with logit sinks[head] and no value; the first key slice owns it + const bool sink = p.sinks && split == 0 && tid < R; + sM[tid] = sink ? p.sinks[kvh * G + tid % G] : FA_DPAS_MINF; + sL[tid] = sink ? 1.0f : 0.0f; + sA[tid] = 1.0f; + } + it.barrier(sycl::access::fence_space::local_space); + + const int k_begin = split * p.chunk; + const int k_end = sycl::min(k_begin + p.chunk, p.ne11); + const char * Kh = p.K + seq * p.nb13 + kvh * p.nb12; + const char * Vh = p.V + seq * p.nb23 + kvh * p.nb22; + const sycl::half * mrow = p.mask ? (const sycl::half *) (p.mask + (seq % p.ne33) * p.nb33) : nullptr; + + // O^T: lane = query row, element m = head dim + fa_dpas_float8 o[NR16][XT]; +#pragma unroll + for (int t = 0; t < NR16; ++t) { +#pragma unroll + for (int x = 0; x < XT; ++x) { + o[t][x] = 0.0f; + } + } + // the dims of this sub-group lie in one V block + const int vb = (DPS * w) / QK4_0; + const int vd0 = (DPS * w) % QK4_0; + + // keys past k_end repeat key k_begin, their scores are -inf + auto stage = [&](const char * base, int64_t nb, int t0) { + if constexpr (ST == 2) { + for (int e = tid; e < TK * RW; e += FA_DPAS_WG) { + const int key = e / RW; + const int q = e - key * RW; + const int j = t0 + key < k_end ? t0 + key : k_begin; + sKV[key * SW + q] = ((const uint32_t *) (base + (int64_t) j * nb))[q]; + } + return; + } + constexpr int RV = ST == 1 ? RW / 4 : 1; + constexpr int NV = TK * RV; + constexpr int PER = (NV + FA_DPAS_WG - 1) / FA_DPAS_WG; + sycl::uint4 v[PER]; +#pragma unroll + for (int i = 0; i < PER; ++i) { + const int e = tid + i * FA_DPAS_WG; + if (e < NV) { + const int key = e / RV; + const int q = e - key * RV; + const int j = t0 + key < k_end ? t0 + key : k_begin; + v[i] = ((const sycl::uint4 *) (base + (int64_t) j * nb))[q]; + } + } +#pragma unroll + for (int i = 0; i < PER; ++i) { + const int e = tid + i * FA_DPAS_WG; + if (e < NV) { + const int key = e / RV; + const int q = e - key * RV; + const int o = key * SW + 4 * q; + sKV[o + 0] = v[i][0]; + sKV[o + 1] = v[i][1]; + sKV[o + 2] = v[i][2]; + sKV[o + 3] = v[i][3]; + } + } + }; + + // the NQ + 1 dwords of block b: of tile key kk in SLM, or of a row that starts 2 ph bytes into dword row[0] + auto load_block = [&](const uint32_t * row, int ph, int kk, int b, uint32_t * wv) { + const int wd = (2 * ph + BB * b) / 4; + if constexpr (ST) { + GGML_UNUSED(row); +#pragma unroll + for (int i = 0; i < NQ + 1; ++i) { + wv[i] = sKV[kk * SW + wd + i]; + } + } else { + GGML_UNUSED(kk); +#pragma unroll + for (int i = 0; i < NQ + 1; ++i) { + wv[i] = row[wd + i]; + } + } + }; + + // start loading the rows of keys t0 .. t0 + TK - 1 into L1 while the current phase computes + auto prefetch_rows = [&](const char * base, int64_t nb, int t0) { + constexpr int NL = RW * 4 / 64 + 1; // cache lines per row + for (int e = tid; e < TK * NL; e += FA_DPAS_WG) { + const int j = t0 + e / NL; + if (j < k_end) { + char * pa = const_cast(base) + (int64_t) j * nb + (e % NL) * 64; + sycl::ext::oneapi::experimental::prefetch(pa, sycl::ext::oneapi::experimental::properties{ sycl::ext::oneapi::experimental::prefetch_hint_L1 }); + } + } + }; + + for (int t0 = k_begin; t0 < k_end; t0 += TK) { + if constexpr (ST) { + stage(Kh, p.nb11, t0); + it.barrier(sycl::access::fence_space::local_space); + } + prefetch_rows(Vh, p.nb21, t0); + + // S = Q K^T, job = (key group, TC row tiles) + const int nch = (RT + TC - 1) / TC; + for (int job = w; job < KG * nch; job += FA_DPAS_NSG) { + const int kg = job % KG; + const int ch = job / KG; + const int j = t0 + kg * 16 + lane; + const bool jv = j < k_end; + const char * kb = Kh + (int64_t) (jv ? j : k_begin) * p.nb11; + const int kp = (ST || !ODD) ? 0 : (int) (((uintptr_t) kb >> 1) & 1); // row starts 2 bytes into a dword + const uint32_t * kr = (const uint32_t *) (kb - 2 * kp); + fa_dpas_float8 s[TC]; +#pragma unroll + for (int tt = 0; tt < TC; ++tt) { + s[tt] = 0.0f; + } +#pragma unroll + for (int b = 0; b < NB; ++b) { + uint32_t wv[NQ + 1]; + uint32_t sc; + uint32_t q[NQ]; + load_block(kr, kp, kg * 16 + lane, b, wv); + fa_dpas_split_block(wv, (b + kp) % 2 != 0, sc, q); + const float dk = static_cast(sycl::bit_cast((uint16_t) sc)); +#pragma unroll + for (int tt = 0; tt < TC; ++tt) { + const int t = ch * TC + tt; + if (t < RT) { + fa_dpas_int8 ia; + if constexpr (Q8) { + const fa_dpas_int8 bv = { (int) q[0], (int) q[1], (int) q[2], (int) q[3], + (int) q[4], (int) q[5], (int) q[6], (int) q[7] }; + fa_dpas_s8_s8(sQ8[(t * NB + b) * 16 + lane], bv, ia); + } else { + // u4 (n + 8) -> s4 n + const fa_dpas_int4 bv = { (int) (q[0] ^ 0x88888888u), (int) (q[1] ^ 0x88888888u), + (int) (q[2] ^ 0x88888888u), (int) (q[3] ^ 0x88888888u) }; + fa_dpas_s8_s4(sQ8[(t * NB + b) * 16 + lane], bv, ia); + } + const fa_dpas_float8 ds = sDQ[t * NB + b] * dk; + s[tt] += __builtin_convertvector(ia, fa_dpas_float8) * ds; + } + } + } +#pragma unroll + for (int tt = 0; tt < TC; ++tt) { + const int t = ch * TC + tt; + if (t < RT) { +#pragma unroll + for (int m = 0; m < 8; ++m) { + const int r = t * 8 + m; + const int c = c0 + r / G; + if (r < R) { + const bool ok = jv && c < p.ne01; + const float mv = (ok && mrow) ? static_cast(mrow[((int64_t) c * p.nb31) / (int64_t) sizeof(sycl::half) + j]) : 0.0f; + sS[r * TK + kg * 16 + lane] = ok ? s[tt][m] + mv : -INFINITY; + } + } + } + } + } + it.barrier(sycl::access::fence_space::local_space); + if constexpr (ST) { + stage(Vh, p.nb21, t0); // the softmax does not use sKV + } + + // online softmax per row -> P + for (int r = w; r < R; r += FA_DPAS_NSG) { + float sv[KG]; + float mt = -INFINITY; +#pragma unroll + for (int i = 0; i < KG; ++i) { + sv[i] = sS[r * TK + i * 16 + lane]; + mt = sycl::fmax(mt, sv[i]); + } + mt = sycl::reduce_over_group(sg, mt, sycl::maximum()); + const float m_old = sM[r]; + const float m_new = sycl::fmax(m_old, mt); + float lt = 0.0f; +#pragma unroll + for (int i = 0; i < KG; ++i) { + const float pv = sycl::native::exp(sv[i] - m_new); + sPs[r * PS + i * 16 + lane] = (short) sycl::bit_cast(sycl::half(pv)); + lt += pv; + } + lt = sycl::reduce_over_group(sg, lt, sycl::plus()); + if (lane == 0) { + const float a = sycl::native::exp(m_old - m_new); + sA[r] = a; + sL[r] = sL[r] * a + lt; + sM[r] = m_new; + } + } + it.barrier(sycl::access::fence_space::local_space); + + prefetch_rows(Kh, p.nb11, t0 + TK); + + // O^T = diag(alpha) O^T + V^T P^T. A = V^T (8 dims x 16 keys, lane = key), B = P^T (16 keys x 16 rows) +#pragma unroll + for (int t = 0; t < NR16; ++t) { + const float a = sA[t * 16 + lane]; +#pragma unroll + for (int x = 0; x < XT; ++x) { + o[t][x] *= a; + } + } +#pragma unroll 1 + for (int kg = 0; kg < ((ALLPV || w < NPV) ? KG : 0); ++kg) { + const int j = t0 + kg * 16 + lane; + const bool jv = j < k_end; + const char * vbp = Vh + (int64_t) (jv ? j : k_begin) * p.nb21; + const int vp = (ST || !ODD) ? 0 : (int) (((uintptr_t) vbp >> 1) & 1); + const uint32_t * vr = (const uint32_t *) (vbp - 2 * vp); + uint32_t wv[NQ + 1]; + uint32_t sc; + uint32_t q[NQ]; + load_block(vr, vp, kg * 16 + lane, vb, wv); + fa_dpas_split_block(wv, (vb + vp) % 2 != 0, sc, q); + const float dv = jv ? static_cast(sycl::bit_cast((uint16_t) sc)) : 0.0f; + fa_dpas_short8 va[XT]; +#pragma unroll + for (int x = 0; x < XT; ++x) { +#pragma unroll + for (int m = 0; m < 8; ++m) { + const int d = vd0 + x * 8 + m; + int v; + if constexpr (Q8) { + v = (int8_t) ((q[d / 4] >> (8 * (d % 4))) & 0xFF); + } else { + const int byte = d % 16; + v = (int) ((q[byte / 4] >> (8 * (byte % 4) + 4 * (d / 16))) & 0xF) - 8; + } + va[x][m] = (short) sycl::bit_cast(sycl::half((float) v * dv)); + } + } +#pragma unroll + for (int t = 0; t < NR16; ++t) { + const fa_dpas_int8 pb = sP[((t * 16 + lane) * PS + kg * 16) / 16]; +#pragma unroll + for (int x = 0; x < XT; ++x) { + fa_dpas_f16(va[x], pb, o[t][x]); + } + } + } + it.barrier(sycl::access::fence_space::local_space); + } + +#pragma unroll + for (int t = 0; t < NR16; ++t) { + const int r = t * 16 + lane; + const int c = c0 + r / G; + if ((ALLPV || w < NPV) && r < R && c < p.ne01) { + const int64_t jdu = ((int64_t) seq * p.ne01 + c) * p.ne02 + kvh * G + r % G; + const float l = sL[r]; +#pragma unroll + for (int x = 0; x < XT; ++x) { +#pragma unroll + for (int m = 0; m < 8; ++m) { + const int d = w * DPS + x * 8 + m; + if (p.nsplit == 1) { + p.dst[jdu * D + d] = l > 0.0f ? o[t][x][m] / l : 0.0f; + } else { + p.parts[(jdu * p.nsplit + split) * D + d] = o[t][x][m]; + } + } + } + } + } + if (p.nsplit > 1 && tid < R && c0 + tid / G < p.ne01) { + const int64_t jdu = ((int64_t) seq * p.ne01 + c0 + tid / G) * p.ne02 + kvh * G + tid % G; + p.meta[jdu * p.nsplit + split] = sycl::float2(sM[tid], sL[tid]); + } + }; + if constexpr (LG) { + cgh.parallel_for(ndr, sycl::ext::oneapi::experimental::properties{ sycl::ext::intel::experimental::grf_size<256> }, kern); + } else { + cgh.parallel_for(ndr, kern); + } + }); +} + +template +static void fattn_dpas_case(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + constexpr int TK = 16 * KG; + + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + + const int ne01 = Q->ne[1]; + const int ne11 = K->ne[1]; + const int nkvh = K->ne[2]; + const int ne03 = Q->ne[3]; + + fa_dpas_params p; + p.Q = (const char *) Q->data; + p.K = (const char *) K->data; + p.V = (const char *) V->data; + p.mask = mask ? (const char *) mask->data : nullptr; + p.sinks = dst->src[4] ? (const float *) dst->src[4]->data : nullptr; + p.dst = (float *) dst->data; + memcpy(&p.scale, (const float *) dst->op_params + 0, sizeof(float)); + p.G = Q->ne[2] / K->ne[2]; + p.nq = std::max(1, std::min(ne01, 16 * NR16 / p.G)); + p.nqc = (ne01 + p.nq - 1) / p.nq; + p.ne01 = ne01; + p.ne02 = Q->ne[2]; + p.ne11 = ne11; + p.ne33 = mask ? mask->ne[3] : 1; + p.nb01 = Q->nb[1]; + p.nb02 = Q->nb[2]; + p.nb03 = Q->nb[3]; + p.nb11 = K->nb[1]; + p.nb12 = K->nb[2]; + p.nb13 = K->nb[3]; + p.nb21 = V->nb[1]; + p.nb22 = V->nb[2]; + p.nb23 = V->nb[3]; + p.nb31 = mask ? mask->nb[1] : 0; + p.nb33 = mask ? mask->nb[3] : 0; + + // split the keys so that all work-groups run in one wave + // SLM fits about 4 work-groups per Xe2 core with 16 rows, 2 with 32. Xe2 core = 8 EUs, nsm = EUs / 16. + const int xe_cores = std::max(1, ggml_sycl_info().devices[ctx.device].nsm * 2); + const int wave = xe_cores * (NR16 == 1 ? 4 : 2); + const int ntiles = (ne11 + TK - 1) / TK; + int nsplit = std::max(1, std::min(wave / (nkvh * ne03 * p.nqc), ntiles)); + p.chunk = ((ntiles + nsplit - 1) / nsplit) * TK; + nsplit = (ne11 + p.chunk - 1) / p.chunk; + p.nsplit = nsplit; + + ggml_sycl_pool_alloc parts(ctx.pool()); + ggml_sycl_pool_alloc meta(ctx.pool()); + if (nsplit > 1) { + parts.alloc((size_t) nsplit * ggml_nelements(dst)); + meta.alloc((size_t) nsplit * ggml_nrows(dst)); + } + p.parts = parts.get(); + p.meta = meta.get(); + + dpct::queue_ptr stream = ctx.stream(); + // the large register file pays off for 32-row launches from about 4K keys + if (NR16 == 2 && ne11 >= 4096) { + fattn_dpas_kernel(p, nkvh, ne03, stream); + } else { + fattn_dpas_kernel(p, nkvh, ne03, stream); + } + + if (nsplit > 1) { + float * parts_p = parts.get(); + sycl::float2 * meta_p = meta.get(); + float * dst_p = (float *) dst->data; + stream->submit([&](sycl::handler & cgh) { + sycl::local_accessor lm(sycl::range<1>(nsplit * sizeof(sycl::float2)), cgh); + cgh.parallel_for( + sycl::nd_range<3>(sycl::range<3>(Q->ne[3], Q->ne[2], (size_t) ne01 * D), sycl::range<3>(1, 1, D)), + [=](sycl::nd_item<3>) [[sycl::reqd_sub_group_size(16)]] { + flash_attn_combine_results(parts_p, meta_p, dst_p, nsplit, + lm.get_multi_ptr().get()); + }); + }); + } +} + +template static void fattn_dpas_dispatch(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + + const int D = K->ne[0]; + const int G = Q->ne[2] / K->ne[2]; + const int ne01 = Q->ne[1]; + + bool aligned16 = true; + for (const ggml_tensor * t : { K, V }) { + aligned16 = aligned16 && t->nb[1] % 16 == 0 && t->nb[2] % 16 == 0 && t->nb[3] % 16 == 0 && + (uintptr_t) t->data % 16 == 0; + } + + // single token decode: staged K/V tiles are faster at long context + if (D == 256 && ne01 == 1 && G <= 16 && aligned16) { + fattn_dpas_case<256, 1, 8, 1, 1, Q8>(ctx, dst); + return; + } + const bool rows16 = ne01 * G <= 16; + // 256-key tiles for one row tile; 128 at head size 512 so S and the Q copy stay in SLM for the planned waves +#define FATTN_DPAS_D(D_, KG16_) \ + case D_: \ + if (rows16) { \ + fattn_dpas_case(ctx, dst); \ + } else { \ + fattn_dpas_case(ctx, dst); \ + } \ + break; + // q8_0 at head size 128: its 136-byte rows gather poorly per lane, stage them in SLM by coalesced dword loads + bool aligned4 = true; + for (const ggml_tensor * t : { K, V }) { + aligned4 = aligned4 && t->nb[1] % 4 == 0 && t->nb[2] % 4 == 0 && t->nb[3] % 4 == 0 && (uintptr_t) t->data % 4 == 0; + } + if (Q8 && D == 128 && aligned4) { + if (rows16) { + fattn_dpas_case<128, 1, 16, 1, 2, Q8>(ctx, dst); + } else { + fattn_dpas_case<128, 2, 8, 2, 2, Q8>(ctx, dst); + } + return; + } + switch (D) { + FATTN_DPAS_D( 64, 16) + FATTN_DPAS_D( 96, 16) + FATTN_DPAS_D(128, 16) + FATTN_DPAS_D(256, 16) + FATTN_DPAS_D(512, 8) + default: + GGML_ABORT("fattn-dpas: unsupported head size %d", D); + } +#undef FATTN_DPAS_D +} + +void ggml_sycl_flash_attn_ext_dpas(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + if (dst->src[1]->type == GGML_TYPE_Q8_0) { + fattn_dpas_dispatch(ctx, dst); + } else { + fattn_dpas_dispatch(ctx, dst); + } +} + +#else + +void ggml_sycl_flash_attn_ext_dpas(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + GGML_UNUSED(ctx); + GGML_UNUSED(dst); + GGML_ABORT("fattn-dpas: not built for this target"); +} + +#endif // GGML_SYCL_FA_DPAS_BUILD diff --git a/ggml/src/ggml-sycl/fattn-dpas.hpp b/ggml/src/ggml-sycl/fattn-dpas.hpp new file mode 100644 index 000000000000..856cbe7fb879 --- /dev/null +++ b/ggml/src/ggml-sycl/fattn-dpas.hpp @@ -0,0 +1,10 @@ +#ifndef GGML_SYCL_FATTN_DPAS_HPP +#define GGML_SYCL_FATTN_DPAS_HPP + +#include "common.hpp" + +// q4_0 / q8_0 K/V flash attention for decode and small batches on Xe2 XMX (s8 x s4 / s8 x s8 DPAS) +bool ggml_sycl_flash_attn_ext_dpas_supported(int device, const ggml_tensor * dst); +void ggml_sycl_flash_attn_ext_dpas(ggml_backend_sycl_context & ctx, ggml_tensor * dst); + +#endif // GGML_SYCL_FATTN_DPAS_HPP diff --git a/ggml/src/ggml-sycl/fattn-mkl.cpp b/ggml/src/ggml-sycl/fattn-mkl.cpp index 5a5cf69fde28..e3b3553de3aa 100644 --- a/ggml/src/ggml-sycl/fattn-mkl.cpp +++ b/ggml/src/ggml-sycl/fattn-mkl.cpp @@ -14,6 +14,7 @@ #include #include #include +#include #define MKL_FA_CHUNK_SIZE_KV 8192 @@ -130,7 +131,8 @@ static void mkl_fa_online_softmax_chunk( int kvh_head, const sycl::half * mask_data, int64_t mask_head_stride, int64_t mask_row_stride, int mask_n_heads, - float logit_softcap, int64_t wg_size) { + float logit_softcap, int64_t wg_size, + const sycl::event & dep_event) { // One work-group per query row: exactly q_rows groups of wg_size // items. q_rows * wg_size is already a multiple of wg_size, so unlike @@ -138,6 +140,7 @@ static void mkl_fa_online_softmax_chunk( const int64_t wg = q_rows * wg_size; const int local_size = (int) wg_size; // stride in the loops below stream->submit([&](sycl::handler & cgh) { + cgh.depends_on(dep_event); cgh.parallel_for(sycl::nd_range<1>(wg, wg_size), [=](sycl::nd_item<1> item) { const int local_id = (int)item.get_local_id(0); @@ -266,19 +269,21 @@ struct mkl_fa_kv_desc { int64_t D = 0; // ne[0] int64_t nb1 = 0; // byte stride, seq dim int64_t nb2 = 0; // byte stride, head dim + int64_t nb3 = 0; // byte stride, batch dim mkl_fa_kv_desc_mode mode = MKL_FA_KV_MODE_F16_DENSE; int64_t ts = 0; // type size (mode 3 base offset) int64_t s01 = 0; // nc row stride in blocks (mode 3) int64_t s02 = 0; // nc head stride in blocks (mode 3) }; -static mkl_fa_kv_desc mkl_fa_make_desc(const ggml_tensor * T, bool interleaved, int n_kv_heads) { +static mkl_fa_kv_desc mkl_fa_make_desc(const ggml_tensor * T, bool interleaved) { mkl_fa_kv_desc d; d.data = (const char *)T->data; d.type = T->type; d.D = T->ne[0]; d.nb1 = (int64_t)T->nb[1]; d.nb2 = (int64_t)T->nb[2]; + d.nb3 = (int64_t)T->nb[3]; d.ts = (int64_t)ggml_type_size(T->type); if (T->type == GGML_TYPE_F16) { @@ -290,20 +295,8 @@ static mkl_fa_kv_desc mkl_fa_make_desc(const ggml_tensor * T, bool interleaved, d.mode = MKL_FA_KV_MODE_QUANT_CONTIG; } else { d.mode = MKL_FA_KV_MODE_QUANT_NC; - const int64_t bs = (int64_t)ggml_blck_size(T->type); - const int64_t blk_per_row = T->ne[0] / bs; - // True Gemma interleave packs heads within a row (nb[2] < ne[1]*nb[1]) - // → reconstruct physical strides. Padded seq-views (nb[2] > ne[1]*nb[1]) - // already have correct physical strides. - const bool gemma = interleaved && - ((int64_t)T->nb[2] < (int64_t)T->ne[1] * (int64_t)T->nb[1]); - if (gemma) { - d.s01 = (int64_t)n_kv_heads * blk_per_row; - d.s02 = blk_per_row; - } else { - d.s01 = d.nb1 / d.ts; - d.s02 = d.nb2 / d.ts; - } + d.s01 = d.nb1 / d.ts; + d.s02 = d.nb2 / d.ts; } return d; } @@ -311,19 +304,20 @@ static mkl_fa_kv_desc mkl_fa_make_desc(const ggml_tensor * T, bool interleaved, // Dequant one KV-head chunk into a dense [this_chunk x D] fp16 buffer. static void mkl_fa_dequant_chunk( dpct::queue_ptr stream, const mkl_fa_kv_desc & d, ggml_tensor * dst_ctx, - sycl::half * out, int ikvh, int chunk_start, int this_chunk) { + sycl::half * out, int ikvh, int ib, int chunk_start, int this_chunk) { const int64_t D = d.D; switch (d.mode) { case MKL_FA_KV_MODE_F16_DENSE: { + // ib * nb3 selects this batch's KV (nb[3] != ne[1]*nb[1] for batched KV views) const char * base = d.data + (int64_t)ikvh * d.nb2 - + (int64_t)chunk_start * d.nb1; + + (int64_t)chunk_start * d.nb1 + (int64_t)ib * d.nb3; stream->memcpy(out, base, (size_t)this_chunk * D * sizeof(sycl::half)); break; } case MKL_FA_KV_MODE_F16_INTERLEAVED: { const char * base = d.data + (int64_t)ikvh * d.nb2 - + (int64_t)chunk_start * d.nb1; + + (int64_t)chunk_start * d.nb1 + (int64_t)ib * d.nb3; const int64_t row_halfs = d.nb1 / (int64_t)sizeof(sycl::half); const sycl::half * src = (const sycl::half *)base; stream->parallel_for( @@ -337,7 +331,7 @@ static void mkl_fa_dequant_chunk( } case MKL_FA_KV_MODE_QUANT_CONTIG: { const char * base = d.data + (int64_t)ikvh * d.nb2 - + (int64_t)chunk_start * d.nb1; + + (int64_t)chunk_start * d.nb1 + (int64_t)ib * d.nb3; to_fp16_sycl_t to_fp16 = ggml_get_to_fp16_sycl(d.type, dst_ctx); to_fp16(base, out, (int64_t)this_chunk * D, stream); break; @@ -345,7 +339,7 @@ static void mkl_fa_dequant_chunk( default: { // MKL_FA_KV_MODE_QUANT_NC to_fp16_nc_sycl_t to_fp16 = ggml_get_to_fp16_nc_sycl(d.type); const int64_t base_blocks = (int64_t)ikvh * d.s02 - + (int64_t)chunk_start * d.s01; + + (int64_t)chunk_start * d.s01 + (int64_t)ib * d.nb3 / d.ts; const char * base = d.data + base_blocks * d.ts; // ne02 = ne03 = 1 → s02/s03 inert; head+chunk offset carried by base. to_fp16(base, out, D, this_chunk, 1, 1, d.s01, d.s02, d.s02, stream); @@ -474,9 +468,9 @@ void ggml_sycl_flash_attn_ext_mkl(ggml_backend_sycl_context & ctx, ggml_tensor * const bool v_interleaved = ((int64_t)V->ne[1] * V->nb[1] != V->nb[2]) && V->ne[2] > 1; - const mkl_fa_kv_desc K_desc = mkl_fa_make_desc(K, k_interleaved, n_kv_heads); + const mkl_fa_kv_desc K_desc = mkl_fa_make_desc(K, k_interleaved); const mkl_fa_kv_desc V_desc = V_is_K_view - ? K_desc : mkl_fa_make_desc(V, v_interleaved, n_kv_heads); + ? K_desc : mkl_fa_make_desc(V, v_interleaved); MKL_ACCUM(dequant_time_us, t_deq); @@ -563,9 +557,6 @@ void ggml_sycl_flash_attn_ext_mkl(ggml_backend_sycl_context & ctx, ggml_tensor * KQ_max_ptr, KQ_sum_ptr, VKQ_accum_ptr, n_query_rows, DV, wg_size); - // Sync before MKL GEMM (MKL may use an internal queue) - stream->wait(); - // 3. KV chunk loop (OUTER): dequant each chunk once, then tile queries. for (int chunk_start = 0; chunk_start < n_kv; chunk_start += chunk_size) { int this_chunk = std::min(chunk_size, n_kv - chunk_start); @@ -574,34 +565,31 @@ void ggml_sycl_flash_attn_ext_mkl(ggml_backend_sycl_context & ctx, ggml_tensor * { MKL_TAKE_TIME(t0); mkl_fa_dequant_chunk(stream, K_desc, KQV, - K_chunk_f16_ptr, ikvh, chunk_start, this_chunk); + K_chunk_f16_ptr, ikvh, ib, chunk_start, this_chunk); if (!V_is_K_view) { mkl_fa_dequant_chunk(stream, V_desc, KQV, - V_chunk_f16_ptr, ikvh, chunk_start, this_chunk); + V_chunk_f16_ptr, ikvh, ib, chunk_start, this_chunk); } - stream->wait(); // dequant must be ready before MKL GEMM MKL_ACCUM(dequant_time_us, t0); } // 3b. Query tile loop (INNER) — bounds KQ_f32/S_f16 footprint. for (int q0 = 0; q0 < n_query_rows; q0 += q_tile_rows) { int q_rows = std::min(q_tile_rows, n_query_rows - q0); + sycl::event kq_done, vkq_done; // GEMM: KQ = Q_tile × K_chunk^T { MKL_TAKE_TIME(t0); - sycl::event ev = gemm(*stream, + kq_done = gemm(*stream, transpose::trans, transpose::nontrans, this_chunk, q_rows, DKQ, alpha, K_chunk_f16_ptr, DKQ, Q_head_f16_ptr + (int64_t)q0 * DKQ, DKQ, beta, - KQ_f32_ptr, this_chunk); - try { ev.wait_and_throw(); } catch (sycl::exception & e) { - GGML_LOG_INFO("[MKL-FA] GEMM KQ: %s\n", e.what()); - GGML_ABORT("MKL GEMM KQ failed"); - } + KQ_f32_ptr, this_chunk, + std::vector{*stream->ext_oneapi_get_last_event()}); MKL_ACCUM(gemm_kq_time_us, t0); } // Online softmax over this chunk for this query tile @@ -615,26 +603,22 @@ void ggml_sycl_flash_attn_ext_mkl(ggml_backend_sycl_context & ctx, ggml_tensor * kvh_base_head, mask_batch, mask_head_stride, mask_row_stride, mask_n_heads, - logit_softcap, wg_size); - stream->wait(); // S_f16 must be ready for GEMM + logit_softcap, wg_size, kq_done); MKL_ACCUM(softmax_time_us, t0); } // GEMM: VKQ_chunk = S × V_chunk { MKL_TAKE_TIME(t0); - sycl::event ev = gemm(*stream, + vkq_done = gemm(*stream, transpose::nontrans, transpose::nontrans, DV, q_rows, this_chunk, alpha, V_chunk_f16_ptr, DV, S_f16_ptr, this_chunk, beta, - VKQ_chunk_ptr, DV); - try { ev.wait_and_throw(); } catch (sycl::exception & e) { - GGML_LOG_INFO("[MKL-FA] GEMM VKQ: %s\n", e.what()); - GGML_ABORT("MKL GEMM VKQ failed"); - } + VKQ_chunk_ptr, DV, + std::vector{*stream->ext_oneapi_get_last_event()}); MKL_ACCUM(gemm_vkq_time_us, t0); } // VKQ_accum[q0..] += VKQ_chunk @@ -644,6 +628,7 @@ void ggml_sycl_flash_attn_ext_mkl(ggml_backend_sycl_context & ctx, ggml_tensor * * wg_size; float * accum = VKQ_accum_ptr + (int64_t)q0 * DV; stream->submit([&](sycl::handler & cgh) { + cgh.depends_on(vkq_done); cgh.parallel_for(sycl::nd_range<1>(wg, wg_size), [=](sycl::nd_item<1> item) { int64_t i = item.get_global_id(0); diff --git a/ggml/src/ggml-sycl/fattn-onednn.cpp b/ggml/src/ggml-sycl/fattn-onednn.cpp index 6e030940a507..4691c8600f18 100644 --- a/ggml/src/ggml-sycl/fattn-onednn.cpp +++ b/ggml/src/ggml-sycl/fattn-onednn.cpp @@ -306,29 +306,15 @@ void ggml_sycl_flash_attn_ext_onednn(ggml_backend_sycl_context & ctx, ggml_tenso { const char * K_data = (const char *)K->data; const bool k_non_dense = ((int64_t)K->ne[1] * K->nb[1] != K->nb[2]) && K->ne[2] > 1; - const bool k_gemma = k_non_dense && - ((int64_t)K->nb[2] < (int64_t)K->ne[1] * (int64_t)K->nb[1]); if (ggml_is_contiguously_allocated(K) && !k_non_dense) { to_fp16_sycl_t to_fp16 = ggml_get_to_fp16_sycl(K->type, dst); to_fp16(K_data, K_ptr, ggml_nelements(K), stream); } else { - const size_t bs = ggml_blck_size(K->type); const size_t ts = ggml_type_size(K->type); to_fp16_nc_sycl_t to_fp16 = ggml_get_to_fp16_nc_sycl(K->type); - int64_t s01, s02, s03; - if (k_gemma) { - const int64_t blk_per_row = (int64_t)K->ne[0] / bs; - s01 = (int64_t)Hkv * blk_per_row; - s02 = blk_per_row; - s03 = (int64_t)K->ne[1] * s01; - } else { - s01 = (int64_t)K->nb[1] / ts; - s02 = (int64_t)K->nb[2] / ts; - s03 = (int64_t)K->nb[3] / ts; - } to_fp16(K_data, K_ptr, K->ne[0], K->ne[1], K->ne[2], K->ne[3], - s01, s02, s03, stream); + (int64_t)K->nb[1] / ts, (int64_t)K->nb[2] / ts, (int64_t)K->nb[3] / ts, stream); } } // Quantized V: always dequant separately. Even when K and V share @@ -340,29 +326,15 @@ void ggml_sycl_flash_attn_ext_onednn(ggml_backend_sycl_context & ctx, ggml_tenso { const char * V_data = (const char *)V->data; const bool v_non_dense = ((int64_t)V->ne[1] * V->nb[1] != V->nb[2]) && V->ne[2] > 1; - const bool v_gemma = v_non_dense && - ((int64_t)V->nb[2] < (int64_t)V->ne[1] * (int64_t)V->nb[1]); if (ggml_is_contiguously_allocated(V) && !v_non_dense) { to_fp16_sycl_t to_fp16 = ggml_get_to_fp16_sycl(V->type, dst); to_fp16(V_data, V_ptr, ggml_nelements(V), stream); } else { - const size_t bs = ggml_blck_size(V->type); const size_t ts = ggml_type_size(V->type); to_fp16_nc_sycl_t to_fp16 = ggml_get_to_fp16_nc_sycl(V->type); - int64_t s01, s02, s03; - if (v_gemma) { - const int64_t blk_per_row = (int64_t)V->ne[0] / bs; - s01 = (int64_t)V->ne[2] * blk_per_row; - s02 = blk_per_row; - s03 = (int64_t)V->ne[1] * s01; - } else { - s01 = (int64_t)V->nb[1] / ts; - s02 = (int64_t)V->nb[2] / ts; - s03 = (int64_t)V->nb[3] / ts; - } to_fp16(V_data, V_ptr, V->ne[0], V->ne[1], V->ne[2], V->ne[3], - s01, s02, s03, stream); + (int64_t)V->nb[1] / ts, (int64_t)V->nb[2] / ts, (int64_t)V->nb[3] / ts, stream); } } } else { diff --git a/ggml/src/ggml-sycl/fattn-sparse.cpp b/ggml/src/ggml-sycl/fattn-sparse.cpp index df283709460d..0c56d43aae78 100644 --- a/ggml/src/ggml-sycl/fattn-sparse.cpp +++ b/ggml/src/ggml-sycl/fattn-sparse.cpp @@ -202,7 +202,8 @@ bool ggml_sycl_flash_attn_ext_sparse(ggml_backend_sycl_context & ctx, ggml_tenso uint8_t * d_V = v_alloc.get(); sycl::half * d_mask = m_alloc.get(); - SYCL_CHECK(CHECK_TRY_ERROR(stream->memset(d_cnt, 0, sizeof(int32_t)))); + // reset with a kernel: on Level Zero a queue memset is not always ordered before the next kernel + stream->single_task([=]() { *d_cnt = 0; }); sparse_fa_compact_mask(stream, (const sycl::half *) mask->data, d_idx, d_cnt, n_kv, n_kv_g); @@ -217,7 +218,7 @@ bool ggml_sycl_flash_attn_ext_sparse(ggml_backend_sycl_context & ctx, ggml_tenso d_idx, d_cnt, n_kv_g, n_rows_m, mask->nb[1] / sizeof(sycl::half)); - if (sparse_fa_debug()) { + if (sparse_fa_debug() && stream->ext_oneapi_get_state() != sycl::ext::oneapi::experimental::queue_state::recording) { int32_t h_cnt = 0; SYCL_CHECK(CHECK_TRY_ERROR(stream->memcpy(&h_cnt, d_cnt, sizeof(int32_t)))); SYCL_CHECK(CHECK_TRY_ERROR(stream->wait())); diff --git a/ggml/src/ggml-sycl/fattn-tile.cpp b/ggml/src/ggml-sycl/fattn-tile.cpp index 9449d75784d0..db030268e0e3 100644 --- a/ggml/src/ggml-sycl/fattn-tile.cpp +++ b/ggml/src/ggml-sycl/fattn-tile.cpp @@ -54,6 +54,6 @@ void ggml_sycl_flash_attn_ext_tile(ggml_backend_sycl_context & ctx, ggml_tensor } break; default: { GGML_ABORT("Unsupported head size"); - } break; + } } } diff --git a/ggml/src/ggml-sycl/fattn.cpp b/ggml/src/ggml-sycl/fattn.cpp index 8bd946e09583..6f5f8a832951 100644 --- a/ggml/src/ggml-sycl/fattn.cpp +++ b/ggml/src/ggml-sycl/fattn.cpp @@ -20,6 +20,7 @@ #include "fattn.hpp" #include "fattn-onednn.hpp" #include "fattn-sparse.hpp" +#include "fattn-dpas.hpp" #define FATTN_VEC_CASE(D, type_K, type_V) \ { \ @@ -97,6 +98,7 @@ static void ggml_sycl_flash_attn_ext_vec(ggml_backend_sycl_context & ctx, ggml_t enum best_fattn_kernel { BEST_FATTN_KERNEL_NONE = 0, BEST_FATTN_KERNEL_VEC = 100, + BEST_FATTN_KERNEL_DPAS = 120, // q4_0 / q8_0 K/V decode on Xe2 XMX BEST_FATTN_KERNEL_ONEDNN = 150, // oneDNN SDPA: native F16 (PR #25222) BEST_FATTN_KERNEL_TILE = 200, BEST_FATTN_KERNEL_MKL = 300, @@ -244,6 +246,11 @@ static best_fattn_kernel ggml_sycl_get_best_fattn_kernel(const int device, const return BEST_FATTN_KERNEL_NONE; } + // q4_0 / q8_0 K/V decode and small batches on Xe2: read the cache directly, no F16 copy of K and V + if (ggml_sycl_flash_attn_ext_dpas_supported(device, dst)) { + return BEST_FATTN_KERNEL_DPAS; + } + // For small batch sizes the vector kernel may be preferable over the kernels optimized for large batch sizes. // BF16 is excluded: the VEC kernel has no BF16 template (it needs GGML_SYCL_FA_ALL_QUANTS for non-F16/Q4_0/Q8_0). const bool has_bf16 = (K->type == GGML_TYPE_BF16 || V->type == GGML_TYPE_BF16); @@ -281,6 +288,22 @@ static best_fattn_kernel ggml_sycl_get_best_fattn_kernel(const int device, const void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { ggml_sycl_set_device(ctx.device); + ggml_tensor * Q = dst->src[0]; + ggml_tensor * K = dst->src[1]; + ggml_tensor * V = dst->src[2]; + if (K && Q && K->ne[0] != Q->ne[0] && Q->ne[0] > 0 && K->ne[0] % Q->ne[0] == 0) { + const int64_t d = Q->ne[0]; + const int64_t n_heads = (K->ne[0] * K->ne[2]) / d; + K->ne[0] = d; + K->ne[2] = n_heads; + } + if (V && Q && V->ne[0] != Q->ne[0] && Q->ne[0] > 0 && V->ne[0] % Q->ne[0] == 0) { + const int64_t d = Q->ne[0]; + const int64_t n_heads = (V->ne[0] * V->ne[2]) / d; + V->ne[0] = d; + V->ne[2] = n_heads; + } + // sparse nodes are gathered down to n_kv_max rows and re-dispatched here if (ggml_sycl_flash_attn_ext_sparse(ctx, dst)) { return; @@ -302,6 +325,7 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst if (k == BEST_FATTN_KERNEL_MKL) kname = "MKL"; if (k == BEST_FATTN_KERNEL_ONEDNN) kname = "ONEDNN"; if (k == BEST_FATTN_KERNEL_VEC) kname = "VEC"; + if (k == BEST_FATTN_KERNEL_DPAS) kname = "DPAS"; int64_t delta = 0; if (Dk == 256) { delta = cur_nkv - last_nkv_d256; @@ -334,6 +358,9 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst case BEST_FATTN_KERNEL_VEC: ggml_sycl_flash_attn_ext_vec(ctx, dst); break; + case BEST_FATTN_KERNEL_DPAS: + ggml_sycl_flash_attn_ext_dpas(ctx, dst); + break; case BEST_FATTN_KERNEL_MKL: ggml_sycl_flash_attn_ext_mkl(ctx, dst); break; @@ -349,10 +376,10 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst const ggml_tensor * K_diag = dst->src[1]; const ggml_tensor * V_diag = dst->src[2]; const ggml_tensor * Q_diag = dst->src[0]; - if (K_diag->ne[1] >= 1024) { + dpct::queue_ptr q = ctx.stream(); + if (K_diag->ne[1] >= 1024 && q->ext_oneapi_get_state() != sycl::ext::oneapi::experimental::queue_state::recording) { fa_diag_count++; float diag_buf[64]; - dpct::queue_ptr q = ctx.stream(); q->memcpy(diag_buf, dst->data, 64 * sizeof(float)); q->wait(); const char * kname = "???"; @@ -361,6 +388,7 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst if (kb == BEST_FATTN_KERNEL_MKL) kname = "MKL"; if (kb == BEST_FATTN_KERNEL_TILE) kname = "TILE"; if (kb == BEST_FATTN_KERNEL_VEC) kname = "VEC"; + if (kb == BEST_FATTN_KERNEL_DPAS) kname = "DPAS"; GGML_LOG_INFO("[FA-DIAG] #%d %s D=%d n_kv=%lld n_q=%lld " "n_qh=%lld n_kvh=%lld K=%s V=%s " "nb1=%zu nb2=%zu first 64 floats:\n", @@ -388,6 +416,14 @@ bool ggml_sycl_flash_attn_ext_supported(int device, const ggml_tensor * dst) { return ggml_sycl_get_best_fattn_kernel(device, dst) != BEST_FATTN_KERNEL_NONE; } +bool ggml_sycl_flash_attn_ext_needs_sync(int device, const ggml_tensor * dst) { + return ggml_sycl_get_best_fattn_kernel(device, dst) == BEST_FATTN_KERNEL_MKL; +} + +bool ggml_sycl_flash_attn_ext_uses_onednn(int device, const ggml_tensor * dst) { + return ggml_sycl_get_best_fattn_kernel(device, dst) == BEST_FATTN_KERNEL_ONEDNN; +} + static uintptr_t ggml_sycl_fattn_reserve_halves(ggml_sycl_fattn_extra & extra, size_t n_halves) { if (n_halves == 0) { return 0; diff --git a/ggml/src/ggml-sycl/fattn.hpp b/ggml/src/ggml-sycl/fattn.hpp index f803aa2a804a..8ba634223be3 100644 --- a/ggml/src/ggml-sycl/fattn.hpp +++ b/ggml/src/ggml-sycl/fattn.hpp @@ -19,6 +19,12 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst bool ggml_sycl_flash_attn_ext_supported(int device, const ggml_tensor * dst); +// Reports if flash attention runs this node with the oneMKL kernel, which waits on the host +bool ggml_sycl_flash_attn_ext_needs_sync(int device, const ggml_tensor * dst); + +// Reports if flash attention runs this node with the oneDNN kernel +bool ggml_sycl_flash_attn_ext_uses_onednn(int device, const ggml_tensor * dst); + // Scratch that flash attention needs beyond the output tensor struct ggml_sycl_fattn_extra { uintptr_t K_buffer_ptr = 0; // F16 copy of the K cache diff --git a/ggml/src/ggml-sycl/fused-gemm.cpp b/ggml/src/ggml-sycl/fused-gemm.cpp index 38c69bc6b1fd..3024f139d5dc 100644 --- a/ggml/src/ggml-sycl/fused-gemm.cpp +++ b/ggml/src/ggml-sycl/fused-gemm.cpp @@ -860,7 +860,7 @@ static void fused_dequant_gemm_tile( } } -template +template static void fused_dequant_gemm_launch(const void * src0, const typename S::tsb * packed, float * dst, const int M, const int N, const int Npad, const int K, const int ldd, const int64_t groups_n, const int64_t groups_m, dpct::queue_ptr stream) { @@ -871,8 +871,8 @@ static void fused_dequant_gemm_launch(const void * src0, const typename S::tsb * sycl::nd_range<2>(sycl::range<2>(groups_n, groups_m * S::WG_SIZE), sycl::range<2>(1, S::WG_SIZE)), [=](sycl::nd_item<2> item) [[sycl::reqd_sub_group_size(S::SG)]] { const int n0 = item.get_group(0) * S::BN; - fused_dequant_gemm_tile((const block_q_t *) src0, packed, dst, M, Npad, K, ldd, - n0, n0, N, tile_a, tile_c, item); + fused_dequant_gemm_tile((const block_q_t *) src0, packed, dst, M, Npad, K, + ldd, n0, n0, N, tile_a, tile_c, item); }); }); } @@ -974,7 +974,7 @@ template static bool fg_visit_type(ggml_type type, bool reordered, } template -static bool fg_fused_run(ggml_type src0_type, const void * src0, const void * src1, ggml_type src1_type, +static bool fg_fused_run(ggml_type src0_type, bool src0_reordered, const void * src0, const void * src1, ggml_type src1_type, float * dst, int64_t M, int64_t N, int64_t K, int64_t ldd, ggml_sycl_pool & pool, dpct::queue_ptr stream) { const int64_t groups_n = (N + S::BN - 1) / S::BN; @@ -992,21 +992,27 @@ static bool fg_fused_run(ggml_type src0_type, const void * src0, const void * sr } const typename S::tsb * packed = packed_b.get(); - return fg_visit_type(src0_type, false, [&](auto tag) { + return fg_visit_type(src0_type, src0_reordered, [&](auto tag) { using block_q_t = typename decltype(tag)::type; if constexpr (fg_plain_ok()) { - fused_dequant_gemm_launch(src0, packed, dst, (int) M, (int) N, Npad, (int) K, (int) ldd, - groups_n, groups_m, stream); + fused_dequant_gemm_launch(src0, packed, dst, (int) M, (int) N, + Npad, (int) K, (int) ldd, groups_n, + groups_m, stream); } }); } -bool ggml_sycl_fused_dequant_gemm(ggml_type src0_type, const void * src0, const void * src1, ggml_type src1_type, +bool ggml_sycl_fused_dequant_gemm(ggml_type src0_type, bool src0_reordered, const void * src0, const void * src1, ggml_type src1_type, int32_t src1_prec, float * dst, int64_t M, int64_t N, int64_t K, int64_t ldd, ggml_sycl_pool & pool, dpct::queue_ptr stream) { - // every BN columns dequantize A again, so wide N is left to the library GEMM + // every BN columns dequantize A again, so wide N is left to the library GEMM. + // src0_reordered: the persistent weight reorder may have been installed on this + // tensor by an earlier small-batch mul_mat; the A stage then has to decode the + // SoA layout. Types without an SoA stage (fg_soa::supported == false) + // decline via fg_visit_layout and the caller falls through to the + // reorder-aware conversion route. bool plain_ok = false; - fg_visit_type(src0_type, false, [&](auto tag) { plain_ok = fg_plain_ok(); }); + fg_visit_type(src0_type, src0_reordered, [&](auto tag) { plain_ok = fg_plain_ok(); }); if (g_ggml_sycl_dynamic_precision == GGML_SYCL_DYNAMIC_PRECISION_F32 || !ggml_sycl_xmx_gather_type_enabled(src0_type) || !plain_ok) { return false; @@ -1023,7 +1029,7 @@ bool ggml_sycl_fused_dequant_gemm(ggml_type src0_type, const void * src0, const } bool launched = false; fg_visit_combo(combo, [&](auto s) { - launched = fg_fused_run(src0_type, src0, src1, src1_type, dst, M, N, K, ldd, pool, stream); + launched = fg_fused_run(src0_type, src0_reordered, src0, src1, src1_type, dst, M, N, K, ldd, pool, stream); }); return launched; } diff --git a/ggml/src/ggml-sycl/fused-gemm.hpp b/ggml/src/ggml-sycl/fused-gemm.hpp index 2989892048cd..226676d12d50 100644 --- a/ggml/src/ggml-sycl/fused-gemm.hpp +++ b/ggml/src/ggml-sycl/fused-gemm.hpp @@ -69,7 +69,7 @@ inline bool ggml_sycl_xmx_gather_type_enabled(ggml_type src0_type) { // (op_params[3], [TAG_GGML_PREC]); the accumulator is f32, which meets any request. // q8_0 and the k-quants are not handled here, only in the grouped path below. // Returns false when the case is not handled (type, device, precision, or shape). -bool ggml_sycl_fused_dequant_gemm(ggml_type src0_type, const void * src0, const void * src1, ggml_type src1_type, +bool ggml_sycl_fused_dequant_gemm(ggml_type src0_type, bool src0_reordered, const void * src0, const void * src1, ggml_type src1_type, int32_t src1_prec, float * dst, int64_t M, int64_t N, int64_t K, int64_t ldd, ggml_sycl_pool & pool, dpct::queue_ptr stream); diff --git a/ggml/src/ggml-sycl/fusion.cpp b/ggml/src/ggml-sycl/fusion.cpp index 79fe13a1d0f4..9b553829be6d 100644 --- a/ggml/src/ggml-sycl/fusion.cpp +++ b/ggml/src/ggml-sycl/fusion.cpp @@ -4,7 +4,7 @@ #include // mul_mat(gate) + mul_mat(up) + GLU: graph shape and tensor properties only. Backend state -// (weight layout, split buffers, DMMV) is checked by ggml_sycl_mul_mat_glu_mmvq_fused(). +// (weight layout, split buffers, DMMV) is checked by ggml_sycl_op_mul_mat_glu_fused(). static bool ggml_sycl_should_fuse_mul_mat_glu(const ggml_tensor * gate, const ggml_tensor * up, const ggml_tensor * glu) { // the fused epilogue implements these two; the rest fall back to the standalone GLU kernels @@ -32,12 +32,29 @@ static bool ggml_sycl_should_fuse_mul_mat_glu(const ggml_tensor * gate, const gg return false; } - // fused GEMVs walk whole QK_K super-blocks: the reorder kernel covers same-type + // fused K-quant GEMVs walk whole QK_K super-blocks: the reorder kernel covers same-type // q4_K, the plain-layout kernel covers q5_K / iq4_xs pairs incl. mixed gate/up types const bool reorder_pair = wu->type == GGML_TYPE_Q4_K && wg->type == GGML_TYPE_Q4_K; const bool plain_pair = (wu->type == GGML_TYPE_Q5_K || wu->type == GGML_TYPE_IQ4_XS) && (wg->type == GGML_TYPE_Q5_K || wg->type == GGML_TYPE_IQ4_XS); - if ((!reorder_pair && !plain_pair) || wu->ne[0] % QK_K != 0) { +#ifdef GGML_SYCL_MMVQ_HAS_XMX + // same-type pairs of the types of the XMX kernels, which also take a few more columns + // (the XMX kernels walk whole QK_K super-blocks, so they need rows of a multiple of QK_K) + const bool xmx_pair = wu->type == wg->type && ggml_sycl_xmx_supports_type(wu->type) && wu->ne[0] % QK_K == 0; +#else + const bool xmx_pair = false; +#endif // GGML_SYCL_MMVQ_HAS_XMX + // the ESIMD kernel covers same-type q2_K..q6_K and q8_0, single column only (as unfused DMMV) +#ifdef GGML_SYCL_DMMV_HAS_ESIMD + const bool esimd_pair = g_ggml_sycl_enable_esimd && wu->type == wg->type && act->ne[1] == 1 && + (wu->type == GGML_TYPE_Q2_K || wu->type == GGML_TYPE_Q3_K || wu->type == GGML_TYPE_Q4_K || + wu->type == GGML_TYPE_Q5_K || wu->type == GGML_TYPE_Q6_K || wu->type == GGML_TYPE_Q8_0); +#else + const bool esimd_pair = false; +#endif + // q8_0 rows are walked in 32-wide blocks, so they only need to be a multiple of QK8_0 + const int64_t row_align = esimd_pair && wu->type == GGML_TYPE_Q8_0 ? QK8_0 : QK_K; + if ((!reorder_pair && !plain_pair && !xmx_pair && !esimd_pair) || wu->ne[0] % row_align != 0) { return false; } @@ -57,7 +74,8 @@ static bool ggml_sycl_should_fuse_mul_mat_glu(const ggml_tensor * gate, const gg return false; } // mat-vec only: one column per decoded token, up to the batch the reorder kernels cover - if (act->ne[1] > MMVQ_MAX_BATCH_SIZE) { + const int max_cols = xmx_pair ? std::max(MMVQ_MAX_BATCH_SIZE, g_ggml_sycl_xmx_glu_max_cols) : MMVQ_MAX_BATCH_SIZE; + if (act->ne[1] > max_cols) { return false; } diff --git a/ggml/src/ggml-sycl/getrows.cpp b/ggml/src/ggml-sycl/getrows.cpp index 4e84bd22253b..7b53e3dcca54 100644 --- a/ggml/src/ggml-sycl/getrows.cpp +++ b/ggml/src/ggml-sycl/getrows.cpp @@ -137,6 +137,47 @@ static void k_get_rows_float( dst_row[i00] = src0_row[i00]; } +// src0 is in reorder layout: all qs of the tensor, then all d +template +static void k_get_rows_reorder( + const void * src0_qs, const void * src0_d, const int32_t * src1, dst_t * dst, + int64_t ne00, int64_t ne12, + size_t s1, size_t s2, size_t s3, + size_t s10, size_t s11, size_t s12, + const sycl::nd_item<3> &item_ct1) { + + const int i00 = (item_ct1.get_group(2) * item_ct1.get_local_range(2) + + item_ct1.get_local_id(2)) * + 2; + const int i10 = item_ct1.get_local_range(1) * item_ct1.get_group(1) + + item_ct1.get_local_id(1); + const int i11 = (item_ct1.get_group(0) * item_ct1.get_local_range(0) + + item_ct1.get_local_id(0)) / + ne12; + const int i12 = (item_ct1.get_group(0) * item_ct1.get_local_range(0) + + item_ct1.get_local_id(0)) % + ne12; + + if (i00 >= ne00) { + return; + } + + const int i01 = src1[i10*s10 + i11*s11 + i12*s12]; + + dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; + + const int64_t ib = (int64_t) i01*(ne00/qk) + i00/qk; // block index in the whole tensor + const int iqs = (i00%qk)/qr; + const int iybs = i00 - i00%qk; + const int y_offset = qr == 1 ? 1 : qk/2; + + dfloat2 v; + dequantize_kernel(src0_d, ib, src0_qs, ib*(qk/qr) + iqs, v); + + dst_row[iybs + iqs + 0] = v.x(); + dst_row[iybs + iqs + y_offset] = v.y(); +} + template static void get_rows_sycl(ggml_backend_sycl_context & ctx, const ggml_tensor *src0, const ggml_tensor *src1, ggml_tensor *dst, const void *src0_dd, @@ -173,6 +214,139 @@ static void get_rows_sycl(ggml_backend_sycl_context & ctx, const ggml_tensor *sr GGML_UNUSED(ctx); } +template +static void get_rows_sycl_reorder(const ggml_tensor *src0, const ggml_tensor *src1, + ggml_tensor *dst, const void *src0_dd, + const int32_t *src1_dd, float *dst_dd, + queue_ptr stream) { + + GGML_TENSOR_BINARY_OP_LOCALS + + // reorder is done only on 2D weights + GGML_ASSERT(ne02 == 1 && ne03 == 1); + GGML_ASSERT(ne00 % 2 == 0); + + const sycl::range<3> block_dims(1, 1, SYCL_GET_ROWS_BLOCK_SIZE); + const int block_num_x = (ne00 + 2*SYCL_GET_ROWS_BLOCK_SIZE - 1) / (2*SYCL_GET_ROWS_BLOCK_SIZE); + const sycl::range<3> block_nums(ne11 * ne12, ne10, block_num_x); + + const size_t s1 = nb1 / ggml_element_size(dst); + const size_t s2 = nb2 / ggml_element_size(dst); + const size_t s3 = nb3 / ggml_element_size(dst); + + const size_t s10 = nb10 / ggml_element_size(src1); + const size_t s11 = nb11 / ggml_element_size(src1); + const size_t s12 = nb12 / ggml_element_size(src1); + + const void * src0_d = (const char *) src0_dd + ne00*ne01/qr; + + stream->parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + k_get_rows_reorder( + src0_dd, src0_d, src1_dd, dst_dd, ne00, ne12, s1, s2, + s3, s10, s11, s12, item_ct1); + }); + + GGML_UNUSED(src0); +} + +// K-quants in reorder layout: one work-group dequantizes one QK_K block of one row +template +static void get_rows_sycl_reorder_k(const ggml_tensor *src0, const ggml_tensor *src1, + ggml_tensor *dst, const int32_t *src1_dd, float *dst_dd, + queue_ptr stream, F dequantize_block) { + + GGML_TENSOR_BINARY_OP_LOCALS + + // reorder is done only on 2D weights + GGML_ASSERT(ne02 == 1 && ne03 == 1); + GGML_ASSERT(ne00 % QK_K == 0); + + const int64_t nblk = ne00 / QK_K; + const int64_t nb = nblk * ne01; // blocks in the whole tensor + const int64_t ngroups = ne10 * ne11 * ne12 * nblk; + + const size_t s1 = nb1 / ggml_element_size(dst); + const size_t s2 = nb2 / ggml_element_size(dst); + const size_t s3 = nb3 / ggml_element_size(dst); + + const size_t s10 = nb10 / ggml_element_size(src1); + const size_t s11 = nb11 / ggml_element_size(src1); + const size_t s12 = nb12 / ggml_element_size(src1); + + stream->submit([&](sycl::handler & cgh) { + sycl::local_accessor scales_local(sycl::range<1>(nlocal), cgh); + + auto kernel = [=](sycl::nd_item item_ct1) { + const int64_t g = item_ct1.get_group(dims - 1); + const int64_t b = g % nblk; + const int64_t r = g / nblk; + const int64_t i10 = r % ne10; + const int64_t i11 = (r / ne10) % ne11; + const int64_t i12 = r / (ne10 * ne11); + + const int64_t i01 = src1_dd[i10*s10 + i11*s11 + i12*s12]; + + float * y = dst_dd + i10*s1 + i11*s2 + i12*s3 + b*QK_K; + dequantize_block(y, i01*nblk + b, get_pointer(scales_local), item_ct1, nb); + }; + + if constexpr (dims == 1) { + cgh.parallel_for(sycl::nd_range<1>(sycl::range<1>(ngroups * nthreads), sycl::range<1>(nthreads)), kernel); + } else { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, ngroups * nthreads), sycl::range<3>(1, 1, nthreads)), kernel); + } + }); + + GGML_UNUSED(src0); +} + +// IQ3_S / IQ3_XXS in the persistent reorder layout: one work-group of 32 threads +// dequantizes one QK_K block of one requested row, reusing the reorder-aware +// block dequantizers that the dequantize-based mul_mat path already uses. +template +static void get_rows_sycl_reorder_iq3(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, + const ggml_tensor * src1, ggml_tensor * dst, + const int32_t * src1_dd, float * dst_dd, + F dequantize_block) { + GGML_TENSOR_BINARY_OP_LOCALS + + // the persistent reorder is only installed for 2D weights + GGML_ASSERT(ne02 == 1 && ne03 == 1); + GGML_ASSERT(ne00 % QK_K == 0); + + const int64_t nblk = ne00 / QK_K; + const int64_t nb = nblk * ne01; // blocks in the whole tensor + const int64_t ngroups = ne10 * ne11 * ne12 * nblk; + + const size_t s1 = nb1 / ggml_element_size(dst); + const size_t s2 = nb2 / ggml_element_size(dst); + const size_t s3 = nb3 / ggml_element_size(dst); + + const size_t s10 = nb10 / ggml_element_size(src1); + const size_t s11 = nb11 / ggml_element_size(src1); + const size_t s12 = nb12 / ggml_element_size(src1); + + queue_ptr stream = ctx.stream(); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, ngroups * 32), sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + const int64_t g = item_ct1.get_group(2); + const int64_t b = g % nblk; + const int64_t r = g / nblk; + const int64_t i10 = r % ne10; + const int64_t i11 = (r / ne10) % ne11; + const int64_t i12 = r / (ne10 * ne11); + + const int64_t i01 = src1_dd[i10*s10 + i11*s11 + i12*s12]; + + float * y = dst_dd + i10*s1 + i11*s2 + i12*s3 + b*QK_K; + dequantize_block(y, i01*nblk + b, item_ct1, nb); + }); + + GGML_UNUSED(dst); +} + template static void get_rows_sycl_f32(ggml_backend_sycl_context & ctx, const ggml_tensor *src0, const ggml_tensor *src1, ggml_tensor *dst, const void *src0_dd, @@ -332,6 +506,11 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { GGML_ASSERT(dst->nb[0] == ggml_type_size(dst->type)); const int32_t * src1_i32 = (const int32_t *) dst->src[1]->data; + // a weight shared with MUL_MAT (e.g. tied embeddings) can be in the + // persistent reorder layout (incl. IQ3_S / IQ3_XXS since the SYCL IQ3 + // reorder work) + const bool src0_reordered = dst->src[0]->extra && + ((const ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder; /* TODO: Refactor and remove duplicates */ switch (dst->src[0]->type) { case GGML_TYPE_F16: @@ -375,6 +554,15 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_IQ3_XXS: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_iq3(ctx, dst->src[0], dst->src[1], dst, src1_i32, (float *) dst->data, + [=](float * y, int64_t iblk, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_iq3_xxs_reorder(vx, y, iblk, item_ct1, nb, + iq3xxs_grid, ksigns_iq2xs, kmask_iq2xs); + }); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; @@ -387,6 +575,15 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_IQ3_S: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_iq3(ctx, dst->src[0], dst->src[1], dst, src1_i32, (float *) dst->data, + [=](float * y, int64_t iblk, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_iq3_s_reorder(vx, y, iblk, item_ct1, nb, + kmask_iq2xs, iq3s_grid); + }); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; @@ -399,14 +596,37 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q2_K: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_k<3, 64, 1>(dst->src[0], dst->src[1], dst, src1_i32, (float *)dst->data, ctx.stream(), + [=](float * y, int64_t ib, uint8_t * scales_local, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_q2_K_reorder(vx, y, ib, item_ct1, nb); + GGML_UNUSED(scales_local); + }); + break; + } get_rows_sycl_f32(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q3_K: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_k<3, 64, 1>(dst->src[0], dst->src[1], dst, src1_i32, (float *)dst->data, ctx.stream(), + [=](float * y, int64_t ib, uint8_t * scales_local, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_q3_K_reorder(vx, y, ib, item_ct1, nb); + GGML_UNUSED(scales_local); + }); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q4_0: + if (src0_reordered) { + get_rows_sycl_reorder(dst->src[0], dst->src[1], dst, dst->src[0]->data, + src1_i32, (float *)dst->data, ctx.stream()); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; @@ -415,6 +635,14 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q4_K: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_k<1, 32, K_SCALE_SIZE>(dst->src[0], dst->src[1], dst, src1_i32, (float *)dst->data, ctx.stream(), + [=](float * y, int64_t ib, uint8_t * scales_local, const sycl::nd_item<1> & item_ct1, int64_t nb) { + dequantize_block_q4_K_reorder(vx, y, ib, scales_local, item_ct1, nb); + }); + break; + } get_rows_sycl_f32(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; @@ -427,14 +655,36 @@ void ggml_sycl_op_get_rows(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q5_K: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_k<3, 32, K_SCALE_SIZE>(dst->src[0], dst->src[1], dst, src1_i32, (float *)dst->data, ctx.stream(), + [=](float * y, int64_t ib, uint8_t * scales_local, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_q5_K_reorder(vx, y, ib, scales_local, item_ct1, nb); + }); + break; + } get_rows_sycl_f32(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q6_K: + if (src0_reordered) { + const void * vx = dst->src[0]->data; + get_rows_sycl_reorder_k<3, 64, 1>(dst->src[0], dst->src[1], dst, src1_i32, (float *)dst->data, ctx.stream(), + [=](float * y, int64_t ib, uint8_t * scales_local, const sycl::nd_item<3> & item_ct1, int64_t nb) { + dequantize_block_q6_K_reorder(vx, y, ib, item_ct1, nb); + GGML_UNUSED(scales_local); + }); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; case GGML_TYPE_Q8_0: + if (src0_reordered) { + get_rows_sycl_reorder(dst->src[0], dst->src[1], dst, dst->src[0]->data, + src1_i32, (float *)dst->data, ctx.stream()); + break; + } get_rows_sycl(ctx, dst->src[0], dst->src[1], dst, (const float *)dst->src[0]->data, src1_i32, (float *)dst->data, ctx.stream()); break; @@ -468,6 +718,5 @@ void ggml_sycl_op_get_rows_back(ggml_backend_sycl_context & ctx, ggml_tensor * d break; default: GGML_ABORT("%s: unsupported src0 type: %s\n", __func__, ggml_type_name(src0->type)); - break; } } diff --git a/ggml/src/ggml-sycl/ggml-sycl.cpp b/ggml/src/ggml-sycl/ggml-sycl.cpp index 97ff4d8a6d84..3f76c205132d 100644 --- a/ggml/src/ggml-sycl/ggml-sycl.cpp +++ b/ggml/src/ggml-sycl/ggml-sycl.cpp @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -46,8 +47,12 @@ # include # define GGML_SYCL_SUPPORT_VMM #endif -#if defined(__INTEL_LLVM_COMPILER) - #define GGML_SYCL_DMMV_HAS_ESIMD +// beginning in oneDNN 3.12.3, "Enabled matmul and inner product primitives compatibility with SYCL Graph native recording mode on Intel GPUs." +#if GGML_SYCL_DNNL +# include "dnnl_version.h" +# if (DNNL_VERSION_MAJOR > 3 || (DNNL_VERSION_MAJOR == 3 && (DNNL_VERSION_MINOR > 12 || (DNNL_VERSION_MINOR == 12 && DNNL_VERSION_PATCH >= 3)))) +# define GGML_SYCL_GRAPH_DNNL_SUPPORTED +# endif #endif #include @@ -100,12 +105,16 @@ int g_ggml_sycl_enable_dnn = 1; int g_ggml_sycl_fa_onednn = 1; int g_ggml_sycl_fa_onednn_max_kv = 0; int g_ggml_sycl_enable_mkl_fa = 1; +int g_ggml_sycl_fa_dpas = 1; int g_ggml_sycl_memtrace = 0; int g_ggml_sycl_memtrace_step = 64; int g_ggml_sycl_enable_vmm = 1; int g_ggml_sycl_enable_fusion = 1; int g_ggml_sycl_enable_esimd = 1; int g_ggml_sycl_mmvq_wide = 1; +int g_ggml_sycl_enable_xmx_esimd = 1; +int g_ggml_sycl_xmx_max_cols = GGML_SYCL_XMX_MAX_COLS_DEFAULT; +int g_ggml_sycl_xmx_glu_max_cols = GGML_SYCL_XMX_GLU_MAX_COLS; int g_ggml_sycl_prioritize_dmmv = 0; int g_ggml_sycl_xmx_gather_types = GGML_SYCL_XMX_GATHER_TYPES_DEFAULT; int g_ggml_sycl_xmx_gather_shapes = GGML_SYCL_XMX_GATHER_SHAPES_DEFAULT; @@ -144,6 +153,7 @@ int g_ggml_sycl_get_mem_api = MEMORY_API_TYPE_LEVEL_ZERO; int g_ggml_sycl_enable_sparse_fa = 0; int g_ggml_sycl_debug_sparse_fa = 0; int g_ggml_sycl_sparse_fa_margin = 256; +int g_ggml_sycl_graph_eviction_timeout = 10; #if GGML_SYCL_DNNL // ask oneDNN which matmul it picks for a small f16 problem @@ -201,10 +211,10 @@ static ggml_sycl_device_info ggml_sycl_init() { int64_t total_vram = 0; /* This is a bit misleading; reserved for later */ -// #if defined(SYCL_USE_XMX) -// GGML_LOG_INFO("%s: SYCL_USE_XMX: yes\n", __func__); +// #if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) +// GGML_LOG_INFO("%s: GGML_SYCL_SUPPORT_XMX: yes\n", __func__); // #else -// GGML_LOG_INFO("%s: SYCL_USE_XMX: no\n", __func__); +// GGML_LOG_INFO("%s: GGML_SYCL_SUPPORT_XMX: no\n", __func__); // #endif for (int i = 0; i < info.device_count; ++i) { dpct::device_info prop; @@ -245,6 +255,11 @@ static ggml_sycl_device_info ggml_sycl_init() { info.devices[i].warp_size = WARP_SIZE; info.devices[i].usm_system_support = device.has(sycl::aspect::usm_system_allocations); +#ifdef GGML_SYCL_GRAPH + info.devices[i].graph_support = device.has(sycl::aspect::ext_oneapi_limited_graph); + info.devices[i].graph_update_support = device.has(sycl::aspect::ext_oneapi_graph); +#endif + info.max_work_group_sizes[i] = prop.get_max_work_group_size(); info.devices[i].max_wg_per_cu = info.max_work_group_sizes[i] / prop.get_max_compute_units(); info.devices[i].hw_info = get_device_hw_info(&device); @@ -283,7 +298,7 @@ static ggml_sycl_device_info ggml_sycl_init() { return info; } -const ggml_sycl_device_info & ggml_sycl_info() { +ggml_sycl_device_info & ggml_sycl_info() { static ggml_sycl_device_info info = ggml_sycl_init(); return info; } @@ -391,14 +406,14 @@ static ze_result_t init_zes() { return res; } -ze_result_t get_zes_init_res() { +static ze_result_t get_zes_init_res() { static ze_result_t zes_init_res = init_zes(); GGML_SYCL_DEBUG("[SYCL] call %s: zesInit result: %d\n", __func__, (int) zes_init_res); return zes_init_res; } #endif -void initialize_sycl_begining() { +static void initialize_sycl_begining() { #ifdef GGML_SYCL_SUPPORT_LEVEL_ZERO_API //must be called in initialization stage, before any other Level Zero API calls GGML_SYCL_DEBUG("[SYCL] call %s\n", __func__); @@ -421,13 +436,19 @@ static void ggml_check_sycl() try { g_ggml_sycl_fa_onednn = ggml_sycl_get_env("GGML_SYCL_FA_ONEDNN", 1); g_ggml_sycl_fa_onednn_max_kv = ggml_sycl_get_env("GGML_SYCL_FA_ONEDNN_MAX_KV", 0); g_ggml_sycl_enable_mkl_fa = ggml_sycl_get_env("GGML_SYCL_ENABLE_MKL_FA", 1); + g_ggml_sycl_fa_dpas = ggml_sycl_get_env("GGML_SYCL_FA_DPAS", 1); g_ggml_sycl_memtrace = ggml_sycl_get_env("GGML_SYCL_MEMTRACE", 0); g_ggml_sycl_memtrace_step = ggml_sycl_get_env("GGML_SYCL_MEMTRACE_STEP", 64); g_ggml_sycl_enable_vmm = ggml_sycl_get_env("GGML_SYCL_ENABLE_VMM", 1); g_ggml_sycl_enable_fusion = ggml_sycl_get_env("GGML_SYCL_ENABLE_FUSION", 1); g_ggml_sycl_enable_esimd = ggml_sycl_get_env("GGML_SYCL_ENABLE_ESIMD", 1); g_ggml_sycl_mmvq_wide = ggml_sycl_get_env("GGML_SYCL_MMVQ_WIDE", 1); + g_ggml_sycl_enable_xmx_esimd = ggml_sycl_get_env("GGML_SYCL_ENABLE_XMX_ESIMD", 1); + g_ggml_sycl_xmx_max_cols = std::max(0, ggml_sycl_get_env("GGML_SYCL_XMX_MAX_COLS", GGML_SYCL_XMX_MAX_COLS_DEFAULT)); + g_ggml_sycl_xmx_glu_max_cols = + std::clamp(ggml_sycl_get_env("GGML_SYCL_XMX_GLU_MAX_COLS", GGML_SYCL_XMX_GLU_MAX_COLS), 0, GGML_SYCL_XMX_GLU_MAX_COLS); g_ggml_sycl_prioritize_dmmv = ggml_sycl_get_env("GGML_SYCL_PRIORITIZE_DMMV", 0); + g_ggml_sycl_graph_eviction_timeout = ggml_sycl_get_env("GGML_SYCL_GRAPH_EVICTION_TIMEOUT", 10); g_ggml_sycl_xmx_gather_types = ggml_sycl_get_env("GGML_SYCL_XMX_GATHER_TYPES", GGML_SYCL_XMX_GATHER_TYPES_DEFAULT); g_ggml_sycl_xmx_gather_shapes = ggml_sycl_get_env("GGML_SYCL_XMX_GATHER_SHAPES", GGML_SYCL_XMX_GATHER_SHAPES_DEFAULT); g_ggml_sycl_dynamic_precision = @@ -486,6 +507,12 @@ static void ggml_check_sycl() try { GGML_LOG_INFO(" GGML_SYCL_FORCE_MMQ: no\n"); #endif +#if defined(GGML_SYCL_SUPPORT_XMX) + GGML_LOG_INFO(" GGML_SYCL_SUPPORT_XMX: yes\n"); +#else + GGML_LOG_INFO(" GGML_SYCL_SUPPORT_XMX: no\n"); +#endif + #if defined(GGML_SYCL_GRAPH) GGML_LOG_INFO(" GGML_SYCL_GRAPH: yes\n"); #else @@ -527,6 +554,7 @@ static void ggml_check_sycl() try { #endif GGML_LOG_INFO(" GGML_SYCL_FA_ONEDNN_MAX_KV: %d\n", g_ggml_sycl_fa_onednn_max_kv); GGML_LOG_INFO(" GGML_SYCL_ENABLE_MKL_FA: %d\n", g_ggml_sycl_enable_mkl_fa); + GGML_LOG_INFO(" GGML_SYCL_FA_DPAS: %d\n", g_ggml_sycl_fa_dpas); GGML_LOG_INFO(" GGML_SYCL_MEMTRACE: %d\n", g_ggml_sycl_memtrace); GGML_LOG_INFO(" GGML_SYCL_MEMTRACE_STEP: %d\n", g_ggml_sycl_memtrace_step); #ifdef SYCL_FLASH_ATTN @@ -538,6 +566,7 @@ static void ggml_check_sycl() try { #ifdef GGML_SYCL_GRAPH GGML_LOG_INFO(" GGML_SYCL_ENABLE_GRAPH: %d\n", g_ggml_sycl_enable_graph); + GGML_LOG_INFO(" GGML_SYCL_GRAPH_EVICTION_TIMEOUT: %d\n", g_ggml_sycl_graph_eviction_timeout); #else GGML_LOG_INFO(" GGML_SYCL_ENABLE_GRAPH: graph disabled by compile flag\n"); #endif @@ -564,7 +593,13 @@ static void ggml_check_sycl() try { #else GGML_LOG_INFO(" GGML_SYCL_ENABLE_ESIMD: %d disabled by compile flag\n", g_ggml_sycl_enable_esimd); #endif + GGML_LOG_INFO(" GGML_SYCL_MMVQ_WIDE: %d\n", g_ggml_sycl_mmvq_wide); + + GGML_LOG_INFO(" GGML_SYCL_ENABLE_XMX_ESIMD: %d\n", g_ggml_sycl_enable_xmx_esimd); + GGML_LOG_INFO(" GGML_SYCL_XMX_MAX_COLS: %d\n", g_ggml_sycl_xmx_max_cols); + GGML_LOG_INFO(" GGML_SYCL_XMX_GLU_MAX_COLS: %d\n", g_ggml_sycl_xmx_glu_max_cols); + GGML_LOG_INFO(" GGML_SYCL_PRIORITIZE_DMMV: %d\n", g_ggml_sycl_prioritize_dmmv); g_ggml_sycl_use_async_mem_op_requested = ggml_sycl_get_env("GGML_SYCL_USE_ASYNC_MEM_OP", 1); @@ -585,16 +620,25 @@ static void ggml_check_sycl() try { GGML_LOG_INFO(" GGML_SYCL_SPARSE_FA_MARGIN: %d\n", g_ggml_sycl_sparse_fa_margin); /* NOT REMOVE, keep it for next optimize for XMX. -#if defined(SYCL_USE_XMX) - fprintf(stderr, "%s: SYCL_USE_XMX: yes\n", __func__); +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) + fprintf(stderr, "%s: GGML_SYCL_SUPPORT_XMX: yes\n", __func__); #else - fprintf(stderr, "%s: SYCL_USE_XMX: no\n", __func__); + fprintf(stderr, "%s: GGML_SYCL_SUPPORT_XMX: no\n", __func__); #endif */ +#ifdef GGML_SYCL_GRAPH + if (g_ggml_sycl_enable_graph) { + for (unsigned int i = 0; i < dpct::dev_mgr::instance().device_count(); ++i) { + if (!dpct::dev_mgr::instance().get_device(i).has(sycl::aspect::ext_oneapi_limited_graph)) { + GGML_LOG_WARN("SYCL device %u does not support SYCL graphs\n", i); + } + } + } + // Async USM allocation/free is also useful outside the graph path: it avoids the host waits in the reorder // staging path while preserving queue ordering semantics. Graph support still depends on the extension being // available, but it no longer needs to control the non-graph fast path. -#if defined(GGML_SYCL_GRAPH) && SYCL_EXT_ONEAPI_ASYNC_MEMORY_ALLOC +#if SYCL_EXT_ONEAPI_ASYNC_MEMORY_ALLOC g_ggml_sycl_use_async_mem_op = g_ggml_sycl_use_async_mem_op_requested || g_ggml_sycl_enable_graph; if (g_ggml_sycl_use_async_mem_op) { for (unsigned int i = 0; i < dpct::dev_mgr::instance().device_count(); ++i) { @@ -604,6 +648,7 @@ static void ggml_check_sycl() try { } } } +#endif #endif if (CHECK_TRY_ERROR(g_all_sycl_device_count = dpct::dev_mgr::instance().device_count()) != 0) { @@ -806,6 +851,19 @@ catch (sycl::exception const &exc) { std::exit(1); } +// allocates the pinned upload staging on first use; returns false if staging is disabled or the allocation failed +static bool ggml_sycl_buffer_init_staging(ggml_backend_sycl_buffer_context * ctx) { + const int n_slots = g_ggml_sycl_upload_staging_slots; + if (n_slots > 0 && ctx->staging.data == nullptr) { + ctx->staging.data = sycl::malloc_host(n_slots * ctx->staging_slot_size, *ctx->stream); + if (ctx->staging.data != nullptr) { + ctx->staging.events.resize(n_slots); + ctx->staging.submitted.assign(n_slots, false); + } + } + return ctx->staging.data != nullptr; +} + static void ggml_backend_sycl_buffer_set_tensor(ggml_backend_buffer_t buffer, ggml_tensor *tensor, const void *data, size_t offset, @@ -818,15 +876,7 @@ static void ggml_backend_sycl_buffer_set_tensor(ggml_backend_buffer_t buffer, // copy through pinned memory so the device never reads mmap()ed pages directly // chunks pipeline on the in-order compute queue, so no drain per tensor is needed - const int n_slots = g_ggml_sycl_upload_staging_slots; - if (n_slots > 0 && ctx->staging.data == nullptr) { - ctx->staging.data = sycl::malloc_host(n_slots * ctx->staging_slot_size, *ctx->stream); - if (ctx->staging.data != nullptr) { - ctx->staging.events.resize(n_slots); - ctx->staging.submitted.assign(n_slots, false); - } - } - if (ctx->staging.data != nullptr) { + if (ggml_sycl_buffer_init_staging(ctx)) { queue_ptr stream = ctx->stream; char * dst = (char *) tensor->data + offset; const char * src = (const char *) data; @@ -868,6 +918,49 @@ catch (sycl::exception const &exc) { std::exit(1); } +// Copy n_copies rows in one call. -sm tensor uploads split weights this way; the generic fallback does one set_tensor per row. +static void ggml_backend_sycl_buffer_set_tensor_2d(ggml_backend_buffer_t buffer, ggml_tensor * tensor, + const void * data, size_t offset, size_t size, + size_t n_copies, size_t stride_tensor, + size_t stride_data) try { + ggml_backend_sycl_buffer_context * ctx = (ggml_backend_sycl_buffer_context *) buffer->context; + const char * src = (const char *) data; + ggml_sycl_set_device(ctx->device); + + if (stride_tensor != size || size > ctx->staging_slot_size || !ggml_sycl_buffer_init_staging(ctx)) { + // dst rows not contiguous, row larger than a staging slot, or no staging: same as the generic fallback + for (size_t i = 0; i < n_copies; ++i) { + ggml_backend_sycl_buffer_set_tensor(buffer, tensor, src + i * stride_data, offset + i * stride_tensor, size); + } + return; + } + + // dst rows are contiguous: pack as many rows as fit into a staging slot and copy each slot with one memcpy + // a slot is only waited on when it is reused, so packing the next slot overlaps with the previous copies + queue_ptr stream = ctx->stream; + char * dst = (char *) tensor->data + offset; + const size_t rows_per_slot = ctx->staging_slot_size / size; + for (size_t i0 = 0; i0 < n_copies; i0 += rows_per_slot) { + const size_t n = std::min(rows_per_slot, n_copies - i0); + const int slot = ctx->staging.next; + ctx->staging.next = (ctx->staging.next + 1) % (int) ctx->staging.submitted.size(); + if (ctx->staging.submitted[slot]) { + ctx->staging.events[slot].wait_and_throw(); + } + char * stage = (char *) ctx->staging.data + slot * ctx->staging_slot_size; + for (size_t i = 0; i < n; ++i) { + memcpy(stage + i * size, src + (i0 + i) * stride_data, size); + } + ctx->staging.events[slot] = stream->memcpy(dst + i0 * size, stage, n * size); + ctx->staging.submitted[slot] = true; + } +} +catch (sycl::exception const &exc) { + std::cerr << exc.what() << "Exception caught at file:" << __FILE__ + << ", line:" << __LINE__ << std::endl; + std::exit(1); +} + static void ggml_backend_sycl_buffer_get_tensor(ggml_backend_buffer_t buffer, const ggml_tensor *tensor, void *data, size_t offset, @@ -899,6 +992,10 @@ static bool ggml_sycl_is_l0_discrete_gpu(int device) { static void memcpy_host_forward(sycl::queue &q_dst, sycl::queue &q_src, void *ptr_dst, const void *ptr_src, size_t size) { char *host_buf = (char *)malloc(size); + if (host_buf == nullptr) { + GGML_LOG_ERROR("%s: can't allocate %zu Bytes of memory for host staging\n", __func__, size); + GGML_ABORT("fatal error"); + } q_src.memcpy(host_buf, (const char *)ptr_src, size).wait(); q_dst.memcpy((char *)ptr_dst, host_buf, size).wait(); free(host_buf); @@ -1082,11 +1179,14 @@ static const ggml_backend_buffer_i ggml_backend_sycl_buffer_interface = { /* .memset_tensor = */ ggml_backend_sycl_buffer_memset_tensor, /* .set_tensor = */ ggml_backend_sycl_buffer_set_tensor, /* .get_tensor = */ ggml_backend_sycl_buffer_get_tensor, - /* .set_tensor_2d = */ NULL, + /* .set_tensor_2d = */ ggml_backend_sycl_buffer_set_tensor_2d, /* .get_tensor_2d = */ NULL, /* .cpy_tensor = */ ggml_backend_sycl_buffer_cpy_tensor, /* .clear = */ ggml_backend_sycl_buffer_clear, /* .reset = */ ggml_backend_sycl_buffer_reset, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; // sycl buffer type @@ -1172,17 +1272,18 @@ static size_t ggml_backend_sycl_buffer_type_get_alignment(ggml_backend_buffer_ty GGML_UNUSED(buft); } -bool is_bmg_g31_arch(int device) { +static bool is_bmg_g31_arch(int device) { return ggml_sycl_info().devices[device].hw_info.arch == gpu_arch::intel_gpu_bmg_g31; } static size_t ggml_backend_sycl_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) { - size_t max_alloc_size = dpct::get_current_device().get_max_mem_alloc_size(); + ggml_backend_sycl_buffer_type_context * ctx = (ggml_backend_sycl_buffer_type_context *)buft->context; + int device = ctx->device; + // use the buft device, the current device may differ on multi-GPU systems + size_t max_alloc_size = dpct::get_device(device).get_max_mem_alloc_size(); if (g_ggml_sycl_host_pinned_mem_2g) { return std::min(max_alloc_size, (size_t) 2LL*1024*1024*1024); } else { - ggml_backend_sycl_buffer_type_context * ctx = (ggml_backend_sycl_buffer_type_context *)buft->context; - int device = ctx->device; if(is_bmg_g31_arch(device)) { //Todo, it's workaround for BMG-G31, which has a known issue with large allocations. //The max alloc size is reduced to 60% of the reported max alloc size. @@ -1398,7 +1499,12 @@ ggml_backend_sycl_split_buffer_init_tensor(ggml_backend_buffer_t buffer, ggml_tensor_extra_gpu * extra = new ggml_tensor_extra_gpu{}; ctx->tensor_extras.push_back(extra); - ctx->streams.push_back(&(dpct::get_current_device().default_queue())); + // consumers index the queues by device id, so size the vector once with one queue per device + if (ctx->streams.empty()) { + for (int i = 0; i < ggml_sycl_info().device_count; ++i) { + ctx->streams.push_back(&(dpct::get_device(i).default_queue())); + } + } for (int i = 0; i < ggml_sycl_info().device_count; ++i) { int64_t row_low, row_high; @@ -1589,6 +1695,9 @@ static struct ggml_backend_buffer_i ggml_backend_sycl_split_buffer_interface = { /* .cpy_tensor = */ NULL, /* .clear = */ ggml_backend_sycl_split_buffer_clear, /* .reset = */ NULL, + /* .set_tensor_n = */ NULL, + /* .get_tensor_n = */ NULL, + /* .cpy_tensor_n = */ NULL, }; // sycl split buffer type @@ -2089,8 +2198,6 @@ struct ggml_sycl_pool_host : public ggml_sycl_pool { queue_ptr qptr; int device; - inline static int counter{ 0 }; - struct ggml_sycl_buffer { void * ptr = nullptr; size_t size = 0; @@ -2100,6 +2207,7 @@ struct ggml_sycl_pool_host : public ggml_sycl_pool { static constexpr int MAX_POOL_SIZE{ 64 }; std::vector buffer_pool = std::vector(MAX_POOL_SIZE); size_t pool_size = 0; + int counter = 0; explicit ggml_sycl_pool_host(queue_ptr qptr_, int device_) : qptr(qptr_), device(device_) {} @@ -2113,41 +2221,55 @@ struct ggml_sycl_pool_host : public ggml_sycl_pool { b.size = 0; } } - counter = 0; } void * alloc(size_t size, size_t * actual_size) override { if (counter == MAX_POOL_SIZE) { - ggml_sycl_buffer b = buffer_pool[0]; - void * ptr = b.ptr; - *actual_size = b.size; - counter = 1; - return ptr; - } - ggml_sycl_buffer & b = buffer_pool[counter]; - - if (b.ptr == nullptr) { - void * ptr; - + // the pool wrapped around, no slot is reserved for this allocation + void * ptr = nullptr; SYCL_CHECK(CHECK_TRY_ERROR(ptr = (void *) sycl::malloc_host(size, *qptr))); if (!ptr) { GGML_LOG_ERROR("%s: can't allocate %zu Bytes of memory on host\n", __func__, size); return nullptr; } - pool_size += size; + pool_size += size; *actual_size = size; - counter = counter + 1; + counter = 0; return ptr; - } else { - ++counter; - b.size = size; - return b.ptr; } + ggml_sycl_buffer & b = buffer_pool[counter]; + ++counter; + + if (b.ptr != nullptr) { + if (b.size >= size) { + // hand out the cached buffer, free() puts it back into the pool + void * ptr = b.ptr; + *actual_size = b.size; + b.ptr = nullptr; + b.size = 0; + return ptr; + } + // the cached buffer is too small, replace it + SYCL_CHECK(CHECK_TRY_ERROR(sycl::free(b.ptr, *qptr))); + pool_size -= b.size; + b.ptr = nullptr; + b.size = 0; + } + + void * ptr; + SYCL_CHECK(CHECK_TRY_ERROR(ptr = (void *) sycl::malloc_host(size, *qptr))); + if (!ptr) { + GGML_LOG_ERROR("%s: can't allocate %zu Bytes of memory on host\n", __func__, size); + return nullptr; + } + pool_size += size; + *actual_size = size; + return ptr; } void free(void * ptr, size_t size) override { // if the pool is not completed add the pointer to it in place of the first nullptr found. - // Otherwise do nothing, pointers will be freed once the pool is deallocated. + // Otherwise free the buffer, all slots are cached. for (int i = 0; i < MAX_POOL_SIZE; ++i) { ggml_sycl_buffer & b = buffer_pool[i]; if (b.ptr == nullptr) { @@ -2156,6 +2278,8 @@ struct ggml_sycl_pool_host : public ggml_sycl_pool { return; } } + SYCL_CHECK(CHECK_TRY_ERROR(sycl::free(ptr, *qptr))); + pool_size -= size; } }; @@ -2901,6 +3025,35 @@ static void top_k_f32_sycl( return; } + // Short rows: one work-item per column and k work-group argmax rounds. + // Ties take the lower column. + const int wg = std::max(WARP_SIZE, next_power_of_2((int) ncols)); + if (wg <= ggml_sycl_info().max_work_group_sizes[ctx.device]) { + main_stream->parallel_for( + sycl::nd_range<1>(sycl::range<1>(nrows * wg), sycl::range<1>(wg)), + [=](sycl::nd_item<1> item_ct1) { + const int64_t row = item_ct1.get_group(0); + const int tid = item_ct1.get_local_id(0); + const auto grp = item_ct1.get_group(); + + // NaN is never preferred, and every round still has a winner since k <= ncols + const float x = tid < ncols ? src[row * ncols + tid] : -INFINITY; + const float val = sycl::isnan(x) ? -INFINITY : x; + bool taken = tid >= ncols; + for (int i = 0; i < k; i++) { + const float cand = taken ? -INFINITY : val; + const float best = sycl::reduce_over_group(grp, cand, sycl::maximum()); + const int winner = sycl::reduce_over_group(grp, !taken && cand == best ? tid : INT_MAX, + sycl::minimum()); + if (tid == winner) { + dst_indices[row * k + i] = tid; + taken = true; + } + } + }); + return; + } + const int block_size = 128; const sycl::range<1> block_dims(block_size); @@ -3073,6 +3226,11 @@ catch (sycl::exception const &exc) { std::exit(1); } +#if GGML_SYCL_DNNL +// F32 GEMMs below this size (row_diff * src1_ncols * ne10) call oneMKL directly instead of oneDNN +static constexpr int64_t SYCL_F32_DNNL_MIN_GEMM_FLOPS = 256 * 256 * 256; +#endif + inline void ggml_sycl_op_mul_mat_sycl( ggml_backend_sycl_context & ctx, const ggml_tensor *src0, const ggml_tensor *src1, ggml_tensor *dst, @@ -3132,9 +3290,16 @@ inline void ggml_sycl_op_mul_mat_sycl( #endif // dequantize inside the GEMM instead of writing the f16 weights out and reading them back; src1 - // goes in its own type, so there is no separate conversion pass + // goes in its own type, so there is no separate conversion pass. The A stage + // decodes the weight bytes in place, so an installed persistent reorder must be + // visible to it: pass the flag through; types without an SoA A-stage decline + // inside and this falls through to the reorder-aware conversion route below. + bool src0_reordered = false; + if (const auto * src0_extra = static_cast(src0->extra)) { + src0_reordered = src0_extra->optimized_feature.reorder; + } if (ggml_is_quantized(src0->type) && ggml_is_contiguous(src0) && row_diff == src0->ne[1] && - ggml_sycl_fused_dequant_gemm(src0->type, src0_dd_i, src1_ddf_i, src1->type, ggml_sycl_src1_prec(dst), dst_dd_i, + ggml_sycl_fused_dequant_gemm(src0->type, src0_reordered, src0_dd_i, src1_ddf_i, src1->type, ggml_sycl_src1_prec(dst), dst_dd_i, row_diff, src1_ncols, ne10, ldc, ctx.pool(), stream)) { return; } @@ -3154,8 +3319,8 @@ inline void ggml_sycl_op_mul_mat_sycl( to_fp16_sycl(src1_ddf_i, src1_as_f16.get(), ne, stream); } const sycl::half *src1_ptr = src1->type == GGML_TYPE_F16 - ? (const sycl::half *)src1->data + src1_padded_row_size - : src1_as_f16.get(); + ? (const sycl::half *)src1_ddf_i + : src1_as_f16.get(); ggml_sycl_pool_alloc src0_as_f16(ctx.pool()); if (src0->type != GGML_TYPE_F16) { @@ -3215,7 +3380,7 @@ inline void ggml_sycl_op_mul_mat_sycl( { #if GGML_SYCL_DNNL const int64_t gemm_flops = (int64_t)row_diff * src1_ncols * ne10; - const bool use_mkl_direct = gemm_flops < 256 * 256 * 256; + const bool use_mkl_direct = gemm_flops < SYCL_F32_DNNL_MIN_GEMM_FLOPS; if (g_ggml_sycl_enable_dnn && !use_mkl_direct && ggml_sycl_dnnl_has_optimized_gemm(ggml_sycl_get_device())) { DnnlGemmWrapper::row_gemm(ctx, row_diff, src1_ncols, ne10, src0_ddf_i, DnnlGemmWrapper::to_dt(), src1_ddf1_i, DnnlGemmWrapper::to_dt(), @@ -3252,6 +3417,8 @@ inline void ggml_sycl_op_sum(ggml_backend_sycl_context & ctx, ggml_tensor *dst) float * dst_dd = static_cast(dst->data); const int64_t ne = ggml_nelements(dst->src[0]); + // the kernel indexes in 32-bit + GGML_ASSERT(ne <= INT32_MAX); sum_rows_f32_sycl(src0_dd, dst_dd, ne, 1, main_stream); } @@ -3266,6 +3433,8 @@ inline void ggml_sycl_op_sum_rows(ggml_backend_sycl_context & ctx, ggml_tensor * const int64_t ncols = dst->src[0]->ne[0]; const int64_t nrows = ggml_nrows(dst->src[0]); + // the kernel indexes in 32-bit + GGML_ASSERT(ncols * nrows <= INT32_MAX); sum_rows_f32_sycl(src0_dd, dst_dd, ncols, nrows, main_stream); } @@ -3282,6 +3451,8 @@ inline void ggml_sycl_op_mean(ggml_backend_sycl_context & ctx, ggml_tensor * dst const int64_t ncols = dst->src[0]->ne[0]; const int64_t nrows = ggml_nrows(dst->src[0]); + // the kernel indexes in 32-bit + GGML_ASSERT(ncols * nrows <= INT32_MAX); sum_rows_f32_sycl(src0_dd, dst_dd, ncols, nrows, main_stream); @@ -3351,6 +3522,8 @@ inline void ggml_sycl_op_argmax(ggml_backend_sycl_context & ctx, ggml_tensor * d const int64_t ncols = dst->src[0]->ne[0]; const int64_t nrows = ggml_nrows(dst->src[0]); + // the kernel indexes in 32-bit + GGML_ASSERT(ncols * nrows <= INT32_MAX); argmax_f32_i32_sycl(src0_dd, dst_dd, ncols, nrows, main_stream); } @@ -3366,6 +3539,8 @@ inline void ggml_sycl_op_diag_mask_inf(ggml_backend_sycl_context & ctx, ggml_ten const int64_t ne00 = dst->src[0]->ne[0]; const int64_t ne01 = dst->src[0]->ne[1]; const int nrows0 = ggml_nrows(dst->src[0]); + // the kernel indexes in 32-bit + GGML_ASSERT(ne00 * nrows0 <= INT32_MAX); const int n_past = ((int32_t *) dst->op_params)[0]; @@ -3444,6 +3619,9 @@ inline void ggml_sycl_op_scale(ggml_backend_sycl_context & ctx, ggml_tensor * ds memcpy(&scale, (float *) dst->op_params + 0, sizeof(float)); memcpy(&bias, (float *) dst->op_params + 1, sizeof(float)); + // the kernel indexes in 32-bit + GGML_ASSERT(ggml_nelements(dst->src[0]) <= INT32_MAX); + scale_f32_sycl(src0_dd, dst_dd, scale, bias, ggml_nelements(dst->src[0]), main_stream); /* DPCT1010:87: SYCL uses exceptions to report errors and does not use the @@ -3524,7 +3702,6 @@ static void ggml_sycl_op_mul_mat(ggml_backend_sycl_context & ctx, const ggml_ten const size_t q8_1_bs = QK8_1; ggml_tensor_extra_gpu * src0_extra = (ggml_tensor_extra_gpu *) src0->extra; - ggml_tensor_extra_gpu * src1_extra = (ggml_tensor_extra_gpu *) src1->extra; const bool src0_is_contiguous = ggml_is_contiguous(src0); const bool src1_is_contiguous = ggml_is_contiguous(src1); @@ -3606,7 +3783,8 @@ static void ggml_sycl_op_mul_mat(ggml_backend_sycl_context & ctx, const ggml_ten queue_ptr stream = ctx.stream(i, 0); if (src0_is_contiguous) { - dev[i].src0_dd = (char *) src0->data; + // a split tensor keeps its rows in the per-device slices of the tensor extra + dev[i].src0_dd = split ? (char *) src0_extra->data_device[i] : (char *) src0->data; } else { dev[i].src0_dd = dev[i].src0_dd_alloc.alloc(ctx.pool(i), ggml_nbytes(src0)); } @@ -3702,7 +3880,8 @@ static void ggml_sycl_op_mul_mat(ggml_backend_sycl_context & ctx, const ggml_ten src1_ncols * src1_padded_col_size * q8_1_ts / q8_1_bs) .wait())); } else { - const char * src1_ddf_i_source = (const char *) src1_extra->data_device[ctx.device] + + // src1 is not split, on the main device it lives at dev[ctx.device].src1_ddf + const char * src1_ddf_i_source = (const char *) dev[ctx.device].src1_ddf + (i0 * ne11 + src1_col_0) * ne10 * ggml_type_size(src1->type); SYCL_CHECK( @@ -4292,12 +4471,50 @@ static bool ggml_sycl_supports_dmmv(enum ggml_type type) { } } +static bool ggml_sycl_supports_mmvq_id(enum ggml_type type) { + switch (type) { + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: + case GGML_TYPE_Q8_0: + case GGML_TYPE_Q2_0: + case GGML_TYPE_Q2_K: + case GGML_TYPE_Q3_K: + case GGML_TYPE_Q4_K: + case GGML_TYPE_Q5_K: + case GGML_TYPE_Q6_K: + case GGML_TYPE_MXFP4: + case GGML_TYPE_NVFP4: + case GGML_TYPE_IQ2_XXS: + case GGML_TYPE_IQ2_XS: + case GGML_TYPE_IQ2_S: + case GGML_TYPE_IQ3_XXS: + case GGML_TYPE_IQ3_S: + case GGML_TYPE_IQ1_S: + case GGML_TYPE_IQ1_M: + case GGML_TYPE_IQ4_NL: + case GGML_TYPE_IQ4_XS: + return true; + default: + return false; + } +} + // Helper functions to unify device memory allocation for both async and sync paths static inline void * sycl_ext_malloc_device(dpct::queue_ptr stream, size_t size) { bool use_async = g_ggml_sycl_use_async_mem_op; #if defined(GGML_SYCL_GRAPH) && SYCL_EXT_ONEAPI_ASYNC_MEMORY_ALLOC if (use_async) { - void * ptr = syclex::async_malloc(*stream, sycl::usm::alloc::device, size); + // async_malloc throws on out-of-memory; return nullptr like the sync path so callers can fall back. + void * ptr = nullptr; + try { + ptr = syclex::async_malloc(*stream, sycl::usm::alloc::device, size); + } catch (const sycl::exception & e) { + GGML_LOG_WARN("%s: async_malloc of %zu bytes failed: %s\n", __func__, size, e.what()); + ggml_sycl_memtrace_fail(GGML_SYCL_MEM_ASYNC, size); + return nullptr; + } ggml_sycl_memtrace_add(GGML_SYCL_MEM_ASYNC, ptr, size); return ptr; } @@ -4364,266 +4581,317 @@ struct sycl_reorder_temp_buffer { bool host_fallback = false; }; -static bool reorder_qw_q4_0(uint8_t * data_device, const int ncols, const int nrows, size_t size, size_t offset, - dpct::queue_ptr stream) { - sycl_reorder_temp_buffer tmp(stream, size); +// Reorder a 2D tensor of quantized blocks in place into [head of every block][tail of every block] without a +// full-size temporary copy. The head is the contiguous `head_bytes` at `head_offset` inside each block. Heads only +// move towards the front, so they are packed in chunks that never overwrite unread blocks. The tail overlaps +// blocks that are not packed yet, so `write_tail(x, ib, tail, nblocks)` first writes every block's remaining fields +// (in their final layout, relative to the start of the tail) into a side buffer that is copied to the end afterwards. +template +static bool reorder_qw_planar(const char * name, uint8_t * data_device, size_t size, size_t head_offset, + size_t head_bytes, tail_fn_t write_tail, dpct::queue_ptr stream) { + GGML_ASSERT(size % sizeof(block_t) == 0); + GGML_ASSERT(head_offset + head_bytes <= sizeof(block_t)); + + const int64_t nblocks = size / sizeof(block_t); + const size_t tail_bytes = (sizeof(block_t) - head_bytes) * nblocks; + + sycl_reorder_temp_buffer tail_tmp(stream, tail_bytes); + if (!tail_tmp) { + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", name, tail_bytes); + return false; + } + uint8_t * tail_buf = static_cast(tail_tmp.ptr); + + const size_t max_chunk_bytes = 32u << 20; + const int64_t chunk_blocks = std::max(1, std::min(nblocks, max_chunk_bytes / sizeof(block_t))); + sycl_reorder_temp_buffer tmp(stream, chunk_blocks * sizeof(block_t)); if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", name, + (size_t) chunk_blocks * sizeof(block_t)); return false; } uint8_t * tmp_buf = static_cast(tmp.ptr); - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); + sycl::event event = stream->parallel_for(nblocks, [=](auto i) { + const int64_t ib = i; + write_tail(((const block_t *) data_device)[ib], ib, tail_buf, nblocks); + }); if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); + event.wait_and_throw(); } - GGML_ASSERT((size % sizeof(block_q4_0) == 0)); - GGML_ASSERT((offset % sizeof(block_q4_0) == 0)); - int offset_blks = offset / sizeof(block_q4_0); - auto qs_ptr = data_device + offset_blks * QK4_0 / 2; - auto d_ptr = (sycl::half*)(qs_ptr + ncols * nrows / 2) + offset_blks; + for (int64_t b0 = 0; b0 < nblocks; b0 += chunk_blocks) { + const int64_t n_chunk = std::min(chunk_blocks, nblocks - b0); - auto reorder_event = stream->parallel_for( - size / sizeof(block_q4_0), - [=](auto i) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - const block_q4_0* x = (const block_q4_0*)tmp_buf; - const int ib = i; + SYCL_CHECK(CHECK_TRY_ERROR(event = stream->memcpy(tmp_buf, data_device + b0 * sizeof(block_t), + n_chunk * sizeof(block_t)))); + if (!g_ggml_sycl_use_async_mem_op) { + event.wait(); + } - for (int j = 0; j < QK4_0/2; j ++) - { - *(qs_ptr + ib * QK4_0 / 2 + j) = x[ib].qs[j]; + uint8_t * head_ptr = data_device + b0 * head_bytes; + event = stream->parallel_for(n_chunk, [=](auto i) { + const int64_t ib = i; + const uint8_t * src = tmp_buf + ib * sizeof(block_t) + head_offset; + for (size_t j = 0; j < head_bytes; ++j) { + head_ptr[ib * head_bytes + j] = src[j]; } - *(d_ptr + ib) = x[ib].d; }); + if (!g_ggml_sycl_use_async_mem_op) { + event.wait_and_throw(); + } + } + + SYCL_CHECK(CHECK_TRY_ERROR(event = stream->memcpy(data_device + head_bytes * nblocks, tail_buf, tail_bytes))); if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); + event.wait(); } return true; } -static bool reorder_qw_q8_0(uint8_t * data_device, const int ncols, const int nrows, size_t size, size_t offset, +static bool reorder_qw_q4_0(uint8_t * data_device, const int ncols, const int nrows, size_t size, size_t offset, dpct::queue_ptr stream) { - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - GGML_ASSERT((size % sizeof(block_q8_0) == 0)); - GGML_ASSERT((offset % sizeof(block_q8_0) == 0)); - int offset_blks = offset / sizeof(block_q8_0); - auto qs_ptr = data_device + offset_blks * QK8_0; - auto d_ptr = (sycl::half*)(qs_ptr + ncols * nrows) + offset_blks; - - auto reorder_event = stream->parallel_for( - size / sizeof(block_q8_0), - [=](auto i) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - const block_q8_0* x = (const block_q8_0*)tmp_buf; - const int ib = i; + GGML_ASSERT(offset == 0); + GGML_ASSERT((size_t) ncols * nrows / 2 == size / sizeof(block_q4_0) * (QK4_0 / 2)); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q4_0, qs), QK4_0 / 2, + [](const block_q4_0 & x, int64_t ib, uint8_t * tail, int64_t) { + ((sycl::half *) tail)[ib] = x.d; + }, stream); +} - for (int j = 0; j < QK8_0; j++) - { - *((int8_t*)qs_ptr + ib * QK8_0 + j) = x[ib].qs[j]; - } - *(d_ptr + ib) = x[ib].d; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; +static bool reorder_qw_q8_0(uint8_t * data_device, const int ncols, const int nrows, size_t size, size_t offset, + dpct::queue_ptr stream) { + GGML_ASSERT(offset == 0); + GGML_ASSERT((size_t) ncols * nrows == size / sizeof(block_q8_0) * QK8_0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q8_0, qs), QK8_0, + [](const block_q8_0 & x, int64_t ib, uint8_t * tail, int64_t) { + ((sycl::half *) tail)[ib] = x.d; + }, stream); } static bool reorder_qw_q4_k(uint8_t * data_device, size_t size, size_t offset, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_q4_K) == 0); - GGML_ASSERT(offset % sizeof(block_q4_K) == 0); + GGML_ASSERT(offset == 0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q4_K, qs), QK_K / 2, + [](const block_q4_K & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * scales = tail; + for (int j = 0; j < K_SCALE_SIZE; ++j) { + scales[ib * K_SCALE_SIZE + j] = x.scales[j]; + } + ((sycl::half2 *) (scales + K_SCALE_SIZE * nblocks))[ib] = x.dm; + }, stream); +} - const int nblocks = size / sizeof(block_q4_K); +// Reorder each Q8_0 expert slice into a self-contained [qs][d] SoA layout, a few experts at a time. +static bool reorder_qw_q8_0_moe(uint8_t * data_device, size_t expert_bytes, int64_t n_expert, dpct::queue_ptr stream) { + GGML_ASSERT(expert_bytes % sizeof(block_q8_0) == 0); + const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q8_0)); + const size_t max_chunk_bytes = 32u << 20; + const int64_t chunk_experts = std::max(1, std::min(n_expert, (int64_t) (max_chunk_bytes / expert_bytes))); - sycl_reorder_temp_buffer tmp(stream, size); + sycl_reorder_temp_buffer tmp(stream, (size_t) chunk_experts * expert_bytes); if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, + (size_t) chunk_experts * expert_bytes); return false; } uint8_t * tmp_buf = static_cast(tmp.ptr); - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } + for (int64_t e0 = 0; e0 < n_expert; e0 += chunk_experts) { + const int64_t n_chunk = std::min(chunk_experts, n_expert - e0); + uint8_t * chunk = data_device + (size_t) e0 * expert_bytes; - auto * qs_ptr = data_device; - auto * scales_ptr = qs_ptr + QK_K / 2 * nblocks; - auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * nblocks); + sycl::event copy_event; + SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, chunk, (size_t) n_chunk * expert_bytes))); + if (!g_ggml_sycl_use_async_mem_op) { + copy_event.wait(); + } - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_q4_K * x = (const block_q4_K *) tmp_buf; - const int ib = i; + const int total_blocks = blocks_per_expert * (int) n_chunk; + auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { + const int gb = gb_; + const int e = gb / blocks_per_expert; + const int ib = gb % blocks_per_expert; + const block_q8_0 * x = (const block_q8_0 *) (tmp_buf + (size_t) e * expert_bytes); + uint8_t * base = chunk + (size_t) e * expert_bytes; - for (int j = 0; j < QK_K / 2; ++j) { - qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; - } + auto * qs_ptr = base; + auto * d_ptr = (sycl::half *) (qs_ptr + (size_t) blocks_per_expert * QK8_0); - for (int j = 0; j < K_SCALE_SIZE; ++j) { - scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; + for (int j = 0; j < QK8_0; ++j) { + *((int8_t *) qs_ptr + ib * QK8_0 + j) = x[ib].qs[j]; + } + d_ptr[ib] = x[ib].d; + }); + if (!g_ggml_sycl_use_async_mem_op) { + reorder_event.wait_and_throw(); } - - dm_ptr[ib] = x[ib].dm; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); } return true; } // Reorder each expert slice into a self-contained SoA layout. +// Like the MXFP4 version below, this goes a few experts at a time through a small temporary: +// a whole-tensor temporary (GBs for large MoE models) can exceed the VRAM left on a nearly full card. static bool reorder_qw_q4_k_moe(uint8_t * data_device, size_t expert_bytes, int64_t n_expert, dpct::queue_ptr stream) { GGML_ASSERT(expert_bytes % sizeof(block_q4_K) == 0); - const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q4_K)); - const size_t total_bytes = expert_bytes * (size_t) n_expert; + const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q4_K)); + const size_t max_chunk_bytes = 32u << 20; + const int64_t chunk_experts = std::max(1, std::min(n_expert, (int64_t) (max_chunk_bytes / expert_bytes))); - sycl_reorder_temp_buffer tmp(stream, total_bytes); + sycl_reorder_temp_buffer tmp(stream, (size_t) chunk_experts * expert_bytes); if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, total_bytes); + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, + (size_t) chunk_experts * expert_bytes); return false; } uint8_t * tmp_buf = static_cast(tmp.ptr); - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, total_bytes))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - const int total_blocks = blocks_per_expert * (int) n_expert; - auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { - const int gb = gb_; - const int e = gb / blocks_per_expert; - const int ib = gb % blocks_per_expert; - const block_q4_K * x = (const block_q4_K *) (tmp_buf + (size_t) e * expert_bytes); - uint8_t * base = data_device + (size_t) e * expert_bytes; - - auto * qs_ptr = base; - auto * scales_ptr = qs_ptr + QK_K / 2 * blocks_per_expert; - auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * blocks_per_expert); + // the queue is in-order: each chunk's copy into tmp_buf waits for the previous chunk's kernel + for (int64_t e0 = 0; e0 < n_expert; e0 += chunk_experts) { + const int64_t n_chunk = std::min(chunk_experts, n_expert - e0); + uint8_t * chunk = data_device + (size_t) e0 * expert_bytes; - for (int j = 0; j < QK_K / 2; ++j) { - qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; + sycl::event copy_event; + SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, chunk, (size_t) n_chunk * expert_bytes))); + if (!g_ggml_sycl_use_async_mem_op) { + copy_event.wait(); } - for (int j = 0; j < K_SCALE_SIZE; ++j) { - scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; + + const int total_blocks = blocks_per_expert * (int) n_chunk; + auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { + const int gb = gb_; + const int e = gb / blocks_per_expert; + const int ib = gb % blocks_per_expert; + const block_q4_K * x = (const block_q4_K *) (tmp_buf + (size_t) e * expert_bytes); + uint8_t * base = chunk + (size_t) e * expert_bytes; + + auto * qs_ptr = base; + auto * scales_ptr = qs_ptr + QK_K / 2 * blocks_per_expert; + auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * blocks_per_expert); + + for (int j = 0; j < QK_K / 2; ++j) { + qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; + } + for (int j = 0; j < K_SCALE_SIZE; ++j) { + scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; + } + dm_ptr[ib] = x[ib].dm; + }); + if (!g_ggml_sycl_use_async_mem_op) { + reorder_event.wait_and_throw(); } - dm_ptr[ib] = x[ib].dm; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); } return true; } -// Reorder each Q5_K expert slice into [qs][qh][scales][dm]. +// Reorder each Q5_K expert slice into [qs][qh][scales][dm], a few experts at a time (see Q4_K above). static bool reorder_qw_q5_k_moe(uint8_t * data_device, size_t expert_bytes, int64_t n_expert, dpct::queue_ptr stream) { GGML_ASSERT(expert_bytes % sizeof(block_q5_K) == 0); - const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q5_K)); - const size_t total_bytes = expert_bytes * (size_t) n_expert; + const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q5_K)); + const size_t max_chunk_bytes = 32u << 20; + const int64_t chunk_experts = std::max(1, std::min(n_expert, (int64_t) (max_chunk_bytes / expert_bytes))); - sycl_reorder_temp_buffer tmp(stream, total_bytes); + sycl_reorder_temp_buffer tmp(stream, (size_t) chunk_experts * expert_bytes); if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, total_bytes); + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, + (size_t) chunk_experts * expert_bytes); return false; } uint8_t * tmp_buf = static_cast(tmp.ptr); - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, total_bytes))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - const int total_blocks = blocks_per_expert * (int) n_expert; - auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { - const int gb = gb_; - const int e = gb / blocks_per_expert; - const int ib = gb % blocks_per_expert; - const block_q5_K * x = (const block_q5_K *) (tmp_buf + (size_t) e * expert_bytes); - uint8_t * base = data_device + (size_t) e * expert_bytes; - - auto * qs_ptr = base; - auto * qh_ptr = qs_ptr + (QK_K / 2) * blocks_per_expert; - auto * scales_ptr = qh_ptr + (QK_K / 8) * blocks_per_expert; - auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * blocks_per_expert); + for (int64_t e0 = 0; e0 < n_expert; e0 += chunk_experts) { + const int64_t n_chunk = std::min(chunk_experts, n_expert - e0); + uint8_t * chunk = data_device + (size_t) e0 * expert_bytes; - for (int j = 0; j < QK_K / 2; ++j) { - qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; - } - for (int j = 0; j < QK_K / 8; ++j) { - qh_ptr[ib * (QK_K / 8) + j] = x[ib].qh[j]; + sycl::event copy_event; + SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, chunk, (size_t) n_chunk * expert_bytes))); + if (!g_ggml_sycl_use_async_mem_op) { + copy_event.wait(); } - for (int j = 0; j < K_SCALE_SIZE; ++j) { - scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; + + const int total_blocks = blocks_per_expert * (int) n_chunk; + auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { + const int gb = gb_; + const int e = gb / blocks_per_expert; + const int ib = gb % blocks_per_expert; + const block_q5_K * x = (const block_q5_K *) (tmp_buf + (size_t) e * expert_bytes); + uint8_t * base = chunk + (size_t) e * expert_bytes; + + auto * qs_ptr = base; + auto * qh_ptr = qs_ptr + (QK_K / 2) * blocks_per_expert; + auto * scales_ptr = qh_ptr + (QK_K / 8) * blocks_per_expert; + auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * blocks_per_expert); + + for (int j = 0; j < QK_K / 2; ++j) { + qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; + } + for (int j = 0; j < QK_K / 8; ++j) { + qh_ptr[ib * (QK_K / 8) + j] = x[ib].qh[j]; + } + for (int j = 0; j < K_SCALE_SIZE; ++j) { + scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; + } + dm_ptr[ib] = x[ib].dm; + }); + if (!g_ggml_sycl_use_async_mem_op) { + reorder_event.wait_and_throw(); } - dm_ptr[ib] = x[ib].dm; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); } return true; } -// Reorder each Q6_K expert slice into [ql][qh][scales][d]. +// Reorder each Q6_K expert slice into [ql][qh][scales][d], a few experts at a time (see Q4_K above). static bool reorder_qw_q6_k_moe(uint8_t * data_device, size_t expert_bytes, int64_t n_expert, dpct::queue_ptr stream) { GGML_ASSERT(expert_bytes % sizeof(block_q6_K) == 0); - const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q6_K)); - const size_t total_bytes = expert_bytes * (size_t) n_expert; + const int blocks_per_expert = (int) (expert_bytes / sizeof(block_q6_K)); + const size_t max_chunk_bytes = 32u << 20; + const int64_t chunk_experts = std::max(1, std::min(n_expert, (int64_t) (max_chunk_bytes / expert_bytes))); - sycl_reorder_temp_buffer tmp(stream, total_bytes); + sycl_reorder_temp_buffer tmp(stream, (size_t) chunk_experts * expert_bytes); if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, total_bytes); + GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, + (size_t) chunk_experts * expert_bytes); return false; } uint8_t * tmp_buf = static_cast(tmp.ptr); - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, total_bytes))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } + for (int64_t e0 = 0; e0 < n_expert; e0 += chunk_experts) { + const int64_t n_chunk = std::min(chunk_experts, n_expert - e0); + uint8_t * chunk = data_device + (size_t) e0 * expert_bytes; - const int total_blocks = blocks_per_expert * (int) n_expert; - auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { - const int gb = gb_; - const int e = gb / blocks_per_expert; - const int ib = gb % blocks_per_expert; - const block_q6_K * x = (const block_q6_K *) (tmp_buf + (size_t) e * expert_bytes); - uint8_t * base = data_device + (size_t) e * expert_bytes; - - auto * ql_ptr = base; - auto * qh_ptr = ql_ptr + (QK_K / 2) * blocks_per_expert; - auto * scales_ptr = qh_ptr + (QK_K / 4) * blocks_per_expert; - auto * d_ptr = (sycl::half *) (scales_ptr + (QK_K / 16) * blocks_per_expert); - - for (int j = 0; j < QK_K / 2; ++j) { - ql_ptr[ib * (QK_K / 2) + j] = x[ib].ql[j]; - } - for (int j = 0; j < QK_K / 4; ++j) { - qh_ptr[ib * (QK_K / 4) + j] = x[ib].qh[j]; + sycl::event copy_event; + SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, chunk, (size_t) n_chunk * expert_bytes))); + if (!g_ggml_sycl_use_async_mem_op) { + copy_event.wait(); } - for (int j = 0; j < QK_K / 16; ++j) { - scales_ptr[ib * (QK_K / 16) + j] = x[ib].scales[j]; + + const int total_blocks = blocks_per_expert * (int) n_chunk; + auto reorder_event = stream->parallel_for(total_blocks, [=](auto gb_) { + const int gb = gb_; + const int e = gb / blocks_per_expert; + const int ib = gb % blocks_per_expert; + const block_q6_K * x = (const block_q6_K *) (tmp_buf + (size_t) e * expert_bytes); + uint8_t * base = chunk + (size_t) e * expert_bytes; + + auto * ql_ptr = base; + auto * qh_ptr = ql_ptr + (QK_K / 2) * blocks_per_expert; + auto * scales_ptr = qh_ptr + (QK_K / 4) * blocks_per_expert; + auto * d_ptr = (sycl::half *) (scales_ptr + (QK_K / 16) * blocks_per_expert); + + for (int j = 0; j < QK_K / 2; ++j) { + ql_ptr[ib * (QK_K / 2) + j] = x[ib].ql[j]; + } + for (int j = 0; j < QK_K / 4; ++j) { + qh_ptr[ib * (QK_K / 4) + j] = x[ib].qh[j]; + } + for (int j = 0; j < QK_K / 16; ++j) { + scales_ptr[ib * (QK_K / 16) + j] = x[ib].scales[j]; + } + d_ptr[ib] = x[ib].d; + }); + if (!g_ggml_sycl_use_async_mem_op) { + reorder_event.wait_and_throw(); } - d_ptr[ib] = x[ib].d; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); } return true; } @@ -4681,278 +4949,89 @@ static bool reorder_qw_mxfp4_moe(uint8_t * data_device, size_t expert_bytes, int } static bool reorder_qw_q2_k(uint8_t * data_device, size_t size, size_t offset, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_q2_K) == 0); - GGML_ASSERT(offset % sizeof(block_q2_K) == 0); - - const int nblocks = size / sizeof(block_q2_K); - - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * qs_ptr = data_device; - auto * scales_ptr = qs_ptr + (QK_K / 4) * nblocks; - sycl::half2 * dm_ptr = (sycl::half2 *) (scales_ptr + (QK_K / 16) * nblocks); - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_q2_K * x = (const block_q2_K *) tmp_buf; - const int ib = i; - - for (int j = 0; j < QK_K / 4; ++j) { - qs_ptr[ib * (QK_K / 4) + j] = x[ib].qs[j]; - } - - for (int j = 0; j < QK_K / 16; ++j) { - scales_ptr[ib * (QK_K / 16) + j] = x[ib].scales[j]; - } - - dm_ptr[ib] = x[ib].dm; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + GGML_ASSERT(offset == 0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q2_K, qs), QK_K / 4, + [](const block_q2_K & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * scales = tail; + for (int j = 0; j < QK_K / 16; ++j) { + scales[ib * (QK_K / 16) + j] = x.scales[j]; + } + ((sycl::half2 *) (scales + (QK_K / 16) * nblocks))[ib] = x.dm; + }, stream); } static bool reorder_qw_q3_k(uint8_t * data_device, size_t size, size_t offset, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_q3_K) == 0); - GGML_ASSERT(offset % sizeof(block_q3_K) == 0); - - const int nblocks = size / sizeof(block_q3_K); - - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * qs_ptr = data_device; - auto * hmask_ptr = qs_ptr + (QK_K / 4) * nblocks; - auto * scales_ptr = hmask_ptr + (QK_K / 8) * nblocks; - sycl::half * d_ptr = (sycl::half *) (scales_ptr + 12 * nblocks); - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_q3_K * x = (const block_q3_K *) tmp_buf; - const int ib = i; - - for (int j = 0; j < QK_K / 4; ++j) { - qs_ptr[ib * (QK_K / 4) + j] = x[ib].qs[j]; - } - - for (int j = 0; j < QK_K / 8; ++j) { - hmask_ptr[ib * (QK_K / 8) + j] = x[ib].hmask[j]; - } - - for (int j = 0; j < 12; ++j) { - scales_ptr[ib * 12 + j] = x[ib].scales[j]; - } - - d_ptr[ib] = x[ib].d; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + GGML_ASSERT(offset == 0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q3_K, qs), QK_K / 4, + [](const block_q3_K & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * hmask = tail; + uint8_t * scales = hmask + (QK_K / 8) * nblocks; + for (int j = 0; j < QK_K / 8; ++j) { + hmask[ib * (QK_K / 8) + j] = x.hmask[j]; + } + for (int j = 0; j < 12; ++j) { + scales[ib * 12 + j] = x.scales[j]; + } + ((sycl::half *) (scales + 12 * nblocks))[ib] = x.d; + }, stream); } static bool reorder_qw_q5_k(uint8_t * data_device, size_t size, size_t offset, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_q5_K) == 0); - GGML_ASSERT(offset % sizeof(block_q5_K) == 0); - - const int nblocks = size / sizeof(block_q5_K); - - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * qs_ptr = data_device; - auto * qh_ptr = qs_ptr + (QK_K / 2) * nblocks; - auto * scales_ptr = qh_ptr + (QK_K / 8) * nblocks; - auto * dm_ptr = (sycl::half2 *) (scales_ptr + K_SCALE_SIZE * nblocks); - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_q5_K * x = (const block_q5_K *) tmp_buf; - const int ib = i; - - for (int j = 0; j < QK_K / 2; ++j) { - qs_ptr[ib * (QK_K / 2) + j] = x[ib].qs[j]; - } - - for (int j = 0; j < QK_K / 8; ++j) { - qh_ptr[ib * (QK_K / 8) + j] = x[ib].qh[j]; - } - - for (int j = 0; j < K_SCALE_SIZE; ++j) { - scales_ptr[ib * K_SCALE_SIZE + j] = x[ib].scales[j]; - } - - dm_ptr[ib] = x[ib].dm; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + GGML_ASSERT(offset == 0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q5_K, qs), QK_K / 2, + [](const block_q5_K & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * qh = tail; + uint8_t * scales = qh + (QK_K / 8) * nblocks; + for (int j = 0; j < QK_K / 8; ++j) { + qh[ib * (QK_K / 8) + j] = x.qh[j]; + } + for (int j = 0; j < K_SCALE_SIZE; ++j) { + scales[ib * K_SCALE_SIZE + j] = x.scales[j]; + } + ((sycl::half2 *) (scales + K_SCALE_SIZE * nblocks))[ib] = x.dm; + }, stream); } static bool reorder_qw_q6_k(uint8_t * data_device, size_t size, size_t offset, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_q6_K) == 0); - GGML_ASSERT(offset % sizeof(block_q6_K) == 0); - - const int nblocks = size / sizeof(block_q6_K); - - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * ql_ptr = data_device; - auto * qh_ptr = ql_ptr + (QK_K / 2) * nblocks; - auto * scales_ptr = qh_ptr + (QK_K / 4) * nblocks; - sycl::half * dm_ptr = (sycl::half *) (scales_ptr + (QK_K / 16) * nblocks); - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_q6_K * x = (const block_q6_K *) tmp_buf; - const int ib = i; - - const uint8_t * ql = x[ib].ql; - const uint8_t * qh = x[ib].qh; - uint8_t * base_ql_ptr = ql_ptr + (QK_K / 2) * ib; - uint8_t * base_qh_ptr = qh_ptr + (QK_K / 4) * ib; - uint8_t * base_scales_ptr = scales_ptr + (QK_K / 16) * ib; - - for (int j = 0; j < QK_K / 2; ++j) { - base_ql_ptr[j] = ql[j]; - } - for (int j = 0; j < QK_K / 4; ++j) { - base_qh_ptr[j] = qh[j]; - } - - for (int j = 0; j < QK_K / 16; ++j) { - base_scales_ptr[j] = x[ib].scales[j]; - } - - dm_ptr[ib] = x[ib].d; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + GGML_ASSERT(offset == 0); + return reorder_qw_planar(__func__, data_device, size, offsetof(block_q6_K, ql), QK_K / 2, + [](const block_q6_K & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * qh = tail; + uint8_t * scales = qh + (QK_K / 4) * nblocks; + for (int j = 0; j < QK_K / 4; ++j) { + qh[ib * (QK_K / 4) + j] = x.qh[j]; + } + for (int j = 0; j < QK_K / 16; ++j) { + scales[ib * (QK_K / 16) + j] = x.scales[j]; + } + ((sycl::half *) (scales + (QK_K / 16) * nblocks))[ib] = x.d; + }, stream); } static bool reorder_qw_iq3_s(uint8_t * data_device, size_t size, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_iq3_s) == 0); - - const int nblocks = size / sizeof(block_iq3_s); - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * qs_ptr = data_device; - auto * qh_ptr = qs_ptr + (QK_K / 4) * nblocks; - auto * signs_ptr = qh_ptr + (QK_K / 32) * nblocks; - auto * metadata_ptr = signs_ptr + (QK_K / 8) * nblocks; - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_iq3_s * x = (const block_iq3_s *) tmp_buf; - const int ib = i; - - for (int j = 0; j < QK_K / 4; ++j) { - qs_ptr[ib * (QK_K / 4) + j] = x[ib].qs[j]; - } - for (int j = 0; j < QK_K / 32; ++j) { - qh_ptr[ib * (QK_K / 32) + j] = x[ib].qh[j]; - } - for (int j = 0; j < QK_K / 8; ++j) { - signs_ptr[ib * (QK_K / 8) + j] = x[ib].signs[j]; - } - - uint8_t * metadata = metadata_ptr + ib * (sizeof(ggml_half) + IQ3S_N_SCALE); - *reinterpret_cast(metadata) = x[ib].d; - for (int j = 0; j < IQ3S_N_SCALE; ++j) { - metadata[sizeof(ggml_half) + j] = x[ib].scales[j]; - } - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + return reorder_qw_planar(__func__, data_device, size, offsetof(block_iq3_s, qs), QK_K / 4, + [](const block_iq3_s & x, int64_t ib, uint8_t * tail, int64_t nblocks) { + uint8_t * qh = tail; + uint8_t * signs = qh + (QK_K / 32) * nblocks; + uint8_t * metadata = signs + (QK_K / 8) * nblocks + ib * (sizeof(ggml_half) + IQ3S_N_SCALE); + for (int j = 0; j < QK_K / 32; ++j) { + qh[ib * (QK_K / 32) + j] = x.qh[j]; + } + for (int j = 0; j < QK_K / 8; ++j) { + signs[ib * (QK_K / 8) + j] = x.signs[j]; + } + *reinterpret_cast(metadata) = x.d; + for (int j = 0; j < IQ3S_N_SCALE; ++j) { + metadata[sizeof(ggml_half) + j] = x.scales[j]; + } + }, stream); } static bool reorder_qw_iq3_xxs(uint8_t * data_device, size_t size, dpct::queue_ptr stream) { - GGML_ASSERT(size % sizeof(block_iq3_xxs) == 0); - - const int nblocks = size / sizeof(block_iq3_xxs); - sycl_reorder_temp_buffer tmp(stream, size); - if (!tmp) { - GGML_LOG_WARN("%s: failed to allocate %zu bytes for reorder temp buffer, skipping reorder\n", __func__, size); - return false; - } - uint8_t * tmp_buf = static_cast(tmp.ptr); - - sycl::event copy_event; - SYCL_CHECK(CHECK_TRY_ERROR(copy_event = stream->memcpy(tmp_buf, data_device, size))); - if (!g_ggml_sycl_use_async_mem_op) { - copy_event.wait(); - } - - auto * qs_ptr = data_device; - auto * d_ptr = reinterpret_cast(qs_ptr + (3 * QK_K / 8) * nblocks); - - auto reorder_event = stream->parallel_for(nblocks, [=](auto i) { - const block_iq3_xxs * x = (const block_iq3_xxs *) tmp_buf; - const int ib = i; - - for (int j = 0; j < 3 * QK_K / 8; ++j) { - qs_ptr[ib * (3 * QK_K / 8) + j] = x[ib].qs[j]; - } - d_ptr[ib] = x[ib].d; - }); - if (!g_ggml_sycl_use_async_mem_op) { - reorder_event.wait_and_throw(); - } - return true; + return reorder_qw_planar(__func__, data_device, size, offsetof(block_iq3_xxs, qs), 3 * QK_K / 8, + [](const block_iq3_xxs & x, int64_t ib, uint8_t * tail, int64_t) { + reinterpret_cast(tail)[ib] = x.d; + }, stream); } static bool reorder_qw(const ggml_tensor * src0, dpct::queue_ptr stream) { @@ -4966,6 +5045,8 @@ static bool reorder_qw(const ggml_tensor * src0, dpct::queue_ptr stream) { if (src0->ne[2] > 1) { GGML_ASSERT((size_t) size == (size_t) src0->ne[2] * src0->nb[2]); switch (src0->type) { + case GGML_TYPE_Q8_0: + return reorder_qw_q8_0_moe(data_device, src0->nb[2], src0->ne[2], stream); case GGML_TYPE_Q4_K: return reorder_qw_q4_k_moe(data_device, src0->nb[2], src0->ne[2], stream); case GGML_TYPE_Q5_K: @@ -5051,8 +5132,8 @@ static void opt_for_reorder_id(ggml_backend_sycl_context * ctx, const ggml_tenso if (!g_ggml_sycl_enable_optimize || !ctx->opt_feature.reorder) { return; } - if (src0->type != GGML_TYPE_Q4_K && src0->type != GGML_TYPE_Q5_K && src0->type != GGML_TYPE_Q6_K && - src0->type != GGML_TYPE_MXFP4) { + if (src0->type != GGML_TYPE_Q8_0 && src0->type != GGML_TYPE_Q4_K && + src0->type != GGML_TYPE_Q5_K && src0->type != GGML_TYPE_Q6_K && src0->type != GGML_TYPE_MXFP4) { return; } // The MXFP4 reorder kernels use 8-byte vector loads, so every expert slice must stay aligned. @@ -5079,9 +5160,38 @@ static bool can_use_dequantize_mul_mat_vec(const ggml_tensor * src0, const ggml_ src0->ne[0] % dmmv_x_required == 0 && src1->ne[1] == 1; } -static bool can_use_mul_mat_vec_q(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { +// reordered weights of the types in ggml_sycl_xmx_supports_type() take the XMX kernel for wider batches +static bool can_use_xmx_batch(int device, const ggml_tensor * src0, const ggml_tensor * src1) { +#ifdef GGML_SYCL_MMVQ_HAS_XMX + const auto * extra = static_cast(src0->extra); + return ggml_sycl_xmx_enabled(device) && ggml_sycl_xmx_supports_type(src0->type) && extra && + extra->optimized_feature.reorder && src1->ne[1] <= g_ggml_sycl_xmx_max_cols && src1->ne[2] == 1 && + src1->ne[3] == 1; +#else + GGML_UNUSED(device); + GGML_UNUSED(src0); + GGML_UNUSED(src1); + return false; +#endif // GGML_SYCL_MMVQ_HAS_XMX +} + +static bool can_use_mul_mat_vec_q(int device, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { return ggml_is_quantized(src0->type) && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 && - src1->ne[1] <= MMVQ_MAX_BATCH_SIZE; + (src1->ne[1] <= MMVQ_MAX_BATCH_SIZE || can_use_xmx_batch(device, src0, src1)); +} + +static bool can_use_mul_mat_q(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + // mmvq and mmq need the __dp4a instruction which is available for gen12+ + // Workaround in https://github.com/ggml-org/llama.cpp/commit/95f84d5ce8b449a9b16009434aca800df504a02e + if (!ggml_sycl_supports_mmq(src0->type) || src0->type == GGML_TYPE_IQ2_XXS) { + return false; + } +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) + if (src1->ne[1] > MMQ_MAX_BATCH_SIZE) { + return false; + } +#endif // GGML_SYCL_SUPPORT_XMX && !GGML_SYCL_FORCE_MMQ + return src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; } static void ggml_sycl_mul_mat(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { @@ -5121,23 +5231,17 @@ static void ggml_sycl_mul_mat(ggml_backend_sycl_context & ctx, const ggml_tensor // check data types and tensor shapes for custom matrix multiplication kernels: bool use_dequantize_mul_mat_vec = can_use_dequantize_mul_mat_vec(src0, src1, dst); + if (src1->ne[1] == 1 && ggml_sycl_xmx_min_cols(src0->type) == 1 && can_use_xmx_batch(ctx.device, src0, src1)) { + use_dequantize_mul_mat_vec = false; + } #ifdef GGML_SYCL_F16 // dmmv may convert src1 to f16 in this build [TAG_GGML_PREC] use_dequantize_mul_mat_vec = use_dequantize_mul_mat_vec && ggml_sycl_src1_f16_ok(dst); #endif - bool use_mul_mat_vec_q = can_use_mul_mat_vec_q(src0, src1, dst); - - bool use_mul_mat_q = ggml_sycl_supports_mmq(src0->type) - && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; + bool use_mul_mat_vec_q = can_use_mul_mat_vec_q(ctx.device, src0, src1, dst); - - // mmvq and mmq need the __dp4a instruction which is available for gen12+ - // Workaround in https://github.com/ggml-org/llama.cpp/commit/95f84d5ce8b449a9b16009434aca800df504a02e - use_mul_mat_q = use_mul_mat_q && (src0->type != GGML_TYPE_IQ2_XXS); -#ifdef SYCL_USE_XMX - use_mul_mat_q = use_mul_mat_q && (src1->ne[1] <= MMQ_MAX_BATCH_SIZE); -#endif // SYCL_USE_XMX + bool use_mul_mat_q = can_use_mul_mat_q(src0, src1, dst); // When reorder is enabled, both ESIMD, MMVQ and DMMV kernels may be used. For // best performance use ESIMD when supported, followed by MMVQ, and finally DMMV. @@ -5205,6 +5309,12 @@ static bool ggml_sycl_mul_mat_glu_mmvq_plain(ggml_backend_sycl_context & ctx, gg return false; } + // the plain kernel only covers q5_K / iq4_xs pairs: bail before quantizing the activation + const auto plain_type = [](ggml_type t) { return t == GGML_TYPE_Q5_K || t == GGML_TYPE_IQ4_XS; }; + if (!plain_type(wu->type) || !plain_type(wg->type)) { + return false; + } + // log the up mat-mul: glu's own srcs are the two intermediates the fusion never materialises scope_op_debug_print scope_dbg_print(__func__, up, /*num_src=*/2, " : fused with gate + GLU (plain layout)"); @@ -5226,11 +5336,74 @@ static bool ggml_sycl_mul_mat_glu_mmvq_plain(ggml_backend_sycl_context & ctx, gg (int) ne11, /*stride_col_y=*/src1_padded_cols / QK8_1, /*stride_col_dst=*/(int) glu->ne[0], stream); + GGML_UNUSED(gate); +} + +// Gate and up weights of one type on the XMX engines: one launch reads the activations once and applies the GLU. +// Both weights must already be in the reorder layout. Returns false if the kernel declined. +static bool ggml_sycl_mul_mat_glu_xmx(ggml_backend_sycl_context & ctx, + ggml_tensor * glu, + ggml_tensor * up, + const ggml_tensor * wu, + const ggml_tensor * wg, + const ggml_tensor * act) { + const int64_t ne00 = wu->ne[0]; + const int64_t ne11 = act->ne[1]; + + const queue_ptr stream = ctx.stream(); + const int src1_padded_cols = GGML_PAD((int) ne00, MATRIX_ROW_PADDING); + const int stride_y_bytes = src1_padded_cols * (int) sizeof(block_q8_1) / QK8_1; + + // log the up mat-mul: glu's own srcs are the two intermediates the fusion never materialises + scope_op_debug_print scope_dbg_print(__func__, up, /*num_src=*/2, " : fused with gate + GLU (XMX)"); + + ggml_sycl_pool_alloc src1_q8_alloc(ctx.pool(), (size_t) ne11 * stride_y_bytes); + char * src1_ddq = src1_q8_alloc.get(); + + quantize_row_q8_1_sycl((const float *) act->data, src1_ddq, (int) ne00, (int) ne11, + src1_padded_cols, stream); + + return ggml_sycl_mul_mat_vec_q_glu_xmx(ctx.device, wu->type, ggml_get_glu_op(glu), wu->data, wg->data, src1_ddq, + (float *) glu->data, (int) ne00, (int) wu->ne[1], (int) ne11, stride_y_bytes, + /*stride_col_dst=*/(int) glu->ne[0], stream); +} + +#ifdef GGML_SYCL_DMMV_HAS_ESIMD +// {mul_mat(gate), mul_mat(up), GLU} on the reorder layout via the ESIMD DMMV kernel, for +// same-type K-quant or Q8_0 pairs and a single activation column. It reads the F32 activation +// directly, so one launch replaces three and no q8_1 quantization is needed. +static bool ggml_sycl_mul_mat_glu_dmmv_esimd(ggml_backend_sycl_context & ctx, ggml_tensor * glu, + ggml_tensor * gate, ggml_tensor * up, const ggml_tensor * wu, + const ggml_tensor * wg, const ggml_tensor * act) { + // the kernel reads the activation while writing the output; glu may reuse the dead activation's memory + const char * act_begin = (const char *) act->data; + const char * glu_begin = (const char *) glu->data; + if (act_begin < glu_begin + ggml_nbytes(glu) && glu_begin < act_begin + ggml_nbytes(act)) { + return false; + } + + // install the reorder (SoA) layout the kernel needs, as the unfused DMMV path would + opt_for_reorder(&ctx, wu, act, up, mul_mat_algo::DMMV); + opt_for_reorder(&ctx, wg, act, gate, mul_mat_algo::DMMV); + + const auto * extra_u = static_cast(wu->extra); + const auto * extra_g = static_cast(wg->extra); + if (!extra_u || !extra_g || !extra_u->optimized_feature.reorder || !extra_g->optimized_feature.reorder) { + return false; + } + + // log the up mat-mul: glu's own srcs are the two intermediates the fusion never materialises + scope_op_debug_print scope_dbg_print(__func__, up, /*num_src=*/2, " : fused with gate + GLU (ESIMD)"); + + return ggml_sycl_dequantize_mul_mat_vec_glu_reorder_esimd(wu->type, ggml_get_glu_op(glu), wu->data, wg->data, + (const float *) act->data, (float *) glu->data, + (int) wu->ne[0], (int) wu->ne[1], ctx.stream()); } +#endif // Fused dense-FFN mat-vec for the {mul_mat(gate), mul_mat(up), GLU} subgraph at node_idx. // Returns false if it declined, in which case the caller runs the three nodes normally. -static bool ggml_sycl_mul_mat_glu_mmvq_fused(ggml_backend_sycl_context & ctx, ggml_cgraph * cgraph, int node_idx) { +static bool ggml_sycl_mul_mat_glu_fused(ggml_backend_sycl_context & ctx, ggml_cgraph * cgraph, int node_idx) { if (!ggml_sycl_can_fuse(cgraph, node_idx, { GGML_OP_MUL_MAT, GGML_OP_MUL_MAT, GGML_OP_GLU }, {})) { return false; } @@ -5248,16 +5421,48 @@ static bool ggml_sycl_mul_mat_glu_mmvq_fused(ggml_backend_sycl_context & ctx, gg return false; } +#ifdef GGML_SYCL_DMMV_HAS_ESIMD + // single-column same-type K-quant or Q8_0 pairs take the ESIMD kernel, as the unfused mul-mats + // would via DMMV; if the reorder layout could not be installed, fall through to mmvq + if (g_ggml_sycl_enable_esimd && wu->type == wg->type && act->ne[1] == 1 && + ggml_sycl_supports_reorder_esimd(wu->type) && + ggml_sycl_mul_mat_glu_dmmv_esimd(ctx, glu, gate, up, wu, wg, act)) { + return true; + } +#endif + // with DMMV prioritised the unfused path would not have gone through mmvq at all if (g_ggml_sycl_prioritize_dmmv) { return false; } + // gate and up of one type the XMX kernel handles, it needs the reorder layout like the unfused mmvq path + if (wg->type == wu->type && gate->src[1] == act && act->ne[1] >= ggml_sycl_xmx_min_cols(wu->type) && + act->ne[1] <= g_ggml_sycl_xmx_glu_max_cols) { + opt_for_reorder(&ctx, wu, act, up, mul_mat_algo::MMVQ); + opt_for_reorder(&ctx, wg, act, gate, mul_mat_algo::MMVQ); + if (can_use_xmx_batch(ctx.device, wu, act) && can_use_xmx_batch(ctx.device, wg, act) && + ggml_sycl_mul_mat_glu_xmx(ctx, glu, up, wu, wg, act)) { + return true; + } + } + + // the kernels below take up to MMVQ_MAX_BATCH_SIZE columns, a wider batch got here for the XMX kernel + if (act->ne[1] > MMVQ_MAX_BATCH_SIZE) { + return false; + } + // quant pairs the reorder kernel does not serve (mixed gate/up types, q5_K off BMG) take the // standard-layout fused path instead; same-type q4_K / q5_K keep the reorder path below const bool reorder_pair = wg->type == wu->type && (wu->type == GGML_TYPE_Q4_K || (wu->type == GGML_TYPE_Q5_K && ggml_sycl_q5_k_mmvq_reuse(ctx.device))); if (!reorder_pair) { + const auto is_plain_type = [](ggml_type type) { + return type == GGML_TYPE_Q5_K || type == GGML_TYPE_IQ4_XS; + }; + if (!is_plain_type(wu->type) || !is_plain_type(wg->type)) { + return false; + } return ggml_sycl_mul_mat_glu_mmvq_plain(ctx, glu, gate, up, wu, wg, act); } @@ -5416,29 +5621,63 @@ __dpct_inline__ static void k_copy_dst_from_contiguous( } } +__dpct_inline__ static void k_zero_dst_rows( + char *__restrict__ dst_original, + const mmid_row_mapping *__restrict__ row_mapping, int64_t ne0, size_t nb1, + size_t nb2, const sycl::nd_item<3> &item_ct1) { + int32_t i = item_ct1.get_group(2); + + const int32_t i1 = row_mapping[i].i1; + const int32_t i2 = row_mapping[i].i2; + + float * dst_row_original = (float *)(dst_original + i1*nb1 + i2*nb2); + + for (int j = item_ct1.get_local_id(2); j < ne0; + j += item_ct1.get_local_range(2)) { + dst_row_original[j] = 0.0f; + } +} + +// returns true when ggml_sycl_mul_mat_id takes the fallback path that requires stream synchronization +static bool ggml_sycl_mul_mat_id_needs_sync(const ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * ids = dst->src[2]; + + const int64_t ne10 = src1->ne[0]; + const int64_t ne11 = src1->ne[1]; + const int64_t ne12 = src1->ne[2]; + + if (ne12 != 1) return true; + if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) return true; + if (ne10 != src0->ne[0] || ne10 % QK8_1 != 0) return true; + if (!ggml_is_contiguous(src1)) return true; + + const int64_t n_ids_per_group = ids->ne[0]; + if (ids->ne[1] != 1) return true; + if (ne11 != 1 && ne11 != n_ids_per_group) return true; + + return !ggml_sycl_supports_mmvq_id(src0->type); +} + // Fused MoE TG fast path. Returns false to fall back to the per-expert loop below. static bool ggml_sycl_mul_mat_id_mmvq_fused( ggml_backend_sycl_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { + if (ggml_sycl_mul_mat_id_needs_sync(dst)) return false; + const int64_t ne10 = src1->ne[0]; const int64_t ne11 = src1->ne[1]; - const int64_t ne12 = src1->ne[2]; - if (ne12 != 1) return false; - if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) return false; - if (ne10 != src0->ne[0] || ne10 % QK8_1 != 0) return false; - if (!ggml_is_contiguous(src1)) return false; const int64_t n_ids_per_group = ids->ne[0]; - if (ids->ne[1] != 1) return false; - if (ne11 != 1 && ne11 != n_ids_per_group) return false; const queue_ptr stream = ctx.stream(); const int src1_padded_cols = GGML_PAD((int) ne10, MATRIX_ROW_PADDING); const int n_experts_used = (int) n_ids_per_group; const int nrows = (int) src0->ne[1]; - // Lazily reorder the (Q4_K) expert weights into a per-expert SoA layout, then run the reorder + // Lazily reorder supported expert weights into a per-expert SoA layout, then run the reorder // GEMV. Placed after the bail checks so a non-dispatchable op does not pay the reorder cost. opt_for_reorder_id(&ctx, src0); const ggml_tensor_extra_gpu * src0_extra = @@ -5484,14 +5723,18 @@ static void mmid_counting_sort_rows( int64_t n_ids, int64_t n_as, int64_t n_routed_rows, std::vector & expert_counts, std::vector & expert_row_offsets, - std::vector & routed_row_src) { + std::vector & routed_row_src, + std::vector & skipped_row_dst) { // frequencies: how many routed rows each expert "owns" expert_counts.assign(n_as, 0); for (int64_t iid1 = 0; iid1 < ids->ne[1]; iid1++) { for (int64_t id = 0; id < n_ids; id++) { const int32_t row_id_i = *(const int32_t *) (ids_host + iid1*ids->nb[1] + id*ids->nb[0]); - GGML_ASSERT(row_id_i >= 0 && row_id_i < n_as); + GGML_ASSERT(row_id_i == -1 || (row_id_i >= 0 && row_id_i < n_as)); + if (row_id_i == -1) { + continue; + } expert_counts[row_id_i]++; } } @@ -5504,10 +5747,17 @@ static void mmid_counting_sort_rows( std::vector expert_row_next = expert_row_offsets; routed_row_src.resize(n_routed_rows); + skipped_row_dst.clear(); for (int64_t iid1 = 0; iid1 < ids->ne[1]; iid1++) { for (int64_t id = 0; id < n_ids; id++) { const int32_t row_id_i = *(const int32_t *) (ids_host + iid1*ids->nb[1] + id*ids->nb[0]); - GGML_ASSERT(row_id_i >= 0 && row_id_i < n_as); + GGML_ASSERT(row_id_i == -1 || (row_id_i >= 0 && row_id_i < n_as)); + + // a skipped slot has no expert, its dst row is zeroed instead + if (row_id_i == -1) { + skipped_row_dst.push_back({(int32_t) id, (int32_t) iid1}); + continue; + } // find and validate the next free row for a given expert (row_id_i) const int64_t routed_row = expert_row_next[row_id_i]++; @@ -5516,6 +5766,7 @@ static void mmid_counting_sort_rows( routed_row_src[routed_row] = {(int32_t) id, (int32_t) iid1}; } } + routed_row_src.resize(expert_row_offsets[n_as]); } static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, @@ -5538,6 +5789,7 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, return; } } + GGML_ASSERT(ggml_sycl_mul_mat_id_needs_sync(dst)); // The per-expert loop below reads the experts in whatever layout they have: reorder MXFP4 here as well, so prompt processing does not depend on a single-token decode having run first. if (src0->type == GGML_TYPE_MXFP4) { @@ -5582,7 +5834,7 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, for (int64_t iid1 = 0; iid1 < ids->ne[1]; iid1++) { for (int64_t id = 0; id < n_ids; id++) { const int32_t i02 = *(const int32_t *) (ids_host.data() + iid1*ids->nb[1] + id*ids->nb[0]); - GGML_ASSERT(i02 >= 0 && i02 < n_as); + GGML_ASSERT(i02 == -1 || (i02 >= 0 && i02 < n_as)); const int64_t i11 = id % ne11; const int64_t i12 = iid1; @@ -5590,6 +5842,12 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, const int64_t i1 = id; const int64_t i2 = i12; + if (i02 == -1) { // skipped slot + SYCL_CHECK(CHECK_TRY_ERROR( + stream->memset(dst_original + i1*nb1 + i2*nb2, 0, ne0*sizeof(float)))); + continue; + } + src0_row.data = src0_original + i02*nb02; src1_row.data = src1_original + i11*nb11 + i12*nb12; dst_row.data = dst_original + i1*nb1 + i2*nb2; @@ -5611,20 +5869,43 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, std::vector expert_row_offsets; // the sources (slot/token pairs) of contiguous rows to guide k_copy_src1_to_contiguous std::vector & routed_row_src = ctx.mmid_row_mapping_host; + // the slot/token pairs of the skipped slots, whose dst rows are zeroed + std::vector skipped_row_dst; mmid_counting_sort_rows(ids, ids_host.data(), n_ids, n_as, n_routed_rows, - expert_row_counts, expert_row_offsets, routed_row_src); + expert_row_counts, expert_row_offsets, routed_row_src, skipped_row_dst); + + const int64_t n_valid_rows = (int64_t) routed_row_src.size(); ggml_sycl_pool_alloc dev_row_mapping(ctx.pool(), n_routed_rows); SYCL_CHECK(CHECK_TRY_ERROR( - stream->memcpy(dev_row_mapping.get(), routed_row_src.data(), n_routed_rows*sizeof(mmid_row_mapping)))); + stream->memcpy(dev_row_mapping.get(), routed_row_src.data(), n_valid_rows*sizeof(mmid_row_mapping)))); const unsigned int max_work_group_size = ggml_sycl_info().max_work_group_sizes[ctx.device]; assert(max_work_group_size % (WARP_SIZE * WARP_SIZE) == 0); - { + if (!skipped_row_dst.empty()) { + ggml_sycl_pool_alloc dev_skipped(ctx.pool(), skipped_row_dst.size()); + SYCL_CHECK(CHECK_TRY_ERROR( + stream->memcpy(dev_skipped.get(), skipped_row_dst.data(), skipped_row_dst.size()*sizeof(mmid_row_mapping)))); + + sycl::range<3> block_dims(1, 1, std::min((unsigned int)ne0, max_work_group_size)); + sycl::range<3> grid_dims(1, 1, skipped_row_dst.size()); + stream->submit([&](sycl::handler &cgh) { + mmid_row_mapping *__restrict dev_skipped_get = dev_skipped.get(); + + cgh.parallel_for( + sycl::nd_range<3>(grid_dims * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + k_zero_dst_rows(dst_original, dev_skipped_get, ne0, nb1, nb2, item_ct1); + }); + }); + SYCL_CHECK(CHECK_TRY_ERROR(stream->wait())); + } + + if (n_valid_rows > 0) { sycl::range<3> block_dims(1, 1, std::min((unsigned int)ne10, max_work_group_size)); - sycl::range<3> grid_dims(1, 1, n_routed_rows); + sycl::range<3> grid_dims(1, 1, n_valid_rows); stream->submit([&](sycl::handler &cgh) { char *__restrict src1_contiguous_get = src1_contiguous.get(); @@ -5690,9 +5971,9 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, ggml_sycl_mul_mat(ctx, &src0_row, &src1_row, &dst_row); } - { + if (n_valid_rows > 0) { sycl::range<3> block_dims(1, 1, std::min((unsigned int)ne0, max_work_group_size)); - sycl::range<3> grid_dims(1, 1, n_routed_rows); + sycl::range<3> grid_dims(1, 1, n_valid_rows); stream->submit([&](sycl::handler &cgh) { const char *__restrict dst_contiguous_get = dst_contiguous.get(); @@ -6197,7 +6478,7 @@ catch (sycl::exception const &exc) { std::exit(1); } -bool sycl_get_mem_info(int device, size_t * free, size_t * total) { +static bool sycl_get_mem_info(int device, size_t * free, size_t * total) { GGML_SYCL_DEBUG("[SYCL] [%s] g_ggml_sycl_get_mem_api=%d\n", __func__, g_ggml_sycl_get_mem_api); @@ -6409,8 +6690,6 @@ static int ggml_sycl_try_gdn_cache_fusion(const ggml_cgraph * cgraph, int node_i } static void ggml_backend_sycl_graph_compute_impl(ggml_backend_sycl_context * sycl_ctx, ggml_cgraph * cgraph) { - ggml_sycl_set_main_device(sycl_ctx->device); - for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; if (ggml_sycl_is_view_or_noop(node)) { @@ -6511,7 +6790,7 @@ static void ggml_backend_sycl_graph_compute_impl(ggml_backend_sycl_context * syc continue; } - if (node->op == GGML_OP_MUL_MAT && ggml_sycl_mul_mat_glu_mmvq_fused(*sycl_ctx, cgraph, i)) { + if (node->op == GGML_OP_MUL_MAT && ggml_sycl_mul_mat_glu_fused(*sycl_ctx, cgraph, i)) { i += 2; continue; } @@ -6525,42 +6804,167 @@ static void ggml_backend_sycl_graph_compute_impl(ggml_backend_sycl_context * syc } #ifdef GGML_SYCL_GRAPH -static bool check_graph_compatibility(ggml_cgraph * cgraph) { - if (ggml_sycl_info().device_count > 1) { +static const void * ggml_sycl_graph_get_key(ggml_cgraph * cgraph) { + return cgraph->nodes[0]; +} + +static bool ggml_sycl_graph_update_required(ggml_sycl_graph * graph, ggml_cgraph * cgraph) { + bool res = false; + + if (cgraph->uid != 0 && cgraph->uid == graph->uid) { + GGML_SYCL_DEBUG("[SYCL-GRAPH] graph id %" PRIu64 " reused\n", cgraph->uid); + GGML_ASSERT((int) graph->node_props.size() == cgraph->n_nodes); + return false; + } + + graph->uid = cgraph->uid; + + if ((int) graph->node_props.size() != cgraph->n_nodes) { + res = true; + graph->node_props.resize(cgraph->n_nodes); + } + + for (int i = 0; i < cgraph->n_nodes; i++) { + ggml_sycl_graph::node_properties prop = {}; + memcpy(&prop.node, cgraph->nodes[i], sizeof(ggml_tensor)); + + for (int j = 0; j < GGML_MAX_SRC; ++j) { + if (cgraph->nodes[i]->src[j]) { + prop.node_src_data_ptrs[j] = cgraph->nodes[i]->src[j]->data; + memcpy(prop.node_src_ne[j], cgraph->nodes[i]->src[j]->ne, sizeof(prop.node_src_ne[j])); + memcpy(prop.node_src_nb[j], cgraph->nodes[i]->src[j]->nb, sizeof(prop.node_src_nb[j])); + } + } + + if (res || memcmp(&graph->node_props[i], &prop, sizeof(prop)) != 0) { + graph->node_props[i] = prop; + res = true; + } + } + + return res; +} + +// Reports if ggml_sycl_mul_mat() gives this node to oneDNN. oneDNN chains the submission on events +// made before recording started, which SYCL graphs do not allow. +static bool mul_mat_uses_onednn(int device, ggml_tensor * dst) { +#if GGML_SYCL_DNNL + if (!g_ggml_sycl_enable_dnn) { + return false; + } + + ggml_tensor * src0 = dst->src[0]; + ggml_tensor * src1 = dst->src[1]; + + // the branch order below follows the dispatch in ggml_sycl_mul_mat(); the F16 branches end in + // a vector kernel or the batched oneMKL path, neither of which uses oneDNN + if (!ggml_backend_buffer_is_sycl_split(src0->buffer) && src0->type == GGML_TYPE_F16) { + if (ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) { + return false; + } + if (!ggml_is_contiguous(src0) && !ggml_is_transposed(src1) && src1->ne[1] == 1 && src1->ne[3] == 1) { + return false; + } + if (!ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2] * src1->ne[3] > 1) { + return false; + } + } + + // ggml_sycl_op_mul_mat_sycl() is the last resort of the dispatch and the only user of oneDNN. + // The reorder decision that ggml_sycl_mul_mat() makes between DMMV and MMVQ is left out here: + // neither uses a library. + if (can_use_dequantize_mul_mat_vec(src0, src1, dst) || can_use_mul_mat_vec_q(device, src0, src1, dst) || + can_use_mul_mat_q(src0, src1, dst)) { + return false; + } + + // the branch order below follows ggml_sycl_op_mul_mat_sycl(); graphs are single device only, so + // row_diff == src0->ne[1] and src1_ncols == src1->ne[1] there +#if defined(GGML_SYCL_HAS_BF16) + if (src0->type == GGML_TYPE_BF16 && ggml_is_contiguous(src0)) { + return true; + } +#endif +#ifdef GGML_SYCL_F16 + if ((src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && ggml_is_contiguous(src0) && + dst->op_params[0] == GGML_PREC_DEFAULT) { + return true; + } +#endif + // the F32 branch only uses oneDNN for large GEMMs and calls oneMKL directly otherwise + const int64_t gemm_flops = src0->ne[1] * src1->ne[1] * src0->ne[0]; + return gemm_flops >= SYCL_F32_DNNL_MIN_GEMM_FLOPS; +#else + GGML_UNUSED(device); + GGML_UNUSED(dst); + return false; +#endif +} + +static bool check_graph_compatibility(ggml_backend_sycl_context * ctx, ggml_cgraph * cgraph) { + if (ggml_sycl_info().active_device_count > 1) { // A sycl_ex::command_graph object can only be created for a single device - GGML_LOG_INFO("%s: disabling SYCL graphs due to multiple devices\n", __func__); + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to multiple devices\n", __func__); return false; } for (int i = 0; i < cgraph->n_nodes; i++) { - const ggml_op node_op = cgraph->nodes[i]->op; + ggml_tensor * node = cgraph->nodes[i]; + + // skip the nodes that ggml_backend_sycl_graph_compute_impl() does not run + if ((node->flags & GGML_TENSOR_FLAG_COMPUTE) == 0 || ggml_sycl_is_view_or_noop(node)) { + continue; + } + + const ggml_op node_op = node->op; + switch (node_op) { default: break; - case GGML_OP_CONCAT: - // ggml_sycl_op_concat() does a blocking host wait after memcpy operations, - // but wait() can't be called on the events returned by a queue recording - // to a graph. - [[fallthrough]]; case GGML_OP_MUL_MAT_ID: - // ggml_sycl_mul_mat_id() does a blocking host wait on the sycl queue after - // submitting a memcpy operation, but wait() can't be called on a queue that - // is recording to a graph. - GGML_LOG_INFO("%s: disabling SYCL graphs due to unsupported node type %s\n", __func__, - ggml_op_name(node_op)); - return false; + // The ggml_sycl_mul_mat_id() fallback path does a blocking host wait on the sycl + // queue after submitting a memcpy operation, but wait() can't be called on a queue + // that is recording to a graph. + if (ggml_sycl_mul_mat_id_needs_sync(node)) { + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to host wait in %s\n", __func__, + ggml_op_name(node_op)); + return false; + } + break; + case GGML_OP_FLASH_ATTN_EXT: + if (ggml_sycl_flash_attn_ext_needs_sync(ctx->device, node)) { + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to host wait in %s\n", __func__, + ggml_op_name(node_op)); + return false; + } +#ifndef GGML_SYCL_GRAPH_DNNL_SUPPORTED + if (ggml_sycl_flash_attn_ext_uses_onednn(ctx->device, node)) { + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to %s using oneDNN\n", __func__, + ggml_op_name(node_op)); + return false; + } +#endif + break; case GGML_OP_MUL_MAT: // We cannot use graphs with ggml_sycl_mul_mat() when SYCL async memory allocation extensions are not available, // as SYCL malloc / free and host wait calls are not supported when recording to a graph which are all present // in reordering. if (!g_ggml_sycl_use_async_mem_op) { - GGML_LOG_INFO( + GGML_LOG_DEBUG( "%s: disabling SYCL graphs due to unsupported node type when using a compiler without the " "oneAPI async memory allocation extension " "%s\n", __func__, ggml_op_name(node_op)); return false; } +#ifndef GGML_SYCL_GRAPH_DNNL_SUPPORTED + if (mul_mat_uses_onednn(ctx->device, node)) { + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to %s using oneDNN\n", __func__, + ggml_op_name(node_op)); + return false; + } +#endif + break; } } return true; @@ -6570,44 +6974,102 @@ static bool check_graph_compatibility(ggml_cgraph * cgraph) { static ggml_status ggml_backend_sycl_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { auto * sycl_ctx = static_cast(backend->context); + // set the device on every call: a graph replay does not go through + // ggml_backend_sycl_graph_compute_impl() + ggml_sycl_set_main_device(sycl_ctx->device); + #ifdef GGML_SYCL_GRAPH - bool use_sycl_graph = false; + bool use_sycl_graph = false; + ggml_sycl_graph * graph = nullptr; + if (g_ggml_sycl_enable_graph) { - use_sycl_graph = check_graph_compatibility(cgraph); + if (!ggml_sycl_info().devices[sycl_ctx->device].graph_support) { + // the device does not change, so report this once + if (sycl_ctx->graph_compatible != false) { + GGML_LOG_DEBUG("%s: disabling SYCL graphs due to unsupported graph feature on device\n", __func__); + GGML_LOG_INFO("%s: disabling SYCL graphs\n", __func__); + sycl_ctx->graph_compatible = false; + } + } else { + graph = sycl_ctx->sycl_graph(ggml_sycl_graph_get_key(cgraph)); + + // The nodes of a cgraph do not change while its uid does not, so the compatibility scan + // runs again only when the uid changes. A uid of 0 means it is not set. + if (cgraph->uid == 0 || cgraph->uid != graph->compatible_uid) { + graph->compatible_uid = cgraph->uid; + graph->compatible = check_graph_compatibility(sycl_ctx, cgraph); + + if (sycl_ctx->graph_compatible != graph->compatible) { + if (graph->compatible) { + GGML_LOG_INFO("%s: enabling SYCL graphs\n", __func__); + } else { + GGML_LOG_INFO("%s: disabling SYCL graphs\n", __func__); + } + sycl_ctx->graph_compatible = graph->compatible; + } + } + + use_sycl_graph = graph->compatible; + } } if (use_sycl_graph) { - const bool graph_support = dpct::get_device(sycl_ctx->device).has(sycl::aspect::ext_oneapi_limited_graph); - if (!graph_support) { - GGML_SYCL_DEBUG("[SYCL-GRAPH] can not use graphs on device:%d\n", sycl_ctx->device); - ggml_backend_sycl_graph_compute_impl(sycl_ctx, cgraph); - return GGML_STATUS_SUCCESS; + const bool properties_changed = ggml_sycl_graph_update_required(graph, cgraph); + bool replay_graph = false; + bool sycl_graph_update_required = false; + + if (!graph->warmup_complete) { + // Warmup: need at least 2 calls with no property change on the 2nd call. + if (!properties_changed) { + graph->warmup_complete = true; + replay_graph = true; + sycl_graph_update_required = true; + GGML_SYCL_DEBUG("[SYCL-GRAPH] warmup complete\n"); + } + } else { + // Post-warmup: replay graph while properties remain stable. + if (properties_changed) { + graph->warmup_complete = false; + GGML_SYCL_DEBUG("[SYCL-GRAPH] warmup reset\n"); + } else { + replay_graph = true; + sycl_graph_update_required = graph->exec_graph == nullptr; + } } - sycl_ex::command_graph model_sycl_graph(*(sycl_ctx->stream()), {sycl_ex::property::graph::assume_buffer_outlives_graph{}}); + if (replay_graph) { + if (sycl_graph_update_required) { + const bool graph_update_support = ggml_sycl_info().devices[sycl_ctx->device].graph_update_support; - model_sycl_graph.begin_recording(*(sycl_ctx->stream())); - ggml_backend_sycl_graph_compute_impl(sycl_ctx, cgraph); - model_sycl_graph.end_recording(); - - const bool graph_update_support = dpct::get_device(sycl_ctx->device).has(sycl::aspect::ext_oneapi_graph); - if (!sycl_ctx->exec_graph || !graph_update_support) { - auto exec_graph = graph_update_support ? model_sycl_graph.finalize(sycl_ex::property::graph::updatable{}) : - model_sycl_graph.finalize(); - sycl_ctx->exec_graph = std::make_unique< - sycl_ex::command_graph>(exec_graph); - } else { - try { - sycl_ctx->exec_graph->update(model_sycl_graph); - GGML_SYCL_DEBUG("[SYCL-GRAPH] update success\n"); - } catch (sycl::exception const & e) { - GGML_SYCL_DEBUG("[SYCL-GRAPH] Exception when updating graph, %s\n", e.what()); - auto exec_graph = model_sycl_graph.finalize({sycl_ex::property::graph::updatable{}}); - sycl_ctx->exec_graph = std::make_unique< - sycl_ex::command_graph>(exec_graph); + sycl_ex::command_graph model_sycl_graph(*(sycl_ctx->stream()), {sycl_ex::property::graph::assume_buffer_outlives_graph{}}); + + model_sycl_graph.begin_recording(*(sycl_ctx->stream())); + ggml_backend_sycl_graph_compute_impl(sycl_ctx, cgraph); + model_sycl_graph.end_recording(); + + if (!graph->exec_graph || !graph_update_support) { + auto exec_graph = graph_update_support ? model_sycl_graph.finalize(sycl_ex::property::graph::updatable{}) : + model_sycl_graph.finalize(); + graph->exec_graph = std::make_unique< + sycl_ex::command_graph>(exec_graph); + } else { + try { + graph->exec_graph->update(model_sycl_graph); + GGML_SYCL_DEBUG("[SYCL-GRAPH] update success\n"); + } catch (sycl::exception const & e) { + // the executable graph cannot be updated due to violated constraints, + // so finalize the recorded graph again + GGML_SYCL_DEBUG("[SYCL-GRAPH] Exception when updating graph, %s\n", e.what()); + auto exec_graph = model_sycl_graph.finalize({sycl_ex::property::graph::updatable{}}); + graph->exec_graph = std::make_unique< + sycl_ex::command_graph>(exec_graph); + } + } } - } - sycl_ctx->stream()->ext_oneapi_graph(*(sycl_ctx->exec_graph)); + sycl_ctx->stream()->ext_oneapi_graph(*(graph->exec_graph)); + } else { + ggml_backend_sycl_graph_compute_impl(sycl_ctx, cgraph); + } } else #endif { @@ -6776,6 +7238,11 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons return false; } case GGML_OP_CONV_2D: + // WHCN: contiguous [KW,KH,IC,OC] kernel and [W,H,C,N] input + // CWHN: channel-fastest input (C fastest) and kernel with OC fastest + return (ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) || + (op->src[1]->nb[2] == ggml_type_size(op->src[1]->type) && + op->src[0]->nb[3] == ggml_type_size(op->src[0]->type)); case GGML_OP_CONV_2D_DW: case GGML_OP_CONV_TRANSPOSE_2D: return true; @@ -6817,11 +7284,12 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: case GGML_GLU_OP_SWIGLU_CLAMP: - return ggml_is_contiguous_1(op->src[0]); + // the fused GLU kernels only have f32/f16 instantiations + return ggml_is_contiguous_1(op->src[0]) && + (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16); default: return false; } - break; case GGML_OP_MUL_MAT: case GGML_OP_MUL_MAT_ID: { @@ -6914,7 +7382,6 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); return res; } - break; case GGML_OP_DSV4_HC_PRE: return op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; @@ -7080,7 +7547,8 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons case GGML_OP_RMS_NORM_BACK: return ggml_is_contiguous(op->src[0]); case GGML_OP_SCALE: - return true; + // the scale kernel is f32 only, and reads src0 flat + return op->type == GGML_TYPE_F32 && op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); case GGML_OP_CONT: return true; case GGML_OP_TRI: @@ -7113,12 +7581,19 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons #endif ) && op->src[0]->type == op->type; - case GGML_OP_CONV_3D: + case GGML_OP_CONV_3D: { + const int32_t * opts = (const int32_t *) op->op_params; + // zero kernel volume, channels or output makes the im2col GEMM degenerate (k == 0 or m == 0) + // and MKL BLAS rejects it; let those fall back to the CPU backend + const int64_t knl_n_total = op->src[0]->ne[0] * op->src[0]->ne[1] * op->src[0]->ne[2] * opts[9]; + const int64_t patch_total = op->ne[0] * op->ne[1] * op->ne[2] * opts[10]; return op->type == GGML_TYPE_F32 && (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16) && op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]) && - ggml_is_contiguous(op->src[1]); + ggml_is_contiguous(op->src[1]) && + knl_n_total > 0 && patch_total > 0; + } case GGML_OP_SUM: case GGML_OP_SUM_ROWS: case GGML_OP_MEAN: @@ -7180,7 +7655,8 @@ static bool do_ggml_backend_sycl_device_supports_op(ggml_backend_dev_t dev, cons case GGML_OP_SOLVE_TRI: return op->src[0]->ne[0] <= SYCL_SOLVE_TRI_MAX_N && op->src[1]->ne[0] <= SYCL_SOLVE_TRI_MAX_K; case GGML_OP_FLASH_ATTN_EXT: - return ggml_sycl_flash_attn_ext_supported(device, op); + // K/V row lists (ggml_flash_attn_ext_rows) are not supported + return op->src[5] == nullptr && ggml_sycl_flash_attn_ext_supported(device, op); default: return false; } @@ -7356,9 +7832,15 @@ struct ggml_backend_sycl_comm_context { // pinned host staging per device context, reused across calls (queues are in-order) uint8_t * host_out[2] = { nullptr, nullptr }; - uint8_t * host_in[2] = { nullptr, nullptr }; + uint8_t * host_in[2] = { nullptr, nullptr }; // only used by the 4-buffer path (separate SYCL contexts) size_t host_bytes = 0; + // SYCL_ENABLE_DEFAULT_CONTEXTS=1 sets comm_exchange_fast on Linux - PR #30956 + using exchange_fn_t = void (*)(ggml_backend_sycl_comm_context * comm, queue_ptr q0, queue_ptr q1, + void * dst0, const void * src1, void * dst1, const void * src0, + size_t nbytes); + exchange_fn_t comm_exchange = nullptr; // Moves same context check out of hot path; tests only once + void free_host() { for (int i = 0; i < 2; ++i) { const sycl::context sctx = ((ggml_backend_sycl_context *) backends[i]->context)->stream()->get_context(); @@ -7369,6 +7851,41 @@ struct ggml_backend_sycl_comm_context { } }; +// dst0 <- src1 and dst1 <- src0 through pinned host memory. +static void ggml_sycl_comm_exchange_fast(ggml_backend_sycl_comm_context * comm, queue_ptr q0, queue_ptr q1, + void * dst0, const void * src1, void * dst1, const void * src0, + size_t nbytes) { + + // Increases Linux tensor split prompt eval speeds on par with layer split speeds + // Reallocate host buffers if they are too small + if (comm->host_bytes < nbytes) { + q0->wait(); + q1->wait(); + comm->free_host(); + comm->host_out[0] = sycl::malloc_host(nbytes, q0->get_context()); + comm->host_out[1] = sycl::malloc_host(nbytes, q1->get_context()); + + GGML_ASSERT(comm->host_out[0] && comm->host_out[1]); + comm->host_bytes = nbytes; + } + + // Step 1: Concurrently copy from GPUs into host buffers (Asynchronous) + sycl::event e_d2h_0 = q0->memcpy(comm->host_out[0], src0, nbytes); + sycl::event e_d2h_1 = q1->memcpy(comm->host_out[1], src1, nbytes); + + // Step 2: Asynchronous Barrier Interlocking (NO HOST BLOCKING), wait() causes MTP conflicts + q0->ext_oneapi_submit_barrier({e_d2h_1}); // q0 waits for q1's device-to-host copy + q1->ext_oneapi_submit_barrier({e_d2h_0}); // q1 waits for q0's device-to-host copy + + // Step 3: Cross-upload directly from the opposing host buffer. + sycl::event e_h2d_0 = q0->memcpy(dst0, comm->host_out[1], nbytes); // q0 pulls from host_out[1] + sycl::event e_h2d_1 = q1->memcpy(dst1, comm->host_out[0], nbytes); // q1 pulls from host_out[0] + + // Step 4: Finalize the exchange before returning to host code + e_h2d_0.wait(); + e_h2d_1.wait(); +} + // dst0 <- src1 and dst1 <- src0 through pinned host memory, with a single host wait static void ggml_sycl_comm_exchange(ggml_backend_sycl_comm_context * comm, queue_ptr q0, queue_ptr q1, void * dst0, const void * src1, void * dst1, const void * src0, @@ -7414,6 +7931,15 @@ void * ggml_backend_sycl_comm_init(ggml_backend_t * backends, size_t n_backends) auto * sctx1 = (ggml_backend_sycl_context *) backends[1]->context; ctx->buf0 = std::make_unique>(sctx0->pool()); ctx->buf1 = std::make_unique>(sctx1->pool()); + +#if defined(_WIN32) || defined(_WIN64) // Not supported on Windows + ctx->comm_exchange = ggml_sycl_comm_exchange; +#else + // SYCL_ENABLE_DEFAULT_CONTEXTS=1 sets comm_exchange_fast on Linux - PR #30956 + ctx->comm_exchange = (sctx0->stream()->get_context() == sctx1->stream()->get_context()) + ? ggml_sycl_comm_exchange_fast + : ggml_sycl_comm_exchange; +#endif return ctx; } catch (const sycl::exception &) { return nullptr; } @@ -7497,7 +8023,7 @@ bool ggml_backend_sycl_comm_allreduce_tensor(void * comm_ctx_v, struct ggml_tens sycl::half * f16_tmp0 = (sycl::half *) buf0; sycl::half * f16_tmp1 = (sycl::half *) buf1; - ggml_sycl_comm_exchange(comm_ctx, q0, q1, f16_tmp0, tensors[1]->data, f16_tmp1, tensors[0]->data, nbytes); + comm_ctx->comm_exchange(comm_ctx, q0, q1, f16_tmp0, tensors[1]->data, f16_tmp1, tensors[0]->data, nbytes); q0->submit([&](sycl::handler & h) { h.parallel_for(sycl::range<1>(nelem), [=](sycl::id<1> i) { @@ -7527,7 +8053,7 @@ bool ggml_backend_sycl_comm_allreduce_tensor(void * comm_ctx_v, struct ggml_tens float * tmp1 = (float *) buf1; // separate SYCL contexts: a raw peer-USM q->memcpy is a silent no-op, so stage through host memory - ggml_sycl_comm_exchange(comm_ctx, q0, q1, tmp0, tensors[1]->data, tmp1, tensors[0]->data, nbytes); + comm_ctx->comm_exchange(comm_ctx, q0, q1, tmp0, tensors[1]->data, tmp1, tensors[0]->data, nbytes); q0->submit([&](sycl::handler & h) { h.parallel_for(sycl::range<1>(nelem), [=](sycl::id<1> i) { @@ -7561,7 +8087,7 @@ bool ggml_backend_sycl_comm_allreduce_tensor(void * comm_ctx_v, struct ggml_tens // Phase B: exchange the compressed bytes (in-order queues keep this after the compress kernels). const size_t bf16_bytes = nelem * sizeof(uint16_t); - ggml_sycl_comm_exchange(comm_ctx, q0, q1, inbox0, outbox1, inbox1, outbox0, bf16_bytes); + comm_ctx->comm_exchange(comm_ctx, q0, q1, inbox0, outbox1, inbox1, outbox0, bf16_bytes); // Phase C: decompress + add into local FP32 partial. q0->submit([&](sycl::handler & h) { @@ -7664,8 +8190,19 @@ ggml_backend_reg_t ggml_backend_sycl_reg() { return ® } +static void set_device_active(int device) { + ggml_sycl_device_info & info = ggml_sycl_info(); + info.devices[device].active = true; + int cnt = 0; + for (int i = 0; i < info.device_count; i++) { + if (info.devices[i].active) + cnt++; + } + info.active_device_count = cnt; +} + ggml_backend_t ggml_backend_sycl_init(int device) { - GGML_SYCL_DEBUG("[SYCL] call ggml_backend_sycl_init\n"); + GGML_SYCL_DEBUG("[SYCL] call ggml_backend_sycl_init. device=%d\n", device); ggml_check_sycl(); check_allow_gpu_index(device); @@ -7676,6 +8213,7 @@ ggml_backend_t ggml_backend_sycl_init(int device) { return nullptr; }; + set_device_active(device); ggml_backend_t sycl_backend = new ggml_backend { /* .guid = */ ggml_backend_sycl_guid(), /* .iface = */ ggml_backend_sycl_interface, diff --git a/ggml/src/ggml-sycl/gla.cpp b/ggml/src/ggml-sycl/gla.cpp index 879184fdd311..379483427046 100644 --- a/ggml/src/ggml-sycl/gla.cpp +++ b/ggml/src/ggml-sycl/gla.cpp @@ -1,6 +1,7 @@ #include #include "common.hpp" +#include "gla.hpp" template static void gated_linear_attn_f32_kernel(const dpct::queue_ptr stream, u_int B, u_int T, u_int C, u_int H, float scale, diff --git a/ggml/src/ggml-sycl/mem.cpp b/ggml/src/ggml-sycl/mem.cpp index ad5bfe0ff1eb..8a1c3262cc11 100644 --- a/ggml/src/ggml-sycl/mem.cpp +++ b/ggml/src/ggml-sycl/mem.cpp @@ -27,7 +27,7 @@ const char * mem_api_int2str(int mem_api) { /* * Depend on to call zesInit(0) before any other Level Zero API calls, otherwise the Level Zero API calls may fail. */ -bool query_free_memory_by_ze(sycl::device dev, size_t & free_bytes, size_t & total_bytes) { +static bool query_free_memory_by_ze(sycl::device dev, size_t & free_bytes, size_t & total_bytes) { GGML_SYCL_DEBUG("[SYCL] call %s: Querying free memory using Level Zero API.\n", __func__); free_bytes = 0; @@ -94,7 +94,7 @@ bool query_free_memory_by_ze(sycl::device dev, size_t & free_bytes, size_t & tot } #endif -bool get_memory_size_by_sycl_api(sycl::device dev, size_t & free_bytes, size_t & total_bytes) { +static bool get_memory_size_by_sycl_api(sycl::device dev, size_t & free_bytes, size_t & total_bytes) { GGML_SYCL_DEBUG("[SYCL] call %s: Querying free memory using SYCL API.\n", __func__); total_bytes = dev.get_info(); diff --git a/ggml/src/ggml-sycl/mmq.cpp b/ggml/src/ggml-sycl/mmq.cpp index ffb272aa2837..68162a8bf7a0 100644 --- a/ggml/src/ggml-sycl/mmq.cpp +++ b/ggml/src/ggml-sycl/mmq.cpp @@ -1340,7 +1340,7 @@ mul_mat_q(const void *__restrict__ vx, const void *__restrict__ vy, #define MMQ_X_Q4_0_RDNA1 64 #define MMQ_Y_Q4_0_RDNA1 64 #define NWARPS_Q4_0_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q4_0_AMPERE 4 #define MMQ_Y_Q4_0_AMPERE 32 #define NWARPS_Q4_0_AMPERE 4 @@ -1384,7 +1384,7 @@ template static void #define MMQ_X_Q4_1_RDNA1 64 #define MMQ_Y_Q4_1_RDNA1 64 #define NWARPS_Q4_1_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q4_1_AMPERE 4 #define MMQ_Y_Q4_1_AMPERE 32 #define NWARPS_Q4_1_AMPERE 4 @@ -1427,7 +1427,7 @@ template static void #define MMQ_X_Q5_0_RDNA1 64 #define MMQ_Y_Q5_0_RDNA1 64 #define NWARPS_Q5_0_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q5_0_AMPERE 4 #define MMQ_Y_Q5_0_AMPERE 32 #define NWARPS_Q5_0_AMPERE 4 @@ -1470,7 +1470,7 @@ template static void #define MMQ_X_Q5_1_RDNA1 64 #define MMQ_Y_Q5_1_RDNA1 64 #define NWARPS_Q5_1_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q5_1_AMPERE 4 #define MMQ_Y_Q5_1_AMPERE 32 #define NWARPS_Q5_1_AMPERE 4 @@ -1513,7 +1513,7 @@ mul_mat_q5_1( #define MMQ_X_Q8_0_RDNA1 64 #define MMQ_Y_Q8_0_RDNA1 64 #define NWARPS_Q8_0_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q8_0_AMPERE 4 #define MMQ_Y_Q8_0_AMPERE 32 #define NWARPS_Q8_0_AMPERE 4 @@ -1556,7 +1556,7 @@ template static void #define MMQ_X_Q2_K_RDNA1 128 #define MMQ_Y_Q2_K_RDNA1 32 #define NWARPS_Q2_K_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q2_K_AMPERE 4 #define MMQ_Y_Q2_K_AMPERE 32 #define NWARPS_Q2_K_AMPERE 4 @@ -1600,7 +1600,7 @@ mul_mat_q2_K( #define MMQ_X_Q3_K_RDNA1 32 #define MMQ_Y_Q3_K_RDNA1 128 #define NWARPS_Q3_K_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q3_K_AMPERE 4 #define MMQ_Y_Q3_K_AMPERE 32 #define NWARPS_Q3_K_AMPERE 4 @@ -1645,7 +1645,7 @@ mul_mat_q3_K( #define MMQ_X_Q4_K_RDNA1 32 #define MMQ_Y_Q4_K_RDNA1 64 #define NWARPS_Q4_K_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q4_K_AMPERE 4 #define MMQ_Y_Q4_K_AMPERE 32 #define NWARPS_Q4_K_AMPERE 4 @@ -1689,7 +1689,7 @@ template static void #define MMQ_X_Q5_K_RDNA1 32 #define MMQ_Y_Q5_K_RDNA1 64 #define NWARPS_Q5_K_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q5_K_AMPERE 4 #define MMQ_Y_Q5_K_AMPERE 32 #define NWARPS_Q5_K_AMPERE 4 @@ -1733,7 +1733,7 @@ mul_mat_q5_K( #define MMQ_X_Q6_K_RDNA1 32 #define MMQ_Y_Q6_K_RDNA1 64 #define NWARPS_Q6_K_RDNA1 8 -#if defined(SYCL_USE_XMX) +#if defined(GGML_SYCL_SUPPORT_XMX) && !defined(GGML_SYCL_FORCE_MMQ) #define MMQ_X_Q6_K_AMPERE 4 #define MMQ_Y_Q6_K_AMPERE 32 #define NWARPS_Q6_K_AMPERE 4 @@ -1807,76 +1807,44 @@ static void ggml_mul_mat_q4_0_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:20: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q4_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q4_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_0) + mmq_y / QI4_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q4_0_acc_ct1), - get_pointer(tile_x_d_q4_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_qs_q4_0_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_d_q4_0_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI4_0) + mmq_y / QI4_0), + cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q4_0( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_qs_q4_0_acc_ct1), + get_pointer(tile_x_d_q4_0_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:21: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q4_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q4_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_0) + mmq_y / QI4_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q4_0_acc_ct1), - get_pointer(tile_x_d_q4_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -1922,76 +1890,44 @@ static void ggml_mul_mat_q4_1_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:22: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q4_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + +mmq_y), cgh); - sycl::local_accessor tile_x_dm_q4_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_1) + mmq_y / QI4_1), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_1( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q4_1_acc_ct1), - get_pointer(tile_x_dm_q4_1_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_qs_q4_1_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + +mmq_y), cgh); + sycl::local_accessor tile_x_dm_q4_1_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI4_1) + mmq_y / QI4_1), + cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q4_1( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_qs_q4_1_acc_ct1), + get_pointer(tile_x_dm_q4_1_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:23: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q4_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + +mmq_y), cgh); - sycl::local_accessor tile_x_dm_q4_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_1) + mmq_y / QI4_1), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_1( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q4_1_acc_ct1), - get_pointer(tile_x_dm_q4_1_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2037,76 +1973,44 @@ static void ggml_mul_mat_q5_0_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:24: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_0_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q5_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_0) + mmq_y / QI5_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_0_acc_ct1), - get_pointer(tile_x_d_q5_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q5_0_acc_ct1( + sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_d_q5_0_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI5_0) + mmq_y / QI5_0), + cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q5_0( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q5_0_acc_ct1), + get_pointer(tile_x_d_q5_0_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:25: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_0_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q5_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_0) + mmq_y / QI5_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_0_acc_ct1), - get_pointer(tile_x_d_q5_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2152,76 +2056,44 @@ static void ggml_mul_mat_q5_1_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:26: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_1_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q5_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_1) + mmq_y / QI5_1), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_1( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_1_acc_ct1), - get_pointer(tile_x_dm_q5_1_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q5_1_acc_ct1( + sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_q5_1_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI5_1) + mmq_y / QI5_1), + cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q5_1( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q5_1_acc_ct1), + get_pointer(tile_x_dm_q5_1_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:27: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_1_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q5_1_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_1) + mmq_y / QI5_1), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_1( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_1_acc_ct1), - get_pointer(tile_x_dm_q5_1_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2267,76 +2139,44 @@ static void ggml_mul_mat_q8_0_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:28: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q8_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q8_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI8_0) + mmq_y / QI8_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q8_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q8_0_acc_ct1), - get_pointer(tile_x_d_q8_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_qs_q8_0_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_d_q8_0_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI8_0) + mmq_y / QI8_0), + cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q8_0( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_qs_q8_0_acc_ct1), + get_pointer(tile_x_d_q8_0_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:29: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_qs_q8_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_d_q8_0_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI8_0) + mmq_y / QI8_0), - cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q8_0( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_qs_q8_0_acc_ct1), - get_pointer(tile_x_d_q8_0_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2382,82 +2222,47 @@ static void ggml_mul_mat_q2_K_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:30: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI2_K) + mmq_y / QI2_K), - cgh); - sycl::local_accessor tile_x_sc_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q2_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q2_K_acc_ct1), - get_pointer(tile_x_dm_q2_K_acc_ct1), - get_pointer(tile_x_sc_q2_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q2_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_q2_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI2_K) + mmq_y / QI2_K), + cgh); + sycl::local_accessor tile_x_sc_q2_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q2_K( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q2_K_acc_ct1), + get_pointer(tile_x_dm_q2_K_acc_ct1), + get_pointer(tile_x_sc_q2_K_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:31: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI2_K) + mmq_y / QI2_K), - cgh); - sycl::local_accessor tile_x_sc_q2_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q2_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q2_K_acc_ct1), - get_pointer(tile_x_dm_q2_K_acc_ct1), - get_pointer(tile_x_sc_q2_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2505,88 +2310,50 @@ static void ggml_mul_mat_q3_K_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:32: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI3_K) + mmq_y / QI3_K), - cgh); - sycl::local_accessor tile_x_qh_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 2) + mmq_y / 2), cgh); - sycl::local_accessor tile_x_sc_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q3_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q3_K_acc_ct1), - get_pointer(tile_x_dm_q3_K_acc_ct1), - get_pointer(tile_x_qh_q3_K_acc_ct1), - get_pointer(tile_x_sc_q3_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q3_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_q3_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI3_K) + mmq_y / QI3_K), + cgh); + sycl::local_accessor tile_x_qh_q3_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 2) + mmq_y / 2), cgh); + sycl::local_accessor tile_x_sc_q3_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q3_K( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q3_K_acc_ct1), + get_pointer(tile_x_dm_q3_K_acc_ct1), + get_pointer(tile_x_qh_q3_K_acc_ct1), + get_pointer(tile_x_sc_q3_K_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:33: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI3_K) + mmq_y / QI3_K), - cgh); - sycl::local_accessor tile_x_qh_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 2) + mmq_y / 2), cgh); - sycl::local_accessor tile_x_sc_q3_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 4) + mmq_y / 4), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q3_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q3_K_acc_ct1), - get_pointer(tile_x_dm_q3_K_acc_ct1), - get_pointer(tile_x_qh_q3_K_acc_ct1), - get_pointer(tile_x_sc_q3_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } #endif } @@ -2633,82 +2400,47 @@ static void ggml_mul_mat_q4_K_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:34: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_K) + mmq_y / QI4_K), - cgh); - sycl::local_accessor tile_x_sc_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q4_K_acc_ct1), - get_pointer(tile_x_dm_q4_K_acc_ct1), - get_pointer(tile_x_sc_q4_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q4_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_q4_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI4_K) + mmq_y / QI4_K), + cgh); + sycl::local_accessor tile_x_sc_q4_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q4_K( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q4_K_acc_ct1), + get_pointer(tile_x_dm_q4_K_acc_ct1), + get_pointer(tile_x_sc_q4_K_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:35: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI4_K) + mmq_y / QI4_K), - cgh); - sycl::local_accessor tile_x_sc_q4_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q4_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q4_K_acc_ct1), - get_pointer(tile_x_dm_q4_K_acc_ct1), - get_pointer(tile_x_sc_q4_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2754,82 +2486,47 @@ static void ggml_mul_mat_q5_K_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:36: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_K) + mmq_y / QI5_K), - cgh); - sycl::local_accessor tile_x_sc_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_K_acc_ct1), - get_pointer(tile_x_dm_q5_K_acc_ct1), - get_pointer(tile_x_sc_q5_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_q5_K_acc_ct1( + sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_q5_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI5_K) + mmq_y / QI5_K), + cgh); + sycl::local_accessor tile_x_sc_q5_K_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q5_K( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_q5_K_acc_ct1), + get_pointer(tile_x_dm_q5_K_acc_ct1), + get_pointer(tile_x_sc_q5_K_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:37: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI5_K) + mmq_y / QI5_K), - cgh); - sycl::local_accessor tile_x_sc_q5_K_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q5_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_q5_K_acc_ct1), - get_pointer(tile_x_dm_q5_K_acc_ct1), - get_pointer(tile_x_sc_q5_K_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { @@ -2875,82 +2572,47 @@ static void ggml_mul_mat_q6_K_q8_1_sycl(const void *vx, const void *vy, const sycl::range<3> block_nums(1, block_num_y, block_num_x); const sycl::range<3> block_dims(1, nwarps, WARP_SIZE); - if (nrows_x % mmq_y == 0) { - const bool need_check = false; + const auto launch = [&](auto need_check) { /* DPCT1049:38: The work-group size passed to the SYCL kernel may exceed the limit. To get the device limit, query info::device::max_work_group_size. Adjust the work-group size if needed. */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI6_K) + mmq_y / QI6_K), - cgh); - sycl::local_accessor tile_x_sc_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q6_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_acc_ct1), - get_pointer(tile_x_dm_acc_ct1), - get_pointer(tile_x_sc_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + dpct::has_capability_or_fail(stream->get_device(), + {sycl::aspect::fp16}); + + stream->submit([&](sycl::handler &cgh) { + sycl::local_accessor tile_x_ql_acc_ct1( + sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); + sycl::local_accessor tile_x_dm_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / QI6_K) + mmq_y / QI6_K), + cgh); + sycl::local_accessor tile_x_sc_acc_ct1( + sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); + sycl::local_accessor tile_y_qs_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE), cgh); + sycl::local_accessor tile_y_ds_acc_ct1( + sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); + + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + mul_mat_q6_K( + vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, + nrows_dst, item_ct1, + get_pointer(tile_x_ql_acc_ct1), + get_pointer(tile_x_dm_acc_ct1), + get_pointer(tile_x_sc_acc_ct1), + get_pointer(tile_y_qs_acc_ct1), + get_pointer(tile_y_ds_acc_ct1)); + }); + }); + }; + + if (nrows_x % mmq_y == 0) { + launch(std::false_type{}); } else { - const bool need_check = true; - /* - DPCT1049:39: The work-group size passed to the SYCL kernel may exceed - the limit. To get the device limit, query - info::device::max_work_group_size. Adjust the work-group size if needed. - */ - { - dpct::has_capability_or_fail(stream->get_device(), - {sycl::aspect::fp16}); - - stream->submit([&](sycl::handler &cgh) { - sycl::local_accessor tile_x_ql_acc_ct1( - sycl::range<1>(mmq_y * (2 * WARP_SIZE) + mmq_y), cgh); - sycl::local_accessor tile_x_dm_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / QI6_K) + mmq_y / QI6_K), - cgh); - sycl::local_accessor tile_x_sc_acc_ct1( - sycl::range<1>(mmq_y * (WARP_SIZE / 8) + mmq_y / 8), cgh); - sycl::local_accessor tile_y_qs_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE), cgh); - sycl::local_accessor tile_y_ds_acc_ct1( - sycl::range<1>(mmq_x * WARP_SIZE / QI8_1), cgh); - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) { - mul_mat_q6_K( - vx, vy, dst, ncols_x, nrows_x, ncols_y, nrows_y, - nrows_dst, item_ct1, - get_pointer(tile_x_ql_acc_ct1), - get_pointer(tile_x_dm_acc_ct1), - get_pointer(tile_x_sc_acc_ct1), - get_pointer(tile_y_qs_acc_ct1), - get_pointer(tile_y_ds_acc_ct1)); - }); - }); - } + launch(std::true_type{}); } } catch (sycl::exception const &exc) { diff --git a/ggml/src/ggml-sycl/mmvq.cpp b/ggml/src/ggml-sycl/mmvq.cpp index eade8949fbb1..c3853814aa29 100644 --- a/ggml/src/ggml-sycl/mmvq.cpp +++ b/ggml/src/ggml-sycl/mmvq.cpp @@ -6,6 +6,10 @@ #include "quants.hpp" #include "vecdotq.hpp" +#ifdef GGML_SYCL_MMVQ_HAS_XMX +# include "esimd.hpp" +#endif // GGML_SYCL_MMVQ_HAS_XMX + // vec_dot_q_sycl_t adapters for the IQ vec_dots that take their codebook tables as extra // arguments: bind the constant tables here (as vec_dot_iq2_s_q8_1 / vec_dot_iq1_m_q8_1 already do // internally) so they can be used as template arguments of mul_mat_vec_q_moe. @@ -365,6 +369,45 @@ static void mul_mat_vec_q_ncols( } } +template +static void launch_mul_mat_vec_q(const void * vx, const void * vy, float * dst, + const int ncols, const int nrows, const int ncols_dst, + const int stride_col_y, const int stride_col_dst, + dpct::queue_ptr stream) { + GGML_ASSERT(ncols % assert_qk == 0); + const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; + const sycl::range<3> block_nums(1, 1, block_num_y); + const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); + + const auto launch = [&](auto ncols_tag) { + constexpr int N = decltype(ncols_tag)::value; + stream->submit([&](sycl::handler & cgh) { + cgh.parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + if constexpr (N == 1) { + mul_mat_vec_q( + vx, vy, dst, ncols, nrows, item_ct1); + } else { + mul_mat_vec_q_ncols( + vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); + } + }); + }); + }; + + switch (ncols_dst) { + case 1: launch(std::integral_constant{}); break; + case 2: launch(std::integral_constant{}); break; + case 3: launch(std::integral_constant{}); break; + case 4: launch(std::integral_constant{}); break; + case 5: launch(std::integral_constant{}); break; + case 6: launch(std::integral_constant{}); break; + case 7: launch(std::integral_constant{}); break; + case 8: launch(std::integral_constant{}); break; + default: GGML_ABORT("unsupported ncols_dst=%d", ncols_dst); + } +} + template static void mul_mat_vec_q_iq2_xxs_q8_1(const void *__restrict__ vx, const void *__restrict__ vy, @@ -864,364 +907,136 @@ static void reorder_mul_mat_vec_q4_0_q8_1_sycl_switch_ncols( static void mul_mat_vec_q4_0_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK4_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - { - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q4_0_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK4_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q4_0_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q4_0_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q4_0_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q4_0_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q4_0_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q4_0_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q4_0_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q4_0_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q4_0_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q4_0 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q4_0 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q4_1_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK4_1 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q4_1_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK4_1 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q4_1_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q4_1_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q4_1_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q4_1_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q4_1_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q4_1_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q4_1_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q4_1_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q4_1_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q4_1 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q4_1 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_mxfp4_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_MXFP4 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - { - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_mxfp4_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_MXFP4 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_mxfp4_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_mxfp4_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_mxfp4_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_mxfp4_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_mxfp4_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_mxfp4_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_mxfp4_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_mxfp4_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_mxfp4_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for MXFP4 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for MXFP4 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_nvfp4_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_NVFP4 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - { - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_nvfp4_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_NVFP4 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_nvfp4_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_nvfp4_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_nvfp4_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_nvfp4_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_nvfp4_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_nvfp4_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_nvfp4_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_nvfp4_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_nvfp4_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for NVFP4 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for NVFP4 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q5_0_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK5_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q5_0_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK5_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q5_0_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q5_0_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q5_0_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q5_0_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q5_0_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q5_0_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q5_0_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q5_0_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q5_0_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q5_0 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q5_0 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q5_1_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK5_1 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q5_1_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK5_1 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q5_1_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q5_1_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q5_1_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q5_1_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q5_1_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q5_1_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q5_1_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q5_1_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q5_1_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q5_1 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q5_1 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void reorder_mul_mat_vec_q8_0_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK8_0 == 0); @@ -1353,248 +1168,98 @@ static void mul_mat_vec_q8_0_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK8_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q8_0_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK8_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q8_0_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q8_0_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q8_0_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q8_0_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q8_0_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q8_0_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q8_0_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q8_0_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q8_0_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q8_0 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q8_0 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q1_0_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK1_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q1_0_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK1_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q1_0_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q1_0_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q1_0_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q1_0_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q1_0_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q1_0_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q1_0_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q1_0_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q1_0_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q1_0 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q1_0 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q2_0_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK2_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q2_0_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK2_0 == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q2_0_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q2_0_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q2_0_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q2_0_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q2_0_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q2_0_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q2_0_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q2_0_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q2_0_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q2_0 multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q2_0 multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q2_K_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q2_K_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q2_K_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q2_K_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q2_K_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q2_K_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q2_K_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q2_K_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q2_K_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q2_K_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q2_K_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q2_K multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q2_K multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void reorder_mul_mat_vec_q2_k_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); @@ -1658,26 +1323,12 @@ static void mul_mat_vec_q3_K_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } + static void reorder_mul_mat_vec_q3_k_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); @@ -1737,95 +1388,30 @@ static void reorder_mul_mat_vec_q3_k_q8_1_sycl_switch_ncols( } } -template -static void mul_mat_vec_q3_K_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, item_ct1); - }); - }); -} - static void mul_mat_vec_q3_K_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, const int ncols, const int nrows, const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q3_K_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q3_K_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q3_K_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q3_K_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q3_K_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q3_K_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q3_K_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q3_K_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q3_K multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q3_K multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_q4_K_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q4_K_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, - stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q4_K_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, @@ -1833,19 +1419,15 @@ static void mul_mat_vec_q4_K_q8_1_sycl_switch_ncols( const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q4_K_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q4_K_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q4_K_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q4_K_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q4_K_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q4_K_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q4_K_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q4_K_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q4_K multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q4_K multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void reorder_mul_mat_vec_q4_k_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); @@ -1927,51 +1509,11 @@ static void mul_mat_vec_q5_K_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q5_K_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, - stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q5_K_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, @@ -1979,19 +1521,15 @@ static void mul_mat_vec_q5_K_q8_1_sycl_switch_ncols( const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q5_K_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q5_K_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q5_K_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q5_K_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q5_K_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q5_K_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q5_K_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q5_K_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q5_K multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q5_K multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void reorder_mul_mat_vec_q5_k_q8_1_sycl(const void * vx, const void * vy, float * dst, const int ncols, const int nrows, dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); @@ -2129,51 +1667,11 @@ static void mul_mat_vec_q6_K_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - { - - stream->submit([&](sycl::handler &cgh) { - - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q( - vx, vy, dst, ncols, nrows, item_ct1); - }); - }); - } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, 1, 0, 0, stream); } -template -static void mul_mat_vec_q6_K_q8_1_sycl_ncols( - const void * vx, const void * vy, float * dst, - const int ncols, const int nrows, - const int stride_col_y, const int stride_col_dst, - dpct::queue_ptr stream) { - GGML_ASSERT(ncols % QK_K == 0); - const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y; - const sycl::range<3> block_nums(1, 1, block_num_y); - const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE); - - stream->submit([&](sycl::handler & cgh) { - cgh.parallel_for( - sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) - [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - mul_mat_vec_q_ncols( - vx, vy, dst, ncols, nrows, - stride_col_y, stride_col_dst, item_ct1); - }); - }); -} static void mul_mat_vec_q6_K_q8_1_sycl_switch_ncols( const void * vx, const void * vy, float * dst, @@ -2181,20 +1679,16 @@ static void mul_mat_vec_q6_K_q8_1_sycl_switch_ncols( const int ncols_dst, const int stride_col_y, const int stride_col_dst, dpct::queue_ptr stream) { - switch (ncols_dst) { - case 1: mul_mat_vec_q6_K_q8_1_sycl(vx, vy, dst, ncols, nrows, stream); break; - case 2: mul_mat_vec_q6_K_q8_1_sycl_ncols<2>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 3: mul_mat_vec_q6_K_q8_1_sycl_ncols<3>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 4: mul_mat_vec_q6_K_q8_1_sycl_ncols<4>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 5: mul_mat_vec_q6_K_q8_1_sycl_ncols<5>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 6: mul_mat_vec_q6_K_q8_1_sycl_ncols<6>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 7: mul_mat_vec_q6_K_q8_1_sycl_ncols<7>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - case 8: mul_mat_vec_q6_K_q8_1_sycl_ncols<8>(vx, vy, dst, ncols, nrows, stride_col_y, stride_col_dst, stream); break; - default: GGML_ABORT("unsupported ncols_dst=%d for Q6_K multi-col MMVQ", ncols_dst); + if (ncols_dst < 1 || ncols_dst > 8) { + GGML_ABORT("unsupported ncols_dst=%d for Q6_K multi-col MMVQ", ncols_dst); } + launch_mul_mat_vec_q( + vx, vy, dst, ncols, nrows, ncols_dst, stride_col_y, stride_col_dst, stream); } + static void mul_mat_vec_iq2_xxs_q8_1_sycl(const void *vx, const void *vy, float *dst, const int ncols, const int nrows, @@ -2557,6 +2051,158 @@ static void mul_mat_vec_iq4_xs_q8_1_sycl_switch_ncols( } } +#ifdef GGML_SYCL_MMVQ_HAS_XMX +// vgate is the gate weight of the fused gate and up kernel, nullptr for a plain mat-vec +template